| Submitter | Yinghai Lu |
|---|---|
| Date | 2009-11-07 05:43:12 |
| Message ID | <4AF508F0.9060105@kernel.org> |
| Download | mbox | patch |
| Permalink | /patch/58293/ |
| State | New |
| Headers | show |
Comments
Can I ask which is the latest version? I think -v10 is the latest. But I could not find -v10 for patch 1/2. Thanks, Kenji Kaneshige Yinghai Lu wrote: > move out bus_size_bridges and assign resources out of pciehp_add_bridge() > and at last do them all together one time including slot bridge, to avoid to > call assign resources several times, when there are several bridges under the > slot bridge. > > need to introduce pci_bridge_assign_resources there. > > handle the case the slot bridge that doesn't get pre-allocated big enough res > from FW. > for example pcie devices need 256M, but the bridge only get preallocated 2M... > > pci_setup_bridge() will take extra check_enabled for the slot bridge, otherwise > update res is not updated to bridge BAR. that is bridge is enabled already for > port service. > > v2: address Alex's concern about pci remove/rescan feature about > pci_setup_bridge changes. > v3: Kenji pointed out that pci_config_slot need to be called before > pci_bus_add_devices() > v4: move out pci_is_enabled checkout of pci_setup_bridge() > v5: change the applying sequence. > v6: change the functions name according to Jesse > v8: address Eric's concern, only overwrite leaf bridge resource that is not > big enough > v9: refresh to be applied after bjorn's patch, and remove trick about save > size and restore resource second try. > v10: alex found need to have export for pci_assign_unassigned_bridge_resources > > Signed-off-by: Yinghai Lu <yinghai@kernel.org> > > --- > drivers/pci/hotplug/pciehp_pci.c | 23 +++++- > drivers/pci/setup-bus.c | 130 +++++++++++++++++++++++++++++++++++++-- > include/linux/pci.h | 1 > 3 files changed, 144 insertions(+), 10 deletions(-) > > Index: linux-2.6/drivers/pci/hotplug/pciehp_pci.c > =================================================================== > --- linux-2.6.orig/drivers/pci/hotplug/pciehp_pci.c > +++ linux-2.6/drivers/pci/hotplug/pciehp_pci.c > @@ -53,17 +53,15 @@ static int __ref pciehp_add_bridge(struc > busnr = pci_scan_bridge(parent, dev, busnr, pass); > if (!dev->subordinate) > return -1; > - pci_bus_size_bridges(dev->subordinate); > - pci_bus_assign_resources(parent); > - pci_enable_bridges(parent); > - pci_bus_add_devices(parent); > + > return 0; > } > > int pciehp_configure_device(struct slot *p_slot) > { > struct pci_dev *dev; > - struct pci_bus *parent = p_slot->ctrl->pcie->port->subordinate; > + struct pci_dev *bridge = p_slot->ctrl->pcie->port; > + struct pci_bus *parent = bridge->subordinate; > int num, fn; > struct controller *ctrl = p_slot->ctrl; > > @@ -96,12 +94,25 @@ int pciehp_configure_device(struct slot > (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { > pciehp_add_bridge(dev); > } > + pci_dev_put(dev); > + } > + > + pci_assign_unassigned_bridge_resources(bridge); > + > + for (fn = 0; fn < 8; fn++) { > + dev = pci_get_slot(parent, PCI_DEVFN(0, fn)); > + if (!dev) > + continue; > + if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) { > + pci_dev_put(dev); > + continue; > + } > pci_configure_slot(dev); > pci_dev_put(dev); > } > > - pci_bus_assign_resources(parent); > pci_bus_add_devices(parent); > + > return 0; > } > > Index: linux-2.6/drivers/pci/setup-bus.c > =================================================================== > --- linux-2.6.orig/drivers/pci/setup-bus.c > +++ linux-2.6/drivers/pci/setup-bus.c > @@ -68,6 +68,52 @@ static void free_failed_list(struct reso > head->next = NULL; > } > > +static void pdev_assign_resources_sorted(struct pci_dev *dev, > + struct resource_list *fail_head) > +{ > + struct resource *res; > + struct resource_list head, *list, *tmp; > + int idx; > + u16 class = dev->class >> 8; > + > + head.next = NULL; > + > + /* Don't touch classless devices or host bridges or ioapics. */ > + if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) > + return; > + > + /* Don't touch ioapic devices already enabled by firmware */ > + if (class == PCI_CLASS_SYSTEM_PIC) { > + u16 command; > + pci_read_config_word(dev, PCI_COMMAND, &command); > + if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) > + return; > + } > + > + pdev_sort_resources(dev, &head); > + > + for (list = head.next; list;) { > + res = list->res; > + idx = res - &list->dev->resource[0]; > + if (pci_assign_resource(list->dev, idx)) { > + if (fail_head && !list->dev->subordinate && > + !pci_is_root_bus(list->dev->bus)) { > + /* > + * device need to keep flags and size > + * for second try > + */ > + add_to_failed_list(fail_head, list->dev, res); > + } else { > + res->start = 0; > + res->end = 0; > + res->flags = 0; > + } > + } > + tmp = list; > + list = list->next; > + kfree(tmp); > + } > +} > static void pbus_assign_resources_sorted(const struct pci_bus *bus, > struct resource_list *fail_head) > { > @@ -282,9 +328,6 @@ static void __pci_setup_bridge(struct pc > { > struct pci_dev *bridge = bus->self; > > - if (pci_is_enabled(bridge)) > - return; > - > dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", > bus->secondary, bus->subordinate); > > @@ -645,7 +688,8 @@ static void __ref __pci_bus_assign_resou > > switch (dev->class >> 8) { > case PCI_CLASS_BRIDGE_PCI: > - pci_setup_bridge(b); > + if (!pci_is_enabled(dev)) > + pci_setup_bridge(b); > break; > > case PCI_CLASS_BRIDGE_CARDBUS: > @@ -666,6 +710,34 @@ void __ref pci_bus_assign_resources(cons > } > EXPORT_SYMBOL(pci_bus_assign_resources); > > +static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, > + struct resource_list *fail_head) > +{ > + struct pci_bus *b; > + > + pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head); > + > + b = bridge->subordinate; > + if (!b) > + return; > + > + __pci_bus_assign_resources(b, fail_head); > + > + switch (bridge->class >> 8) { > + case PCI_CLASS_BRIDGE_PCI: > + pci_setup_bridge(b); > + break; > + > + case PCI_CLASS_BRIDGE_CARDBUS: > + pci_setup_cardbus(b); > + break; > + > + default: > + dev_info(&bridge->dev, "not setting up bridge for bus " > + "%04x:%02x\n", pci_domain_nr(b), b->number); > + break; > + } > +} > static void release_children_resource(struct resource *r) > { > struct resource *p; > @@ -841,3 +913,53 @@ enable_and_dump: > pci_bus_dump_resources(bus); > } > } > + > +void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) > +{ > + struct pci_bus *bus; > + struct pci_bus *parent = bridge->subordinate; > + bool second_tried = false; > + struct resource_list head, *list, *tmp; > + int retval; > + unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | > + IORESOURCE_PREFETCH; > + > +again: > + head.next = NULL; > + > + pci_bus_size_bridges(parent); > + pci_clear_master(bridge); > + __pci_bridge_assign_resources(bridge, &head); > + retval = pci_reenable_device(bridge); > + pci_set_master(bridge); > + pci_enable_bridges(parent); > + > + /* any device complain? */ > + if (!head.next) > + return; > + > + if (second_tried) { > + /* still fail, don't want to try more */ > + free_failed_list(&head); > + return; > + } > + > + second_tried = true; > + printk(KERN_DEBUG "PCI: second try to assign unassigned res\n"); > + > + /* > + * Try to release leaf bridge's resources that doesn't fit resource of > + * child device under that bridge > + */ > + for (list = head.next; list;) { > + bus = list->dev->bus; > + pci_bus_release_unused_bridge_res(bus, > + list->res->flags & type_mask); > + tmp = list; > + list = list->next; > + kfree(tmp); > + } > + > + goto again; > +} > +EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); > Index: linux-2.6/include/linux/pci.h > =================================================================== > --- linux-2.6.orig/include/linux/pci.h > +++ linux-2.6/include/linux/pci.h > @@ -768,6 +768,7 @@ void pci_bus_assign_resources(const stru > void pci_bus_size_bridges(struct pci_bus *bus); > int pci_claim_resource(struct pci_dev *, int); > void pci_assign_unassigned_resources(void); > +void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); > void pdev_enable_device(struct pci_dev *); > void pdev_sort_resources(struct pci_dev *, struct resource_list *); > int pci_enable_resources(struct pci_dev *, int mask); > > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Kenji Kaneshige wrote: > Can I ask which is the latest version? > > I think -v10 is the latest. But I could not find -v10 for patch 1/2. please use http://patchwork.kernel.org/patch/57814/ 1/2 -v9 http://patchwork.kernel.org/patch/58294/ 2/2 -v10 Thanks Yinghai -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Yinghai Lu wrote: > Kenji Kaneshige wrote: >> Can I ask which is the latest version? >> >> I think -v10 is the latest. But I could not find -v10 for patch 1/2. > > please use > > http://patchwork.kernel.org/patch/57814/ 1/2 -v9 > http://patchwork.kernel.org/patch/58294/ 2/2 -v10 > Regardless of PCIe hotplug, some of PCIe devices (not on hotplug slots) doesn't work with your patches by the following error. Copyright (c) 2007-2009 Intel Corporation. igb 0000:07:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 igb 0000:07:00.0: setting latency timer to 64 igb 0000:07:00.0: PCI INT A disabled igb: probe of 0000:07:00.0 failed with error -5 igb 0000:07:00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17 igb 0000:07:00.1: setting latency timer to 64 igb 0000:07:00.1: PCI INT B disabled igb: probe of 0000:07:00.1 failed with error -5 igb 0000:08:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 igb 0000:08:00.0: setting latency timer to 64 igb 0000:08:00.0: PCI INT A disabled igb: probe of 0000:08:00.0 failed with error -5 igb 0000:08:00.1: PCI INT B -> GSI 18 (level, low) -> IRQ 18 igb 0000:08:00.1: setting latency timer to 64 igb 0000:08:00.1: PCI INT B disabled igb: probe of 0000:08:00.1 failed with error -5 I'm using Jesse's latest linux-next. I'm attaching the /proc/iomem outputs. The iomem-default.txt is /proc/iomem output without your patches. The iomem-yinghai.txt is /proc/iomem output with your patches. Thanks, Kenji Kaneshige 00000000-0009efff : System RAM 0009f000-0009ffff : ACPI Non-volatile Storage 00100000-79190fff : System RAM 01000000-0141dbe2 : Kernel code 0141dbe3-0183639f : Kernel data 01acb000-027006f7 : Kernel bss 79191000-791c0fff : reserved 791c1000-79207fff : System RAM 79208000-79214fff : ACPI Tables 79215000-79321fff : System RAM 79322000-79322fff : reserved 79323000-7934afff : System RAM 7934b000-7934bfff : ACPI Tables 7934c000-793dffff : System RAM 793e0000-793e1fff : ACPI Tables 793e2000-79401fff : System RAM 79402000-79404fff : ACPI Tables 79405000-79450fff : System RAM 79451000-79451fff : ACPI Tables 79452000-79452fff : ACPI Non-volatile Storage 79453000-799e6fff : System RAM 799e7000-799e9fff : reserved 799ea000-799eefff : System RAM 799ef000-799f1fff : reserved 799f2000-79a30fff : System RAM 79a31000-79a34fff : reserved 79a35000-79a3cfff : System RAM 79a3d000-79a5ffff : reserved 79a60000-79aa1fff : System RAM 79aa2000-7a2b2fff : ACPI Non-volatile Storage 7a2b3000-7a302fff : System RAM 7a303000-7a303fff : reserved 7a304000-7a31dfff : System RAM 7a31e000-7a31efff : ACPI Tables 7a31f000-7a320fff : ACPI Non-volatile Storage 7a321000-7a3a4fff : System RAM 7a3a5000-7a3a7fff : reserved 7a3a8000-7a3a8fff : ACPI Tables 7a3a9000-7a3b4fff : System RAM 7a3b5000-7a3d4fff : reserved 7a3d5000-7a43dfff : System RAM 7a43e000-7a443fff : reserved 7a444000-7a4a1fff : System RAM 7a4a2000-7a4a5fff : reserved 7a4a6000-7a4f3fff : System RAM 7a4f4000-7a4fbfff : reserved 7a4fc000-7a514fff : System RAM 7a515000-7a515fff : ACPI Tables 7a516000-7a553fff : System RAM 7a554000-7a557fff : reserved 7a558000-7a9a9fff : System RAM 7a9aa000-7a9aafff : reserved 7a9ab000-7a9e3fff : System RAM 7a9e4000-7a9e7fff : reserved 7a9e8000-7aad4fff : System RAM 7aad5000-7aad5fff : reserved 7aad6000-7af3efff : System RAM 7af3f000-7af3ffff : reserved 7af40000-7af44fff : System RAM 7af45000-7af45fff : reserved 7af46000-7effffff : System RAM 7f000000-7fffffff : RAM buffer 80000000-8fffffff : PCI MMCONFIG 0 [00-ff] 80000000-8fffffff : reserved 90000000-fbffffff : PCI Bus #00 90000000-90ffffff : PCI Bus 0000:19 90000000-90ffffff : 0000:19:00.0 90000000-907fffff : efifb 91000000-917fffff : PCI Bus 0000:03 91000000-917fffff : PCI Bus 0000:04 91000000-917fffff : PCI Bus 0000:0c 91000000-917fffff : PCI Bus 0000:0d 91000000-911fffff : PCI Bus 0000:11 91000000-9103ffff : 0000:11:00.0 91200000-913fffff : PCI Bus 0000:10 91400000-915fffff : PCI Bus 0000:0f 91400000-9141ffff : 0000:0f:00.0 91420000-9143ffff : 0000:0f:00.1 91600000-917fffff : PCI Bus 0000:0e c6000000-c68fffff : PCI Bus 0000:19 c6000000-c67fffff : 0000:19:00.0 c6800000-c6803fff : 0000:19:00.0 c6810000-c681ffff : 0000:19:00.0 c6a00000-c79fffff : PCI Bus 0000:03 c6a00000-c79fffff : PCI Bus 0000:04 c6a00000-c75fffff : PCI Bus 0000:0c c6a00000-c75fffff : PCI Bus 0000:0d c6a00000-c6cfffff : PCI Bus 0000:11 c6c00000-c6c03fff : 0000:11:00.0 c6c04000-c6c04fff : 0000:11:00.0 c6e00000-c6ffffff : PCI Bus 0000:10 c7000000-c72fffff : PCI Bus 0000:0f c7200000-c721ffff : 0000:0f:00.1 c7200000-c721ffff : e1000e c7220000-c723ffff : 0000:0f:00.1 c7220000-c723ffff : e1000e c7240000-c725ffff : 0000:0f:00.0 c7240000-c725ffff : e1000e c7260000-c727ffff : 0000:0f:00.0 c7260000-c727ffff : e1000e c7400000-c75fffff : PCI Bus 0000:0e c7600000-c79fffff : PCI Bus 0000:05 c7600000-c79fffff : PCI Bus 0000:06 c7600000-c76fffff : PCI Bus 0000:0a c7600000-c760ffff : 0000:0a:00.0 c7600000-c760ffff : mpt c7610000-c7613fff : 0000:0a:00.0 c7610000-c7613fff : mpt c7700000-c77fffff : PCI Bus 0000:09 c7700000-c770ffff : 0000:09:00.0 c7700000-c770ffff : mpt c7710000-c7713fff : 0000:09:00.0 c7710000-c7713fff : mpt c7800000-c78fffff : PCI Bus 0000:08 c7800000-c781ffff : 0000:08:00.1 c7800000-c781ffff : igb c7820000-c783ffff : 0000:08:00.1 c7820000-c783ffff : igb c7840000-c785ffff : 0000:08:00.0 c7840000-c785ffff : igb c7860000-c787ffff : 0000:08:00.0 c7860000-c787ffff : igb c7880000-c7883fff : 0000:08:00.1 c7880000-c7883fff : igb c7884000-c7887fff : 0000:08:00.0 c7884000-c7887fff : igb c78a0000-c78bffff : 0000:08:00.0 c78c0000-c78dffff : 0000:08:00.1 c78e0000-c78fffff : 0000:08:00.0 c7900000-c79fffff : PCI Bus 0000:07 c7900000-c791ffff : 0000:07:00.1 c7900000-c791ffff : igb c7920000-c793ffff : 0000:07:00.1 c7920000-c793ffff : igb c7940000-c795ffff : 0000:07:00.0 c7940000-c795ffff : igb c7960000-c797ffff : 0000:07:00.0 c7960000-c797ffff : igb c7980000-c7983fff : 0000:07:00.1 c7980000-c7983fff : igb c7984000-c7987fff : 0000:07:00.0 c7984000-c7987fff : igb c79a0000-c79bffff : 0000:07:00.0 c79c0000-c79dffff : 0000:07:00.1 c79e0000-c79fffff : 0000:07:00.0 c7a00000-c7a1ffff : 0000:00:19.0 c7a00000-c7a1ffff : e1000e c7a20000-c7a23fff : 0000:00:16.0 c7a20000-c7a23fff : ioatdma c7a24000-c7a27fff : 0000:00:16.1 c7a24000-c7a27fff : ioatdma c7a28000-c7a2bfff : 0000:00:16.2 c7a28000-c7a2bfff : ioatdma c7a2c000-c7a2ffff : 0000:00:16.3 c7a2c000-c7a2ffff : ioatdma c7a30000-c7a33fff : 0000:00:16.4 c7a30000-c7a33fff : ioatdma c7a34000-c7a37fff : 0000:00:16.5 c7a34000-c7a37fff : ioatdma c7a38000-c7a3bfff : 0000:00:16.6 c7a38000-c7a3bfff : ioatdma c7a3c000-c7a3ffff : 0000:00:16.7 c7a3c000-c7a3ffff : ioatdma c7a40000-c7a40fff : 0000:00:1f.6 c7a41000-c7a41fff : 0000:00:19.0 c7a41000-c7a41fff : e1000e c7a42000-c7a42fff : 0000:00:13.0 c7a43000-c7a433ff : 0000:00:1d.7 c7a43000-c7a433ff : ehci_hcd c7a43400-c7a437ff : 0000:00:1a.7 c7a43400-c7a437ff : ehci_hcd c7a43800-c7a438ff : 0000:00:1f.3 fec00000-fec00fff : IOAPIC 0 fee00000-fee00fff : Local APIC 100000000-47fffffff : System RAM fc000000000-fc07fffffff : PCI Bus #00 00000000-0009efff : System RAM 0009f000-0009ffff : ACPI Non-volatile Storage 00100000-79190fff : System RAM 01000000-0141e142 : Kernel code 0141e143-0183639f : Kernel data 01acb000-027006f7 : Kernel bss 79191000-791c0fff : reserved 791c1000-79207fff : System RAM 79208000-79214fff : ACPI Tables 79215000-79321fff : System RAM 79322000-79322fff : reserved 79323000-7934afff : System RAM 7934b000-7934bfff : ACPI Tables 7934c000-793dffff : System RAM 793e0000-793e1fff : ACPI Tables 793e2000-79401fff : System RAM 79402000-79404fff : ACPI Tables 79405000-79450fff : System RAM 79451000-79451fff : ACPI Tables 79452000-79452fff : ACPI Non-volatile Storage 79453000-799e6fff : System RAM 799e7000-799e9fff : reserved 799ea000-799eefff : System RAM 799ef000-799f1fff : reserved 799f2000-79a30fff : System RAM 79a31000-79a34fff : reserved 79a35000-79a3cfff : System RAM 79a3d000-79a5ffff : reserved 79a60000-79aa1fff : System RAM 79aa2000-7a2b2fff : ACPI Non-volatile Storage 7a2b3000-7a302fff : System RAM 7a303000-7a303fff : reserved 7a304000-7a31dfff : System RAM 7a31e000-7a31efff : ACPI Tables 7a31f000-7a320fff : ACPI Non-volatile Storage 7a321000-7a3a4fff : System RAM 7a3a5000-7a3a7fff : reserved 7a3a8000-7a3a8fff : ACPI Tables 7a3a9000-7a3b4fff : System RAM 7a3b5000-7a3d4fff : reserved 7a3d5000-7a43dfff : System RAM 7a43e000-7a443fff : reserved 7a444000-7a4a1fff : System RAM 7a4a2000-7a4a5fff : reserved 7a4a6000-7a4f3fff : System RAM 7a4f4000-7a4fbfff : reserved 7a4fc000-7a514fff : System RAM 7a515000-7a515fff : ACPI Tables 7a516000-7a553fff : System RAM 7a554000-7a557fff : reserved 7a558000-7a9a9fff : System RAM 7a9aa000-7a9aafff : reserved 7a9ab000-7a9e3fff : System RAM 7a9e4000-7a9e7fff : reserved 7a9e8000-7aad4fff : System RAM 7aad5000-7aad5fff : reserved 7aad6000-7af3efff : System RAM 7af3f000-7af3ffff : reserved 7af40000-7af44fff : System RAM 7af45000-7af45fff : reserved 7af46000-7effffff : System RAM 7f000000-7fffffff : RAM buffer 80000000-8fffffff : PCI MMCONFIG 0 [00-ff] 80000000-8fffffff : reserved 90000000-fbffffff : PCI Bus #00 90000000-90ffffff : PCI Bus 0000:19 90000000-90ffffff : 0000:19:00.0 90000000-907fffff : efifb 91000000-917fffff : PCI Bus 0000:03 91000000-917fffff : PCI Bus 0000:04 91000000-917fffff : PCI Bus 0000:0c 91000000-917fffff : PCI Bus 0000:0d 91000000-911fffff : PCI Bus 0000:11 91000000-9103ffff : 0000:11:00.0 91200000-913fffff : PCI Bus 0000:10 91400000-915fffff : PCI Bus 0000:0f 91400000-9141ffff : 0000:0f:00.0 91420000-9143ffff : 0000:0f:00.1 91600000-917fffff : PCI Bus 0000:0e c6000000-c68fffff : PCI Bus 0000:19 c6000000-c67fffff : 0000:19:00.0 c6800000-c6803fff : 0000:19:00.0 c6810000-c681ffff : 0000:19:00.0 c6a00000-c79fffff : PCI Bus 0000:03 c6a00000-c79fffff : PCI Bus 0000:04 c6a00000-c75fffff : PCI Bus 0000:0c c6a00000-c75fffff : PCI Bus 0000:0d c6a00000-c6cfffff : PCI Bus 0000:11 c6c00000-c6c03fff : 0000:11:00.0 c6c00000-c6c03fff : lpfc c6c04000-c6c04fff : 0000:11:00.0 c6c04000-c6c04fff : lpfc c6e00000-c6ffffff : PCI Bus 0000:10 c7000000-c72fffff : PCI Bus 0000:0f c7200000-c721ffff : 0000:0f:00.1 c7200000-c721ffff : e1000e c7220000-c723ffff : 0000:0f:00.1 c7220000-c723ffff : e1000e c7240000-c725ffff : 0000:0f:00.0 c7240000-c725ffff : e1000e c7260000-c727ffff : 0000:0f:00.0 c7260000-c727ffff : e1000e c7400000-c75fffff : PCI Bus 0000:0e c7600000-c79fffff : PCI Bus 0000:05 c7600000-c79fffff : PCI Bus 0000:06 c7600000-c76fffff : PCI Bus 0000:0a c7600000-c760ffff : 0000:0a:00.0 c7600000-c760ffff : mpt c7610000-c7613fff : 0000:0a:00.0 c7610000-c7613fff : mpt c7700000-c77fffff : PCI Bus 0000:09 c7700000-c770ffff : 0000:09:00.0 c7700000-c770ffff : mpt c7710000-c7713fff : 0000:09:00.0 c7710000-c7713fff : mpt c7800000-c79fffff : PCI Bus 0000:09 c7800000-c79fffff : 0000:09:00.0 c7a00000-c7a1ffff : 0000:00:19.0 c7a00000-c7a1ffff : e1000e c7a20000-c7a23fff : 0000:00:16.0 c7a20000-c7a23fff : ioatdma c7a24000-c7a27fff : 0000:00:16.1 c7a24000-c7a27fff : ioatdma c7a28000-c7a2bfff : 0000:00:16.2 c7a28000-c7a2bfff : ioatdma c7a2c000-c7a2ffff : 0000:00:16.3 c7a2c000-c7a2ffff : ioatdma c7a30000-c7a33fff : 0000:00:16.4 c7a30000-c7a33fff : ioatdma c7a34000-c7a37fff : 0000:00:16.5 c7a34000-c7a37fff : ioatdma c7a38000-c7a3bfff : 0000:00:16.6 c7a38000-c7a3bfff : ioatdma c7a3c000-c7a3ffff : 0000:00:16.7 c7a3c000-c7a3ffff : ioatdma c7a40000-c7a40fff : 0000:00:1f.6 c7a41000-c7a41fff : 0000:00:19.0 c7a41000-c7a41fff : e1000e c7a42000-c7a42fff : 0000:00:13.0 c7a43000-c7a433ff : 0000:00:1d.7 c7a43000-c7a433ff : ehci_hcd c7a43400-c7a437ff : 0000:00:1a.7 c7a43400-c7a437ff : ehci_hcd c7a43800-c7a438ff : 0000:00:1f.3 fec00000-fec00fff : IOAPIC 0 fee00000-fee00fff : Local APIC 100000000-47fffffff : System RAM fc000000000-fc07fffffff : PCI Bus #00
Kenji Kaneshige wrote: > Yinghai Lu wrote: >> Kenji Kaneshige wrote: >>> Can I ask which is the latest version? >>> >>> I think -v10 is the latest. But I could not find -v10 for patch 1/2. >> >> please use >> >> http://patchwork.kernel.org/patch/57814/ 1/2 -v9 >> http://patchwork.kernel.org/patch/58294/ 2/2 -v10 >> > > Regardless of PCIe hotplug, some of PCIe devices (not on hotplug > slots) doesn't work with your patches by the following error. > > Copyright (c) 2007-2009 Intel Corporation. > igb 0000:07:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 > igb 0000:07:00.0: setting latency timer to 64 > igb 0000:07:00.0: PCI INT A disabled > igb: probe of 0000:07:00.0 failed with error -5 > igb 0000:07:00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17 > igb 0000:07:00.1: setting latency timer to 64 > igb 0000:07:00.1: PCI INT B disabled > igb: probe of 0000:07:00.1 failed with error -5 > igb 0000:08:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 > igb 0000:08:00.0: setting latency timer to 64 > igb 0000:08:00.0: PCI INT A disabled > igb: probe of 0000:08:00.0 failed with error -5 > igb 0000:08:00.1: PCI INT B -> GSI 18 (level, low) -> IRQ 18 > igb 0000:08:00.1: setting latency timer to 64 > igb 0000:08:00.1: PCI INT B disabled > igb: probe of 0000:08:00.1 failed with error -5 > > I'm using Jesse's latest linux-next. > I'm attaching the /proc/iomem outputs. The iomem-default.txt is > /proc/iomem output without your patches. The iomem-yinghai.txt > is /proc/iomem output with your patches. can you post whole bootlog with pci debug enabled? Thanks Yinghai -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Yinghai Lu wrote: > Kenji Kaneshige wrote: >> Yinghai Lu wrote: >>> Kenji Kaneshige wrote: >>>> Can I ask which is the latest version? >>>> >>>> I think -v10 is the latest. But I could not find -v10 for patch 1/2. >>> please use >>> >>> http://patchwork.kernel.org/patch/57814/ 1/2 -v9 >>> http://patchwork.kernel.org/patch/58294/ 2/2 -v10 >>> >> Regardless of PCIe hotplug, some of PCIe devices (not on hotplug >> slots) doesn't work with your patches by the following error. >> >> Copyright (c) 2007-2009 Intel Corporation. >> igb 0000:07:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 >> igb 0000:07:00.0: setting latency timer to 64 >> igb 0000:07:00.0: PCI INT A disabled >> igb: probe of 0000:07:00.0 failed with error -5 >> igb 0000:07:00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17 >> igb 0000:07:00.1: setting latency timer to 64 >> igb 0000:07:00.1: PCI INT B disabled >> igb: probe of 0000:07:00.1 failed with error -5 >> igb 0000:08:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 >> igb 0000:08:00.0: setting latency timer to 64 >> igb 0000:08:00.0: PCI INT A disabled >> igb: probe of 0000:08:00.0 failed with error -5 >> igb 0000:08:00.1: PCI INT B -> GSI 18 (level, low) -> IRQ 18 >> igb 0000:08:00.1: setting latency timer to 64 >> igb 0000:08:00.1: PCI INT B disabled >> igb: probe of 0000:08:00.1 failed with error -5 >> >> I'm using Jesse's latest linux-next. >> I'm attaching the /proc/iomem outputs. The iomem-default.txt is >> /proc/iomem output without your patches. The iomem-yinghai.txt >> is /proc/iomem output with your patches. > > can you post whole bootlog with pci debug enabled? > I'll send it privately. Thanks, Kenji Kaneshige -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Patch
Index: linux-2.6/drivers/pci/hotplug/pciehp_pci.c =================================================================== --- linux-2.6.orig/drivers/pci/hotplug/pciehp_pci.c +++ linux-2.6/drivers/pci/hotplug/pciehp_pci.c @@ -53,17 +53,15 @@ static int __ref pciehp_add_bridge(struc busnr = pci_scan_bridge(parent, dev, busnr, pass); if (!dev->subordinate) return -1; - pci_bus_size_bridges(dev->subordinate); - pci_bus_assign_resources(parent); - pci_enable_bridges(parent); - pci_bus_add_devices(parent); + return 0; } int pciehp_configure_device(struct slot *p_slot) { struct pci_dev *dev; - struct pci_bus *parent = p_slot->ctrl->pcie->port->subordinate; + struct pci_dev *bridge = p_slot->ctrl->pcie->port; + struct pci_bus *parent = bridge->subordinate; int num, fn; struct controller *ctrl = p_slot->ctrl; @@ -96,12 +94,25 @@ int pciehp_configure_device(struct slot (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { pciehp_add_bridge(dev); } + pci_dev_put(dev); + } + + pci_assign_unassigned_bridge_resources(bridge); + + for (fn = 0; fn < 8; fn++) { + dev = pci_get_slot(parent, PCI_DEVFN(0, fn)); + if (!dev) + continue; + if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) { + pci_dev_put(dev); + continue; + } pci_configure_slot(dev); pci_dev_put(dev); } - pci_bus_assign_resources(parent); pci_bus_add_devices(parent); + return 0; } Index: linux-2.6/drivers/pci/setup-bus.c =================================================================== --- linux-2.6.orig/drivers/pci/setup-bus.c +++ linux-2.6/drivers/pci/setup-bus.c @@ -68,6 +68,52 @@ static void free_failed_list(struct reso head->next = NULL; } +static void pdev_assign_resources_sorted(struct pci_dev *dev, + struct resource_list *fail_head) +{ + struct resource *res; + struct resource_list head, *list, *tmp; + int idx; + u16 class = dev->class >> 8; + + head.next = NULL; + + /* Don't touch classless devices or host bridges or ioapics. */ + if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) + return; + + /* Don't touch ioapic devices already enabled by firmware */ + if (class == PCI_CLASS_SYSTEM_PIC) { + u16 command; + pci_read_config_word(dev, PCI_COMMAND, &command); + if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) + return; + } + + pdev_sort_resources(dev, &head); + + for (list = head.next; list;) { + res = list->res; + idx = res - &list->dev->resource[0]; + if (pci_assign_resource(list->dev, idx)) { + if (fail_head && !list->dev->subordinate && + !pci_is_root_bus(list->dev->bus)) { + /* + * device need to keep flags and size + * for second try + */ + add_to_failed_list(fail_head, list->dev, res); + } else { + res->start = 0; + res->end = 0; + res->flags = 0; + } + } + tmp = list; + list = list->next; + kfree(tmp); + } +} static void pbus_assign_resources_sorted(const struct pci_bus *bus, struct resource_list *fail_head) { @@ -282,9 +328,6 @@ static void __pci_setup_bridge(struct pc { struct pci_dev *bridge = bus->self; - if (pci_is_enabled(bridge)) - return; - dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", bus->secondary, bus->subordinate); @@ -645,7 +688,8 @@ static void __ref __pci_bus_assign_resou switch (dev->class >> 8) { case PCI_CLASS_BRIDGE_PCI: - pci_setup_bridge(b); + if (!pci_is_enabled(dev)) + pci_setup_bridge(b); break; case PCI_CLASS_BRIDGE_CARDBUS: @@ -666,6 +710,34 @@ void __ref pci_bus_assign_resources(cons } EXPORT_SYMBOL(pci_bus_assign_resources); +static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, + struct resource_list *fail_head) +{ + struct pci_bus *b; + + pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head); + + b = bridge->subordinate; + if (!b) + return; + + __pci_bus_assign_resources(b, fail_head); + + switch (bridge->class >> 8) { + case PCI_CLASS_BRIDGE_PCI: + pci_setup_bridge(b); + break; + + case PCI_CLASS_BRIDGE_CARDBUS: + pci_setup_cardbus(b); + break; + + default: + dev_info(&bridge->dev, "not setting up bridge for bus " + "%04x:%02x\n", pci_domain_nr(b), b->number); + break; + } +} static void release_children_resource(struct resource *r) { struct resource *p; @@ -841,3 +913,53 @@ enable_and_dump: pci_bus_dump_resources(bus); } } + +void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) +{ + struct pci_bus *bus; + struct pci_bus *parent = bridge->subordinate; + bool second_tried = false; + struct resource_list head, *list, *tmp; + int retval; + unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | + IORESOURCE_PREFETCH; + +again: + head.next = NULL; + + pci_bus_size_bridges(parent); + pci_clear_master(bridge); + __pci_bridge_assign_resources(bridge, &head); + retval = pci_reenable_device(bridge); + pci_set_master(bridge); + pci_enable_bridges(parent); + + /* any device complain? */ + if (!head.next) + return; + + if (second_tried) { + /* still fail, don't want to try more */ + free_failed_list(&head); + return; + } + + second_tried = true; + printk(KERN_DEBUG "PCI: second try to assign unassigned res\n"); + + /* + * Try to release leaf bridge's resources that doesn't fit resource of + * child device under that bridge + */ + for (list = head.next; list;) { + bus = list->dev->bus; + pci_bus_release_unused_bridge_res(bus, + list->res->flags & type_mask); + tmp = list; + list = list->next; + kfree(tmp); + } + + goto again; +} +EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); Index: linux-2.6/include/linux/pci.h =================================================================== --- linux-2.6.orig/include/linux/pci.h +++ linux-2.6/include/linux/pci.h @@ -768,6 +768,7 @@ void pci_bus_assign_resources(const stru void pci_bus_size_bridges(struct pci_bus *bus); int pci_claim_resource(struct pci_dev *, int); void pci_assign_unassigned_resources(void); +void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); void pdev_enable_device(struct pci_dev *); void pdev_sort_resources(struct pci_dev *, struct resource_list *); int pci_enable_resources(struct pci_dev *, int mask);
move out bus_size_bridges and assign resources out of pciehp_add_bridge() and at last do them all together one time including slot bridge, to avoid to call assign resources several times, when there are several bridges under the slot bridge. need to introduce pci_bridge_assign_resources there. handle the case the slot bridge that doesn't get pre-allocated big enough res from FW. for example pcie devices need 256M, but the bridge only get preallocated 2M... pci_setup_bridge() will take extra check_enabled for the slot bridge, otherwise update res is not updated to bridge BAR. that is bridge is enabled already for port service. v2: address Alex's concern about pci remove/rescan feature about pci_setup_bridge changes. v3: Kenji pointed out that pci_config_slot need to be called before pci_bus_add_devices() v4: move out pci_is_enabled checkout of pci_setup_bridge() v5: change the applying sequence. v6: change the functions name according to Jesse v8: address Eric's concern, only overwrite leaf bridge resource that is not big enough v9: refresh to be applied after bjorn's patch, and remove trick about save size and restore resource second try. v10: alex found need to have export for pci_assign_unassigned_bridge_resources Signed-off-by: Yinghai Lu <yinghai@kernel.org> --- drivers/pci/hotplug/pciehp_pci.c | 23 +++++- drivers/pci/setup-bus.c | 130 +++++++++++++++++++++++++++++++++++++-- include/linux/pci.h | 1 3 files changed, 144 insertions(+), 10 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html