@@ -246,6 +246,31 @@ void __init omap3_check_revision(void)
}
}
+void __init omap4_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev;
+ char *rev_name = "ES1.0";
+
+ /*
+ * The IC rev detection is done with hawkeye and rev.
+ * Note that rev does not map directly to defined processor
+ * revision numbers as ES1.0 uses value 0.
+ */
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+
+ if ((hawkeye == 0xb852) && (rev == 0x0)) {
+ omap_revision = OMAP4430_REV_ES1_0;
+ pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
+ return;
+ }
+
+ printk(KERN_ERR "Unknown OMAP CPU id\n");
+}
+
#define OMAP3_SHOW_FEATURE(feat) \
if (omap3_has_ ##feat()) \
printk(#feat" ");
@@ -336,7 +361,7 @@ void __init omap2_check_revision(void)
omap3_check_features();
omap3_cpuinfo();
} else if (cpu_is_omap44xx()) {
- printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
+ omap4_check_revision();
return;
} else {
pr_err("OMAP revision unknown, please fix!\n");
@@ -280,7 +280,7 @@ void __init omap2_set_globals_343x(void)
#if defined(CONFIG_ARCH_OMAP4)
static struct omap_globals omap4_globals = {
.class = OMAP443X_CLASS,
- .tap = OMAP2_L4_IO_ADDRESS(0x4830a000),
+ .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
.ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
.prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
@@ -443,7 +443,8 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12))
#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12))
-#define OMAP443X_CLASS 0x44300034
+#define OMAP443X_CLASS 0x44300044
+#define OMAP4430_REV_ES1_0 0x44300044
/*
* omap_chip bits