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Tue, 31 Oct 2023 16:49:47 +0000 From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Dragan Mladjenovic , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang Subject: [PATCH v3 06/11] irqchip: mips-gic: Multi-cluster support Date: Tue, 31 Oct 2023 17:49:22 +0100 Message-Id: <20231031164927.371663-7-aleksandar.rikalo@syrmia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231031164927.371663-1-aleksandar.rikalo@syrmia.com> References: <20231031164927.371663-1-aleksandar.rikalo@syrmia.com> X-ClientProxiedBy: AM0PR10CA0065.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:208:15::18) To VI1PR0302MB3486.eurprd03.prod.outlook.com (2603:10a6:803:1e::32) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0302MB3486:EE_|AM9PR03MB7187:EE_ X-MS-Office365-Filtering-Correlation-Id: b830f2ca-5b7d-49b2-c235-08dbda31644d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1/qmUVBxeH5MvjgJJm2hv16h+RrHeVYYifCGe55M0GOlvhzQst7WYuXDcE3fWiC19NFNP7K/jk7xPdtuUsS7ttQYtQZxQDjJny57voQtutmHGTVhgVkWYz0cxRMEbgYWIrBtRL/4m8jQP6QLYRIs/AEgPFNoXlRz2UrV0F2AIYxmbjsEe/6TxcHo0GZzGvnkwbahedFI28OtbW3mdk73zcuVFpasDeoP44N4RMAY8fpkzr48Yd6vU9ReJF67ecaFyZWfI7IPMZAFB5kLdMvtfQzZzDoTrGWUaBITtznGKLpoJ/NKiXwOlKpgL0BgrqEnVXL1rcFSfvq1NSp6MRwtgOZg7DdbU19CJRjqxuRr4qCaxSuDItHMsZamzPGQDuhP/SaOmc/i+GWrPeVfMKVDmNIo9BB/HxoQ8Iuuh8O+ZeR/YLIvq6DuRsaimdkeLfBIGz06tvyJrh32u/9dhvDoSp/vzErQ7VfKGFVcp+issePNe0zXrq2Z7OyXzWFANYN8uVcdHcwNUnlNXtZKrtzNo3mTeYeCibVwu0UwBUY7kqZTejOhwi2nbl8qwIvfqquxKyk6RwCBGZY+vthPmPBybitfXjBy/s5Kfr42n0yDnJoD4VmGckSWckqyIeruhQKvB50pv/BYD7ryXMnU6XiY7ybuPefomWLs1B+6aDcwp6ywehYZpzvm4FtjeBi2+L3bA/7fH7gDoOZsNdfBIQo97Qr20gYHxdG3WnQwe03MVEqxGPL5PuMqPHnYSPHSaQIzgjwYwJQRva62iyw7ljIP1RjCAo0lUG67UIgy6IJpLt0qka/YngZzEj+VqkHFN8DcHi6WVjTbcVBODeyg4kIF0iTSPXd+QIGnxsWwYDNKmhFBvgYD1hmVSNeYka2uUddXdQRwyx2JdQvUkq5tKqzJiQ1ghYK+rkMx/CGneZM7+F2XsT+KIl8n67DpOEWBhYzsSN4AtVSiWIGgEjRQvcGbkrgrFEknhhL2mJjKTTLXPV2eKF8wNB7/cUFlBB3fZbTgxpJM8j7UzDOzq+84LpPm2pwD1krlF+xN1sYmPUIXQ2Guz6gB7hpRLAI1ZfXWtQNK7EnbAy0nXfhoT+eFA9IumstHHV+zOsgbWy9AY3vAR4sDZPT2VqLo2yaPDUsPMarYKl3smZTC6ngI8S0LOCS2aJxd804IgHdsO0gJw1VuLXdYrHAwPI0bNQr6Jzrng3v+YqEteRn0f6NSzuXkrwt0uX+XiLJaJIHFrkLme5eSCXHOH/VgZwmz+X4GkSk5KL8fu6pFmZyaCVWYTqxjdgG3qX3yByKEdRVEsfB2iyyIUSrZkMNQU218OSpmGJDuQHpojJFdhZGB/irw9+ybT/aBEpjW3IDzX/kkneuq2luuCdXcJ3TjW2LkWg2BDpfNr+nbQZwva4Z42ksuYobDaky5lbO5nCfPKU0mSYd7DFz11eYSFR4naheVhE2aeX6XXa3hjMpL5sPUVjCDTwAa1629VWrWf1citAtFpm5RvrIUfEcp8prhTjmGGo79DRxAZT9ag5ztr6CAqLVpTwW9dCWFoUhPvjBabP+7H37TuUk2irzfYRKgovNfLg8Q965aztXfrWGUszvo0l2tOYOgGyoaEg== X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b830f2ca-5b7d-49b2-c235-08dbda31644d X-MS-Exchange-CrossTenant-AuthSource: VI1PR0302MB3486.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2023 16:49:47.6473 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3q2jhfBmP+hYdaVJynZM8G/yxNvQJfGqqOwsITTqIx3ZRtODS2y3mukbxpr5oTBdWdvtifGi9kUQf3vU9+Gy7DW1M/xYwWpIgZrLtF580Pk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7187 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Burton The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept of multiple clusters to the system. In these systems each cluster contains its own GIC, so the GIC isn't truly global any longer. We do have the ability to access registers in the GICs of remote clusters using a redirect register block much like the redirect register blocks provided by the CM & CPC, and configured through the same GCR_REDIRECT register that we our mips_cm_lock_other() abstraction builds upon. It is expected that external interrupts are connected identically to all clusters. That is, if we have a device providing an interrupt connected to GIC interrupt pin 0 then it should be connected to pin 0 of every GIC in the system. This simplifies things somewhat by allowing us for the most part to treat the GIC as though it is still truly global, so long as we take care to configure interrupts in the cluster that we want them affine to. This patch introduces support for such multi-cluster systems in the MIPS GIC irqchip driver. We introduce a new gic_irq_lock_cluster() function which allows us to either: 1) Configure access to a GIC in a remote cluster via the redirect register block, using mips_cm_lock_other(). Or: 2) Detect that the interrupt in question is affine to the local cluster and we should use plain old GIC register access to the GIC in the local cluster. It is possible to access the local cluster's GIC registers via the redirect block, but keeping the special case for them is both good for performance (because we avoid the locking & indirection overhead of using the redirect block) and necessary to maintain compatibility with systems using CM revisions prior to 3.5 which don't support the redirect block. The gic_irq_lock_cluster() function relies upon an IRQs effective affinity in order to discover which cluster the IRQ is affine to. In order to track this & allow it to be updated at an appropriate point during gic_set_affinity() we select the generic support for effective affinity using CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK. gic_set_affinity() is the one function which gains much complexity. It now deconfigures routing to any VP(E), ie. CPU, on the old cluster when moving affinity to a new cluster. Because we only configure an interrupts trigger type in the cluster which it is affine to we call gic_set_type() to configure that in the new cluster, after having updated the effective affinity mask such that gic_irq_lock_cluster() begins operating on the new cluster. Finally we map the interrupt to the appropriate pin & VP(E) in the new cluster. gic_shared_irq_domain_map() moves its update of the IRQs effective affinity to before its use of gic_irq_lock_cluster(), in order to ensure we operate on the cluster the IRQ is affine to. The remaining changes are straightforward use of the gic_irq_lock_cluster() function to select between local cluster & remote cluster code-paths when configuring interrupts. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-mips-gic.c | 161 +++++++++++++++++++++++++++++---- 2 files changed, 143 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f7149d0f3d45..be9f0797c4ed 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -328,6 +328,7 @@ config KEYSTONE_IRQ config MIPS_GIC bool + select GENERIC_IRQ_EFFECTIVE_AFF_MASK select GENERIC_IRQ_IPI if SMP select IRQ_DOMAIN_HIERARCHY select MIPS_CM diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index cdd8973912a9..8e9046516e63 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -135,6 +135,41 @@ static inline void __lockdep_assert_held(raw_spinlock_t *gic_lock) (cpu) = __gic_with_next_online_cpu(cpu), \ (cpu) < nr_cpu_ids;) +/** + * gic_irq_lock_cluster() - Lock redirect block access to IRQ's cluster + * @d: struct irq_data corresponding to the interrupt we're interested in + * + * Locks redirect register block access to the global register block of the GIC + * within the remote cluster that the IRQ corresponding to @d is affine to, + * returning true when this redirect block setup & locking has been performed. + * + * If @d is affine to the local cluster then no locking is performed and this + * function will return false, indicating to the caller that it should access + * the local clusters registers without the overhead of indirection through the + * redirect block. + * + * In summary, if this function returns true then the caller should access GIC + * registers using redirect register block accessors & then call + * mips_cm_unlock_other() when done. If this function returns false then the + * caller should trivially access GIC registers in the local cluster. + * + * Returns true if locking performed, else false. + */ +static bool gic_irq_lock_cluster(struct irq_data *d) +{ + unsigned int cpu, cl; + + cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); + BUG_ON(cpu >= NR_CPUS); + + cl = cpu_cluster(&cpu_data[cpu]); + if (cl == cpu_cluster(¤t_cpu_data)) + return false; + + mips_cm_lock_other(cl, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + return true; +} + static void gic_clear_pcpu_masks(unsigned int intr) { unsigned int i; @@ -181,7 +216,12 @@ static void gic_send_ipi(struct irq_data *d, unsigned int cpu) { irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); - write_gic_wedge(GIC_WEDGE_RW | hwirq); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_wedge(GIC_WEDGE_RW | hwirq); + mips_cm_unlock_other(); + } else { + write_gic_wedge(GIC_WEDGE_RW | hwirq); + } } int gic_get_c0_compare_int(void) @@ -249,7 +289,13 @@ static void gic_mask_irq(struct irq_data *d) { unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); - write_gic_rmask(intr); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_rmask(intr); + mips_cm_unlock_other(); + } else { + write_gic_rmask(intr); + } + gic_clear_pcpu_masks(intr); } @@ -258,7 +304,12 @@ static void gic_unmask_irq(struct irq_data *d) unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); unsigned int cpu; - write_gic_smask(intr); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_smask(intr); + mips_cm_unlock_other(); + } else { + write_gic_smask(intr); + } gic_clear_pcpu_masks(intr); cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); @@ -269,7 +320,12 @@ static void gic_ack_irq(struct irq_data *d) { unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); - write_gic_wedge(irq); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_wedge(irq); + mips_cm_unlock_other(); + } else { + write_gic_wedge(irq); + } } static int gic_set_type(struct irq_data *d, unsigned int type) @@ -309,9 +365,16 @@ static int gic_set_type(struct irq_data *d, unsigned int type) break; } - change_gic_pol(irq, pol); - change_gic_trig(irq, trig); - change_gic_dual(irq, dual); + if (gic_irq_lock_cluster(d)) { + change_gic_redir_pol(irq, pol); + change_gic_redir_trig(irq, trig); + change_gic_redir_dual(irq, dual); + mips_cm_unlock_other(); + } else { + change_gic_pol(irq, pol); + change_gic_trig(irq, trig); + change_gic_dual(irq, dual); + } if (trig == GIC_TRIG_EDGE) irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, @@ -329,25 +392,72 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) { unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); + unsigned int cpu, cl, old_cpu, old_cl; unsigned long flags; - unsigned int cpu; + /* + * The GIC specifies that we can only route an interrupt to one VP(E), + * ie. CPU in Linux parlance, at a time. Therefore we always route to + * the first online CPU in the mask. + */ cpu = cpumask_first_and(cpumask, cpu_online_mask); if (cpu >= NR_CPUS) return -EINVAL; - /* Assumption : cpumask refers to a single CPU */ - raw_spin_lock_irqsave(&gic_lock, flags); + old_cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); + old_cl = cpu_cluster(&cpu_data[old_cpu]); + cl = cpu_cluster(&cpu_data[cpu]); - /* Re-route this IRQ */ - write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + raw_spin_lock_irqsave(&gic_lock, flags); - /* Update the pcpu_masks */ - gic_clear_pcpu_masks(irq); - if (read_gic_mask(irq)) - set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + /* + * If we're moving affinity between clusters, stop routing the + * interrupt to any VP(E) in the old cluster. + */ + if (cl != old_cl) { + if (gic_irq_lock_cluster(d)) { + write_gic_redir_map_vp(irq, 0); + mips_cm_unlock_other(); + } else { + write_gic_map_vp(irq, 0); + } + } + /* + * Update effective affinity - after this gic_irq_lock_cluster() will + * begin operating on the new cluster. + */ irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + /* + * If we're moving affinity between clusters, configure the interrupt + * trigger type in the new cluster. + */ + if (cl != old_cl) + gic_set_type(d, irqd_get_trigger_type(d)); + + /* Route the interrupt to its new VP(E) */ + if (gic_irq_lock_cluster(d)) { + write_gic_redir_map_pin(irq, + GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_redir_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + + /* Update the pcpu_masks */ + gic_clear_pcpu_masks(irq); + if (read_gic_redir_mask(irq)) + set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + + mips_cm_unlock_other(); + } else { + write_gic_map_pin(irq, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + + /* Update the pcpu_masks */ + gic_clear_pcpu_masks(irq); + if (read_gic_mask(irq)) + set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + } + raw_spin_unlock_irqrestore(&gic_lock, flags); return IRQ_SET_MASK_OK; @@ -503,11 +613,21 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, unsigned long flags; data = irq_get_irq_data(virq); + irq_data_update_effective_affinity(data, cpumask_of(cpu)); raw_spin_lock_irqsave(&gic_lock, flags); - write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); - write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); - irq_data_update_effective_affinity(data, cpumask_of(cpu)); + + /* Route the interrupt to its VP(E) */ + if (gic_irq_lock_cluster(data)) { + write_gic_redir_map_pin(intr, + GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_redir_map_vp(intr, BIT(mips_cm_vp_id(cpu))); + mips_cm_unlock_other(); + } else { + write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); + } + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0; @@ -687,6 +807,9 @@ static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, if (ret) goto error; + /* Set affinity to cpu. */ + irq_data_update_effective_affinity(irq_get_irq_data(virq + i), + cpumask_of(cpu)); ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); if (ret) goto error;