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Tue, 31 Oct 2023 16:49:51 +0000 From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Dragan Mladjenovic , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang Subject: [PATCH v3 08/11] clocksource: mips-gic-timer: Enable counter when CPUs start Date: Tue, 31 Oct 2023 17:49:24 +0100 Message-Id: <20231031164927.371663-9-aleksandar.rikalo@syrmia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231031164927.371663-1-aleksandar.rikalo@syrmia.com> References: <20231031164927.371663-1-aleksandar.rikalo@syrmia.com> X-ClientProxiedBy: AM0PR10CA0065.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:208:15::18) To VI1PR0302MB3486.eurprd03.prod.outlook.com (2603:10a6:803:1e::32) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0302MB3486:EE_|DB4PR03MB8706:EE_ X-MS-Office365-Filtering-Correlation-Id: 9249120b-70be-44dd-94a4-08dbda316687 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AP4HNrQMni7j3Rcag9IgZ8nI+rsB72kkqP0VY1Ay0uzulvXNoFp9LkMfDgoMaaMKBIkyE/M45sQExzr4tzPb08AxTOzBsk48ZkP9CuxHKCKmkPeVe7PvdBAdhF8E2WLKu6EkaR4PopGq7yFI7GgApk3zwze84w4ThHFUfYW9B+yTwvBf99q0MnTaVjmY4p9xsReCFTFpQuoEUIa/oMtGERluUtaAjDfzLR1jAFWRVexLotEZtBWekbpWNgnGmIUPfh2lmWuhgbHeCN/BHvaGNsPKJRKO9SYBJPuB34LEbbaz+8SedqOGUHMuKiYLtZpx0afPIwPOXdBQbfa6+Xhf2CPxiPrann60XbVFrphBk/Zu4eO77nf0ZC/z1HrJe2bhKfmEbY3t4x4ejrWBmraOTbQwNiKB11FLP4KvVzAVi7k0IPk/+0erl/BVzwtAACoTpwuX627Tv+acVMqiK2EbDs21MeZVxvI5iKq9WOGsz+MC7H71aT1gd4hFINLTsbCii7SPZIq9AJG3afE3xXt1BKFLdBQJY8urr9AjLkJynd8HwoJtXQJzL+ml/tD+taOCnwgyxjV96fAkvOa859ObBMXAdSD7t9gDzlgh9n61nDyoaGTGACIH5nRHQH7IgFV8T/aHbheGexdDaqG12qpJWXZle/QNNNZ3iu+XuhqkWRLGOaFzEWzvlxAbFukVPT7CZAdO7Fcdqig90Is3tAN8hfChttwmczqD3DVki1tFhtJVrHUnpDi3V1AlQxt4CB+eo3v8oSy4j26sOXWTmxjmOj3mrUM0NunCxd3ZryXJ81ZGkY8YYeARnz+G6i6wB1TouavUvNrl51cqR2ucQlMvdgcINwYZMaZmNaKSeF7mDPeUnvLESF6/KWEGHtiagBumYEP0qKBj9PrQB34pSRZe957SV7zO4Czdi+J0ndy17MXTVgoZveXPGVFyoODzB6I/O7byCG+3OYIR5P0u+leI25Lg2ZbOpCDq2YiR5iqSqQkeAueO5SLehMAKKU7LuEJbIQtdqJ1VIUc3FvtPp6FAkz4umE85TweQ101zGoVzmqGwA3osy1obzYkLvLmPoBqpXZwPWWk/rBmdqzmeKg+iEMNkUa/Mo8G+gbqXWC+PU2as7eBO+kRxerREIByWTBqIpYj2IpeTsfUkZi2WzB+e0mk4bmcr+SPrGRGEkuWEcjdiXTXf/uKMvqkE031PWhUrXVEKZXWJW89aKvL42ESfqeQUfCpEdGI3RV0VUHZ1VdWkB+YiJAYhrkE1KkfEulqoR26vEBp202eIYkqCkeWcaiYGTz2agpv8IOR4pGGs4Jyct3UjOYaMnxf3iu2sx/kbfUTj+XRgmtRuXmZOiad61oIGQsrglx4KgKaTZolu6JtLmaumItF2zPIkKQ2EXoq/rg0BxB4hPWCENhLcbPsbTuseJ5S8w2TPcBYRD/m3xmP6tlv0Qhmdrgqd1LfA8WawLhiL8pR54wNSsToBFRyK0aJ6mU4Iog9MSKvf7X5JGn1Y3QGN592XPiQPT31wQRRU0qB94GUx/CdZohiEDnnFbEJLO2YSm52IhLE1I3/mXlqm8lix+h0I1rr0zkOZFq19A83LtBmCMcy5urAeK0Xgyg== X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9249120b-70be-44dd-94a4-08dbda316687 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0302MB3486.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2023 16:49:51.2739 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OxwSUaRS2OkLiZnGwalwvQlJpBlKKXTkwTqyk1IaCAbI20eRX/FmNNtjy458wFlwrKmZi6hKk4CEcl9C+h7IpsXKeH1KbbHoNo09WUraji4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR03MB8706 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Burton In multi-cluster MIPS I6500 systems we have a GIC in each cluster, each with its own counter. When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems it has been fine for us to clear COUNTSTOP once in gic_clocksource_of_init() in order to start the counter, since with only one cluster we know that we won't be resetting that cluster's GIC at any point (ignoring suspend/resume cycles which would need to handle clearing COUNTSTOP in the resume path). Once we support multi-cluster systems this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo --- drivers/clocksource/mips-gic-timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index ebf308916fb1..4d7659c119e1 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -114,6 +114,9 @@ static void gic_update_frequency(void *data) static int gic_starting_cpu(unsigned int cpu) { + /* Ensure the GIC counter is running */ + clear_gic_config(GIC_CONFIG_COUNTSTOP); + gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); return 0; } @@ -284,9 +287,6 @@ static int __init gic_clocksource_of_init(struct device_node *node) pr_warn("Unable to register clock notifier\n"); } - /* And finally start the counter */ - clear_gic_config(GIC_CONFIG_COUNTSTOP); - /* * It's safe to use the MIPS GIC timer as a sched clock source only if * its ticks are stable, which is true on either the platforms with