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Thu, 2 May 2024 05:59:42 -0400 (EDT) From: Jiaxun Yang Date: Thu, 02 May 2024 10:59:33 +0100 Subject: [PATCH v3 6/9] MIPS: debug_ll: Implement support for Alchemy uarts Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240502-mips_debug_ll-v3-6-3b61f30e484c@flygoat.com> References: <20240502-mips_debug_ll-v3-0-3b61f30e484c@flygoat.com> In-Reply-To: <20240502-mips_debug_ll-v3-0-3b61f30e484c@flygoat.com> To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2825; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=dssAdswcFICvMOQneWOD2aRjHwqfi0CLy3Px0yTWsrA=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTjFHZ2AZXdC2Z9Te2ZGbej6vPVS46S926c3ZCxZdcyJ nbJFVm7OkpZGMQ4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAi7/8x/LO1Xe0Sdach+ozv FRWrwo3t+Yf5MlOi98T9kGu3n5/1zI+RYdsppQ/PkhS2xtQ6JaUy7dtlrXWQ++NrucdXRb+fNGV 6zwEA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Alchemy uart is a 8250 derivative that requires some special care on barriers and readys, also they have a wired register layout. Implement it as a special include. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig.debug | 10 +++++++++ arch/mips/include/debug/alchemy.S | 46 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 3609d298a9eb..aef116058654 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -257,11 +257,20 @@ choice Say Y here if you want kernel low-level debugging support on uart0 of Ingenic SoCs. + config DEBUG_ALCHEMY_UART + bool "Kernel low-level debugging messages via Alchemy UART" + depends on MIPS_ALCHEMY + select DEBUG_LL_UART + help + Say Y here if you want kernel low-level debugging support + on uart of alchemy SoCs. + endchoice config DEBUG_LL_INCLUDE string default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default "debug/alchemy.S" if DEBUG_ALCHEMY_UART default "debug/uhi.S" if DEBUG_MIPS_UHI default "debug-macro.S" @@ -293,6 +302,7 @@ config DEBUG_UART_PHYS default 0x1fd003f8 if DEBUG_LOONGSON3_UART default 0x1fe00000 if DEBUG_LOONGSON2K_UART default 0x10030000 if DEBUG_INGENIC_UART + default 0x11100000 if DEBUG_ALCHEMY_UART help This is the physical base address of the debug UART. It must be accessible from unmapped kernel space (i.e. KSEG1 for 32bit kernels diff --git a/arch/mips/include/debug/alchemy.S b/arch/mips/include/debug/alchemy.S new file mode 100644 index 000000000000..933efc6e828c --- /dev/null +++ b/arch/mips/include/debug/alchemy.S @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023, Jiaxun Yang + * MIPS Low level debug include file for Au1xxx UART + * Dereived from drivers/tty/serial/8250/8250_rt288x.c + */ + +#include +#include +#include + +#define DEBUG_LL_UART + +#define UART_BASE CKSEG1ADDR(CONFIG_DEBUG_UART_PHYS) + +#define UART_TX_OFS (1 << 2) +#define UART_LSR_OFS (7 << 2) + +# define UART_L lw +# define UART_S sw + + .macro addruart,rd,rx + PTR_LA \rd, UART_BASE + .endm + + .macro senduart,rd,rx + UART_S \rd, UART_TX_OFS(\rx) + sync /* wmb */ + .endm + + .macro busyuart,rd,rx +1002: + UART_L \rd, UART_LSR_OFS(\rx) + andi \rd, \rd, (UART_LSR_TEMT | UART_LSR_THRE) + xori \rd, (UART_LSR_TEMT | UART_LSR_THRE) + sync /* cpu_relax */ + bnez \rd, 1002b + .endm + + .macro waituarttxrdy,rd,rx + busyuart \rd, \rx + .endm + + /* Au1xxx has no MSR */ + .macro waituartcts,rd,rx + .endm