| Message ID | 20240511130349.23409-3-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | mips: bmips: improve handling of RAC and CBR addr | expand |
On Sat, 11 May 2024 15:03:46 +0200, Christian Marangi wrote: > Document brcm,bmips-cbr-reg property. > > Some SoC suffer from a BUG where CBR(Core Base Register) > address might be badly or never initialized by the Bootloader > or reading it from co-processor registers, if the system boots > from secondary CPU, results in invalid address. > > The CBR address is always the same on the SoC. > > Usage of this property is to give an address also in these broken > configuration/bootloader. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++ > 1 file changed, 24 insertions(+) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
On 5/11/2024 6:03 AM, Christian Marangi wrote: > Document brcm,bmips-cbr-reg property. > > Some SoC suffer from a BUG where CBR(Core Base Register) > address might be badly or never initialized by the Bootloader > or reading it from co-processor registers, if the system boots > from secondary CPU, results in invalid address. > > The CBR address is always the same on the SoC. > > Usage of this property is to give an address also in these broken > configuration/bootloader. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..0cc634482a6a 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,16 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where CBR(Core Base Register) + address might be badly or never initialized by the Bootloader + or reading it from co-processor registers, if the system boots + from secondary CPU, results in invalid address. + The CBR address is always the same on the SoC hence it + can be provided in DT to handle these broken case. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +74,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: