From patchwork Tue Mar 2 10:29:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aggarwal, Anuj" X-Patchwork-Id: 83168 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o22AU0jP021182 for ; Tue, 2 Mar 2010 10:30:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752086Ab0CBKaE (ORCPT ); Tue, 2 Mar 2010 05:30:04 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:48878 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751830Ab0CBKaD (ORCPT ); Tue, 2 Mar 2010 05:30:03 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o22ATsbj024786 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 2 Mar 2010 04:29:56 -0600 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o22ATr59028601; Tue, 2 Mar 2010 15:59:53 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o22ATru7003252; Tue, 2 Mar 2010 15:59:53 +0530 Received: (from a0393534@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o22ATrPi003249; Tue, 2 Mar 2010 15:59:53 +0530 From: Anuj Aggarwal To: tony@atomide.com Cc: linux-omap@vger.kernel.org, broonie@opensource.wolfsonmicro.com, lrg@slimlogic.co.uk, Anuj Aggarwal Subject: [PATCHv3 3/4] Regulator: OMAP: Kconfig modified to select TWL4030 for OMAP3-platforms Date: Tue, 2 Mar 2010 15:59:53 +0530 Message-Id: <1267525793-3220-1-git-send-email-anuj.aggarwal@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 02 Mar 2010 10:30:05 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1974dda..f58f321 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -57,6 +57,7 @@ config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB + select PMIC_TWL4030 config MACH_DEVKIT8000 bool "DEVKIT8000 board" @@ -66,16 +67,19 @@ config MACH_OMAP_LDP bool "OMAP3 LDP board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB + select PMIC_TWL4030 config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB + select PMIC_TWL4030 config MACH_OMAP3EVM bool "OMAP 3530 EVM board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB + select PMIC_TWL4030 config PMIC_TWL4030 bool "TWL4030/TPS65950 Power Module" @@ -100,11 +104,13 @@ config MACH_OMAP3_TOUCHBOOK bool "OMAP3 Touch Book" depends on ARCH_OMAP3 select BACKLIGHT_CLASS_DEVICE + select PMIC_TWL4030 config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB + select PMIC_TWL4030 config MACH_NOKIA_N800 bool @@ -131,27 +137,32 @@ config MACH_OMAP_ZOOM2 bool "OMAP3 Zoom2 board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB + select PMIC_TWL4030 config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBP + select PMIC_TWL4030 config MACH_CM_T35 bool "CompuLab CM-T35 module" depends on ARCH_OMAP3 select OMAP_PACKAGE_CUS select OMAP_MUX + select PMIC_TWL4030 config MACH_IGEP0020 bool "IGEP v2 board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB + select PMIC_TWL4030 config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" depends on ARCH_OMAP3 select OMAP_PACKAGE_CBP + select PMIC_TWL4030 config MACH_OMAP_4430SDP bool "OMAP 4430 SDP board" From patchwork Tue Mar 2 10:30:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aggarwal, Anuj" X-Patchwork-Id: 83169 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o22AUCsC021298 for ; Tue, 2 Mar 2010 10:30:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752237Ab0CBKaM (ORCPT ); Tue, 2 Mar 2010 05:30:12 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:38909 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752163Ab0CBKaK (ORCPT ); Tue, 2 Mar 2010 05:30:10 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o22AU1oQ025645 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 2 Mar 2010 04:30:03 -0600 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o22AU0GA028613; Tue, 2 Mar 2010 16:00:00 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o22AU09Y003311; Tue, 2 Mar 2010 16:00:00 +0530 Received: (from a0393534@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o22AU07E003308; Tue, 2 Mar 2010 16:00:00 +0530 From: Anuj Aggarwal To: tony@atomide.com Cc: linux-omap@vger.kernel.org, broonie@opensource.wolfsonmicro.com, lrg@slimlogic.co.uk, Anuj Aggarwal Subject: [PATCHv3 4/4] Regulator: OMAP: Use common regulator supplies and init data structs Date: Tue, 2 Mar 2010 16:00:00 +0530 Message-Id: <1267525800-3264-1-git-send-email-anuj.aggarwal@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 02 Mar 2010 10:30:13 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index f312b15..e414371 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -47,6 +47,7 @@ #include "sdram-qimonda-hyb18m512160af-6.h" #include "hsmmc.h" #include "pm.h" +#include "twl4030-pmic.h" #define CONFIG_DISABLE_HFCLK 1 @@ -365,18 +366,6 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct regulator_consumer_supply sdp3430_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply sdp3430_vsim_supply = { - .supply = "vmmc_aux", -}; - -static struct regulator_consumer_supply sdp3430_vmmc2_supply = { - .supply = "vmmc", -}; - static int sdp3430_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -390,9 +379,9 @@ static int sdp3430_twl_gpio_setup(struct device *dev, /* link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. */ - sdp3430_vmmc1_supply.dev = mmc[0].dev; - sdp3430_vsim_supply.dev = mmc[0].dev; - sdp3430_vmmc2_supply.dev = mmc[1].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; + twl4030_vsim_supply.dev = mmc[0].dev; + twl4030_vmmc2_supply.dev = mmc[1].dev; /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ gpio_request(gpio + 7, "sub_lcd_en_bkl"); @@ -422,108 +411,6 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = { .irq_line = 1, }; -/* - * Apply all the fixed voltages since most versions of U-Boot - * don't bother with that initialization. - */ - -/* VAUX1 for mainboard (irda and sub-lcd) */ -static struct regulator_init_data sdp3430_vaux1 = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - -/* VAUX2 for camera module */ -static struct regulator_init_data sdp3430_vaux2 = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - -/* VAUX3 for LCD board */ -static struct regulator_init_data sdp3430_vaux3 = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - -/* VAUX4 for OMAP VDD_CSI2 (camera) */ -static struct regulator_init_data sdp3430_vaux4 = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - -/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -static struct regulator_init_data sdp3430_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &sdp3430_vmmc1_supply, -}; - -/* VMMC2 for MMC2 card */ -static struct regulator_init_data sdp3430_vmmc2 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 1850000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &sdp3430_vmmc2_supply, -}; - -/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ -static struct regulator_init_data sdp3430_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &sdp3430_vsim_supply, -}; - /* VDAC for DSS driving S-Video */ static struct regulator_init_data sdp3430_vdac = { .constraints = { @@ -587,13 +474,13 @@ static struct twl4030_platform_data sdp3430_twldata = { .usb = &sdp3430_usb_data, .codec = &sdp3430_codec, - .vaux1 = &sdp3430_vaux1, - .vaux2 = &sdp3430_vaux2, - .vaux3 = &sdp3430_vaux3, - .vaux4 = &sdp3430_vaux4, - .vmmc1 = &sdp3430_vmmc1, - .vmmc2 = &sdp3430_vmmc2, - .vsim = &sdp3430_vsim, + .vaux1 = &twl4030_vaux1_data, + .vaux2 = &twl4030_vaux2_data, + .vaux3 = &twl4030_vaux3_data, + .vaux4 = &twl4030_vaux4_data, + .vmmc1 = &twl4030_vmmc1_data, + .vmmc2 = &twl4030_vmmc2_data, + .vsim = &twl4030_vsim_data, .vdac = &sdp3430_vdac, .vpll2 = &sdp3430_vpll2, }; diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index afa77ca..051c931 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -51,6 +51,7 @@ #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" +#include "twl4030-pmic.h" #define CM_T35_GPIO_PENDOWN 57 @@ -494,14 +495,6 @@ out: return; } -static struct regulator_consumer_supply cm_t35_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply cm_t35_vsim_supply = { - .supply = "vmmc_aux", -}; - static struct regulator_consumer_supply cm_t35_vdac_supply = { .supply = "vdda_dac", .dev = &cm_t35_dss_device.dev, @@ -512,36 +505,6 @@ static struct regulator_consumer_supply cm_t35_vdvi_supply = { .dev = &cm_t35_dss_device.dev, }; -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data cm_t35_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &cm_t35_vmmc1_supply, -}; - -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data cm_t35_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &cm_t35_vsim_supply, -}; - /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ static struct regulator_init_data cm_t35_vdac = { .constraints = { @@ -645,8 +608,8 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ - cm_t35_vmmc1_supply.dev = mmc[0].dev; - cm_t35_vsim_supply.dev = mmc[0].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; + twl4030_vsim_supply.dev = mmc[0].dev; /* setup USB with proper PHY reset GPIOs */ ehci_pdata.reset_gpio_port[0] = gpio + 6; @@ -672,8 +635,8 @@ static struct twl4030_platform_data cm_t35_twldata = { .keypad = &cm_t35_kp_data, .usb = &cm_t35_usb_data, .gpio = &cm_t35_gpio_data, - .vmmc1 = &cm_t35_vmmc1, - .vsim = &cm_t35_vsim, + .vmmc1 = &twl4030_vmmc1_data, + .vsim = &twl4030_vsim_data, .vdac = &cm_t35_vdac, .vpll2 = &cm_t35_vpll2, }; diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 9958987..514697c 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -35,6 +35,7 @@ #include "mux.h" #include "hsmmc.h" #include "sdram-numonyx-m65kxxxxam.h" +#include "twl4030-pmic.h" #define IGEP2_SMSC911X_CS 5 #define IGEP2_SMSC911X_GPIO 176 @@ -208,29 +209,10 @@ static inline void __init igep2_init_smsc911x(void) { } static struct omap_board_config_kernel igep2_config[] __initdata = { }; -static struct regulator_consumer_supply igep2_vmmc1_supply = { - .supply = "vmmc", -}; - static struct regulator_consumer_supply igep2_vmmc2_supply = { .supply = "vmmc", }; -/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -static struct regulator_init_data igep2_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &igep2_vmmc1_supply, -}; - /* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */ static struct regulator_init_data igep2_vmmc2 = { .constraints = { @@ -272,7 +254,7 @@ static int igep2_twl_gpio_setup(struct device *dev, /* link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. */ - igep2_vmmc1_supply.dev = mmc[0].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; igep2_vmmc2_supply.dev = mmc[1].dev; return 0; @@ -411,7 +393,7 @@ static struct twl4030_platform_data igep2_twldata = { .usb = &igep2_usb_data, .codec = &igep2_codec_data, .gpio = &igep2_gpio_data, - .vmmc1 = &igep2_vmmc1, + .vmmc1 = &twl4030_vmmc1_data, .vmmc2 = &igep2_vmmc2, .vpll2 = &igep2_vpll2, diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 5fcb52e..ed0154e 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -45,6 +45,7 @@ #include "mux.h" #include "hsmmc.h" +#include "twl4030-pmic.h" #define LDP_SMSC911X_CS 1 #define LDP_SMSC911X_GPIO 152 @@ -310,25 +311,6 @@ static struct twl4030_madc_platform_data ldp_madc_data = { .irq_line = 1, }; -static struct regulator_consumer_supply ldp_vmmc1_supply = { - .supply = "vmmc", -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data ldp_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &ldp_vmmc1_supply, -}; - static struct twl4030_platform_data ldp_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -336,7 +318,7 @@ static struct twl4030_platform_data ldp_twldata = { /* platform_data for children goes here */ .madc = &ldp_madc_data, .usb = &ldp_usb_data, - .vmmc1 = &ldp_vmmc1, + .vmmc1 = &twl4030_vmmc1_data, .gpio = &ldp_gpio_data, .keypad = &ldp_kp_twl4030_data, }; @@ -404,7 +386,7 @@ static void __init omap_ldp_init(void) omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ - ldp_vmmc1_supply.dev = mmc[0].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; } static void __init omap_ldp_map_io(void) diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 6eb77e1..464bd14 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -46,6 +46,7 @@ #include "mux.h" #include "hsmmc.h" +#include "twl4030-pmic.h" #define GPMC_CS0_BASE 0x60 #define GPMC_CS_SIZE 0x30 @@ -126,14 +127,6 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct regulator_consumer_supply beagle_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply beagle_vsim_supply = { - .supply = "vmmc_aux", -}; - static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, @@ -150,8 +143,8 @@ static int beagle_twl_gpio_setup(struct device *dev, omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ - beagle_vmmc1_supply.dev = mmc[0].dev; - beagle_vsim_supply.dev = mmc[0].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; + twl4030_vsim_supply.dev = mmc[0].dev; /* REVISIT: need ehci-omap hooks for external VBUS * power switch and overcurrent detect @@ -191,36 +184,6 @@ static struct regulator_consumer_supply beagle_vdvi_supply = { .dev = &omap3_beagle_lcd_device.dev, }; -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data beagle_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vmmc1_supply, -}; - -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data beagle_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vsim_supply, -}; - /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ static struct regulator_init_data beagle_vdac = { .constraints = { @@ -271,8 +234,8 @@ static struct twl4030_platform_data beagle_twldata = { .usb = &beagle_usb_data, .gpio = &beagle_gpio_data, .codec = &beagle_codec_data, - .vmmc1 = &beagle_vmmc1, - .vsim = &beagle_vsim, + .vmmc1 = &twl4030_vmmc1_data, + .vsim = &twl4030_vsim_data, .vdac = &beagle_vdac, .vpll2 = &beagle_vpll2, }; diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index d6bc88c..61fb896 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -46,6 +46,7 @@ #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" +#include "twl4030-pmic.h" #define OMAP3_EVM_TS_GPIO 175 #define OMAP3_EVM_EHCI_VBUS 22 @@ -329,44 +330,6 @@ static struct platform_device omap3_evm_dss_device = { }, }; -static struct regulator_consumer_supply omap3evm_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply omap3evm_vsim_supply = { - .supply = "vmmc_aux", -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data omap3evm_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3evm_vmmc1_supply, -}; - -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data omap3evm_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3evm_vsim_supply, -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -410,8 +373,8 @@ static int omap3evm_twl_gpio_setup(struct device *dev, omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ - omap3evm_vmmc1_supply.dev = mmc[0].dev; - omap3evm_vsim_supply.dev = mmc[0].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; + twl4030_vsim_supply.dev = mmc[0].dev; /* * Most GPIOs are for USB OTG. Some are mostly sent to @@ -563,8 +526,8 @@ static int __init omap3_evm_i2c_init(void) * REVISIT: These entries can be set in omap3evm_twl_data * after a merge with MFD tree */ - omap3evm_twldata.vmmc1 = &omap3evm_vmmc1; - omap3evm_twldata.vsim = &omap3evm_vsim; + omap3evm_twldata.vmmc1 = &twl4030_vmmc1_data; + omap3evm_twldata.vsim = &twl4030_vsim_data; omap_register_i2c_bus(1, 2600, omap3evm_i2c_boardinfo, ARRAY_SIZE(omap3evm_i2c_boardinfo)); diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 3943d0f..2388198 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -51,6 +51,7 @@ #include "mux.h" #include "hsmmc.h" +#include "twl4030-pmic.h" #include @@ -140,14 +141,6 @@ static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct regulator_consumer_supply touchbook_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply touchbook_vsim_supply = { - .supply = "vmmc_aux", -}; - static struct gpio_led gpio_leds[]; static int touchbook_twl_gpio_setup(struct device *dev, @@ -164,8 +157,8 @@ static int touchbook_twl_gpio_setup(struct device *dev, omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ - touchbook_vmmc1_supply.dev = mmc[0].dev; - touchbook_vsim_supply.dev = mmc[0].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; + twl4030_vsim_supply.dev = mmc[0].dev; /* REVISIT: need ehci-omap hooks for external VBUS * power switch and overcurrent detect @@ -205,36 +198,6 @@ static struct regulator_consumer_supply touchbook_vdvi_supply = { .dev = &omap3_touchbook_lcd_device.dev, }; -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data touchbook_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &touchbook_vmmc1_supply, -}; - -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data touchbook_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &touchbook_vsim_supply, -}; - /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ static struct regulator_init_data touchbook_vdac = { .constraints = { @@ -285,8 +248,8 @@ static struct twl4030_platform_data touchbook_twldata = { .usb = &touchbook_usb_data, .gpio = &touchbook_gpio_data, .codec = &touchbook_codec_data, - .vmmc1 = &touchbook_vmmc1, - .vsim = &touchbook_vsim, + .vmmc1 = &twl4030_vmmc1_data, + .vsim = &twl4030_vsim_data, .vdac = &touchbook_vdac, .vpll2 = &touchbook_vpll2, }; diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 50872a4..4707695 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -49,6 +49,7 @@ #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" +#include "twl4030-pmic.h" #define OVERO_GPIO_BT_XGATE 15 #define OVERO_GPIO_W2W_NRESET 16 @@ -290,16 +291,12 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct regulator_consumer_supply overo_vmmc1_supply = { - .supply = "vmmc", -}; - static int overo_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { omap2_hsmmc_init(mmc); - overo_vmmc1_supply.dev = mmc[0].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; return 0; } @@ -315,20 +312,6 @@ static struct twl4030_usb_data overo_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static struct regulator_init_data overo_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &overo_vmmc1_supply, -}; - static struct twl4030_codec_audio_data overo_audio_data = { .audio_mclk = 26000000, }; @@ -346,7 +329,7 @@ static struct twl4030_platform_data overo_twldata = { .gpio = &overo_gpio_data, .usb = &overo_usb_data, .codec = &overo_codec_data, - .vmmc1 = &overo_vmmc1, + .vmmc1 = &twl4030_vmmc1_data, }; static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index ca95d8d..3796a92 100755 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -26,6 +26,7 @@ #include "mux.h" #include "hsmmc.h" +#include "twl4030-pmic.h" /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { @@ -94,63 +95,6 @@ static struct twl4030_keypad_data zoom_kp_twl4030_data = { .rep = 1, }; -static struct regulator_consumer_supply zoom_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply zoom_vsim_supply = { - .supply = "vmmc_aux", -}; - -static struct regulator_consumer_supply zoom_vmmc2_supply = { - .supply = "vmmc", -}; - -/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -static struct regulator_init_data zoom_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &zoom_vmmc1_supply, -}; - -/* VMMC2 for MMC2 card */ -static struct regulator_init_data zoom_vmmc2 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 1850000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &zoom_vmmc2_supply, -}; - -/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ -static struct regulator_init_data zoom_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &zoom_vsim_supply, -}; - static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -181,9 +125,9 @@ static int zoom_twl_gpio_setup(struct device *dev, /* link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. */ - zoom_vmmc1_supply.dev = mmc[0].dev; - zoom_vsim_supply.dev = mmc[0].dev; - zoom_vmmc2_supply.dev = mmc[1].dev; + twl4030_vmmc1_supply.dev = mmc[0].dev; + twl4030_vsim_supply.dev = mmc[0].dev; + twl4030_vmmc2_supply.dev = mmc[1].dev; return 0; } @@ -240,10 +184,9 @@ static struct twl4030_platform_data zoom_twldata = { .gpio = &zoom_gpio_data, .keypad = &zoom_kp_twl4030_data, .codec = &zoom_codec_data, - .vmmc1 = &zoom_vmmc1, - .vmmc2 = &zoom_vmmc2, - .vsim = &zoom_vsim, - + .vmmc1 = &twl4030_vmmc1_data, + .vmmc2 = &twl4030_vmmc2_data, + .vsim = &twl4030_vsim_data, }; static struct i2c_board_info __initdata zoom_i2c_boardinfo[] = { From patchwork Thu Jul 1 00:20:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 108994 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o610EpL3017660 for ; Thu, 1 Jul 2010 00:14:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932236Ab0GAANl (ORCPT ); Wed, 30 Jun 2010 20:13:41 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:38022 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756030Ab0GAALl (ORCPT ); Wed, 30 Jun 2010 20:11:41 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o610BcL6019821 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 30 Jun 2010 19:11:39 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o610BcZ4010933; Wed, 30 Jun 2010 19:11:38 -0500 (CDT) Received: from localhost (x0095840-desktop.am.dhcp.ti.com [128.247.77.44]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o610BcP08746; Wed, 30 Jun 2010 19:11:38 -0500 (CDT) From: Fernando Guzman Lugo To: , Cc: , , , , Fernando Guzman Lugo Subject: [PATCH 2/9] dspbridge: move shared memory iommu maps to tiomap3430.c Date: Wed, 30 Jun 2010 19:20:53 -0500 Message-Id: <1277943660-4112-3-git-send-email-x0095840@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277943660-4112-2-git-send-email-x0095840@ti.com> References: <1277943660-4112-1-git-send-email-x0095840@ti.com> <1277943660-4112-2-git-send-email-x0095840@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 00:14:53 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/_tiomap.h b/drivers/dsp/bridge/core/_tiomap.h index d13677a..6a822c6 100644 --- a/drivers/dsp/bridge/core/_tiomap.h +++ b/drivers/dsp/bridge/core/_tiomap.h @@ -310,6 +310,11 @@ static const struct bpwr_clk_t bpwr_clks[] = { #define CLEAR_BIT_INDEX(reg, index) (reg &= ~(1 << (index))) +struct shm_segs { + u32 seg0_da, seg0_pa, seg0_va, seg0_size; + u32 seg1_da, seg1_pa, seg1_va, seg1_size; +}; + /* This Bridge driver's device context: */ struct bridge_dev_context { struct dev_object *hdev_obj; /* Handle to Bridge device object. */ @@ -333,6 +338,7 @@ struct bridge_dev_context { struct omap_mbox *mbox; /* Mail box handle */ struct iommu *dsp_mmu; /* iommu for iva2 handler */ + struct shm_segs *sh_s; struct cfg_hostres *resources; /* Host Resources */ diff --git a/drivers/dsp/bridge/core/io_sm.c b/drivers/dsp/bridge/core/io_sm.c index 1f47f8b..aca9854 100644 --- a/drivers/dsp/bridge/core/io_sm.c +++ b/drivers/dsp/bridge/core/io_sm.c @@ -290,8 +290,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) struct cod_manager *cod_man; struct chnl_mgr *hchnl_mgr; struct msg_mgr *hmsg_mgr; - struct iommu *mmu; - struct iotlb_entry e; + struct shm_segs *sm_sg; u32 ul_shm_base; u32 ul_shm_base_offset; u32 ul_shm_limit; @@ -317,14 +316,6 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) u32 shm0_end; u32 ul_dyn_ext_base; u32 ul_seg1_size = 0; - u32 pa_curr = 0; - u32 va_curr = 0; - u32 gpp_va_curr = 0; - u32 num_bytes = 0; - u32 all_bits = 0; - u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB, - HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB - }; status = dev_get_bridge_context(hio_mgr->hdev_obj, &pbridge_context); if (!pbridge_context) { @@ -338,19 +329,12 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) goto func_end; } - mmu = pbridge_context->dsp_mmu; + sm_sg = kmalloc(sizeof(*sm_sg), GFP_KERNEL); - if (mmu) - iommu_put(mmu); - mmu = iommu_get("iva2"); - - if (IS_ERR_OR_NULL(mmu)) { - pr_err("Error in iommu_get\n"); - pbridge_context->dsp_mmu = NULL; - status = -EFAULT; + if (!sm_sg) { + status = -ENOMEM; goto func_end; } - pbridge_context->dsp_mmu = mmu; status = dev_get_cod_mgr(hio_mgr->hdev_obj, &cod_man); if (!cod_man) { @@ -488,74 +472,16 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) if (DSP_FAILED(status)) goto func_end; - pa_curr = ul_gpp_pa; - va_curr = ul_dyn_ext_base * hio_mgr->word_size; - gpp_va_curr = ul_gpp_va; - num_bytes = ul_seg1_size; + sm_sg->seg1_pa = ul_gpp_pa; + sm_sg->seg1_da = ul_dyn_ext_base; + sm_sg->seg1_va = ul_gpp_va; + sm_sg->seg1_size = ul_seg1_size; + sm_sg->seg0_pa = ul_gpp_pa + ul_pad_size + ul_seg1_size; + sm_sg->seg0_da = ul_dsp_va; + sm_sg->seg0_va = ul_gpp_va + ul_pad_size + ul_seg1_size; + sm_sg->seg0_size = ul_seg_size; - va_curr = iommu_kmap(mmu, va_curr, pa_curr, num_bytes, - IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32); - if (IS_ERR_VALUE(va_curr)) { - status = (int)va_curr; - goto func_end; - } - - pa_curr += ul_pad_size + num_bytes; - va_curr += ul_pad_size + num_bytes; - gpp_va_curr += ul_pad_size + num_bytes; - - /* Configure the TLB entries for the next cacheable segment */ - num_bytes = ul_seg_size; - va_curr = ul_dsp_va * hio_mgr->word_size; - while (num_bytes) { - /* - * To find the max. page size with which both PA & VA are - * aligned. - */ - all_bits = pa_curr | va_curr; - dev_dbg(bridge, "all_bits for Seg1 %x, pa_curr %x, " - "va_curr %x, num_bytes %x\n", all_bits, pa_curr, - va_curr, num_bytes); - for (i = 0; i < 4; i++) { - if (!(num_bytes >= page_size[i]) || - !((all_bits & (page_size[i] - 1)) == 0)) - continue; - if (ndx < MAX_LOCK_TLB_ENTRIES) { - /* - * This is the physical address written to - * DSP MMU. - */ - ae_proc[ndx].ul_gpp_pa = pa_curr; - /* - * This is the virtual uncached ioremapped - * address!!! - */ - ae_proc[ndx].ul_gpp_va = gpp_va_curr; - ae_proc[ndx].ul_dsp_va = - va_curr / hio_mgr->word_size; - ae_proc[ndx].ul_size = page_size[i]; - ae_proc[ndx].endianism = HW_LITTLE_ENDIAN; - ae_proc[ndx].elem_size = HW_ELEM_SIZE16BIT; - ae_proc[ndx].mixed_mode = HW_MMU_CPUES; - dev_dbg(bridge, "shm MMU TLB entry PA %x" - " VA %x DSP_VA %x Size %x\n", - ae_proc[ndx].ul_gpp_pa, - ae_proc[ndx].ul_gpp_va, - ae_proc[ndx].ul_dsp_va * - hio_mgr->word_size, page_size[i]); - ndx++; - } - pa_curr += page_size[i]; - va_curr += page_size[i]; - gpp_va_curr += page_size[i]; - num_bytes -= page_size[i]; - /* - * Don't try smaller sizes. Hopefully we have reached - * an address aligned to a bigger page size. - */ - break; - } - } + pbridge_context->sh_s = sm_sg; /* * Copy remaining entries from CDB. All entries are 1 MB and @@ -602,17 +528,6 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) goto func_end; } - dsp_iotlb_init(&e, 0, 0, IOVMF_PGSZ_4K); - - /* Map the L4 peripherals */ - i = 0; - while (l4_peripheral_table[i].phys_addr) { - e.da = l4_peripheral_table[i].dsp_virt_addr; - e.pa = l4_peripheral_table[i].phys_addr; - iopgtable_store_entry(mmu, &e); - i++; - } - for (i = ndx; i < BRDIOCTL_NUMOFMMUTLB; i++) { ae_proc[i].ul_dsp_va = 0; ae_proc[i].ul_gpp_pa = 0; @@ -635,12 +550,12 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) status = -EFAULT; goto func_end; } else { - if (ae_proc[0].ul_dsp_va > ul_shm_base) { + if (sm_sg->seg0_da > ul_shm_base) { status = -EPERM; goto func_end; } /* ul_shm_base may not be at ul_dsp_va address */ - ul_shm_base_offset = (ul_shm_base - ae_proc[0].ul_dsp_va) * + ul_shm_base_offset = (ul_shm_base - sm_sg->seg0_da) * hio_mgr->word_size; /* * bridge_dev_ctrl() will set dev context dsp-mmu info. In @@ -665,7 +580,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) } /* Register SM */ status = - register_shm_segs(hio_mgr, cod_man, ae_proc[0].ul_gpp_pa); + register_shm_segs(hio_mgr, cod_man, sm_sg->seg0_pa); } hio_mgr->shared_mem = (struct shm *)ul_shm_base; diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index e750767..89d4936 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -300,8 +300,7 @@ static int bridge_brd_monitor(struct bridge_dev_context *hDevContext) (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, OMAP3430_IVA2_MOD, CM_CLKSTCTRL); } - (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, 0, - OMAP3430_IVA2_MOD, RM_RSTCTRL); + dsp_clk_enable(DSP_CLK_IVA2); if (DSP_SUCCEEDED(status)) { @@ -374,15 +373,16 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, int status = 0; struct bridge_dev_context *dev_context = hDevContext; struct iommu *mmu; - struct iotlb_entry en; + struct iotlb_entry e; + struct shm_segs *sm_sg; + int i; + struct bridge_ioctl_extproc *tlb = dev_context->atlb_entry; u32 dw_sync_addr = 0; u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */ u32 ul_shm_base_virt; /* Dsp Virt SM base addr */ u32 ul_tlb_base_virt; /* Base of MMU TLB entry */ /* Offset of shm_base_virt from tlb_base_virt */ u32 ul_shm_offset_virt; - s32 entry_ndx; - s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */ struct cfg_hostres *resources = NULL; u32 temp; u32 ul_dsp_clk_rate; @@ -394,8 +394,6 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; - mmu = dev_context->dsp_mmu; - /* The device context contains all the mmu setup info from when the * last dsp base image was loaded. The first entry is always * SHMMEM base. */ @@ -405,12 +403,12 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, ul_shm_base_virt *= DSPWORDSIZE; DBC_ASSERT(ul_shm_base_virt != 0); /* DSP Virtual address */ - ul_tlb_base_virt = dev_context->atlb_entry[0].ul_dsp_va; + ul_tlb_base_virt = dev_context->sh_s->seg0_da; DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt); ul_shm_offset_virt = ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE); /* Kernel logical address */ - ul_shm_base = dev_context->atlb_entry[0].ul_gpp_va + ul_shm_offset_virt; + ul_shm_base = dev_context->sh_s->seg0_va + ul_shm_offset_virt; DBC_ASSERT(ul_shm_base != 0); /* 2nd wd is used as sync field */ @@ -445,152 +443,193 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, OMAP343X_CONTROL_IVA2_BOOTMOD)); } } - if (DSP_SUCCEEDED(status)) { - /* Only make TLB entry if both addresses are non-zero */ - for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; - entry_ndx++) { - struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx]; - if (!e->ul_gpp_pa || !e->ul_dsp_va) - continue; - - dev_dbg(bridge, - "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x", - itmp_entry_ndx, - e->ul_gpp_pa, - e->ul_dsp_va, - e->ul_size); - - dsp_iotlb_init(&en, e->ul_dsp_va, e->ul_gpp_pa, - bytes_to_iopgsz(e->ul_size)); - iopgtable_store_entry(mmu, &en); - itmp_entry_ndx++; - } + + if (status) + goto err1; + + (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, 0, + OMAP3430_IVA2_MOD, RM_RSTCTRL); + + mmu = dev_context->dsp_mmu; + + if (mmu) + iommu_put(mmu); + mmu = iommu_get("iva2"); + + if (IS_ERR(mmu)) { + pr_err("Error in iommu_get %ld\n", PTR_ERR(mmu)); + dev_context->dsp_mmu = NULL; + status = (int)mmu; + goto end; } + dev_context->dsp_mmu = mmu; + sm_sg = dev_context->sh_s; - /* Lock the above TLB entries and get the BIOS and load monitor timer - * information */ - if (DSP_SUCCEEDED(status)) { + sm_sg->seg0_da = iommu_kmap(mmu, sm_sg->seg0_da, sm_sg->seg0_pa, + sm_sg->seg0_size, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32); - /* Enable the BIOS clock */ - (void)dev_get_symbol(dev_context->hdev_obj, - BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer); - (void)dev_get_symbol(dev_context->hdev_obj, - BRIDGEINIT_LOADMON_GPTIMER, - &ul_load_monitor_timer); - if (ul_load_monitor_timer != 0xFFFF) { - clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) | - ul_load_monitor_timer; - dsp_peripheral_clk_ctrl(dev_context, &clk_cmd); - } else { - dev_dbg(bridge, "Not able to get the symbol for Load " - "Monitor Timer\n"); - } + if (IS_ERR_VALUE(sm_sg->seg0_da)) { + status = (int)sm_sg->seg0_da; + goto err1; } - if (DSP_SUCCEEDED(status)) { - if (ul_bios_gp_timer != 0xFFFF) { - clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) | - ul_bios_gp_timer; - dsp_peripheral_clk_ctrl(dev_context, &clk_cmd); - } else { - dev_dbg(bridge, - "Not able to get the symbol for BIOS Timer\n"); - } + sm_sg->seg1_da = iommu_kmap(mmu, sm_sg->seg1_da, sm_sg->seg1_pa, + sm_sg->seg1_size, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32); + + if (IS_ERR_VALUE(sm_sg->seg1_da)) { + iommu_kunmap(mmu, sm_sg->seg0_da); + status = (int)sm_sg->seg1_da; + goto err2; } - if (DSP_SUCCEEDED(status)) { - /* Set the DSP clock rate */ - (void)dev_get_symbol(dev_context->hdev_obj, - "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr); - /*Set Autoidle Mode for IVA2 PLL */ - (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, - OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL); - - if ((unsigned int *)ul_dsp_clk_addr != NULL) { - /* Get the clock rate */ - ul_dsp_clk_rate = dsp_clk_get_iva2_rate(); - dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n", - __func__, ul_dsp_clk_rate); - (void)bridge_brd_write(dev_context, - (u8 *) &ul_dsp_clk_rate, - ul_dsp_clk_addr, sizeof(u32), 0); - } - /* - * Enable Mailbox events and also drain any pending - * stale messages. - */ - dev_context->mbox = omap_mbox_get("dsp"); - if (IS_ERR(dev_context->mbox)) { - dev_context->mbox = NULL; - pr_err("%s: Failed to get dsp mailbox handle\n", - __func__); - status = -EPERM; - } + dsp_iotlb_init(&e, 0, 0, IOVMF_PGSZ_4K); + /* Map the L4 peripherals */ + i = 0; + while (l4_peripheral_table[i].phys_addr) { + e.da = l4_peripheral_table[i].dsp_virt_addr; + e.pa = l4_peripheral_table[i].phys_addr; + iopgtable_store_entry(mmu, &e); + i++; + } + + for (i = 0; i < BRDIOCTL_NUMOFMMUTLB; i++) { + if (!tlb[i].ul_gpp_pa) + continue; + + dev_dbg(bridge, "(proc) MMU %d GppPa: 0x%x DspVa 0x%x Size" + " 0x%x\n", i, tlb[i].ul_gpp_pa, tlb[i].ul_dsp_va, + tlb[i].ul_size); + + dsp_iotlb_init(&e, tlb[i].ul_dsp_va, tlb[i].ul_gpp_pa, + bytes_to_iopgsz(tlb[i].ul_size)); + iopgtable_store_entry(mmu, &e); } - if (DSP_SUCCEEDED(status)) { - dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg; + + /* Get the BIOS and load monitor timer information */ + /* Enable the BIOS clock */ + (void)dev_get_symbol(dev_context->hdev_obj, + BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer); + (void)dev_get_symbol(dev_context->hdev_obj, + BRIDGEINIT_LOADMON_GPTIMER, + &ul_load_monitor_timer); + if (ul_load_monitor_timer != 0xFFFF) { + clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) | + ul_load_monitor_timer; + dsp_peripheral_clk_ctrl(dev_context, &clk_cmd); + } else { + dev_dbg(bridge, "Not able to get the symbol for Load " + "Monitor Timer\n"); + } + + if (ul_bios_gp_timer != 0xFFFF) { + clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) | + ul_bios_gp_timer; + dsp_peripheral_clk_ctrl(dev_context, &clk_cmd); + } else { + dev_dbg(bridge, + "Not able to get the symbol for BIOS Timer\n"); + } + + /* Set the DSP clock rate */ + (void)dev_get_symbol(dev_context->hdev_obj, + "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr); + /*Set Autoidle Mode for IVA2 PLL */ + (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, + OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL); + + if ((unsigned int *)ul_dsp_clk_addr != NULL) { + /* Get the clock rate */ + ul_dsp_clk_rate = dsp_clk_get_iva2_rate(); + dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n", + __func__, ul_dsp_clk_rate); + (void)bridge_brd_write(dev_context, + (u8 *) &ul_dsp_clk_rate, + ul_dsp_clk_addr, sizeof(u32), 0); + } + /* + * Enable Mailbox events and also drain any pending + * stale messages. + */ + dev_context->mbox = omap_mbox_get("dsp"); + if (IS_ERR(dev_context->mbox)) { + dev_context->mbox = NULL; + pr_err("%s: Failed to get dsp mailbox handle\n", __func__); + status = -EPERM; + goto err3; + } + + dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg; /*PM_IVA2GRPSEL_PER = 0xC0;*/ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA8)); - temp = (temp & 0xFFFFFF30) | 0xC0; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) = - (u32) temp; + temp = (u32) *((reg_uword32 *) + ((u32) (resources->dw_per_pm_base) + 0xA8)); + temp = (temp & 0xFFFFFF30) | 0xC0; + *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) = + (u32) temp; /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA4)); - temp = (temp & 0xFFFFFF3F); - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) = - (u32) temp; + temp = (u32) *((reg_uword32 *) + ((u32) (resources->dw_per_pm_base) + 0xA4)); + temp = (temp & 0xFFFFFF3F); + *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) = + (u32) temp; /*CM_SLEEPDEP_PER |= 0x04; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_base) + 0x44)); - temp = (temp & 0xFFFFFFFB) | 0x04; - *((reg_uword32 *) ((u32) (resources->dw_per_base) + 0x44)) = - (u32) temp; + temp = (u32) *((reg_uword32 *) + ((u32) (resources->dw_per_base) + 0x44)); + temp = (temp & 0xFFFFFFFB) | 0x04; + *((reg_uword32 *) ((u32) (resources->dw_per_base) + 0x44)) = + (u32) temp; /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */ - (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, - OMAP3430_IVA2_MOD, CM_CLKSTCTRL); - - /* Let DSP go */ - dev_dbg(bridge, "%s Unreset\n", __func__); - /* release the RST1, DSP starts executing now .. */ - (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, 0, - OMAP3430_IVA2_MOD, RM_RSTCTRL); - - dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr); - dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dwDSPAddr); - if (dsp_debug) - while (*((volatile u16 *)dw_sync_addr)) - ;; - - /* Wait for DSP to clear word in shared memory */ - /* Read the Location */ - if (!wait_for_start(dev_context, dw_sync_addr)) - status = -ETIMEDOUT; + (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, + OMAP3430_IVA2_MOD, CM_CLKSTCTRL); + + /* Let DSP go */ + dev_dbg(bridge, "%s Unreset\n", __func__); + /* release the RST1, DSP starts executing now .. */ + (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, 0, + OMAP3430_IVA2_MOD, RM_RSTCTRL); + + dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr); + dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dwDSPAddr); + if (dsp_debug) + while (*((volatile u16 *)dw_sync_addr)) + ;; + + /* Wait for DSP to clear word in shared memory */ + /* Read the Location */ + if (!wait_for_start(dev_context, dw_sync_addr)) { + status = -ETIMEDOUT; + goto err3; + } - /* Start wdt */ - dsp_wdt_sm_set((void *)ul_shm_base); - dsp_wdt_enable(true); + /* Start wdt */ + dsp_wdt_sm_set((void *)ul_shm_base); + dsp_wdt_enable(true); - status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr); - if (hio_mgr) { - io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL); - /* Write the synchronization bit to indicate the - * completion of OPP table update to DSP - */ - *((volatile u32 *)dw_sync_addr) = 0XCAFECAFE; + status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr); + if (hio_mgr) { + io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL); + /* Write the synchronization bit to indicate the + * completion of OPP table update to DSP + */ + *((volatile u32 *)dw_sync_addr) = 0XCAFECAFE; - /* update board state */ - dev_context->dw_brd_state = BRD_RUNNING; - /* (void)chnlsm_enable_interrupt(dev_context); */ - } else { - dev_context->dw_brd_state = BRD_UNKNOWN; - } + /* update board state */ + dev_context->dw_brd_state = BRD_RUNNING; + /* (void)chnlsm_enable_interrupt(dev_context); */ + } else { + dev_context->dw_brd_state = BRD_UNKNOWN; + goto err3; } +end: + return 0; +err3: + iommu_kunmap(mmu, sm_sg->seg0_da); +err2: + iommu_kunmap(mmu, sm_sg->seg1_da); +err1: return status; } @@ -654,15 +693,30 @@ static int bridge_brd_stop(struct bridge_dev_context *hDevContext) memset((u8 *) pt_attrs->pg_info, 0x00, (pt_attrs->l2_num_pages * sizeof(struct page_info))); } + + /* Reset DSP */ + (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, OMAP3430_RST1_IVA2, + OMAP3430_IVA2_MOD, RM_RSTCTRL); /* Disable the mailbox interrupts */ if (dev_context->mbox) { omap_mbox_disable_irq(dev_context->mbox, IRQ_RX); omap_mbox_put(dev_context->mbox); dev_context->mbox = NULL; } - /* Reset IVA2 clocks*/ - (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2 | OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); + + if (dev_context->dsp_mmu) { + if (dev_context->sh_s) { + iommu_kunmap(dev_context->dsp_mmu, + dev_context->sh_s->seg0_da); + iommu_kunmap(dev_context->dsp_mmu, + dev_context->sh_s->seg1_da); + } + iommu_put(dev_context->dsp_mmu); + dev_context->dsp_mmu = NULL; + } + + (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, OMAP3430_RST2_IVA2, + OMAP3430_IVA2_MOD, RM_RSTCTRL); return status; } @@ -709,6 +763,11 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) memset((u8 *) pt_attrs->pg_info, 0x00, (pt_attrs->l2_num_pages * sizeof(struct page_info))); } + + /* Reset DSP */ + (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, OMAP3430_RST1_IVA2, + OMAP3430_IVA2_MOD, RM_RSTCTRL); + /* Disable the mail box interrupts */ if (dev_context->mbox) { omap_mbox_disable_irq(dev_context->mbox, IRQ_RX); @@ -716,11 +775,19 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) dev_context->mbox = NULL; } - if (dev_context->dsp_mmu) - dev_context->dsp_mmu = (iommu_put(dev_context->dsp_mmu), NULL); - /* Reset IVA2 clocks*/ - (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2 | OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); + if (dev_context->dsp_mmu) { + if (dev_context->sh_s) { + iommu_kunmap(dev_context->dsp_mmu, + dev_context->sh_s->seg0_da); + iommu_kunmap(dev_context->dsp_mmu, + dev_context->sh_s->seg1_da); + } + iommu_put(dev_context->dsp_mmu); + dev_context->dsp_mmu = NULL; + } + + (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, OMAP3430_RST2_IVA2, + OMAP3430_IVA2_MOD, RM_RSTCTRL); return status; } diff --git a/drivers/dsp/bridge/core/tiomap_io.c b/drivers/dsp/bridge/core/tiomap_io.c index 3b2ea70..c23ca66 100644 --- a/drivers/dsp/bridge/core/tiomap_io.c +++ b/drivers/dsp/bridge/core/tiomap_io.c @@ -133,10 +133,9 @@ int read_ext_dsp_data(struct bridge_dev_context *hDevContext, if (DSP_SUCCEEDED(status)) { ul_tlb_base_virt = - dev_context->atlb_entry[0].ul_dsp_va * DSPWORDSIZE; + dev_context->sh_s->seg0_da * DSPWORDSIZE; DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt); - dw_ext_prog_virt_mem = - dev_context->atlb_entry[0].ul_gpp_va; + dw_ext_prog_virt_mem = dev_context->sh_s->seg0_va; if (!trace_read) { ul_shm_offset_virt = @@ -317,8 +316,8 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context, ret = -EPERM; if (DSP_SUCCEEDED(ret)) { - ul_tlb_base_virt = - dev_context->atlb_entry[0].ul_dsp_va * DSPWORDSIZE; + ul_tlb_base_virt = dev_context->sh_s->seg0_da * + DSPWORDSIZE; DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt); if (symbols_reloaded) { @@ -339,7 +338,7 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context, ul_shm_base_virt - ul_tlb_base_virt; if (trace_load) { dw_ext_prog_virt_mem = - dev_context->atlb_entry[0].ul_gpp_va; + dev_context->sh_s->seg0_va; } else { dw_ext_prog_virt_mem = host_res->dw_mem_base[1]; dw_ext_prog_virt_mem += From patchwork Wed Mar 24 13:00:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkatraman S X-Patchwork-Id: 87916 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2OD0utt020278 for ; Wed, 24 Mar 2010 13:00:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756130Ab0CXNAz (ORCPT ); Wed, 24 Mar 2010 09:00:55 -0400 Received: from mail-iw0-f176.google.com ([209.85.223.176]:59707 "EHLO mail-iw0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756004Ab0CXNAx (ORCPT ); Wed, 24 Mar 2010 09:00:53 -0400 Received: by iwn6 with SMTP id 6so2639241iwn.4 for ; Wed, 24 Mar 2010 06:00:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=hdzOhRYveCwXvJonTSmeLN0NjZzgdxSBwZYBaZvO6a4=; b=qE2sdEmVWdQLvf/+WBGcwyQLpsS5ZXthenEObozcKuj7qbxCPJUGGpicvwy5ygJNIT 5i1mgpPVgXzTsnzkw973qI5R7RCn5s58KIPFOtKS8jvxmGBni+EO+ccznG+1iC95p+Mg ggqeQRuaBEf8Ec8DfGyjV2+P4yRw+FZbAgLw4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type; b=CMILB3BxCVb0m4p/7HNivamB658Pkck/HoP1u+qw5Z/aV/xkV/oi6lAolqvPPhYWZk 94wOVeXF5RyANO0SJIPzP+C0zN5LNcnJ0nhR1Kc88oKLB4EFkD5xM+iA7gHpRKw5sygh zIwYh/Kgb7VpLHXy55w8r8amb0KfDYImbYnq8= MIME-Version: 1.0 Received: by 10.231.167.208 with SMTP id r16mr634475iby.57.1269435652818; Wed, 24 Mar 2010 06:00:52 -0700 (PDT) Date: Wed, 24 Mar 2010 18:30:52 +0530 X-Google-Sender-Auth: bd99a180967a8c56 Message-ID: <618f0c911003240600m1a38935av68f31a232ed8b8ad@mail.gmail.com> Subject: [PATCH] mmc: fix race condition between dma and omap_hsmmc callback From: Venkatraman S To: linux-omap@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Adrian Hunter , Madhusudhan Chikkature , Tony Lindgren Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 24 Mar 2010 13:00:57 +0000 (UTC) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 83f0aff..9a70b36 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -1046,8 +1046,18 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) if (end_cmd || ((status & CC) && host->cmd)) omap_hsmmc_cmd_done(host, host->cmd); - if ((end_trans || (status & TC)) && host->mrq) + if ((end_trans || (status & TC)) && host->mrq) { + if (host->dma_ch != -1) { + omap_free_dma(host->dma_ch); + host->dma_ch = -1; + /* + * Callback run in interrupt context. + * mutex_unlock will throw a kernel warning if used. + */ + up(&host->sem); + } omap_hsmmc_xfer_done(host, data); + } spin_unlock(&host->irq_lock); @@ -1267,13 +1277,6 @@ static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data) return; } - omap_free_dma(host->dma_ch); - host->dma_ch = -1; - /* - * DMA Callback: run in interrupt context. - * mutex_unlock will throw a kernel warning if used. - */ - up(&host->sem); } From patchwork Thu Jul 1 00:20:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 108992 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o610DYa7017455 for ; Thu, 1 Jul 2010 00:13:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932341Ab0GAANE (ORCPT ); Wed, 30 Jun 2010 20:13:04 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:48434 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757534Ab0GAALm (ORCPT ); Wed, 30 Jun 2010 20:11:42 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o610Be8Y012516 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 30 Jun 2010 19:11:40 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o610BdUN010941; Wed, 30 Jun 2010 19:11:39 -0500 (CDT) Received: from localhost (x0095840-desktop.am.dhcp.ti.com [128.247.77.44]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o610BdP08762; Wed, 30 Jun 2010 19:11:39 -0500 (CDT) From: Fernando Guzman Lugo To: , Cc: , , , , Fernando Guzman Lugo Subject: [PATCH 6/9] dspbridge: remove hw directory Date: Wed, 30 Jun 2010 19:20:57 -0500 Message-Id: <1277943660-4112-7-git-send-email-x0095840@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277943660-4112-6-git-send-email-x0095840@ti.com> References: <1277943660-4112-1-git-send-email-x0095840@ti.com> <1277943660-4112-2-git-send-email-x0095840@ti.com> <1277943660-4112-3-git-send-email-x0095840@ti.com> <1277943660-4112-4-git-send-email-x0095840@ti.com> <1277943660-4112-5-git-send-email-x0095840@ti.com> <1277943660-4112-6-git-send-email-x0095840@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 00:13:36 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/dspioctl.h b/arch/arm/plat-omap/include/dspbridge/dspioctl.h index 41e0594..bad1801 100644 --- a/arch/arm/plat-omap/include/dspbridge/dspioctl.h +++ b/arch/arm/plat-omap/include/dspbridge/dspioctl.h @@ -19,10 +19,6 @@ #ifndef DSPIOCTL_ #define DSPIOCTL_ -/* ------------------------------------ Hardware Abstraction Layer */ -#include -#include - /* * Any IOCTLS at or above this value are reserved for standard Bridge driver * interfaces. @@ -65,9 +61,6 @@ struct bridge_ioctl_extproc { /* GPP virtual address. __va does not work for ioremapped addresses */ u32 ul_gpp_va; u32 ul_size; /* Size of the mapped memory in bytes */ - enum hw_endianism_t endianism; - enum hw_mmu_mixed_size_t mixed_mode; - enum hw_element_size_t elem_size; }; #endif /* DSPIOCTL_ */ diff --git a/drivers/dsp/bridge/Makefile b/drivers/dsp/bridge/Makefile index 4c2f923..66ca10a 100644 --- a/drivers/dsp/bridge/Makefile +++ b/drivers/dsp/bridge/Makefile @@ -13,10 +13,9 @@ librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \ rmgr/nldr.o rmgr/drv_interface.o libdload = dynload/cload.o dynload/getsection.o dynload/reloc.o \ dynload/tramp.o -libhw = hw/hw_mmu.o bridgedriver-objs = $(libgen) $(libservices) $(libcore) $(libpmgr) $(librmgr) \ - $(libdload) $(libhw) + $(libdload) #Machine dependent ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \ diff --git a/drivers/dsp/bridge/core/_tiomap.h b/drivers/dsp/bridge/core/_tiomap.h index c41fd8e..35f20a7 100644 --- a/drivers/dsp/bridge/core/_tiomap.h +++ b/drivers/dsp/bridge/core/_tiomap.h @@ -26,7 +26,6 @@ #include #include #include -#include #include /* for bridge_ioctl_extproc defn */ #include #include diff --git a/drivers/dsp/bridge/core/io_sm.c b/drivers/dsp/bridge/core/io_sm.c index aca9854..72d64cb 100644 --- a/drivers/dsp/bridge/core/io_sm.c +++ b/drivers/dsp/bridge/core/io_sm.c @@ -40,10 +40,6 @@ #include #include -/* Hardware Abstraction Layer */ -#include -#include - /* Bridge Driver */ #include #include diff --git a/drivers/dsp/bridge/core/mmu_fault.c b/drivers/dsp/bridge/core/mmu_fault.c index d991c6a..54c0bc3 100644 --- a/drivers/dsp/bridge/core/mmu_fault.c +++ b/drivers/dsp/bridge/core/mmu_fault.c @@ -33,10 +33,6 @@ /* ----------------------------------- Link Driver */ #include -/* ------------------------------------ Hardware Abstraction Layer */ -#include -#include - /* ----------------------------------- This */ #include "_deh.h" #include diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 89867e7..9b6293b 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -34,10 +34,6 @@ #include #include -/* ------------------------------------ Hardware Abstraction Layer */ -#include -#include - /* ----------------------------------- Link Driver */ #include #include @@ -483,24 +479,18 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg; /*PM_IVA2GRPSEL_PER = 0xC0;*/ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA8)); + temp = __raw_readl(resources->dw_per_pm_base + 0xA8); temp = (temp & 0xFFFFFF30) | 0xC0; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) = - (u32) temp; + __raw_writel(temp, resources->dw_per_pm_base + 0xA8); /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA4)); + temp = __raw_readl(resources->dw_per_pm_base + 0xA4); temp = (temp & 0xFFFFFF3F); - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) = - (u32) temp; + __raw_writel(temp, resources->dw_per_pm_base + 0xA4); /*CM_SLEEPDEP_PER |= 0x04; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_base) + 0x44)); + temp = __raw_readl(resources->dw_per_pm_base + 0x44); temp = (temp & 0xFFFFFFFB) | 0x04; - *((reg_uword32 *) ((u32) (resources->dw_per_base) + 0x44)) = - (u32) temp; + __raw_writel(temp, resources->dw_per_pm_base + 0x44); /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */ (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, diff --git a/drivers/dsp/bridge/core/tiomap3430_pwr.c b/drivers/dsp/bridge/core/tiomap3430_pwr.c index a45db99..6746fc5 100644 --- a/drivers/dsp/bridge/core/tiomap3430_pwr.c +++ b/drivers/dsp/bridge/core/tiomap3430_pwr.c @@ -27,10 +27,6 @@ #include #include -/* ------------------------------------ Hardware Abstraction Layer */ -#include -#include - #include /* ----------------------------------- Bridge Driver */ @@ -412,7 +408,7 @@ void dsp_clk_wakeup_event_ctrl(u32 ClkId, bool enable) struct cfg_hostres *resources; int status = 0; u32 iva2_grpsel; - u32 mpu_grpsel; + u32 mpu_grpsel, mask; struct dev_object *hdev_object = NULL; struct bridge_dev_context *bridge_context = NULL; @@ -430,175 +426,46 @@ void dsp_clk_wakeup_event_ctrl(u32 ClkId, bool enable) switch (ClkId) { case BPWR_GP_TIMER5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_GPT5; - mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_GPT5; - iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5; - } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + mask = OMAP3430_GRPSEL_GPT5; break; case BPWR_GP_TIMER6: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_GPT6; - mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_GPT6; - iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6; - } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + mask = OMAP3430_GRPSEL_GPT6; break; case BPWR_GP_TIMER7: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_GPT7; - mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_GPT7; - iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7; - } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + mask = OMAP3430_GRPSEL_GPT7; break; case BPWR_GP_TIMER8: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_GPT8; - mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_GPT8; - iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8; - } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + mask = OMAP3430_GRPSEL_GPT8; break; case BPWR_MCBSP1: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1; - mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1; - iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1; - } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + mask = BPWR_MCBSP1; break; case BPWR_MCBSP2: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2; - mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2; - iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2; - } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + mask = BPWR_MCBSP2; break; case BPWR_MCBSP3: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3; - mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3; - iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3; - } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + mask = BPWR_MCBSP3; break; case BPWR_MCBSP4: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4; - mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4; - iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4; - } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + mask = BPWR_MCBSP4; break; case BPWR_MCBSP5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); - if (enable) { - iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5; - mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5; - } else { - mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5; - iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5; - } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + mask = BPWR_MCBSP5; break; + default: + return; + } + iva2_grpsel = __raw_readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = __raw_readl(resources->dw_per_pm_base + 0xA4); + if (enable) { + iva2_grpsel |= mask; + mpu_grpsel &= ~mask; + } else { + mpu_grpsel |= mask; + iva2_grpsel &= ~mask; + } + __raw_writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + __raw_writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); + } diff --git a/drivers/dsp/bridge/core/tiomap_io.c b/drivers/dsp/bridge/core/tiomap_io.c index c23ca66..3c0d3a3 100644 --- a/drivers/dsp/bridge/core/tiomap_io.c +++ b/drivers/dsp/bridge/core/tiomap_io.c @@ -142,7 +142,7 @@ int read_ext_dsp_data(struct bridge_dev_context *hDevContext, ul_shm_base_virt - ul_tlb_base_virt; ul_shm_offset_virt += PG_ALIGN_HIGH(ul_ext_end - ul_dyn_ext_base + - 1, HW_PAGE_SIZE64KB); + 1, PAGE_SIZE * 16); dw_ext_prog_virt_mem -= ul_shm_offset_virt; dw_ext_prog_virt_mem += (ul_ext_base - ul_dyn_ext_base); @@ -394,7 +394,6 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) omap_dspbridge_dev->dev.platform_data; struct cfg_hostres *resources = dev_context->resources; int status = 0; - u32 temp; if (!dev_context->mbox) return 0; @@ -438,7 +437,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) omap_mbox_restore_ctx(dev_context->mbox); /* Access MMU SYS CONFIG register to generate a short wakeup */ - temp = *(reg_uword32 *) (resources->dw_dmmu_base + 0x10); + __raw_readl(resources->dw_dmmu_base + 0x10); dev_context->dw_brd_state = BRD_RUNNING; } else if (dev_context->dw_brd_state == BRD_RETENTION) { diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index a03d172..72cc6c0 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -41,10 +41,6 @@ #include #include -/* ------------------------------------ Hardware Abstraction Layer */ -#include -#include - /* ----------------------------------- This */ #include "mmu_fault.h" #include "_tiomap.h" diff --git a/drivers/dsp/bridge/hw/EasiGlobal.h b/drivers/dsp/bridge/hw/EasiGlobal.h deleted file mode 100644 index 9b45aa7..0000000 --- a/drivers/dsp/bridge/hw/EasiGlobal.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * EasiGlobal.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Copyright (C) 2007 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef _EASIGLOBAL_H -#define _EASIGLOBAL_H -#include - -/* - * DEFINE: READ_ONLY, WRITE_ONLY & READ_WRITE - * - * DESCRIPTION: Defines used to describe register types for EASI-checker tests. - */ - -#define READ_ONLY 1 -#define WRITE_ONLY 2 -#define READ_WRITE 3 - -/* - * MACRO: _DEBUG_LEVEL1_EASI - * - * DESCRIPTION: A MACRO which can be used to indicate that a particular beach - * register access function was called. - * - * NOTE: We currently dont use this functionality. - */ -#define _DEBUG_LEVEL1_EASI(easiNum) ((void)0) - -#endif /* _EASIGLOBAL_H */ diff --git a/drivers/dsp/bridge/hw/GlobalTypes.h b/drivers/dsp/bridge/hw/GlobalTypes.h deleted file mode 100644 index 9b55150..0000000 --- a/drivers/dsp/bridge/hw/GlobalTypes.h +++ /dev/null @@ -1,308 +0,0 @@ -/* - * GlobalTypes.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Global HW definitions - * - * Copyright (C) 2007 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef _GLOBALTYPES_H -#define _GLOBALTYPES_H - -/* - * Definition: TRUE, FALSE - * - * DESCRIPTION: Boolean Definitions - */ -#ifndef TRUE -#define FALSE 0 -#define TRUE (!(FALSE)) -#endif - -/* - * Definition: NULL - * - * DESCRIPTION: Invalid pointer - */ -#ifndef NULL -#define NULL (void *)0 -#endif - -/* - * Definition: RET_CODE_BASE - * - * DESCRIPTION: Base value for return code offsets - */ -#define RET_CODE_BASE 0 - -/* - * Definition: *BIT_OFFSET - * - * DESCRIPTION: offset in bytes from start of 32-bit word. - */ -#define LOWER16BIT_OFFSET 0 -#define UPPER16BIT_OFFSET 2 - -#define LOWER8BIT_OFFSET 0 -#define LOWER_MIDDLE8BIT_OFFSET 1 -#define UPPER_MIDDLE8BIT_OFFSET 2 -#define UPPER8BIT_OFFSET 3 - -#define LOWER8BIT_OF16_OFFSET 0 -#define UPPER8BIT_OF16_OFFSET 1 - -/* - * Definition: *BIT_SHIFT - * - * DESCRIPTION: offset in bits from start of 32-bit word. - */ -#define LOWER16BIT_SHIFT 0 -#define UPPER16BIT_SHIFT 16 - -#define LOWER8BIT_SHIFT 0 -#define LOWER_MIDDLE8BIT_SHIFT 8 -#define UPPER_MIDDLE8BIT_SHIFT 16 -#define UPPER8BIT_SHIFT 24 - -#define LOWER8BIT_OF16_SHIFT 0 -#define UPPER8BIT_OF16_SHIFT 8 - -/* - * Definition: LOWER16BIT_MASK - * - * DESCRIPTION: 16 bit mask used for inclusion of lower 16 bits i.e. mask out - * the upper 16 bits - */ -#define LOWER16BIT_MASK 0x0000FFFF - -/* - * Definition: LOWER8BIT_MASK - * - * DESCRIPTION: 8 bit masks used for inclusion of 8 bits i.e. mask out - * the upper 16 bits - */ -#define LOWER8BIT_MASK 0x000000FF - -/* - * Definition: RETURN32BITS_FROM16LOWER_AND16UPPER(lower16Bits, upper16Bits) - * - * DESCRIPTION: Returns a 32 bit value given a 16 bit lower value and a 16 - * bit upper value - */ -#define RETURN32BITS_FROM16LOWER_AND16UPPER(lower16Bits, upper16Bits)\ - (((((u32)lower16Bits) & LOWER16BIT_MASK)) | \ - (((((u32)upper16Bits) & LOWER16BIT_MASK) << UPPER16BIT_SHIFT))) - -/* - * Definition: RETURN16BITS_FROM8LOWER_AND8UPPER(lower16Bits, upper16Bits) - * - * DESCRIPTION: Returns a 16 bit value given a 8 bit lower value and a 8 - * bit upper value - */ -#define RETURN16BITS_FROM8LOWER_AND8UPPER(lower8Bits, upper8Bits)\ - (((((u32)lower8Bits) & LOWER8BIT_MASK)) | \ - (((((u32)upper8Bits) & LOWER8BIT_MASK) << UPPER8BIT_OF16_SHIFT))) - -/* - * Definition: RETURN32BITS_FROM48BIT_VALUES(lower8Bits, lowerMiddle8Bits, - * lowerUpper8Bits, upper8Bits) - * - * DESCRIPTION: Returns a 32 bit value given four 8 bit values - */ -#define RETURN32BITS_FROM48BIT_VALUES(lower8Bits, lowerMiddle8Bits,\ - lowerUpper8Bits, upper8Bits)\ - (((((u32)lower8Bits) & LOWER8BIT_MASK)) | \ - (((((u32)lowerMiddle8Bits) & LOWER8BIT_MASK) <<\ - LOWER_MIDDLE8BIT_SHIFT)) | \ - (((((u32)lowerUpper8Bits) & LOWER8BIT_MASK) <<\ - UPPER_MIDDLE8BIT_SHIFT)) | \ - (((((u32)upper8Bits) & LOWER8BIT_MASK) <<\ - UPPER8BIT_SHIFT))) - -/* - * Definition: READ_LOWER16BITS_OF32(value32bits) - * - * DESCRIPTION: Returns a 16 lower bits of 32bit value - */ -#define READ_LOWER16BITS_OF32(value32bits)\ - ((u16)((u32)(value32bits) & LOWER16BIT_MASK)) - -/* - * Definition: READ_UPPER16BITS_OF32(value32bits) - * - * DESCRIPTION: Returns a 16 lower bits of 32bit value - */ -#define READ_UPPER16BITS_OF32(value32bits)\ - (((u16)((u32)(value32bits) >> UPPER16BIT_SHIFT)) &\ - LOWER16BIT_MASK) - -/* - * Definition: READ_LOWER8BITS_OF32(value32bits) - * - * DESCRIPTION: Returns a 8 lower bits of 32bit value - */ -#define READ_LOWER8BITS_OF32(value32bits)\ - ((u8)((u32)(value32bits) & LOWER8BIT_MASK)) - -/* - * Definition: READ_LOWER_MIDDLE8BITS_OF32(value32bits) - * - * DESCRIPTION: Returns a 8 lower middle bits of 32bit value - */ -#define READ_LOWER_MIDDLE8BITS_OF32(value32bits)\ - (((u8)((u32)(value32bits) >> LOWER_MIDDLE8BIT_SHIFT)) &\ - LOWER8BIT_MASK) - -/* - * Definition: READ_LOWER_MIDDLE8BITS_OF32(value32bits) - * - * DESCRIPTION: Returns a 8 lower middle bits of 32bit value - */ -#define READ_UPPER_MIDDLE8BITS_OF32(value32bits)\ - (((u8)((u32)(value32bits) >> LOWER_MIDDLE8BIT_SHIFT)) &\ - LOWER8BIT_MASK) - -/* - * Definition: READ_UPPER8BITS_OF32(value32bits) - * - * DESCRIPTION: Returns a 8 upper bits of 32bit value - */ -#define READ_UPPER8BITS_OF32(value32bits)\ - (((u8)((u32)(value32bits) >> UPPER8BIT_SHIFT)) & LOWER8BIT_MASK) - -/* - * Definition: READ_LOWER8BITS_OF16(value16bits) - * - * DESCRIPTION: Returns a 8 lower bits of 16bit value - */ -#define READ_LOWER8BITS_OF16(value16bits)\ - ((u8)((u16)(value16bits) & LOWER8BIT_MASK)) - -/* - * Definition: READ_UPPER8BITS_OF16(value32bits) - * - * DESCRIPTION: Returns a 8 upper bits of 16bit value - */ -#define READ_UPPER8BITS_OF16(value16bits)\ - (((u8)((u32)(value16bits) >> UPPER8BIT_SHIFT)) & LOWER8BIT_MASK) - -/* UWORD16: 16 bit tpyes */ - -/* reg_uword8, reg_word8: 8 bit register types */ -typedef volatile unsigned char reg_uword8; -typedef volatile signed char reg_word8; - -/* reg_uword16, reg_word16: 16 bit register types */ -#ifndef OMAPBRIDGE_TYPES -typedef volatile unsigned short reg_uword16; -#endif -typedef volatile short reg_word16; - -/* reg_uword32, REG_WORD32: 32 bit register types */ -typedef volatile unsigned long reg_uword32; - -/* FLOAT - * - * Type to be used for floating point calculation. Note that floating point - * calculation is very CPU expensive, and you should only use if you - * absolutely need this. */ - -/* boolean_t: Boolean Type True, False */ -/* return_code_t: Return codes to be returned by all library functions */ -enum return_code_label { - RET_OK = 0, - RET_FAIL = -1, - RET_BAD_NULL_PARAM = -2, - RET_PARAM_OUT_OF_RANGE = -3, - RET_INVALID_ID = -4, - RET_EMPTY = -5, - RET_FULL = -6, - RET_TIMEOUT = -7, - RET_INVALID_OPERATION = -8, - - /* Add new error codes at end of above list */ - - RET_NUM_RET_CODES /* this should ALWAYS be LAST entry */ -}; - -/* MACRO: RD_MEM8, WR_MEM8 - * - * DESCRIPTION: 32 bit memory access macros - */ -#define RD_MEM8(addr) ((u8)(*((u8 *)(addr)))) -#define WR_MEM8(addr, data) (*((u8 *)(addr)) = (u8)(data)) - -/* MACRO: RD_MEM8_VOLATILE, WR_MEM8_VOLATILE - * - * DESCRIPTION: 8 bit register access macros - */ -#define RD_MEM8_VOLATILE(addr) ((u8)(*((reg_uword8 *)(addr)))) -#define WR_MEM8_VOLATILE(addr, data) (*((reg_uword8 *)(addr)) = (u8)(data)) - -/* - * MACRO: RD_MEM16, WR_MEM16 - * - * DESCRIPTION: 16 bit memory access macros - */ -#define RD_MEM16(addr) ((u16)(*((u16 *)(addr)))) -#define WR_MEM16(addr, data) (*((u16 *)(addr)) = (u16)(data)) - -/* - * MACRO: RD_MEM16_VOLATILE, WR_MEM16_VOLATILE - * - * DESCRIPTION: 16 bit register access macros - */ -#define RD_MEM16_VOLATILE(addr) ((u16)(*((reg_uword16 *)(addr)))) -#define WR_MEM16_VOLATILE(addr, data) (*((reg_uword16 *)(addr)) =\ - (u16)(data)) - -/* - * MACRO: RD_MEM32, WR_MEM32 - * - * DESCRIPTION: 32 bit memory access macros - */ -#define RD_MEM32(addr) ((u32)(*((u32 *)(addr)))) -#define WR_MEM32(addr, data) (*((u32 *)(addr)) = (u32)(data)) - -/* - * MACRO: RD_MEM32_VOLATILE, WR_MEM32_VOLATILE - * - * DESCRIPTION: 32 bit register access macros - */ -#define RD_MEM32_VOLATILE(addr) ((u32)(*((reg_uword32 *)(addr)))) -#define WR_MEM32_VOLATILE(addr, data) (*((reg_uword32 *)(addr)) =\ - (u32)(data)) - -/* Not sure if this all belongs here */ - -#define CHECK_RETURN_VALUE(actualValue, expectedValue, returnCodeIfMismatch,\ - spyCodeIfMisMatch) -#define CHECK_RETURN_VALUE_RET(actualValue, expectedValue, returnCodeIfMismatch) -#define CHECK_RETURN_VALUE_RES(actualValue, expectedValue, spyCodeIfMisMatch) -#define CHECK_RETURN_VALUE_RET_VOID(actualValue, expectedValue,\ - spyCodeIfMisMatch) - -#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\ - spyCodeIfMisMatch) -#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue,\ - returnCodeIfMismatch) -#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue,\ - returnCodeIfMismatch, spyCodeIfMisMatch) -#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue, maxValidValue,\ - returnCodeIfMismatch) -#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue,\ - returnCodeIfMismatch, spyCodeIfMisMatch) -#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, maxValidValue,\ - returnCodeIfMismatch) - -#endif /* _GLOBALTYPES_H */ diff --git a/drivers/dsp/bridge/hw/MMUAccInt.h b/drivers/dsp/bridge/hw/MMUAccInt.h deleted file mode 100644 index 1cefca3..0000000 --- a/drivers/dsp/bridge/hw/MMUAccInt.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * MMUAccInt.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Copyright (C) 2007 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef _MMU_ACC_INT_H -#define _MMU_ACC_INT_H - -/* Mappings of level 1 EASI function numbers to function names */ - -#define EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32 (MMU_BASE_EASIL1 + 3) -#define EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32 (MMU_BASE_EASIL1 + 17) -#define EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32 (MMU_BASE_EASIL1 + 39) -#define EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 51) -#define EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32 (MMU_BASE_EASIL1 + 102) -#define EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 103) -#define EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32 (MMU_BASE_EASIL1 + 156) -#define EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32 (MMU_BASE_EASIL1 + 174) -#define EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 180) -#define EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 190) -#define EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32 (MMU_BASE_EASIL1 + 194) -#define EASIL1_MMUMMU_TTB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 198) -#define EASIL1_MMUMMU_LOCK_READ_REGISTER32 (MMU_BASE_EASIL1 + 203) -#define EASIL1_MMUMMU_LOCK_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 204) -#define EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32 (MMU_BASE_EASIL1 + 205) -#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32 (MMU_BASE_EASIL1 + 209) -#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32 (MMU_BASE_EASIL1 + 211) -#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32 (MMU_BASE_EASIL1 + 212) -#define EASIL1_MMUMMU_LD_TLB_READ_REGISTER32 (MMU_BASE_EASIL1 + 213) -#define EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 214) -#define EASIL1_MMUMMU_CAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 226) -#define EASIL1_MMUMMU_RAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 268) -#define EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 322) - -/* Register offset address definitions */ -#define MMU_MMU_SYSCONFIG_OFFSET 0x10 -#define MMU_MMU_IRQSTATUS_OFFSET 0x18 -#define MMU_MMU_IRQENABLE_OFFSET 0x1c -#define MMU_MMU_WALKING_ST_OFFSET 0x40 -#define MMU_MMU_CNTL_OFFSET 0x44 -#define MMU_MMU_FAULT_AD_OFFSET 0x48 -#define MMU_MMU_TTB_OFFSET 0x4c -#define MMU_MMU_LOCK_OFFSET 0x50 -#define MMU_MMU_LD_TLB_OFFSET 0x54 -#define MMU_MMU_CAM_OFFSET 0x58 -#define MMU_MMU_RAM_OFFSET 0x5c -#define MMU_MMU_GFLUSH_OFFSET 0x60 -#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64 -/* Bitfield mask and offset declarations */ -#define MMU_MMU_SYSCONFIG_IDLE_MODE_MASK 0x18 -#define MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET 3 -#define MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK 0x1 -#define MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET 0 -#define MMU_MMU_WALKING_ST_TWL_RUNNING_MASK 0x1 -#define MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET 0 -#define MMU_MMU_CNTL_TWL_ENABLE_MASK 0x4 -#define MMU_MMU_CNTL_TWL_ENABLE_OFFSET 2 -#define MMU_MMU_CNTL_MMU_ENABLE_MASK 0x2 -#define MMU_MMU_CNTL_MMU_ENABLE_OFFSET 1 -#define MMU_MMU_LOCK_BASE_VALUE_MASK 0xfc00 -#define MMU_MMU_LOCK_BASE_VALUE_OFFSET 10 -#define MMU_MMU_LOCK_CURRENT_VICTIM_MASK 0x3f0 -#define MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET 4 - -#endif /* _MMU_ACC_INT_H */ diff --git a/drivers/dsp/bridge/hw/MMURegAcM.h b/drivers/dsp/bridge/hw/MMURegAcM.h deleted file mode 100644 index 8c0c549..0000000 --- a/drivers/dsp/bridge/hw/MMURegAcM.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * MMURegAcM.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Copyright (C) 2007 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef _MMU_REG_ACM_H -#define _MMU_REG_ACM_H - -#include -#include -#include - -#include "MMUAccInt.h" - -#if defined(USE_LEVEL_1_MACROS) - -#define MMUMMU_SYSCONFIG_READ_REGISTER32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32),\ - __raw_readl((baseAddress)+MMU_MMU_SYSCONFIG_OFFSET)) - -#define MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32);\ - data &= ~(MMU_MMU_SYSCONFIG_IDLE_MODE_MASK);\ - newValue <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\ - newValue &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - -#define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32);\ - data &= ~(MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK);\ - newValue <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\ - newValue &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - -#define MMUMMU_IRQSTATUS_READ_REGISTER32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\ - __raw_readl((baseAddress)+MMU_MMU_IRQSTATUS_OFFSET)) - -#define MMUMMU_IRQSTATUS_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#define MMUMMU_IRQENABLE_READ_REGISTER32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32),\ - __raw_readl((baseAddress)+MMU_MMU_IRQENABLE_OFFSET)) - -#define MMUMMU_IRQENABLE_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#define MMUMMU_WALKING_STTWL_RUNNING_READ32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_WALKING_ST_OFFSET))))\ - & MMU_MMU_WALKING_ST_TWL_RUNNING_MASK) >>\ - MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET)) - -#define MMUMMU_CNTLTWL_ENABLE_READ32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) &\ - MMU_MMU_CNTL_TWL_ENABLE_MASK) >>\ - MMU_MMU_CNTL_TWL_ENABLE_OFFSET)) - -#define MMUMMU_CNTLTWL_ENABLE_WRITE32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_CNTL_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32);\ - data &= ~(MMU_MMU_CNTL_TWL_ENABLE_MASK);\ - newValue <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\ - newValue &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - -#define MMUMMU_CNTLMMU_ENABLE_WRITE32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_CNTL_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32);\ - data &= ~(MMU_MMU_CNTL_MMU_ENABLE_MASK);\ - newValue <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\ - newValue &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - -#define MMUMMU_FAULT_AD_READ_REGISTER32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32),\ - __raw_readl((baseAddress)+MMU_MMU_FAULT_AD_OFFSET)) - -#define MMUMMU_TTB_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_TTB_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_TTB_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#define MMUMMU_LOCK_READ_REGISTER32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_READ_REGISTER32),\ - __raw_readl((baseAddress)+MMU_MMU_LOCK_OFFSET)) - -#define MMUMMU_LOCK_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LOCK_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#define MMUMMU_LOCK_BASE_VALUE_READ32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\ - MMU_MMU_LOCK_BASE_VALUE_MASK) >>\ - MMU_MMU_LOCK_BASE_VALUE_OFFSET)) - -#define MMUMMU_LOCK_BASE_VALUE_WRITE32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LOCK_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\ - data &= ~(MMU_MMU_LOCK_BASE_VALUE_MASK);\ - newValue <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\ - newValue &= MMU_MMU_LOCK_BASE_VALUE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - -#define MMUMMU_LOCK_CURRENT_VICTIM_READ32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\ - MMU_MMU_LOCK_CURRENT_VICTIM_MASK) >>\ - MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET)) - -#define MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LOCK_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32);\ - data &= ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK);\ - newValue <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\ - newValue &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - -#define MMUMMU_LOCK_CURRENT_VICTIM_SET32(var, value)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32),\ - (((var) & ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK)) |\ - (((value) << MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET) &\ - MMU_MMU_LOCK_CURRENT_VICTIM_MASK))) - -#define MMUMMU_LD_TLB_READ_REGISTER32(baseAddress)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_READ_REGISTER32),\ - __raw_readl((baseAddress)+MMU_MMU_LD_TLB_OFFSET)) - -#define MMUMMU_LD_TLB_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LD_TLB_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#define MMUMMU_CAM_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_CAM_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CAM_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#define MMUMMU_RAM_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_RAM_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_RAM_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - -#endif /* USE_LEVEL_1_MACROS */ - -#endif /* _MMU_REG_ACM_H */ diff --git a/drivers/dsp/bridge/hw/hw_defs.h b/drivers/dsp/bridge/hw/hw_defs.h deleted file mode 100644 index 98f6045..0000000 --- a/drivers/dsp/bridge/hw/hw_defs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * hw_defs.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Global HW definitions - * - * Copyright (C) 2007 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef _HW_DEFS_H -#define _HW_DEFS_H - -#include - -/* Page size */ -#define HW_PAGE_SIZE4KB 0x1000 -#define HW_PAGE_SIZE64KB 0x10000 -#define HW_PAGE_SIZE1MB 0x100000 -#define HW_PAGE_SIZE16MB 0x1000000 - -/* hw_status: return type for HW API */ -typedef long hw_status; - -/* Macro used to set and clear any bit */ -#define HW_CLEAR 0 -#define HW_SET 1 - -/* hw_endianism_t: Enumerated Type used to specify the endianism - * Do NOT change these values. They are used as bit fields. */ -enum hw_endianism_t { - HW_LITTLE_ENDIAN, - HW_BIG_ENDIAN -}; - -/* hw_element_size_t: Enumerated Type used to specify the element size - * Do NOT change these values. They are used as bit fields. */ -enum hw_element_size_t { - HW_ELEM_SIZE8BIT, - HW_ELEM_SIZE16BIT, - HW_ELEM_SIZE32BIT, - HW_ELEM_SIZE64BIT -}; - -/* hw_idle_mode_t: Enumerated Type used to specify Idle modes */ -enum hw_idle_mode_t { - HW_FORCE_IDLE, - HW_NO_IDLE, - HW_SMART_IDLE -}; - -#endif /* _HW_DEFS_H */ diff --git a/drivers/dsp/bridge/hw/hw_mmu.c b/drivers/dsp/bridge/hw/hw_mmu.c deleted file mode 100644 index 965b659..0000000 --- a/drivers/dsp/bridge/hw/hw_mmu.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * hw_mmu.c - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * API definitions to setup MMU TLB and PTE - * - * Copyright (C) 2007 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include -#include -#include "MMURegAcM.h" -#include -#include -#include - -#define MMU_BASE_VAL_MASK 0xFC00 -#define MMU_PAGE_MAX 3 -#define MMU_ELEMENTSIZE_MAX 3 -#define MMU_ADDR_MASK 0xFFFFF000 -#define MMU_TTB_MASK 0xFFFFC000 -#define MMU_SECTION_ADDR_MASK 0xFFF00000 -#define MMU_SSECTION_ADDR_MASK 0xFF000000 -#define MMU_PAGE_TABLE_MASK 0xFFFFFC00 -#define MMU_LARGE_PAGE_MASK 0xFFFF0000 -#define MMU_SMALL_PAGE_MASK 0xFFFFF000 - -#define MMU_LOAD_TLB 0x00000001 - -/* - * hw_mmu_page_size_t: Enumerated Type used to specify the MMU Page Size(SLSS) - */ -enum hw_mmu_page_size_t { - HW_MMU_SECTION, - HW_MMU_LARGE_PAGE, - HW_MMU_SMALL_PAGE, - HW_MMU_SUPERSECTION -}; - -/* - * FUNCTION : mmu_flush_entry - * - * INPUTS: - * - * Identifier : baseAddress - * Type : const u32 - * Description : Base Address of instance of MMU module - * - * RETURNS: - * - * Type : hw_status - * Description : RET_OK -- No errors occured - * RET_BAD_NULL_PARAM -- A Pointer - * Paramater was set to NULL - * - * PURPOSE: : Flush the TLB entry pointed by the - * lock counter register - * even if this entry is set protected - * - * METHOD: : Check the Input parameter and Flush a - * single entry in the TLB. - */ -static hw_status mmu_flush_entry(const void __iomem *baseAddress); - -/* - * FUNCTION : mmu_set_cam_entry - * - * INPUTS: - * - * Identifier : baseAddress - * TypE : const u32 - * Description : Base Address of instance of MMU module - * - * Identifier : pageSize - * TypE : const u32 - * Description : It indicates the page size - * - * Identifier : preservedBit - * Type : const u32 - * Description : It indicates the TLB entry is preserved entry - * or not - * - * Identifier : validBit - * Type : const u32 - * Description : It indicates the TLB entry is valid entry or not - * - * - * Identifier : virtual_addr_tag - * Type : const u32 - * Description : virtual Address - * - * RETURNS: - * - * Type : hw_status - * Description : RET_OK -- No errors occured - * RET_BAD_NULL_PARAM -- A Pointer Paramater - * was set to NULL - * RET_PARAM_OUT_OF_RANGE -- Input Parameter out - * of Range - * - * PURPOSE: : Set MMU_CAM reg - * - * METHOD: : Check the Input parameters and set the CAM entry. - */ -static hw_status mmu_set_cam_entry(const void __iomem *baseAddress, - const u32 pageSize, - const u32 preservedBit, - const u32 validBit, - const u32 virtual_addr_tag); - -/* - * FUNCTION : mmu_set_ram_entry - * - * INPUTS: - * - * Identifier : baseAddress - * Type : const u32 - * Description : Base Address of instance of MMU module - * - * Identifier : physicalAddr - * Type : const u32 - * Description : Physical Address to which the corresponding - * virtual Address shouldpoint - * - * Identifier : endianism - * Type : hw_endianism_t - * Description : endianism for the given page - * - * Identifier : element_size - * Type : hw_element_size_t - * Description : The element size ( 8,16, 32 or 64 bit) - * - * Identifier : mixed_size - * Type : hw_mmu_mixed_size_t - * Description : Element Size to follow CPU or TLB - * - * RETURNS: - * - * Type : hw_status - * Description : RET_OK -- No errors occured - * RET_BAD_NULL_PARAM -- A Pointer Paramater - * was set to NULL - * RET_PARAM_OUT_OF_RANGE -- Input Parameter - * out of Range - * - * PURPOSE: : Set MMU_CAM reg - * - * METHOD: : Check the Input parameters and set the RAM entry. - */ -static hw_status mmu_set_ram_entry(const void __iomem *baseAddress, - const u32 physicalAddr, - enum hw_endianism_t endianism, - enum hw_element_size_t element_size, - enum hw_mmu_mixed_size_t mixed_size); - -/* HW FUNCTIONS */ - -hw_status hw_mmu_enable(const void __iomem *baseAddress) -{ - hw_status status = RET_OK; - - MMUMMU_CNTLMMU_ENABLE_WRITE32(baseAddress, HW_SET); - - return status; -} - -hw_status hw_mmu_disable(const void __iomem *baseAddress) -{ - hw_status status = RET_OK; - - MMUMMU_CNTLMMU_ENABLE_WRITE32(baseAddress, HW_CLEAR); - - return status; -} - -hw_status hw_mmu_num_locked_set(const void __iomem *baseAddress, - u32 numLockedEntries) -{ - hw_status status = RET_OK; - - MMUMMU_LOCK_BASE_VALUE_WRITE32(baseAddress, numLockedEntries); - - return status; -} - -hw_status hw_mmu_victim_num_set(const void __iomem *baseAddress, - u32 victimEntryNum) -{ - hw_status status = RET_OK; - - MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(baseAddress, victimEntryNum); - - return status; -} - -hw_status hw_mmu_event_ack(const void __iomem *baseAddress, u32 irqMask) -{ - hw_status status = RET_OK; - - MMUMMU_IRQSTATUS_WRITE_REGISTER32(baseAddress, irqMask); - - return status; -} - -hw_status hw_mmu_event_disable(const void __iomem *baseAddress, u32 irqMask) -{ - hw_status status = RET_OK; - u32 irq_reg; - - irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(baseAddress); - - MMUMMU_IRQENABLE_WRITE_REGISTER32(baseAddress, irq_reg & ~irqMask); - - return status; -} - -hw_status hw_mmu_event_enable(const void __iomem *baseAddress, u32 irqMask) -{ - hw_status status = RET_OK; - u32 irq_reg; - - irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(baseAddress); - - MMUMMU_IRQENABLE_WRITE_REGISTER32(baseAddress, irq_reg | irqMask); - - return status; -} - -hw_status hw_mmu_event_status(const void __iomem *baseAddress, u32 *irqMask) -{ - hw_status status = RET_OK; - - *irqMask = MMUMMU_IRQSTATUS_READ_REGISTER32(baseAddress); - - return status; -} - -hw_status hw_mmu_fault_addr_read(const void __iomem *baseAddress, u32 *addr) -{ - hw_status status = RET_OK; - - /*Check the input Parameters */ - CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, - RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - - /* read values from register */ - *addr = MMUMMU_FAULT_AD_READ_REGISTER32(baseAddress); - - return status; -} - -hw_status hw_mmu_ttb_set(const void __iomem *baseAddress, u32 TTBPhysAddr) -{ - hw_status status = RET_OK; - u32 load_ttb; - - /*Check the input Parameters */ - CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, - RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - - load_ttb = TTBPhysAddr & ~0x7FUL; - /* write values to register */ - MMUMMU_TTB_WRITE_REGISTER32(baseAddress, load_ttb); - - return status; -} - -hw_status hw_mmu_twl_enable(const void __iomem *baseAddress) -{ - hw_status status = RET_OK; - - MMUMMU_CNTLTWL_ENABLE_WRITE32(baseAddress, HW_SET); - - return status; -} - -hw_status hw_mmu_twl_disable(const void __iomem *baseAddress) -{ - hw_status status = RET_OK; - - MMUMMU_CNTLTWL_ENABLE_WRITE32(baseAddress, HW_CLEAR); - - return status; -} - -hw_status hw_mmu_tlb_flush(const void __iomem *baseAddress, u32 virtualAddr, - u32 pageSize) -{ - hw_status status = RET_OK; - u32 virtual_addr_tag; - enum hw_mmu_page_size_t pg_size_bits; - - switch (pageSize) { - case HW_PAGE_SIZE4KB: - pg_size_bits = HW_MMU_SMALL_PAGE; - break; - - case HW_PAGE_SIZE64KB: - pg_size_bits = HW_MMU_LARGE_PAGE; - break; - - case HW_PAGE_SIZE1MB: - pg_size_bits = HW_MMU_SECTION; - break; - - case HW_PAGE_SIZE16MB: - pg_size_bits = HW_MMU_SUPERSECTION; - break; - - default: - return RET_FAIL; - } - - /* Generate the 20-bit tag from virtual address */ - virtual_addr_tag = ((virtualAddr & MMU_ADDR_MASK) >> 12); - - mmu_set_cam_entry(baseAddress, pg_size_bits, 0, 0, virtual_addr_tag); - - mmu_flush_entry(baseAddress); - - return status; -} - -hw_status hw_mmu_tlb_add(const void __iomem *baseAddress, - u32 physicalAddr, - u32 virtualAddr, - u32 pageSize, - u32 entryNum, - struct hw_mmu_map_attrs_t *map_attrs, - s8 preservedBit, s8 validBit) -{ - hw_status status = RET_OK; - u32 lock_reg; - u32 virtual_addr_tag; - enum hw_mmu_page_size_t mmu_pg_size; - - /*Check the input Parameters */ - CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, - RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - CHECK_INPUT_RANGE_MIN0(pageSize, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE, - RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - CHECK_INPUT_RANGE_MIN0(map_attrs->element_size, MMU_ELEMENTSIZE_MAX, - RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE + - RES_INVALID_INPUT_PARAM); - - switch (pageSize) { - case HW_PAGE_SIZE4KB: - mmu_pg_size = HW_MMU_SMALL_PAGE; - break; - - case HW_PAGE_SIZE64KB: - mmu_pg_size = HW_MMU_LARGE_PAGE; - break; - - case HW_PAGE_SIZE1MB: - mmu_pg_size = HW_MMU_SECTION; - break; - - case HW_PAGE_SIZE16MB: - mmu_pg_size = HW_MMU_SUPERSECTION; - break; - - default: - return RET_FAIL; - } - - lock_reg = MMUMMU_LOCK_READ_REGISTER32(baseAddress); - - /* Generate the 20-bit tag from virtual address */ - virtual_addr_tag = ((virtualAddr & MMU_ADDR_MASK) >> 12); - - /* Write the fields in the CAM Entry Register */ - mmu_set_cam_entry(baseAddress, mmu_pg_size, preservedBit, validBit, - virtual_addr_tag); - - /* Write the different fields of the RAM Entry Register */ - /* endianism of the page,Element Size of the page (8, 16, 32, 64 bit) */ - mmu_set_ram_entry(baseAddress, physicalAddr, map_attrs->endianism, - map_attrs->element_size, map_attrs->mixed_size); - - /* Update the MMU Lock Register */ - /* currentVictim between lockedBaseValue and (MMU_Entries_Number - 1) */ - MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(baseAddress, entryNum); - - /* Enable loading of an entry in TLB by writing 1 - into LD_TLB_REG register */ - MMUMMU_LD_TLB_WRITE_REGISTER32(baseAddress, MMU_LOAD_TLB); - - MMUMMU_LOCK_WRITE_REGISTER32(baseAddress, lock_reg); - - return status; -} - -hw_status hw_mmu_pte_set(const u32 pg_tbl_va, - u32 physicalAddr, - u32 virtualAddr, - u32 pageSize, struct hw_mmu_map_attrs_t *map_attrs) -{ - hw_status status = RET_OK; - u32 pte_addr, pte_val; - s32 num_entries = 1; - - switch (pageSize) { - case HW_PAGE_SIZE4KB: - pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & - MMU_SMALL_PAGE_MASK); - pte_val = - ((physicalAddr & MMU_SMALL_PAGE_MASK) | - (map_attrs->endianism << 9) | (map_attrs-> - element_size << 4) | - (map_attrs->mixed_size << 11) | 2); - break; - - case HW_PAGE_SIZE64KB: - num_entries = 16; - pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & - MMU_LARGE_PAGE_MASK); - pte_val = - ((physicalAddr & MMU_LARGE_PAGE_MASK) | - (map_attrs->endianism << 9) | (map_attrs-> - element_size << 4) | - (map_attrs->mixed_size << 11) | 1); - break; - - case HW_PAGE_SIZE1MB: - pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & - MMU_SECTION_ADDR_MASK); - pte_val = - ((((physicalAddr & MMU_SECTION_ADDR_MASK) | - (map_attrs->endianism << 15) | (map_attrs-> - element_size << 10) | - (map_attrs->mixed_size << 17)) & ~0x40000) | 0x2); - break; - - case HW_PAGE_SIZE16MB: - num_entries = 16; - pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & - MMU_SSECTION_ADDR_MASK); - pte_val = - (((physicalAddr & MMU_SSECTION_ADDR_MASK) | - (map_attrs->endianism << 15) | (map_attrs-> - element_size << 10) | - (map_attrs->mixed_size << 17) - ) | 0x40000 | 0x2); - break; - - case HW_MMU_COARSE_PAGE_SIZE: - pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & - MMU_SECTION_ADDR_MASK); - pte_val = (physicalAddr & MMU_PAGE_TABLE_MASK) | 1; - break; - - default: - return RET_FAIL; - } - - while (--num_entries >= 0) - ((u32 *) pte_addr)[num_entries] = pte_val; - - return status; -} - -hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtualAddr, u32 page_size) -{ - hw_status status = RET_OK; - u32 pte_addr; - s32 num_entries = 1; - - switch (page_size) { - case HW_PAGE_SIZE4KB: - pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & - MMU_SMALL_PAGE_MASK); - break; - - case HW_PAGE_SIZE64KB: - num_entries = 16; - pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & - MMU_LARGE_PAGE_MASK); - break; - - case HW_PAGE_SIZE1MB: - case HW_MMU_COARSE_PAGE_SIZE: - pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & - MMU_SECTION_ADDR_MASK); - break; - - case HW_PAGE_SIZE16MB: - num_entries = 16; - pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & - MMU_SSECTION_ADDR_MASK); - break; - - default: - return RET_FAIL; - } - - while (--num_entries >= 0) - ((u32 *) pte_addr)[num_entries] = 0; - - return status; -} - -/* mmu_flush_entry */ -static hw_status mmu_flush_entry(const void __iomem *baseAddress) -{ - hw_status status = RET_OK; - u32 flush_entry_data = 0x1; - - /*Check the input Parameters */ - CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, - RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - - /* write values to register */ - MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(baseAddress, flush_entry_data); - - return status; -} - -/* mmu_set_cam_entry */ -static hw_status mmu_set_cam_entry(const void __iomem *baseAddress, - const u32 pageSize, - const u32 preservedBit, - const u32 validBit, - const u32 virtual_addr_tag) -{ - hw_status status = RET_OK; - u32 mmu_cam_reg; - - /*Check the input Parameters */ - CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, - RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - - mmu_cam_reg = (virtual_addr_tag << 12); - mmu_cam_reg = (mmu_cam_reg) | (pageSize) | (validBit << 2) | - (preservedBit << 3); - - /* write values to register */ - MMUMMU_CAM_WRITE_REGISTER32(baseAddress, mmu_cam_reg); - - return status; -} - -/* mmu_set_ram_entry */ -static hw_status mmu_set_ram_entry(const void __iomem *baseAddress, - const u32 physicalAddr, - enum hw_endianism_t endianism, - enum hw_element_size_t element_size, - enum hw_mmu_mixed_size_t mixed_size) -{ - hw_status status = RET_OK; - u32 mmu_ram_reg; - - /*Check the input Parameters */ - CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, - RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - CHECK_INPUT_RANGE_MIN0(element_size, MMU_ELEMENTSIZE_MAX, - RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE + - RES_INVALID_INPUT_PARAM); - - mmu_ram_reg = (physicalAddr & MMU_ADDR_MASK); - mmu_ram_reg = (mmu_ram_reg) | ((endianism << 9) | (element_size << 7) | - (mixed_size << 6)); - - /* write values to register */ - MMUMMU_RAM_WRITE_REGISTER32(baseAddress, mmu_ram_reg); - - return status; - -} diff --git a/drivers/dsp/bridge/hw/hw_mmu.h b/drivers/dsp/bridge/hw/hw_mmu.h deleted file mode 100644 index 9b13468..0000000 --- a/drivers/dsp/bridge/hw/hw_mmu.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * hw_mmu.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * MMU types and API declarations - * - * Copyright (C) 2007 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef _HW_MMU_H -#define _HW_MMU_H - -#include - -/* Bitmasks for interrupt sources */ -#define HW_MMU_TRANSLATION_FAULT 0x2 -#define HW_MMU_ALL_INTERRUPTS 0x1F - -#define HW_MMU_COARSE_PAGE_SIZE 0x400 - -/* hw_mmu_mixed_size_t: Enumerated Type used to specify whether to follow - CPU/TLB Element size */ -enum hw_mmu_mixed_size_t { - HW_MMU_TLBES, - HW_MMU_CPUES -}; - -/* hw_mmu_map_attrs_t: Struct containing MMU mapping attributes */ -struct hw_mmu_map_attrs_t { - enum hw_endianism_t endianism; - enum hw_element_size_t element_size; - enum hw_mmu_mixed_size_t mixed_size; - bool donotlockmpupage; -}; - -extern hw_status hw_mmu_enable(const void __iomem *baseAddress); - -extern hw_status hw_mmu_disable(const void __iomem *baseAddress); - -extern hw_status hw_mmu_num_locked_set(const void __iomem *baseAddress, - u32 numLockedEntries); - -extern hw_status hw_mmu_victim_num_set(const void __iomem *baseAddress, - u32 victimEntryNum); - -/* For MMU faults */ -extern hw_status hw_mmu_event_ack(const void __iomem *baseAddress, - u32 irqMask); - -extern hw_status hw_mmu_event_disable(const void __iomem *baseAddress, - u32 irqMask); - -extern hw_status hw_mmu_event_enable(const void __iomem *baseAddress, - u32 irqMask); - -extern hw_status hw_mmu_event_status(const void __iomem *baseAddress, - u32 *irqMask); - -extern hw_status hw_mmu_fault_addr_read(const void __iomem *baseAddress, - u32 *addr); - -/* Set the TT base address */ -extern hw_status hw_mmu_ttb_set(const void __iomem *baseAddress, - u32 TTBPhysAddr); - -extern hw_status hw_mmu_twl_enable(const void __iomem *baseAddress); - -extern hw_status hw_mmu_twl_disable(const void __iomem *baseAddress); - -extern hw_status hw_mmu_tlb_flush(const void __iomem *baseAddress, - u32 virtualAddr, u32 pageSize); - -extern hw_status hw_mmu_tlb_add(const void __iomem *baseAddress, - u32 physicalAddr, - u32 virtualAddr, - u32 pageSize, - u32 entryNum, - struct hw_mmu_map_attrs_t *map_attrs, - s8 preservedBit, s8 validBit); - -/* For PTEs */ -extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, - u32 physicalAddr, - u32 virtualAddr, - u32 pageSize, - struct hw_mmu_map_attrs_t *map_attrs); - -extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, - u32 page_size, u32 virtualAddr); - -static inline u32 hw_mmu_pte_addr_l1(u32 L1_base, u32 va) -{ - u32 pte_addr; - u32 va31_to20; - - va31_to20 = va >> (20 - 2); /* Left-shift by 2 here itself */ - va31_to20 &= 0xFFFFFFFCUL; - pte_addr = L1_base + va31_to20; - - return pte_addr; -} - -static inline u32 hw_mmu_pte_addr_l2(u32 L2_base, u32 va) -{ - u32 pte_addr; - - pte_addr = (L2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC); - - return pte_addr; -} - -static inline u32 hw_mmu_pte_coarse_l1(u32 pte_val) -{ - u32 pte_coarse; - - pte_coarse = pte_val & 0xFFFFFC00; - - return pte_coarse; -} - -static inline u32 hw_mmu_pte_size_l1(u32 pte_val) -{ - u32 pte_size = 0; - - if ((pte_val & 0x3) == 0x1) { - /* Points to L2 PT */ - pte_size = HW_MMU_COARSE_PAGE_SIZE; - } - - if ((pte_val & 0x3) == 0x2) { - if (pte_val & (1 << 18)) - pte_size = HW_PAGE_SIZE16MB; - else - pte_size = HW_PAGE_SIZE1MB; - } - - return pte_size; -} - -static inline u32 hw_mmu_pte_size_l2(u32 pte_val) -{ - u32 pte_size = 0; - - if (pte_val & 0x2) - pte_size = HW_PAGE_SIZE4KB; - else if (pte_val & 0x1) - pte_size = HW_PAGE_SIZE64KB; - - return pte_size; -} - -#endif /* _HW_MMU_H */ diff --git a/drivers/dsp/bridge/rmgr/node.c b/drivers/dsp/bridge/rmgr/node.c index 3d2cf96..e1b3128 100644 --- a/drivers/dsp/bridge/rmgr/node.c +++ b/drivers/dsp/bridge/rmgr/node.c @@ -621,9 +621,7 @@ func_cont: ul_gpp_mem_base = (u32) host_res->dw_mem_base[1]; off_set = pul_value - dynext_base; ul_stack_seg_addr = ul_gpp_mem_base + off_set; - ul_stack_seg_val = (u32) *((reg_uword32 *) - ((u32) - (ul_stack_seg_addr))); + ul_stack_seg_val = __raw_readl(ul_stack_seg_addr); dev_dbg(bridge, "%s: StackSegVal = 0x%x, StackSegAddr =" " 0x%x\n", __func__, ul_stack_seg_val, From patchwork Thu Jul 1 00:20:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 108993 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o610DYa8017455 for ; Thu, 1 Jul 2010 00:13:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757576Ab0GAANX (ORCPT ); Wed, 30 Jun 2010 20:13:23 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:53011 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756195Ab0GAALl (ORCPT ); Wed, 30 Jun 2010 20:11:41 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o610Bdwt012385 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 30 Jun 2010 19:11:39 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o610BdGE013483; Wed, 30 Jun 2010 19:11:39 -0500 (CDT) Received: from localhost (x0095840-desktop.am.dhcp.ti.com [128.247.77.44]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o610BcP08758; Wed, 30 Jun 2010 19:11:38 -0500 (CDT) From: Fernando Guzman Lugo To: , Cc: , , , , Fernando Guzman Lugo Subject: [PATCH 5/9] dspbridge: add mmufault support Date: Wed, 30 Jun 2010 19:20:56 -0500 Message-Id: <1277943660-4112-6-git-send-email-x0095840@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277943660-4112-5-git-send-email-x0095840@ti.com> References: <1277943660-4112-1-git-send-email-x0095840@ti.com> <1277943660-4112-2-git-send-email-x0095840@ti.com> <1277943660-4112-3-git-send-email-x0095840@ti.com> <1277943660-4112-4-git-send-email-x0095840@ti.com> <1277943660-4112-5-git-send-email-x0095840@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 00:13:37 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/mmu_fault.c b/drivers/dsp/bridge/core/mmu_fault.c index 5c0124f..d991c6a 100644 --- a/drivers/dsp/bridge/core/mmu_fault.c +++ b/drivers/dsp/bridge/core/mmu_fault.c @@ -23,9 +23,12 @@ /* ----------------------------------- Trace & Debug */ #include #include +#include /* ----------------------------------- OS Adaptation Layer */ #include +#include + /* ----------------------------------- Link Driver */ #include @@ -40,11 +43,6 @@ #include "_tiomap.h" #include "mmu_fault.h" -static u32 dmmu_event_mask; -u32 fault_addr; - -static bool mmu_check_if_fault(struct bridge_dev_context *dev_context); - /* * ======== mmu_fault_dpc ======== * Deferred procedure call to handle DSP MMU fault. @@ -62,78 +60,21 @@ void mmu_fault_dpc(IN unsigned long pRefData) * ======== mmu_fault_isr ======== * ISR to be triggered by a DSP MMU fault interrupt. */ -irqreturn_t mmu_fault_isr(int irq, IN void *pRefData) -{ - struct deh_mgr *deh_mgr_obj = (struct deh_mgr *)pRefData; - struct bridge_dev_context *dev_context; - struct cfg_hostres *resources; - - DBC_REQUIRE(irq == INT_DSP_MMU_IRQ); - DBC_REQUIRE(deh_mgr_obj); - - if (deh_mgr_obj) { - - dev_context = - (struct bridge_dev_context *)deh_mgr_obj->hbridge_context; - - resources = dev_context->resources; - - if (!resources) { - dev_dbg(bridge, "%s: Failed to get Host Resources\n", - __func__); - return IRQ_HANDLED; - } - if (mmu_check_if_fault(dev_context)) { - printk(KERN_INFO "***** DSPMMU FAULT ***** IRQStatus " - "0x%x\n", dmmu_event_mask); - printk(KERN_INFO "***** DSPMMU FAULT ***** fault_addr " - "0x%x\n", fault_addr); - /* - * Schedule a DPC directly. In the future, it may be - * necessary to check if DSP MMU fault is intended for - * Bridge. - */ - tasklet_schedule(&deh_mgr_obj->dpc_tasklet); - - /* Reset err_info structure before use. */ - deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT; - deh_mgr_obj->err_info.dw_val1 = fault_addr >> 16; - deh_mgr_obj->err_info.dw_val2 = fault_addr & 0xFFFF; - deh_mgr_obj->err_info.dw_val3 = 0L; - /* Disable the MMU events, else once we clear it will - * start to raise INTs again */ - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_TRANSLATION_FAULT); - } else { - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_ALL_INTERRUPTS); - } - } - return IRQ_HANDLED; -} +int mmu_fault_isr(struct iommu *mmu) -/* - * ======== mmu_check_if_fault ======== - * Check to see if MMU Fault is valid TLB miss from DSP - * Note: This function is called from an ISR - */ -static bool mmu_check_if_fault(struct bridge_dev_context *dev_context) { + struct deh_mgr *dm; + u32 da; + + dev_get_deh_mgr(dev_get_first(), &dm); + + if (!dm) + return -EPERM; + + da = iommu_read_reg(mmu, MMU_FAULT_AD); + iommu_write_reg(mmu, 0, MMU_IRQENABLE); + dm->err_info.dw_val1 = da; + tasklet_schedule(&dm->dpc_tasklet); - bool ret = false; - hw_status hw_status_obj; - struct cfg_hostres *resources = dev_context->resources; - - if (!resources) { - dev_dbg(bridge, "%s: Failed to get Host Resources in\n", - __func__); - return ret; - } - hw_status_obj = - hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); - if (dmmu_event_mask == HW_MMU_TRANSLATION_FAULT) { - hw_mmu_fault_addr_read(resources->dw_dmmu_base, &fault_addr); - ret = true; - } - return ret; + return 0; } diff --git a/drivers/dsp/bridge/core/mmu_fault.h b/drivers/dsp/bridge/core/mmu_fault.h index 74db489..df3fba6 100644 --- a/drivers/dsp/bridge/core/mmu_fault.h +++ b/drivers/dsp/bridge/core/mmu_fault.h @@ -19,8 +19,6 @@ #ifndef MMU_FAULT_ #define MMU_FAULT_ -extern u32 fault_addr; - /* * ======== mmu_fault_dpc ======== * Deferred procedure call to handle DSP MMU fault. @@ -31,6 +29,7 @@ void mmu_fault_dpc(IN unsigned long pRefData); * ======== mmu_fault_isr ======== * ISR to be triggered by a DSP MMU fault interrupt. */ -irqreturn_t mmu_fault_isr(int irq, IN void *pRefData); +int mmu_fault_isr(struct iommu *mmu); + #endif /* MMU_FAULT_ */ diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 96cceea..89867e7 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -57,6 +57,7 @@ #include "_tiomap.h" #include "_tiomap_pwr.h" #include "tiomap_io.h" +#include "mmu_fault.h" /* Offset in shared mem to write to in order to synchronize start with DSP */ #define SHMSYNCOFFSET 4 /* GPP byte offset */ @@ -382,6 +383,7 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, goto end; } dev_context->dsp_mmu = mmu; + mmu->isr = mmu_fault_isr; sm_sg = dev_context->sh_s; sm_sg->seg0_da = iommu_kmap(mmu, sm_sg->seg0_da, sm_sg->seg0_pa, diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index ce13e6c..a03d172 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -18,6 +18,7 @@ /* ----------------------------------- Host OS */ #include +#include /* ----------------------------------- DSP/BIOS Bridge */ #include @@ -51,12 +52,6 @@ #include "_tiomap_pwr.h" #include - -static struct hw_mmu_map_attrs_t map_attrs = { HW_LITTLE_ENDIAN, - HW_ELEM_SIZE16BIT, - HW_MMU_CPUES -}; - static void *dummy_va_addr; int bridge_deh_create(struct deh_mgr **ret_deh_mgr, @@ -154,10 +149,10 @@ int bridge_deh_register_notify(struct deh_mgr *deh_mgr, u32 event_mask, void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) { struct bridge_dev_context *dev_context; - int status = 0; u32 hw_mmu_max_tlb_count = 31; struct cfg_hostres *resources; - hw_status hw_status_obj; + u32 fault_addr, tmp; + struct iotlb_entry e; if (!deh_mgr) return; @@ -181,6 +176,9 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) break; case DSP_MMUFAULT: /* MMU fault routine should have set err info structure. */ + fault_addr = iommu_read_reg(dev_context->dsp_mmu, + MMU_FAULT_AD); + deh_mgr->err_info.dw_err_mask = DSP_MMUFAULT; dev_err(bridge, "%s: %s, err_info = 0x%x\n", __func__, "DSP_MMUFAULT", dwErrInfo); @@ -206,21 +204,18 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) dev_context->num_tlb_entries = dev_context->fixed_tlb_entries; } - if (DSP_SUCCEEDED(status)) { - hw_status_obj = - hw_mmu_tlb_add(resources->dw_dmmu_base, - virt_to_phys(dummy_va_addr), fault_addr, - HW_PAGE_SIZE4KB, 1, - &map_attrs, HW_SET, HW_SET); - } + dsp_iotlb_init(&e, fault_addr & PAGE_MASK, + virt_to_phys(dummy_va_addr), IOVMF_PGSZ_4K); + load_iotlb_entry(dev_context->dsp_mmu, &e); + dsp_clk_enable(DSP_CLK_GPT8); dsp_gpt_wait_overflow(DSP_CLK_GPT8, 0xfffffffe); - /* Clear MMU interrupt */ - hw_mmu_event_ack(resources->dw_dmmu_base, - HW_MMU_TRANSLATION_FAULT); + tmp = iommu_read_reg(dev_context->dsp_mmu, MMU_IRQSTATUS); + iommu_write_reg(dev_context->dsp_mmu, tmp, MMU_IRQSTATUS); + dump_dsp_stack(deh_mgr->hbridge_context); dsp_clk_disable(DSP_CLK_GPT8); break; From patchwork Thu Jul 1 00:20:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 108990 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o610DYa5017455 for ; Thu, 1 Jul 2010 00:13:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932358Ab0GAAMb (ORCPT ); Wed, 30 Jun 2010 20:12:31 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:48436 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932277Ab0GAALo (ORCPT ); Wed, 30 Jun 2010 20:11:44 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o610Bd3I012513 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 30 Jun 2010 19:11:39 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o610Bc5n010937; Wed, 30 Jun 2010 19:11:38 -0500 (CDT) Received: from localhost (x0095840-desktop.am.dhcp.ti.com [128.247.77.44]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o610BcP08754; Wed, 30 Jun 2010 19:11:38 -0500 (CDT) From: Fernando Guzman Lugo To: , Cc: , , , , Fernando Guzman Lugo Subject: [PATCH 4/9] dspbridge: remove custom mmu code from tiomap3430.c Date: Wed, 30 Jun 2010 19:20:55 -0500 Message-Id: <1277943660-4112-5-git-send-email-x0095840@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277943660-4112-4-git-send-email-x0095840@ti.com> References: <1277943660-4112-1-git-send-email-x0095840@ti.com> <1277943660-4112-2-git-send-email-x0095840@ti.com> <1277943660-4112-3-git-send-email-x0095840@ti.com> <1277943660-4112-4-git-send-email-x0095840@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 00:13:36 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/_tiomap.h b/drivers/dsp/bridge/core/_tiomap.h index 4aa2358..c41fd8e 100644 --- a/drivers/dsp/bridge/core/_tiomap.h +++ b/drivers/dsp/bridge/core/_tiomap.h @@ -356,7 +356,6 @@ struct bridge_dev_context { /* TC Settings */ bool tc_word_swap_on; /* Traffic Controller Word Swap */ - struct pg_table_attrs *pt_attrs; u32 dsp_per_clks; }; diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 88f5167..96cceea 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -105,56 +105,9 @@ static int bridge_dev_create(OUT struct bridge_dev_context static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, u32 dw_cmd, IN OUT void *pargs); static int bridge_dev_destroy(struct bridge_dev_context *dev_context); -static u32 user_va2_pa(struct mm_struct *mm, u32 address); -static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, - u32 va, u32 size, - struct hw_mmu_map_attrs_t *map_attrs); -static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va, - u32 size, struct hw_mmu_map_attrs_t *attrs); -static int mem_map_vmalloc(struct bridge_dev_context *hDevContext, - u32 ul_mpu_addr, u32 ulVirtAddr, - u32 ul_num_bytes, - struct hw_mmu_map_attrs_t *hw_attrs); bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr); -/* ----------------------------------- Globals */ - -/* Attributes of L2 page tables for DSP MMU */ -struct page_info { - u32 num_entries; /* Number of valid PTEs in the L2 PT */ -}; - -/* Attributes used to manage the DSP MMU page tables */ -struct pg_table_attrs { - spinlock_t pg_lock; /* Critical section object handle */ - - u32 l1_base_pa; /* Physical address of the L1 PT */ - u32 l1_base_va; /* Virtual address of the L1 PT */ - u32 l1_size; /* Size of the L1 PT */ - u32 l1_tbl_alloc_pa; - /* Physical address of Allocated mem for L1 table. May not be aligned */ - u32 l1_tbl_alloc_va; - /* Virtual address of Allocated mem for L1 table. May not be aligned */ - u32 l1_tbl_alloc_sz; - /* Size of consistent memory allocated for L1 table. - * May not be aligned */ - - u32 l2_base_pa; /* Physical address of the L2 PT */ - u32 l2_base_va; /* Virtual address of the L2 PT */ - u32 l2_size; /* Size of the L2 PT */ - u32 l2_tbl_alloc_pa; - /* Physical address of Allocated mem for L2 table. May not be aligned */ - u32 l2_tbl_alloc_va; - /* Virtual address of Allocated mem for L2 table. May not be aligned */ - u32 l2_tbl_alloc_sz; - /* Size of consistent memory allocated for L2 table. - * May not be aligned */ - - u32 l2_num_pages; /* Number of allocated L2 PT */ - /* Array [l2_num_pages] of L2 PT info structs */ - struct page_info *pg_info; -}; /* * This Bridge driver's function interface table. @@ -210,32 +163,6 @@ static struct bridge_drv_interface drv_interface_fxns = { bridge_msg_set_queue_id, }; -static inline void tlb_flush_all(const void __iomem *base) -{ - __raw_writeb(__raw_readb(base + MMU_GFLUSH) | 1, base + MMU_GFLUSH); -} - -static inline void flush_all(struct bridge_dev_context *dev_context) -{ - if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION || - dev_context->dw_brd_state == BRD_HIBERNATION) - wake_dsp(dev_context, NULL); - - tlb_flush_all(dev_context->dw_dsp_mmu_base); -} - -static void bad_page_dump(u32 pa, struct page *pg) -{ - pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa); - pr_emerg("Bad page state in process '%s'\n" - "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n" - "Backtrace:\n", - current->comm, pg, (int)(2 * sizeof(unsigned long)), - (unsigned long)pg->flags, pg->mapping, - page_mapcount(pg), page_count(pg)); - dump_stack(); -} - /* * ======== bridge_drv_entry ======== * purpose: @@ -637,7 +564,6 @@ static int bridge_brd_stop(struct bridge_dev_context *hDevContext) { int status = 0; struct bridge_dev_context *dev_context = hDevContext; - struct pg_table_attrs *pt_attrs; u32 dsp_pwr_state; int clk_status; struct dspbridge_platform_data *pdata = @@ -677,15 +603,6 @@ static int bridge_brd_stop(struct bridge_dev_context *hDevContext) dsp_wdt_enable(false); - /* This is a good place to clear the MMU page tables as well */ - if (dev_context->pt_attrs) { - pt_attrs = dev_context->pt_attrs; - memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size); - memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size); - memset((u8 *) pt_attrs->pg_info, 0x00, - (pt_attrs->l2_num_pages * sizeof(struct page_info))); - } - /* Reset DSP */ (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, OMAP3430_RST1_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); @@ -725,7 +642,6 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) { int status = 0; struct bridge_dev_context *dev_context = hDevContext; - struct pg_table_attrs *pt_attrs; int clk_status; struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; @@ -747,15 +663,6 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) dev_context->dw_brd_state = BRD_STOPPED; /* update board state */ - /* This is a good place to clear the MMU page tables as well */ - if (dev_context->pt_attrs) { - pt_attrs = dev_context->pt_attrs; - memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size); - memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size); - memset((u8 *) pt_attrs->pg_info, 0x00, - (pt_attrs->l2_num_pages * sizeof(struct page_info))); - } - /* Reset DSP */ (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, OMAP3430_RST1_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); @@ -836,10 +743,6 @@ static int bridge_dev_create(OUT struct bridge_dev_context struct bridge_dev_context *dev_context = NULL; s32 entry_ndx; struct cfg_hostres *resources = pConfig; - struct pg_table_attrs *pt_attrs; - u32 pg_tbl_pa; - u32 pg_tbl_va; - u32 align_size; struct drv_data *drv_datap = dev_get_drvdata(bridge); /* Allocate and initialize a data structure to contain the bridge driver @@ -871,97 +774,11 @@ static int bridge_dev_create(OUT struct bridge_dev_context if (!dev_context->dw_dsp_base_addr) status = -EPERM; - pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL); - if (pt_attrs != NULL) { - /* Assuming that we use only DSP's memory map - * until 0x4000:0000 , we would need only 1024 - * L1 enties i.e L1 size = 4K */ - pt_attrs->l1_size = 0x1000; - align_size = pt_attrs->l1_size; - /* Align sizes are expected to be power of 2 */ - /* we like to get aligned on L1 table size */ - pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size, - align_size, &pg_tbl_pa); - - /* Check if the PA is aligned for us */ - if ((pg_tbl_pa) & (align_size - 1)) { - /* PA not aligned to page table size , - * try with more allocation and align */ - mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa, - pt_attrs->l1_size); - /* we like to get aligned on L1 table size */ - pg_tbl_va = - (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2, - align_size, &pg_tbl_pa); - /* We should be able to get aligned table now */ - pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa; - pt_attrs->l1_tbl_alloc_va = pg_tbl_va; - pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2; - /* Align the PA to the next 'align' boundary */ - pt_attrs->l1_base_pa = - ((pg_tbl_pa) + - (align_size - 1)) & (~(align_size - 1)); - pt_attrs->l1_base_va = - pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa); - } else { - /* We got aligned PA, cool */ - pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa; - pt_attrs->l1_tbl_alloc_va = pg_tbl_va; - pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size; - pt_attrs->l1_base_pa = pg_tbl_pa; - pt_attrs->l1_base_va = pg_tbl_va; - } - if (pt_attrs->l1_base_va) - memset((u8 *) pt_attrs->l1_base_va, 0x00, - pt_attrs->l1_size); - - /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM + - * L4 pages */ - pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6); - pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE * - pt_attrs->l2_num_pages; - align_size = 4; /* Make it u32 aligned */ - /* we like to get aligned on L1 table size */ - pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size, - align_size, &pg_tbl_pa); - pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa; - pt_attrs->l2_tbl_alloc_va = pg_tbl_va; - pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size; - pt_attrs->l2_base_pa = pg_tbl_pa; - pt_attrs->l2_base_va = pg_tbl_va; - - if (pt_attrs->l2_base_va) - memset((u8 *) pt_attrs->l2_base_va, 0x00, - pt_attrs->l2_size); - - pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages * - sizeof(struct page_info), GFP_KERNEL); - dev_dbg(bridge, - "L1 pa %x, va %x, size %x\n L2 pa %x, va " - "%x, size %x\n", pt_attrs->l1_base_pa, - pt_attrs->l1_base_va, pt_attrs->l1_size, - pt_attrs->l2_base_pa, pt_attrs->l2_base_va, - pt_attrs->l2_size); - dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n", - pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info); - } - if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) && - (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL)) - dev_context->pt_attrs = pt_attrs; - else - status = -ENOMEM; - if (DSP_SUCCEEDED(status)) { - spin_lock_init(&pt_attrs->pg_lock); dev_context->tc_word_swap_on = drv_datap->tc_wordswapon; - - /* Set the Clock Divisor for the DSP module */ - udelay(5); /* MMU address is obtained from the host * resources struct */ dev_context->dw_dsp_mmu_base = resources->dw_dmmu_base; - } - if (DSP_SUCCEEDED(status)) { dev_context->hdev_obj = hdev_obj; dev_context->ul_int_mask = 0; /* Store current board state. */ @@ -970,23 +787,6 @@ static int bridge_dev_create(OUT struct bridge_dev_context /* Return ptr to our device state to the DSP API for storage */ *ppDevContext = dev_context; } else { - if (pt_attrs != NULL) { - kfree(pt_attrs->pg_info); - - if (pt_attrs->l2_tbl_alloc_va) { - mem_free_phys_mem((void *) - pt_attrs->l2_tbl_alloc_va, - pt_attrs->l2_tbl_alloc_pa, - pt_attrs->l2_tbl_alloc_sz); - } - if (pt_attrs->l1_tbl_alloc_va) { - mem_free_phys_mem((void *) - pt_attrs->l1_tbl_alloc_va, - pt_attrs->l1_tbl_alloc_pa, - pt_attrs->l1_tbl_alloc_sz); - } - } - kfree(pt_attrs); kfree(dev_context); } func_end: @@ -1054,7 +854,6 @@ static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, */ static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) { - struct pg_table_attrs *pt_attrs; int status = 0; struct bridge_dev_context *dev_context = (struct bridge_dev_context *) hDevContext; @@ -1068,23 +867,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) /* first put the device to stop state */ bridge_brd_delete(dev_context); - if (dev_context->pt_attrs) { - pt_attrs = dev_context->pt_attrs; - kfree(pt_attrs->pg_info); - - if (pt_attrs->l2_tbl_alloc_va) { - mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va, - pt_attrs->l2_tbl_alloc_pa, - pt_attrs->l2_tbl_alloc_sz); - } - if (pt_attrs->l1_tbl_alloc_va) { - mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va, - pt_attrs->l1_tbl_alloc_pa, - pt_attrs->l1_tbl_alloc_sz); - } - kfree(pt_attrs); - - } if (dev_context->resources) { host_res = dev_context->resources; @@ -1315,258 +1097,6 @@ int user_to_dsp_unmap(struct iommu *mmu, u32 da) } /* - * ======== user_va2_pa ======== - * Purpose: - * This function walks through the page tables to convert a userland - * virtual address to physical address - */ -static u32 user_va2_pa(struct mm_struct *mm, u32 address) -{ - pgd_t *pgd; - pmd_t *pmd; - pte_t *ptep, pte; - - pgd = pgd_offset(mm, address); - if (!(pgd_none(*pgd) || pgd_bad(*pgd))) { - pmd = pmd_offset(pgd, address); - if (!(pmd_none(*pmd) || pmd_bad(*pmd))) { - ptep = pte_offset_map(pmd, address); - if (ptep) { - pte = *ptep; - if (pte_present(pte)) - return pte & PAGE_MASK; - } - } - } - - return 0; -} - -/* - * ======== pte_update ======== - * This function calculates the optimum page-aligned addresses and sizes - * Caller must pass page-aligned values - */ -static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, - u32 va, u32 size, - struct hw_mmu_map_attrs_t *map_attrs) -{ - u32 i; - u32 all_bits; - u32 pa_curr = pa; - u32 va_curr = va; - u32 num_bytes = size; - struct bridge_dev_context *dev_context = hDevContext; - int status = 0; - u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB, - HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB - }; - - while (num_bytes && DSP_SUCCEEDED(status)) { - /* To find the max. page size with which both PA & VA are - * aligned */ - all_bits = pa_curr | va_curr; - - for (i = 0; i < 4; i++) { - if ((num_bytes >= page_size[i]) && ((all_bits & - (page_size[i] - - 1)) == 0)) { - status = - pte_set(dev_context->pt_attrs, pa_curr, - va_curr, page_size[i], map_attrs); - pa_curr += page_size[i]; - va_curr += page_size[i]; - num_bytes -= page_size[i]; - /* Don't try smaller sizes. Hopefully we have - * reached an address aligned to a bigger page - * size */ - break; - } - } - } - - return status; -} - -/* - * ======== pte_set ======== - * This function calculates PTE address (MPU virtual) to be updated - * It also manages the L2 page tables - */ -static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va, - u32 size, struct hw_mmu_map_attrs_t *attrs) -{ - u32 i; - u32 pte_val; - u32 pte_addr_l1; - u32 pte_size; - /* Base address of the PT that will be updated */ - u32 pg_tbl_va; - u32 l1_base_va; - /* Compiler warns that the next three variables might be used - * uninitialized in this function. Doesn't seem so. Working around, - * anyways. */ - u32 l2_base_va = 0; - u32 l2_base_pa = 0; - u32 l2_page_num = 0; - int status = 0; - - l1_base_va = pt->l1_base_va; - pg_tbl_va = l1_base_va; - if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) { - /* Find whether the L1 PTE points to a valid L2 PT */ - pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va); - if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) { - pte_val = *(u32 *) pte_addr_l1; - pte_size = hw_mmu_pte_size_l1(pte_val); - } else { - return -EPERM; - } - spin_lock(&pt->pg_lock); - if (pte_size == HW_MMU_COARSE_PAGE_SIZE) { - /* Get the L2 PA from the L1 PTE, and find - * corresponding L2 VA */ - l2_base_pa = hw_mmu_pte_coarse_l1(pte_val); - l2_base_va = - l2_base_pa - pt->l2_base_pa + pt->l2_base_va; - l2_page_num = - (l2_base_pa - - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE; - } else if (pte_size == 0) { - /* L1 PTE is invalid. Allocate a L2 PT and - * point the L1 PTE to it */ - /* Find a free L2 PT. */ - for (i = 0; (i < pt->l2_num_pages) && - (pt->pg_info[i].num_entries != 0); i++) - ;; - if (i < pt->l2_num_pages) { - l2_page_num = i; - l2_base_pa = pt->l2_base_pa + (l2_page_num * - HW_MMU_COARSE_PAGE_SIZE); - l2_base_va = pt->l2_base_va + (l2_page_num * - HW_MMU_COARSE_PAGE_SIZE); - /* Endianness attributes are ignored for - * HW_MMU_COARSE_PAGE_SIZE */ - status = - hw_mmu_pte_set(l1_base_va, l2_base_pa, va, - HW_MMU_COARSE_PAGE_SIZE, - attrs); - } else { - status = -ENOMEM; - } - } else { - /* Found valid L1 PTE of another size. - * Should not overwrite it. */ - status = -EPERM; - } - if (DSP_SUCCEEDED(status)) { - pg_tbl_va = l2_base_va; - if (size == HW_PAGE_SIZE64KB) - pt->pg_info[l2_page_num].num_entries += 16; - else - pt->pg_info[l2_page_num].num_entries++; - dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum " - "%x, num_entries %x\n", l2_base_va, - l2_base_pa, l2_page_num, - pt->pg_info[l2_page_num].num_entries); - } - spin_unlock(&pt->pg_lock); - } - if (DSP_SUCCEEDED(status)) { - dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n", - pg_tbl_va, pa, va, size); - dev_dbg(bridge, "PTE: endianism %x, element_size %x, " - "mixed_size %x\n", attrs->endianism, - attrs->element_size, attrs->mixed_size); - status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs); - } - - return status; -} - -/* Memory map kernel VA -- memory allocated with vmalloc */ -static int mem_map_vmalloc(struct bridge_dev_context *dev_context, - u32 ul_mpu_addr, u32 ulVirtAddr, - u32 ul_num_bytes, - struct hw_mmu_map_attrs_t *hw_attrs) -{ - int status = 0; - struct page *page[1]; - u32 i; - u32 pa_curr; - u32 pa_next; - u32 va_curr; - u32 size_curr; - u32 num_pages; - u32 pa; - u32 num_of4k_pages; - u32 temp = 0; - - /* - * Do Kernel va to pa translation. - * Combine physically contiguous regions to reduce TLBs. - * Pass the translated pa to pte_update. - */ - num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */ - i = 0; - va_curr = ul_mpu_addr; - page[0] = vmalloc_to_page((void *)va_curr); - pa_next = page_to_phys(page[0]); - while (DSP_SUCCEEDED(status) && (i < num_pages)) { - /* - * Reuse pa_next from the previous iteraion to avoid - * an extra va2pa call - */ - pa_curr = pa_next; - size_curr = PAGE_SIZE; - /* - * If the next page is physically contiguous, - * map it with the current one by increasing - * the size of the region to be mapped - */ - while (++i < num_pages) { - page[0] = - vmalloc_to_page((void *)(va_curr + size_curr)); - pa_next = page_to_phys(page[0]); - - if (pa_next == (pa_curr + size_curr)) - size_curr += PAGE_SIZE; - else - break; - - } - if (pa_next == 0) { - status = -ENOMEM; - break; - } - pa = pa_curr; - num_of4k_pages = size_curr / HW_PAGE_SIZE4KB; - while (temp++ < num_of4k_pages) { - get_page(PHYS_TO_PAGE(pa)); - pa += HW_PAGE_SIZE4KB; - } - status = pte_update(dev_context, pa_curr, ulVirtAddr + - (va_curr - ul_mpu_addr), size_curr, - hw_attrs); - va_curr += size_curr; - } - if (DSP_SUCCEEDED(status)) - status = 0; - else - status = -EPERM; - - /* - * In any case, flush the TLB - * This is called from here instead from pte_update to avoid unnecessary - * repetition while mapping non-contiguous physical regions of a virtual - * region - */ - flush_all(dev_context); - dev_dbg(bridge, "%s status %x\n", __func__, status); - return status; -} - -/* * ======== wait_for_start ======== * Wait for the singal from DSP that it has started, or time out. */ From patchwork Thu Jul 1 00:20:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 108991 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o610DYa6017455 for ; Thu, 1 Jul 2010 00:13:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932334Ab0GAAMb (ORCPT ); Wed, 30 Jun 2010 20:12:31 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:38024 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932242Ab0GAALo (ORCPT ); Wed, 30 Jun 2010 20:11:44 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o610BcZF019818 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 30 Jun 2010 19:11:38 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o610BcWa021340; Wed, 30 Jun 2010 19:11:38 -0500 (CDT) Received: from localhost (x0095840-desktop.am.dhcp.ti.com [128.247.77.44]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o610BbP08742; Wed, 30 Jun 2010 19:11:37 -0500 (CDT) From: Fernando Guzman Lugo To: , Cc: , , , , Fernando Guzman Lugo Subject: [PATCH 1/9] dspbridge: replace iommu custom for opensource implementation Date: Wed, 30 Jun 2010 19:20:52 -0500 Message-Id: <1277943660-4112-2-git-send-email-x0095840@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277943660-4112-1-git-send-email-x0095840@ti.com> References: <1277943660-4112-1-git-send-email-x0095840@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 00:13:36 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/_tiomap.h b/drivers/dsp/bridge/core/_tiomap.h index bf0164e..d13677a 100644 --- a/drivers/dsp/bridge/core/_tiomap.h +++ b/drivers/dsp/bridge/core/_tiomap.h @@ -23,6 +23,8 @@ #include #include #include +#include +#include #include #include #include /* for bridge_ioctl_extproc defn */ @@ -330,6 +332,7 @@ struct bridge_dev_context { u32 dw_internal_size; /* Internal memory size */ struct omap_mbox *mbox; /* Mail box handle */ + struct iommu *dsp_mmu; /* iommu for iva2 handler */ struct cfg_hostres *resources; /* Host Resources */ @@ -374,4 +377,17 @@ extern s32 dsp_debug; */ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val); +static inline void dsp_iotlb_init(struct iotlb_entry *e, u32 da, u32 pa, + u32 pgsz) +{ + e->da = da; + e->pa = pa; + e->valid = 1; + e->prsvd = 1; + e->pgsz = pgsz & MMU_CAM_PGSZ_MASK; + e->endian = MMU_RAM_ENDIAN_LITTLE; + e->elsz = MMU_RAM_ELSZ_32; + e->mixed = 0; +} + #endif /* _TIOMAP_ */ diff --git a/drivers/dsp/bridge/core/io_sm.c b/drivers/dsp/bridge/core/io_sm.c index 7fb840d..1f47f8b 100644 --- a/drivers/dsp/bridge/core/io_sm.c +++ b/drivers/dsp/bridge/core/io_sm.c @@ -290,6 +290,8 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) struct cod_manager *cod_man; struct chnl_mgr *hchnl_mgr; struct msg_mgr *hmsg_mgr; + struct iommu *mmu; + struct iotlb_entry e; u32 ul_shm_base; u32 ul_shm_base_offset; u32 ul_shm_limit; @@ -312,7 +314,6 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) struct bridge_ioctl_extproc ae_proc[BRDIOCTL_NUMOFMMUTLB]; struct cfg_hostres *host_res; struct bridge_dev_context *pbridge_context; - u32 map_attrs; u32 shm0_end; u32 ul_dyn_ext_base; u32 ul_seg1_size = 0; @@ -336,6 +337,21 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) status = -EFAULT; goto func_end; } + + mmu = pbridge_context->dsp_mmu; + + if (mmu) + iommu_put(mmu); + mmu = iommu_get("iva2"); + + if (IS_ERR_OR_NULL(mmu)) { + pr_err("Error in iommu_get\n"); + pbridge_context->dsp_mmu = NULL; + status = -EFAULT; + goto func_end; + } + pbridge_context->dsp_mmu = mmu; + status = dev_get_cod_mgr(hio_mgr->hdev_obj, &cod_man); if (!cod_man) { status = -EFAULT; @@ -477,55 +493,16 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) gpp_va_curr = ul_gpp_va; num_bytes = ul_seg1_size; - /* - * Try to fit into TLB entries. If not possible, push them to page - * tables. It is quite possible that if sections are not on - * bigger page boundary, we may end up making several small pages. - * So, push them onto page tables, if that is the case. - */ - map_attrs = 0x00000000; - map_attrs = DSP_MAPLITTLEENDIAN; - map_attrs |= DSP_MAPPHYSICALADDR; - map_attrs |= DSP_MAPELEMSIZE32; - map_attrs |= DSP_MAPDONOTLOCK; - - while (num_bytes) { - /* - * To find the max. page size with which both PA & VA are - * aligned. - */ - all_bits = pa_curr | va_curr; - dev_dbg(bridge, "all_bits %x, pa_curr %x, va_curr %x, " - "num_bytes %x\n", all_bits, pa_curr, va_curr, - num_bytes); - for (i = 0; i < 4; i++) { - if ((num_bytes >= page_size[i]) && ((all_bits & - (page_size[i] - - 1)) == 0)) { - status = - hio_mgr->intf_fxns-> - pfn_brd_mem_map(hio_mgr->hbridge_context, - pa_curr, va_curr, - page_size[i], map_attrs, - NULL); - if (DSP_FAILED(status)) - goto func_end; - pa_curr += page_size[i]; - va_curr += page_size[i]; - gpp_va_curr += page_size[i]; - num_bytes -= page_size[i]; - /* - * Don't try smaller sizes. Hopefully we have - * reached an address aligned to a bigger page - * size. - */ - break; - } - } + va_curr = iommu_kmap(mmu, va_curr, pa_curr, num_bytes, + IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32); + if (IS_ERR_VALUE(va_curr)) { + status = (int)va_curr; + goto func_end; } - pa_curr += ul_pad_size; - va_curr += ul_pad_size; - gpp_va_curr += ul_pad_size; + + pa_curr += ul_pad_size + num_bytes; + va_curr += ul_pad_size + num_bytes; + gpp_va_curr += ul_pad_size + num_bytes; /* Configure the TLB entries for the next cacheable segment */ num_bytes = ul_seg_size; @@ -567,22 +544,6 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) ae_proc[ndx].ul_dsp_va * hio_mgr->word_size, page_size[i]); ndx++; - } else { - status = - hio_mgr->intf_fxns-> - pfn_brd_mem_map(hio_mgr->hbridge_context, - pa_curr, va_curr, - page_size[i], map_attrs, - NULL); - dev_dbg(bridge, - "shm MMU PTE entry PA %x" - " VA %x DSP_VA %x Size %x\n", - ae_proc[ndx].ul_gpp_pa, - ae_proc[ndx].ul_gpp_va, - ae_proc[ndx].ul_dsp_va * - hio_mgr->word_size, page_size[i]); - if (DSP_FAILED(status)) - goto func_end; } pa_curr += page_size[i]; va_curr += page_size[i]; @@ -635,35 +596,20 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) "DSP_VA 0x%x\n", ae_proc[ndx].ul_gpp_pa, ae_proc[ndx].ul_dsp_va); ndx++; - } else { - status = hio_mgr->intf_fxns->pfn_brd_mem_map - (hio_mgr->hbridge_context, - hio_mgr->ext_proc_info.ty_tlb[i]. - ul_gpp_phys, - hio_mgr->ext_proc_info.ty_tlb[i]. - ul_dsp_virt, 0x100000, map_attrs, - NULL); } } if (DSP_FAILED(status)) goto func_end; } - map_attrs = 0x00000000; - map_attrs = DSP_MAPLITTLEENDIAN; - map_attrs |= DSP_MAPPHYSICALADDR; - map_attrs |= DSP_MAPELEMSIZE32; - map_attrs |= DSP_MAPDONOTLOCK; + dsp_iotlb_init(&e, 0, 0, IOVMF_PGSZ_4K); /* Map the L4 peripherals */ i = 0; while (l4_peripheral_table[i].phys_addr) { - status = hio_mgr->intf_fxns->pfn_brd_mem_map - (hio_mgr->hbridge_context, l4_peripheral_table[i].phys_addr, - l4_peripheral_table[i].dsp_virt_addr, HW_PAGE_SIZE4KB, - map_attrs, NULL); - if (DSP_FAILED(status)) - goto func_end; + e.da = l4_peripheral_table[i].dsp_virt_addr; + e.pa = l4_peripheral_table[i].phys_addr; + iopgtable_store_entry(mmu, &e); i++; } diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 35c6678..e750767 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -373,6 +373,8 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, { int status = 0; struct bridge_dev_context *dev_context = hDevContext; + struct iommu *mmu; + struct iotlb_entry en; u32 dw_sync_addr = 0; u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */ u32 ul_shm_base_virt; /* Dsp Virt SM base addr */ @@ -392,6 +394,8 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; + mmu = dev_context->dsp_mmu; + /* The device context contains all the mmu setup info from when the * last dsp base image was loaded. The first entry is always * SHMMEM base. */ @@ -442,30 +446,10 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, } } if (DSP_SUCCEEDED(status)) { - /* Reset and Unreset the RST2, so that BOOTADDR is copied to - * IVA2 SYSC register */ - (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, - OMAP3430_RST2_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); - udelay(100); - (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, 0, - OMAP3430_IVA2_MOD, RM_RSTCTRL); - udelay(100); - - /* Disbale the DSP MMU */ - hw_mmu_disable(resources->dw_dmmu_base); - /* Disable TWL */ - hw_mmu_twl_disable(resources->dw_dmmu_base); - /* Only make TLB entry if both addresses are non-zero */ for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) { struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx]; - struct hw_mmu_map_attrs_t map_attrs = { - .endianism = e->endianism, - .element_size = e->elem_size, - .mixed_size = e->mixed_mode, - }; - if (!e->ul_gpp_pa || !e->ul_dsp_va) continue; @@ -476,13 +460,9 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, e->ul_dsp_va, e->ul_size); - hw_mmu_tlb_add(dev_context->dw_dsp_mmu_base, - e->ul_gpp_pa, - e->ul_dsp_va, - e->ul_size, - itmp_entry_ndx, - &map_attrs, 1, 1); - + dsp_iotlb_init(&en, e->ul_dsp_va, e->ul_gpp_pa, + bytes_to_iopgsz(e->ul_size)); + iopgtable_store_entry(mmu, &en); itmp_entry_ndx++; } } @@ -490,19 +470,6 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, /* Lock the above TLB entries and get the BIOS and load monitor timer * information */ if (DSP_SUCCEEDED(status)) { - hw_mmu_num_locked_set(resources->dw_dmmu_base, itmp_entry_ndx); - hw_mmu_victim_num_set(resources->dw_dmmu_base, itmp_entry_ndx); - hw_mmu_ttb_set(resources->dw_dmmu_base, - dev_context->pt_attrs->l1_base_pa); - hw_mmu_twl_enable(resources->dw_dmmu_base); - /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */ - - temp = __raw_readl((resources->dw_dmmu_base) + 0x10); - temp = (temp & 0xFFFFFFEF) | 0x11; - __raw_writel(temp, (resources->dw_dmmu_base) + 0x10); - - /* Let the DSP MMU run */ - hw_mmu_enable(resources->dw_dmmu_base); /* Enable the BIOS clock */ (void)dev_get_symbol(dev_context->hdev_obj, @@ -510,9 +477,6 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, (void)dev_get_symbol(dev_context->hdev_obj, BRIDGEINIT_LOADMON_GPTIMER, &ul_load_monitor_timer); - } - - if (DSP_SUCCEEDED(status)) { if (ul_load_monitor_timer != 0xFFFF) { clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) | ul_load_monitor_timer; @@ -593,9 +557,6 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, /* Let DSP go */ dev_dbg(bridge, "%s Unreset\n", __func__); - /* Enable DSP MMU Interrupts */ - hw_mmu_event_enable(resources->dw_dmmu_base, - HW_MMU_ALL_INTERRUPTS); /* release the RST1, DSP starts executing now .. */ (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, 0, OMAP3430_IVA2_MOD, RM_RSTCTRL); @@ -754,6 +715,9 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) omap_mbox_put(dev_context->mbox); dev_context->mbox = NULL; } + + if (dev_context->dsp_mmu) + dev_context->dsp_mmu = (iommu_put(dev_context->dsp_mmu), NULL); /* Reset IVA2 clocks*/ (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2 | OMAP3430_RST2_IVA2 | OMAP3430_RST3_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); @@ -1199,219 +1163,67 @@ static int bridge_brd_mem_write(struct bridge_dev_context *hDevContext, * * TODO: Disable MMU while updating the page tables (but that'll stall DSP) */ -static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext, - u32 ul_mpu_addr, u32 ulVirtAddr, - u32 ul_num_bytes, u32 ul_map_attr, - struct page **mapped_pages) +static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctx, + u32 uva, u32 da, u32 size, u32 attr, + struct page **usr_pgs) { - u32 attrs; - int status = 0; - struct bridge_dev_context *dev_context = hDevContext; - struct hw_mmu_map_attrs_t hw_attrs; + int res, w; + unsigned pages, i; + struct iommu *mmu = dev_ctx->dsp_mmu; struct vm_area_struct *vma; struct mm_struct *mm = current->mm; - u32 write = 0; - u32 num_usr_pgs = 0; - struct page *mapped_page, *pg; - s32 pg_num; - u32 va = ulVirtAddr; - struct task_struct *curr_task = current; - u32 pg_i = 0; - u32 mpu_addr, pa; - - dev_dbg(bridge, - "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n", - __func__, hDevContext, ul_mpu_addr, ulVirtAddr, ul_num_bytes, - ul_map_attr); - if (ul_num_bytes == 0) - return -EINVAL; + struct sg_table *sgt; + struct scatterlist *sg; - if (ul_map_attr & DSP_MAP_DIR_MASK) { - attrs = ul_map_attr; - } else { - /* Assign default attributes */ - attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16); - } - /* Take mapping properties */ - if (attrs & DSP_MAPBIGENDIAN) - hw_attrs.endianism = HW_BIG_ENDIAN; - else - hw_attrs.endianism = HW_LITTLE_ENDIAN; - - hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t) - ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2); - /* Ignore element_size if mixed_size is enabled */ - if (hw_attrs.mixed_size == 0) { - if (attrs & DSP_MAPELEMSIZE8) { - /* Size is 8 bit */ - hw_attrs.element_size = HW_ELEM_SIZE8BIT; - } else if (attrs & DSP_MAPELEMSIZE16) { - /* Size is 16 bit */ - hw_attrs.element_size = HW_ELEM_SIZE16BIT; - } else if (attrs & DSP_MAPELEMSIZE32) { - /* Size is 32 bit */ - hw_attrs.element_size = HW_ELEM_SIZE32BIT; - } else if (attrs & DSP_MAPELEMSIZE64) { - /* Size is 64 bit */ - hw_attrs.element_size = HW_ELEM_SIZE64BIT; - } else { - /* - * Mixedsize isn't enabled, so size can't be - * zero here - */ - return -EINVAL; - } - } - if (attrs & DSP_MAPDONOTLOCK) - hw_attrs.donotlockmpupage = 1; - else - hw_attrs.donotlockmpupage = 0; + if (!size || !usr_pgs) + return -EINVAL; - if (attrs & DSP_MAPVMALLOCADDR) { - return mem_map_vmalloc(hDevContext, ul_mpu_addr, ulVirtAddr, - ul_num_bytes, &hw_attrs); - } - /* - * Do OS-specific user-va to pa translation. - * Combine physically contiguous regions to reduce TLBs. - * Pass the translated pa to pte_update. - */ - if ((attrs & DSP_MAPPHYSICALADDR)) { - status = pte_update(dev_context, ul_mpu_addr, ulVirtAddr, - ul_num_bytes, &hw_attrs); - goto func_cont; - } + pages = size / PG_SIZE4K; - /* - * Important Note: ul_mpu_addr is mapped from user application process - * to current process - it must lie completely within the current - * virtual memory address space in order to be of use to us here! - */ down_read(&mm->mmap_sem); - vma = find_vma(mm, ul_mpu_addr); - if (vma) - dev_dbg(bridge, - "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, " - "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr, - ul_num_bytes, vma->vm_start, vma->vm_end, - vma->vm_flags); - - /* - * It is observed that under some circumstances, the user buffer is - * spread across several VMAs. So loop through and check if the entire - * user buffer is covered - */ - while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) { - /* jump to the next VMA region */ + vma = find_vma(mm, uva); + while (vma && (uva + size > vma->vm_end)) vma = find_vma(mm, vma->vm_end + 1); - dev_dbg(bridge, - "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, " - "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr, - ul_num_bytes, vma->vm_start, vma->vm_end, - vma->vm_flags); - } + if (!vma) { pr_err("%s: Failed to get VMA region for 0x%x (%d)\n", - __func__, ul_mpu_addr, ul_num_bytes); - status = -EINVAL; + __func__, uva, size); up_read(&mm->mmap_sem); - goto func_cont; + return -EINVAL; } + if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE)) + w = 1; + res = get_user_pages(current, mm, uva, pages, w, 1, usr_pgs, NULL); + up_read(&mm->mmap_sem); + if (res < 0) + return res; - if (vma->vm_flags & VM_IO) { - num_usr_pgs = ul_num_bytes / PG_SIZE4K; - mpu_addr = ul_mpu_addr; - - /* Get the physical addresses for user buffer */ - for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) { - pa = user_va2_pa(mm, mpu_addr); - if (!pa) { - status = -EPERM; - pr_err("DSPBRIDGE: VM_IO mapping physical" - "address is invalid\n"); - break; - } - if (pfn_valid(__phys_to_pfn(pa))) { - pg = PHYS_TO_PAGE(pa); - get_page(pg); - if (page_count(pg) < 1) { - pr_err("Bad page in VM_IO buffer\n"); - bad_page_dump(pa, pg); - } - } - status = pte_set(dev_context->pt_attrs, pa, - va, HW_PAGE_SIZE4KB, &hw_attrs); - if (DSP_FAILED(status)) - break; + sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); - va += HW_PAGE_SIZE4KB; - mpu_addr += HW_PAGE_SIZE4KB; - pa += HW_PAGE_SIZE4KB; - } - } else { - num_usr_pgs = ul_num_bytes / PG_SIZE4K; - if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE)) - write = 1; - - for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) { - pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1, - write, 1, &mapped_page, NULL); - if (pg_num > 0) { - if (page_count(mapped_page) < 1) { - pr_err("Bad page count after doing" - "get_user_pages on" - "user buffer\n"); - bad_page_dump(page_to_phys(mapped_page), - mapped_page); - } - status = pte_set(dev_context->pt_attrs, - page_to_phys(mapped_page), va, - HW_PAGE_SIZE4KB, &hw_attrs); - if (DSP_FAILED(status)) - break; - - if (mapped_pages) - mapped_pages[pg_i] = mapped_page; - - va += HW_PAGE_SIZE4KB; - ul_mpu_addr += HW_PAGE_SIZE4KB; - } else { - pr_err("DSPBRIDGE: get_user_pages FAILED," - "MPU addr = 0x%x," - "vma->vm_flags = 0x%lx," - "get_user_pages Err" - "Value = %d, Buffer" - "size=0x%x\n", ul_mpu_addr, - vma->vm_flags, pg_num, ul_num_bytes); - status = -EPERM; - break; - } - } - } - up_read(&mm->mmap_sem); -func_cont: - if (DSP_SUCCEEDED(status)) { - status = 0; - } else { - /* - * Roll out the mapped pages incase it failed in middle of - * mapping - */ - if (pg_i) { - bridge_brd_mem_un_map(dev_context, ulVirtAddr, - (pg_i * PG_SIZE4K)); - } - status = -EPERM; + if (!sgt) + return -ENOMEM; + + res = sg_alloc_table(sgt, pages, GFP_KERNEL); + + if (res < 0) + goto err_sg; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) + sg_set_page(sg, usr_pgs[i], PAGE_SIZE, 0); + + da = iommu_vmap(mmu, da, sgt, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32); + + if (IS_ERR_VALUE(da)) { + res = (int)da; + goto err_map; } - /* - * In any case, flush the TLB - * This is called from here instead from pte_update to avoid unnecessary - * repetition while mapping non-contiguous physical regions of a virtual - * region - */ - flush_all(dev_context); - dev_dbg(bridge, "%s status %x\n", __func__, status); - return status; + return 0; + +err_map: + sg_free_table(sgt); +err_sg: + kfree(sgt); + return res; } /* @@ -1422,196 +1234,27 @@ func_cont: * So, instead of looking up the PTE address for every 4K block, * we clear consecutive PTEs until we unmap all the bytes */ -static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, - u32 ulVirtAddr, u32 ul_num_bytes) +static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctx, + u32 da, u32 size) { - u32 l1_base_va; - u32 l2_base_va; - u32 l2_base_pa; - u32 l2_page_num; - u32 pte_val; - u32 pte_size; - u32 pte_count; - u32 pte_addr_l1; - u32 pte_addr_l2 = 0; - u32 rem_bytes; - u32 rem_bytes_l2; - u32 va_curr; - struct page *pg = NULL; - int status = 0; - struct bridge_dev_context *dev_context = hDevContext; - struct pg_table_attrs *pt = dev_context->pt_attrs; - u32 temp; - u32 paddr; - u32 numof4k_pages = 0; - - va_curr = ulVirtAddr; - rem_bytes = ul_num_bytes; - rem_bytes_l2 = 0; - l1_base_va = pt->l1_base_va; - pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr); - dev_dbg(bridge, "%s hDevContext %p, va %x, NumBytes %x l1_base_va %x, " - "pte_addr_l1 %x\n", __func__, hDevContext, ulVirtAddr, - ul_num_bytes, l1_base_va, pte_addr_l1); + unsigned i; + struct sg_table *sgt; + struct scatterlist *sg; - while (rem_bytes && (DSP_SUCCEEDED(status))) { - u32 va_curr_orig = va_curr; - /* Find whether the L1 PTE points to a valid L2 PT */ - pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr); - pte_val = *(u32 *) pte_addr_l1; - pte_size = hw_mmu_pte_size_l1(pte_val); - - if (pte_size != HW_MMU_COARSE_PAGE_SIZE) - goto skip_coarse_page; - - /* - * Get the L2 PA from the L1 PTE, and find - * corresponding L2 VA - */ - l2_base_pa = hw_mmu_pte_coarse_l1(pte_val); - l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va; - l2_page_num = - (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE; - /* - * Find the L2 PTE address from which we will start - * clearing, the number of PTEs to be cleared on this - * page, and the size of VA space that needs to be - * cleared on this L2 page - */ - pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr); - pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1); - pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32); - if (rem_bytes < (pte_count * PG_SIZE4K)) - pte_count = rem_bytes / PG_SIZE4K; - rem_bytes_l2 = pte_count * PG_SIZE4K; - - /* - * Unmap the VA space on this L2 PT. A quicker way - * would be to clear pte_count entries starting from - * pte_addr_l2. However, below code checks that we don't - * clear invalid entries or less than 64KB for a 64KB - * entry. Similar checking is done for L1 PTEs too - * below - */ - while (rem_bytes_l2 && (DSP_SUCCEEDED(status))) { - pte_val = *(u32 *) pte_addr_l2; - pte_size = hw_mmu_pte_size_l2(pte_val); - /* va_curr aligned to pte_size? */ - if (pte_size == 0 || rem_bytes_l2 < pte_size || - va_curr & (pte_size - 1)) { - status = -EPERM; - break; - } + if (!size) + return -EINVAL; - /* Collect Physical addresses from VA */ - paddr = (pte_val & ~(pte_size - 1)); - if (pte_size == HW_PAGE_SIZE64KB) - numof4k_pages = 16; - else - numof4k_pages = 1; - temp = 0; - while (temp++ < numof4k_pages) { - if (!pfn_valid(__phys_to_pfn(paddr))) { - paddr += HW_PAGE_SIZE4KB; - continue; - } - pg = PHYS_TO_PAGE(paddr); - if (page_count(pg) < 1) { - pr_info("DSPBRIDGE: UNMAP function: " - "COUNT 0 FOR PA 0x%x, size = " - "0x%x\n", paddr, ul_num_bytes); - bad_page_dump(paddr, pg); - } else { - SetPageDirty(pg); - page_cache_release(pg); - } - paddr += HW_PAGE_SIZE4KB; - } - if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size) - == RET_FAIL) { - status = -EPERM; - goto EXIT_LOOP; - } + sgt = iommu_vunmap(dev_ctx->dsp_mmu, da); + if (!sgt) + return -EFAULT; - status = 0; - rem_bytes_l2 -= pte_size; - va_curr += pte_size; - pte_addr_l2 += (pte_size >> 12) * sizeof(u32); - } - spin_lock(&pt->pg_lock); - if (rem_bytes_l2 == 0) { - pt->pg_info[l2_page_num].num_entries -= pte_count; - if (pt->pg_info[l2_page_num].num_entries == 0) { - /* - * Clear the L1 PTE pointing to the L2 PT - */ - if (hw_mmu_pte_clear(l1_base_va, va_curr_orig, - HW_MMU_COARSE_PAGE_SIZE) == - RET_OK) - status = 0; - else { - status = -EPERM; - spin_unlock(&pt->pg_lock); - goto EXIT_LOOP; - } - } - rem_bytes -= pte_count * PG_SIZE4K; - } else - status = -EPERM; + for_each_sg(sgt->sgl, sg, sgt->nents, i) + put_page(sg_page(sg)); - spin_unlock(&pt->pg_lock); - continue; -skip_coarse_page: - /* va_curr aligned to pte_size? */ - /* pte_size = 1 MB or 16 MB */ - if (pte_size == 0 || rem_bytes < pte_size || - va_curr & (pte_size - 1)) { - status = -EPERM; - break; - } + sg_free_table(sgt); + kfree(sgt); - if (pte_size == HW_PAGE_SIZE1MB) - numof4k_pages = 256; - else - numof4k_pages = 4096; - temp = 0; - /* Collect Physical addresses from VA */ - paddr = (pte_val & ~(pte_size - 1)); - while (temp++ < numof4k_pages) { - if (pfn_valid(__phys_to_pfn(paddr))) { - pg = PHYS_TO_PAGE(paddr); - if (page_count(pg) < 1) { - pr_info("DSPBRIDGE: UNMAP function: " - "COUNT 0 FOR PA 0x%x, size = " - "0x%x\n", paddr, ul_num_bytes); - bad_page_dump(paddr, pg); - } else { - SetPageDirty(pg); - page_cache_release(pg); - } - } - paddr += HW_PAGE_SIZE4KB; - } - if (hw_mmu_pte_clear(l1_base_va, va_curr, pte_size) == RET_OK) { - status = 0; - rem_bytes -= pte_size; - va_curr += pte_size; - } else { - status = -EPERM; - goto EXIT_LOOP; - } - } - /* - * It is better to flush the TLB here, so that any stale old entries - * get flushed - */ -EXIT_LOOP: - flush_all(dev_context); - dev_dbg(bridge, - "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x," - " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1, - pte_addr_l2, rem_bytes, rem_bytes_l2, status); - return status; + return 0; } /* diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 64e9366..ce13e6c 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -99,14 +99,6 @@ int bridge_deh_create(struct deh_mgr **ret_deh_mgr, deh_mgr->err_info.dw_val2 = 0L; deh_mgr->err_info.dw_val3 = 0L; - /* Install ISR function for DSP MMU fault */ - if ((request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0, - "DspBridge\tiommu fault", - (void *)deh_mgr)) == 0) - status = 0; - else - status = -EPERM; - err: if (DSP_FAILED(status)) { /* If create failed, cleanup */ @@ -131,8 +123,6 @@ int bridge_deh_destroy(struct deh_mgr *deh_mgr) ntfy_delete(deh_mgr->ntfy_obj); kfree(deh_mgr->ntfy_obj); } - /* Disable DSP MMU fault */ - free_irq(INT_DSP_MMU_IRQ, deh_mgr); /* Free DPC object */ tasklet_kill(&deh_mgr->dpc_tasklet); From patchwork Wed Jul 7 09:44:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110602 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679isGF027951 for ; Wed, 7 Jul 2010 09:44:54 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754651Ab0GGJox (ORCPT ); Wed, 7 Jul 2010 05:44:53 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:60235 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754022Ab0GGJow (ORCPT ); Wed, 7 Jul 2010 05:44:52 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRBT-000Jvk-3r; Wed, 07 Jul 2010 09:44:51 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1+n9sHAwsbvTIB2OLJX9M6n Subject: [PATCH 13/13] Add OMAP4 Panda Support To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: linux-omap@vger.kernel.org, David Anders Date: Wed, 07 Jul 2010 12:44:49 +0300 Message-ID: <20100707094449.2562.87272.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:54 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 84fecd0..b48bacf 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -238,6 +238,11 @@ config MACH_OMAP_4430SDP default y depends on ARCH_OMAP4 +config MACH_OMAP4_PANDA + bool "OMAP4 Panda Board" + default y + depends on ARCH_OMAP4 + config OMAP3_EMU bool "OMAP3 debugging peripherals" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d7be082..f5b4ff4 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -145,6 +145,8 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ hsmmc.o +obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c new file mode 100644 index 0000000..c03d1d5 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -0,0 +1,304 @@ +/* + * Board support file for OMAP4430 based PandaBoard. + * + * Copyright (C) 2010 Texas Instruments + * + * Author: David Anders + * + * Based on mach-omap2/board-4430sdp.c + * + * Author: Santosh Shilimkar + * + * Based on mach-omap2/board-3430sdp.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include "hsmmc.h" + + +static void __init omap4_panda_init_irq(void) +{ + omap2_init_common_hw(NULL, NULL); + gic_init_irq(); + omap_gpio_init(); +} + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_UTMI, + .mode = MUSB_PERIPHERAL, + .power = 100, +}; + +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .wires = 8, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + +static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.0", + }, + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", + }, +}; + +static int omap4_twl6030_hsmmc_late_init(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_mmc_platform_data *pdata = dev->platform_data; + + /* Setting MMC1 Card detect Irq */ + if (pdev->id == 0) + pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + + MMCDETECT_INTR_OFFSET; + return ret; +} + +static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *pdata = dev->platform_data; + + pdata->init = omap4_twl6030_hsmmc_late_init; +} + +static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + + omap2_hsmmc_init(controllers); + for (c = controllers; c->mmc; c++) + omap4_twl6030_hsmmc_set_late_init(c->dev); + + return 0; +} + +static struct regulator_init_data omap4_panda_vaux1 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vaux2 = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vaux3 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VMMC1 for MMC1 card */ +static struct regulator_init_data omap4_panda_vmmc = { + .constraints = { + .min_uV = 1200000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 2, + .consumer_supplies = omap4_panda_vmmc_supply, +}; + +static struct regulator_init_data omap4_panda_vpp = { + .constraints = { + .min_uV = 1800000, + .max_uV = 2500000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vusim = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2900000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vana = { + .constraints = { + .min_uV = 2100000, + .max_uV = 2100000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vcxio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vusb = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct twl4030_platform_data omap4_panda_twldata = { + .irq_base = TWL6030_IRQ_BASE, + .irq_end = TWL6030_IRQ_END, + + /* Regulators */ + .vmmc = &omap4_panda_vmmc, + .vpp = &omap4_panda_vpp, + .vusim = &omap4_panda_vusim, + .vana = &omap4_panda_vana, + .vcxio = &omap4_panda_vcxio, + .vdac = &omap4_panda_vdac, + .vusb = &omap4_panda_vusb, + .vaux1 = &omap4_panda_vaux1, + .vaux2 = &omap4_panda_vaux2, + .vaux3 = &omap4_panda_vaux3, +}; + +static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl6030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = OMAP44XX_IRQ_SYS_1N, + .platform_data = &omap4_panda_twldata, + }, +}; +static int __init omap4_panda_i2c_init(void) +{ + /* + * Phoenix Audio IC needs I2C1 to + * start with 400 KHz or less + */ + omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo, + ARRAY_SIZE(omap4_panda_i2c_boardinfo)); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + omap_register_i2c_bus(4, 400, NULL, 0); + return 0; +} +static void __init omap4_panda_init(void) +{ + int status; + + omap4_panda_i2c_init(); + omap_serial_init(); + omap4_twl6030_hsmmc_init(mmc); + /* OMAP4 Panda uses internal transceiver so register nop transceiver */ + usb_nop_xceiv_register(); + /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ + if (!cpu_is_omap44xx()) + usb_musb_init(&musb_board_data); +} + +static void __init omap4_panda_map_io(void) +{ + omap2_set_globals_443x(); + omap44xx_map_common_io(); +} + +MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") + /* Maintainer: David Anders - Texas Instruments Inc */ + .phys_io = 0x48000000, + .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap4_panda_map_io, + .init_irq = omap4_panda_init_irq, + .init_machine = omap4_panda_init, + .timer = &omap_timer, +MACHINE_END From patchwork Wed Jul 7 09:44:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110601 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679iokE027936 for ; Wed, 7 Jul 2010 09:44:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754552Ab0GGJot (ORCPT ); Wed, 7 Jul 2010 05:44:49 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:59340 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753498Ab0GGJos (ORCPT ); Wed, 7 Jul 2010 05:44:48 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRBP-000IMu-N0; Wed, 07 Jul 2010 09:44:47 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19/RJliTOq5m4d57/oV8o1v Subject: [PATCH 12/13] OMAP4: Add GPIO LED support for SDP board To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Hemanth V , linux-omap@vger.kernel.org Date: Wed, 07 Jul 2010 12:44:46 +0300 Message-ID: <20100707094446.2562.47199.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:50 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index eb1775e..f287461 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -40,6 +41,54 @@ #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 +static struct gpio_led sdp4430_gpio_leds[] = { + { + .name = "omap4:green:debug0", + .gpio = 61, + }, + { + .name = "omap4:green:debug1", + .gpio = 30, + }, + { + .name = "omap4:green:debug2", + .gpio = 7, + }, + { + .name = "omap4:green:debug3", + .gpio = 8, + }, + { + .name = "omap4:green:debug4", + .gpio = 50, + }, + { + .name = "omap4:blue:user", + .gpio = 169, + }, + { + .name = "omap4:red:user", + .gpio = 170, + }, + { + .name = "omap4:green:user", + .gpio = 139, + }, + +}; + +static struct gpio_led_platform_data sdp4430_led_data = { + .leds = sdp4430_gpio_leds, + .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), +}; + +static struct platform_device sdp4430_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &sdp4430_led_data, + }, +}; static struct spi_board_info sdp4430_spi_board_info[] __initdata = { { .modalias = "ks8851", @@ -112,6 +161,7 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, + &sdp4430_leds_gpio, }; static struct omap_lcd_config sdp4430_lcd_config __initdata = { From patchwork Wed Jul 7 09:44:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110600 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679ik3i027925 for ; Wed, 7 Jul 2010 09:44:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754624Ab0GGJop (ORCPT ); Wed, 7 Jul 2010 05:44:45 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:60103 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753498Ab0GGJoo (ORCPT ); Wed, 7 Jul 2010 05:44:44 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRBM-000JtC-7c; Wed, 07 Jul 2010 09:44:44 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19BAdyAyFvClz0wIHYaWlz2 Subject: [PATCH 11/13] omap4: Board changes for 4430sdp tmp105 temperature sensor To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: linux-omap@vger.kernel.org, Shubhrajyoti D Date: Wed, 07 Jul 2010 12:44:42 +0300 Message-ID: <20100707094442.2562.53424.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:46 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 216870b..eb1775e 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -357,6 +357,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { .platform_data = &sdp4430_twldata, }, }; +static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { + { + I2C_BOARD_INFO("tmp105", 0x48), + }, +}; static int __init omap4_i2c_init(void) { /* @@ -366,7 +371,8 @@ static int __init omap4_i2c_init(void) omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo, ARRAY_SIZE(sdp4430_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, NULL, 0); + omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, + ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); omap_register_i2c_bus(4, 400, NULL, 0); return 0; } From patchwork Sun May 16 15:45:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99968 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkHfc025161 for ; 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b=Z6K6RNrMcXlIETZKdpigxaZMh9eGeHXYh7IlAL/W49FRAaq3w3wAxV2mRgvrJ1HWLt Jzcs8U5fbAnV6i0or7VQvu3EGjscvLBGaZIhfA53MyHzEaVZXFXDTHHMznyAN1ywfBbv WKqXf164QSdFnY6A7a7fU+jIsX6sRXFFLDnLM= Received: by 10.87.29.33 with SMTP id g33mr6800152fgj.27.1274024776897; Sun, 16 May 2010 08:46:16 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id 4sm11649099fgg.22.2010.05.16.08.46.16 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:16 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 04/14] dspbridge: deh: free dummy page immediately Date: Sun, 16 May 2010 18:45:55 +0300 Message-Id: <1274024765-21076-5-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:19 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 605cec7..593a0e3 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -60,8 +60,6 @@ /* Max time to check for GP Timer IRQ */ #define GPTIMER_IRQ_WAIT_MAX_CNT 1000 -static void *dummy_va_addr; - static struct omap_dm_timer *timer; dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, @@ -203,6 +201,7 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) .element_size = HW_ELEM_SIZE16BIT, .mixed_size = HW_MMU_CPUES, }; + void *dummy_va_addr; if (!deh_mgr) return; @@ -259,6 +258,9 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) hw_mmu_event_ack(resources->dw_dmmu_base, HW_MMU_TRANSLATION_FAULT); dump_dsp_stack(dev_context); + + hw_mmu_disable(resources->dw_dmmu_base); + free_page((unsigned long)dummy_va_addr); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR case DSP_PWRERROR: @@ -321,6 +323,4 @@ dsp_status bridge_deh_get_info(struct deh_mgr *deh_mgr, void bridge_deh_release_dummy_mem(void) { - free_page((unsigned long)dummy_va_addr); - dummy_va_addr = NULL; } From patchwork Wed May 5 14:27:33 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97107 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5PB002693 for ; Wed, 5 May 2010 14:28:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934815Ab0EEO2K (ORCPT ); Wed, 5 May 2010 10:28:10 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34121 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934770Ab0EEO2G (ORCPT ); Wed, 5 May 2010 10:28:06 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ES3HP005919; Wed, 5 May 2010 09:28:04 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:02 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:02 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRF016232; Wed, 5 May 2010 17:28:01 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 13/21] OMAP: DSS2: Taal: Change probe error handling labels Date: Wed, 5 May 2010 17:27:33 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:02.0241 (UTC) FILETIME=[2B164B10:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:18 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index fa4c67b..e32424c 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -539,7 +539,7 @@ static int taal_probe(struct omap_dss_device *dssdev) td = kzalloc(sizeof(*td), GFP_KERNEL); if (!td) { r = -ENOMEM; - goto err0; + goto err; } td->dssdev = dssdev; @@ -549,7 +549,7 @@ static int taal_probe(struct omap_dss_device *dssdev) if (td->esd_wq == NULL) { dev_err(&dssdev->dev, "can't create ESD workqueue\n"); r = -ENOMEM; - goto err1; + goto err_wq; } INIT_DELAYED_WORK_DEFERRABLE(&td->esd_work, taal_esd_work); @@ -571,7 +571,7 @@ static int taal_probe(struct omap_dss_device *dssdev) &taal_bl_ops, &props); if (IS_ERR(bldev)) { r = PTR_ERR(bldev); - goto err2; + goto err_bl; } td->bldev = bldev; @@ -591,7 +591,7 @@ static int taal_probe(struct omap_dss_device *dssdev) r = gpio_request(gpio, "taal irq"); if (r) { dev_err(&dssdev->dev, "GPIO request failed\n"); - goto err3; + goto err_gpio; } gpio_direction_input(gpio); @@ -603,7 +603,7 @@ static int taal_probe(struct omap_dss_device *dssdev) if (r) { dev_err(&dssdev->dev, "IRQ request failed\n"); gpio_free(gpio); - goto err4; + goto err_irq; } init_completion(&td->te_completion); @@ -614,23 +614,23 @@ static int taal_probe(struct omap_dss_device *dssdev) r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group); if (r) { dev_err(&dssdev->dev, "failed to create sysfs files\n"); - goto err5; + goto err_sysfs; } return 0; -err5: +err_sysfs: if (td->use_ext_te) free_irq(gpio_to_irq(dssdev->phy.dsi.ext_te_gpio), dssdev); -err4: +err_irq: if (td->use_ext_te) gpio_free(dssdev->phy.dsi.ext_te_gpio); -err3: +err_gpio: backlight_device_unregister(bldev); -err2: +err_bl: destroy_workqueue(td->esd_wq); -err1: +err_wq: kfree(td); -err0: +err: return r; } From patchwork Thu Apr 1 00:25:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Madhusudhan X-Patchwork-Id: 90036 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o310Ple9006402 for ; Thu, 1 Apr 2010 00:25:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757192Ab0DAAZp (ORCPT ); Wed, 31 Mar 2010 20:25:45 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:36913 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756254Ab0DAAZo (ORCPT ); Wed, 31 Mar 2010 20:25:44 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o310Pgig017135 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 31 Mar 2010 19:25:43 -0500 Received: from webmail.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o310PdsT021955; Wed, 31 Mar 2010 19:25:41 -0500 (CDT) Received: from 192.168.10.89 (proxying for 128.247.79.84) (SquirrelMail authenticated user x0070977); by dbdmail.itg.ti.com with HTTP; Thu, 1 Apr 2010 05:55:42 +0530 (IST) Message-ID: <37310.192.168.10.89.1270081542.squirrel@dbdmail.itg.ti.com> Date: Thu, 1 Apr 2010 05:55:42 +0530 (IST) Subject: [PATCH] Disable the non working eMMC on Zoom2/3 From: "Madhusudhan Chikkature" To: tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-mmc@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Apr 2010 00:25:49 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b39849..ac791d2 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -102,10 +102,6 @@ static struct regulator_consumer_supply zoom_vsim_supply = { .supply = "vmmc_aux", }; -static struct regulator_consumer_supply zoom_vmmc2_supply = { - .supply = "vmmc", -}; - /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data zoom_vmmc1 = { .constraints = { @@ -121,21 +117,6 @@ static struct regulator_init_data zoom_vmmc1 = { .consumer_supplies = &zoom_vmmc1_supply, }; -/* VMMC2 for MMC2 card */ -static struct regulator_init_data zoom_vmmc2 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 1850000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &zoom_vmmc2_supply, -}; - /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ static struct regulator_init_data zoom_vsim = { .constraints = { @@ -159,15 +140,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = { .gpio_wp = -EINVAL, .power_saving = true, }, - { - .name = "internal", - .mmc = 2, - .wires = 8, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - .nonremovable = true, - .power_saving = true, - }, {} /* Terminator */ }; @@ -183,7 +155,6 @@ static int zoom_twl_gpio_setup(struct device *dev, */ zoom_vmmc1_supply.dev = mmc[0].dev; zoom_vsim_supply.dev = mmc[0].dev; - zoom_vmmc2_supply.dev = mmc[1].dev; return 0; } @@ -241,7 +212,6 @@ static struct twl4030_platform_data zoom_twldata = { .keypad = &zoom_kp_twl4030_data, .codec = &zoom_codec_data, .vmmc1 = &zoom_vmmc1, - .vmmc2 = &zoom_vmmc2, .vsim = &zoom_vsim, }; From patchwork Sat Jul 10 02:23:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111178 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2QYAY002081 for ; Sat, 10 Jul 2010 02:26:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753769Ab0GJCZg (ORCPT ); Fri, 9 Jul 2010 22:25:36 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:55218 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751975Ab0GJCZU (ORCPT ); Fri, 9 Jul 2010 22:25:20 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PC46006464 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:12 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6A2PAwR026419; Fri, 9 Jul 2010 21:25:11 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68F021595; Fri, 9 Jul 2010 21:25:10 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 03/15] staging:ti dspbridge: Rename words with camel case. Date: Fri, 9 Jul 2010 21:23:57 -0500 Message-Id: <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:26:34 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== hStrm to stream_obj iMode to io_mode irqMask to irq_mask lOffset to offset memPtr to mem_ptr moduleId to module_id msgCallback to msg_callback msgList to msg_list nArgc to num_argc nEntryStart to entry_start nMemSpace to mem_space nStatus to node_status nStrms to strms numLibs to num_libs numLockedEntries to num_locked_entries pageSize to page_sz ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/io_sm.c | 26 ++-- drivers/staging/tidspbridge/core/msg_sm.c | 24 ++-- drivers/staging/tidspbridge/hw/hw_mmu.c | 42 +++--- drivers/staging/tidspbridge/hw/hw_mmu.h | 16 +- .../staging/tidspbridge/include/dspbridge/cod.h | 8 +- .../staging/tidspbridge/include/dspbridge/dbdcd.h | 4 +- .../staging/tidspbridge/include/dspbridge/dev.h | 2 +- .../tidspbridge/include/dspbridge/dspdefs.h | 8 +- .../staging/tidspbridge/include/dspbridge/dspmsg.h | 2 +- .../staging/tidspbridge/include/dspbridge/io_sm.h | 4 +- .../staging/tidspbridge/include/dspbridge/msg.h | 6 +- .../tidspbridge/include/dspbridge/msgdefs.h | 2 +- .../tidspbridge/include/dspbridge/nldrdefs.h | 8 +- .../staging/tidspbridge/include/dspbridge/node.h | 4 +- .../include/dspbridge/resourcecleanup.h | 4 +- .../staging/tidspbridge/include/dspbridge/strm.h | 72 +++++----- drivers/staging/tidspbridge/pmgr/cod.c | 16 +- drivers/staging/tidspbridge/pmgr/dbll.c | 14 +- drivers/staging/tidspbridge/pmgr/dev.c | 4 +- drivers/staging/tidspbridge/pmgr/msg.c | 6 +- drivers/staging/tidspbridge/rmgr/dbdcd.c | 4 +- drivers/staging/tidspbridge/rmgr/drv.c | 4 +- drivers/staging/tidspbridge/rmgr/node.c | 18 +- drivers/staging/tidspbridge/rmgr/strm.c | 156 ++++++++++--------- 24 files changed, 231 insertions(+), 223 deletions(-) diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 346f0aa..81b81e1 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -133,16 +133,16 @@ struct io_mgr { /* Function Prototypes */ static void io_dispatch_chnl(IN struct io_mgr *pio_mgr, - IN OUT struct chnl_object *pchnl, u8 iMode); + IN OUT struct chnl_object *pchnl, u8 io_mode); static void io_dispatch_msg(IN struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr); static void io_dispatch_pm(struct io_mgr *pio_mgr); static void notify_chnl_complete(struct chnl_object *pchnl, struct chnl_irp *chnl_packet_obj); static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, - u8 iMode); + u8 io_mode); static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, - u8 iMode); + u8 io_mode); static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr); static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr); static u32 find_ready_output(struct chnl_mgr *chnl_mgr_obj, @@ -839,18 +839,18 @@ func_end: * Proc-copy chanl dispatch. */ static void io_dispatch_chnl(IN struct io_mgr *pio_mgr, - IN OUT struct chnl_object *pchnl, u8 iMode) + IN OUT struct chnl_object *pchnl, u8 io_mode) { if (!pio_mgr) goto func_end; /* See if there is any data available for transfer */ - if (iMode != IO_SERVICE) + if (io_mode != IO_SERVICE) goto func_end; /* Any channel will do for this mode */ - input_chnl(pio_mgr, pchnl, iMode); - output_chnl(pio_mgr, pchnl, iMode); + input_chnl(pio_mgr, pchnl, io_mode); + output_chnl(pio_mgr, pchnl, io_mode); func_end: return; } @@ -1014,7 +1014,7 @@ void io_mbox_msg(u32 msg) * interrupts the DSP. */ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, - u8 iMode, OUT u16 *pwMbVal) + u8 io_mode, OUT u16 *pwMbVal) { struct chnl_mgr *chnl_mgr_obj; struct shm *sm; @@ -1023,7 +1023,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, goto func_end; chnl_mgr_obj = pio_mgr->hchnl_mgr; sm = pio_mgr->shared_mem; - if (iMode == IO_INPUT) { + if (io_mode == IO_INPUT) { /* * Assertion fires if CHNL_AddIOReq() called on a stream * which was cancelled, or attached to a dead board. @@ -1034,7 +1034,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, IO_OR_VALUE(pio_mgr->hbridge_context, struct shm, sm, host_free_mask, (1 << pchnl->chnl_id)); *pwMbVal = MBX_PCPY_CLASS; - } else if (iMode == IO_OUTPUT) { + } else if (io_mode == IO_OUTPUT) { /* * This assertion fails if CHNL_AddIOReq() was called on a * stream which was cancelled, or attached to a dead board. @@ -1047,7 +1047,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, */ chnl_mgr_obj->dw_output_mask |= (1 << pchnl->chnl_id); } else { - DBC_ASSERT(iMode); /* Shouldn't get here. */ + DBC_ASSERT(io_mode); /* Shouldn't get here. */ } func_end: return; @@ -1116,7 +1116,7 @@ func_end: * Dispatch a buffer on an input channel. */ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, - u8 iMode) + u8 io_mode) { struct chnl_mgr *chnl_mgr_obj; struct shm *sm; @@ -1403,7 +1403,7 @@ func_end: * Dispatch a buffer on an output channel. */ static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, - u8 iMode) + u8 io_mode) { struct chnl_mgr *chnl_mgr_obj; struct shm *sm; diff --git a/drivers/staging/tidspbridge/core/msg_sm.c b/drivers/staging/tidspbridge/core/msg_sm.c index 7c6d6cc..0a68df9 100644 --- a/drivers/staging/tidspbridge/core/msg_sm.c +++ b/drivers/staging/tidspbridge/core/msg_sm.c @@ -38,10 +38,10 @@ #include /* ----------------------------------- Function Prototypes */ -static int add_new_msg(struct lst_list *msgList); +static int add_new_msg(struct lst_list *msg_list); static void delete_msg_mgr(struct msg_mgr *hmsg_mgr); static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 uNumToDSP); -static void free_msg_list(struct lst_list *msgList); +static void free_msg_list(struct lst_list *msg_list); /* * ======== bridge_msg_create ======== @@ -50,13 +50,13 @@ static void free_msg_list(struct lst_list *msgList); */ int bridge_msg_create(OUT struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, - msg_onexit msgCallback) + msg_onexit msg_callback) { struct msg_mgr *msg_mgr_obj; struct io_mgr *hio_mgr; int status = 0; - if (!phMsgMgr || !msgCallback || !hdev_obj) { + if (!phMsgMgr || !msg_callback || !hdev_obj) { status = -EFAULT; goto func_end; } @@ -70,7 +70,7 @@ int bridge_msg_create(OUT struct msg_mgr **phMsgMgr, msg_mgr_obj = kzalloc(sizeof(struct msg_mgr), GFP_KERNEL); if (msg_mgr_obj) { - msg_mgr_obj->on_exit = msgCallback; + msg_mgr_obj->on_exit = msg_callback; msg_mgr_obj->hio_mgr = hio_mgr; /* List of MSG_QUEUEs */ msg_mgr_obj->queue_list = kzalloc(sizeof(struct lst_list), @@ -551,7 +551,7 @@ void bridge_msg_set_queue_id(struct msg_queue *msg_queue_obj, u32 msgq_id) * ======== add_new_msg ======== * Must be called in message manager critical section. */ -static int add_new_msg(struct lst_list *msgList) +static int add_new_msg(struct lst_list *msg_list) { struct msg_frame *pmsg; int status = 0; @@ -559,7 +559,7 @@ static int add_new_msg(struct lst_list *msgList) pmsg = kzalloc(sizeof(struct msg_frame), GFP_ATOMIC); if (pmsg != NULL) { lst_init_elem((struct list_head *)pmsg); - lst_put_tail(msgList, (struct list_head *)pmsg); + lst_put_tail(msg_list, (struct list_head *)pmsg); } else { status = -ENOMEM; } @@ -655,19 +655,19 @@ func_end: /* * ======== free_msg_list ======== */ -static void free_msg_list(struct lst_list *msgList) +static void free_msg_list(struct lst_list *msg_list) { struct msg_frame *pmsg; - if (!msgList) + if (!msg_list) goto func_end; - while ((pmsg = (struct msg_frame *)lst_get_head(msgList)) != NULL) + while ((pmsg = (struct msg_frame *)lst_get_head(msg_list)) != NULL) kfree(pmsg); - DBC_ASSERT(LST_IS_EMPTY(msgList)); + DBC_ASSERT(LST_IS_EMPTY(msg_list)); - kfree(msgList); + kfree(msg_list); func_end: return; } diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index 5f9f4ea..2bb64cd 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -81,7 +81,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); * TypE : const u32 * Description : Base Address of instance of MMU module * - * Identifier : pageSize + * Identifier : page_sz * TypE : const u32 * Description : It indicates the page size * @@ -113,7 +113,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); * METHOD: : Check the Input parameters and set the CAM entry. */ static hw_status mmu_set_cam_entry(const void __iomem *base_address, - const u32 pageSize, + const u32 page_sz, const u32 preservedBit, const u32 validBit, const u32 virtual_addr_tag); @@ -184,11 +184,11 @@ hw_status hw_mmu_disable(const void __iomem *base_address) } hw_status hw_mmu_num_locked_set(const void __iomem *base_address, - u32 numLockedEntries) + u32 num_locked_entries) { hw_status status = RET_OK; - MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, numLockedEntries); + MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, num_locked_entries); return status; } @@ -203,44 +203,44 @@ hw_status hw_mmu_victim_num_set(const void __iomem *base_address, return status; } -hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irqMask) +hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask) { hw_status status = RET_OK; - MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irqMask); + MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irq_mask); return status; } -hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irqMask) +hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask) { hw_status status = RET_OK; u32 irq_reg; irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address); - MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg & ~irqMask); + MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg & ~irq_mask); return status; } -hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irqMask) +hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask) { hw_status status = RET_OK; u32 irq_reg; irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address); - MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg | irqMask); + MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg | irq_mask); return status; } -hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irqMask) +hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask) { hw_status status = RET_OK; - *irqMask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address); + *irq_mask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address); return status; } @@ -294,13 +294,13 @@ hw_status hw_mmu_twl_disable(const void __iomem *base_address) } hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, - u32 pageSize) + u32 page_sz) { hw_status status = RET_OK; u32 virtual_addr_tag; enum hw_mmu_page_size_t pg_size_bits; - switch (pageSize) { + switch (page_sz) { case HW_PAGE_SIZE4KB: pg_size_bits = HW_MMU_SMALL_PAGE; break; @@ -334,7 +334,7 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, hw_status hw_mmu_tlb_add(const void __iomem *base_address, u32 physicalAddr, u32 virtualAddr, - u32 pageSize, + u32 page_sz, u32 entry_num, struct hw_mmu_map_attrs_t *map_attrs, s8 preservedBit, s8 validBit) @@ -347,13 +347,13 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, /*Check the input Parameters */ CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM, RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - CHECK_INPUT_RANGE_MIN0(pageSize, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE, + CHECK_INPUT_RANGE_MIN0(page_sz, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE + RES_INVALID_INPUT_PARAM); CHECK_INPUT_RANGE_MIN0(map_attrs->element_size, MMU_ELEMENTSIZE_MAX, RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - switch (pageSize) { + switch (page_sz) { case HW_PAGE_SIZE4KB: mmu_pg_size = HW_MMU_SMALL_PAGE; break; @@ -404,13 +404,13 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, hw_status hw_mmu_pte_set(const u32 pg_tbl_va, u32 physicalAddr, u32 virtualAddr, - u32 pageSize, struct hw_mmu_map_attrs_t *map_attrs) + u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs) { hw_status status = RET_OK; u32 pte_addr, pte_val; s32 num_entries = 1; - switch (pageSize) { + switch (page_sz) { case HW_PAGE_SIZE4KB: pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, virtualAddr & @@ -537,7 +537,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address) /* mmu_set_cam_entry */ static hw_status mmu_set_cam_entry(const void __iomem *base_address, - const u32 pageSize, + const u32 page_sz, const u32 preservedBit, const u32 validBit, const u32 virtual_addr_tag) @@ -550,7 +550,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, RES_MMU_BASE + RES_INVALID_INPUT_PARAM); mmu_cam_reg = (virtual_addr_tag << 12); - mmu_cam_reg = (mmu_cam_reg) | (pageSize) | (validBit << 2) | + mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (validBit << 2) | (preservedBit << 3); /* write values to register */ diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h index 7c851bd..aeedbe2 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.h +++ b/drivers/staging/tidspbridge/hw/hw_mmu.h @@ -47,23 +47,23 @@ extern hw_status hw_mmu_enable(const void __iomem *base_address); extern hw_status hw_mmu_disable(const void __iomem *base_address); extern hw_status hw_mmu_num_locked_set(const void __iomem *base_address, - u32 numLockedEntries); + u32 num_locked_entries); extern hw_status hw_mmu_victim_num_set(const void __iomem *base_address, u32 victimEntryNum); /* For MMU faults */ extern hw_status hw_mmu_event_ack(const void __iomem *base_address, - u32 irqMask); + u32 irq_mask); extern hw_status hw_mmu_event_disable(const void __iomem *base_address, - u32 irqMask); + u32 irq_mask); extern hw_status hw_mmu_event_enable(const void __iomem *base_address, - u32 irqMask); + u32 irq_mask); extern hw_status hw_mmu_event_status(const void __iomem *base_address, - u32 *irqMask); + u32 *irq_mask); extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr); @@ -77,12 +77,12 @@ extern hw_status hw_mmu_twl_enable(const void __iomem *base_address); extern hw_status hw_mmu_twl_disable(const void __iomem *base_address); extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address, - u32 virtualAddr, u32 pageSize); + u32 virtualAddr, u32 page_sz); extern hw_status hw_mmu_tlb_add(const void __iomem *base_address, u32 physicalAddr, u32 virtualAddr, - u32 pageSize, + u32 page_sz, u32 entry_num, struct hw_mmu_map_attrs_t *map_attrs, s8 preservedBit, s8 validBit); @@ -91,7 +91,7 @@ extern hw_status hw_mmu_tlb_add(const void __iomem *base_address, extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, u32 physicalAddr, u32 virtualAddr, - u32 pageSize, + u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs); extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index 6914247..ae711df 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -50,7 +50,7 @@ struct cod_attrs { * and freeing DSP memory. */ typedef u32(*cod_writefxn) (void *priv_ref, u32 ulDspAddr, - void *pbuf, u32 ul_num_bytes, u32 nMemSpace); + void *pbuf, u32 ul_num_bytes, u32 mem_space); /* * ======== cod_close ======== @@ -276,7 +276,7 @@ extern bool cod_init(void); * qualified pathname. * Parameters: * hmgr: manager to load the code with - * nArgc: number of arguments in the args array + * num_argc: number of arguments in the args array * args: array of strings for arguments to DSP program * write_fxn: board-specific function to write data to DSP system * pArb: arbitrary pointer to be passed as first arg to write_fxn @@ -287,14 +287,14 @@ extern bool cod_init(void); * Requires: * COD module initialized. * hmgr is valid. - * nArgc > 0. + * num_argc > 0. * args != NULL. * args[0] != NULL. * pfn_write != NULL. * Ensures: */ extern int cod_load_base(struct cod_manager *cod_mgr_obj, - u32 nArgc, char *args[], + u32 num_argc, char *args[], cod_writefxn pfn_write, void *pArb, char *envp[]); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h index 54e8238..6658b74 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h @@ -153,7 +153,7 @@ extern void dcd_exit(void); * Parameters: * hdcd_mgr: A DCD manager handle. * uuid_obj: Pointer to a dsp_uuid for a library. - * numLibs: Size of uuid array (number of library uuids). + * num_libs: Size of uuid array (number of library uuids). * pDepLibUuids: Array of dependent library uuids to be filled in. * pPersistentDepLibs: Array indicating if corresponding lib is persistent. * phase: phase to obtain correct input library @@ -171,7 +171,7 @@ extern void dcd_exit(void); */ extern int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - u16 numLibs, + u16 num_libs, OUT struct dsp_uuid *pDepLibUuids, OUT bool *pPersistentDepLibs, IN enum nldr_phase phase); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index 2ee1c41..72d4591 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -56,7 +56,7 @@ */ extern u32 dev_brd_write_fxn(void *pArb, u32 ulDspAddr, - void *pHostBuf, u32 ul_num_bytes, u32 nMemSpace); + void *pHostBuf, u32 ul_num_bytes, u32 mem_space); /* * ======== dev_create_device ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 73034c3..fc8f8d3 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -806,19 +806,19 @@ typedef int(*fxn_io_getprocload) (struct io_mgr *hio_mgr, * Parameters: * phMsgMgr: Location to store msg_ctrl manager on output. * hdev_obj: Handle to a device object. - * msgCallback: Called whenever an RMS_EXIT message is received. + * msg_callback: Called whenever an RMS_EXIT message is received. * Returns: * 0: Success. * -ENOMEM: Insufficient memory. * Requires: * phMsgMgr != NULL. - * msgCallback != NULL. + * msg_callback != NULL. * hdev_obj != NULL. * Ensures: */ typedef int(*fxn_msg_create) (OUT struct msg_mgr **phMsgMgr, - struct dev_object *hdev_obj, msg_onexit msgCallback); + struct dev_object *hdev_obj, msg_onexit msg_callback); /* * ======== bridge_msg_create_queue ======== @@ -831,7 +831,7 @@ typedef int(*fxn_msg_create) * phMsgQueue: Location to store msg_ctrl queue on output. * msgq_id: Identifier for messages (node environment pointer). * max_msgs: Max number of simultaneous messages for the node. - * h: Handle passed to hmsg_mgr->msgCallback(). + * h: Handle passed to hmsg_mgr->msg_callback(). * Returns: * 0: Success. * -ENOMEM: Insufficient memory. diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h index a10634e..18f56e1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h @@ -28,7 +28,7 @@ extern int bridge_msg_create(OUT struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, - msg_onexit msgCallback); + msg_onexit msg_callback); extern int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, OUT struct msg_queue **phMsgQueue, diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index 62899f2..8b0cd7f 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -108,7 +108,7 @@ void io_mbox_msg(u32 msg); * Parameters: * hio_mgr: IO manager handle. * pchnl: Ptr to the channel requesting I/O. - * iMode: Mode of channel: {IO_INPUT | IO_OUTPUT}. + * io_mode: Mode of channel: {IO_INPUT | IO_OUTPUT}. * Returns: * Requires: * pchnl != NULL @@ -116,7 +116,7 @@ void io_mbox_msg(u32 msg); */ extern void io_request_chnl(struct io_mgr *hio_mgr, struct chnl_object *pchnl, - u8 iMode, OUT u16 *pwMbVal); + u8 io_mode, OUT u16 *pwMbVal); /* * ======== iosm_schedule ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/msg.h b/drivers/staging/tidspbridge/include/dspbridge/msg.h index baac5f3..973bce2 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/msg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/msg.h @@ -31,18 +31,18 @@ * Parameters: * phMsgMgr: Location to store msg_ctrl manager handle on output. * hdev_obj: The device object. - * msgCallback: Called whenever an RMS_EXIT message is received. + * msg_callback: Called whenever an RMS_EXIT message is received. * Returns: * Requires: * msg_mod_init(void) called. * phMsgMgr != NULL. * hdev_obj != NULL. - * msgCallback != NULL. + * msg_callback != NULL. * Ensures: */ extern int msg_create(OUT struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, - msg_onexit msgCallback); + msg_onexit msg_callback); /* * ======== msg_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/msgdefs.h b/drivers/staging/tidspbridge/include/dspbridge/msgdefs.h index fe24656..80a3fa1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/msgdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/msgdefs.h @@ -24,6 +24,6 @@ struct msg_mgr; struct msg_queue; /* Function prototype for callback to be called on RMS_EXIT message received */ -typedef void (*msg_onexit) (void *h, s32 nStatus); +typedef void (*msg_onexit) (void *h, s32 node_status); #endif /* MSGDEFS_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h index 9be0483..d53b43e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h @@ -48,7 +48,7 @@ enum nldr_loadtype { * ulDspRunAddr: Run address of code or data. * ulDspLoadAddr: Load address of code or data. * ul_num_bytes: Number of (GPP) bytes to copy. - * nMemSpace: RMS_CODE or RMS_DATA. + * mem_space: RMS_CODE or RMS_DATA. * Returns: * ul_num_bytes: Success. * 0: Failure. @@ -56,7 +56,7 @@ enum nldr_loadtype { * Ensures: */ typedef u32(*nldr_ovlyfxn) (void *priv_ref, u32 ulDspRunAddr, - u32 ulDspLoadAddr, u32 ul_num_bytes, u32 nMemSpace); + u32 ulDspLoadAddr, u32 ul_num_bytes, u32 mem_space); /* * ======== nldr_writefxn ======== @@ -66,7 +66,7 @@ typedef u32(*nldr_ovlyfxn) (void *priv_ref, u32 ulDspRunAddr, * ulDspAddr: Address of code or data. * pbuf: Code or data to be written * ul_num_bytes: Number of (GPP) bytes to write. - * nMemSpace: DBLL_DATA or DBLL_CODE. + * mem_space: DBLL_DATA or DBLL_CODE. * Returns: * ul_num_bytes: Success. * 0: Failure. @@ -75,7 +75,7 @@ typedef u32(*nldr_ovlyfxn) (void *priv_ref, u32 ulDspRunAddr, */ typedef u32(*nldr_writefxn) (void *priv_ref, u32 ulDspAddr, void *pbuf, - u32 ul_num_bytes, u32 nMemSpace); + u32 ul_num_bytes, u32 mem_space); /* * ======== nldr_attrs ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index 5358d77..9dfa3a8 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -420,11 +420,11 @@ extern bool node_init(void); * called by the Bridge driver when an exit message for a node is received. * Parameters: * hnode: Handle of the node that the exit message is for. - * nStatus: Return status of the node's execute phase. + * node_status: Return status of the node's execute phase. * Returns: * Ensures: */ -void node_on_exit(struct node_object *hnode, s32 nStatus); +void node_on_exit(struct node_object *hnode, s32 node_status); /* * ======== node_pause ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h index 1fa7d13..6c78f2d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h +++ b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h @@ -48,11 +48,11 @@ extern void drv_proc_node_update_status(void *node_resource, s32 status); extern int drv_proc_update_strm_res(u32 num_bufs, void *strm_res); -extern int drv_proc_insert_strm_res_element(void *hStrm, +extern int drv_proc_insert_strm_res_element(void *stream_obj, void *strm_res, void *pPctxt); -extern int drv_get_strm_res_element(void *hStrm, void *strm_res, +extern int drv_get_strm_res_element(void *stream_obj, void *strm_res, void *ctxt); extern int drv_proc_remove_strm_res_element(void *strm_res, diff --git a/drivers/staging/tidspbridge/include/dspbridge/strm.h b/drivers/staging/tidspbridge/include/dspbridge/strm.h index 2ac630d..c4a4d65 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/strm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/strm.h @@ -29,13 +29,13 @@ * Purpose: * Allocate data buffer(s) for use with a stream. * Parameter: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * usize: Size (GPP bytes) of the buffer(s). * num_bufs: Number of buffers to allocate. * ap_buffer: Array to hold buffer addresses. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -ENOMEM: Insufficient memory. * -EPERM: Failure occurred, unable to allocate buffers. * -EINVAL: usize must be > 0 bytes. @@ -44,7 +44,7 @@ * ap_buffer != NULL. * Ensures: */ -extern int strm_allocate_buffer(struct strm_object *hStrm, +extern int strm_allocate_buffer(struct strm_object *stream_obj, u32 usize, OUT u8 **ap_buffer, u32 num_bufs, @@ -55,10 +55,10 @@ extern int strm_allocate_buffer(struct strm_object *hStrm, * Purpose: * Close a stream opened with strm_open(). * Parameter: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -EPIPE: Some data buffers issued to the stream have not * been reclaimed. * -EPERM: Failure to close stream. @@ -66,7 +66,7 @@ extern int strm_allocate_buffer(struct strm_object *hStrm, * strm_init(void) called. * Ensures: */ -extern int strm_close(struct strm_object *hStrm, +extern int strm_close(struct strm_object *stream_obj, struct process_context *pr_ctxt); /* @@ -125,7 +125,7 @@ extern void strm_exit(void); * Purpose: * Free buffer(s) allocated with strm_allocate_buffer. * Parameter: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * ap_buffer: Array containing buffer addresses. * num_bufs: Number of buffers to be freed. * Returns: @@ -137,7 +137,7 @@ extern void strm_exit(void); * ap_buffer != NULL. * Ensures: */ -extern int strm_free_buffer(struct strm_object *hStrm, +extern int strm_free_buffer(struct strm_object *stream_obj, u8 **ap_buffer, u32 num_bufs, struct process_context *pr_ctxt); @@ -147,17 +147,17 @@ extern int strm_free_buffer(struct strm_object *hStrm, * Get stream's user event handle. This function is used when closing * a stream, so the event can be closed. * Parameter: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * ph_event: Location to store event handle on output. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * Requires: * strm_init(void) called. * ph_event != NULL. * Ensures: */ -extern int strm_get_event_handle(struct strm_object *hStrm, +extern int strm_get_event_handle(struct strm_object *stream_obj, OUT void **ph_event); /* @@ -166,12 +166,12 @@ extern int strm_get_event_handle(struct strm_object *hStrm, * Get information about a stream. User's dsp_streaminfo is contained * in stream_info struct. stream_info also contains Bridge private info. * Parameters: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * stream_info: Location to store stream info on output. * uSteamInfoSize: Size of user's dsp_streaminfo structure. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -EINVAL: stream_info_size < sizeof(dsp_streaminfo). * -EPERM: Unable to get stream info. * Requires: @@ -179,7 +179,7 @@ extern int strm_get_event_handle(struct strm_object *hStrm, * stream_info != NULL. * Ensures: */ -extern int strm_get_info(struct strm_object *hStrm, +extern int strm_get_info(struct strm_object *stream_obj, OUT struct stream_info *stream_info, u32 stream_info_size); @@ -195,18 +195,18 @@ extern int strm_get_info(struct strm_object *hStrm, * After a successful call to strm_idle(), all buffers can immediately * be reclaimed. * Parameters: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * flush_data: If TRUE, discard output buffers. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -ETIME: A timeout occurred before the stream could be idled. * -EPERM: Unable to idle stream. * Requires: * strm_init(void) called. * Ensures: */ -extern int strm_idle(struct strm_object *hStrm, bool flush_data); +extern int strm_idle(struct strm_object *stream_obj, bool flush_data); /* * ======== strm_init ======== @@ -225,14 +225,14 @@ extern bool strm_init(void); * Purpose: * Send a buffer of data to a stream. * Parameters: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * pbuf: Pointer to buffer of data to be sent to the stream. * ul_bytes: Number of bytes of data in the buffer. * ul_buf_size: Actual buffer size in bytes. * dw_arg: A user argument that travels with the buffer. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -ENOSR: The stream is full. * -EPERM: Failure occurred, unable to issue buffer. * Requires: @@ -240,7 +240,7 @@ extern bool strm_init(void); * pbuf != NULL. * Ensures: */ -extern int strm_issue(struct strm_object *hStrm, IN u8 * pbuf, +extern int strm_issue(struct strm_object *stream_obj, IN u8 * pbuf, u32 ul_bytes, u32 ul_buf_size, IN u32 dw_arg); /* @@ -281,19 +281,19 @@ extern int strm_open(struct node_object *hnode, u32 dir, * Prepare a data buffer not allocated by DSPStream_AllocateBuffers() * for use with a stream. * Parameter: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * usize: Size (GPP bytes) of the buffer. * pbuffer: Buffer address. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -EPERM: Failure occurred, unable to prepare buffer. * Requires: * strm_init(void) called. * pbuffer != NULL. * Ensures: */ -extern int strm_prepare_buffer(struct strm_object *hStrm, +extern int strm_prepare_buffer(struct strm_object *stream_obj, u32 usize, u8 *pbuffer); /* @@ -301,7 +301,7 @@ extern int strm_prepare_buffer(struct strm_object *hStrm, * Purpose: * Request a buffer back from a stream. * Parameters: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * buf_ptr: Location to store pointer to reclaimed buffer. * pulBytes: Location where number of bytes of data in the * buffer will be written. @@ -310,7 +310,7 @@ extern int strm_prepare_buffer(struct strm_object *hStrm, * the buffer will be written. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -ETIME: A timeout occurred before a buffer could be * retrieved. * -EPERM: Failure occurred, unable to reclaim buffer. @@ -321,7 +321,7 @@ extern int strm_prepare_buffer(struct strm_object *hStrm, * pdw_arg != NULL. * Ensures: */ -extern int strm_reclaim(struct strm_object *hStrm, +extern int strm_reclaim(struct strm_object *stream_obj, OUT u8 **buf_ptr, u32 * pulBytes, u32 *pulBufSize, u32 *pdw_arg); @@ -330,13 +330,13 @@ extern int strm_reclaim(struct strm_object *hStrm, * Purpose: * Register to be notified on specific events for this stream. * Parameters: - * hStrm: Stream handle returned by strm_open(). + * stream_obj: Stream handle returned by strm_open(). * event_mask: Mask of types of events to be notified about. * notify_type: Type of notification to be sent. * hnotification: Handle to be used for notification. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -ENOMEM: Insufficient memory on GPP. * -EINVAL: event_mask is invalid. * -ENOSYS: Notification type specified by notify_type is not @@ -346,7 +346,7 @@ extern int strm_reclaim(struct strm_object *hStrm, * hnotification != NULL. * Ensures: */ -extern int strm_register_notify(struct strm_object *hStrm, +extern int strm_register_notify(struct strm_object *stream_obj, u32 event_mask, u32 notify_type, struct dsp_notification *hnotification); @@ -357,12 +357,12 @@ extern int strm_register_notify(struct strm_object *hStrm, * Select a ready stream. * Parameters: * strm_tab: Array of stream handles returned from strm_open(). - * nStrms: Number of stream handles in array. + * strms: Number of stream handles in array. * pmask: Location to store mask of ready streams on output. * utimeout: Timeout value (milliseconds). * Returns: * 0: Success. - * -EDOM: nStrms out of range. + * -EDOM: strms out of range. * -EFAULT: Invalid stream handle in array. * -ETIME: A timeout occurred before a stream became ready. @@ -370,14 +370,14 @@ extern int strm_register_notify(struct strm_object *hStrm, * Requires: * strm_init(void) called. * strm_tab != NULL. - * nStrms > 0. + * strms > 0. * pmask != NULL. * Ensures: * 0: *pmask != 0 || utimeout == 0. * Error: *pmask == 0. */ extern int strm_select(IN struct strm_object **strm_tab, - u32 nStrms, OUT u32 *pmask, u32 utimeout); + u32 strms, OUT u32 *pmask, u32 utimeout); /* * ======== strm_unprepare_buffer ======== @@ -386,19 +386,19 @@ extern int strm_select(IN struct strm_object **strm_tab, * with DSPStream_PrepareBuffer(), and that will no longer be used with * the stream. * Parameter: - * hStrm: Stream handle returned from strm_open(). + * stream_obj: Stream handle returned from strm_open(). * usize: Size (GPP bytes) of the buffer. * pbuffer: Buffer address. * Returns: * 0: Success. - * -EFAULT: Invalid hStrm. + * -EFAULT: Invalid stream_obj. * -EPERM: Failure occurred, unable to unprepare buffer. * Requires: * strm_init(void) called. * pbuffer != NULL. * Ensures: */ -extern int strm_unprepare_buffer(struct strm_object *hStrm, +extern int strm_unprepare_buffer(struct strm_object *stream_obj, u32 usize, u8 *pbuffer); #endif /* STRM_ */ diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index a9b0491..7682035 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -155,7 +155,7 @@ static s32 cod_f_read(void __user *pbuffer, s32 size, s32 count, return -EINVAL; } -static s32 cod_f_seek(struct file *filp, s32 lOffset, s32 origin) +static s32 cod_f_seek(struct file *filp, s32 offset, s32 origin) { loff_t dw_cur_pos; @@ -164,7 +164,7 @@ static s32 cod_f_seek(struct file *filp, s32 lOffset, s32 origin) return -EFAULT; /* based on the origin flag, move the internal pointer */ - dw_cur_pos = filp->f_op->llseek(filp, lOffset, origin); + dw_cur_pos = filp->f_op->llseek(filp, offset, origin); if ((s32) dw_cur_pos < 0) return -EPERM; @@ -487,12 +487,12 @@ bool cod_init(void) * loaded must be the first element of the args array and must be a fully * qualified pathname. * Details: - * if nArgc doesn't match the number of arguments in the args array, the + * if num_argc doesn't match the number of arguments in the args array, the * args array is searched for a NULL terminating entry, and argc is * recalculated to reflect this. In this way, we can support NULL - * terminating args arrays, if nArgc is very large. + * terminating args arrays, if num_argc is very large. */ -int cod_load_base(struct cod_manager *hmgr, u32 nArgc, char *args[], +int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], cod_writefxn pfn_write, void *pArb, char *envp[]) { dbll_flags flags; @@ -503,7 +503,7 @@ int cod_load_base(struct cod_manager *hmgr, u32 nArgc, char *args[], DBC_REQUIRE(refs > 0); DBC_REQUIRE(IS_VALID(hmgr)); - DBC_REQUIRE(nArgc > 0); + DBC_REQUIRE(num_argc > 0); DBC_REQUIRE(args != NULL); DBC_REQUIRE(args[0] != NULL); DBC_REQUIRE(pfn_write != NULL); @@ -513,9 +513,9 @@ int cod_load_base(struct cod_manager *hmgr, u32 nArgc, char *args[], * Make sure every argv[] stated in argc has a value, or change argc to * reflect true number in NULL terminated argv array. */ - for (i = 0; i < nArgc; i++) { + for (i = 0; i < num_argc; i++) { if (args[i] == NULL) { - nArgc = i; + num_argc = i; break; } } diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index 3636aa3..1f67193 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -156,14 +156,14 @@ static struct dynload_symbol *dbll_find_symbol(struct dynamic_loader_sym *this, const char *name); static struct dynload_symbol *dbll_add_to_symbol_table(struct dynamic_loader_sym *this, const char *name, - unsigned moduleId); + unsigned module_id); static struct dynload_symbol *find_in_symbol_table(struct dynamic_loader_sym *this, const char *name, unsigned moduleid); static void dbll_purge_symbol_table(struct dynamic_loader_sym *this, - unsigned moduleId); + unsigned module_id); static void *allocate(struct dynamic_loader_sym *this, unsigned memsize); -static void deallocate(struct dynamic_loader_sym *this, void *memPtr); +static void deallocate(struct dynamic_loader_sym *this, void *mem_ptr); static void dbll_err_report(struct dynamic_loader_sym *this, const char *errstr, va_list args); /* dynamic_loader_allocate */ @@ -1094,7 +1094,7 @@ static struct dynload_symbol *find_in_symbol_table(struct dynamic_loader_sym */ static struct dynload_symbol *dbll_add_to_symbol_table(struct dynamic_loader_sym *this, const char *name, - unsigned moduleId) + unsigned module_id) { struct dbll_symbol *sym_ptr = NULL; struct dbll_symbol symbol; @@ -1150,7 +1150,7 @@ static struct dynload_symbol *dbll_add_to_symbol_table(struct dynamic_loader_sym * ======== dbll_purge_symbol_table ======== */ static void dbll_purge_symbol_table(struct dynamic_loader_sym *this, - unsigned moduleId) + unsigned module_id) { struct ldr_symbol *ldr_sym = (struct ldr_symbol *)this; struct dbll_library_obj *lib; @@ -1183,7 +1183,7 @@ static void *allocate(struct dynamic_loader_sym *this, unsigned memsize) /* * ======== deallocate ======== */ -static void deallocate(struct dynamic_loader_sym *this, void *memPtr) +static void deallocate(struct dynamic_loader_sym *this, void *mem_ptr) { struct ldr_symbol *ldr_sym = (struct ldr_symbol *)this; struct dbll_library_obj *lib; @@ -1192,7 +1192,7 @@ static void deallocate(struct dynamic_loader_sym *this, void *memPtr) lib = ldr_sym->lib; DBC_REQUIRE(lib); - kfree(memPtr); + kfree(mem_ptr); } /* diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index aac448e..eb4799d 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -101,7 +101,7 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, * device's bridge_brd_write() function. */ u32 dev_brd_write_fxn(void *pArb, u32 ulDspAddr, void *pHostBuf, - u32 ul_num_bytes, u32 nMemSpace) + u32 ul_num_bytes, u32 mem_space) { struct dev_object *dev_obj = (struct dev_object *)pArb; u32 ul_written = 0; @@ -114,7 +114,7 @@ u32 dev_brd_write_fxn(void *pArb, u32 ulDspAddr, void *pHostBuf, DBC_ASSERT(dev_obj->hbridge_context != NULL); status = (*dev_obj->bridge_interface.pfn_brd_write) ( dev_obj->hbridge_context, pHostBuf, - ulDspAddr, ul_num_bytes, nMemSpace); + ulDspAddr, ul_num_bytes, mem_space); /* Special case of getting the address only */ if (ul_num_bytes == 0) ul_num_bytes = 1; diff --git a/drivers/staging/tidspbridge/pmgr/msg.c b/drivers/staging/tidspbridge/pmgr/msg.c index 64f1cb4..6122cd4 100644 --- a/drivers/staging/tidspbridge/pmgr/msg.c +++ b/drivers/staging/tidspbridge/pmgr/msg.c @@ -46,7 +46,7 @@ static u32 refs; /* module reference count */ * can exist per device object. */ int msg_create(OUT struct msg_mgr **phMsgMgr, - struct dev_object *hdev_obj, msg_onexit msgCallback) + struct dev_object *hdev_obj, msg_onexit msg_callback) { struct bridge_drv_interface *intf_fxns; struct msg_mgr_ *msg_mgr_obj; @@ -55,7 +55,7 @@ int msg_create(OUT struct msg_mgr **phMsgMgr, DBC_REQUIRE(refs > 0); DBC_REQUIRE(phMsgMgr != NULL); - DBC_REQUIRE(msgCallback != NULL); + DBC_REQUIRE(msg_callback != NULL); DBC_REQUIRE(hdev_obj != NULL); *phMsgMgr = NULL; @@ -64,7 +64,7 @@ int msg_create(OUT struct msg_mgr **phMsgMgr, /* Let Bridge message module finish the create: */ status = - (*intf_fxns->pfn_msg_create) (&hmsg_mgr, hdev_obj, msgCallback); + (*intf_fxns->pfn_msg_create) (&hmsg_mgr, hdev_obj, msg_callback); if (DSP_SUCCEEDED(status)) { /* Fill in DSP API message module's fields of the msg_mgr diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 4fe96bf..9d05166 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -327,7 +327,7 @@ void dcd_exit(void) */ int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - u16 numLibs, OUT struct dsp_uuid *pDepLibUuids, + u16 num_libs, OUT struct dsp_uuid *pDepLibUuids, OUT bool *pPersistentDepLibs, IN enum nldr_phase phase) { @@ -340,7 +340,7 @@ int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, DBC_REQUIRE(pPersistentDepLibs != NULL); status = - get_dep_lib_info(hdcd_mgr, uuid_obj, &numLibs, NULL, pDepLibUuids, + get_dep_lib_info(hdcd_mgr, uuid_obj, &num_libs, NULL, pDepLibUuids, pPersistentDepLibs, phase); return status; diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 36ddfdf..4abfd81 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -375,7 +375,7 @@ int drv_remove_all_strm_res_elements(void *process_ctxt) } /* Getting the stream resource element */ -int drv_get_strm_res_element(void *hStrm, void *hstrm_res, +int drv_get_strm_res_element(void *stream_obj, void *hstrm_res, void *process_ctxt) { struct strm_res_object **strm_res = @@ -389,7 +389,7 @@ int drv_get_strm_res_element(void *hStrm, void *hstrm_res, return -EPERM; temp_strm = ctxt->pstrm_list; - while ((temp_strm != NULL) && (temp_strm->hstream != hStrm)) { + while ((temp_strm != NULL) && (temp_strm->hstream != stream_obj)) { temp_strm2 = temp_strm; temp_strm = temp_strm->next; } diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index aaea5bb..d19d990 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -258,9 +258,9 @@ static int get_proc_props(struct node_mgr *hnode_mgr, struct dev_object *hdev_obj); static int get_rms_fxns(struct node_mgr *hnode_mgr); static u32 ovly(void *priv_ref, u32 ulDspRunAddr, u32 ulDspLoadAddr, - u32 ul_num_bytes, u32 nMemSpace); + u32 ul_num_bytes, u32 mem_space); static u32 mem_write(void *priv_ref, u32 ulDspAddr, void *pbuf, - u32 ul_num_bytes, u32 nMemSpace); + u32 ul_num_bytes, u32 mem_space); static u32 refs; /* module reference count */ @@ -1987,14 +1987,14 @@ bool node_init(void) * Purpose: * Gets called when RMS_EXIT is received for a node. */ -void node_on_exit(struct node_object *hnode, s32 nStatus) +void node_on_exit(struct node_object *hnode, s32 node_status) { if (!hnode) return; /* Set node state to done */ NODE_SET_STATE(hnode, NODE_DONE); - hnode->exit_status = nStatus; + hnode->exit_status = node_status; if (hnode->loaded && hnode->phase_split) { (void)hnode->hnode_mgr->nldr_fxns.pfn_unload(hnode-> nldr_node_obj, @@ -3128,7 +3128,7 @@ static int get_rms_fxns(struct node_mgr *hnode_mgr) * Called during overlay.Sends command to RMS to copy a block of data. */ static u32 ovly(void *priv_ref, u32 ulDspRunAddr, u32 ulDspLoadAddr, - u32 ul_num_bytes, u32 nMemSpace) + u32 ul_num_bytes, u32 mem_space) { struct node_object *hnode = (struct node_object *)priv_ref; struct node_mgr *hnode_mgr; @@ -3154,7 +3154,7 @@ static u32 ovly(void *priv_ref, u32 ulDspRunAddr, u32 ulDspLoadAddr, status = (*intf_fxns->pfn_brd_mem_copy) (hbridge_context, ulDspRunAddr, ulDspLoadAddr, - ul_num_bytes, (u32) nMemSpace); + ul_num_bytes, (u32) mem_space); if (DSP_SUCCEEDED(status)) ul_bytes = ul_num_bytes; else @@ -3172,7 +3172,7 @@ static u32 ovly(void *priv_ref, u32 ulDspRunAddr, u32 ulDspLoadAddr, * ======== mem_write ======== */ static u32 mem_write(void *priv_ref, u32 ulDspAddr, void *pbuf, - u32 ul_num_bytes, u32 nMemSpace) + u32 ul_num_bytes, u32 mem_space) { struct node_object *hnode = (struct node_object *)priv_ref; struct node_mgr *hnode_mgr; @@ -3184,12 +3184,12 @@ static u32 mem_write(void *priv_ref, u32 ulDspAddr, void *pbuf, struct bridge_drv_interface *intf_fxns; DBC_REQUIRE(hnode); - DBC_REQUIRE(nMemSpace & DBLL_CODE || nMemSpace & DBLL_DATA); + DBC_REQUIRE(mem_space & DBLL_CODE || mem_space & DBLL_DATA); hnode_mgr = hnode->hnode_mgr; ul_timeout = hnode->utimeout; - mem_sect_type = (nMemSpace & DBLL_CODE) ? RMS_CODE : RMS_DATA; + mem_sect_type = (mem_space & DBLL_CODE) ? RMS_CODE : RMS_DATA; /* Call new MemWrite function */ intf_fxns = hnode_mgr->intf_fxns; diff --git a/drivers/staging/tidspbridge/rmgr/strm.c b/drivers/staging/tidspbridge/rmgr/strm.c index ffacfd4..795332e 100644 --- a/drivers/staging/tidspbridge/rmgr/strm.c +++ b/drivers/staging/tidspbridge/rmgr/strm.c @@ -88,7 +88,7 @@ struct strm_object { static u32 refs; /* module reference count */ /* ----------------------------------- Function Prototypes */ -static int delete_strm(struct strm_object *hStrm); +static int delete_strm(struct strm_object *stream_obj); static void delete_strm_mgr(struct strm_mgr *strm_mgr_obj); /* @@ -96,7 +96,7 @@ static void delete_strm_mgr(struct strm_mgr *strm_mgr_obj); * Purpose: * Allocates buffers for a stream. */ -int strm_allocate_buffer(struct strm_object *hStrm, u32 usize, +int strm_allocate_buffer(struct strm_object *stream_obj, u32 usize, OUT u8 **ap_buffer, u32 num_bufs, struct process_context *pr_ctxt) { @@ -109,7 +109,7 @@ int strm_allocate_buffer(struct strm_object *hStrm, u32 usize, DBC_REQUIRE(refs > 0); DBC_REQUIRE(ap_buffer != NULL); - if (hStrm) { + if (stream_obj) { /* * Allocate from segment specified at time of stream open. */ @@ -124,8 +124,9 @@ int strm_allocate_buffer(struct strm_object *hStrm, u32 usize, goto func_end; for (i = 0; i < num_bufs; i++) { - DBC_ASSERT(hStrm->xlator != NULL); - (void)cmm_xlator_alloc_buf(hStrm->xlator, &ap_buffer[i], usize); + DBC_ASSERT(stream_obj->xlator != NULL); + (void)cmm_xlator_alloc_buf(stream_obj->xlator, &ap_buffer[i], + usize); if (ap_buffer[i] == NULL) { status = -ENOMEM; alloc_cnt = i; @@ -133,12 +134,12 @@ int strm_allocate_buffer(struct strm_object *hStrm, u32 usize, } } if (DSP_FAILED(status)) - strm_free_buffer(hStrm, ap_buffer, alloc_cnt, pr_ctxt); + strm_free_buffer(stream_obj, ap_buffer, alloc_cnt, pr_ctxt); if (DSP_FAILED(status)) goto func_end; - if (drv_get_strm_res_element(hStrm, &hstrm_res, pr_ctxt) != + if (drv_get_strm_res_element(stream_obj, &hstrm_res, pr_ctxt) != -ENOENT) drv_proc_update_strm_res(num_bufs, hstrm_res); @@ -151,7 +152,7 @@ func_end: * Purpose: * Close a stream opened with strm_open(). */ -int strm_close(struct strm_object *hStrm, +int strm_close(struct strm_object *stream_obj, struct process_context *pr_ctxt) { struct bridge_drv_interface *intf_fxns; @@ -162,35 +163,35 @@ int strm_close(struct strm_object *hStrm, DBC_REQUIRE(refs > 0); - if (!hStrm) { + if (!stream_obj) { status = -EFAULT; } else { /* Have all buffers been reclaimed? If not, return * -EPIPE */ - intf_fxns = hStrm->strm_mgr_obj->intf_fxns; + intf_fxns = stream_obj->strm_mgr_obj->intf_fxns; status = - (*intf_fxns->pfn_chnl_get_info) (hStrm->chnl_obj, + (*intf_fxns->pfn_chnl_get_info) (stream_obj->chnl_obj, &chnl_info_obj); DBC_ASSERT(DSP_SUCCEEDED(status)); if (chnl_info_obj.cio_cs > 0 || chnl_info_obj.cio_reqs > 0) status = -EPIPE; else - status = delete_strm(hStrm); + status = delete_strm(stream_obj); } if (DSP_FAILED(status)) goto func_end; - if (drv_get_strm_res_element(hStrm, &hstrm_res, pr_ctxt) != + if (drv_get_strm_res_element(stream_obj, &hstrm_res, pr_ctxt) != -ENOENT) drv_proc_remove_strm_res_element(hstrm_res, pr_ctxt); func_end: DBC_ENSURE(status == 0 || status == -EFAULT || status == -EPIPE || status == -EPERM); - dev_dbg(bridge, "%s: hStrm: %p, status 0x%x\n", __func__, - hStrm, status); + dev_dbg(bridge, "%s: stream_obj: %p, status 0x%x\n", __func__, + stream_obj, status); return status; } @@ -270,7 +271,7 @@ void strm_exit(void) * Purpose: * Frees the buffers allocated for a stream. */ -int strm_free_buffer(struct strm_object *hStrm, u8 ** ap_buffer, +int strm_free_buffer(struct strm_object *stream_obj, u8 ** ap_buffer, u32 num_bufs, struct process_context *pr_ctxt) { int status = 0; @@ -281,20 +282,21 @@ int strm_free_buffer(struct strm_object *hStrm, u8 ** ap_buffer, DBC_REQUIRE(refs > 0); DBC_REQUIRE(ap_buffer != NULL); - if (!hStrm) + if (!stream_obj) status = -EFAULT; if (DSP_SUCCEEDED(status)) { for (i = 0; i < num_bufs; i++) { - DBC_ASSERT(hStrm->xlator != NULL); + DBC_ASSERT(stream_obj->xlator != NULL); status = - cmm_xlator_free_buf(hStrm->xlator, ap_buffer[i]); + cmm_xlator_free_buf(stream_obj->xlator, + ap_buffer[i]); if (DSP_FAILED(status)) break; ap_buffer[i] = NULL; } } - if (drv_get_strm_res_element(hStrm, hstrm_res, pr_ctxt) != + if (drv_get_strm_res_element(stream_obj, hstrm_res, pr_ctxt) != -ENOENT) drv_proc_update_strm_res(num_bufs - i, hstrm_res); @@ -306,7 +308,7 @@ int strm_free_buffer(struct strm_object *hStrm, u8 ** ap_buffer, * Purpose: * Retrieves information about a stream. */ -int strm_get_info(struct strm_object *hStrm, +int strm_get_info(struct strm_object *stream_obj, OUT struct stream_info *stream_info, u32 stream_info_size) { @@ -319,7 +321,7 @@ int strm_get_info(struct strm_object *hStrm, DBC_REQUIRE(stream_info != NULL); DBC_REQUIRE(stream_info_size >= sizeof(struct stream_info)); - if (!hStrm) { + if (!stream_obj) { status = -EFAULT; } else { if (stream_info_size < sizeof(struct stream_info)) { @@ -330,22 +332,23 @@ int strm_get_info(struct strm_object *hStrm, if (DSP_FAILED(status)) goto func_end; - intf_fxns = hStrm->strm_mgr_obj->intf_fxns; + intf_fxns = stream_obj->strm_mgr_obj->intf_fxns; status = - (*intf_fxns->pfn_chnl_get_info) (hStrm->chnl_obj, &chnl_info_obj); + (*intf_fxns->pfn_chnl_get_info) (stream_obj->chnl_obj, + &chnl_info_obj); if (DSP_FAILED(status)) goto func_end; - if (hStrm->xlator) { + if (stream_obj->xlator) { /* We have a translator */ - DBC_ASSERT(hStrm->segment_id > 0); - cmm_xlator_info(hStrm->xlator, (u8 **) &virt_base, 0, - hStrm->segment_id, false); + DBC_ASSERT(stream_obj->segment_id > 0); + cmm_xlator_info(stream_obj->xlator, (u8 **) &virt_base, 0, + stream_obj->segment_id, false); } - stream_info->segment_id = hStrm->segment_id; - stream_info->strm_mode = hStrm->strm_mode; + stream_info->segment_id = stream_obj->segment_id; + stream_info->strm_mode = stream_obj->strm_mode; stream_info->virt_base = virt_base; - stream_info->user_strm->number_bufs_allowed = hStrm->num_bufs; + stream_info->user_strm->number_bufs_allowed = stream_obj->num_bufs; stream_info->user_strm->number_bufs_in_stream = chnl_info_obj.cio_cs + chnl_info_obj.cio_reqs; /* # of bytes transferred since last call to DSPStream_Idle() */ @@ -373,25 +376,25 @@ func_end: * Purpose: * Idles a particular stream. */ -int strm_idle(struct strm_object *hStrm, bool flush_data) +int strm_idle(struct strm_object *stream_obj, bool flush_data) { struct bridge_drv_interface *intf_fxns; int status = 0; DBC_REQUIRE(refs > 0); - if (!hStrm) { + if (!stream_obj) { status = -EFAULT; } else { - intf_fxns = hStrm->strm_mgr_obj->intf_fxns; + intf_fxns = stream_obj->strm_mgr_obj->intf_fxns; - status = (*intf_fxns->pfn_chnl_idle) (hStrm->chnl_obj, - hStrm->utimeout, + status = (*intf_fxns->pfn_chnl_idle) (stream_obj->chnl_obj, + stream_obj->utimeout, flush_data); } - dev_dbg(bridge, "%s: hStrm: %p flush_data: 0x%x status: 0x%x\n", - __func__, hStrm, flush_data, status); + dev_dbg(bridge, "%s: stream_obj: %p flush_data: 0x%x status: 0x%x\n", + __func__, stream_obj, flush_data, status); return status; } @@ -419,7 +422,7 @@ bool strm_init(void) * Purpose: * Issues a buffer on a stream */ -int strm_issue(struct strm_object *hStrm, IN u8 *pbuf, u32 ul_bytes, +int strm_issue(struct strm_object *stream_obj, IN u8 *pbuf, u32 ul_bytes, u32 ul_buf_size, u32 dw_arg) { struct bridge_drv_interface *intf_fxns; @@ -429,13 +432,13 @@ int strm_issue(struct strm_object *hStrm, IN u8 *pbuf, u32 ul_bytes, DBC_REQUIRE(refs > 0); DBC_REQUIRE(pbuf != NULL); - if (!hStrm) { + if (!stream_obj) { status = -EFAULT; } else { - intf_fxns = hStrm->strm_mgr_obj->intf_fxns; + intf_fxns = stream_obj->strm_mgr_obj->intf_fxns; - if (hStrm->segment_id != 0) { - tmp_buf = cmm_xlator_translate(hStrm->xlator, + if (stream_obj->segment_id != 0) { + tmp_buf = cmm_xlator_translate(stream_obj->xlator, (void *)pbuf, CMM_VA2DSPPA); if (tmp_buf == NULL) @@ -444,15 +447,15 @@ int strm_issue(struct strm_object *hStrm, IN u8 *pbuf, u32 ul_bytes, } if (DSP_SUCCEEDED(status)) { status = (*intf_fxns->pfn_chnl_add_io_req) - (hStrm->chnl_obj, pbuf, ul_bytes, ul_buf_size, + (stream_obj->chnl_obj, pbuf, ul_bytes, ul_buf_size, (u32) tmp_buf, dw_arg); } if (status == -EIO) status = -ENOSR; } - dev_dbg(bridge, "%s: hStrm: %p pbuf: %p ul_bytes: 0x%x dw_arg: 0x%x " - "status: 0x%x\n", __func__, hStrm, pbuf, + dev_dbg(bridge, "%s: stream_obj: %p pbuf: %p ul_bytes: 0x%x dw_arg:" + " 0x%x status: 0x%x\n", __func__, stream_obj, pbuf, ul_bytes, dw_arg, status); return status; } @@ -615,7 +618,7 @@ func_cont: * Purpose: * Relcaims a buffer from a stream. */ -int strm_reclaim(struct strm_object *hStrm, OUT u8 ** buf_ptr, +int strm_reclaim(struct strm_object *stream_obj, OUT u8 ** buf_ptr, u32 *pulBytes, u32 *pulBufSize, u32 *pdw_arg) { struct bridge_drv_interface *intf_fxns; @@ -628,14 +631,15 @@ int strm_reclaim(struct strm_object *hStrm, OUT u8 ** buf_ptr, DBC_REQUIRE(pulBytes != NULL); DBC_REQUIRE(pdw_arg != NULL); - if (!hStrm) { + if (!stream_obj) { status = -EFAULT; goto func_end; } - intf_fxns = hStrm->strm_mgr_obj->intf_fxns; + intf_fxns = stream_obj->strm_mgr_obj->intf_fxns; status = - (*intf_fxns->pfn_chnl_get_ioc) (hStrm->chnl_obj, hStrm->utimeout, + (*intf_fxns->pfn_chnl_get_ioc) (stream_obj->chnl_obj, + stream_obj->utimeout, &chnl_ioc_obj); if (DSP_SUCCEEDED(status)) { *pulBytes = chnl_ioc_obj.byte_size; @@ -656,7 +660,7 @@ int strm_reclaim(struct strm_object *hStrm, OUT u8 ** buf_ptr, /* Translate zerocopy buffer if channel not canceled. */ if (DSP_SUCCEEDED(status) && (!CHNL_IS_IO_CANCELLED(chnl_ioc_obj)) - && (hStrm->strm_mode == STRMMODE_ZEROCOPY)) { + && (stream_obj->strm_mode == STRMMODE_ZEROCOPY)) { /* * This is a zero-copy channel so chnl_ioc_obj.pbuf * contains the DSP address of SM. We need to @@ -664,12 +668,13 @@ int strm_reclaim(struct strm_object *hStrm, OUT u8 ** buf_ptr, * thread to access. * Note: Could add CMM_DSPPA2VA to CMM in the future. */ - tmp_buf = cmm_xlator_translate(hStrm->xlator, + tmp_buf = cmm_xlator_translate(stream_obj->xlator, chnl_ioc_obj.pbuf, CMM_DSPPA2PA); if (tmp_buf != NULL) { /* now convert this GPP Pa to Va */ - tmp_buf = cmm_xlator_translate(hStrm->xlator, + tmp_buf = cmm_xlator_translate(stream_obj-> + xlator, tmp_buf, CMM_PA2VA); } @@ -686,8 +691,8 @@ func_end: status == -ETIME || status == -ESRCH || status == -EPERM); - dev_dbg(bridge, "%s: hStrm: %p buf_ptr: %p pulBytes: %p pdw_arg: %p " - "status 0x%x\n", __func__, hStrm, + dev_dbg(bridge, "%s: stream_obj: %p buf_ptr: %p pulBytes: %p " + "pdw_arg: %p status 0x%x\n", __func__, stream_obj, buf_ptr, pulBytes, pdw_arg, status); return status; } @@ -697,7 +702,7 @@ func_end: * Purpose: * Register to be notified on specific events for this stream. */ -int strm_register_notify(struct strm_object *hStrm, u32 event_mask, +int strm_register_notify(struct strm_object *stream_obj, u32 event_mask, u32 notify_type, struct dsp_notification * hnotification) { @@ -707,7 +712,7 @@ int strm_register_notify(struct strm_object *hStrm, u32 event_mask, DBC_REQUIRE(refs > 0); DBC_REQUIRE(hnotification != NULL); - if (!hStrm) { + if (!stream_obj) { status = -EFAULT; } else if ((event_mask & ~((DSP_STREAMIOCOMPLETION) | DSP_STREAMDONE)) != 0) { @@ -718,10 +723,11 @@ int strm_register_notify(struct strm_object *hStrm, u32 event_mask, } if (DSP_SUCCEEDED(status)) { - intf_fxns = hStrm->strm_mgr_obj->intf_fxns; + intf_fxns = stream_obj->strm_mgr_obj->intf_fxns; status = - (*intf_fxns->pfn_chnl_register_notify) (hStrm->chnl_obj, + (*intf_fxns->pfn_chnl_register_notify) (stream_obj-> + chnl_obj, event_mask, notify_type, hnotification); @@ -738,7 +744,7 @@ int strm_register_notify(struct strm_object *hStrm, u32 event_mask, * Purpose: * Selects a ready stream. */ -int strm_select(IN struct strm_object **strm_tab, u32 nStrms, +int strm_select(IN struct strm_object **strm_tab, u32 strms, OUT u32 *pmask, u32 utimeout) { u32 index; @@ -751,10 +757,10 @@ int strm_select(IN struct strm_object **strm_tab, u32 nStrms, DBC_REQUIRE(refs > 0); DBC_REQUIRE(strm_tab != NULL); DBC_REQUIRE(pmask != NULL); - DBC_REQUIRE(nStrms > 0); + DBC_REQUIRE(strms > 0); *pmask = 0; - for (i = 0; i < nStrms; i++) { + for (i = 0; i < strms; i++) { if (!strm_tab[i]) { status = -EFAULT; break; @@ -764,7 +770,7 @@ int strm_select(IN struct strm_object **strm_tab, u32 nStrms, goto func_end; /* Determine which channels have IO ready */ - for (i = 0; i < nStrms; i++) { + for (i = 0; i < strms; i++) { intf_fxns = strm_tab[i]->strm_mgr_obj->intf_fxns; status = (*intf_fxns->pfn_chnl_get_info) (strm_tab[i]->chnl_obj, &chnl_info_obj); @@ -778,13 +784,13 @@ int strm_select(IN struct strm_object **strm_tab, u32 nStrms, } if (DSP_SUCCEEDED(status) && utimeout > 0 && *pmask == 0) { /* Non-zero timeout */ - sync_events = kmalloc(nStrms * sizeof(struct sync_object *), + sync_events = kmalloc(strms * sizeof(struct sync_object *), GFP_KERNEL); if (sync_events == NULL) { status = -ENOMEM; } else { - for (i = 0; i < nStrms; i++) { + for (i = 0; i < strms; i++) { intf_fxns = strm_tab[i]->strm_mgr_obj->intf_fxns; status = (*intf_fxns->pfn_chnl_get_info) @@ -799,7 +805,7 @@ int strm_select(IN struct strm_object **strm_tab, u32 nStrms, } if (DSP_SUCCEEDED(status)) { status = - sync_wait_on_multiple_events(sync_events, nStrms, + sync_wait_on_multiple_events(sync_events, strms, utimeout, &index); if (DSP_SUCCEEDED(status)) { /* Since we waited on the event, we have to @@ -823,27 +829,29 @@ func_end: * Purpose: * Frees the resources allocated for a stream. */ -static int delete_strm(struct strm_object *hStrm) +static int delete_strm(struct strm_object *stream_obj) { struct bridge_drv_interface *intf_fxns; int status = 0; - if (hStrm) { - if (hStrm->chnl_obj) { - intf_fxns = hStrm->strm_mgr_obj->intf_fxns; + if (stream_obj) { + if (stream_obj->chnl_obj) { + intf_fxns = stream_obj->strm_mgr_obj->intf_fxns; /* Channel close can fail only if the channel handle * is invalid. */ - status = (*intf_fxns->pfn_chnl_close) (hStrm->chnl_obj); + status = (*intf_fxns->pfn_chnl_close) + (stream_obj->chnl_obj); /* Free all SM address translator resources */ if (DSP_SUCCEEDED(status)) { - if (hStrm->xlator) { + if (stream_obj->xlator) { /* force free */ - (void)cmm_xlator_delete(hStrm->xlator, + (void)cmm_xlator_delete(stream_obj-> + xlator, true); } } } - kfree(hStrm); + kfree(stream_obj); } else { status = -EFAULT; } From patchwork Fri May 21 15:22:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nagarajan, Rajkumar" X-Patchwork-Id: 101435 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4LFMfnk003015 for ; Fri, 21 May 2010 15:22:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933438Ab0EUPW0 (ORCPT ); Fri, 21 May 2010 11:22:26 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:33329 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933449Ab0EUPWZ convert rfc822-to-8bit (ORCPT ); Fri, 21 May 2010 11:22:25 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4LFMLsu005825 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 21 May 2010 10:22:24 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4LFML7h016687 for ; Fri, 21 May 2010 20:52:21 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Fri, 21 May 2010 20:52:21 +0530 From: "Nagarajan, Rajkumar" To: "linux-omap@vger.kernel.org" Date: Fri, 21 May 2010 20:52:20 +0530 Subject: [PATCH V6] OMAP: DSS: Add NEC NL8048HL11-01B display panel Thread-Topic: [PATCH V6] OMAP: DSS: Add NEC NL8048HL11-01B display panel Thread-Index: Acr4+leazIXF9nCBTeGJgkDEzE12mg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 21 May 2010 15:22:41 +0000 (UTC) diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig index 5f568a2..83f3224 100644 --- a/drivers/video/omap2/displays/Kconfig +++ b/drivers/video/omap2/displays/Kconfig @@ -37,6 +37,12 @@ config PANEL_TPO_TD043MTEA1 help LCD Panel used in OMAP3 Pandora +config PANEL_NEC_NL8048HL11_01B + tristate "NEC NL8048HL11-01B Panel support" + depends on OMAP2_DSS + help + LCD Panel from NEC. + config PANEL_ACX565AKM tristate "ACX565AKM Panel" depends on OMAP2_DSS_SDI diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile index aa38609..fc8aca3 100644 --- a/drivers/video/omap2/displays/Makefile +++ b/drivers/video/omap2/displays/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PANEL_SHARP_LQ043T1DG01) += panel-sharp-lq043t1dg01.o obj-$(CONFIG_PANEL_TAAL) += panel-taal.o obj-$(CONFIG_PANEL_TOPPOLY_TDO35S) += panel-toppoly-tdo35s.o obj-$(CONFIG_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o +obj-$(CONFIG_PANEL_NEC_NL8048HL11_01B) += panel-nec-nl8048hl11-01b.o obj-$(CONFIG_PANEL_ACX565AKM) += panel-acx565akm.o diff --git a/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c b/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c new file mode 100644 index 0000000..ced8df2 --- /dev/null +++ b/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c @@ -0,0 +1,281 @@ +/* + * NEC panel support + * + * Copyright (C) 2010 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include + +#include + +#define LCD_XRES 800 +#define LCD_YRES 480 +/* NEC PIX Clock Ratings + * MIN:21.8MHz TYP:23.8MHz MAX:25.7MHz + */ +#define LCD_PIXEL_CLOCK 23800 + +/* NEC NL8048HL11-01B Manual + * defines HFB, HSW, HBP, VFP, VSW, VBP as shown below + */ + +static struct omap_video_timings nec_8048_panel_timings = { + /* 800 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ + .x_res = LCD_XRES, + .y_res = LCD_YRES, + .pixel_clock = LCD_PIXEL_CLOCK, + .hfp = 6, + .hsw = 1, + .hbp = 4, + .vfp = 3, + .vsw = 1, + .vbp = 4, +}; + +static int nec_8048_panel_probe(struct omap_dss_device *dssdev) +{ + dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_RF | + OMAP_DSS_LCD_ONOFF; + dssdev->panel.timings = nec_8048_panel_timings; + + return 0; +} + +static void nec_8048_panel_remove(struct omap_dss_device *dssdev) +{ +} + +static int nec_8048_panel_enable(struct omap_dss_device *dssdev) +{ + int r = 0; + + if (dssdev->platform_enable) + r = dssdev->platform_enable(dssdev); + omapdss_dpi_display_enable(dssdev); + + return r; +} + +static void nec_8048_panel_disable(struct omap_dss_device *dssdev) +{ + omapdss_dpi_display_disable(dssdev); + if (dssdev->platform_disable) + dssdev->platform_disable(dssdev); +} + +static int nec_8048_panel_suspend(struct omap_dss_device *dssdev) +{ + nec_8048_panel_disable(dssdev); + return 0; +} + +static int nec_8048_panel_resume(struct omap_dss_device *dssdev) +{ + return nec_8048_panel_enable(dssdev); +} + +static int nec_8048_recommended_bpp(struct omap_dss_device *dssdev) +{ + return 16; +} + +static struct omap_dss_driver nec_8048_driver = { + .probe = nec_8048_panel_probe, + .remove = nec_8048_panel_remove, + .enable = nec_8048_panel_enable, + .disable = nec_8048_panel_disable, + .suspend = nec_8048_panel_suspend, + .resume = nec_8048_panel_resume, + .get_recommended_bpp = nec_8048_recommended_bpp, + .driver = { + .name = "NEC_8048_panel", + .owner = THIS_MODULE, + }, +}; + +static int +spi_send(struct spi_device *spi, unsigned char reg_addr, unsigned char reg_data) +{ + int ret = 0; + unsigned int cmd = 0, data = 0; + + cmd = 0x0000 | reg_addr; /* register address write */ + data = 0x0100 | reg_data; /* register data write */ + data = (cmd << 16) | data; + ret = spi_write(spi, (unsigned char *)&data, 4); + if (ret) { + printk(KERN_ERR "error in spi_write %x\n", data); + return ret; + } + + return 0; +} + +static int init_nec_8048_wvga_lcd(struct spi_device *spi) +{ + /* Initialization Sequence */ + /* spi_send(spi, REG, VAL) */ + spi_send(spi, 3, 0x01); + spi_send(spi, 0, 0x00); + spi_send(spi, 1, 0x01); /* R1 = 0x01 (normal), 0x03 (reversed) */ + spi_send(spi, 4, 0x00); + spi_send(spi, 5, 0x14); + spi_send(spi, 6, 0x24); + spi_send(spi, 16, 0xD7); + spi_send(spi, 17, 0x00); + spi_send(spi, 18, 0x00); + spi_send(spi, 19, 0x55); + spi_send(spi, 20, 0x01); + spi_send(spi, 21, 0x70); + spi_send(spi, 22, 0x1E); + spi_send(spi, 23, 0x25); + spi_send(spi, 24, 0x25); + spi_send(spi, 25, 0x02); + spi_send(spi, 26, 0x02); + spi_send(spi, 27, 0xA0); + spi_send(spi, 32, 0x2F); + spi_send(spi, 33, 0x0F); + spi_send(spi, 34, 0x0F); + spi_send(spi, 35, 0x0F); + spi_send(spi, 36, 0x0F); + spi_send(spi, 37, 0x0F); + spi_send(spi, 38, 0x0F); + spi_send(spi, 39, 0x00); + spi_send(spi, 40, 0x02); + spi_send(spi, 41, 0x02); + spi_send(spi, 42, 0x02); + spi_send(spi, 43, 0x0F); + spi_send(spi, 44, 0x0F); + spi_send(spi, 45, 0x0F); + spi_send(spi, 46, 0x0F); + spi_send(spi, 47, 0x0F); + spi_send(spi, 48, 0x0F); + spi_send(spi, 49, 0x0F); + spi_send(spi, 50, 0x00); + spi_send(spi, 51, 0x02); + spi_send(spi, 52, 0x02); + spi_send(spi, 53, 0x02); + spi_send(spi, 80, 0x0C); + spi_send(spi, 83, 0x42); + spi_send(spi, 84, 0x42); + spi_send(spi, 85, 0x41); + spi_send(spi, 86, 0x14); + spi_send(spi, 89, 0x88); + spi_send(spi, 90, 0x01); + spi_send(spi, 91, 0x00); + spi_send(spi, 92, 0x02); + spi_send(spi, 93, 0x0C); + spi_send(spi, 94, 0x1C); + spi_send(spi, 95, 0x27); + spi_send(spi, 98, 0x49); + spi_send(spi, 99, 0x27); + spi_send(spi, 102, 0x76); + spi_send(spi, 103, 0x27); + spi_send(spi, 112, 0x01); + spi_send(spi, 113, 0x0E); + spi_send(spi, 114, 0x02); + spi_send(spi, 115, 0x0C); + spi_send(spi, 118, 0x0C); + spi_send(spi, 121, 0x30); /* R121 = 0x30 (normal), 0x10 (reversed) */ + spi_send(spi, 130, 0x00); + spi_send(spi, 131, 0x00); + spi_send(spi, 132, 0xFC); + spi_send(spi, 134, 0x00); + spi_send(spi, 136, 0x00); + spi_send(spi, 138, 0x00); + spi_send(spi, 139, 0x00); + spi_send(spi, 140, 0x00); + spi_send(spi, 141, 0xFC); + spi_send(spi, 143, 0x00); + spi_send(spi, 145, 0x00); + spi_send(spi, 147, 0x00); + spi_send(spi, 148, 0x00); + spi_send(spi, 149, 0x00); + spi_send(spi, 150, 0xFC); + spi_send(spi, 152, 0x00); + spi_send(spi, 154, 0x00); + spi_send(spi, 156, 0x00); + spi_send(spi, 157, 0x00); + udelay(20); + spi_send(spi, 2, 0x00); + + return 0; +} + +static int nec_8048_spi_probe(struct spi_device *spi) +{ + spi->mode = SPI_MODE_0; + spi->bits_per_word = 32; + spi_setup(spi); + + init_nec_8048_wvga_lcd(spi); + + return omap_dss_register_driver(&nec_8048_driver); +} + +static int nec_8048_spi_remove(struct spi_device *spi) +{ + omap_dss_unregister_driver(&nec_8048_driver); + + return 0; +} + +static int nec_8048_spi_suspend(struct spi_device *spi, pm_message_t mesg) +{ + spi_send(spi, 2, 0x01); + mdelay(40); + + return 0; +} + +static int nec_8048_spi_resume(struct spi_device *spi) +{ + /* reinitialize the panel */ + spi_setup(spi); + spi_send(spi, 2, 0x00); + init_nec_8048_wvga_lcd(spi); + + return 0; +} + +static struct spi_driver nec_8048_spi_driver = { + .probe = nec_8048_spi_probe, + .remove = __devexit_p(nec_8048_spi_remove), + .suspend = nec_8048_spi_suspend, + .resume = nec_8048_spi_resume, + .driver = { + .name = "nec_8048_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, +}; + +static int __init nec_8048_lcd_init(void) +{ + return spi_register_driver(&nec_8048_spi_driver); +} + +static void __exit nec_8048_lcd_exit(void) +{ + return spi_unregister_driver(&nec_8048_spi_driver); +} + +module_init(nec_8048_lcd_init); +module_exit(nec_8048_lcd_exit); +MODULE_LICENSE("GPL"); + From patchwork Fri May 21 15:17:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nagarajan, Rajkumar" X-Patchwork-Id: 101432 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4LFHm8V000868 for ; Fri, 21 May 2010 15:17:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932446Ab0EUPRq (ORCPT ); Fri, 21 May 2010 11:17:46 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:57951 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932381Ab0EUPRp convert rfc822-to-8bit (ORCPT ); Fri, 21 May 2010 11:17:45 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4LFHfrS009608 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 21 May 2010 10:17:44 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4LFHfSU014766 for ; Fri, 21 May 2010 20:47:41 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Fri, 21 May 2010 20:47:41 +0530 From: "Nagarajan, Rajkumar" To: "linux-omap@vger.kernel.org" Date: Fri, 21 May 2010 20:47:39 +0530 Subject: [PATCH 1/2 V7] OMAP: ZOOM2/3&SDP3630: Add display board file for zoom boards Thread-Topic: [PATCH 1/2 V7] OMAP: ZOOM2/3&SDP3630: Add display board file for zoom boards Thread-Index: Acr4+bBkXzIPn4vISAG8oLHPNGnJCg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 21 May 2010 15:17:48 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b03cbb4..a79e6f0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -125,14 +125,17 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-video.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ + board-zoom-display.o \ board-zoom-peripherals.o \ hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ + board-zoom-display.o \ board-zoom-peripherals.o \ hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ + board-zoom-display.o \ board-zoom-peripherals.o \ hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index a0a2a11..048afe3 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -97,6 +97,7 @@ static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); zoom_peripherals_init(); + zoom_display_init(OMAP_DSS_VENC_TYPE_SVIDEO); board_smc91x_init(); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c new file mode 100644 index 0000000..e6e4f08 --- /dev/null +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2010 Texas Instruments Inc. + * + * Modified from mach-omap2/board-zoom-peripherals.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LCD_PANEL_ENABLE_GPIO (7 + OMAP_MAX_GPIO_LINES) +#define LCD_PANEL_RESET_GPIO_PROD 96 +#define LCD_PANEL_RESET_GPIO_PILOT 55 +#define LCD_PANEL_QVGA_GPIO 56 +#define TV_PANEL_ENABLE_GPIO 95 + +static void zoom_lcd_tv_panel_init(void) +{ + int ret; + unsigned char lcd_panel_reset_gpio; + + lcd_panel_reset_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? + LCD_PANEL_RESET_GPIO_PROD : + LCD_PANEL_RESET_GPIO_PILOT; + + ret = gpio_request(lcd_panel_reset_gpio, "lcd reset"); + if (ret) { + pr_err("Failed to get LCD reset GPIO (gpio%d)\n", + lcd_panel_reset_gpio); + return; + } + gpio_direction_output(lcd_panel_reset_gpio, 1); + + ret = gpio_request(LCD_PANEL_QVGA_GPIO, "lcd qvga"); + if (ret) { + pr_err("Failed to get LCD_PANEL_QVGA_GPIO (gpio%d).\n", + LCD_PANEL_QVGA_GPIO); + goto err0; + } + gpio_direction_output(LCD_PANEL_QVGA_GPIO, 1); + + ret = gpio_request(TV_PANEL_ENABLE_GPIO, "tv panel"); + if (ret) { + pr_err("Failed to get TV_PANEL_ENABLE_GPIO (gpio%d).\n", + TV_PANEL_ENABLE_GPIO); + goto err1; + } + gpio_direction_output(TV_PANEL_ENABLE_GPIO, 1); + + return; + +err1: + gpio_free(LCD_PANEL_QVGA_GPIO); +err0: + gpio_free(lcd_panel_reset_gpio); +} + +static int zoom_panel_enable_lcd(struct omap_dss_device *dssdev) +{ + gpio_set_value(LCD_PANEL_ENABLE_GPIO, 1); + + return 0; +} + +static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev) +{ + gpio_set_value(LCD_PANEL_ENABLE_GPIO, 0); +} + +static int zoom_panel_enable_tv(struct omap_dss_device *dssdev) +{ + gpio_set_value(TV_PANEL_ENABLE_GPIO, 0); + + return 0; +} + +static void zoom_panel_disable_tv(struct omap_dss_device *dssdev) +{ + gpio_set_value(TV_PANEL_ENABLE_GPIO, 1); +} + +static struct omap_dss_device zoom_lcd_device = { + .name = "lcd", + .driver_name = "NEC_8048_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 24, + .platform_enable = zoom_panel_enable_lcd, + .platform_disable = zoom_panel_disable_lcd, +}; + +static struct omap_dss_device zoom_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = -1, + .platform_enable = zoom_panel_enable_tv, + .platform_disable = zoom_panel_disable_tv, +}; + +static struct omap_dss_device *zoom_dss_devices[] = { + &zoom_lcd_device, + &zoom_tv_device, +}; + +static struct omap_dss_board_info zoom_dss_data = { + .num_devices = ARRAY_SIZE(zoom_dss_devices), + .devices = zoom_dss_devices, + .default_device = &zoom_lcd_device, +}; + +static struct platform_device zoom_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &zoom_dss_data, + }, +}; + +static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { + .turbo_mode = 1, + .single_channel = 1, /* 0: slave, 1: master */ +}; + +static struct spi_board_info nec_8048_spi_board_info[] __initdata = { + [0] = { + .modalias = "nec_8048_spi", + .bus_num = 1, + .chip_select = 2, + .max_speed_hz = 375000, + .controller_data = &dss_lcd_mcspi_config, + }, +}; + +static struct platform_device *zoom_display_devices[] __initdata = { + &zoom_dss_device, +}; + +void __init zoom_display_init(enum omap_dss_venc_type venc_type) +{ + zoom_tv_device.phy.venc.type = venc_type; + platform_add_devices(zoom_display_devices, + ARRAY_SIZE(zoom_display_devices)); + spi_register_board_info(nec_8048_spi_board_info, + ARRAY_SIZE(nec_8048_spi_board_info)); + zoom_lcd_tv_panel_init(); +} + diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index ca95d8d..306167e 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -27,6 +27,8 @@ #include "mux.h" #include "hsmmc.h" +#define LCD_PANEL_ENABLE_GPIO (7 + OMAP_MAX_GPIO_LINES) + /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { KEY(0, 0, KEY_E), @@ -171,9 +173,43 @@ static struct omap2_hsmmc_info mmc[] __initdata = { {} /* Terminator */ }; +static struct regulator_consumer_supply zoom_vpll2_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); + +static struct regulator_consumer_supply zoom_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); + +static struct regulator_init_data zoom_vpll2 = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom_vpll2_supply, +}; + +static struct regulator_init_data zoom_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom_vdda_dac_supply, +}; + static int zoom_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { + int ret; + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ mmc[0].gpio_cd = gpio + 0; omap2_hsmmc_init(mmc); @@ -185,7 +221,15 @@ static int zoom_twl_gpio_setup(struct device *dev, zoom_vsim_supply.dev = mmc[0].dev; zoom_vmmc2_supply.dev = mmc[1].dev; - return 0; + ret = gpio_request(LCD_PANEL_ENABLE_GPIO, "lcd enable"); + if (ret) { + pr_err("Failed to get LCD_PANEL_ENABLE_GPIO (gpio%d).\n", + LCD_PANEL_ENABLE_GPIO); + return ret; + } + gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0); + + return ret; } @@ -243,6 +287,8 @@ static struct twl4030_platform_data zoom_twldata = { .vmmc1 = &zoom_vmmc1, .vmmc2 = &zoom_vmmc2, .vsim = &zoom_vsim, + .vpll2 = &zoom_vpll2, + .vdac = &zoom_vdac, }; diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 9a26f84..c432a21 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -82,6 +82,7 @@ static void __init omap_zoom2_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); zoom_peripherals_init(); zoom_debugboard_init(); + zoom_display_init(OMAP_DSS_VENC_TYPE_COMPOSITE); } static void __init omap_zoom2_map_io(void) diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index cd3e40c..25ed9b4 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -70,6 +70,7 @@ static void __init omap_zoom_init(void) omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); usb_ehci_init(&ehci_pdata); + zoom_display_init(OMAP_DSS_VENC_TYPE_COMPOSITE); } MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index c93b29e..aec73b4 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -1,5 +1,8 @@ /* * Defines for zoom boards */ +#include + extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); +extern void __init zoom_display_init(enum omap_dss_venc_type venc_type); From patchwork Thu Jun 24 11:17:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 107840 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5OBILMb019352 for ; Thu, 24 Jun 2010 11:18:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755013Ab0FXLSI (ORCPT ); Thu, 24 Jun 2010 07:18:08 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:46368 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754706Ab0FXLSG convert rfc822-to-8bit (ORCPT ); Thu, 24 Jun 2010 07:18:06 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5OBHwvP002454 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 24 Jun 2010 06:18:00 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5OBHtwk007457; Thu, 24 Jun 2010 16:47:56 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Thu, 24 Jun 2010 16:47:55 +0530 From: "Gupta, Ajay Kumar" To: "felipe.balbi@nokia.com" CC: "linux-usb@vger.kernel.org" , "linux-omap@vger.kernel.org" , "gregkh@suse.de" Date: Thu, 24 Jun 2010 16:47:54 +0530 Subject: RE: [PATCH 3/8] musb: fix compilation warning in host only mode Thread-Topic: [PATCH 3/8] musb: fix compilation warning in host only mode Thread-Index: AcsTY1iryAX5kqoYTI6+HCJRFRIDPgAK1KXA Message-ID: <19F8576C6E063C45BE387C64729E7394044E9E38CA@dbde02.ent.ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> <20100624060338.GF8078@nokia.com> In-Reply-To: <20100624060338.GF8078@nokia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 24 Jun 2010 11:18:21 +0000 (UTC) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index a8b0440..ed6e1a4 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -704,7 +704,6 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, #ifdef CONFIG_USB_MUSB_HDRC_HCD if (int_usb & MUSB_INTR_CONNECT) { struct usb_hcd *hcd = musb_to_hcd(musb); - void __iomem *mbase = musb->mregs; handled = IRQ_HANDLED; musb->is_active = 1; @@ -717,9 +716,9 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, if (is_peripheral_active(musb)) { /* REVISIT HNP; just force disconnect */ } - musb_writew(mbase, MUSB_INTRTXE, musb->epmask); - musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); - musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); + musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); + musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); + musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); #endif musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |USB_PORT_STAT_HIGH_SPEED From patchwork Mon May 24 07:07:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 101821 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4O78EBF024754 for ; Mon, 24 May 2010 07:08:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756365Ab0EXHIK (ORCPT ); Mon, 24 May 2010 03:08:10 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:44306 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755587Ab0EXHIH convert rfc822-to-8bit (ORCPT ); Mon, 24 May 2010 03:08:07 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4O77gKh002460 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 24 May 2010 02:07:45 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4O77cFO019896; Mon, 24 May 2010 12:37:39 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Mon, 24 May 2010 12:37:39 +0530 From: "Gupta, Ajay Kumar" To: Amit Kucheria , Kevin Hilman CC: "me@felipebalbi.com" , "felipe.balbi@nokia.com" , "linux-omap@vger.kernel.org" , "tony@atomide.com" Date: Mon, 24 May 2010 12:37:37 +0530 Subject: RE: usb_nop_xceiv_register() missing when OTG built as modules Thread-Topic: usb_nop_xceiv_register() missing when OTG built as modules Thread-Index: Acr6CegIQrevZZXfQsaKVw7XnfB9UQBA3KNA Message-ID: <19F8576C6E063C45BE387C64729E7394044E61643A@dbde02.ent.ti.com> References: <87635d54nn.fsf@deeprootsystems.com> <19F8576C6E063C45BE387C64729E7394044DB7B6BD@dbde02.ent.ti.com> <87eik03scn.fsf@deeprootsystems.com> <20100305090426.GG12757@nokia.com> <871vfy3azr.fsf@deeprootsystems.com> <558f5bffd42210a777154737d6730232@secure211.sgcpanel.com> <87y6i6zatj.fsf@deeprootsystems.com> <20100522235310.GA15859@matterhorn.lan> In-Reply-To: <20100522235310.GA15859@matterhorn.lan> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 24 May 2010 07:08:14 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index e4a5d66..77af4c9 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -374,8 +373,6 @@ static void __init omap_4430sdp_init(void) platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); - /* OMAP4 SDP uses internal transceiver so register nop transceiver */ - usb_nop_xceiv_register(); /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ if (!cpu_is_omap44xx()) usb_musb_init(&musb_board_data); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 81bba19..83d3aa5 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -682,9 +681,6 @@ static void __init omap3_evm_init(void) omap_serial_init(); - /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */ - usb_nop_xceiv_register(); - if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { /* enable EHCI VBUS using GPIO22 */ omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP); diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index e06d65e..58acd0c 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -198,6 +198,13 @@ int __init musb_platform_init(struct musb *musb, void *board_data) omap_cfg_reg(AE5_2430_USB0HS_STP); #endif +#if defined(CONFIG_MACH_OMAP3EVM) || defined(CONFIG_MACH_OMAP_4430SDP) + /* OMAP3EVM used ISP150x and OMAP4 SDP uses internal transceiver + * so register nop transceiver + */ + usb_nop_xceiv_register(); +#endif + /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. @@ -325,6 +332,8 @@ int musb_platform_exit(struct musb *musb) { musb_platform_suspend(musb); - +#if defined(CONFIG_MACH_OMAP3EVM) || defined(CONFIG_MACH_OMAP_4430SDP) + usb_nop_xceiv_unregister(); +#endif return 0; } From patchwork Thu Apr 29 08:48:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Rapoport X-Patchwork-Id: 96066 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3UL3bJT031256 for ; Fri, 30 Apr 2010 21:03:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759545Ab0D3VDO (ORCPT ); Fri, 30 Apr 2010 17:03:14 -0400 Received: from compulab.co.il ([67.18.134.219]:38483 "EHLO compulab.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754155Ab0D3VDB (ORCPT ); Fri, 30 Apr 2010 17:03:01 -0400 Received: from [62.90.235.247] (helo=zimbra-mta.compulab.co.il) by compulab.site5.com with esmtp (Exim 4.69) (envelope-from ) id 1O7PR6-0008J9-Vz; Thu, 29 Apr 2010 03:49:33 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by zimbra-mta.compulab.co.il (Postfix) with ESMTP id 019CB9A0029; Thu, 29 Apr 2010 11:49:32 +0300 (IDT) X-Virus-Scanned: amavisd-new at compulab.co.il Received: from zimbra-mta.compulab.co.il ([127.0.0.1]) by localhost (zimbra-mta.compulab.co.il [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YZdMhRycEAtI; Thu, 29 Apr 2010 11:49:31 +0300 (IDT) Received: from droid.compulab.local (droid.compulab.local [10.1.1.77]) by zimbra-mta.compulab.co.il (Postfix) with ESMTP id AA67E9A0026; Thu, 29 Apr 2010 11:49:31 +0300 (IDT) Received: from droid.compulab.local (localhost [127.0.0.1]) by droid.compulab.local (8.14.0/8.14.0) with ESMTP id o3T8mIeq015320; Thu, 29 Apr 2010 11:48:18 +0300 Received: (from mike@localhost) by droid.compulab.local (8.14.4/8.14.0/Submit) id o3T8mIIE015319; Thu, 29 Apr 2010 11:48:18 +0300 X-Authentication-Warning: droid.compulab.local: mike set sender to mike@compulab.co.il using -f From: Mike Rapoport To: linux-omap@vger.kernel.org Cc: tony@atomide.com, vimal.newwork@gmail.com, s-ghorai@ti.com, Mike Rapoport Subject: [PATCH v2 1/3] omap: gpmc: add gpmc_cs_get_timings Date: Thu, 29 Apr 2010 11:48:10 +0300 Message-Id: X-Mailer: git-send-email 1.6.6.2 In-Reply-To: References: X-ACL-Warn: { X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - compulab.site5.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - compulab.co.il X-Source: X-Source-Args: X-Source-Dir: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 30 Apr 2010 21:03:50 +0000 (UTC) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5bc3ca0..527a0da 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -163,6 +163,36 @@ unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) } #ifdef DEBUG +static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, + const char *name) +#else +static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit) +#endif +{ + u32 l; + int ticks, mask, nr_bits, time; + + nr_bits = end_bit - st_bit + 1; + mask = ((1 << nr_bits) - 1); + + l = gpmc_cs_read_reg(cs, reg); + ticks = (l >> st_bit) & mask; + + if (ticks == 0) + time = 0; + else + time = gpmc_ticks_to_ns(ticks); + +#ifdef DEBUG + printk(KERN_INFO + "GPMC CS%d: %-10s: %3d ticks, %3d ns\n", + cs, name, ticks, time); +#endif + + return time; +} + +#ifdef DEBUG static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int time, const char *name) #else @@ -206,10 +236,14 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ t->field, #field) < 0) \ return -1 +#define GPMC_GET_ONE(reg, st, end, field) \ + t->field = get_gpmc_timing_reg(cs, (reg), (st), (end), #field) #else #define GPMC_SET_ONE(reg, st, end, field) \ if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ return -1 +#define GPMC_GET_ONE(reg, st, end, field) \ + t->field = get_gpmc_timing_reg(cs, (reg), (st), (end)) #endif int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) @@ -227,6 +261,48 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) return div; } +void gpmc_cs_get_timings(int cs, struct gpmc_timings *t) +{ + int div; + u32 l; + + GPMC_GET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); + GPMC_GET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); + GPMC_GET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); + + GPMC_GET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); + GPMC_GET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); + GPMC_GET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); + + GPMC_GET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); + GPMC_GET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); + GPMC_GET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); + GPMC_GET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); + + GPMC_GET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); + GPMC_GET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); + GPMC_GET_ONE(GPMC_CS_CONFIG5, 16, 20, access); + + GPMC_GET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); + + if (cpu_is_omap34xx()) { + GPMC_GET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); + GPMC_GET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); + } + + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { + div = (l & 0x03) + 1; +#ifdef DEBUG + printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", + cs, (div * gpmc_get_fclk_period()) / 1000, div); +#endif + t->sync_clk = (div * gpmc_get_fclk_period()) / 1000; + } else { + t->sync_clk = 0; + } +} + int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) { int div; diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 145838a..5c345f1 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -102,6 +102,7 @@ extern void gpmc_cs_write_reg(int cs, int idx, u32 val); extern u32 gpmc_cs_read_reg(int cs, int idx); extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); +extern void gpmc_cs_get_timings(int cs, struct gpmc_timings *t); extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); extern int gpmc_cs_set_reserved(int cs, int reserved); From patchwork Mon Jul 12 16:30:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 111373 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6C5WbPZ010989 for ; Mon, 12 Jul 2010 05:32:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751940Ab0GLFcc (ORCPT ); Mon, 12 Jul 2010 01:32:32 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:43783 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751782Ab0GLFcc (ORCPT ); Mon, 12 Jul 2010 01:32:32 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6C5WSwb001285 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 12 Jul 2010 00:32:31 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6C5WQsc012085; Mon, 12 Jul 2010 11:02:27 +0530 (IST) From: Tarun Kanti DebBarma To: linux-omap@vger.kernel.org Cc: Tarun Kanti Debbarma Subject: [PATCHv2]omap:dmtimer:no null check for kzalloc Date: Mon, 12 Jul 2010 22:00:05 +0530 Message-Id: <1278952205-2580-1-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.6.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 05:32:37 +0000 (UTC) diff --git a/arch/arm/mach-omap2/dmtimers.c b/arch/arm/mach-omap2/dmtimers.c index 772be63..1540627 100644 --- a/arch/arm/mach-omap2/dmtimers.c +++ b/arch/arm/mach-omap2/dmtimers.c @@ -192,7 +192,7 @@ void __init omap2_dm_timer_setup_clksrc(void) is_initialized = 1; } -void __init omap2_dm_timer_early_init(void) +int __init omap2_dm_timer_early_init(void) { int i = 0; @@ -219,7 +219,7 @@ void __init omap2_dm_timer_early_init(void) break; default: /* Error should never enter here */ - return; + return -EINVAL; } pdata->io_base = ioremap(base, SZ_8K); @@ -248,7 +248,12 @@ void __init omap2_dm_timer_early_init(void) pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), GFP_KERNEL); - + if (!pdata) { + pr_err("%s:" + "No memory for omap_dm_timer_plat_info\n", + __func__); + return -ENOMEM; + } pdata->omap_dm_clk_enable = omap2_dm_timer_enable; pdata->omap_dm_clk_disable = omap2_dm_timer_disable; pdata->omap_dm_set_source_clk = omap2_dm_timer_set_clk; @@ -271,7 +276,7 @@ void __init omap2_dm_timer_early_init(void) omap2_dm_timer_setup_clksrc(); early_platform_driver_register_all("earlytimer"); early_platform_driver_probe("earlytimer", NO_EARLY_TIMERS, 0); - return; + return 0; } int __init omap2_dm_timer_init(void) @@ -346,6 +351,12 @@ int __init omap2_dm_timer_init(void) pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), GFP_KERNEL); + if (!pdata) { + pr_err("%s:" + "No memory for omap_dm_timer_plat_info\n", + __func__); + return -ENOMEM; + } pdata->omap_dm_clk_enable = omap2_dm_timer_enable; pdata->omap_dm_clk_disable = omap2_dm_timer_disable; pdata->omap_dm_set_source_clk = omap2_dm_timer_set_clk; @@ -397,7 +408,12 @@ fail: break; pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), GFP_KERNEL); - + if (!pdata) { + pr_err("%s:" + "No memory for omap_dm_timer_plat_info\n", + __func__); + return -ENOMEM; + } pdata->omap_dm_clk_enable = omap2_dm_timer_enable; pdata->omap_dm_clk_disable = omap2_dm_timer_disable; pdata->omap_dm_set_source_clk = omap2_dm_timer_set_clk; diff --git a/arch/arm/mach-omap2/dmtimers.h b/arch/arm/mach-omap2/dmtimers.h index 2309e4a..afb2d36 100644 --- a/arch/arm/mach-omap2/dmtimers.h +++ b/arch/arm/mach-omap2/dmtimers.h @@ -52,6 +52,6 @@ #define OMAP44XX_GPTIMER11_BASE 0x48088000 #define OMAP44XX_GPTIMER12_BASE 0x4a320000 -void __init omap2_dm_timer_early_init(void); +int __init omap2_dm_timer_early_init(void); #endif From patchwork Thu Jul 29 09:59:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 115037 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6TA56aV005543 for ; Thu, 29 Jul 2010 10:10:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756297Ab0G2KBT (ORCPT ); Thu, 29 Jul 2010 06:01:19 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:38819 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756098Ab0G2KBF (ORCPT ); Thu, 29 Jul 2010 06:01:05 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6TA0wF2013313 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Jul 2010 05:01:00 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6TA0qYq006167; Thu, 29 Jul 2010 15:30:56 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Venkatraman S , Benoit Cousson , Kevin Hilman , Paul Walmsley , Tony Lindgren , Anand Sawant , Santosh Shilimkar , Rajendra Nayak , Basak Partha , Charulatha V Subject: [PATCH 11/11] sDMA: descriptor autoloading feature Date: Thu, 29 Jul 2010 15:29:05 +0530 Message-Id: <1280397545-27323-12-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280397545-27323-1-git-send-email-manjugk@ti.com> References: <1280397545-27323-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 29 Jul 2010 10:10:45 +0000 (UTC) diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index eadc160..1f10f62 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -304,6 +304,11 @@ void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) } EXPORT_SYMBOL(omap_dma_set_global_params); +void omap_clear_dma_sglist_mode(int lch) +{ + return; +} + static int __init omap1_system_dma_init(void) { struct platform_device *pdev; diff --git a/arch/arm/mach-omap1/include/mach/dma.h b/arch/arm/mach-omap1/include/mach/dma.h index 1eb0d31..afe486b 100644 --- a/arch/arm/mach-omap1/include/mach/dma.h +++ b/arch/arm/mach-omap1/include/mach/dma.h @@ -143,4 +143,6 @@ struct omap_dma_lch { long flags; }; +/* Dummy function */ +extern void omap_clear_dma_sglist_mode(int lch); #endif /* __ASM_ARCH_OMAP1_DMA_H */ diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 390c428..c24ed00 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -204,6 +204,77 @@ static void dma_ocpsysconfig_errata(u32 *sys_cf, bool flag) dma_write(*sys_cf, OCP_SYSCONFIG); } +static inline void omap_dma_list_set_ntype(struct omap_dma_sglist_node *node, + int value) +{ + node->num_of_elem |= ((value) << 29); +} + +static void omap_set_dma_sglist_pausebit( + struct omap_dma_list_config_params *lcfg, int nelem, int set) +{ + struct omap_dma_sglist_node *sgn = lcfg->sghead; + + if (nelem > 0 && nelem < lcfg->num_elem) { + lcfg->pausenode = nelem; + sgn += nelem; + + if (set) + sgn->next_desc_add_ptr |= DMA_LIST_DESC_PAUSE; + else + sgn->next_desc_add_ptr &= ~(DMA_LIST_DESC_PAUSE); + } +} + +static int dma_sglist_set_phy_params(struct omap_dma_sglist_node *sghead, + dma_addr_t phyaddr, int nelem) +{ + struct omap_dma_sglist_node *sgcurr, *sgprev; + dma_addr_t elem_paddr = phyaddr; + + for (sgprev = sghead; + sgprev < sghead + nelem; + sgprev++) { + + sgcurr = sgprev + 1; + sgprev->next = sgcurr; + elem_paddr += (int)sizeof(*sgcurr); + sgprev->next_desc_add_ptr = elem_paddr; + + switch (sgcurr->desc_type) { + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE1: + omap_dma_list_set_ntype(sgprev, 1); + break; + + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2a: + /* intentional no break */ + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2b: + omap_dma_list_set_ntype(sgprev, 2); + break; + + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3a: + /* intentional no break */ + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3b: + omap_dma_list_set_ntype(sgprev, 3); + break; + + default: + return -EINVAL; + + } + if (sgcurr->flags & OMAP_DMA_LIST_SRC_VALID) + sgprev->num_of_elem |= DMA_LIST_DESC_SRC_VALID; + if (sgcurr->flags & OMAP_DMA_LIST_DST_VALID) + sgprev->num_of_elem |= DMA_LIST_DESC_DST_VALID; + if (sgcurr->flags & OMAP_DMA_LIST_NOTIFY_BLOCK_END) + sgprev->num_of_elem |= DMA_LIST_DESC_BLK_END; + } + sgprev--; + sgprev->next_desc_add_ptr = OMAP_DMA_INVALID_DESCRIPTOR_POINTER; + return 0; +} + + void omap_dma_global_context_save(void) { omap_dma_global_context.dma_irqenable_l0 = @@ -861,6 +932,189 @@ void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) } EXPORT_SYMBOL(omap_set_dma_write_mode); +int omap_set_dma_sglist_mode(int lch, struct omap_dma_sglist_node *sgparams, + dma_addr_t padd, int nelem, struct omap_dma_channel_params *chparams) +{ + struct omap_dma_list_config_params *lcfg; + int l = DMA_LIST_CDP_LISTMODE; /* Enable Linked list mode in CDP */ + + if ((dma_caps0_status & DMA_CAPS_SGLIST_SUPPORT) == 0) { + printk(KERN_ERR "omap DMA: sglist feature not supported\n"); + return -EPERM; + } + if (dma_chan[lch].flags & OMAP_DMA_ACTIVE) { + printk(KERN_ERR "omap DMA: configuring active DMA channel\n"); + return -EPERM; + } + + if (padd == 0) { + printk(KERN_ERR "omap DMA: sglist invalid dma_addr\n"); + return -EINVAL; + } + lcfg = &dma_chan[lch].list_config; + + lcfg->sghead = sgparams; + lcfg->num_elem = nelem; + lcfg->sgheadphy = padd; + lcfg->pausenode = -1; + + + if (NULL == chparams) + l |= DMA_LIST_CDP_FASTMODE; + else + omap_set_dma_params(lch, chparams); + + dma_write(l, CDP(lch)); + dma_write(0, CCDN(lch)); /* Reset List index numbering */ + /* Initialize frame and element counters to invalid values */ + dma_write(OMAP_DMA_INVALID_FRAME_COUNT, CCFN(lch)); + dma_write(OMAP_DMA_INVALID_ELEM_COUNT, CCEN(lch)); + + return dma_sglist_set_phy_params(sgparams, lcfg->sgheadphy, nelem); + +} +EXPORT_SYMBOL(omap_set_dma_sglist_mode); + +void omap_clear_dma_sglist_mode(int lch) +{ + /* Clear entire CDP which is related to sglist handling */ + dma_write(0, CDP(lch)); + dma_write(0, CCDN(lch)); + /** + * Put back the original enabled irqs, which + * could have been overwritten by type 1 or type 2 + * descriptors + */ + dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); + return; +} +EXPORT_SYMBOL(omap_clear_dma_sglist_mode); + +int omap_start_dma_sglist_transfers(int lch, int pauseafter) +{ + struct omap_dma_list_config_params *lcfg; + struct omap_dma_sglist_node *sgn; + unsigned int l, type_id; + + lcfg = &dma_chan[lch].list_config; + sgn = lcfg->sghead; + + lcfg->pausenode = 0; + omap_set_dma_sglist_pausebit(lcfg, pauseafter, 1); + + /* Program the head descriptor's properties into CDP */ + switch (lcfg->sghead->desc_type) { + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE1: + type_id = DMA_LIST_CDP_TYPE1; + break; + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2a: + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2b: + type_id = DMA_LIST_CDP_TYPE2; + break; + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3a: + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3b: + type_id = DMA_LIST_CDP_TYPE3; + break; + default: + return -EINVAL; + } + + l = dma_read(CDP(lch)); + l |= type_id; + if (lcfg->sghead->flags & OMAP_DMA_LIST_SRC_VALID) + l |= DMA_LIST_CDP_SRC_VALID; + if (lcfg->sghead->flags & OMAP_DMA_LIST_DST_VALID) + l |= DMA_LIST_CDP_DST_VALID; + + dma_write(l, CDP(lch)); + dma_write((lcfg->sgheadphy), CNDP(lch)); + /** + * Barrier needed as writes to the + * descriptor memory needs to be flushed + * before it's used by DMA controller + */ + wmb(); + omap_start_dma(lch); + + return 0; +} +EXPORT_SYMBOL(omap_start_dma_sglist_transfers); + +int omap_resume_dma_sglist_transfers(int lch, int pauseafter) +{ + struct omap_dma_list_config_params *lcfg; + struct omap_dma_sglist_node *sgn; + int l, get_sysconfig; + + lcfg = &dma_chan[lch].list_config; + sgn = lcfg->sghead; + + /* Maintain the pause state in descriptor */ + omap_set_dma_sglist_pausebit(lcfg, lcfg->pausenode, 0); + omap_set_dma_sglist_pausebit(lcfg, pauseafter, 1); + + /** + * Barrier needed as writes to the + * descriptor memory needs to be flushed + * before it's used by DMA controller + */ + wmb(); + + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, false) + + /* Clear pause bit in CDP */ + l = dma_read(CDP(lch)); + l &= ~(DMA_LIST_CDP_PAUSEMODE); + dma_write(l, CDP(lch)); + + omap_start_dma(lch); + + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, true); + + return 0; +} +EXPORT_SYMBOL(omap_resume_dma_sglist_transfers); + +void omap_release_dma_sglist(int lch) +{ + omap_clear_dma_sglist_mode(lch); + omap_free_dma(lch); + + return; +} +EXPORT_SYMBOL(omap_release_dma_sglist); + +int omap_get_completed_sglist_nodes(int lch) +{ + int list_count; + + list_count = dma_read(CCDN(lch)); + return list_count & 0xffff; /* only 16 LSB bits are valid */ +} +EXPORT_SYMBOL(omap_get_completed_sglist_nodes); + +int omap_dma_sglist_is_paused(int lch) +{ + int list_state; + list_state = dma_read(CDP(lch)); + return (list_state & DMA_LIST_CDP_PAUSEMODE) ? 1 : 0; +} +EXPORT_SYMBOL(omap_dma_sglist_is_paused); + +void omap_dma_set_sglist_fastmode(int lch, int fastmode) +{ + int l = dma_read(CDP(lch)); + + if (fastmode) + l |= DMA_LIST_CDP_FASTMODE; + else + l &= ~(DMA_LIST_CDP_FASTMODE); + dma_write(l, CDP(lch)); +} +EXPORT_SYMBOL(omap_dma_set_sglist_fastmode); + static int omap2_dma_handle_ch(int ch) { u32 status = dma_read(CSR(ch)); diff --git a/arch/arm/mach-omap2/include/mach/dma.h b/arch/arm/mach-omap2/include/mach/dma.h index f3e21d5..e039ea4 100644 --- a/arch/arm/mach-omap2/include/mach/dma.h +++ b/arch/arm/mach-omap2/include/mach/dma.h @@ -143,6 +143,112 @@ #define OMAP_DMA4_GSCR 0 #define OMAP1_DMA_REVISION 0 +/* CDP Register bitmaps */ +#define DMA_LIST_CDP_DST_VALID (BIT(0)) +#define DMA_LIST_CDP_SRC_VALID (BIT(2)) +#define DMA_LIST_CDP_TYPE1 (BIT(4)) +#define DMA_LIST_CDP_TYPE2 (BIT(5)) +#define DMA_LIST_CDP_TYPE3 (BIT(4) | BIT(5)) +#define DMA_LIST_CDP_PAUSEMODE (BIT(7)) +#define DMA_LIST_CDP_LISTMODE (BIT(8)) +#define DMA_LIST_CDP_FASTMODE (BIT(10)) +/* CAPS register bitmaps */ +#define DMA_CAPS_SGLIST_SUPPORT (BIT(20)) + +#define DMA_LIST_DESC_PAUSE (BIT(0)) +#define DMA_LIST_DESC_SRC_VALID (BIT(24)) +#define DMA_LIST_DESC_DST_VALID (BIT(26)) +#define DMA_LIST_DESC_BLK_END (BIT(28)) + +#define OMAP_DMA_INVALID_FRAME_COUNT (0xffff) +#define OMAP_DMA_INVALID_ELEM_COUNT (0xffffff) +#define OMAP_DMA_INVALID_DESCRIPTOR_POINTER (0xfffffffc) + +struct omap_dma_list_config_params { + unsigned int num_elem; + struct omap_dma_sglist_node *sghead; + dma_addr_t sgheadphy; + unsigned int pausenode; +}; + +struct omap_dma_sglist_type1_params { + u32 src_addr; + u32 dst_addr; + u16 cfn_fn; + u16 cicr; + u16 dst_elem_idx; + u16 src_elem_idx; + u32 dst_frame_idx_or_pkt_size; + u32 src_frame_idx_or_pkt_size; + u32 color; + u32 csdp; + u32 clnk_ctrl; + u32 ccr; +}; + +struct omap_dma_sglist_type2a_params { + u32 src_addr; + u32 dst_addr; + u16 cfn_fn; + u16 cicr; + u16 dst_elem_idx; + u16 src_elem_idx; + u32 dst_frame_idx_or_pkt_size; + u32 src_frame_idx_or_pkt_size; +}; + +struct omap_dma_sglist_type2b_params { + u32 src_or_dest_addr; + u16 cfn_fn; + u16 cicr; + u16 dst_elem_idx; + u16 src_elem_idx; + u32 dst_frame_idx_or_pkt_size; + u32 src_frame_idx_or_pkt_size; +}; + +struct omap_dma_sglist_type3a_params { + u32 src_addr; + u32 dst_addr; +}; + +struct omap_dma_sglist_type3b_params { + u32 src_or_dest_addr; +}; + +enum omap_dma_sglist_descriptor_select { + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE1, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2a, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2b, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3a, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3b, +}; + +union omap_dma_sglist_node_type{ + struct omap_dma_sglist_type1_params t1; + struct omap_dma_sglist_type2a_params t2a; + struct omap_dma_sglist_type2b_params t2b; + struct omap_dma_sglist_type3a_params t3a; + struct omap_dma_sglist_type3b_params t3b; +}; + +struct omap_dma_sglist_node { + + /* Common elements for all descriptors */ + dma_addr_t next_desc_add_ptr; + u32 num_of_elem; + /* Type specific elements */ + union omap_dma_sglist_node_type sg_node; + /* Control fields */ + unsigned short flags; + /* Fields that can be set in flags variable */ + #define OMAP_DMA_LIST_SRC_VALID BIT(0) + #define OMAP_DMA_LIST_DST_VALID BIT(1) + #define OMAP_DMA_LIST_NOTIFY_BLOCK_END BIT(2) + enum omap_dma_sglist_descriptor_select desc_type; + struct omap_dma_sglist_node *next; +}; + struct omap_dma_lch { int next_lch; int dev_id; @@ -158,8 +264,96 @@ struct omap_dma_lch { int state; int chain_id; int status; + struct omap_dma_list_config_params list_config; }; +/** + * omap_set_dma_sglist_mode() Switch channel to scatter gather mode + * @lch: Logical channel to switch to sglist mode + * @sghead: Contains the descriptor elements to be executed + * Should be allocated using dma_alloc_coherent + * @padd: The dma address of sghead, as returned by dma_alloc_coherent + * @nelem: Number of elements in sghead + * @chparams: DMA channel transfer parameters. Can be NULL + */ +extern int omap_set_dma_sglist_mode(int lch, + struct omap_dma_sglist_node *sghead, dma_addr_t padd, + int nelem, struct omap_dma_channel_params *chparams); + +/** + * omap_clear_dma_sglist_mode() Switch from scatter gather mode + * to normal mode + * @lch: The logical channel to be switched to normal mode + * + * Switches the requested logical channel to normal mode + * from scatter gather mode + */ +extern void omap_clear_dma_sglist_mode(int lch); + +/** + * omap_start_dma_sglist_transfers() Starts the sglist transfer + * @lch: logical channel on which sglist transfer to be started + * @pauseafter: index of the element on which to pause the transfer + * set to -1 if no pause is needed till end of transfer + * + * Start the dma transfer in list mode + * The index (in pauseafter) is absolute (from the head of the list) + * User should have previously called omap_set_dma_sglist_mode() + */ +extern int omap_start_dma_sglist_transfers(int lch, int pauseafter); + +/** + * omap_resume_dma_sglist_transfers() Resumes a previously paused + * sglist transfer + * @lch: The logical channel to be resumed + * @pauseafter: The index of sglist to be paused again + * set to -1 if no pause is needed till end of transfer + * + * Resume the previously paused transfer + * The index (in pauseafter) is absolute (from the head of the list) + */ +extern int omap_resume_dma_sglist_transfers(int lch, int pauseafter); + +/** + * omap_release_dma_sglist() Releases a previously requested + * DMA channel which is in sglist mode + * @lch: The logical channel to be released + */ +extern void omap_release_dma_sglist(int lch); + +/** + * omap_get_completed_sglist_nodes() Returns a list of completed + * sglist nodes + * @lch: The logical on which the query is to be made + * + * Returns the number of completed elements in the linked list + * The value is transient if the API is invoked for an ongoing transfer + */ +int omap_get_completed_sglist_nodes(int lch); + +/** + * omap_dma_sglist_is_paused() Query is the logical channel in + * sglist mode is paused or note + * @lch: The logical on which the query is to be made + * + * Returns non zero if the linked list is currently in pause state + */ +int omap_dma_sglist_is_paused(int lch); + +/** + * omap_dma_set_sglist_fastmode() Set the sglist transfer to fastmode + * @lch: The logical channel which is to be changed to fastmode + * @fastmode: Set or clear the fastmode status + * 1 = set fastmode + * 0 = clear fastmode + * + * In fastmode, DMA register settings are updated from the first element + * of the linked list, before initiating the tranfer. + * In non-fastmode, the first element is used only after completing the + * transfer as already configured in the registers + */ +void omap_dma_set_sglist_fastmode(int lch, int fastmode); + /* Chaining APIs */ extern int omap_request_dma_chain(int dev_id, const char *dev_name, void (*callback) (int lch, u16 ch_status, diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 643f538..daac49c 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -543,6 +543,7 @@ void omap_free_dma(int lch) /* Make sure the DMA transfer is stopped. */ dma_write(0, CCR(lch)); omap_clear_dma(lch); + omap_clear_dma_sglist_mode(lch); } spin_lock_irqsave(&dma_chan_lock, flags); From patchwork Fri May 7 10:49:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 97718 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o47AmxNu027627 for ; Fri, 7 May 2010 10:50:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756555Ab0EGKtn (ORCPT ); Fri, 7 May 2010 06:49:43 -0400 Received: from mail.gmx.net ([213.165.64.20]:45422 "HELO mail.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1756554Ab0EGKtm (ORCPT ); Fri, 7 May 2010 06:49:42 -0400 Received: (qmail invoked by alias); 07 May 2010 10:49:35 -0000 Received: from p57BD1BFA.dip0.t-ipconnect.de (EHLO axis700.grange) [87.189.27.250] by mail.gmx.net (mp002) with SMTP; 07 May 2010 12:49:35 +0200 X-Authenticated: #20450766 X-Provags-ID: V01U2FsdGVkX19e9qIvakhegvQLDZqP42cdB83E+fx1jeMYbHAg8c fipipb4zeMbYjR Received: from lyakh (helo=localhost) by axis700.grange with local-esmtp (Exim 4.63) (envelope-from ) id 1OAL7l-0001oI-Hb; Fri, 07 May 2010 12:49:41 +0200 Date: Fri, 7 May 2010 12:49:41 +0200 (CEST) From: Guennadi Liakhovetski To: "linux-sh@vger.kernel.org" cc: Magnus Damm , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, Tomi Valkeinen Subject: [PATCH 1.5/4] sh: add a YUV422 output data format, that is also supported by LCDC In-Reply-To: Message-ID: References: MIME-Version: 1.0 X-Y-GMX-Trusted: 0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 07 May 2010 10:50:15 +0000 (UTC) diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h index 2cc893f..5eaea78 100644 --- a/include/video/sh_mobile_lcdc.h +++ b/include/video/sh_mobile_lcdc.h @@ -3,24 +3,27 @@ #include -enum { RGB8, /* 24bpp, 8:8:8 */ - RGB9, /* 18bpp, 9:9 */ - RGB12A, /* 24bpp, 12:12 */ - RGB12B, /* 12bpp */ - RGB16, /* 16bpp */ - RGB18, /* 18bpp */ - RGB24, /* 24bpp */ - SYS8A, /* 24bpp, 8:8:8 */ - SYS8B, /* 18bpp, 8:8:2 */ - SYS8C, /* 18bpp, 2:8:8 */ - SYS8D, /* 16bpp, 8:8 */ - SYS9, /* 18bpp, 9:9 */ - SYS12, /* 24bpp, 12:12 */ - SYS16A, /* 16bpp */ - SYS16B, /* 18bpp, 16:2 */ - SYS16C, /* 18bpp, 2:16 */ - SYS18, /* 18bpp */ - SYS24 };/* 24bpp */ +enum { + RGB8, /* 24bpp, 8:8:8 */ + RGB9, /* 18bpp, 9:9 */ + RGB12A, /* 24bpp, 12:12 */ + RGB12B, /* 12bpp */ + RGB16, /* 16bpp */ + RGB18, /* 18bpp */ + RGB24, /* 24bpp */ + YUV422, /* 16bpp */ + SYS8A, /* 24bpp, 8:8:8 */ + SYS8B, /* 18bpp, 8:8:2 */ + SYS8C, /* 18bpp, 2:8:8 */ + SYS8D, /* 16bpp, 8:8 */ + SYS9, /* 18bpp, 9:9 */ + SYS12, /* 24bpp, 12:12 */ + SYS16A, /* 16bpp */ + SYS16B, /* 18bpp, 16:2 */ + SYS16C, /* 18bpp, 2:16 */ + SYS18, /* 18bpp */ + SYS24, /* 24bpp */ +}; enum { LCDC_CHAN_DISABLED = 0, LCDC_CHAN_MAINLCD, From patchwork Thu Jul 29 09:59:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 115036 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6TA56aT005543 for ; Thu, 29 Jul 2010 10:09:07 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756570Ab0G2KBR (ORCPT ); Thu, 29 Jul 2010 06:01:17 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:38820 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756512Ab0G2KBF (ORCPT ); Thu, 29 Jul 2010 06:01:05 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6TA0wHl013312 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Jul 2010 05:01:00 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6TA0qYp006167; Thu, 29 Jul 2010 15:30:55 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Benoit Cousson , Kevin Hilman , Paul Walmsley , Tony Lindgren , Anand Sawant , Santosh Shilimkar , Rajendra Nayak , Basak Partha , Charulatha V Subject: [PATCH 10/11] OMAP: DMA: Use DMA device attributes Date: Thu, 29 Jul 2010 15:29:04 +0530 Message-Id: <1280397545-27323-11-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280397545-27323-1-git-send-email-manjugk@ti.com> References: <1280397545-27323-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 29 Jul 2010 10:09:55 +0000 (UTC) diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 00ef40f..eadc160 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -140,13 +140,177 @@ static struct resource res[] __initdata = { }; static void __iomem *dma_base; +static struct omap_dma_lch *dma_chan; +struct omap_dma_dev_attr *d; + +u32 enable_1510_mode; + +#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) +static inline int omap1_get_gdma_dev(int req) +{ + u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; + int shift = ((req - 1) % 5) * 6; + + return ((omap_readl(reg) >> shift) & 0x3f) + 1; +} + +static inline void omap1_set_gdma_dev(int req, int dev) +{ + u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; + int shift = ((req - 1) % 5) * 6; + u32 l; + + l = omap_readl(reg); + l &= ~(0x3f << shift); + l |= (dev - 1) << shift; + omap_writel(l, reg); +} + +static void omap1_clear_lch_regs(int lch) +{ + int i; + void __iomem *lch_base = dma_base + OMAP1_DMA_CH_BASE(lch); + + for (i = 0; i < 0x2c; i += 2) + __raw_writew(0, lch_base + i); +} + +static inline void omap1_enable_channel_irq(int lch) +{ + u32 status; + + status = dma_read(CSR(lch)); + dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); +} + +static void omap1_disable_channel_irq(int lch) +{ + return; +} + +static inline void omap1_enable_lnk(int lch) +{ + u32 l; + + l = dma_read(CLNK_CTRL(lch)); + + l &= ~(1 << 14); + + /* Set the ENABLE_LNK bits */ + if (dma_chan[lch].next_lch != -1) + l = dma_chan[lch].next_lch | (1 << 15); + + dma_write(l, CLNK_CTRL(lch)); +} + +static inline void omap1_disable_lnk(int lch) +{ + u32 l; + + l = dma_read(CLNK_CTRL(lch)); + + /* Disable interrupts */ + dma_write(0, CICR(lch)); + /* Set the STOP_LNK bit */ + l |= 1 << 14; + + dma_write(l, CLNK_CTRL(lch)); + dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; +} + +static int omap1_dma_handle_ch(int ch) +{ + u32 csr; + + if (enable_1510_mode && ch >= 6) { + csr = dma_chan[ch].saved_csr; + dma_chan[ch].saved_csr = 0; + } else + csr = dma_read(CSR(ch)); + if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { + dma_chan[ch + 6].saved_csr = csr >> 7; + csr &= 0x7f; + } + if ((csr & 0x3f) == 0) + return 0; + if (unlikely(dma_chan[ch].dev_id == -1)) { + printk(KERN_WARNING "Spurious interrupt from DMA channel " + "%d (CSR %04x)\n", ch, csr); + return 0; + } + if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) + printk(KERN_WARNING "DMA timeout with device %d\n", + dma_chan[ch].dev_id); + if (unlikely(csr & OMAP_DMA_DROP_IRQ)) + printk(KERN_WARNING "DMA synchronization event drop occurred " + "with device %d\n", dma_chan[ch].dev_id); + if (likely(csr & OMAP_DMA_BLOCK_IRQ)) + dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; + if (likely(dma_chan[ch].callback != NULL)) + dma_chan[ch].callback(ch, csr, dma_chan[ch].data); + + return 1; +} + +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + int ch = ((int) dev_id) - 1; + int handled = 0; + + for (;;) { + int handled_now = 0; + + handled_now += omap1_dma_handle_ch(ch); + if (enable_1510_mode && dma_chan[ch + 6].saved_csr) + handled_now += omap1_dma_handle_ch(ch + 6); + if (!handled_now) + break; + handled += handled_now; + } + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) +{ + if (!(d->dma_dev_attr & ENABLE_1510_MODE)) { + u32 l; + + l = dma_read(LCH_CTRL(lch)); + l &= ~0x7; + l |= mode; + dma_write(l, LCH_CTRL(lch)); + } +} +EXPORT_SYMBOL(omap_set_dma_channel_mode); + +void omap_set_dma_src_index(int lch, int eidx, int fidx) +{ + dma_write(eidx, CSEI(lch)); + dma_write(fidx, CSFI(lch)); +} +EXPORT_SYMBOL(omap_set_dma_src_index); + +void omap_set_dma_dest_index(int lch, int eidx, int fidx) +{ + dma_write(eidx, CDEI(lch)); + dma_write(fidx, CDFI(lch)); +} +EXPORT_SYMBOL(omap_set_dma_dest_index); + +void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) +{ + return; +} +EXPORT_SYMBOL(omap_dma_set_global_params); static int __init omap1_system_dma_init(void) { struct platform_device *pdev; struct omap_system_dma_plat_info *pdata; - struct omap_dma_dev_attr *d; - int ret; + int dma_irq, ret, ch; + char irq_name[14]; + int irq_rel; pdev = platform_device_alloc("system_dma", 0); if (!pdev) { @@ -155,11 +319,19 @@ static int __init omap1_system_dma_init(void) return -ENOMEM; } + dma_irq = platform_get_irq_byname(pdev, irq_name); + if (dma_irq < 0) { + dev_err(&pdev->dev, "%s:unable to get irq\n", + __func__); + ret = dma_irq; + goto exit_pdev; + } + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); if (ret) { pr_err("%s: Unable to add resources for %s%d\n", __func__, pdev->name, pdev->id); - goto exit_device_put; + goto exit_pdev; } pdata = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); @@ -167,7 +339,7 @@ static int __init omap1_system_dma_init(void) dev_err(&pdev->dev, "%s: Unable to allocate pdata for %s\n", __func__, pdev->name); ret = -ENOMEM; - goto exit_device_put; + goto exit_pdev; } /* Errata handling for all omap1 plus processors */ @@ -183,6 +355,7 @@ static int __init omap1_system_dma_init(void) if (cpu_is_omap15xx()) d->dma_dev_attr = ENABLE_1510_MODE; + enable_1510_mode = d->dma_dev_attr & ENABLE_1510_MODE; d->dma_dev_attr |= SRC_PORT; d->dma_dev_attr |= DST_PORT; @@ -194,6 +367,19 @@ static int __init omap1_system_dma_init(void) d->dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; + pdata->enable_channel_irq = omap1_enable_channel_irq; + pdata->disable_channel_irq = omap1_disable_channel_irq; + pdata->enable_lnk = omap1_enable_lnk; + pdata->disable_lnk = omap1_disable_lnk; + pdata->clear_lch_regs = omap1_clear_lch_regs; + if (cpu_is_omap16xx()) { + pdata->get_gdma_dev = omap1_get_gdma_dev; + pdata->set_gdma_dev = omap1_set_gdma_dev; + } + pdata->enable_irq_lch = NULL; + pdata->disable_irq_lch = NULL; + pdata->set_dma_chain_ch = NULL; + if (cpu_is_omap15xx()) d->dma_chan_count = 9; else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { @@ -203,38 +389,53 @@ static int __init omap1_system_dma_init(void) d->dma_chan_count = 9; } + for (ch = 0; ch < d->dma_chan_count; ch++) { + if (ch >= 6 && enable_1510_mode) + continue; + ret = request_irq(dma_irq, irq_handler, 0, "DMA", + (void *) (ch + 1)); + if (ret != 0) + goto exit_pdata; + } + pdata->omap_dma_base = (void __iomem *)res[0].start; dma_base = pdata->omap_dma_base; - d->dma_chan = kzalloc(sizeof(struct omap_dma_lch) * (d->dma_lch_count), GFP_KERNEL); - if (!d->dma_chan) { dev_err(&pdev->dev, "%s: Memory allcation failed" "for dma_chan!!!\n", __func__); - goto exit_release_pdata; + goto exit_pdata; } + dma_chan = d->dma_chan; ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); if (ret) { dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", __func__, pdev->name, pdev->id); - goto exit_release_dma_chan; + goto exit_pdata; } ret = platform_device_add(pdev); if (ret) { dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", __func__, pdev->name, pdev->id); - goto exit_release_dma_chan; + goto exit_dma_chan; } -exit_release_dma_chan: +exit_dma_chan: kfree(d->dma_chan); -exit_release_pdata: +exit_pdata: + printk(KERN_ERR "unable to request IRQ %d" + "for DMA (error %d)\n", dma_irq, ret); + if (enable_1510_mode) + ch = 6; + for (irq_rel = 0; irq_rel < ch; irq_rel++) { + dma_irq = platform_get_irq(pdev, irq_rel); + free_irq(dma_irq, (void *)(irq_rel + 1)); + } kfree(pdata); -exit_device_put: +exit_pdev: platform_device_put(pdev); - return ret; } arch_initcall(omap1_system_dma_init); diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 72abfec..390c428 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -50,9 +50,70 @@ __raw_writel((val), dma_base + OMAP_DMA4_##reg); \ }) +static struct omap_dma_global_context_registers { + u32 dma_irqenable_l0; + u32 dma_ocp_sysconfig; + u32 dma_gcr; +} omap_dma_global_context; + +struct dma_link_info { + int *linked_dmach_q; + int no_of_lchs_linked; + + int q_count; + int q_tail; + int q_head; + + int chain_state; + int chain_mode; + +}; + +static struct dma_link_info *dma_linked_lch; +static struct omap_dma_lch *dma_chan; + +static int dma_chan_count; + +enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, + DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED +}; + +enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; + +/* Chain handling macros */ +#define OMAP_DMA_CHAIN_QINIT(chain_id) \ + do { \ + dma_linked_lch[chain_id].q_head = \ + dma_linked_lch[chain_id].q_tail = \ + dma_linked_lch[chain_id].q_count = 0; \ + } while (0) +#define OMAP_DMA_CHAIN_QFULL(chain_id) \ + (dma_linked_lch[chain_id].no_of_lchs_linked == \ + dma_linked_lch[chain_id].q_count) +#define OMAP_DMA_CHAIN_QLAST(chain_id) \ + do { \ + ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ + dma_linked_lch[chain_id].q_count) \ + } while (0) +#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ + (0 == dma_linked_lch[chain_id].q_count) +#define __OMAP_DMA_CHAIN_INCQ(end) \ + ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) +#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ + do { \ + __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ + dma_linked_lch[chain_id].q_count--; \ + } while (0) + +#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ + do { \ + __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ + dma_linked_lch[chain_id].q_count++; \ + } while (0) + static struct omap_dma_dev_attr *d; static void __iomem *dma_base; -static struct omap_system_dma_plat_info *omap2_pdata; +static struct omap_system_dma_plat_info *p; static int dma_caps0_status; static struct omap_device_pm_latency omap2_dma_latency[] = { @@ -63,6 +124,874 @@ static struct omap_device_pm_latency omap2_dma_latency[] = { }, }; +static inline void omap2_enable_irq_lch(int lch) +{ + u32 val; + + val = dma_read(IRQENABLE_L0); + val |= 1 << lch; + dma_write(val, IRQENABLE_L0); +} + +static inline void omap2_disable_irq_lch(int lch) +{ + u32 val; + + val = dma_read(IRQENABLE_L0); + val &= ~(1 << lch); + dma_write(val, IRQENABLE_L0); +} + +static inline void omap2_enable_channel_irq(int lch) +{ + /* Clear CSR */ + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); + + dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); +} + +static void omap2_disable_channel_irq(int lch) +{ + dma_write(0, CICR(lch)); +} + +static inline void omap2_enable_lnk(int lch) +{ + u32 l; + + l = dma_read(CLNK_CTRL(lch)); + + /* Set the ENABLE_LNK bits */ + if (dma_chan[lch].next_lch != -1) + l = dma_chan[lch].next_lch | (1 << 15); + + if (dma_chan[lch].next_linked_ch != -1) + l = dma_chan[lch].next_linked_ch | (1 << 15); + + dma_write(l, CLNK_CTRL(lch)); +} + +static inline void omap2_disable_lnk(int lch) +{ + u32 l; + + l = dma_read(CLNK_CTRL(lch)); + + omap2_disable_channel_irq(lch); + /* Clear the ENABLE_LNK bit */ + l &= ~(1 << 15); + + dma_write(l, CLNK_CTRL(lch)); + dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; +} + +static void dma_ocpsysconfig_errata(u32 *sys_cf, bool flag) +{ + u32 l; + + /* + * DMA Errata: + * Special programming model needed to disable DMA before end of block + */ + if (!flag) { + *sys_cf = dma_read(OCP_SYSCONFIG); + l = *sys_cf; + /* Middle mode reg set no Standby */ + l &= ~((1 << 12)|(1 << 13)); + dma_write(l, OCP_SYSCONFIG); + } else + /* put back old value */ + dma_write(*sys_cf, OCP_SYSCONFIG); +} + +void omap_dma_global_context_save(void) +{ + omap_dma_global_context.dma_irqenable_l0 = + dma_read(IRQENABLE_L0); + omap_dma_global_context.dma_ocp_sysconfig = + dma_read(OCP_SYSCONFIG); + omap_dma_global_context.dma_gcr = dma_read(GCR); +} + +void omap_dma_global_context_restore(void) +{ + int ch; + + dma_write(omap_dma_global_context.dma_gcr, GCR); + dma_write(omap_dma_global_context.dma_ocp_sysconfig, + OCP_SYSCONFIG); + dma_write(omap_dma_global_context.dma_irqenable_l0, + IRQENABLE_L0); + + /* + * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared + * after secure sram context save and restore. Hence we need to + * manually clear those IRQs to avoid spurious interrupts. This + * affects only secure devices. + */ + if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + dma_write(0x3 , IRQSTATUS_L0); + + for (ch = 0; ch < dma_chan_count; ch++) + if (dma_chan[ch].dev_id != -1) + omap_clear_dma(ch); +} + +/* Create chain of DMA channesls */ +static void create_dma_lch_chain(int lch_head, int lch_queue) +{ + u32 l; + + /* Check if this is the first link in chain */ + if (dma_chan[lch_head].next_linked_ch == -1) { + dma_chan[lch_head].next_linked_ch = lch_queue; + dma_chan[lch_head].prev_linked_ch = lch_queue; + dma_chan[lch_queue].next_linked_ch = lch_head; + dma_chan[lch_queue].prev_linked_ch = lch_head; + } + + /* a link exists, link the new channel in circular chain */ + else { + dma_chan[lch_queue].next_linked_ch = + dma_chan[lch_head].next_linked_ch; + dma_chan[lch_queue].prev_linked_ch = lch_head; + dma_chan[lch_head].next_linked_ch = lch_queue; + dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch = + lch_queue; + } + + l = dma_read(CLNK_CTRL(lch_head)); + l &= ~(0x1f); + l |= lch_queue; + dma_write(l, CLNK_CTRL(lch_head)); + + l = dma_read(CLNK_CTRL(lch_queue)); + l &= ~(0x1f); + l |= (dma_chan[lch_queue].next_linked_ch); + dma_write(l, CLNK_CTRL(lch_queue)); +} + +static void set_dma_chain_ch(int free_ch) +{ + dma_chan[free_ch].chain_id = -1; + dma_chan[free_ch].next_linked_ch = -1; +} + +/** + * @brief omap_request_dma_chain : Request a chain of DMA channels + * + * @param dev_id - Device id using the dma channel + * @param dev_name - Device name + * @param callback - Call back function + * @chain_id - + * @no_of_chans - Number of channels requested + * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN + * OMAP_DMA_DYNAMIC_CHAIN + * @params - Channel parameters + * + * @return - Success : 0 + * Failure : -EINVAL/-ENOMEM + */ +int omap_request_dma_chain(int dev_id, const char *dev_name, + void (*callback) (int lch, u16 ch_status, + void *data), + int *chain_id, int no_of_chans, int chain_mode, + struct omap_dma_channel_params params) +{ + int *channels; + int i, err; + + /* Is the chain mode valid ? */ + if (chain_mode != OMAP_DMA_STATIC_CHAIN + && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) { + printk(KERN_ERR "Invalid chain mode requested\n"); + return -EINVAL; + } + + if (unlikely((no_of_chans < 1 + || no_of_chans > dma_chan_count))) { + printk(KERN_ERR "Invalid Number of channels requested\n"); + return -EINVAL; + } + + /* + * Allocate a queue to maintain the status of the channels + * in the chain + */ + channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); + if (channels == NULL) { + printk(KERN_ERR "omap_dma: No memory for channel queue\n"); + return -ENOMEM; + } + + /* request and reserve DMA channels for the chain */ + for (i = 0; i < no_of_chans; i++) { + err = omap_request_dma(dev_id, dev_name, + callback, NULL, &channels[i]); + if (err < 0) { + int j; + for (j = 0; j < i; j++) + omap_free_dma(channels[j]); + kfree(channels); + printk(KERN_ERR "omap_dma: Request failed %d\n", err); + return err; + } + dma_chan[channels[i]].prev_linked_ch = -1; + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; + + /* + * Allowing client drivers to set common parameters now, + * so that later only relevant (src_start, dest_start + * and element count) can be set + */ + omap_set_dma_params(channels[i], ¶ms); + } + + *chain_id = channels[0]; + dma_linked_lch[*chain_id].linked_dmach_q = channels; + dma_linked_lch[*chain_id].chain_mode = chain_mode; + dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED; + dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans; + + for (i = 0; i < no_of_chans; i++) + dma_chan[channels[i]].chain_id = *chain_id; + + /* Reset the Queue pointers */ + OMAP_DMA_CHAIN_QINIT(*chain_id); + + /* Set up the chain */ + if (no_of_chans == 1) + create_dma_lch_chain(channels[0], channels[0]); + else { + for (i = 0; i < (no_of_chans - 1); i++) + create_dma_lch_chain(channels[i], channels[i + 1]); + } + + return 0; +} +EXPORT_SYMBOL(omap_request_dma_chain); + +/** + * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the + * params after setting it. Dont do this while dma is running!! + * + * @param chain_id - Chained logical channel id. + * @param params + * + * @return - Success : 0 + * Failure : -EINVAL + */ +int omap_modify_dma_chain_params(int chain_id, + struct omap_dma_channel_params params) +{ + int *channels; + u32 i; + + /* Check for input params */ + if (unlikely((chain_id < 0 + || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + channels = dma_linked_lch[chain_id].linked_dmach_q; + + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { + /* + * Allowing client drivers to set common parameters now, + * so that later only relevant (src_start, dest_start + * and element count) can be set + */ + omap_set_dma_params(channels[i], ¶ms); + } + + return 0; +} +EXPORT_SYMBOL(omap_modify_dma_chain_params); + +/** + * @brief omap_free_dma_chain - Free all the logical channels in a chain. + * + * @param chain_id + * + * @return - Success : 0 + * Failure : -EINVAL + */ +int omap_free_dma_chain(int chain_id) +{ + int *channels; + u32 i; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { + dma_chan[channels[i]].next_linked_ch = -1; + dma_chan[channels[i]].prev_linked_ch = -1; + dma_chan[channels[i]].chain_id = -1; + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; + omap_free_dma(channels[i]); + } + + kfree(channels); + + dma_linked_lch[chain_id].linked_dmach_q = NULL; + dma_linked_lch[chain_id].chain_mode = -1; + dma_linked_lch[chain_id].chain_state = -1; + + return 0; +} +EXPORT_SYMBOL(omap_free_dma_chain); + +/** + * @brief omap_dma_chain_status - Check if the chain is in + * active / inactive state. + * @param chain_id + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_dma_chain_status(int chain_id) +{ + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + pr_debug("CHAINID=%d, qcnt=%d\n", chain_id, + dma_linked_lch[chain_id].q_count); + + if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) + return OMAP_DMA_CHAIN_INACTIVE; + + return OMAP_DMA_CHAIN_ACTIVE; +} +EXPORT_SYMBOL(omap_dma_chain_status); + +/** + * @brief omap_dma_chain_a_transfer - Get a free channel from a chain, + * set the params and start the transfer. + * + * @param chain_id + * @param src_start - buffer start address + * @param dest_start - Dest address + * @param elem_count + * @param frame_count + * @param callbk_data - channel callback parameter data. + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, + int elem_count, int frame_count, void *callbk_data) +{ + int *channels; + u32 l, lch; + int start_dma = 0; + + /* + * if buffer size is less than 1 then there is + * no use of starting the chain + */ + if (elem_count < 1) { + printk(KERN_ERR "Invalid buffer size\n"); + return -EINVAL; + } + + /* Check for input params */ + if (unlikely((chain_id < 0 + || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exist\n"); + return -EINVAL; + } + + /* Check if all the channels in chain are in use */ + if (OMAP_DMA_CHAIN_QFULL(chain_id)) + return -EBUSY; + + /* Frame count may be negative in case of indexed transfers */ + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get a free channel */ + lch = channels[dma_linked_lch[chain_id].q_tail]; + + /* Store the callback data */ + dma_chan[lch].data = callbk_data; + + /* Increment the q_tail */ + OMAP_DMA_CHAIN_INCQTAIL(chain_id); + + /* Set the params to the free channel */ + if (src_start != 0) + dma_write(src_start, CSSA(lch)); + if (dest_start != 0) + dma_write(dest_start, CDSA(lch)); + + /* Write the buffer size */ + dma_write(elem_count, CEN(lch)); + dma_write(frame_count, CFN(lch)); + + /* + * If the chain is dynamically linked, + * then we may have to start the chain if its not active + */ + if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { + + /* + * In Dynamic chain, if the chain is not started, + * queue the channel + */ + if (dma_linked_lch[chain_id].chain_state == + DMA_CHAIN_NOTSTARTED) { + /* Enable the link in previous channel */ + if (dma_chan[dma_chan[lch].prev_linked_ch].state == + DMA_CH_QUEUED) + omap2_enable_lnk(dma_chan[lch].prev_linked_ch); + dma_chan[lch].state = DMA_CH_QUEUED; + } + + /* + * Chain is already started, make sure its active, + * if not then start the chain + */ + else { + start_dma = 1; + + if (dma_chan[dma_chan[lch].prev_linked_ch].state == + DMA_CH_STARTED) { + omap2_enable_lnk(dma_chan[lch].prev_linked_ch); + dma_chan[lch].state = DMA_CH_QUEUED; + start_dma = 0; + if (0 == ((1 << 7) & dma_read( + CCR(dma_chan[lch].prev_linked_ch)))) { + omap2_disable_lnk(dma_chan[lch]. + prev_linked_ch); + pr_debug("\n prev ch is stopped\n"); + start_dma = 1; + } + } + + else if (dma_chan[dma_chan[lch].prev_linked_ch].state + == DMA_CH_QUEUED) { + omap2_enable_lnk(dma_chan[lch].prev_linked_ch); + dma_chan[lch].state = DMA_CH_QUEUED; + start_dma = 0; + } + omap2_enable_channel_irq(lch); + + l = dma_read(CCR(lch)); + + if ((0 == (l & (1 << 24)))) + l &= ~(1 << 25); + else + l |= (1 << 25); + if (start_dma == 1) { + if (0 == (l & (1 << 7))) { + l |= (1 << 7); + dma_chan[lch].state = DMA_CH_STARTED; + pr_debug("starting %d\n", lch); + dma_write(l, CCR(lch)); + } else + start_dma = 0; + } else { + if (0 == (l & (1 << 7))) + dma_write(l, CCR(lch)); + } + dma_chan[lch].flags |= OMAP_DMA_ACTIVE; + } + } + + return 0; +} +EXPORT_SYMBOL(omap_dma_chain_a_transfer); + +/** + * @brief omap_start_dma_chain_transfers - Start the chain + * + * @param chain_id + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_start_dma_chain_transfers(int chain_id) +{ + int *channels; + u32 l, i; + + if (unlikely((chain_id < 0 || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) { + printk(KERN_ERR "Chain is already started\n"); + return -EBUSY; + } + + if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) { + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; + i++) { + omap2_enable_lnk(channels[i]); + omap2_enable_channel_irq(channels[i]); + } + } else { + omap2_enable_channel_irq(channels[0]); + } + + l = dma_read(CCR(channels[0])); + l |= (1 << 7); + dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; + dma_chan[channels[0]].state = DMA_CH_STARTED; + + if ((0 == (l & (1 << 24)))) + l &= ~(1 << 25); + else + l |= (1 << 25); + dma_write(l, CCR(channels[0])); + + dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; + + return 0; +} +EXPORT_SYMBOL(omap_start_dma_chain_transfers); + +/** + * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain. + * + * @param chain_id + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_stop_dma_chain_transfers(int chain_id) +{ + int *channels; + u32 l, i; + u32 get_sysconfig; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + channels = dma_linked_lch[chain_id].linked_dmach_q; + + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, false); + + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { + + /* Stop the Channel transmission */ + l = dma_read(CCR(channels[i])); + l &= ~(1 << 7); + dma_write(l, CCR(channels[i])); + + /* Disable the link in all the channels */ + omap2_disable_lnk(channels[i]); + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; + + } + dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED; + + /* Reset the Queue pointers */ + OMAP_DMA_CHAIN_QINIT(chain_id); + + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, true); + + return 0; +} +EXPORT_SYMBOL(omap_stop_dma_chain_transfers); + +/* Get the index of the ongoing DMA in chain */ +/** + * @brief omap_get_dma_chain_index - Get the element and frame index + * of the ongoing DMA in chain + * + * @param chain_id + * @param ei - Element index + * @param fi - Frame index + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) +{ + int lch; + int *channels; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + if ((!ei) || (!fi)) + return -EINVAL; + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get the current channel */ + lch = channels[dma_linked_lch[chain_id].q_head]; + + *ei = dma_read(CCEN(lch)); + *fi = dma_read(CCFN(lch)); + + return 0; +} +EXPORT_SYMBOL(omap_get_dma_chain_index); + +/** + * @brief omap_get_dma_chain_dst_pos - Get the destination position of the + * ongoing DMA in chain + * + * @param chain_id + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_get_dma_chain_dst_pos(int chain_id) +{ + int lch; + int *channels; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get the current channel */ + lch = channels[dma_linked_lch[chain_id].q_head]; + + return dma_read(CDAC(lch)); +} +EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); + +/** + * @brief omap_get_dma_chain_src_pos - Get the source position + * of the ongoing DMA in chain + * @param chain_id + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_get_dma_chain_src_pos(int chain_id) +{ + int lch; + int *channels; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= dma_chan_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get the current channel */ + lch = channels[dma_linked_lch[chain_id].q_head]; + + return dma_read(CSAC(lch)); +} +EXPORT_SYMBOL(omap_get_dma_chain_src_pos); + +void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) +{ + u32 csdp; + + csdp = dma_read(CSDP(lch)); + csdp &= ~(0x3 << 16); + csdp |= (mode << 16); + dma_write(csdp, CSDP(lch)); +} +EXPORT_SYMBOL(omap_set_dma_write_mode); + +static int omap2_dma_handle_ch(int ch) +{ + u32 status = dma_read(CSR(ch)); + + if (!status) { + if (printk_ratelimit()) + printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", + ch); + dma_write(1 << ch, IRQSTATUS_L0); + return 0; + } + if (unlikely(dma_chan[ch].dev_id == -1)) { + if (printk_ratelimit()) + printk(KERN_WARNING "IRQ %04x for non-allocated DMA" + "channel %d\n", status, ch); + return 0; + } + if (unlikely(status & OMAP_DMA_DROP_IRQ)) + printk(KERN_INFO + "DMA synchronization event drop occurred with device " + "%d\n", dma_chan[ch].dev_id); + if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { + printk(KERN_INFO "DMA transaction error with device %d\n", + dma_chan[ch].dev_id); + if (cpu_class_is_omap2()) { + /* + * Errata: sDMA Channel is not disabled + * after a transaction error. So we explicitely + * disable the channel + */ + u32 ccr; + + ccr = dma_read(CCR(ch)); + ccr &= ~OMAP_DMA_CCR_EN; + dma_write(ccr, CCR(ch)); + dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; + } + } + if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) + printk(KERN_INFO "DMA secure error with device %d\n", + dma_chan[ch].dev_id); + if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) + printk(KERN_INFO "DMA misaligned error with device %d\n", + dma_chan[ch].dev_id); + + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch)); + dma_write(1 << ch, IRQSTATUS_L0); + + /* If the ch is not chained then chain_id will be -1 */ + if (dma_chan[ch].chain_id != -1) { + int chain_id = dma_chan[ch].chain_id; + dma_chan[ch].state = DMA_CH_NOTSTARTED; + if (dma_read(CLNK_CTRL(ch)) & (1 << 15)) + dma_chan[dma_chan[ch].next_linked_ch].state = + DMA_CH_STARTED; + if (dma_linked_lch[chain_id].chain_mode == + OMAP_DMA_DYNAMIC_CHAIN) + omap2_disable_lnk(ch); + + if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) + OMAP_DMA_CHAIN_INCQHEAD(chain_id); + + status = dma_read(CSR(ch)); + } + + dma_write(status, CSR(ch)); + + if (likely(dma_chan[ch].callback != NULL)) + dma_chan[ch].callback(ch, status, dma_chan[ch].data); + + return 0; +} + +/* STATUS register count is from 1-32 while our is 0-31 */ +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + u32 val, enable_reg; + int i; + + val = dma_read(IRQSTATUS_L0); + if (val == 0) { + if (printk_ratelimit()) + printk(KERN_WARNING "Spurious DMA IRQ\n"); + return IRQ_HANDLED; + } + enable_reg = dma_read(IRQENABLE_L0); + val &= enable_reg; /* Dispatch only relevant interrupts */ + for (i = 0; i < dma_chan_count && val != 0; i++) { + if (val & 1) + omap2_dma_handle_ch(i); + val >>= 1; + } + + return IRQ_HANDLED; +} + +static struct irqaction omap24xx_dma_irq = { + .name = "DMA", + .handler = irq_handler, + .flags = IRQF_DISABLED +}; + +/** + * @brief omap_dma_set_global_params : Set global priority settings for dma + * + * @param arb_rate + * @param max_fifo_depth + * @param tparams - Number of threads to reserve: + * DMA_THREAD_RESERVE_NORM + * DMA_THREAD_RESERVE_ONET + * DMA_THREAD_RESERVE_TWOT + * DMA_THREAD_RESERVE_THREET + */ +void +omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) +{ + u32 reg; + + if (max_fifo_depth == 0) + max_fifo_depth = 1; + if (arb_rate == 0) + arb_rate = 1; + + reg = 0xff & max_fifo_depth; + reg |= (0x3 & tparams) << 12; + reg |= (arb_rate & 0xff) << 16; + + dma_write(reg, GCR); +} +EXPORT_SYMBOL(omap_dma_set_global_params); + /* One time initializations */ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) { @@ -70,6 +999,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) struct omap_system_dma_plat_info *pdata; struct resource *mem; char *name = "dma"; + int dma_irq, ret; pdata = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); if (!pdata) { @@ -114,6 +1044,18 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) /* Errata3.3: Applicable for all omap2 plus */ pdata->errata |= OMAP3_3_ERRATUM; + p = pdata; + p->enable_irq_lch = omap2_enable_irq_lch; + p->disable_irq_lch = omap2_disable_irq_lch; + p->enable_channel_irq = omap2_enable_channel_irq; + p->disable_channel_irq = omap2_disable_channel_irq; + p->enable_lnk = omap2_enable_lnk; + p->disable_lnk = omap2_disable_lnk; + p->set_dma_chain_ch = set_dma_chain_ch; + p->clear_lch_regs = NULL; + p->get_gdma_dev = NULL; + p->set_gdma_dev = NULL; + od = omap_device_build(name, 0, oh, pdata, sizeof(*pdata), omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); @@ -136,21 +1078,37 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) return -ENOMEM; } + dma_irq = platform_get_irq_byname(&od->pdev, "dma_0"); + ret = setup_irq(dma_irq, &omap24xx_dma_irq); + if (ret) { + dev_err(&od->pdev.dev, "%s:irq handler setup fail\n", __func__); + return -EINVAL; + } + /* Get DMA device attributes from hwmod data base */ d = (struct omap_dma_dev_attr *)oh->dev_attr; /* OMAP2 Plus: physical and logical channel count is same */ - d->dma_chan_count = d->dma_lch_count; + d->dma_chan_count = d->dma_lch_count; + dma_chan_count = d->dma_chan_count; d->dma_chan = kzalloc(sizeof(struct omap_dma_lch) * - (d->dma_lch_count), GFP_KERNEL); + (dma_chan_count), GFP_KERNEL); if (!d->dma_chan) { dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__); return -ENOMEM; } - omap2_pdata = pdata; + dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * + dma_chan_count, GFP_KERNEL); + if (!dma_linked_lch) { + kfree(d->dma_chan); + return -ENOMEM; + } + + dma_chan = d->dma_chan; + dma_caps0_status = dma_read(CAPS_0); return 0; diff --git a/arch/arm/mach-omap2/include/mach/dma.h b/arch/arm/mach-omap2/include/mach/dma.h index 22f4b41..f3e21d5 100644 --- a/arch/arm/mach-omap2/include/mach/dma.h +++ b/arch/arm/mach-omap2/include/mach/dma.h @@ -160,4 +160,25 @@ struct omap_dma_lch { int status; }; +/* Chaining APIs */ +extern int omap_request_dma_chain(int dev_id, const char *dev_name, + void (*callback) (int lch, u16 ch_status, + void *data), + int *chain_id, int no_of_chans, + int chain_mode, + struct omap_dma_channel_params params); +extern int omap_free_dma_chain(int chain_id); +extern int omap_dma_chain_a_transfer(int chain_id, int src_start, + int dest_start, int elem_count, + int frame_count, void *callbk_data); +extern int omap_start_dma_chain_transfers(int chain_id); +extern int omap_stop_dma_chain_transfers(int chain_id); +extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); +extern int omap_get_dma_chain_dst_pos(int chain_id); +extern int omap_get_dma_chain_src_pos(int chain_id); + +extern int omap_modify_dma_chain_params(int chain_id, + struct omap_dma_channel_params params); +extern int omap_dma_chain_status(int chain_id); + #endif /* __ASM_ARCH_OMAP2_DMA_H */ diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index b31c88f..643f538 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -35,101 +35,25 @@ #include #include + #include -#include +#include #include -#undef DEBUG - -#ifndef CONFIG_ARCH_OMAP1 -enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, - DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED -}; - -enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; -#endif - -#define OMAP_DMA_ACTIVE 0x01 -#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe - -#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) - static int enable_1510_mode; - -static struct omap_dma_global_context_registers { - u32 dma_irqenable_l0; - u32 dma_ocp_sysconfig; - u32 dma_gcr; -} omap_dma_global_context; - -struct dma_link_info { - int *linked_dmach_q; - int no_of_lchs_linked; - - int q_count; - int q_tail; - int q_head; - - int chain_state; - int chain_mode; - -}; - -static struct dma_link_info *dma_linked_lch; - -#ifndef CONFIG_ARCH_OMAP1 - -/* Chain handling macros */ -#define OMAP_DMA_CHAIN_QINIT(chain_id) \ - do { \ - dma_linked_lch[chain_id].q_head = \ - dma_linked_lch[chain_id].q_tail = \ - dma_linked_lch[chain_id].q_count = 0; \ - } while (0) -#define OMAP_DMA_CHAIN_QFULL(chain_id) \ - (dma_linked_lch[chain_id].no_of_lchs_linked == \ - dma_linked_lch[chain_id].q_count) -#define OMAP_DMA_CHAIN_QLAST(chain_id) \ - do { \ - ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ - dma_linked_lch[chain_id].q_count) \ - } while (0) -#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ - (0 == dma_linked_lch[chain_id].q_count) -#define __OMAP_DMA_CHAIN_INCQ(end) \ - ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) -#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ - dma_linked_lch[chain_id].q_count--; \ - } while (0) - -#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ - dma_linked_lch[chain_id].q_count++; \ - } while (0) -#endif - static int dma_lch_count; static int dma_chan_count; static int omap_dma_reserve_channels; static spinlock_t dma_chan_lock; -static struct omap_dma_lch *dma_chan; static void __iomem *omap_dma_base; + +static struct omap_dma_lch *dma_chan; static struct omap_system_dma_plat_info *p; static struct omap_dma_dev_attr *d; -static inline void disable_lnk(int lch); -static void omap_disable_channel_irq(int lch); -static inline void omap_enable_channel_irq(int lch); - -#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ - __func__); - #define dma_read(reg) \ ({ \ u32 __val; \ @@ -148,75 +72,12 @@ static inline void omap_enable_channel_irq(int lch); __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \ }) -#ifdef CONFIG_ARCH_OMAP15XX -/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ -int omap_dma_in_1510_mode(void) -{ - return enable_1510_mode; -} -#else -#define omap_dma_in_1510_mode() 0 -#endif - -#ifdef CONFIG_ARCH_OMAP1 -static inline int get_gdma_dev(int req) -{ - u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; - int shift = ((req - 1) % 5) * 6; - - return ((omap_readl(reg) >> shift) & 0x3f) + 1; -} - -static inline void set_gdma_dev(int req, int dev) -{ - u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; - int shift = ((req - 1) % 5) * 6; - u32 l; - - l = omap_readl(reg); - l &= ~(0x3f << shift); - l |= (dev - 1) << shift; - omap_writel(l, reg); -} -#else -#define set_gdma_dev(req, dev) do {} while (0) -#endif - -static void dma_ocpsysconfig_errata(u32 *sys_cf, bool flag) -{ - u32 l; - - /* - * DMA Errata: - * Special programming model needed to disable DMA before end of block - */ - if (!flag) { - *sys_cf = dma_read(OCP_SYSCONFIG); - l = *sys_cf; - /* Middle mode reg set no Standby */ - l &= ~((1 << 12)|(1 << 13)); - dma_write(l, OCP_SYSCONFIG); - } else - /* put back old value */ - dma_write(*sys_cf, OCP_SYSCONFIG); -} - -/* Omap1 only */ -static void clear_lch_regs(int lch) -{ - int i; - void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch); - - for (i = 0; i < 0x2c; i += 2) - __raw_writew(0, lch_base + i); -} - void omap_set_dma_priority(int lch, int dst_port, int priority) { unsigned long reg; u32 l; - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & IS_WORD_16) { switch (dst_port) { case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ reg = OMAP_TC_OCPT1_PRIOR; @@ -238,9 +99,7 @@ void omap_set_dma_priority(int lch, int dst_port, int priority) l &= ~(0xf << 8); l |= (priority & 0xf) << 8; omap_writel(l, reg); - } - - if (cpu_class_is_omap2()) { + } else { u32 ccr; ccr = dma_read(CCR(lch)); @@ -264,7 +123,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, l |= data_type; dma_write(l, CSDP(lch)); - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & IS_WORD_16) { u16 ccr; ccr = dma_read(CCR(lch)); @@ -278,9 +137,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, if (sync_mode == OMAP_DMA_SYNC_BLOCK) ccr |= 1 << 2; dma_write(ccr, CCR2(lch)); - } - - if (cpu_class_is_omap2() && dma_trigger) { + } else if (dma_trigger) { u32 val; val = dma_read(CCR(lch)); @@ -315,9 +172,9 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params); void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) { - BUG_ON(omap_dma_in_1510_mode()); + BUG_ON(enable_1510_mode); - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & IS_WORD_16) { u16 w; w = dma_read(CCR2(lch)); @@ -346,9 +203,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) w |= 1; /* Channel type G */ } dma_write(w, LCH_CTRL(lch)); - } - - if (cpu_class_is_omap2()) { + } else { u32 val; val = dma_read(CCR(lch)); @@ -374,32 +229,6 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) } EXPORT_SYMBOL(omap_set_dma_color_mode); -void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) -{ - if (cpu_class_is_omap2()) { - u32 csdp; - - csdp = dma_read(CSDP(lch)); - csdp &= ~(0x3 << 16); - csdp |= (mode << 16); - dma_write(csdp, CSDP(lch)); - } -} -EXPORT_SYMBOL(omap_set_dma_write_mode); - -void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) -{ - if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { - u32 l; - - l = dma_read(LCH_CTRL(lch)); - l &= ~0x7; - l |= mode; - dma_write(l, LCH_CTRL(lch)); - } -} -EXPORT_SYMBOL(omap_set_dma_channel_mode); - /* Note that src_port is only for omap1 */ void omap_set_dma_src_params(int lch, int src_port, int src_amode, unsigned long src_start, @@ -407,7 +236,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, { u32 l; - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & SRC_PORT) { u16 w; w = dma_read(CSDP(lch)); @@ -421,12 +250,10 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, l |= src_amode << 12; dma_write(l, CCR(lch)); - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & IS_WORD_16) { dma_write(src_start >> 16, CSSA_U(lch)); dma_write((u16)src_start, CSSA_L(lch)); - } - - if (cpu_class_is_omap2()) + } else dma_write(src_start, CSSA(lch)); dma_write(src_ei, CSEI(lch)); @@ -453,16 +280,6 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) } EXPORT_SYMBOL(omap_set_dma_params); -void omap_set_dma_src_index(int lch, int eidx, int fidx) -{ - if (cpu_class_is_omap2()) - return; - - dma_write(eidx, CSEI(lch)); - dma_write(fidx, CSFI(lch)); -} -EXPORT_SYMBOL(omap_set_dma_src_index); - void omap_set_dma_src_data_pack(int lch, int enable) { u32 l; @@ -487,13 +304,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) case OMAP_DMA_DATA_BURST_DIS: break; case OMAP_DMA_DATA_BURST_4: - if (cpu_class_is_omap2()) - burst = 0x1; - else + if (d->dma_dev_attr & IS_BURST_ONLY4) burst = 0x2; + else + burst = 0x1; break; case OMAP_DMA_DATA_BURST_8: - if (cpu_class_is_omap2()) { + if (!(d->dma_dev_attr & IS_BURST_ONLY4)) { burst = 0x2; break; } @@ -503,7 +320,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) * fall through */ case OMAP_DMA_DATA_BURST_16: - if (cpu_class_is_omap2()) { + if (!(d->dma_dev_attr & IS_BURST_ONLY4)) { burst = 0x3; break; } @@ -527,7 +344,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, { u32 l; - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & DST_PORT) { l = dma_read(CSDP(lch)); l &= ~(0x1f << 9); l |= dest_port << 9; @@ -539,12 +356,10 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, l |= dest_amode << 14; dma_write(l, CCR(lch)); - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & IS_WORD_16) { dma_write(dest_start >> 16, CDSA_U(lch)); dma_write(dest_start, CDSA_L(lch)); - } - - if (cpu_class_is_omap2()) + } else dma_write(dest_start, CDSA(lch)); dma_write(dst_ei, CDEI(lch)); @@ -552,16 +367,6 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, } EXPORT_SYMBOL(omap_set_dma_dest_params); -void omap_set_dma_dest_index(int lch, int eidx, int fidx) -{ - if (cpu_class_is_omap2()) - return; - - dma_write(eidx, CDEI(lch)); - dma_write(fidx, CDFI(lch)); -} -EXPORT_SYMBOL(omap_set_dma_dest_index); - void omap_set_dma_dest_data_pack(int lch, int enable) { u32 l; @@ -586,19 +391,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) case OMAP_DMA_DATA_BURST_DIS: break; case OMAP_DMA_DATA_BURST_4: - if (cpu_class_is_omap2()) - burst = 0x1; - else + if (d->dma_dev_attr & IS_BURST_ONLY4) burst = 0x2; + else + burst = 0x1; break; case OMAP_DMA_DATA_BURST_8: - if (cpu_class_is_omap2()) - burst = 0x2; - else + if (d->dma_dev_attr & IS_BURST_ONLY4) burst = 0x3; + else + burst = 0x2; break; case OMAP_DMA_DATA_BURST_16: - if (cpu_class_is_omap2()) { + if (!(d->dma_dev_attr & IS_BURST_ONLY4)) { burst = 0x3; break; } @@ -616,26 +421,6 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) } EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); -static inline void omap_enable_channel_irq(int lch) -{ - u32 status; - - /* Clear CSR */ - if (cpu_class_is_omap1()) - status = dma_read(CSR(lch)); - else if (cpu_class_is_omap2()) - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); - - /* Enable some nice interrupts. */ - dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); -} - -static void omap_disable_channel_irq(int lch) -{ - if (cpu_class_is_omap2()) - dma_write(0, CICR(lch)); -} - void omap_enable_dma_irq(int lch, u16 bits) { dma_chan[lch].enabled_irqs |= bits; @@ -648,81 +433,6 @@ void omap_disable_dma_irq(int lch, u16 bits) } EXPORT_SYMBOL(omap_disable_dma_irq); -static inline void enable_lnk(int lch) -{ - u32 l; - - l = dma_read(CLNK_CTRL(lch)); - - if (cpu_class_is_omap1()) - l &= ~(1 << 14); - - /* Set the ENABLE_LNK bits */ - if (dma_chan[lch].next_lch != -1) - l = dma_chan[lch].next_lch | (1 << 15); - -#ifndef CONFIG_ARCH_OMAP1 - if (cpu_class_is_omap2()) - if (dma_chan[lch].next_linked_ch != -1) - l = dma_chan[lch].next_linked_ch | (1 << 15); -#endif - - dma_write(l, CLNK_CTRL(lch)); -} - -static inline void disable_lnk(int lch) -{ - u32 l; - - l = dma_read(CLNK_CTRL(lch)); - - /* Disable interrupts */ - if (cpu_class_is_omap1()) { - dma_write(0, CICR(lch)); - /* Set the STOP_LNK bit */ - l |= 1 << 14; - } - - if (cpu_class_is_omap2()) { - omap_disable_channel_irq(lch); - /* Clear the ENABLE_LNK bit */ - l &= ~(1 << 15); - } - - dma_write(l, CLNK_CTRL(lch)); - dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; -} - -static inline void omap2_enable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (!cpu_class_is_omap2()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - val = dma_read(IRQENABLE_L0); - val |= 1 << lch; - dma_write(val, IRQENABLE_L0); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - -static inline void omap2_disable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (!cpu_class_is_omap2()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - val = dma_read(IRQENABLE_L0); - val &= ~(1 << lch); - dma_write(val, IRQENABLE_L0); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) @@ -746,10 +456,9 @@ int omap_request_dma(int dev_id, const char *dev_name, chan = dma_chan + free_ch; chan->dev_id = dev_id; - if (cpu_class_is_omap1()) - clear_lch_regs(free_ch); - - if (cpu_class_is_omap2()) + if (p->clear_lch_regs) + p->clear_lch_regs(free_ch); + else omap_clear_dma(free_ch); spin_unlock_irqrestore(&dma_chan_lock, flags); @@ -759,25 +468,21 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->data = data; chan->flags = 0; -#ifndef CONFIG_ARCH_OMAP1 - if (cpu_class_is_omap2()) { - chan->chain_id = -1; - chan->next_linked_ch = -1; - } -#endif + if (p->set_dma_chain_ch) + p->set_dma_chain_ch(free_ch); chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; - if (cpu_class_is_omap1()) + if (d->dma_dev_attr & IS_WORD_16) chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; - else if (cpu_class_is_omap2()) + else chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | - OMAP2_DMA_TRANS_ERR_IRQ; + OMAP2_DMA_TRANS_ERR_IRQ; - if (cpu_is_omap16xx()) { + if (p->set_gdma_dev) { /* If the sync device is set, configure it dynamically. */ if (dev_id != 0) { - set_gdma_dev(free_ch + 1, dev_id); + p->set_gdma_dev(free_ch + 1, dev_id); dev_id = free_ch + 1; } /* @@ -785,13 +490,15 @@ int omap_request_dma(int dev_id, const char *dev_name, * id. */ dma_write(dev_id | (1 << 10), CCR(free_ch)); - } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { + } else if (d->dma_dev_attr & IS_WORD_16) dma_write(dev_id, CCR(free_ch)); - } - if (cpu_class_is_omap2()) { - omap2_enable_irq_lch(free_ch); - omap_enable_channel_irq(free_ch); + if (p->enable_irq_lch) { + spin_lock_irqsave(&dma_chan_lock, flags); + p->enable_irq_lch(free_ch); + spin_unlock_irqrestore(&dma_chan_lock, flags); + if (p->enable_channel_irq) + p->enable_channel_irq(free_ch); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); dma_write(1 << free_ch, IRQSTATUS_L0); @@ -813,15 +520,18 @@ void omap_free_dma(int lch) return; } - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & IS_WORD_16) { /* Disable all DMA interrupts for the channel. */ dma_write(0, CICR(lch)); /* Make sure the DMA transfer is stopped. */ dma_write(0, CCR(lch)); } - if (cpu_class_is_omap2()) { - omap2_disable_irq_lch(lch); + if (p->disable_irq_lch) { + unsigned long flags; + spin_lock_irqsave(&dma_chan_lock, flags); + p->disable_irq_lch(lch); + spin_unlock_irqrestore(&dma_chan_lock, flags); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); @@ -844,39 +554,6 @@ void omap_free_dma(int lch) EXPORT_SYMBOL(omap_free_dma); /** - * @brief omap_dma_set_global_params : Set global priority settings for dma - * - * @param arb_rate - * @param max_fifo_depth - * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM - * DMA_THREAD_RESERVE_ONET - * DMA_THREAD_RESERVE_TWOT - * DMA_THREAD_RESERVE_THREET - */ -void -omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) -{ - u32 reg; - - if (!cpu_class_is_omap2()) { - printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); - return; - } - - if (max_fifo_depth == 0) - max_fifo_depth = 1; - if (arb_rate == 0) - arb_rate = 1; - - reg = 0xff & max_fifo_depth; - reg |= (0x3 & tparams) << 12; - reg |= (arb_rate & 0xff) << 16; - - dma_write(reg, GCR); -} -EXPORT_SYMBOL(omap_dma_set_global_params); - -/** * @brief omap_dma_set_prio_lch : Set channel wise priority settings * * @param lch @@ -897,7 +574,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio, } l = dma_read(CCR(lch)); l &= ~((1 << 6) | (1 << 26)); - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) + if (d->dma_dev_attr & IS_RW_PRIORIY) l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); else l |= ((read_prio & 0x1) << 6); @@ -918,7 +595,7 @@ void omap_clear_dma(int lch) local_irq_save(flags); - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & IS_WORD_16) { u32 l; l = dma_read(CCR(lch)); @@ -927,9 +604,7 @@ void omap_clear_dma(int lch) /* Clear pending interrupts */ l = dma_read(CSR(lch)); - } - - if (cpu_class_is_omap2()) { + } else { int i; void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch); for (i = 0; i < 0x44; i += 4) @@ -948,18 +623,19 @@ void omap_start_dma(int lch) * The CPC/CDAC register needs to be initialized to zero * before starting dma transfer. */ - if (cpu_is_omap15xx()) + if (d->dma_dev_attr & IS_WORD_16) dma_write(0, CPC(lch)); else dma_write(0, CDAC(lch)); - if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { + if (!enable_1510_mode && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; char dma_chan_link_map[dma_chan_count]; dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ - enable_lnk(lch); + if (p->enable_lnk) + p->enable_lnk(lch); memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); cur_lch = dma_chan[lch].next_lch; @@ -972,8 +648,10 @@ void omap_start_dma(int lch) /* Mark the current channel */ dma_chan_link_map[cur_lch] = 1; - enable_lnk(cur_lch); - omap_enable_channel_irq(cur_lch); + if (p->enable_lnk) + p->enable_lnk(cur_lch); + if (p->enable_channel_irq) + p->enable_channel_irq(cur_lch); cur_lch = next_lch; } while (next_lch != -1); @@ -982,7 +660,8 @@ void omap_start_dma(int lch) if (p->errata & DMA_CHAINING_ERRATA) dma_write(lch, CLNK_CTRL(lch)); - omap_enable_channel_irq(lch); + if (p->enable_channel_irq) + p->enable_channel_irq(lch); l = dma_read(CCR(lch)); @@ -1001,14 +680,14 @@ void omap_stop_dma(int lch) u32 l; /* Disable all interrupts on the channel */ - if (cpu_class_is_omap1()) + if (d->dma_dev_attr & IS_WORD_16) dma_write(0, CICR(lch)); l = dma_read(CCR(lch)); l &= ~OMAP_DMA_CCR_EN; dma_write(l, CCR(lch)); - if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { + if (!(enable_1510_mode && (dma_chan[lch].next_lch != -1))) { int next_lch, cur_lch = lch; char dma_chan_link_map[dma_chan_count]; @@ -1020,7 +699,8 @@ void omap_stop_dma(int lch) /* Mark the current channel */ dma_chan_link_map[cur_lch] = 1; - disable_lnk(cur_lch); + if (p->disable_lnk) + p->disable_lnk(cur_lch); next_lch = dma_chan[cur_lch].next_lch; cur_lch = next_lch; @@ -1070,19 +750,16 @@ dma_addr_t omap_get_dma_src_pos(int lch) { dma_addr_t offset = 0; - if (cpu_is_omap15xx()) + if (d->dma_dev_attr & ENABLE_1510_MODE) offset = dma_read(CPC(lch)); else offset = dma_read(CSAC(lch)); - /* - * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is - * read before the DMA controller finished disabling the channel. - */ - if (!cpu_is_omap15xx() && offset == 0) + if ((p->errata & OMAP3_3_ERRATUM) && !(enable_1510_mode) + && (offset == 0)) offset = dma_read(CSAC(lch)); - if (cpu_class_is_omap1()) + if (d->dma_dev_attr & IS_WORD_16) offset |= (dma_read(CSSA_U(lch)) << 16); return offset; @@ -1101,19 +778,16 @@ dma_addr_t omap_get_dma_dst_pos(int lch) { dma_addr_t offset = 0; - if (cpu_is_omap15xx()) + if (d->dma_dev_attr & ENABLE_1510_MODE) offset = dma_read(CPC(lch)); else offset = dma_read(CDAC(lch)); - /* - * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is - * read before the DMA controller finished disabling the channel. - */ - if (!cpu_is_omap15xx() && offset == 0) + if ((p->errata & OMAP3_3_ERRATUM) && !(enable_1510_mode) + && (offset == 0)) offset = dma_read(CDAC(lch)); - if (cpu_class_is_omap1()) + if (d->dma_dev_attr & IS_WORD_16) offset |= (dma_read(CDSA_U(lch)) << 16); return offset; @@ -1130,7 +804,7 @@ int omap_dma_running(void) { int lch; - if (cpu_class_is_omap1()) + if (d->dma_dev_attr & IS_WORD_16) if (omap_lcd_dma_running()) return 1; @@ -1148,7 +822,7 @@ int omap_dma_running(void) */ void omap_dma_link_lch(int lch_head, int lch_queue) { - if (omap_dma_in_1510_mode()) { + if (enable_1510_mode) { if (lch_head == lch_queue) { dma_write(dma_read(CCR(lch_head)) | (3 << 8), CCR(lch_head)); @@ -1175,7 +849,7 @@ EXPORT_SYMBOL(omap_dma_link_lch); */ void omap_dma_unlink_lch(int lch_head, int lch_queue) { - if (omap_dma_in_1510_mode()) { + if (enable_1510_mode) { if (lch_head == lch_queue) { dma_write(dma_read(CCR(lch_head)) & ~(3 << 8), CCR(lch_head)); @@ -1204,828 +878,11 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) } EXPORT_SYMBOL(omap_dma_unlink_lch); -/*----------------------------------------------------------------------------*/ - -#ifndef CONFIG_ARCH_OMAP1 -/* Create chain of DMA channesls */ -static void create_dma_lch_chain(int lch_head, int lch_queue) -{ - u32 l; - - /* Check if this is the first link in chain */ - if (dma_chan[lch_head].next_linked_ch == -1) { - dma_chan[lch_head].next_linked_ch = lch_queue; - dma_chan[lch_head].prev_linked_ch = lch_queue; - dma_chan[lch_queue].next_linked_ch = lch_head; - dma_chan[lch_queue].prev_linked_ch = lch_head; - } - - /* a link exists, link the new channel in circular chain */ - else { - dma_chan[lch_queue].next_linked_ch = - dma_chan[lch_head].next_linked_ch; - dma_chan[lch_queue].prev_linked_ch = lch_head; - dma_chan[lch_head].next_linked_ch = lch_queue; - dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch = - lch_queue; - } - - l = dma_read(CLNK_CTRL(lch_head)); - l &= ~(0x1f); - l |= lch_queue; - dma_write(l, CLNK_CTRL(lch_head)); - - l = dma_read(CLNK_CTRL(lch_queue)); - l &= ~(0x1f); - l |= (dma_chan[lch_queue].next_linked_ch); - dma_write(l, CLNK_CTRL(lch_queue)); -} - -/** - * @brief omap_request_dma_chain : Request a chain of DMA channels - * - * @param dev_id - Device id using the dma channel - * @param dev_name - Device name - * @param callback - Call back function - * @chain_id - - * @no_of_chans - Number of channels requested - * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN - * OMAP_DMA_DYNAMIC_CHAIN - * @params - Channel parameters - * - * @return - Success : 0 - * Failure: -EINVAL/-ENOMEM - */ -int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int lch, u16 ch_status, - void *data), - int *chain_id, int no_of_chans, int chain_mode, - struct omap_dma_channel_params params) -{ - int *channels; - int i, err; - - /* Is the chain mode valid ? */ - if (chain_mode != OMAP_DMA_STATIC_CHAIN - && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) { - printk(KERN_ERR "Invalid chain mode requested\n"); - return -EINVAL; - } - - if (unlikely((no_of_chans < 1 - || no_of_chans > dma_lch_count))) { - printk(KERN_ERR "Invalid Number of channels requested\n"); - return -EINVAL; - } - - /* - * Allocate a queue to maintain the status of the channels - * in the chain - */ - channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); - if (channels == NULL) { - printk(KERN_ERR "omap_dma: No memory for channel queue\n"); - return -ENOMEM; - } - - /* request and reserve DMA channels for the chain */ - for (i = 0; i < no_of_chans; i++) { - err = omap_request_dma(dev_id, dev_name, - callback, NULL, &channels[i]); - if (err < 0) { - int j; - for (j = 0; j < i; j++) - omap_free_dma(channels[j]); - kfree(channels); - printk(KERN_ERR "omap_dma: Request failed %d\n", err); - return err; - } - dma_chan[channels[i]].prev_linked_ch = -1; - dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; - - /* - * Allowing client drivers to set common parameters now, - * so that later only relevant (src_start, dest_start - * and element count) can be set - */ - omap_set_dma_params(channels[i], ¶ms); - } - - *chain_id = channels[0]; - dma_linked_lch[*chain_id].linked_dmach_q = channels; - dma_linked_lch[*chain_id].chain_mode = chain_mode; - dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED; - dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans; - - for (i = 0; i < no_of_chans; i++) - dma_chan[channels[i]].chain_id = *chain_id; - - /* Reset the Queue pointers */ - OMAP_DMA_CHAIN_QINIT(*chain_id); - - /* Set up the chain */ - if (no_of_chans == 1) - create_dma_lch_chain(channels[0], channels[0]); - else { - for (i = 0; i < (no_of_chans - 1); i++) - create_dma_lch_chain(channels[i], channels[i + 1]); - } - - return 0; -} -EXPORT_SYMBOL(omap_request_dma_chain); - -/** - * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the - * params after setting it. Dont do this while dma is running!! - * - * @param chain_id - Chained logical channel id. - * @param params - * - * @return - Success : 0 - * Failure : -EINVAL - */ -int omap_modify_dma_chain_params(int chain_id, - struct omap_dma_channel_params params) -{ - int *channels; - u32 i; - - /* Check for input params */ - if (unlikely((chain_id < 0 - || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - channels = dma_linked_lch[chain_id].linked_dmach_q; - - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { - /* - * Allowing client drivers to set common parameters now, - * so that later only relevant (src_start, dest_start - * and element count) can be set - */ - omap_set_dma_params(channels[i], ¶ms); - } - - return 0; -} -EXPORT_SYMBOL(omap_modify_dma_chain_params); - -/** - * @brief omap_free_dma_chain - Free all the logical channels in a chain. - * - * @param chain_id - * - * @return - Success : 0 - * Failure : -EINVAL - */ -int omap_free_dma_chain(int chain_id) -{ - int *channels; - u32 i; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { - dma_chan[channels[i]].next_linked_ch = -1; - dma_chan[channels[i]].prev_linked_ch = -1; - dma_chan[channels[i]].chain_id = -1; - dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; - omap_free_dma(channels[i]); - } - - kfree(channels); - - dma_linked_lch[chain_id].linked_dmach_q = NULL; - dma_linked_lch[chain_id].chain_mode = -1; - dma_linked_lch[chain_id].chain_state = -1; - - return (0); -} -EXPORT_SYMBOL(omap_free_dma_chain); - -/** - * @brief omap_dma_chain_status - Check if the chain is in - * active / inactive state. - * @param chain_id - * - * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE - * Failure : -EINVAL - */ -int omap_dma_chain_status(int chain_id) -{ - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - pr_debug("CHAINID=%d, qcnt=%d\n", chain_id, - dma_linked_lch[chain_id].q_count); - - if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) - return OMAP_DMA_CHAIN_INACTIVE; - - return OMAP_DMA_CHAIN_ACTIVE; -} -EXPORT_SYMBOL(omap_dma_chain_status); - -/** - * @brief omap_dma_chain_a_transfer - Get a free channel from a chain, - * set the params and start the transfer. - * - * @param chain_id - * @param src_start - buffer start address - * @param dest_start - Dest address - * @param elem_count - * @param frame_count - * @param callbk_data - channel callback parameter data. - * - * @return - Success : 0 - * Failure: -EINVAL/-EBUSY - */ -int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, - int elem_count, int frame_count, void *callbk_data) -{ - int *channels; - u32 l, lch; - int start_dma = 0; - - /* - * if buffer size is less than 1 then there is - * no use of starting the chain - */ - if (elem_count < 1) { - printk(KERN_ERR "Invalid buffer size\n"); - return -EINVAL; - } - - /* Check for input params */ - if (unlikely((chain_id < 0 - || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exist\n"); - return -EINVAL; - } - - /* Check if all the channels in chain are in use */ - if (OMAP_DMA_CHAIN_QFULL(chain_id)) - return -EBUSY; - - /* Frame count may be negative in case of indexed transfers */ - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get a free channel */ - lch = channels[dma_linked_lch[chain_id].q_tail]; - - /* Store the callback data */ - dma_chan[lch].data = callbk_data; - - /* Increment the q_tail */ - OMAP_DMA_CHAIN_INCQTAIL(chain_id); - - /* Set the params to the free channel */ - if (src_start != 0) - dma_write(src_start, CSSA(lch)); - if (dest_start != 0) - dma_write(dest_start, CDSA(lch)); - - /* Write the buffer size */ - dma_write(elem_count, CEN(lch)); - dma_write(frame_count, CFN(lch)); - - /* - * If the chain is dynamically linked, - * then we may have to start the chain if its not active - */ - if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { - - /* - * In Dynamic chain, if the chain is not started, - * queue the channel - */ - if (dma_linked_lch[chain_id].chain_state == - DMA_CHAIN_NOTSTARTED) { - /* Enable the link in previous channel */ - if (dma_chan[dma_chan[lch].prev_linked_ch].state == - DMA_CH_QUEUED) - enable_lnk(dma_chan[lch].prev_linked_ch); - dma_chan[lch].state = DMA_CH_QUEUED; - } - - /* - * Chain is already started, make sure its active, - * if not then start the chain - */ - else { - start_dma = 1; - - if (dma_chan[dma_chan[lch].prev_linked_ch].state == - DMA_CH_STARTED) { - enable_lnk(dma_chan[lch].prev_linked_ch); - dma_chan[lch].state = DMA_CH_QUEUED; - start_dma = 0; - if (0 == ((1 << 7) & dma_read( - CCR(dma_chan[lch].prev_linked_ch)))) { - disable_lnk(dma_chan[lch]. - prev_linked_ch); - pr_debug("\n prev ch is stopped\n"); - start_dma = 1; - } - } - - else if (dma_chan[dma_chan[lch].prev_linked_ch].state - == DMA_CH_QUEUED) { - enable_lnk(dma_chan[lch].prev_linked_ch); - dma_chan[lch].state = DMA_CH_QUEUED; - start_dma = 0; - } - omap_enable_channel_irq(lch); - - l = dma_read(CCR(lch)); - - if ((0 == (l & (1 << 24)))) - l &= ~(1 << 25); - else - l |= (1 << 25); - if (start_dma == 1) { - if (0 == (l & (1 << 7))) { - l |= (1 << 7); - dma_chan[lch].state = DMA_CH_STARTED; - pr_debug("starting %d\n", lch); - dma_write(l, CCR(lch)); - } else - start_dma = 0; - } else { - if (0 == (l & (1 << 7))) - dma_write(l, CCR(lch)); - } - dma_chan[lch].flags |= OMAP_DMA_ACTIVE; - } - } - - return 0; -} -EXPORT_SYMBOL(omap_dma_chain_a_transfer); - -/** - * @brief omap_start_dma_chain_transfers - Start the chain - * - * @param chain_id - * - * @return - Success : 0 - * Failure : -EINVAL/-EBUSY - */ -int omap_start_dma_chain_transfers(int chain_id) -{ - int *channels; - u32 l, i; - - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) { - printk(KERN_ERR "Chain is already started\n"); - return -EBUSY; - } - - if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) { - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; - i++) { - enable_lnk(channels[i]); - omap_enable_channel_irq(channels[i]); - } - } else { - omap_enable_channel_irq(channels[0]); - } - - l = dma_read(CCR(channels[0])); - l |= (1 << 7); - dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; - dma_chan[channels[0]].state = DMA_CH_STARTED; - - if ((0 == (l & (1 << 24)))) - l &= ~(1 << 25); - else - l |= (1 << 25); - dma_write(l, CCR(channels[0])); - - dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; - - return 0; -} -EXPORT_SYMBOL(omap_start_dma_chain_transfers); - -/** - * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain. - * - * @param chain_id - * - * @return - Success : 0 - * Failure : EINVAL - */ -int omap_stop_dma_chain_transfers(int chain_id) -{ - int *channels; - u32 l, i; - u32 get_sysconfig; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - channels = dma_linked_lch[chain_id].linked_dmach_q; - - if (p->errata & DMA_SYSCONFIG_ERRATA) - dma_ocpsysconfig_errata(&get_sysconfig, false); - - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { - - /* Stop the Channel transmission */ - l = dma_read(CCR(channels[i])); - l &= ~(1 << 7); - dma_write(l, CCR(channels[i])); - - /* Disable the link in all the channels */ - disable_lnk(channels[i]); - dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; - - } - dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED; - - /* Reset the Queue pointers */ - OMAP_DMA_CHAIN_QINIT(chain_id); - - if (p->errata & DMA_SYSCONFIG_ERRATA) - dma_ocpsysconfig_errata(&get_sysconfig, true); - - return 0; -} -EXPORT_SYMBOL(omap_stop_dma_chain_transfers); - -/* Get the index of the ongoing DMA in chain */ -/** - * @brief omap_get_dma_chain_index - Get the element and frame index - * of the ongoing DMA in chain - * - * @param chain_id - * @param ei - Element index - * @param fi - Frame index - * - * @return - Success : 0 - * Failure : -EINVAL - */ -int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) -{ - int lch; - int *channels; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - if ((!ei) || (!fi)) - return -EINVAL; - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get the current channel */ - lch = channels[dma_linked_lch[chain_id].q_head]; - - *ei = dma_read(CCEN(lch)); - *fi = dma_read(CCFN(lch)); - - return 0; -} -EXPORT_SYMBOL(omap_get_dma_chain_index); - -/** - * @brief omap_get_dma_chain_dst_pos - Get the destination position of the - * ongoing DMA in chain - * - * @param chain_id - * - * @return - Success : Destination position - * Failure : -EINVAL - */ -int omap_get_dma_chain_dst_pos(int chain_id) -{ - int lch; - int *channels; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get the current channel */ - lch = channels[dma_linked_lch[chain_id].q_head]; - - return dma_read(CDAC(lch)); -} -EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); - -/** - * @brief omap_get_dma_chain_src_pos - Get the source position - * of the ongoing DMA in chain - * @param chain_id - * - * @return - Success : Destination position - * Failure : -EINVAL - */ -int omap_get_dma_chain_src_pos(int chain_id) -{ - int lch; - int *channels; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get the current channel */ - lch = channels[dma_linked_lch[chain_id].q_head]; - - return dma_read(CSAC(lch)); -} -EXPORT_SYMBOL(omap_get_dma_chain_src_pos); -#endif /* ifndef CONFIG_ARCH_OMAP1 */ - -/*----------------------------------------------------------------------------*/ - -#ifdef CONFIG_ARCH_OMAP1 - -static int omap1_dma_handle_ch(int ch) -{ - u32 csr; - - if (enable_1510_mode && ch >= 6) { - csr = dma_chan[ch].saved_csr; - dma_chan[ch].saved_csr = 0; - } else - csr = dma_read(CSR(ch)); - if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { - dma_chan[ch + 6].saved_csr = csr >> 7; - csr &= 0x7f; - } - if ((csr & 0x3f) == 0) - return 0; - if (unlikely(dma_chan[ch].dev_id == -1)) { - printk(KERN_WARNING "Spurious interrupt from DMA channel " - "%d (CSR %04x)\n", ch, csr); - return 0; - } - if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) - printk(KERN_WARNING "DMA timeout with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(csr & OMAP_DMA_DROP_IRQ)) - printk(KERN_WARNING "DMA synchronization event drop occurred " - "with device %d\n", dma_chan[ch].dev_id); - if (likely(csr & OMAP_DMA_BLOCK_IRQ)) - dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; - if (likely(dma_chan[ch].callback != NULL)) - dma_chan[ch].callback(ch, csr, dma_chan[ch].data); - - return 1; -} - -static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) -{ - int ch = ((int) dev_id) - 1; - int handled = 0; - - for (;;) { - int handled_now = 0; - - handled_now += omap1_dma_handle_ch(ch); - if (enable_1510_mode && dma_chan[ch + 6].saved_csr) - handled_now += omap1_dma_handle_ch(ch + 6); - if (!handled_now) - break; - handled += handled_now; - } - - return handled ? IRQ_HANDLED : IRQ_NONE; -} - -#else -#define omap1_dma_irq_handler NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2PLUS - -static int omap2_dma_handle_ch(int ch) -{ - u32 status = dma_read(CSR(ch)); - - if (!status) { - if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", - ch); - dma_write(1 << ch, IRQSTATUS_L0); - return 0; - } - if (unlikely(dma_chan[ch].dev_id == -1)) { - if (printk_ratelimit()) - printk(KERN_WARNING "IRQ %04x for non-allocated DMA" - "channel %d\n", status, ch); - return 0; - } - if (unlikely(status & OMAP_DMA_DROP_IRQ)) - printk(KERN_INFO - "DMA synchronization event drop occurred with device " - "%d\n", dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { - printk(KERN_INFO "DMA transaction error with device %d\n", - dma_chan[ch].dev_id); - if (cpu_class_is_omap2()) { - /* - * Errata: sDMA Channel is not disabled - * after a transaction error. So we explicitely - * disable the channel - */ - u32 ccr; - - ccr = dma_read(CCR(ch)); - ccr &= ~OMAP_DMA_CCR_EN; - dma_write(ccr, CCR(ch)); - dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; - } - } - if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) - printk(KERN_INFO "DMA secure error with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) - printk(KERN_INFO "DMA misaligned error with device %d\n", - dma_chan[ch].dev_id); - - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch)); - dma_write(1 << ch, IRQSTATUS_L0); - - /* If the ch is not chained then chain_id will be -1 */ - if (dma_chan[ch].chain_id != -1) { - int chain_id = dma_chan[ch].chain_id; - dma_chan[ch].state = DMA_CH_NOTSTARTED; - if (dma_read(CLNK_CTRL(ch)) & (1 << 15)) - dma_chan[dma_chan[ch].next_linked_ch].state = - DMA_CH_STARTED; - if (dma_linked_lch[chain_id].chain_mode == - OMAP_DMA_DYNAMIC_CHAIN) - disable_lnk(ch); - - if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) - OMAP_DMA_CHAIN_INCQHEAD(chain_id); - - status = dma_read(CSR(ch)); - } - - dma_write(status, CSR(ch)); - - if (likely(dma_chan[ch].callback != NULL)) - dma_chan[ch].callback(ch, status, dma_chan[ch].data); - - return 0; -} - -/* STATUS register count is from 1-32 while our is 0-31 */ -static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) -{ - u32 val, enable_reg; - int i; - - val = dma_read(IRQSTATUS_L0); - if (val == 0) { - if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ\n"); - return IRQ_HANDLED; - } - enable_reg = dma_read(IRQENABLE_L0); - val &= enable_reg; /* Dispatch only relevant interrupts */ - for (i = 0; i < dma_lch_count && val != 0; i++) { - if (val & 1) - omap2_dma_handle_ch(i); - val >>= 1; - } - - return IRQ_HANDLED; -} - -static struct irqaction omap24xx_dma_irq = { - .name = "DMA", - .handler = omap2_dma_irq_handler, - .flags = IRQF_DISABLED -}; - -#else -static struct irqaction omap24xx_dma_irq; -#endif - -/*----------------------------------------------------------------------------*/ - -void omap_dma_global_context_save(void) -{ - omap_dma_global_context.dma_irqenable_l0 = - dma_read(IRQENABLE_L0); - omap_dma_global_context.dma_ocp_sysconfig = - dma_read(OCP_SYSCONFIG); - omap_dma_global_context.dma_gcr = dma_read(GCR); -} - -void omap_dma_global_context_restore(void) -{ - int ch; - - dma_write(omap_dma_global_context.dma_gcr, GCR); - dma_write(omap_dma_global_context.dma_ocp_sysconfig, - OCP_SYSCONFIG); - dma_write(omap_dma_global_context.dma_irqenable_l0, - IRQENABLE_L0); - - /* - * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared - * after secure sram context save and restore. Hence we need to - * manually clear those IRQs to avoid spurious interrupts. This - * affects only secure devices. - */ - if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) - dma_write(0x3 , IRQSTATUS_L0); - - for (ch = 0; ch < dma_chan_count; ch++) - if (dma_chan[ch].dev_id != -1) - omap_clear_dma(ch); -} - static int __devinit omap_system_dma_probe(struct platform_device *pdev) { struct omap_system_dma_plat_info *pdata = pdev->dev.platform_data; struct resource *mem; int ch, ret = 0; - int dma_irq; - char irq_name[14]; if (!pdata) { dev_err(&pdev->dev, "%s: System DMA initialized without" @@ -2046,10 +903,11 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) if (!omap_dma_base) { dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); ret = -ENOMEM; - goto exit_release_region; + release_mem_region(mem->start, resource_size(mem)); + return ret; } - if (cpu_class_is_omap2() && omap_dma_reserve_channels + if (!(d->dma_dev_attr & IS_WORD_16) && omap_dma_reserve_channels && (omap_dma_reserve_channels <= dma_lch_count)) d->dma_lch_count = omap_dma_reserve_channels; @@ -2057,19 +915,12 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) dma_chan_count = d->dma_chan_count; dma_chan = d->dma_chan; - if (cpu_class_is_omap2()) { - dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * - dma_lch_count, GFP_KERNEL); - if (!dma_linked_lch) { - ret = -ENOMEM; - goto exit_dma_chan; - } - } + enable_1510_mode = d->dma_dev_attr & ENABLE_1510_MODE; - if (cpu_is_omap15xx()) { + if (enable_1510_mode) { printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); - } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { + } else if (d->dma_dev_attr & IS_WORD_16) { printk(KERN_INFO "OMAP DMA hardware version %d\n", dma_read(HW_ID)); printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", @@ -2087,7 +938,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) w |= 1 << 3; dma_write(w, GSCR); } - } else if (cpu_class_is_omap2()) { + } else { u8 revision = dma_read(REVISION) & 0xff; printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", revision >> 4, revision & 0xf); @@ -2096,60 +947,23 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) spin_lock_init(&dma_chan_lock); for (ch = 0; ch < dma_chan_count; ch++) { omap_clear_dma(ch); - if (cpu_class_is_omap2()) - omap2_disable_irq_lch(ch); + if (p->disable_irq_lch) { + unsigned long flags; + spin_lock_irqsave(&dma_chan_lock, flags); + p->disable_irq_lch(ch); + spin_unlock_irqrestore(&dma_chan_lock, flags); + } dma_chan[ch].dev_id = -1; dma_chan[ch].next_lch = -1; - - if (ch >= 6 && enable_1510_mode) - continue; - - if (cpu_class_is_omap1()) { - /* - * request_irq() doesn't like dev_id (ie. ch) being - * zero, so we have to kludge around this. - */ - dma_irq = platform_get_irq_byname(pdev, irq_name); - - if (dma_irq < 0) { - dev_err(&pdev->dev, "%s:unable to get irq\n", - __func__); - ret = dma_irq; - goto exit_unmap; - } - ret = request_irq(dma_irq, - omap1_dma_irq_handler, 0, "DMA", - (void *) (ch + 1)); - if (ret != 0) { - int irq_rel; - printk(KERN_ERR "unable to request IRQ %d" - "for DMA (error %d)\n", dma_irq, ret); - for (irq_rel = 0; irq_rel < ch; - irq_rel++) { - dma_irq = platform_get_irq(pdev, - irq_rel); - free_irq(dma_irq, (void *) - (irq_rel + 1)); - goto exit_dma_chan; - } - } - } } - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) + if (d->dma_dev_attr & GLOBAL_PRIORITY) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); - if (cpu_class_is_omap2()) { - strcpy(irq_name, "dma_0"); - dma_irq = platform_get_irq_byname(pdev, irq_name); - setup_irq(dma_irq, &omap24xx_dma_irq); - } - /* reserve dma channels 0 and 1 in high security devices */ - if (cpu_is_omap34xx() && - (omap_type() != OMAP2_DEVICE_TYPE_GP)) { + if (d->dma_dev_attr & RESERVE_CHANNEL) { printk(KERN_INFO "Reserving DMA channels 0 and 1 for " "HS ROM code\n"); dma_chan[0].dev_id = 0; @@ -2158,14 +972,6 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) dev_info(&pdev->dev, "System DMA registered\n"); return 0; - -exit_dma_chan: - kfree(dma_chan); -exit_unmap: - iounmap(omap_dma_base); -exit_release_region: - release_mem_region(mem->start, resource_size(mem)); - return ret; } static int __devexit omap_system_dma_remove(struct platform_device *pdev) diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 6d1fee0..bed582b 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -241,6 +241,9 @@ #define DMA_THREAD_FIFO_25 (0x02 << 14) #define DMA_THREAD_FIFO_50 (0x03 << 14) +#define OMAP_DMA_ACTIVE 0x01 +#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe + /* Chaining modes*/ #ifndef CONFIG_ARCH_OMAP1 #define OMAP_DMA_STATIC_CHAIN 0x1 @@ -354,6 +357,16 @@ struct omap_system_dma_plat_info { struct omap_dma_dev_attr *dma_attr; void __iomem *omap_dma_base; u32 errata; + void (*enable_irq_lch)(int lch); + void (*disable_irq_lch)(int lch); + void (*enable_lnk)(int lch); + void (*disable_lnk)(int lch); + void (*clear_lch_regs)(int lch); + int (*get_gdma_dev)(int req); + void (*set_gdma_dev)(int req, int dev); + void (*enable_channel_irq)(int lch); + void (*disable_channel_irq)(int lch); + void (*set_dma_chain_ch)(int free_ch); }; extern void omap_set_dma_priority(int lch, int dst_port, int priority); @@ -417,29 +430,6 @@ void omap_dma_global_context_restore(void); extern void omap_dma_disable_irq(int lch); -/* Chaining APIs */ -#ifndef CONFIG_ARCH_OMAP1 -extern int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int lch, u16 ch_status, - void *data), - int *chain_id, int no_of_chans, - int chain_mode, - struct omap_dma_channel_params params); -extern int omap_free_dma_chain(int chain_id); -extern int omap_dma_chain_a_transfer(int chain_id, int src_start, - int dest_start, int elem_count, - int frame_count, void *callbk_data); -extern int omap_start_dma_chain_transfers(int chain_id); -extern int omap_stop_dma_chain_transfers(int chain_id); -extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); -extern int omap_get_dma_chain_dst_pos(int chain_id); -extern int omap_get_dma_chain_src_pos(int chain_id); - -extern int omap_modify_dma_chain_params(int chain_id, - struct omap_dma_channel_params params); -extern int omap_dma_chain_status(int chain_id); -#endif - #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP) #include #else From patchwork Wed Jul 21 17:33:43 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113412 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONV007938 for ; Wed, 21 Jul 2010 17:35:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758422Ab0GURe5 (ORCPT ); Wed, 21 Jul 2010 13:34:57 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758465Ab0GURez (ORCPT ); Wed, 21 Jul 2010 13:34:55 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:54 -0700 (PDT) Received: by 10.204.163.69 with SMTP id z5mr333625bkx.167.1279733694470; Wed, 21 Jul 2010 10:34:54 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:53 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 09/20] wireless: wl1271: make ref_clock configurable by board Date: Wed, 21 Jul 2010 20:33:43 +0300 Message-Id: <1279733634-21974-10-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:13 +0000 (UTC) diff --git a/drivers/net/wireless/wl12xx/wl1271.h b/drivers/net/wireless/wl12xx/wl1271.h index a21cdb2..595f1a8 100644 --- a/drivers/net/wireless/wl12xx/wl1271.h +++ b/drivers/net/wireless/wl12xx/wl1271.h @@ -357,6 +357,7 @@ struct wl1271 { void (*set_power)(bool enable); int irq; + int ref_clock; spinlock_t wl_lock; diff --git a/drivers/net/wireless/wl12xx/wl1271_boot.c b/drivers/net/wireless/wl12xx/wl1271_boot.c index 1a36d8a..d3f0521 100644 --- a/drivers/net/wireless/wl12xx/wl1271_boot.c +++ b/drivers/net/wireless/wl12xx/wl1271_boot.c @@ -455,17 +455,18 @@ int wl1271_boot(struct wl1271 *wl) { int ret = 0; u32 tmp, clk, pause; + int ref_clock = wl->ref_clock; wl1271_boot_hw_version(wl); - if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4) + if (ref_clock == 0 || ref_clock == 2 || ref_clock == 4) /* ref clk: 19.2/38.4/38.4-XTAL */ clk = 0x3; - else if (REF_CLOCK == 1 || REF_CLOCK == 3) + else if (ref_clock == 1 || ref_clock == 3) /* ref clk: 26/52 */ clk = 0x5; - if (REF_CLOCK != 0) { + if (ref_clock != 0) { u16 val; /* Set clock type (open drain) */ val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE); @@ -514,7 +515,7 @@ int wl1271_boot(struct wl1271 *wl) wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); /* 2 */ - clk |= (REF_CLOCK << 1) << 4; + clk |= (ref_clock << 1) << 4; wl1271_write32(wl, DRPW_SCRATCH_START, clk); wl1271_set_partition(wl, &part_table[PART_WORK]); diff --git a/drivers/net/wireless/wl12xx/wl1271_boot.h b/drivers/net/wireless/wl12xx/wl1271_boot.h index f829699..f73b0b1 100644 --- a/drivers/net/wireless/wl12xx/wl1271_boot.h +++ b/drivers/net/wireless/wl12xx/wl1271_boot.h @@ -46,7 +46,6 @@ struct wl1271_static_data { /* delay between retries */ #define INIT_LOOP_DELAY 50 -#define REF_CLOCK 2 #define WU_COUNTER_PAUSE_VAL 0x3FF #define WELP_ARM_COMMAND_VAL 0x4 diff --git a/drivers/net/wireless/wl12xx/wl1271_sdio.c b/drivers/net/wireless/wl12xx/wl1271_sdio.c index 75901a6..5967718 100644 --- a/drivers/net/wireless/wl12xx/wl1271_sdio.c +++ b/drivers/net/wireless/wl12xx/wl1271_sdio.c @@ -198,11 +198,12 @@ static int __devinit wl1271_probe(struct sdio_func *func, func->card->quirks |= MMC_QUIRK_LENIENT_FN0; wlan_data = mmc_get_embedded_data(func->card->host); - if (wlan_data && wlan_data->irq) + if (wlan_data) { wl->irq = wlan_data->irq; - else { + wl->ref_clock = wlan_data->board_ref_clock; + } else { ret = -EINVAL; - wl1271_error("could not get irq!"); + wl1271_error("missing wlan data (needed for irq/ref_clk)!"); goto out_free; } diff --git a/drivers/net/wireless/wl12xx/wl1271_spi.c b/drivers/net/wireless/wl12xx/wl1271_spi.c index 85a167f..501b8b4 100644 --- a/drivers/net/wireless/wl12xx/wl1271_spi.c +++ b/drivers/net/wireless/wl12xx/wl1271_spi.c @@ -373,6 +373,8 @@ static int __devinit wl1271_probe(struct spi_device *spi) goto out_free; } + wl->ref_clock = pdata->board_ref_clock; + wl->irq = spi->irq; if (wl->irq < 0) { wl1271_error("irq missing in platform data"); diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h index 137ac89..ef6eed9 100644 --- a/include/linux/wl12xx.h +++ b/include/linux/wl12xx.h @@ -29,6 +29,7 @@ struct wl12xx_platform_data { /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */ int irq; bool use_eeprom; + int board_ref_clock; }; #endif From patchwork Wed Jul 21 17:33:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113410 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONT007938 for ; Wed, 21 Jul 2010 17:35:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758463Ab0GURey (ORCPT ); Wed, 21 Jul 2010 13:34:54 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758422Ab0GURew (ORCPT ); Wed, 21 Jul 2010 13:34:52 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:51 -0700 (PDT) Received: by 10.204.118.3 with SMTP id t3mr325264bkq.163.1279733691043; Wed, 21 Jul 2010 10:34:51 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.47 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:50 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 08/20] wireless: wl1271: take irq info from private board data Date: Wed, 21 Jul 2010 20:33:42 +0300 Message-Id: <1279733634-21974-9-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:13 +0000 (UTC) diff --git a/drivers/net/wireless/wl12xx/wl1271_sdio.c b/drivers/net/wireless/wl12xx/wl1271_sdio.c index 571c6b9..75901a6 100644 --- a/drivers/net/wireless/wl12xx/wl1271_sdio.c +++ b/drivers/net/wireless/wl12xx/wl1271_sdio.c @@ -28,15 +28,14 @@ #include #include #include +#include +#include #include #include "wl1271.h" #include "wl12xx_80211.h" #include "wl1271_io.h" - -#define RX71_WL1271_IRQ_GPIO 42 - static const struct sdio_device_id wl1271_devices[] = { { SDIO_DEVICE(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271) }, {} @@ -178,6 +177,7 @@ static int __devinit wl1271_probe(struct sdio_func *func, const struct sdio_device_id *id) { struct ieee80211_hw *hw; + struct wl12xx_platform_data *wlan_data; struct wl1271 *wl; int ret; @@ -197,9 +197,11 @@ static int __devinit wl1271_probe(struct sdio_func *func, /* Grab access to FN0 for ELP reg. */ func->card->quirks |= MMC_QUIRK_LENIENT_FN0; - wl->irq = gpio_to_irq(RX71_WL1271_IRQ_GPIO); - if (wl->irq < 0) { - ret = wl->irq; + wlan_data = mmc_get_embedded_data(func->card->host); + if (wlan_data && wlan_data->irq) + wl->irq = wlan_data->irq; + else { + ret = -EINVAL; wl1271_error("could not get irq!"); goto out_free; } From patchwork Wed Aug 4 11:24:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 116999 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74BP9p6022066 for ; Wed, 4 Aug 2010 11:25:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932631Ab0HDLZE (ORCPT ); Wed, 4 Aug 2010 07:25:04 -0400 Received: from mail-gw0-f46.google.com ([74.125.83.46]:46926 "EHLO mail-gw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932618Ab0HDLZA (ORCPT ); Wed, 4 Aug 2010 07:25:00 -0400 Received: by gwb20 with SMTP id 20so1920725gwb.19 for ; Wed, 04 Aug 2010 04:24:59 -0700 (PDT) Received: by 10.231.34.70 with SMTP id k6mr10298825ibd.25.1280921099589; Wed, 04 Aug 2010 04:24:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.146.207 with HTTP; Wed, 4 Aug 2010 04:24:39 -0700 (PDT) X-Originating-IP: [89.139.22.112] In-Reply-To: References: <1279733634-21974-1-git-send-email-ohad@wizery.com> <1279733634-21974-4-git-send-email-ohad@wizery.com> From: Ohad Ben-Cohen Date: Wed, 4 Aug 2010 14:24:39 +0300 Message-ID: Subject: Re: [PATCH v2 03/20] mmc: support embedded data field in mmc_host To: Vitaly Wool Cc: linux-wireless@vger.kernel.org, linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org, Kalle Valo , Pandita Vikram , linux@arm.linux.org.uk, Nicolas Pitre , Tony Lindgren , Roger Quadros , San Mehat , Chikkature Rajashekar Madhusudhan , Luciano Coelho , akpm@linux-foundation.org, linux-arm-kernel@lists.infradead.org Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 11:25:10 +0000 (UTC) diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout index 13755f5..df32b2f 100644 --- a/arch/arm/mach-msm/board-trout-mmc.c +++ b/arch/arm/mach-msm/board-trout-mmc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -297,11 +298,16 @@ int trout_wifi_reset(int on) EXPORT_SYMBOL(trout_wifi_reset); #endif +struct wl12xx_platform_data trout_wlan_data = { + .irq = 62, /* put here your irq number */ + .board_ref_clock = 1, /* put here your ref clock */ +}; + static struct mmc_platform_data trout_wifi_data = { .ocr_mask = MMC_VDD_28_29, .status = trout_wifi_status, .register_status_notify = trout_wifi_status_register, - .embedded_sdio = &trout_wifi_emb_data, + .embedded_sdio = &trout_wlan_data, }; int __init trout_init_mmc(unsigned int sys_rev) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 1697d42..c40f0d1 100755 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -1261,6 +1261,7 @@ msmsdcc_probe(struct platform_device *pdev) mmc->f_min = msmsdcc_fmin; mmc->f_max = msmsdcc_fmax; mmc->ocr_avail = plat->ocr_mask; + mmc_set_embedded_data(mmc, plat->embedded_sdio); if (msmsdcc_4bit) mmc->caps |= MMC_CAP_4_BIT_DATA; From patchwork Tue Jun 22 15:01:48 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107408 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF1axS017688 for ; Tue, 22 Jun 2010 15:01:39 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758746Ab0FVPBg (ORCPT ); Tue, 22 Jun 2010 11:01:36 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33378 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758669Ab0FVPBb (ORCPT ); Tue, 22 Jun 2010 11:01:31 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1NwH031356 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:26 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZl026711; Tue, 22 Jun 2010 20:31:21 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 05/13] OMAP: GPIO: Introduce support for OMAP16xx chip GPIO init Date: Tue, 22 Jun 2010 20:31:48 +0530 Message-Id: <1277218916-15213-6-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-5-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> <1277218916-15213-3-git-send-email-charu@ti.com> <1277218916-15213-4-git-send-email-charu@ti.com> <1277218916-15213-5-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:39 +0000 (UTC) diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c new file mode 100644 index 0000000..4f042bf --- /dev/null +++ b/arch/arm/mach-omap1/gpio16xx.c @@ -0,0 +1,209 @@ +/* + * OMAP16XX-specific gpio code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Author: + * Charulatha V + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#define OMAP1610_GPIO1_BASE 0xfffbe400 +#define OMAP1610_GPIO2_BASE 0xfffbec00 +#define OMAP1610_GPIO3_BASE 0xfffbb400 +#define OMAP1610_GPIO4_BASE 0xfffbbc00 +#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE + +static struct omap_gpio_dev_attr omap16xx_gpio_attr = { + .gpio_bank_width = 16, + .omap1_ick_flag = false, +}; + +/* + * OMAP16XX MPU GPIO interface data + */ +static struct __initdata resource omap16xx_mpu_gpio_resources[] = { + { + .start = OMAP1_MPUIO_VBASE, + .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MPUIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { + .virtual_irq_start = IH_MPUIO_BASE, + .bank_type = METHOD_MPUIO, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_mpu_gpio = { + .name = "omap-gpio", + .id = 0, + .dev = { + .platform_data = &omap16xx_mpu_gpio_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_mpu_gpio_resources), + .resource = omap16xx_mpu_gpio_resources, +}; + +/* + * OMAP16XX GPIO1 interface data + */ +static struct __initdata resource omap16xx_gpio1_resources[] = { + { + .start = OMAP1610_GPIO1_BASE, + .end = OMAP1610_GPIO1_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_GPIO_BANK1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { + .virtual_irq_start = IH_GPIO_BASE, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio1 = { + .name = "omap-gpio", + .id = 1, + .dev = { + .platform_data = &omap16xx_gpio1_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio1_resources), + .resource = omap16xx_gpio1_resources, +}; + +/* + * OMAP16XX GPIO2 interface data + */ +static struct __initdata resource omap16xx_gpio2_resources[] = { + { + .start = OMAP1610_GPIO2_BASE, + .end = OMAP1610_GPIO2_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_1610_GPIO_BANK2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { + .virtual_irq_start = IH_GPIO_BASE + 16, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio2 = { + .name = "omap-gpio", + .id = 2, + .dev = { + .platform_data = &omap16xx_gpio2_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio2_resources), + .resource = omap16xx_gpio2_resources, +}; + +/* + * OMAP16XX GPIO3 interface data + */ +static struct __initdata resource omap16xx_gpio3_resources[] = { + { + .start = OMAP1610_GPIO3_BASE, + .end = OMAP1610_GPIO3_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_1610_GPIO_BANK3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { + .virtual_irq_start = IH_GPIO_BASE + 32, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio3 = { + .name = "omap-gpio", + .id = 3, + .dev = { + .platform_data = &omap16xx_gpio3_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio3_resources), + .resource = omap16xx_gpio3_resources, +}; + +/* + * OMAP16XX GPIO4 interface data + */ +static struct __initdata resource omap16xx_gpio4_resources[] = { + { + .start = OMAP1610_GPIO4_BASE, + .end = OMAP1610_GPIO4_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_1610_GPIO_BANK4, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { + .virtual_irq_start = IH_GPIO_BASE + 48, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio4 = { + .name = "omap-gpio", + .id = 4, + .dev = { + .platform_data = &omap16xx_gpio4_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio4_resources), + .resource = omap16xx_gpio4_resources, +}; + +static struct __initdata platform_device * omap16xx_gpio_dev[] = { + &omap16xx_mpu_gpio, + &omap16xx_gpio1, + &omap16xx_gpio2, + &omap16xx_gpio3, + &omap16xx_gpio4, +}; + +/* + * omap16xx_gpio_init needs to be done before + * machine_init functions access gpio APIs. + * Hence omap16xx_gpio_init is a postcore_initcall. + */ +static int __init omap16xx_gpio_init(void) +{ + int i; + + if (!cpu_is_omap16xx()) + return -EINVAL; + + for (i = 0; i < sizeof(omap16xx_gpio_dev); i++) + platform_device_register(omap16xx_gpio_dev[i]); + + gpio_bank_count = sizeof(omap16xx_gpio_dev); + + return 0; +} +postcore_initcall(omap16xx_gpio_init); From patchwork Wed Jul 21 17:33:45 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113415 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONY007938 for ; Wed, 21 Jul 2010 17:35:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758622Ab0GURfH (ORCPT ); Wed, 21 Jul 2010 13:35:07 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758554Ab0GURfE (ORCPT ); Wed, 21 Jul 2010 13:35:04 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:35:03 -0700 (PDT) Received: by 10.204.141.16 with SMTP id k16mr356544bku.177.1279733701388; Wed, 21 Jul 2010 10:35:01 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:35:00 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 11/20] omap: hsmmc: support mmc3 regulator power control Date: Wed, 21 Jul 2010 20:33:45 +0300 Message-Id: <1279733634-21974-12-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:14 +0000 (UTC) diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 1ef54b0..5d3d789 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -174,7 +174,7 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, } } -static void hsmmc23_before_set_reg(struct device *dev, int slot, +static void hsmmc2_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { struct omap_mmc_platform_data *mmc = dev->platform_data; @@ -325,14 +325,16 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) c->transceiver = 1; if (c->transceiver && c->wires > 4) c->wires = 4; - /* FALLTHROUGH */ - case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* off-chip level shifting, or none */ - mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; + mmc->slots[0].before_set_reg = hsmmc2_before_set_reg; mmc->slots[0].after_set_reg = NULL; } break; + case 3: + mmc->slots[0].before_set_reg = NULL; + mmc->slots[0].after_set_reg = NULL; + break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); kfree(mmc); diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b032828..4c5a669 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -258,7 +258,7 @@ static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, return ret; } -static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, +static int omap_hsmmc_2_set_power(struct device *dev, int slot, int power_on, int vdd) { struct omap_hsmmc_host *host = @@ -309,6 +309,31 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, return ret; } +static int omap_hsmmc_3_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + struct omap_hsmmc_host *host = + platform_get_drvdata(to_platform_device(dev)); + int ret = 0; + + if (power_on) { + ret = mmc_regulator_set_ocr(host->vcc, vdd); + /* Enable interface voltage rail, if needed */ + if (ret == 0 && host->vcc) { + ret = regulator_enable(host->vcc); + if (ret < 0) + ret = mmc_regulator_set_ocr(host->vcc, 0); + } + } else { + if (host->vcc) + ret = regulator_disable(host->vcc); + if (ret == 0) + ret = mmc_regulator_set_ocr(host->vcc, 0); + } + + return ret; +} + static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, int vdd, int cardsleep) { @@ -319,7 +344,7 @@ static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, return regulator_set_mode(host->vcc, mode); } -static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, +static int omap_hsmmc_2_set_sleep(struct device *dev, int slot, int sleep, int vdd, int cardsleep) { struct omap_hsmmc_host *host = @@ -358,6 +383,31 @@ static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, return regulator_enable(host->vcc_aux); } +static int omap_hsmmc_3_set_sleep(struct device *dev, int slot, int sleep, + int vdd, int cardsleep) +{ + struct omap_hsmmc_host *host = + platform_get_drvdata(to_platform_device(dev)); + int err = 0; + + /* + * If we don't see a Vcc regulator, assume it's a fixed + * voltage always-on regulator. + */ + if (!host->vcc) + return 0; + + if (cardsleep) { + /* VCC can be turned off if card is asleep */ + if (sleep) + err = mmc_regulator_set_ocr(host->vcc, 0); + else + err = mmc_regulator_set_ocr(host->vcc, vdd); + } + + return err; +} + static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) { struct regulator *reg; @@ -370,10 +420,13 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; break; case OMAP_MMC2_DEVID: - case OMAP_MMC3_DEVID: /* Off-chip level shifting, or none */ - mmc_slot(host).set_power = omap_hsmmc_23_set_power; - mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; + mmc_slot(host).set_power = omap_hsmmc_2_set_power; + mmc_slot(host).set_sleep = omap_hsmmc_2_set_sleep; + break; + case OMAP_MMC3_DEVID: + mmc_slot(host).set_power = omap_hsmmc_3_set_power; + mmc_slot(host).set_sleep = omap_hsmmc_3_set_sleep; break; default: pr_err("MMC%d configuration not supported!\n", host->id); @@ -386,9 +439,9 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) /* * HACK: until fixed.c regulator is usable, * we don't require a main regulator - * for MMC2 or MMC3 + * for MMC2 */ - if (host->id == OMAP_MMC1_DEVID) { + if (host->id != OMAP_MMC2_DEVID) { ret = PTR_ERR(reg); goto err; } From patchwork Tue Aug 3 19:59:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gadiyar X-Patchwork-Id: 116853 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o73Jxc1T001081 for ; Tue, 3 Aug 2010 19:59:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757616Ab0HCT7e (ORCPT ); Tue, 3 Aug 2010 15:59:34 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:40444 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756207Ab0HCT7e (ORCPT ); Tue, 3 Aug 2010 15:59:34 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o73JxUD7025012 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 3 Aug 2010 14:59:32 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o73JxPHr018560; Wed, 4 Aug 2010 01:29:25 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o73JxPEL006627; Wed, 4 Aug 2010 01:29:25 +0530 Received: (from a0393673@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o73JxOWC006625; Wed, 4 Aug 2010 01:29:24 +0530 From: Anand Gadiyar To: linux-omap@vger.kernel.org Cc: Anand Gadiyar , Nishanth Menon , Manjunatha GK , Tony Lindgren Subject: [PATCH v2] OMAP3630: Add ES1.1 and ES1.2 detection Date: Wed, 4 Aug 2010 01:29:24 +0530 Message-Id: <1280865564-6456-1-git-send-email-gadiyar@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <20100803073940.GS12293@atomide.com> References: <20100803073940.GS12293@atomide.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 03 Aug 2010 19:59:38 +0000 (UTC) Index: linux-2.6/arch/arm/mach-omap2/id.c =================================================================== --- linux-2.6.orig/arch/arm/mach-omap2/id.c +++ linux-2.6/arch/arm/mach-omap2/id.c @@ -261,9 +261,26 @@ void __init omap3_check_revision(void) case 0xb891: /* FALLTHROUGH */ default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; + /* Unknown hawkeye defaults to latest silicon revision */ + + /* Handle 36xx devices */ omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + break; + case 2: + /* Fall through */ + default: + /* Use the latest known revision as default */ + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + } } } @@ -339,6 +356,12 @@ void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; Index: linux-2.6/arch/arm/plat-omap/include/plat/cpu.h =================================================================== --- linux-2.6.orig/arch/arm/plat-omap/include/plat/cpu.h +++ linux-2.6/arch/arm/plat-omap/include/plat/cpu.h @@ -66,6 +66,8 @@ unsigned int omap_rev(void); * family. This difference can be handled separately. */ #define OMAP_REVBITS_00 0x00 +#define OMAP_REVBITS_01 0x01 +#define OMAP_REVBITS_02 0x02 #define OMAP_REVBITS_10 0x10 #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 @@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3430_REV_ES3_1_2 0x34305034 #define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 +#define OMAP3630_REV_ES1_2 0x36300234 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) #define CHIP_IS_OMAP4430ES1 (1 << 8) +#define CHIP_IS_OMAP3630ES1_1 (1 << 9) +#define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517) */ #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ CHIP_IS_OMAP3430ES3_0 | \ - CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) + CHIP_GE_OMAP3430ES3_1) #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) - + CHIP_IS_OMAP3630ES1 | \ + CHIP_GE_OMAP3630ES1_1) +#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ + CHIP_IS_OMAP3630ES1_2) int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); From patchwork Fri Aug 6 15:57:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 117857 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76Fw3HJ020702 for ; Fri, 6 Aug 2010 15:58:03 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761556Ab0HFP6A (ORCPT ); Fri, 6 Aug 2010 11:58:00 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:60977 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761498Ab0HFP57 (ORCPT ); Fri, 6 Aug 2010 11:57:59 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76FvpJn018064 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 10:57:54 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76FvoZN005425; Fri, 6 Aug 2010 21:27:51 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o76Fvo7E004228; Fri, 6 Aug 2010 21:27:50 +0530 Received: (from a0876481@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o76FvoKa004226; Fri, 6 Aug 2010 21:27:50 +0530 From: Hema HK To: linux-usb@vger.kernel.org, linux-omap@vger.kernel.org Cc: Hema HK , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH V2 4/8]usb : musb:Using omap_device_build for musb device registration Date: Fri, 6 Aug 2010 21:27:50 +0530 Message-Id: <1281110270-4185-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 15:58:04 +0000 (UTC) Index: linux-omap-pm/arch/arm/mach-omap2/usb-musb.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/usb-musb.c 2010-08-06 09:01:25.526112352 -0400 +++ linux-omap-pm/arch/arm/mach-omap2/usb-musb.c 2010-08-06 09:01:43.786112839 -0400 @@ -29,24 +29,12 @@ #include #include #include +#include #ifdef CONFIG_USB_MUSB_SOC -static struct resource musb_resources[] = { - [0] = { /* start and end set dynamically */ - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = INT_243X_HS_USB_MC, - .flags = IORESOURCE_IRQ, - .name = "mc", - }, - [2] = { /* DMA IRQ */ - .start = INT_243X_HS_USB_DMA, - .flags = IORESOURCE_IRQ, - .name = "dma", - }, -}; +static const char name[] = "musb_hdrc"; +#define MAX_OMAP_MUSB_HWMOD_NAME_LEN 16 static struct musb_hdrc_config musb_config = { .multipoint = 1, @@ -75,43 +63,61 @@ static u64 musb_dmamask = DMA_BIT_MASK(32); -static struct platform_device musb_device = { - .name = "musb_hdrc", - .id = -1, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, +static struct omap_device_pm_latency omap_musb_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, }; void __init usb_musb_init(struct omap_musb_board_data *board_data) { - if (cpu_is_omap243x()) { - musb_resources[0].start = OMAP243X_HS_BASE; - } else if (cpu_is_omap34xx()) { - musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; - } else if (cpu_is_omap44xx()) { - musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; - musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; - musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; + char oh_name[MAX_OMAP_MUSB_HWMOD_NAME_LEN]; + struct omap_hwmod *oh; + struct omap_device *od; + struct platform_device *pdev; + struct device *dev; + int l, bus_id = -1; + struct musb_hdrc_platform_data *pdata; + + l = snprintf(oh_name, MAX_OMAP_MUSB_HWMOD_NAME_LEN, + "usb_otg_hs"); + WARN(l >= MAX_OMAP_MUSB_HWMOD_NAME_LEN, + "String buffer overflow in MUSB device setup\n"); + + oh = omap_hwmod_lookup(oh_name); + + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + } else { + /* + * REVISIT: This line can be removed once all the platforms + * using musb_core.c have been converted to use use clkdev. + */ + musb_plat.clock = "ick"; + musb_plat.board_data = board_data; + musb_plat.power = board_data->power >> 1; + musb_plat.mode = board_data->mode; + pdata = &musb_plat; + + od = omap_device_build(name, bus_id, oh, pdata, + sizeof(struct musb_hdrc_platform_data), + omap_musb_latency, + ARRAY_SIZE(omap_musb_latency), false); + if (IS_ERR(od)) { + pr_err("Could not build omap_device for %s %s\n", + name, oh_name); + } else { + + pdev = &od->pdev; + dev = &pdev->dev; + get_device(dev); + dev->dma_mask = &musb_dmamask; + dev->coherent_dma_mask = musb_dmamask; + put_device(dev); + } } - musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; - - /* - * REVISIT: This line can be removed once all the platforms using - * musb_core.c have been converted to use use clkdev. - */ - musb_plat.clock = "ick"; - musb_plat.board_data = board_data; - musb_plat.power = board_data->power >> 1; - musb_plat.mode = board_data->mode; - musb_plat.extvbus = board_data->extvbus; - - if (platform_device_register(&musb_device) < 0) - printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); } #else From patchwork Fri Aug 6 15:57:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 117856 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76FvgoD020612 for ; Fri, 6 Aug 2010 15:57:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761554Ab0HFP5i (ORCPT ); Fri, 6 Aug 2010 11:57:38 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:54885 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761550Ab0HFP5h (ORCPT ); Fri, 6 Aug 2010 11:57:37 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76FvVmQ018907 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 10:57:33 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76FvUln005414; Fri, 6 Aug 2010 21:27:30 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o76FvUOG004175; Fri, 6 Aug 2010 21:27:30 +0530 Received: (from a0876481@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o76FvUeR004173; Fri, 6 Aug 2010 21:27:30 +0530 From: Hema HK To: linux-usb@vger.kernel.org, linux-omap@vger.kernel.org Cc: Hema HK , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH 4/8]usb: musb: HWMOD database structures fixes OMAP4 Date: Fri, 6 Aug 2010 21:27:29 +0530 Message-Id: <1281110249-4098-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 15:57:42 +0000 (UTC) Index: linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_44xx_data.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2010-08-06 08:31:45.885868560 -0400 +++ linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2010-08-06 08:35:41.250112281 -0400 @@ -4516,8 +4516,15 @@ */ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { - .sysc_flags = SYSS_MISSING, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, }; static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { @@ -4884,7 +4891,7 @@ /* usb_host_hs class */ /* &omap44xx_usb_host_hs_hwmod, */ /* usb_otg_hs class */ -/* &omap44xx_usb_otg_hs_hwmod, */ + &omap44xx_usb_otg_hs_hwmod, /* usb_tll_hs class */ /* &omap44xx_usb_tll_hs_hwmod, */ /* wd_timer class */ From patchwork Fri Aug 6 15:56:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 117855 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76Fv9xi020523 for ; Fri, 6 Aug 2010 15:57:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759119Ab0HFP5F (ORCPT ); Fri, 6 Aug 2010 11:57:05 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:60922 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754948Ab0HFP5D (ORCPT ); Fri, 6 Aug 2010 11:57:03 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76FupQh017951 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 10:56:54 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76FuoXK005381; Fri, 6 Aug 2010 21:26:50 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o76Fuo8u004029; Fri, 6 Aug 2010 21:26:50 +0530 Received: (from a0876481@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o76FuoDZ004027; Fri, 6 Aug 2010 21:26:50 +0530 From: Hema HK To: linux-usb@vger.kernel.org, linux-omap@vger.kernel.org Cc: Hema HK , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH V2 3/4]usb: musb: HWMOD database structures addition for OMAP3 Date: Fri, 6 Aug 2010 21:26:50 +0530 Message-Id: <1281110210-3961-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 15:57:09 +0000 (UTC) Index: linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2010-08-06 08:31:45.000000000 -0400 +++ linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2010-08-06 08:34:24.761878220 -0400 @@ -82,6 +82,16 @@ }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; +static struct omap_hwmod omap3xxx_usbhsotg_hwmod; + +/* L3 <- USBHSOTG interface */ +static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { + .master = &omap3xxx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -90,6 +100,38 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* +* USBHSOTG interface data +*/ + +static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { + { + .pa_start = OMAP34XX_HSUSB_OTG_BASE, + .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* USBHSOTG <- L4_CORE interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = omap3xxx_usbhsotg_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs), + .user = OCP_USER_MPU, + +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { + &omap3xxx_usbhsotg__l3, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { + &omap3xxx_l4_core__usbhsotg, +}; + + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -197,6 +239,56 @@ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* + * USBHSOTG (USBHS) + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap3xxx_usbhsotg_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, + +}; + +static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs), + .main_clk = "hsotgusb_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_GRPSEL_HSOTGUSB_MASK, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT + }, + }, + .masters = omap3xxx_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), + .slaves = omap3xxx_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), + .class = &usbotg_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +296,7 @@ &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_usbhsotg_hwmod, NULL, }; From patchwork Fri Aug 6 15:56:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 117854 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76FuXID020305 for ; Fri, 6 Aug 2010 15:56:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761547Ab0HFP4b (ORCPT ); Fri, 6 Aug 2010 11:56:31 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:36387 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754948Ab0HFP43 (ORCPT ); Fri, 6 Aug 2010 11:56:29 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76FuKGs029628 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 10:56:23 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76FuJ8A005368; Fri, 6 Aug 2010 21:26:19 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o76FuJK1003947; Fri, 6 Aug 2010 21:26:19 +0530 Received: (from a0876481@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o76FuJeK003945; Fri, 6 Aug 2010 21:26:19 +0530 From: Hema HK To: linux-usb@vger.kernel.org, linux-omap@vger.kernel.org Cc: Hema HK , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH 2/8] usb: musb: Remove board_data parameter from musb_platform_init() Date: Fri, 6 Aug 2010 21:26:19 +0530 Message-Id: <1281110179-3793-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 15:56:34 +0000 (UTC) Index: linux-omap-pm/drivers/usb/musb/blackfin.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/blackfin.c 2010-08-06 09:01:19.805863959 -0400 +++ linux-omap-pm/drivers/usb/musb/blackfin.c 2010-08-06 09:01:30.721863471 -0400 @@ -323,7 +323,7 @@ return -EIO; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { /* Index: linux-omap-pm/drivers/usb/musb/davinci.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/davinci.c 2010-08-06 09:01:19.821862599 -0400 +++ linux-omap-pm/drivers/usb/musb/davinci.c 2010-08-06 09:01:30.721863471 -0400 @@ -376,7 +376,7 @@ return -EIO; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { void __iomem *tibase = musb->ctrl_base; u32 revision; Index: linux-omap-pm/drivers/usb/musb/musb_core.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/musb_core.c 2010-08-06 09:01:25.530112841 -0400 +++ linux-omap-pm/drivers/usb/musb/musb_core.c 2010-08-06 09:01:30.721863471 -0400 @@ -2023,7 +2023,7 @@ * isp1504, non-OTG, etc) mostly hooking up through ULPI. */ musb->isr = generic_interrupt; - status = musb_platform_init(musb, plat->board_data); + status = musb_platform_init(musb); if (status < 0) goto fail2; Index: linux-omap-pm/drivers/usb/musb/musb_core.h =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/musb_core.h 2010-08-06 09:01:19.785863497 -0400 +++ linux-omap-pm/drivers/usb/musb/musb_core.h 2010-08-06 09:01:30.721863471 -0400 @@ -612,7 +612,7 @@ #define musb_platform_get_vbus_status(x) 0 #endif -extern int __init musb_platform_init(struct musb *musb, void *board_data); +extern int __init musb_platform_init(struct musb *musb); extern int musb_platform_exit(struct musb *musb); #endif /* __MUSB_CORE_H__ */ Index: linux-omap-pm/drivers/usb/musb/omap2430.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/omap2430.c 2010-08-06 09:01:19.793863369 -0400 +++ linux-omap-pm/drivers/usb/musb/omap2430.c 2010-08-06 09:01:30.721863471 -0400 @@ -189,10 +189,12 @@ return 0; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { u32 l; - struct omap_musb_board_data *data = board_data; + struct device *dev = musb->controller; + struct musb_hdrc_platform_data *plat = dev->platform_data; + struct omap_musb_board_data *data = plat->board_data; #if defined(CONFIG_ARCH_OMAP2430) omap_cfg_reg(AE5_2430_USB0HS_STP); Index: linux-omap-pm/drivers/usb/musb/tusb6010.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/tusb6010.c 2010-08-06 09:01:19.813862848 -0400 +++ linux-omap-pm/drivers/usb/musb/tusb6010.c 2010-08-06 09:01:30.721863471 -0400 @@ -1091,7 +1091,7 @@ return -ENODEV; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { struct platform_device *pdev; struct resource *mem; From patchwork Wed Aug 4 10:51:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 116991 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74ApHF2016402 for ; Wed, 4 Aug 2010 10:51:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932618Ab0HDKvP (ORCPT ); Wed, 4 Aug 2010 06:51:15 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:58527 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932295Ab0HDKvO (ORCPT ); Wed, 4 Aug 2010 06:51:14 -0400 Received: from muru.com ([72.249.23.125] helo=localhost.localdomain) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OgbZ3-000BbA-3L; Wed, 04 Aug 2010 10:51:13 +0000 Received: from Mutt by mutt-smtp-wrapper.pl 1.2 (www.zdo.com/articles/mutt-smtp-wrapper.shtml) X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1/eAqhKqCfc65j/eedTeY3o Date: Wed, 4 Aug 2010 13:51:39 +0300 From: Tony Lindgren To: Anand Gadiyar Cc: linux-omap@vger.kernel.org, Nishanth Menon , Manjunatha GK Subject: Re: [PATCH v2] OMAP3630: Add ES1.1 and ES1.2 detection Message-ID: <20100804105138.GJ9881@atomide.com> References: <20100803073940.GS12293@atomide.com> <1280865564-6456-1-git-send-email-gadiyar@ti.com> <20100804103029.GI9881@atomide.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20100804103029.GI9881@atomide.com> User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 10:51:24 +0000 (UTC) From 03323e6ae5e93e32aad9005b252f5b7125b39564 Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Tue, 3 Aug 2010 19:59:24 +0000 Subject: [PATCH] OMAP3630: Add ES1.1 and ES1.2 detection Add revision detection for ES1.1 and ES1.2. Set default revision as ES1.2. Add CHIP_GE_OMAP3630ES1_1 to detect revisions 1.1 and later. This is needed for at least one feature that is broken in 3630ES1.0 but exists on older (3430 ES3.1) and newer revisions. Additionally, update some of the CHIP_GE_* macros to use other macros for ease of maintenance. Signed-off-by: Anand Gadiyar Cc: Nishanth Menon Cc: Manjunatha GK [tony@atomide.com: update fallthrough handling] Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index fd1904b..0a0ff0c 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -269,11 +269,29 @@ static void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; break; case 0xb891: + /* Handle 36xx devices */ + omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + break; + case 2: + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + break; + default: + /* FALLTHROUGH */ + } /* FALLTHROUGH */ default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP3630ES1; + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; } } @@ -349,6 +367,12 @@ static void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index aa2f4f0..2e2ae53 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -66,6 +66,8 @@ unsigned int omap_rev(void); * family. This difference can be handled separately. */ #define OMAP_REVBITS_00 0x00 +#define OMAP_REVBITS_01 0x01 +#define OMAP_REVBITS_02 0x02 #define OMAP_REVBITS_10 0x10 #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 @@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3430_REV_ES3_1_2 0x34305034 #define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 +#define OMAP3630_REV_ES1_2 0x36300234 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) #define CHIP_IS_OMAP4430ES1 (1 << 8) +#define CHIP_IS_OMAP3630ES1_1 (1 << 9) +#define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517) */ #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ CHIP_IS_OMAP3430ES3_0 | \ - CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) + CHIP_GE_OMAP3430ES3_1) #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) - + CHIP_IS_OMAP3630ES1 | \ + CHIP_GE_OMAP3630ES1_1) +#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ + CHIP_IS_OMAP3630ES1_2) int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); From patchwork Tue Jun 22 15:01:45 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107403 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF1XKi017599 for ; Tue, 22 Jun 2010 15:01:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758695Ab0FVPBb (ORCPT ); Tue, 22 Jun 2010 11:01:31 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41817 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756450Ab0FVPB2 (ORCPT ); Tue, 22 Jun 2010 11:01:28 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1MTl024610 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:25 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZi026711; Tue, 22 Jun 2010 20:31:20 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 02/13] OMAP: GPIO: Populate GPIO base address in omapxxxx.h Date: Tue, 22 Jun 2010 20:31:45 +0530 Message-Id: <1277218916-15213-3-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-2-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:33 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h index 7055672..4406bbe 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/plat-omap/include/plat/omap24xx.h @@ -85,5 +85,17 @@ #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) +/* GPIO controller*/ +#define OMAP242X_GPIO1_BASE (L4_24XX_BASE + 0x18000) +#define OMAP242X_GPIO2_BASE (L4_24XX_BASE + 0x1a000) +#define OMAP242X_GPIO3_BASE (L4_24XX_BASE + 0x1c000) +#define OMAP242X_GPIO4_BASE (L4_24XX_BASE + 0x1e000) + +#define OMAP243X_GPIO1_BASE (L4_WK_243X_BASE + 0xC000) +#define OMAP243X_GPIO2_BASE (L4_WK_243X_BASE + 0xE000) +#define OMAP243X_GPIO3_BASE (L4_WK_243X_BASE + 0x10000) +#define OMAP243X_GPIO4_BASE (L4_WK_243X_BASE + 0x12000) +#define OMAP243X_GPIO5_BASE (L4_24XX_BASE + 0xB6000) + #endif /* __ASM_ARCH_OMAP2_H */ diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index 98fc8b4..53279b8 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h @@ -87,5 +87,13 @@ #define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000) #define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000) +/* GPIO controller*/ +#define OMAP34XX_GPIO1_BASE (L4_WK_34XX_BASE + 0x10000) +#define OMAP34XX_GPIO2_BASE (L4_PER_34XX_BASE + 0x50000) +#define OMAP34XX_GPIO3_BASE (L4_PER_34XX_BASE + 0x52000) +#define OMAP34XX_GPIO4_BASE (L4_PER_34XX_BASE + 0x54000) +#define OMAP34XX_GPIO5_BASE (L4_PER_34XX_BASE + 0x56000) +#define OMAP34XX_GPIO6_BASE (L4_PER_34XX_BASE + 0x58000) + #endif /* __ASM_ARCH_OMAP3_H */ diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index 8b3f12f..bec7d69 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -52,5 +52,13 @@ #define OMAP4_MMU1_BASE 0x55082000 #define OMAP4_MMU2_BASE 0x4A066000 +/* GPIO controller*/ +#define OMAP44XX_GPIO1_BASE (L4_WK_44XX_BASE + 0x10000) +#define OMAP44XX_GPIO2_BASE (L4_PER_44XX_BASE + 0x55000) +#define OMAP44XX_GPIO3_BASE (L4_PER_44XX_BASE + 0x57000) +#define OMAP44XX_GPIO4_BASE (L4_PER_44XX_BASE + 0x59000) +#define OMAP44XX_GPIO5_BASE (L4_PER_44XX_BASE + 0x5B000) +#define OMAP44XX_GPIO6_BASE (L4_PER_44XX_BASE + 0x5D000) + #endif /* __ASM_ARCH_OMAP44XX_H */ From patchwork Wed Aug 4 11:06:45 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 116992 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74B6KtH018857 for ; Wed, 4 Aug 2010 11:06:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932381Ab0HDLGU (ORCPT ); Wed, 4 Aug 2010 07:06:20 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:55285 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932201Ab0HDLGT (ORCPT ); Wed, 4 Aug 2010 07:06:19 -0400 Received: from muru.com ([72.249.23.125] helo=localhost.localdomain) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1Ogbne-000HeC-Me; Wed, 04 Aug 2010 11:06:19 +0000 Received: from Mutt by mutt-smtp-wrapper.pl 1.2 (www.zdo.com/articles/mutt-smtp-wrapper.shtml) X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19K5PoWr/RtbXMgc+W3sbc8 Date: Wed, 4 Aug 2010 14:06:45 +0300 From: Tony Lindgren To: Anand Gadiyar Cc: linux-omap@vger.kernel.org, Nishanth Menon , Manjunatha GK Subject: Re: [PATCH v2] OMAP3630: Add ES1.1 and ES1.2 detection Message-ID: <20100804110644.GK9881@atomide.com> References: <20100803073940.GS12293@atomide.com> <1280865564-6456-1-git-send-email-gadiyar@ti.com> <20100804103029.GI9881@atomide.com> <20100804105138.GJ9881@atomide.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20100804105138.GJ9881@atomide.com> User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 11:06:21 +0000 (UTC) From 9c6484502a8aba4b7a0f1f3ca847557d52a9350b Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Tue, 3 Aug 2010 19:59:24 +0000 Subject: [PATCH] OMAP3630: Add ES1.1 and ES1.2 detection Add revision detection for ES1.1 and ES1.2. Set default revision as ES1.2. Add CHIP_GE_OMAP3630ES1_1 to detect revisions 1.1 and later. This is needed for at least one feature that is broken in 3630ES1.0 but exists on older (3430 ES3.1) and newer revisions. Additionally, update some of the CHIP_GE_* macros to use other macros for ease of maintenance. Signed-off-by: Anand Gadiyar Cc: Nishanth Menon Cc: Manjunatha GK [tony@atomide.com: update fallthrough handling] Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index fd1904b..e8256a2 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -269,11 +269,27 @@ static void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; break; case 0xb891: - /* FALLTHROUGH */ + /* Handle 36xx devices */ + omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + break; + case 2: + default: + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + break; + } default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP3630ES1; + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; } } @@ -349,6 +365,12 @@ static void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index aa2f4f0..2e2ae53 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -66,6 +66,8 @@ unsigned int omap_rev(void); * family. This difference can be handled separately. */ #define OMAP_REVBITS_00 0x00 +#define OMAP_REVBITS_01 0x01 +#define OMAP_REVBITS_02 0x02 #define OMAP_REVBITS_10 0x10 #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 @@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3430_REV_ES3_1_2 0x34305034 #define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 +#define OMAP3630_REV_ES1_2 0x36300234 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) #define CHIP_IS_OMAP4430ES1 (1 << 8) +#define CHIP_IS_OMAP3630ES1_1 (1 << 9) +#define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517) */ #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ CHIP_IS_OMAP3430ES3_0 | \ - CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) + CHIP_GE_OMAP3430ES3_1) #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) - + CHIP_IS_OMAP3630ES1 | \ + CHIP_GE_OMAP3630ES1_1) +#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ + CHIP_IS_OMAP3630ES1_2) int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); From patchwork Fri Mar 12 15:39:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 85269 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2CDshL1000493 for ; Fri, 12 Mar 2010 13:54:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757973Ab0CLNyo (ORCPT ); Fri, 12 Mar 2010 08:54:44 -0500 Received: from smtp.nokia.com ([192.100.105.134]:53982 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757705Ab0CLNym (ORCPT ); Fri, 12 Mar 2010 08:54:42 -0500 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CDrxZ7008613 for ; Fri, 12 Mar 2010 07:54:41 -0600 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 15:54:40 +0200 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 15:54:40 +0200 Received: from localhost.localdomain (sokoban.nmp.nokia.com [172.22.215.13]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CDsV8n003701 for ; Fri, 12 Mar 2010 15:54:37 +0200 From: Tero Kristo To: linux-omap@vger.kernel.org Subject: [PATCHv7 6/7] OMAP3: PM: Moved pwrdm state control logic from omap_sram_idle to cpuidle Date: Fri, 12 Mar 2010 17:39:16 +0200 Message-Id: <1268408357-15621-6-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1268408357-15621-5-git-send-email-tero.kristo@nokia.com> References: <> <1268408357-15621-1-git-send-email-tero.kristo@nokia.com> <1268408357-15621-2-git-send-email-tero.kristo@nokia.com> <1268408357-15621-3-git-send-email-tero.kristo@nokia.com> <1268408357-15621-4-git-send-email-tero.kristo@nokia.com> <1268408357-15621-5-git-send-email-tero.kristo@nokia.com> X-OriginalArrivalTime: 12 Mar 2010 13:54:40.0635 (UTC) FILETIME=[8FBAF4B0:01CAC1EB] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 12 Mar 2010 13:54:47 +0000 (UTC) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 9445e1e..c3f2e03 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -60,7 +60,8 @@ struct omap3_processor_cx { struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; -struct powerdomain *mpu_pd, *core_pd; +static struct powerdomain *mpu_pd, *core_pd, *per_pd, *iva2_pd; +static struct powerdomain *sgx_pd, *usb_pd, *cam_pd, *dss_pd; /* * The latencies/thresholds for various C states have @@ -209,14 +210,96 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_state *state) { struct cpuidle_state *new_state = next_valid_state(dev, state); + u32 per_state = 0, saved_per_state = 0, cam_state, usb_state; + u32 iva2_state, sgx_state, dss_state, new_core_state; + struct omap3_processor_cx *cx; + int ret; + + if (state->flags & CPUIDLE_FLAG_CHECK_BM) { + if (omap3_idle_bm_check()) { + BUG_ON(!dev->safe_state); + new_state = dev->safe_state; + goto select_state; + } + cx = cpuidle_get_statedata(state); + new_core_state = cx->core_state; + + /* Check if CORE is active, if yes, fallback to inactive */ + if (!pwrdm_can_idle(core_pd)) + new_core_state = PWRDM_POWER_INACTIVE; + + /* + * Prevent idle completely if CAM is active. + * CAM does not have wakeup capability in OMAP3. + */ + cam_state = pwrdm_read_pwrst(cam_pd); + if (cam_state == PWRDM_POWER_ON) { + new_state = dev->safe_state; + goto select_state; + } + + /* + * Check if PER can idle or not. If we are not likely + * to idle, deny PER off. This prevents unnecessary + * context save/restore. + */ + saved_per_state = omap3_pwrdm_read_next_pwrst(per_pd); + if (pwrdm_can_idle(per_pd)) { + per_state = saved_per_state; + /* + * Prevent PER off if CORE is active as this + * would disable PER wakeups completely + */ + if (per_state == PWRDM_POWER_OFF && + new_core_state > PWRDM_POWER_RET) + per_state = PWRDM_POWER_RET; + + } else if (saved_per_state == PWRDM_POWER_OFF) + per_state = PWRDM_POWER_RET; + else + per_state = saved_per_state; + + /* + * If we are attempting CORE off, check if any other + * powerdomains are at retention or higher. CORE off causes + * chipwide reset which would reset these domains also. + */ + if (new_core_state == PWRDM_POWER_OFF) { + dss_state = pwrdm_read_pwrst(dss_pd); + iva2_state = pwrdm_read_pwrst(iva2_pd); + sgx_state = pwrdm_read_pwrst(sgx_pd); + usb_state = pwrdm_read_pwrst(usb_pd); + + if (cam_state > PWRDM_POWER_OFF || + dss_state > PWRDM_POWER_OFF || + iva2_state > PWRDM_POWER_OFF || + per_state > PWRDM_POWER_OFF || + sgx_state > PWRDM_POWER_OFF || + usb_state > PWRDM_POWER_OFF) + new_core_state = PWRDM_POWER_RET; + } - if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { - BUG_ON(!dev->safe_state); - new_state = dev->safe_state; + /* Fallback to new target core state */ + while (cx->core_state < new_core_state) { + state--; + cx = cpuidle_get_statedata(state); + } + new_state = state; + + /* Are we changing PER target state? */ + if (per_state != saved_per_state) + omap3_pwrdm_set_next_pwrst(per_pd, per_state); } +select_state: dev->last_state = new_state; - return omap3_enter_idle(dev, new_state); + ret = omap3_enter_idle(dev, new_state); + + /* Restore potentially tampered PER state */ + if (per_state != saved_per_state) + omap3_pwrdm_set_next_pwrst(per_pd, saved_per_state); + + return ret; } DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); @@ -304,7 +387,8 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].threshold; omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_INACTIVE; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; /* C3 . MPU CSWR + Core inactive */ omap3_power_states[OMAP3_STATE_C3].valid = @@ -402,6 +486,12 @@ int __init omap3_idle_init(void) mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); + per_pd = pwrdm_lookup("per_pwrdm"); + iva2_pd = pwrdm_lookup("iva2_pwrdm"); + sgx_pd = pwrdm_lookup("sgx_pwrdm"); + usb_pd = pwrdm_lookup("usbhost_pwrdm"); + cam_pd = pwrdm_lookup("cam_pwrdm"); + dss_pd = pwrdm_lookup("dss_pwrdm"); omap_init_power_states(); cpuidle_register_driver(&omap3_idle_driver); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index f1f1932..78b0926 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -93,7 +93,6 @@ static int (*_omap_save_secure_sram)(u32 *addr); static struct powerdomain *mpu_pwrdm, *neon_pwrdm; static struct powerdomain *core_pwrdm, *per_pwrdm; -static struct powerdomain *cam_pwrdm; static struct prm_setup_vc prm_setup = { .clksetup = 0xff, @@ -373,7 +372,6 @@ void omap_sram_idle(void) int core_next_state = PWRDM_POWER_ON; int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; - int per_state_modified = 0; if (!_omap_sram_idle) return; @@ -411,20 +409,11 @@ void omap_sram_idle(void) core_next_state = omap3_pwrdm_read_next_pwrst(core_pwrdm); if (per_next_state < PWRDM_POWER_ON) { omap2_gpio_prepare_for_idle(per_next_state); - if (per_next_state == PWRDM_POWER_OFF) { - if (core_next_state == PWRDM_POWER_ON) { - per_next_state = PWRDM_POWER_RET; - pwrdm_set_next_pwrst(per_pwrdm, per_next_state); - per_state_modified = 1; - } else - omap3_per_save_context(); - } + if (per_next_state == PWRDM_POWER_OFF) + omap3_per_save_context(); omap_uart_prepare_idle(2); } - if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) - omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); - /* * Disable smartreflex before entering WFI. * Only needed if we are going to enter retention or off. @@ -554,8 +543,6 @@ void omap_sram_idle(void) } omap2_gpio_resume_after_idle(); omap_uart_resume_idle(2); - if (per_state_modified) - pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); } /* Disable IO-PAD and IO-CHAIN wakeup */ @@ -564,7 +551,6 @@ void omap_sram_idle(void) omap3_disable_io_chain(); } - pwrdm_post_transition(); } @@ -1248,7 +1234,6 @@ static int __init omap3_pm_init(void) neon_pwrdm = pwrdm_lookup("neon_pwrdm"); per_pwrdm = pwrdm_lookup("per_pwrdm"); core_pwrdm = pwrdm_lookup("core_pwrdm"); - cam_pwrdm = pwrdm_lookup("cam_pwrdm"); neon_clkdm = clkdm_lookup("neon_clkdm"); mpu_clkdm = clkdm_lookup("mpu_clkdm"); From patchwork Thu Jul 1 13:40:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Afzal Mohammed X-Patchwork-Id: 109114 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o61DfnJQ026312 for ; Thu, 1 Jul 2010 13:41:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754481Ab0GANkw (ORCPT ); Thu, 1 Jul 2010 09:40:52 -0400 Received: from mail-pv0-f174.google.com ([74.125.83.174]:41466 "EHLO mail-pv0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751941Ab0GANkv (ORCPT ); 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Thu, 01 Jul 2010 06:40:49 -0700 (PDT) From: Afzal Mohammed To: tomi.valkeinen@nokia.com Cc: ville.syrjala@nokia.com, tj@kernel.org, lazfamam@gmail.com, linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] OMAP:DSS2:OMAPFB: Fix probe error path Date: Thu, 1 Jul 2010 19:10:01 +0530 Message-Id: <1277991601-16528-2-git-send-email-lazfamam@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1277991601-16528-1-git-send-email-lazfamam@gmail.com> References: <1277991601-16528-1-git-send-email-lazfamam@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 13:41:49 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 4b4506d..710e117 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -1928,13 +1928,6 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev) } } - DBG("create sysfs for fbs\n"); - r = omapfb_create_sysfs(fbdev); - if (r) { - dev_err(fbdev->dev, "failed to create sysfs entries\n"); - return r; - } - /* Enable fb0 */ if (fbdev->num_fbs > 0) { struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]); @@ -2220,6 +2213,13 @@ static int omapfb_probe(struct platform_device *pdev) } } + DBG("create sysfs for fbs\n"); + r = omapfb_create_sysfs(fbdev); + if (r) { + dev_err(fbdev->dev, "failed to create sysfs entries\n"); + goto cleanup; + } + return 0; cleanup: From patchwork Wed Mar 17 22:46:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ville.syrjala@nokia.com X-Patchwork-Id: 86569 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2HMkvMs022445 for ; Wed, 17 Mar 2010 22:46:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756262Ab0CQWq4 (ORCPT ); Wed, 17 Mar 2010 18:46:56 -0400 Received: from smtp.nokia.com ([192.100.105.134]:63357 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756226Ab0CQWqz (ORCPT ); Wed, 17 Mar 2010 18:46:55 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2HMkrZp002157; Wed, 17 Mar 2010 17:46:54 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:52 +0200 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:52 +0200 Received: from stinkpad (esdhcp04093.research.nokia.com [172.21.40.93]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with SMTP id o2HMknuY011443; Thu, 18 Mar 2010 00:46:50 +0200 Received: by stinkpad (sSMTP sendmail emulation); Thu, 18 Mar 2010 00:46:49 +0200 From: ville.syrjala@nokia.com To: "Tomi Valkeinen" Cc: "Imre Deak" , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Subject: [PATCH v4 7/8] DSS2: OMAPFB: Make lockdep happy Date: Thu, 18 Mar 2010 00:46:22 +0200 Message-Id: <1268865983-16270-8-git-send-email-ville.syrjala@nokia.com> X-Mailer: git-send-email 1.6.4.4 In-Reply-To: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> References: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> MIME-Version: 1.0 X-OriginalArrivalTime: 17 Mar 2010 22:46:52.0403 (UTC) FILETIME=[BC9CD430:01CAC623] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Mar 2010 22:46:58 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c index 4d5e5af..a3681da 100644 --- a/drivers/video/omap2/omapfb/omapfb-ioctl.c +++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c @@ -55,7 +55,7 @@ static struct omapfb2_mem_region *get_mem_region(struct omapfb_info *ofbi, if (mem_idx >= fbdev->num_fbs) return NULL; - return omapfb_get_mem_region(&fbdev->regions[mem_idx]); + return &fbdev->regions[mem_idx]; } static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) @@ -77,20 +77,30 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) /* XXX uses only the first overlay */ ovl = ofbi->overlays[0]; - old_rg = omapfb_get_mem_region(ofbi->region); + old_rg = ofbi->region; new_rg = get_mem_region(ofbi, pi->mem_idx); if (!new_rg) { r = -EINVAL; - goto put_old; + goto out; } + /* Take the locks in a specific order to keep lockdep happy */ + if (old_rg->id < new_rg->id) { + omapfb_get_mem_region(old_rg); + omapfb_get_mem_region(new_rg); + } else if (new_rg->id < old_rg->id) { + omapfb_get_mem_region(new_rg); + omapfb_get_mem_region(old_rg); + } else + omapfb_get_mem_region(old_rg); + if (pi->enabled && !new_rg->size) { /* * This plane's memory was freed, can't enable it * until it's reallocated. */ r = -EINVAL; - goto put_new; + goto put_mem; } ovl->get_overlay_info(ovl, &old_info); @@ -135,8 +145,15 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) if (ovl->manager) ovl->manager->apply(ovl->manager); - omapfb_put_mem_region(new_rg); - omapfb_put_mem_region(old_rg); + /* Release the locks in a specific order to keep lockdep happy */ + if (old_rg->id > new_rg->id) { + omapfb_put_mem_region(old_rg); + omapfb_put_mem_region(new_rg); + } else if (new_rg->id > old_rg->id) { + omapfb_put_mem_region(new_rg); + omapfb_put_mem_region(old_rg); + } else + omapfb_put_mem_region(old_rg); return 0; @@ -147,10 +164,16 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) } ovl->set_overlay_info(ovl, &old_info); - put_new: - omapfb_put_mem_region(new_rg); - put_old: - omapfb_put_mem_region(old_rg); + put_mem: + /* Release the locks in a specific order to keep lockdep happy */ + if (old_rg->id > new_rg->id) { + omapfb_put_mem_region(old_rg); + omapfb_put_mem_region(new_rg); + } else if (new_rg->id > old_rg->id) { + omapfb_put_mem_region(new_rg); + omapfb_put_mem_region(old_rg); + } else + omapfb_put_mem_region(old_rg); out: dev_err(fbdev->dev, "setup_plane failed\n"); @@ -198,7 +221,7 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) rg = ofbi->region; - down_write(&rg->lock); + down_write_nested(&rg->lock, rg->id); if (atomic_read(&rg->map_count)) { r = -EBUSY; diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c index aa22f7b..1b7cf57 100644 --- a/drivers/video/omap2/omapfb/omapfb-sysfs.c +++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c @@ -445,7 +445,7 @@ static ssize_t store_size(struct device *dev, struct device_attribute *attr, rg = ofbi->region; - down_write(&rg->lock); + down_write_nested(&rg->lock, rg->id); if (atomic_read(&rg->map_count)) { r = -EBUSY; diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h index 195a760..676b55d 100644 --- a/drivers/video/omap2/omapfb/omapfb.h +++ b/drivers/video/omap2/omapfb/omapfb.h @@ -165,7 +165,7 @@ static inline int omapfb_overlay_enable(struct omap_overlay *ovl, static inline struct omapfb2_mem_region * omapfb_get_mem_region(struct omapfb2_mem_region *rg) { - down_read(&rg->lock); + down_read_nested(&rg->lock, rg->id); return rg; } From patchwork Wed Mar 17 22:46:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ville.syrjala@nokia.com X-Patchwork-Id: 86568 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2HMkt4R022429 for ; Wed, 17 Mar 2010 22:46:55 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756251Ab0CQWqy (ORCPT ); Wed, 17 Mar 2010 18:46:54 -0400 Received: from smtp.nokia.com ([192.100.122.233]:28635 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756226Ab0CQWqw (ORCPT ); Wed, 17 Mar 2010 18:46:52 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2HMk6Nf030520; Thu, 18 Mar 2010 00:46:50 +0200 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:46 +0200 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:46 +0200 Received: from stinkpad (esdhcp04093.research.nokia.com [172.21.40.93]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with SMTP id o2HMkh95010948; Thu, 18 Mar 2010 00:46:44 +0200 Received: by stinkpad (sSMTP sendmail emulation); Thu, 18 Mar 2010 00:46:43 +0200 From: ville.syrjala@nokia.com To: "Tomi Valkeinen" Cc: "Imre Deak" , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Subject: [PATCH v4 5/8] DSS2: OMAPFB: Add locking for memory regions Date: Thu, 18 Mar 2010 00:46:20 +0200 Message-Id: <1268865983-16270-6-git-send-email-ville.syrjala@nokia.com> X-Mailer: git-send-email 1.6.4.4 In-Reply-To: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> References: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> MIME-Version: 1.0 X-OriginalArrivalTime: 17 Mar 2010 22:46:46.0227 (UTC) FILETIME=[B8EE7230:01CAC623] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Mar 2010 22:46:55 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c index a160a3e..f02b1b0 100644 --- a/drivers/video/omap2/omapfb/omapfb-ioctl.c +++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c @@ -55,7 +55,7 @@ static struct omapfb2_mem_region *get_mem_region(struct omapfb_info *ofbi, if (mem_idx >= fbdev->num_fbs) return NULL; - return &fbdev->regions[mem_idx]; + return omapfb_get_mem_region(&fbdev->regions[mem_idx]); } static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) @@ -77,11 +77,11 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) /* XXX uses only the first overlay */ ovl = ofbi->overlays[0]; - old_rg = ofbi->region; + old_rg = omapfb_get_mem_region(ofbi->region); new_rg = get_mem_region(ofbi, pi->mem_idx); if (!new_rg) { r = -EINVAL; - goto out; + goto put_old; } if (pi->enabled && !new_rg->size) { @@ -90,7 +90,7 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) * until it's reallocated. */ r = -EINVAL; - goto out; + goto put_new; } ovl->get_overlay_info(ovl, &old_info); @@ -135,6 +135,9 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) if (ovl->manager) ovl->manager->apply(ovl->manager); + omapfb_put_mem_region(new_rg); + omapfb_put_mem_region(old_rg); + return 0; undo: @@ -144,6 +147,10 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) } ovl->set_overlay_info(ovl, &old_info); + put_new: + omapfb_put_mem_region(new_rg); + put_old: + omapfb_put_mem_region(old_rg); out: dev_err(fbdev->dev, "setup_plane failed\n"); @@ -181,7 +188,7 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) struct omapfb_info *ofbi = FB2OFB(fbi); struct omapfb2_device *fbdev = ofbi->fbdev; struct omapfb2_mem_region *rg; - int r, i; + int r = 0, i; size_t size; if (mi->type > OMAPFB_MEMTYPE_MAX) @@ -191,8 +198,18 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) rg = ofbi->region; - if (atomic_read(&rg->map_count)) - return -EBUSY; + /* FIXME probably should be a rwsem ... */ + mutex_lock(&rg->mtx); + while (rg->ref) { + mutex_unlock(&rg->mtx); + schedule(); + mutex_lock(&rg->mtx); + } + + if (atomic_read(&rg->map_count)) { + r = -EBUSY; + goto out; + } for (i = 0; i < fbdev->num_fbs; i++) { struct omapfb_info *ofbi2 = FB2OFB(fbdev->fbs[i]); @@ -204,7 +221,7 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) for (j = 0; j < ofbi2->num_overlays; j++) { if (ofbi2->overlays[j]->info.enabled) { r = -EBUSY; - return r; + goto out; } } } @@ -213,11 +230,14 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) r = omapfb_realloc_fbmem(fbi, size, mi->type); if (r) { dev_err(fbdev->dev, "realloc fbmem failed\n"); - return r; + goto out; } } - return 0; + out: + mutex_unlock(&rg->mtx); + + return r; } static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) @@ -225,12 +245,14 @@ static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) struct omapfb_info *ofbi = FB2OFB(fbi); struct omapfb2_mem_region *rg; - rg = ofbi->region; + rg = omapfb_get_mem_region(ofbi->region); memset(mi, 0, sizeof(*mi)); mi->size = rg->size; mi->type = rg->type; + omapfb_put_mem_region(rg); + return 0; } diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index ceb7d92..d330032 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -1018,36 +1018,48 @@ err: * DO NOT MODIFY PAR */ static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) { + struct omapfb_info *ofbi = FB2OFB(fbi); int r; DBG("check_var(%d)\n", FB2OFB(fbi)->id); + omapfb_get_mem_region(ofbi->region); + r = check_fb_var(fbi, var); + omapfb_put_mem_region(ofbi->region); + return r; } /* set the video mode according to info->var */ static int omapfb_set_par(struct fb_info *fbi) { + struct omapfb_info *ofbi = FB2OFB(fbi); int r; DBG("set_par(%d)\n", FB2OFB(fbi)->id); + omapfb_get_mem_region(ofbi->region); + set_fb_fix(fbi); r = setup_vrfb_rotation(fbi); if (r) - return r; + goto out; r = omapfb_apply_changes(fbi, 0); + out: + omapfb_put_mem_region(ofbi->region); + return r; } static int omapfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi) { + struct omapfb_info *ofbi = FB2OFB(fbi); struct fb_var_screeninfo new_var; int r; @@ -1063,8 +1075,12 @@ static int omapfb_pan_display(struct fb_var_screeninfo *var, fbi->var = new_var; + omapfb_get_mem_region(ofbi->region); + r = omapfb_apply_changes(fbi, 0); + omapfb_put_mem_region(ofbi->region); + return r; } @@ -1072,14 +1088,18 @@ static void mmap_user_open(struct vm_area_struct *vma) { struct omapfb2_mem_region *rg = vma->vm_private_data; + omapfb_get_mem_region(rg); atomic_inc(&rg->map_count); + omapfb_put_mem_region(rg); } static void mmap_user_close(struct vm_area_struct *vma) { struct omapfb2_mem_region *rg = vma->vm_private_data; + omapfb_get_mem_region(rg); atomic_dec(&rg->map_count); + omapfb_put_mem_region(rg); } static struct vm_operations_struct mmap_user_ops = { @@ -1095,6 +1115,7 @@ static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma) unsigned long off; unsigned long start; u32 len; + int r = -EINVAL; if (vma->vm_end - vma->vm_start == 0) return 0; @@ -1102,14 +1123,14 @@ static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma) return -EINVAL; off = vma->vm_pgoff << PAGE_SHIFT; - rg = ofbi->region; + rg = omapfb_get_mem_region(ofbi->region); start = omapfb_get_region_paddr(ofbi); len = fix->smem_len; if (off >= len) - return -EINVAL; + goto error; if ((vma->vm_end - vma->vm_start + off) > len) - return -EINVAL; + goto error; off += start; @@ -1121,11 +1142,23 @@ static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma) vma->vm_ops = &mmap_user_ops; vma->vm_private_data = rg; if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, - vma->vm_end - vma->vm_start, vma->vm_page_prot)) - return -EAGAIN; + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) { + r = -EAGAIN; + goto error; + } + /* vm_ops.open won't be called for mmap itself. */ atomic_inc(&rg->map_count); + + omapfb_put_mem_region(rg); + return 0; + + error: + omapfb_put_mem_region(ofbi->region); + + return r; } /* Store a single color palette entry into a pseudo palette or the hardware @@ -1896,6 +1929,7 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev) ofbi->region = &fbdev->regions[i]; ofbi->region->id = i; + mutex_init(&ofbi->region->mtx); /* assign these early, so that fb alloc can use them */ ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB : @@ -1926,7 +1960,13 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev) /* setup fb_infos */ for (i = 0; i < fbdev->num_fbs; i++) { - r = omapfb_fb_init(fbdev, fbdev->fbs[i]); + struct fb_info *fbi = fbdev->fbs[i]; + struct omapfb_info *ofbi = FB2OFB(fbi); + + omapfb_get_mem_region(ofbi->region); + r = omapfb_fb_init(fbdev, fbi); + omapfb_put_mem_region(ofbi->region); + if (r) { dev_err(fbdev->dev, "failed to setup fb_info\n"); return r; @@ -1947,7 +1987,13 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev) DBG("framebuffers registered\n"); for (i = 0; i < fbdev->num_fbs; i++) { - r = omapfb_apply_changes(fbdev->fbs[i], 1); + struct fb_info *fbi = fbdev->fbs[i]; + struct omapfb_info *ofbi = FB2OFB(fbi); + + omapfb_get_mem_region(ofbi->region); + r = omapfb_apply_changes(fbi, 1); + omapfb_put_mem_region(ofbi->region); + if (r) { dev_err(fbdev->dev, "failed to change mode\n"); return r; diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c index 6fbe39a..6aee279 100644 --- a/drivers/video/omap2/omapfb/omapfb-sysfs.c +++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c @@ -49,6 +49,7 @@ static ssize_t store_rotate_type(struct device *dev, { struct fb_info *fbi = dev_get_drvdata(dev); struct omapfb_info *ofbi = FB2OFB(fbi); + struct omapfb2_mem_region *rg; enum omap_dss_rotation_type rot_type; int r; @@ -63,9 +64,11 @@ static ssize_t store_rotate_type(struct device *dev, if (rot_type == ofbi->rotation_type) goto out; - if (ofbi->region->size) { + rg = omapfb_get_mem_region(ofbi->region); + + if (rg->size) { r = -EBUSY; - goto out; + goto put_region; } ofbi->rotation_type = rot_type; @@ -74,6 +77,8 @@ static ssize_t store_rotate_type(struct device *dev, * Since the VRAM for this FB is not allocated at the moment we don't * need to do any further parameter checking at this point. */ +put_region: + omapfb_put_mem_region(rg); out: unlock_fb_info(fbi); @@ -109,6 +114,8 @@ static ssize_t store_mirror(struct device *dev, ofbi->mirror = mirror; + omapfb_get_mem_region(ofbi->region); + memcpy(&new_var, &fbi->var, sizeof(new_var)); r = check_fb_var(fbi, &new_var); if (r) @@ -123,6 +130,8 @@ static ssize_t store_mirror(struct device *dev, r = count; out: + omapfb_put_mem_region(ofbi->region); + unlock_fb_info(fbi); return r; @@ -259,11 +268,15 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr, DBG("detaching %d\n", ofbi->overlays[i]->id); + omapfb_get_mem_region(ofbi->region); + omapfb_overlay_enable(ovl, 0); if (ovl->manager) ovl->manager->apply(ovl->manager); + omapfb_put_mem_region(ofbi->region); + for (t = i + 1; t < ofbi->num_overlays; t++) { ofbi->rotation[t-1] = ofbi->rotation[t]; ofbi->overlays[t-1] = ofbi->overlays[t]; @@ -296,7 +309,12 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr, } if (added) { + omapfb_get_mem_region(ofbi->region); + r = omapfb_apply_changes(fbi, 0); + + omapfb_put_mem_region(ofbi->region); + if (r) goto out; } @@ -382,7 +400,12 @@ static ssize_t store_overlays_rotate(struct device *dev, for (i = 0; i < num_ovls; ++i) ofbi->rotation[i] = rotation[i]; + omapfb_get_mem_region(ofbi->region); + r = omapfb_apply_changes(fbi, 0); + + omapfb_put_mem_region(ofbi->region); + if (r) goto out; @@ -422,6 +445,14 @@ static ssize_t store_size(struct device *dev, struct device_attribute *attr, rg = ofbi->region; + /* FIXME probably should be a rwsem ... */ + mutex_lock(&rg->mtx); + while (rg->ref) { + mutex_unlock(&rg->mtx); + schedule(); + mutex_lock(&rg->mtx); + } + if (atomic_read(&rg->map_count)) { r = -EBUSY; goto out; @@ -452,6 +483,8 @@ static ssize_t store_size(struct device *dev, struct device_attribute *attr, r = count; out: + mutex_unlock(&rg->mtx); + unlock_fb_info(fbi); return r; diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h index 02f1ba9..db3aef5 100644 --- a/drivers/video/omap2/omapfb/omapfb.h +++ b/drivers/video/omap2/omapfb/omapfb.h @@ -52,6 +52,8 @@ struct omapfb2_mem_region { u8 type; /* OMAPFB_PLANE_MEM_* */ bool alloc; /* allocated by the driver */ bool map; /* kernel mapped by the driver */ + struct mutex mtx; + unsigned int ref; atomic_t map_count; }; @@ -159,4 +161,20 @@ static inline int omapfb_overlay_enable(struct omap_overlay *ovl, return ovl->set_overlay_info(ovl, &info); } +static inline struct omapfb2_mem_region * +omapfb_get_mem_region(struct omapfb2_mem_region *rg) +{ + mutex_lock(&rg->mtx); + rg->ref++; + mutex_unlock(&rg->mtx); + return rg; +} + +static inline void omapfb_put_mem_region(struct omapfb2_mem_region *rg) +{ + mutex_lock(&rg->mtx); + rg->ref--; + mutex_unlock(&rg->mtx); +} + #endif From patchwork Mon May 3 06:57:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 96441 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o436vWxC017346 for ; Mon, 3 May 2010 06:57:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756275Ab0ECG5a (ORCPT ); Mon, 3 May 2010 02:57:30 -0400 Received: from smtp.nokia.com ([192.100.122.233]:34218 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752008Ab0ECG53 (ORCPT ); Mon, 3 May 2010 02:57:29 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o436uugB025650; Mon, 3 May 2010 09:57:17 +0300 Received: from vaepf101.NOE.Nokia.com ([10.160.244.86]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:57:15 +0300 Received: from [172.21.41.121] ([172.21.41.121]) by vaepf101.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:57:15 +0300 Message-ID: <4BDE73CB.4040604@nokia.com> Date: Mon, 03 May 2010 09:57:15 +0300 From: Adrian Hunter User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: Andrew Morton CC: Tony Lindgren , Madhusudhan , "'Venkatraman S'" , "'linux-mmc Mailing List'" , "'linux-omap Mailing List'" Subject: Re: [PATCH v2] omap_hsmmc: improve interrupt synchronisation References: <4BD19BBB.40701@nokia.com> <002801cae554$09ac97c0$544ff780@am.dhcp.ti.com> <20100426211741.GO7225@atomide.com> In-Reply-To: <20100426211741.GO7225@atomide.com> X-OriginalArrivalTime: 03 May 2010 06:57:15.0983 (UTC) FILETIME=[DD6F55F0:01CAEA8D] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 06:57:33 +0000 (UTC) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index c0b5021..cc0272d 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -157,12 +157,10 @@ struct omap_hsmmc_host { */ struct regulator *vcc; struct regulator *vcc_aux; - struct semaphore sem; struct work_struct mmc_carddetect_work; void __iomem *base; resource_size_t mapbase; spinlock_t irq_lock; /* Prevent races with irq handler */ - unsigned long flags; unsigned int id; unsigned int dma_len; unsigned int dma_sg_idx; @@ -183,6 +181,7 @@ struct omap_hsmmc_host { int protect_card; int reqs_blocked; int use_reg; + int req_in_progress; struct omap_mmc_platform_data *pdata; }; @@ -480,6 +479,27 @@ static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); } +static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host) +{ + unsigned int irq_mask; + + if (host->use_dma) + irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); + else + irq_mask = INT_EN_MASK; + + OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); + OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); + OMAP_HSMMC_WRITE(host->base, IE, irq_mask); +} + +static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) +{ + OMAP_HSMMC_WRITE(host->base, ISE, 0); + OMAP_HSMMC_WRITE(host->base, IE, 0); + OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); +} + #ifdef CONFIG_PM /* @@ -548,9 +568,7 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) && time_before(jiffies, timeout)) ; - OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); - OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); - OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); + omap_hsmmc_disable_irq(host); /* Do not initialize card-specific things if the power is off */ if (host->power_mode == MMC_POWER_OFF) @@ -653,6 +671,8 @@ static void send_init_stream(struct omap_hsmmc_host *host) return; disable_irq(host->irq); + + OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); @@ -718,17 +738,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, mmc_hostname(host->mmc), cmd->opcode, cmd->arg); host->cmd = cmd; - /* - * Clear status bits and enable interrupts - */ - OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); - OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); - - if (host->use_dma) - OMAP_HSMMC_WRITE(host->base, IE, - INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE)); - else - OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); + omap_hsmmc_enable_irq(host); host->response_busy = 0; if (cmd->flags & MMC_RSP_PRESENT) { @@ -762,13 +772,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, if (host->use_dma) cmdreg |= DMA_EN; - /* - * In an interrupt context (i.e. STOP command), the spinlock is unlocked - * by the interrupt handler, otherwise (i.e. for a new request) it is - * unlocked here. - */ - if (!in_interrupt()) - spin_unlock_irqrestore(&host->irq_lock, host->flags); + host->req_in_progress = 1; OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); @@ -783,6 +787,23 @@ omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) return DMA_FROM_DEVICE; } +static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) +{ + int dma_ch; + + spin_lock(&host->irq_lock); + host->req_in_progress = 0; + dma_ch = host->dma_ch; + spin_unlock(&host->irq_lock); + + omap_hsmmc_disable_irq(host); + /* Do not complete the request if DMA is still in progress */ + if (mrq->data && host->use_dma && dma_ch != -1) + return; + host->mrq = NULL; + mmc_request_done(host->mmc, mrq); +} + /* * Notify the transfer complete to MMC core */ @@ -799,25 +820,19 @@ omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) return; } - host->mrq = NULL; - mmc_request_done(host->mmc, mrq); + omap_hsmmc_request_done(host, mrq); return; } host->data = NULL; - if (host->use_dma && host->dma_ch != -1) - dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, - omap_hsmmc_get_dma_dir(host, data)); - if (!data->error) data->bytes_xfered += data->blocks * (data->blksz); else data->bytes_xfered = 0; if (!data->stop) { - host->mrq = NULL; - mmc_request_done(host->mmc, data->mrq); + omap_hsmmc_request_done(host, data->mrq); return; } omap_hsmmc_start_command(host, data->stop, NULL); @@ -843,10 +858,8 @@ omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); } } - if ((host->data == NULL && !host->response_busy) || cmd->error) { - host->mrq = NULL; - mmc_request_done(host->mmc, cmd->mrq); - } + if ((host->data == NULL && !host->response_busy) || cmd->error) + omap_hsmmc_request_done(host, cmd->mrq); } /* @@ -854,14 +867,19 @@ omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) */ static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) { + int dma_ch; + host->data->error = errno; - if (host->use_dma && host->dma_ch != -1) { + spin_lock(&host->irq_lock); + dma_ch = host->dma_ch; + host->dma_ch = -1; + spin_unlock(&host->irq_lock); + + if (host->use_dma && dma_ch != -1) { dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, omap_hsmmc_get_dma_dir(host, host->data)); - omap_free_dma(host->dma_ch); - host->dma_ch = -1; - up(&host->sem); + omap_free_dma(dma_ch); } host->data = NULL; } @@ -923,28 +941,21 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, __func__); } -/* - * MMC controller IRQ handler - */ -static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) +static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) { - struct omap_hsmmc_host *host = dev_id; struct mmc_data *data; - int end_cmd = 0, end_trans = 0, status; - - spin_lock(&host->irq_lock); - - if (host->mrq == NULL) { - OMAP_HSMMC_WRITE(host->base, STAT, - OMAP_HSMMC_READ(host->base, STAT)); - /* Flush posted write */ - OMAP_HSMMC_READ(host->base, STAT); - spin_unlock(&host->irq_lock); - return IRQ_HANDLED; + int end_cmd = 0, end_trans = 0; + + if (!host->req_in_progress) { + do { + OMAP_HSMMC_WRITE(host->base, STAT, status); + /* Flush posted write */ + status = OMAP_HSMMC_READ(host->base, STAT); + } while (status & INT_EN_MASK); + return; } data = host->data; - status = OMAP_HSMMC_READ(host->base, STAT); dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); if (status & ERR) { @@ -997,15 +1008,27 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) } OMAP_HSMMC_WRITE(host->base, STAT, status); - /* Flush posted write */ - OMAP_HSMMC_READ(host->base, STAT); if (end_cmd || ((status & CC) && host->cmd)) omap_hsmmc_cmd_done(host, host->cmd); if ((end_trans || (status & TC)) && host->mrq) omap_hsmmc_xfer_done(host, data); +} - spin_unlock(&host->irq_lock); +/* + * MMC controller IRQ handler + */ +static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) +{ + struct omap_hsmmc_host *host = dev_id; + int status; + + status = OMAP_HSMMC_READ(host->base, STAT); + do { + omap_hsmmc_do_irq(host, status); + /* Flush posted write */ + status = OMAP_HSMMC_READ(host->base, STAT); + } while (status & INT_EN_MASK); return IRQ_HANDLED; } @@ -1205,31 +1228,47 @@ static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, /* * DMA call back function */ -static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data) +static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) { - struct omap_hsmmc_host *host = data; + struct omap_hsmmc_host *host = cb_data; + struct mmc_data *data = host->mrq->data; + int dma_ch, req_in_progress; if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); - if (host->dma_ch < 0) + spin_lock(&host->irq_lock); + if (host->dma_ch < 0) { + spin_unlock(&host->irq_lock); return; + } host->dma_sg_idx++; if (host->dma_sg_idx < host->dma_len) { /* Fire up the next transfer. */ - omap_hsmmc_config_dma_params(host, host->data, - host->data->sg + host->dma_sg_idx); + omap_hsmmc_config_dma_params(host, data, + data->sg + host->dma_sg_idx); + spin_unlock(&host->irq_lock); return; } - omap_free_dma(host->dma_ch); + dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, + omap_hsmmc_get_dma_dir(host, data)); + + req_in_progress = host->req_in_progress; + dma_ch = host->dma_ch; host->dma_ch = -1; - /* - * DMA Callback: run in interrupt context. - * mutex_unlock will throw a kernel warning if used. - */ - up(&host->sem); + spin_unlock(&host->irq_lock); + + omap_free_dma(dma_ch); + + /* If DMA has finished after TC, complete the request */ + if (!req_in_progress) { + struct mmc_request *mrq = host->mrq; + + host->mrq = NULL; + mmc_request_done(host->mmc, mrq); + } } /* @@ -1238,7 +1277,7 @@ static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data) static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, struct mmc_request *req) { - int dma_ch = 0, ret = 0, err = 1, i; + int dma_ch = 0, ret = 0, i; struct mmc_data *data = req->data; /* Sanity check: all the SG entries must be aligned by block size. */ @@ -1255,23 +1294,7 @@ static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, */ return -EINVAL; - /* - * If for some reason the DMA transfer is still active, - * we wait for timeout period and free the dma - */ - if (host->dma_ch != -1) { - set_current_state(TASK_UNINTERRUPTIBLE); - schedule_timeout(100); - if (down_trylock(&host->sem)) { - omap_free_dma(host->dma_ch); - host->dma_ch = -1; - up(&host->sem); - return err; - } - } else { - if (down_trylock(&host->sem)) - return err; - } + BUG_ON(host->dma_ch != -1); ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); @@ -1371,37 +1394,27 @@ static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) struct omap_hsmmc_host *host = mmc_priv(mmc); int err; - /* - * Prevent races with the interrupt handler because of unexpected - * interrupts, but not if we are already in interrupt context i.e. - * retries. - */ - if (!in_interrupt()) { - spin_lock_irqsave(&host->irq_lock, host->flags); - /* - * Protect the card from I/O if there is a possibility - * it can be removed. - */ - if (host->protect_card) { - if (host->reqs_blocked < 3) { - /* - * Ensure the controller is left in a consistent - * state by resetting the command and data state - * machines. - */ - omap_hsmmc_reset_controller_fsm(host, SRD); - omap_hsmmc_reset_controller_fsm(host, SRC); - host->reqs_blocked += 1; - } - req->cmd->error = -EBADF; - if (req->data) - req->data->error = -EBADF; - spin_unlock_irqrestore(&host->irq_lock, host->flags); - mmc_request_done(mmc, req); - return; - } else if (host->reqs_blocked) - host->reqs_blocked = 0; - } + BUG_ON(host->req_in_progress); + BUG_ON(host->dma_ch != -1); + if (host->protect_card) { + if (host->reqs_blocked < 3) { + /* + * Ensure the controller is left in a consistent + * state by resetting the command and data state + * machines. + */ + omap_hsmmc_reset_controller_fsm(host, SRD); + omap_hsmmc_reset_controller_fsm(host, SRC); + host->reqs_blocked += 1; + } + req->cmd->error = -EBADF; + if (req->data) + req->data->error = -EBADF; + req->cmd->retries = 0; + mmc_request_done(mmc, req); + return; + } else if (host->reqs_blocked) + host->reqs_blocked = 0; WARN_ON(host->mrq != NULL); host->mrq = req; err = omap_hsmmc_prepare_data(host, req); @@ -1410,8 +1423,6 @@ static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) if (req->data) req->data->error = err; host->mrq = NULL; - if (!in_interrupt()) - spin_unlock_irqrestore(&host->irq_lock, host->flags); mmc_request_done(mmc, req); return; } @@ -1980,7 +1991,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) mmc->f_min = 400000; mmc->f_max = 52000000; - sema_init(&host->sem, 1); spin_lock_init(&host->irq_lock); host->iclk = clk_get(&pdev->dev, "ick"); @@ -2126,8 +2136,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) } } - OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); - OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); + omap_hsmmc_disable_irq(host); mmc_host_lazy_disable(host->mmc); @@ -2247,10 +2256,7 @@ static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state) mmc_host_enable(host->mmc); ret = mmc_suspend_host(host->mmc, state); if (ret == 0) { - OMAP_HSMMC_WRITE(host->base, ISE, 0); - OMAP_HSMMC_WRITE(host->base, IE, 0); - - + omap_hsmmc_disable_irq(host); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); mmc_host_disable(host->mmc); From patchwork Mon May 3 06:59:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Reddy, Teerth" X-Patchwork-Id: 96442 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o436vWxE017346 for ; Mon, 3 May 2010 06:59:54 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932069Ab0ECG7y (ORCPT ); Mon, 3 May 2010 02:59:54 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:42871 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754277Ab0ECG7w convert rfc822-to-8bit (ORCPT ); Mon, 3 May 2010 02:59:52 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o436xl17005464 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 3 May 2010 01:59:49 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o436xkBR010699; Mon, 3 May 2010 12:29:46 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Mon, 3 May 2010 12:29:46 +0530 From: "Reddy, Teerth" To: Peter Tseng , "Shilimkar, Santosh" CC: Kevin Hilman , Cliff Brake , "linux-omap@vger.kernel.org" Date: Mon, 3 May 2010 12:29:44 +0530 Subject: RE: ARM suspend to disk? Thread-Topic: ARM suspend to disk? Thread-Index: Acrqfzktq371HoejTyaJHg4PaNvpSQADr05Q Message-ID: <5A47E75E594F054BAF48C5E4FC4B92AB0322A8AACA@dbde02.ent.ti.com> References: <4BD881A7.2020402@gmail.com> <87y6g6w373.fsf@deeprootsystems.com> <87iq78d295.fsf@deeprootsystems.com> <4BDE5AFD.9070506@gmail.com> In-Reply-To: <4BDE5AFD.9070506@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 06:59:55 +0000 (UTC) diff -purN 12x_old/arch/arm/kernel/vmlinux.lds.S 12x_git/arch/arm/kernel/vmlinux.lds.S --- 12x_old/arch/arm/kernel/vmlinux.lds.S 2009-06-30 14:29:09.000000000 +0530 +++ 12x_git/arch/arm/kernel/vmlinux.lds.S 2009-06-30 11:05:16.000000000 +0530 @@ -87,6 +87,7 @@ SECTIONS } .text : { /* Real text segment */ + _kern_text_start = .; _text = .; /* Text and read-only data */ __exception_text_start = .; *(.exception.text) @@ -108,6 +109,7 @@ SECTIONS RODATA _etext = .; /* End of text and rodata section */ + _kern_text_end = .; #ifdef CONFIG_XIP_KERNEL __data_loc = ALIGN(4); /* location in binary */ @@ -134,12 +136,6 @@ SECTIONS __init_end = .; #endif - . = ALIGN(4096); - __nosave_begin = .; - *(.data.nosave) - . = ALIGN(4096); - __nosave_end = .; - /* * then the cacheline aligned data */ @@ -165,6 +161,11 @@ SECTIONS _edata = .; } _edata_loc = __data_loc + SIZEOF(.data); + . = ALIGN(4096); + __nosave_begin = .; + .data.nosave : { *(.data.nosave) } + . = ALIGN(4096); + __nosave_end = .; .bss : { __bss_start = .; /* BSS */ diff -purN 12x_old/arch/arm/Makefile 12x_git/arch/arm/Makefile --- 12x_old/arch/arm/Makefile 2009-06-30 14:29:09.000000000 +0530 +++ 12x_git/arch/arm/Makefile 2009-06-30 11:05:16.000000000 +0530 @@ -198,6 +198,7 @@ core-$(CONFIG_ARCH_MXC) += arch/arm/pla drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/ drivers-$(CONFIG_ARCH_L7200) += drivers/acorn/char/ +drivers-$(CONFIG_HIBERNATION) += arch/arm/power/ libs-y := arch/arm/lib/ $(libs-y) diff -purN 12x_old/arch/arm/mm/init.c 12x_git/arch/arm/mm/init.c --- 12x_old/arch/arm/mm/init.c 2009-06-30 14:29:09.000000000 +0530 +++ 12x_git/arch/arm/mm/init.c 2009-06-30 11:05:16.000000000 +0530 @@ -354,6 +354,25 @@ static inline void free_area(unsigned lo printk(KERN_INFO "Freeing %s memory: %dK\n", s, size); } +#if defined(CONFIG_HIBERNATION) + +/* + * Swap suspend & friends need this for resume. + */ + +/* pgd_t is unsigned long [2], so 2 * 4 (byte/word) */ + +char __nosavedata swsusp_pg_dir[PTRS_PER_PGD * 2 * 4] +/* Translation Table Base must be on 16KB boundary. */ +__attribute__ ((aligned (1UL << 14))); + +void swsusp_save_pg_dir(void) +{ + memcpy(swsusp_pg_dir, swapper_pg_dir, PTRS_PER_PGD * 2 * 4); +} +#endif + + static inline void free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn) { diff -purN 12x_git/arch/arm/power/cpu.c 2.6.24.7-linux/arch/arm/power/cpu.c --- 12x_git/arch/arm/power/cpu.c 1970-01-01 05:30:00.000000000 +0530 +++ 2.6.24.7-linux/arch/arm/power/cpu.c 2009-07-06 15:45:30.000000000 +0530 @@ -0,0 +1,157 @@ +/* + * cpu.c - Suspend support specific for ARM. + * based on arch/i386/power/cpu.c + * + * Distribute under GPLv2 + * + * Copyright (c) 2002 Pavel Machek + * Copyright (c) 2001 Patrick Mochel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct saved_context saved_context; + +void __save_processor_state(struct saved_context *ctxt) +{ + unsigned long reg; + + /* save preempt state and disable it */ + preempt_disable(); + + /* save coprocessor 15 registers*/ + asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r"(ctxt->CSSR)); + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(ctxt->CR)); + asm volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r"(ctxt->CACR)); + asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r"(ctxt->TTB_0R)); + asm volatile ("mrc p15, 0, %0, c2, c0, 1" : "=r"(ctxt->TTB_1R)); + asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r"(ctxt->TTBCR)); + asm volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r"(ctxt->DACR)); + asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r"(ctxt->D_FSR)); + asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r"(ctxt->I_FSR)); + asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r"(ctxt->D_AFSR)); + asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r"(ctxt->I_AFSR)); + asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r"(ctxt->D_FAR)); + asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r"(ctxt->I_FAR)); + asm volatile ("mrc p15, 0, %0, c7, c4, 0" : "=r"(ctxt->PAR)); + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(ctxt->PMControlR)); + asm volatile ("mrc p15, 0, %0, c9, c12, 1" : "=r"(ctxt->CESR)); + asm volatile ("mrc p15, 0, %0, c9, c12, 2" : "=r"(ctxt->CECR)); + asm volatile ("mrc p15, 0, %0, c9, c12, 3" : "=r"(ctxt->OFSR)); + asm volatile ("mrc p15, 0, %0, c9, c12, 4" : "=r"(ctxt->SIR)); + asm volatile ("mrc p15, 0, %0, c9, c12, 5" : "=r"(ctxt->PCSR)); + asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(ctxt->CCR)); + asm volatile ("mrc p15, 0, %0, c9, c13, 1" : "=r"(ctxt->ESR)); + asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(ctxt->PMCountR)); + asm volatile ("mrc p15, 0, %0, c9, c14, 0" : "=r"(ctxt->UER)); + asm volatile ("mrc p15, 0, %0, c9, c14, 1" : "=r"(ctxt->IESR)); + asm volatile ("mrc p15, 0, %0, c9, c14, 2" : "=r"(ctxt->IECR)); + asm volatile ("mrc p15, 1, %0, c9, c0, 0" : "=r"(ctxt->L2CLR)); + asm volatile ("mrc p15, 0, %0, c10, c0, 0" : "=r"(ctxt->D_TLBLR)); + asm volatile ("mrc p15, 0, %0, c10, c0, 1" : "=r"(ctxt->I_TLBLR)); + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(ctxt->PRRR)); + asm volatile ("mrc p15, 0, %0, c10, c2, 1" : "=r"(ctxt->NRRR)); + asm volatile ("mrc p15, 0, %0, c11, c1, 0" : "=r"(ctxt->PLEUAR)); + asm volatile ("mrc p15, 0, %0, c11, c2, 0" : "=r"(ctxt->PLECNR)); + asm volatile ("mrc p15, 0, %0, c11, c4, 0" : "=r"(ctxt->PLECR)); + asm volatile ("mrc p15, 0, %0, c11, c5, 0" : "=r"(ctxt->PLEISAR)); + asm volatile ("mrc p15, 0, %0, c11, c7, 0" : "=r"(ctxt->PLEIEAR)); + asm volatile ("mrc p15, 0, %0, c11, c15, 0" : "=r"(ctxt->PLECIDR)); + asm volatile ("mrc p15, 0, %0, c12, c0, 0" : "=r"(ctxt->SNSVBAR)); + asm volatile ("mrc p15, 0, %0, c13, c0, 0" : "=r"(ctxt->FCSE)); + asm volatile ("mrc p15, 0, %0, c13, c0, 1" : "=r"(ctxt->CID)); + asm volatile ("mrc p15, 0, %0, c13, c0, 2" : "=r"(ctxt->URWTPID)); + asm volatile ("mrc p15, 0, %0, c13, c0, 3" : "=r"(ctxt->UROTPID)); + asm volatile ("mrc p15, 0, %0, c13, c0, 4" : "=r"(ctxt->POTPID)); + +} + +void save_processor_state(void) +{ + __save_processor_state(&saved_context); +} + +void __restore_processor_state(struct saved_context *ctxt) +{ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r"(ctxt->CSSR)); + asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ctxt->CR)); + asm volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r"(ctxt->CACR)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ctxt->TTB_0R)); + asm volatile ("mcr p15, 0, %0, c2, c0, 1" : : "r"(ctxt->TTB_1R)); + asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r"(ctxt->TTBCR)); + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(ctxt->DACR)); + asm volatile ("mcr p15, 0, %0, c5, c0, 0" : : "r"(ctxt->D_FSR)); + asm volatile ("mcr p15, 0, %0, c5, c0, 1" : : "r"(ctxt->I_FSR)); + asm volatile ("mcr p15, 0, %0, c5, c1, 0" : : "r"(ctxt->D_AFSR)); + asm volatile ("mcr p15, 0, %0, c5, c1, 1" : : "r"(ctxt->I_AFSR)); + asm volatile ("mcr p15, 0, %0, c6, c0, 0" : : "r"(ctxt->D_FAR)); + asm volatile ("mcr p15, 0, %0, c6, c0, 2" : : "r"(ctxt->I_FAR)); + asm volatile ("mcr p15, 0, %0, c7, c4, 0" : : "r"(ctxt->PAR)); + asm volatile ("mcr p15, 0, %0, c9, c12, 0" : : "r"(ctxt->PMControlR)); + asm volatile ("mcr p15, 0, %0, c9, c12, 1" : : "r"(ctxt->CESR)); + asm volatile ("mcr p15, 0, %0, c9, c12, 2" : : "r"(ctxt->CECR)); + asm volatile ("mcr p15, 0, %0, c9, c12, 3" : : "r"(ctxt->OFSR)); + asm volatile ("mcr p15, 0, %0, c9, c12, 4" : : "r"(ctxt->SIR)); + asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(ctxt->PCSR)); + asm volatile ("mcr p15, 0, %0, c9, c13, 0" : : "r"(ctxt->CCR)); + asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(ctxt->ESR)); + asm volatile ("mcr p15, 0, %0, c9, c13, 2" : : "r"(ctxt->PMCountR)); + asm volatile ("mcr p15, 0, %0, c9, c14, 0" : : "r"(ctxt->UER)); + asm volatile ("mcr p15, 0, %0, c9, c14, 1" : : "r"(ctxt->IESR)); + asm volatile ("mcr p15, 0, %0, c9, c14, 2" : : "r"(ctxt->IECR)); + asm volatile ("mcr p15, 1, %0, c9, c0, 0" : : "r"(ctxt->L2CLR)); + asm volatile ("mcr p15, 0, %0, c10, c0, 0" : : "r"(ctxt->D_TLBLR)); + asm volatile ("mcr p15, 0, %0, c10, c0, 1" : : "r"(ctxt->I_TLBLR)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(ctxt->PRRR)); + asm volatile ("mcr p15, 0, %0, c10, c2, 1" : : "r"(ctxt->NRRR)); + asm volatile ("mcr p15, 0, %0, c11, c1, 0" : : "r"(ctxt->PLEUAR)); + asm volatile ("mcr p15, 0, %0, c11, c2, 0" : : "r"(ctxt->PLECNR)); + asm volatile ("mcr p15, 0, %0, c11, c4, 0" : : "r"(ctxt->PLECR)); + asm volatile ("mcr p15, 0, %0, c11, c5, 0" : : "r"(ctxt->PLEISAR)); + asm volatile ("mcr p15, 0, %0, c11, c7, 0" : : "r"(ctxt->PLEIEAR)); + asm volatile ("mcr p15, 0, %0, c11, c15, 0" : : "r"(ctxt->PLECIDR)); + asm volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r"(ctxt->SNSVBAR)); + asm volatile ("mcr p15, 0, %0, c13, c0, 0" : : "r"(ctxt->FCSE)); + asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(ctxt->CID)); + asm volatile ("mcr p15, 0, %0, c13, c0, 2" : : "r"(ctxt->URWTPID)); + asm volatile ("mcr p15, 0, %0, c13, c0, 3" : : "r"(ctxt->UROTPID)); + asm volatile ("mcr p15, 0, %0, c13, c0, 4" : : "r"(ctxt->POTPID)); + + /* restore preempt state */ + preempt_enable(); +} + +void restore_processor_state(void) +{ + __restore_processor_state(&saved_context); +} + + +EXPORT_SYMBOL(save_processor_state); +EXPORT_SYMBOL(restore_processor_state); diff -purN 12x_git/arch/arm/power/Makefile 2.6.24.7-linux/arch/arm/power/Makefile --- 12x_git/arch/arm/power/Makefile 1970-01-01 05:30:00.000000000 +0530 +++ 2.6.24.7-linux/arch/arm/power/Makefile 2009-06-29 15:35:58.000000000 +0530 @@ -0,0 +1 @@ +obj-$(CONFIG_HIBERNATION) += cpu.o swsusp.o suspend.o diff -purN 12x_git/arch/arm/power/suspend.c 2.6.24.7-linux/arch/arm/power/suspend.c --- 12x_git/arch/arm/power/suspend.c 1970-01-01 05:30:00.000000000 +0530 +++ 2.6.24.7-linux/arch/arm/power/suspend.c 2009-06-29 15:34:04.000000000 +0530 @@ -0,0 +1,29 @@ +/* + * Suspend support specific for ARM - temporary page tables + * + * Distribute under GPLv2 + * + * Copyright (c) 2006 Rafael J. Wysocki + */ + +#include +#include + +#include +#include +#include + +/* References to section boundaries */ +extern const void __nosave_begin, __nosave_end; + + +/* + * pfn_is_nosave - check if given pfn is in the 'nosave' section + */ + +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT; + unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT; + return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); +} diff -purN 12x_git/arch/arm/power/swsusp.S 2.6.24.7-linux/arch/arm/power/swsusp.S --- 12x_git/arch/arm/power/swsusp.S 1970-01-01 05:30:00.000000000 +0530 +++ 2.6.24.7-linux/arch/arm/power/swsusp.S 2009-07-07 16:08:33.000000000 +0530 @@ -0,0 +1,447 @@ +/* + * swsusp.S - This file is based on arch/i386/power/swsusp.S; + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * This may not use any stack, nor any variable that is not "NoSave": + * + * Its rewriting one kernel image with another. What is stack in "old" + * image could very well be data page in "new" image, and overwriting + * your own stack under you is bad idea. + */ + +/* + * FIXME: Work needs to be done for core with fp. + */ + +#include +#include +#include + + .text + +#define LOCAL_WORD(x) \ + .data ; \ + .p2align 2 ; \ + .type x, #object ; \ + .size x, 4 ; \ +x: ; \ + .long 1 + +#define WORD_ADDR(x) \ + .align 2 ; \ +.L##x: ; \ + .word x + +#define FUNC(x) \ + .text ; \ + .p2align 2 ; \ + .globl x ; \ + .type x, #function ; \ +x: + +#define FUNC_END(x) \ + .size x, .-x + +#define CHANGE_MODE(x) \ + mov r1, r0 ; \ + bic r1, r1, #0x1f ; \ + orr r1, r1, #0x##x ; \ + msr cpsr_c, r1 + +#define SAVE_VFP_REG(x) \ + fmrrd r0, r1, d##x ; \ + str r0, [r2] ; \ + str r1, [r3] ; \ + add r2, r2, #4 ; \ + add r3, r3, #4 + + +#define RESTORE_VFP_REG(x) \ + ldr r0, [r2] ; \ + ldr r1, [r3] ; \ + fmdrr d##x, r0, r1 + + +/* nonvolatile int registers */ +#ifdef DEBUG + .globl saved_context_r0 // for debug +#endif + LOCAL_WORD(saved_context_r0) + LOCAL_WORD(saved_context_r1) + LOCAL_WORD(saved_context_r2) + LOCAL_WORD(saved_context_r3) + LOCAL_WORD(saved_context_r4) + LOCAL_WORD(saved_context_r5) + LOCAL_WORD(saved_context_r6) + LOCAL_WORD(saved_context_r7) + LOCAL_WORD(saved_context_r8) + LOCAL_WORD(saved_context_r9) + LOCAL_WORD(saved_context_r10) + LOCAL_WORD(saved_context_r11) + LOCAL_WORD(saved_context_r12) + LOCAL_WORD(saved_context_r13) + LOCAL_WORD(saved_context_r14) + LOCAL_WORD(saved_cpsr) + + LOCAL_WORD(saved_context_r8_fiq) + LOCAL_WORD(saved_context_r9_fiq) + LOCAL_WORD(saved_context_r10_fiq) + LOCAL_WORD(saved_context_r11_fiq) + LOCAL_WORD(saved_context_r12_fiq) + LOCAL_WORD(saved_context_r13_fiq) + LOCAL_WORD(saved_context_r14_fiq) + LOCAL_WORD(saved_spsr_fiq) + + LOCAL_WORD(saved_context_r13_irq) + LOCAL_WORD(saved_context_r14_irq) + LOCAL_WORD(saved_spsr_irq) + + LOCAL_WORD(saved_context_r13_svc) + LOCAL_WORD(saved_context_r14_svc) + LOCAL_WORD(saved_spsr_svc) + + LOCAL_WORD(saved_context_r13_abt) + LOCAL_WORD(saved_context_r14_abt) + LOCAL_WORD(saved_spsr_abt) + + LOCAL_WORD(saved_context_r13_und) + LOCAL_WORD(saved_context_r14_und) + LOCAL_WORD(saved_spsr_und) + + LOCAL_WORD(saved_fpscr) + LOCAL_WORD(saved_fpexc) + + LOCAL_WORD(lower_d0); + LOCAL_WORD(lower_d1); + LOCAL_WORD(lower_d2); + LOCAL_WORD(lower_d3); + LOCAL_WORD(lower_d4); + LOCAL_WORD(lower_d5); + LOCAL_WORD(lower_d6); + LOCAL_WORD(lower_d7); + LOCAL_WORD(lower_d8); + LOCAL_WORD(lower_d9); + LOCAL_WORD(lower_d10); + LOCAL_WORD(lower_d11); + LOCAL_WORD(lower_d12); + LOCAL_WORD(lower_d13); + LOCAL_WORD(lower_d14); + LOCAL_WORD(lower_d15); + + LOCAL_WORD(high_d0); + LOCAL_WORD(high_d1); + LOCAL_WORD(high_d2); + LOCAL_WORD(high_d3); + LOCAL_WORD(high_d4); + LOCAL_WORD(high_d5); + LOCAL_WORD(high_d6); + LOCAL_WORD(high_d7); + LOCAL_WORD(high_d8); + LOCAL_WORD(high_d9); + LOCAL_WORD(high_d10); + LOCAL_WORD(high_d11); + LOCAL_WORD(high_d12); + LOCAL_WORD(high_d13); + LOCAL_WORD(high_d14); + LOCAL_WORD(high_d15); + +/* + * non volatile fpu registers + * s16 - s31 + */ + /* XXX:TBD */ + +FUNC(swsusp_arch_suspend) + + ldr r2, .Llower_d0 + ldr r3, .Lhigh_d0 + + /* save NEON and VFP registers */ + fmrrd r0, r1, d0 + str r0, [r2] + str r1, [r3] + + ldr r2, .Llower_d1 + ldr r3, .Lhigh_d1 + SAVE_VFP_REG(1) + SAVE_VFP_REG(2) + SAVE_VFP_REG(3) + SAVE_VFP_REG(4) + SAVE_VFP_REG(5) + SAVE_VFP_REG(6) + SAVE_VFP_REG(7) + SAVE_VFP_REG(8) + SAVE_VFP_REG(9) + SAVE_VFP_REG(10) + SAVE_VFP_REG(11) + SAVE_VFP_REG(12) + SAVE_VFP_REG(13) + SAVE_VFP_REG(14) + SAVE_VFP_REG(15) + + /* save current program status register */ + ldr r3, .Lsaved_cpsr + mrs r1, cpsr + str r1, [r3] + + /* hold current mode */ + mrs r0, cpsr + + CHANGE_MODE(1f) /* change to system(user) mode */ + /* save nonvolatile int register */ + ldr r3, .Lsaved_context_r0 + stmia r3, {r0-r14} + + /* Save NEON and VFP System registers */ + /* First read FPEXC and check whether bit no. 30 is 1 (enabled) or 0 (disabled) */ + FMRX r3, FPEXC + ldr r1, .Lsaved_fpexc + str r3, [r1] + bic r3, r3, #0x80000000 + cmp r3, #0 + beq .Lnext + FMRX r3, FPSCR + ldr r1, .Lsaved_fpscr + str r3, [r1] + +.Lnext: + CHANGE_MODE(11) /* change to fiq mode */ + /* save nonvolatile int register */ + ldr r3, .Lsaved_context_r8_fiq + stmia r3, {r8-r14} + /* save spsr_fiq register */ + ldr r3, .Lsaved_spsr_fiq + mrs r1, spsr + str r1, [r3] + + CHANGE_MODE(12) /* change to irq mode */ + /* save nonvolatile int register */ + ldr r3, .Lsaved_context_r13_irq + stmia r3, {r13-r14} + /* save spsr_irq register */ + ldr r3, .Lsaved_spsr_irq + mrs r1, spsr + str r1, [r3] + + CHANGE_MODE(13) /* change to svc mode */ + /* save nonvolatile int register */ + ldr r3, .Lsaved_context_r13_svc + stmia r3, {r13-r14} + /* save spsr_svc register */ + ldr r3, .Lsaved_spsr_svc + mrs r1, spsr + str r1, [r3] + + CHANGE_MODE(17) /* change to abt mode */ + /* save nonvolatile int register */ + ldr r3, .Lsaved_context_r13_abt + stmia r3, {r13-r14} + /* save spsr_abt register */ + ldr r3, .Lsaved_spsr_abt + mrs r1, spsr + str r1, [r3] + + CHANGE_MODE(1b) /* change to und mode */ + /* save nonvolatile int register */ + ldr r3, .Lsaved_context_r13_und + stmia r3, {r13-r14} + /* save spsr_und register */ + ldr r3, .Lsaved_spsr_und + mrs r1, spsr + str r1, [r3] + + /* go back to original mode */ + msr cpsr_c, r0 + + /* + * save nonvolatile fp registers + * and fp status/system registers, if needed + */ + /* XXX:TBD */ + + /* call swsusp_save */ + bl swsusp_save + + /* restore return address */ + ldr r3, .Lsaved_context_r14_svc + ldr lr, [r3] + mov pc, lr + + WORD_ADDR(saved_context_r0) + WORD_ADDR(saved_cpsr) + WORD_ADDR(saved_context_r8_fiq) + WORD_ADDR(saved_spsr_fiq) + WORD_ADDR(saved_context_r13_irq) + WORD_ADDR(saved_spsr_irq) + WORD_ADDR(saved_context_r13_svc) + WORD_ADDR(saved_context_r14_svc) + WORD_ADDR(saved_spsr_svc) + WORD_ADDR(saved_context_r13_abt) + WORD_ADDR(saved_spsr_abt) + WORD_ADDR(saved_context_r13_und) + WORD_ADDR(saved_spsr_und) + + WORD_ADDR(saved_fpscr) + WORD_ADDR(saved_fpexc) + + WORD_ADDR(lower_d0) + WORD_ADDR(high_d0) + WORD_ADDR(lower_d1) + WORD_ADDR(high_d1) + +FUNC_END(swsusp_arch_suspend) + +FUNC(swsusp_arch_resume) + + /* Set page table if needed */ + + /* restore_pblist is the starting point for loaded pages */ + ldr r0, .Lrestore_pblist + ldr r6, [r0] + +.Lcopy_loop: + ldr r4, [r6] /* src IOW present address */ + ldr r5, [r6, #4] /* dst IOW original address*/ + mov r9, #1024 /* No. of entries in one page, where each entry is 4 bytes */ + + /* this loop could be optimized by using stm and ldm. */ +.Lcopy_one_page: + ldr r8, [r4] + str r8, [r5] + + add r4, r4, #4 + add r5, r5, #4 + sub r9, r9, #1 + cmp r9, #0 + bne .Lcopy_one_page + + ldr r6, [r6, #8] /* The last field of struct pbe is a pointer to the next pbe structure */ + cmp r6, #0 + bne .Lcopy_loop + + /* Restore Neon and VFP Registers */ + ldr r2, .Llower_d0 + ldr r3, .Lhigh_d0 + + ldr r0, [r2] + ldr r1, [r3] + fmdrr d0, r0, r1 + + ldr r2, .Llower_d1 + ldr r3, .Lhigh_d1 + + RESTORE_VFP_REG(1) + RESTORE_VFP_REG(2) + RESTORE_VFP_REG(3) + RESTORE_VFP_REG(4) + RESTORE_VFP_REG(5) + RESTORE_VFP_REG(6) + RESTORE_VFP_REG(7) + RESTORE_VFP_REG(8) + RESTORE_VFP_REG(9) + RESTORE_VFP_REG(10) + RESTORE_VFP_REG(11) + RESTORE_VFP_REG(12) + RESTORE_VFP_REG(13) + RESTORE_VFP_REG(14) + RESTORE_VFP_REG(15) + /* hold current mode */ + mrs r0, cpsr + + CHANGE_MODE(1f) /* change to system(user) mode */ + /* Restore NEON and VFP system control registers */ + ldr r3, .Lsaved_fpexc + ldr r1, [r3] + FMXR FPEXC, r1 + bic r1, r1, #0x80000000 + cmp r1, #0 + beq .Lnext_restore + ldr r3, .Lsaved_fpscr + ldr r1, [r3] + FMXR FPSCR, r1 + +.Lnext_restore: + /* restore nonvolatile int register */ + ldr r3, .Lsaved_context_r0 + ldmia r3, {r0-r14} + /* restore current program status register */ + ldr r3, .Lsaved_cpsr + ldr r1, [r3] + msr cpsr_cxsf, r1 + + CHANGE_MODE(11) /* change to fiq mode */ + /* restore nonvolatile int register */ + ldr r3, .Lsaved_context_r8_fiq + ldmia r3, {r8-r14} + /* restore spsr_fiq register */ + ldr r3, .Lsaved_spsr_fiq + ldr r1, [r3] + msr spsr_cxsf, r1 + + CHANGE_MODE(12) /* change to irq mode */ + /* restore nonvolatile int register */ + ldr r3, .Lsaved_context_r13_irq + ldmia r3, {r13-r14} + /* restore spsr_irq register */ + ldr r3, .Lsaved_spsr_irq + ldr r1, [r3] + msr spsr_cxsf, r1 + + CHANGE_MODE(13) /* change to svc mode */ + /* restore nonvolatile int register */ + ldr r3, .Lsaved_context_r13_svc + ldmia r3, {r13-r14} + /* ldr r13, [r3] */ + /* restore spsr_svc register */ + ldr r3, .Lsaved_spsr_svc + ldr r1, [r3] + msr spsr_cxsf, r1 + + CHANGE_MODE(17) /* change to abt mode */ + /* restore nonvolatile int register */ + ldr r3, .Lsaved_context_r13_abt + ldmia r3, {r13-r14} + /* restore spsr_abt register */ + ldr r3, .Lsaved_spsr_abt + ldr r1, [r3] + msr spsr_cxsf, r1 + + CHANGE_MODE(1b) /* change to und mode */ + /* restore nonvolatile int register */ + ldr r3, .Lsaved_context_r13_und + ldmia r3, {r13-r14} + /* restore spsr_und register */ + ldr r3, .Lsaved_spsr_und + ldr r1, [r3] + msr spsr_cxsf, r1 + + /* go back to original mode */ + msr cpsr_c, r0 + + /* Flush TLB (Invalidate unified TLB unlocked entries) */ + mov r1, #0 + mcr p15, 0, r1, c8, c7, 0 + + /* restore return address */ + ldr r3, .Lsaved_context_r14_svc + ldr lr, [r3] + mov pc, lr + +.Lrestore_pblist: + .word restore_pblist + +FUNC_END(swsusp_arch_resume) diff -purN 12x_old/.config_mindrivers 12x_git/.config_mindrivers --- 12x_old/.config_mindrivers 1970-01-01 05:30:00.000000000 +0530 +++ 12x_git/.config_mindrivers 2009-06-30 11:05:16.000000000 +0530 @@ -0,0 +1,1211 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24.7-omap1-arm2 +# Tue Jun 16 11:50:46 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y + +# +# OMAP Feature Selections +# +CONFIG_OMAP_DEBUG_SRAM_PATCH=y +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_BOOT_TAG=y +CONFIG_OMAP_BOOT_REASON=y +# CONFIG_OMAP_COMPONENT_VERSION is not set +# CONFIG_OMAP_GPIO_SWITCH is not set +CONFIG_OMAP_MUX=y +CONFIG_OMAP_MUX_DEBUG=y +CONFIG_OMAP_MUX_WARNINGS=y +# CONFIG_OMAP_MMU_FWK is not set +# CONFIG_OMAP_MBOX_FWK is not set +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +CONFIG_OMAP_LL_DEBUG_UART1=y +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +# CONFIG_OMAP_LL_DEBUG_UART3 is not set +CONFIG_OMAP_SERIAL_WAKE=y +# CONFIG_HS_SERIAL_SUPPORT is not set +# CONFIG_OMAP_DSI is not set +CONFIG_OMAP_DMA_LIBRARY_CHANNELS=24 +# CONFIG_OMAP3430_ENABLE_SPI2_PIN_MUX is not set +CONFIG_ARCH_OMAP34XX=y +CONFIG_ARCH_OMAP3430=y +CONFIG_OMAP3430_ES2=y +# CONFIG_ARCH_OMAP3410 is not set + +# +# OMAP Board Type +# +CONFIG_MACH_OMAP_3430SDP=y +# CONFIG_MACH_OMAP_3430LABRADOR is not set +# CONFIG_INTERCONNECT_IO_POSTING is not set +CONFIG_OMAP3_PM=y +CONFIG_OMAP_VOLT_SR_BYPASS=y +# CONFIG_OMAP_VOLT_SR is not set +# CONFIG_OMAP_VOLT_VSEL is not set +# CONFIG_OMAP_VOLT_VMODE is not set +CONFIG_OMAP3ES2_VDD1_OPP1=y +# CONFIG_OMAP3ES2_VDD1_OPP2 is not set +# CONFIG_OMAP3ES2_VDD1_OPP3 is not set +# CONFIG_OMAP3ES2_VDD1_OPP4 is not set +# CONFIG_OMAP3ES2_VDD1_OPP5 is not set +# CONFIG_OMAP3_CORE_133MHZ is not set +CONFIG_OMAP3_CORE_166MHZ=y +CONFIG_OMAP3ES2_VDD2_OPP2=y +CONFIG_OMAP3ES2_VDD2_OPP2_L3_83MHZ=y +# CONFIG_OMAP3ES2_VDD2_OPP3_L3_166MHZ is not set +# CONFIG_OMAP3ES2_VDD2_OPP2_L3_66MHZ is not set +# CONFIG_OMAP3ES2_VDD2_OPP3_L3_133MHZ is not set +# CONFIG_ENABLE_VOLTSCALE_IN_SUSPEND is not set +CONFIG_MPU_OFF=y +CONFIG_OMAP34XX_OFFMODE=y +CONFIG_CORE_OFF=y +CONFIG_CORE_OFF_CPUIDLE=y +# CONFIG_SYSOFFMODE is not set +CONFIG_HW_SUP_TRANS=y +# CONFIG_TRACK_RESOURCES is not set +CONFIG_AUTO_POWER_DOMAIN_CTRL=y +# CONFIG_PREVENT_MPU_RET is not set +# CONFIG_PREVENT_CORE_RET is not set +CONFIG_DISABLE_EMUDOMAIN_CONTROL=y +# CONFIG_ENABLE_SWLATENCY_MEASURE is not set +# CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_LOCKDOWN_TO_64K_L2 is not set +# CONFIG_CPU_LOCKDOWN_TO_128K_L2 is not set +CONFIG_CPU_LOCKDOWN_TO_256K_L2=y +CONFIG_CPU_USER_L2_PLE_ACCESS=y +# CONFIG_CPU_L2CACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_OUTER_CACHE is not set +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_451027=y +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=128 +# CONFIG_THUMB2_KERNEL is not set +# CONFIG_ARM_ASM_UNIFIED is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_OPROFILE_ARMV7=y + +# +# CPUIdle +# + +# +# CPI idle PM support +# +CONFIG_CPU_IDLE=y + +# +# Governors +# +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_NEON_CACHE_BUG=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +CONFIG_PM_DEBUG=y +CONFIG_PM_VERBOSE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_UP_POSSIBLE=y +CONFIG_SUSPEND=y +CONFIG_HIBERNATION_UP_POSSIBLE=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_SWSUSP_MTDBLOCK_FLUSH is not set +# CONFIG_APM_EMULATION is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_NL80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_OMAP_NOR=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_OMAP_HWECC=y +CONFIG_MTD_NAND_OMAP_PREFETCH=y +CONFIG_MTD_NAND_OMAP_PREFETCH_MPU=y +# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +# CONFIG_MTD_ONENAND_GENERIC is not set +CONFIG_MTD_ONENAND_OMAP2=y +# CONFIG_MTD_ONENAND_OTP is not set +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set +# CONFIG_MTD_ONENAND_SIM is not set +CONFIG_MTD_ONENAND_SYNC_BURST_READ=y + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +CONFIG_TWL4030_MADC=y + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_OMAP=y +CONFIG_SERIAL_OMAP_CONSOLE=y +# CONFIG_SERIAL_OMAP_DMA_UART1 is not set +CONFIG_SERIAL_OMAP_DMA_UART2=y +CONFIG_SERIAL_OMAP_UART2_RXDMA_TIMEOUT=1 +CONFIG_SERIAL_OMAP_UART2_RXDMA_BUFSIZE=4096 +# CONFIG_SERIAL_OMAP_DMA_UART3 is not set +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y + +# +# OMAP34XX HS I2C buses +# +CONFIG_I2C_OMAP34XX_HS_BUS1=2600 +CONFIG_I2C_OMAP34XX_HS_BUS2=100 +CONFIG_I2C_OMAP34XX_HS_BUS3=400 +CONFIG_OMAP_I2C_SLAVE=y +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_ISP1301_OMAP is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_TLV320AIC23 is not set +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_DBG_SYSFS=y +CONFIG_TWL4030_IRQ_PRIO=26 +CONFIG_TWL4030_GPIO=y +CONFIG_TWL4030_USB=y +CONFIG_TWL4030_USB_HS_ULPI=y +# CONFIG_TWL4030_DETECT_USB_CABLE_TYPE is not set +# CONFIG_TWL4030_POWEROFF is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS1WM is not set +CONFIG_HDQ_MASTER_OMAP=y + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +CONFIG_W1_SLAVE_BQ27000=y +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +CONFIG_TWL4030_BCI_BATTERY=y +CONFIG_BATTERY_BQ27000=y +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_FB_OMAP_LCD_VGA is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set + +# +# Synchronous Serial Interfaces (SSI) +# +# CONFIG_OMAP_MCBSP is not set + +# +# McBSP fifo support +# +CONFIG_USE_MCBSP_FIFO=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_OMAP_HS=y +CONFIG_OMAP_HS_MMC1=y +# CONFIG_OMAP_HS_MMC2 is not set +# CONFIG_OMAP_SDIO_NON_DMA_MODE is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +CONFIG_RTC_DRV_TWL4030=y + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# + +# +# CBUS support +# +# CONFIG_CBUS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +# CONFIG_WANT_EXTRA_DEBUG_INFORMATION is not set +# CONFIG_UNWIND_INFO is not set +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -purN 12x_git/drivers/mmc/core/core.c 2.6.24.7-linux/drivers/mmc/core/core.c --- 12x_git/drivers/mmc/core/core.c 2009-07-08 12:15:46.000000000 +0530 +++ 2.6.24.7-linux/drivers/mmc/core/core.c 2009-07-09 09:55:43.000000000 +0530 @@ -619,8 +619,8 @@ void mmc_detect_change(struct mmc_host * WARN_ON(host->removed); spin_unlock_irqrestore(&host->lock, flags); #endif - - mmc_schedule_delayed_work(&host->detect, delay); + mmc_rescan(&host->detect.work); + //mmc_schedule_delayed_work(&host->detect, delay); } EXPORT_SYMBOL(mmc_detect_change); @@ -688,6 +688,7 @@ void mmc_rescan(struct work_struct *work mmc_bus_put(host); } } +EXPORT_SYMBOL(mmc_rescan); void mmc_start_host(struct mmc_host *host) { diff -purN 12x_git/drivers/mmc/host/omap_hsmmc.c 2.6.24.7-linux/drivers/mmc/host/omap_hsmmc.c --- 12x_git/drivers/mmc/host/omap_hsmmc.c 2009-07-08 12:15:46.000000000 +0530 +++ 2.6.24.7-linux/drivers/mmc/host/omap_hsmmc.c 2009-07-09 10:14:46.000000000 +0530 @@ -139,6 +137,8 @@ static int bytec; #endif +extern void mmc_rescan(struct work_struct *); + struct mmc_omap_host { struct device *dev; struct mmc_host *mmc; @@ -1398,7 +1395,8 @@ static int __init omap_mmc_probe(struct platform_set_drvdata(pdev, host); mmc_add_host(mmc); - + cancel_delayed_work(&mmc->detect.work); + mmc_rescan(&mmc->detect.work); return 0; err: diff -purN 12x_old/include/asm-arm/page.h 12x_git/include/asm-arm/page.h --- 12x_old/include/asm-arm/page.h 2009-06-30 14:29:37.000000000 +0530 +++ 12x_git/include/asm-arm/page.h 2009-06-30 11:26:56.000000000 +0530 @@ -178,6 +178,8 @@ typedef unsigned long pgprot_t; #include +#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) + #endif /* !__ASSEMBLY__ */ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ diff -purN 12x_old/include/asm-arm/suspend.h 12x_git/include/asm-arm/suspend.h --- 12x_old/include/asm-arm/suspend.h 2009-06-30 14:29:37.000000000 +0530 +++ 12x_git/include/asm-arm/suspend.h 2009-06-30 11:14:10.000000000 +0530 @@ -1,4 +1,81 @@ #ifndef _ASMARM_SUSPEND_H #define _ASMARM_SUSPEND_H +/* + * Based on code include/asm-i386/suspend.h + * Copyright 2001-2002 Pavel Machek + * Copyright 2001 Patrick Mochel + */ + +#include + +static inline int +arch_prepare_suspend(void) +{ + return 0; +} + +/* image of the saved processor state */ +struct saved_context { + /* + * Structure saved_context would be used to hold processor state + * except caller and callee registers, just before suspending. + */ + + /* coprocessor 15 registers */ +// __u32 ID_code; /* read only reg */ +// __u32 cache_type; /* read only reg */ +// __u32 TCM_stat; /* read only reg */ + __u32 CR; + __u32 DACR; + __u32 D_FSR; + __u32 I_FSR; + __u32 D_FAR; + __u32 I_FAR; +// __u32 COR; /*write only reg */ +// __u32 TLBOR; /*write only reg */ + __u32 D_CLR; + __u32 I_CLR; + __u32 D_TCMRR; + __u32 I_TCMRR; + __u32 D_TLBLR; + __u32 FCSE; + __u32 CID; + __u32 CSSR; + __u32 CACR; + __u32 TTB_0R; + __u32 TTB_1R; + __u32 TTBCR; + __u32 D_AFSR; + __u32 I_AFSR; + __u32 PAR; + __u32 PMControlR; + __u32 CESR; + __u32 CECR; + __u32 OFSR; + __u32 SIR; + __u32 PCSR; + __u32 CCR; + __u32 ESR; + __u32 PMCountR; + __u32 UER; + __u32 IESR; + __u32 IECR; + __u32 L2CLR; + __u32 I_TLBLR; + __u32 PRRR; + __u32 NRRR; + __u32 PLEUAR; + __u32 PLECNR; + __u32 PLECR; + __u32 PLEISAR; + __u32 PLEIEAR; + __u32 PLECIDR; + __u32 SNSVBAR; + __u32 URWTPID; + __u32 UROTPID; + __u32 POTPID; + __u32 r0; +} __attribute__((packed)); + #endif diff -purN 12x_old/kernel/power/disk.c 12x_git/kernel/power/disk.c --- 12x_old/kernel/power/disk.c 2009-06-30 14:29:37.000000000 +0530 +++ 12x_git/kernel/power/disk.c 2009-06-30 11:14:50.000000000 +0530 @@ -21,6 +21,7 @@ #include #include #include +#include #include "power.h" diff -purN 12x_old/kernel/power/Kconfig 12x_git/kernel/power/Kconfig --- 12x_old/kernel/power/Kconfig 2009-06-30 14:29:37.000000000 +0530 +++ 12x_git/kernel/power/Kconfig 2009-06-30 11:10:36.000000000 +0530 @@ -99,7 +99,7 @@ config SUSPEND config HIBERNATION_UP_POSSIBLE bool - depends on X86 || PPC64_SWSUSP || PPC32 + depends on X86 || PPC64_SWSUSP || PPC32 || ARM depends on !SMP default y From patchwork Wed Mar 17 22:42:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Olaya, Margarita" X-Patchwork-Id: 86563 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2HMgdmo021239 for ; Wed, 17 Mar 2010 22:42:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756173Ab0CQWmj (ORCPT ); Wed, 17 Mar 2010 18:42:39 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51524 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755278Ab0CQWmi convert rfc822-to-8bit (ORCPT ); Wed, 17 Mar 2010 18:42:38 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2HMgUUt009704 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 17 Mar 2010 17:42:31 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o2HMgUfL021553; Wed, 17 Mar 2010 17:42:30 -0500 (CDT) Received: from dsbe71.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2HMgUin000070; Wed, 17 Mar 2010 17:42:30 -0500 (CDT) Received: from dlee06.ent.ti.com ([157.170.170.11]) by dsbe71.ent.ti.com ([156.117.232.23]) with mapi; Wed, 17 Mar 2010 17:42:30 -0500 From: "Olaya, Margarita" To: "alsa-devel@alsa-project.org" , "linux-omap@vger.kernel.org" CC: "broonie@opensource.wolfsonmicro.com" , "lrg@slimlogic.co.uk" Date: Wed, 17 Mar 2010 17:42:29 -0500 Subject: [PATCHv2 1/2] OMAP4: PMIC: Rename twl6030_codec as twl6040_codec Thread-Topic: [PATCHv2 1/2] OMAP4: PMIC: Rename twl6030_codec as twl6040_codec Thread-Index: AcrGIx/nBNde6E7nRUiD9SSIQQwiqA== Message-ID: <1889FA7136B567478A67D4B0F85B0CCE662AC371@dlee06.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Mar 2010 22:42:40 +0000 (UTC) diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index 562cd49..720e099 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -109,7 +109,7 @@ #endif #if defined(CONFIG_TWL4030_CODEC) || defined(CONFIG_TWL4030_CODEC_MODULE) ||\ - defined(CONFIG_SND_SOC_TWL6030) || defined(CONFIG_SND_SOC_TWL6030_MODULE) + defined(CONFIG_SND_SOC_TWL6040) || defined(CONFIG_SND_SOC_TWL6040_MODULE) #define twl_has_codec() true #else #define twl_has_codec() false @@ -708,7 +708,7 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features) /* Phoenix*/ if (twl_has_codec() && pdata->codec && twl_class_is_6030()) { sub_chip_id = twl_map[TWL_MODULE_AUDIO_VOICE].sid; - child = add_child(sub_chip_id, "twl6030_codec", + child = add_child(sub_chip_id, "twl6040_codec", pdata->codec, sizeof(*pdata->codec), false, 0, 0); if (IS_ERR(child)) diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index fb6784e..ebd90ce 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -569,9 +569,9 @@ struct twl4030_codec_data { struct twl4030_codec_audio_data *audio; struct twl4030_codec_vibra_data *vibra; - /* twl6030 */ - int audpwron_gpio; /* audio power-on gpio */ - int naudint_irq; /* audio interrupt */ + /* twl6040 */ + int audpwron_gpio; /* audio power-on gpio */ + int naudint_irq; /* audio interrupt */ }; struct twl4030_platform_data { From patchwork Sun May 16 15:45:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99967 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkHfb025161 for ; Sun, 16 May 2010 15:46:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753221Ab0EPPqQ (ORCPT ); Sun, 16 May 2010 11:46:16 -0400 Received: from fg-out-1718.google.com ([72.14.220.157]:34390 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753138Ab0EPPqP (ORCPT ); Sun, 16 May 2010 11:46:15 -0400 Received: by fg-out-1718.google.com with SMTP id 22so178499fge.1 for ; Sun, 16 May 2010 08:46:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=6GIFzWJNcEnpHANHX8qwqEXG5qGnRisk+C9Jkl3qSnk=; b=NZo8VYdQq6wheh56hfoRjWBvlKzfZ9DCXzX/jTVomfOfr6FumH7SSQVN7vNyCWLYDq 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<1274024765-21076-4-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:17 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/mmu_fault.c b/drivers/dsp/bridge/core/mmu_fault.c index 883f45d..1de9cb4 100644 --- a/drivers/dsp/bridge/core/mmu_fault.c +++ b/drivers/dsp/bridge/core/mmu_fault.c @@ -42,11 +42,8 @@ #include "_tiomap.h" #include "mmu_fault.h" -static u32 dmmu_event_mask; u32 fault_addr; -static bool mmu_check_if_fault(struct bridge_dev_context *dev_context); - /* * ======== mmu_fault_dpc ======== * Deferred procedure call to handle DSP MMU fault. @@ -55,9 +52,10 @@ void mmu_fault_dpc(IN unsigned long pRefData) { struct deh_mgr *hdeh_mgr = (struct deh_mgr *)pRefData; - if (hdeh_mgr) - bridge_deh_notify(hdeh_mgr, DSP_MMUFAULT, 0L); + if (!hdeh_mgr) + return; + bridge_deh_notify(hdeh_mgr, DSP_MMUFAULT, 0L); } /* @@ -66,76 +64,44 @@ void mmu_fault_dpc(IN unsigned long pRefData) */ irqreturn_t mmu_fault_isr(int irq, IN void *pRefData) { - struct deh_mgr *deh_mgr_obj = (struct deh_mgr *)pRefData; - struct bridge_dev_context *dev_context; + struct deh_mgr *deh_mgr_obj = pRefData; struct cfg_hostres *resources; + u32 dmmu_event_mask; - DBC_REQUIRE(irq == INT_DSP_MMU_IRQ); - DBC_REQUIRE(deh_mgr_obj); - - if (deh_mgr_obj) { - - dev_context = - (struct bridge_dev_context *)deh_mgr_obj->hbridge_context; - - resources = dev_context->resources; + if (!deh_mgr_obj) + return IRQ_HANDLED; - if (!resources) { - dev_dbg(bridge, "%s: Failed to get Host Resources\n", + resources = deh_mgr_obj->hbridge_context->resources; + if (!resources) { + dev_dbg(bridge, "%s: Failed to get Host Resources\n", __func__); - return IRQ_HANDLED; - } - if (mmu_check_if_fault(dev_context)) { - printk(KERN_INFO "***** DSPMMU FAULT ***** IRQStatus " - "0x%x\n", dmmu_event_mask); - printk(KERN_INFO "***** DSPMMU FAULT ***** fault_addr " - "0x%x\n", fault_addr); - /* - * Schedule a DPC directly. In the future, it may be - * necessary to check if DSP MMU fault is intended for - * Bridge. - */ - tasklet_schedule(&deh_mgr_obj->dpc_tasklet); - - /* Reset err_info structure before use. */ - deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT; - deh_mgr_obj->err_info.dw_val1 = fault_addr >> 16; - deh_mgr_obj->err_info.dw_val2 = fault_addr & 0xFFFF; - deh_mgr_obj->err_info.dw_val3 = 0L; - /* Disable the MMU events, else once we clear it will - * start to raise INTs again */ - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_TRANSLATION_FAULT); - } else { - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_ALL_INTERRUPTS); - } + return IRQ_HANDLED; } - return IRQ_HANDLED; -} -/* - * ======== mmu_check_if_fault ======== - * Check to see if MMU Fault is valid TLB miss from DSP - * Note: This function is called from an ISR - */ -static bool mmu_check_if_fault(struct bridge_dev_context *dev_context) -{ - - bool ret = false; - hw_status hw_status_obj; - struct cfg_hostres *resources = dev_context->resources; - - if (!resources) { - dev_dbg(bridge, "%s: Failed to get Host Resources in\n", - __func__); - return ret; - } - hw_status_obj = - hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); + hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); if (dmmu_event_mask == HW_MMU_TRANSLATION_FAULT) { hw_mmu_fault_addr_read(resources->dw_dmmu_base, &fault_addr); - ret = true; + dev_info(bridge, "%s: status=0x%x, fault_addr=0x%x\n", __func__, + dmmu_event_mask, fault_addr); + /* + * Schedule a DPC directly. In the future, it may be + * necessary to check if DSP MMU fault is intended for + * Bridge. + */ + tasklet_schedule(&deh_mgr_obj->dpc_tasklet); + + /* Reset err_info structure before use. */ + deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT; + deh_mgr_obj->err_info.dw_val1 = fault_addr >> 16; + deh_mgr_obj->err_info.dw_val2 = fault_addr & 0xFFFF; + deh_mgr_obj->err_info.dw_val3 = 0L; + /* Disable the MMU events, else once we clear it will + * start to raise INTs again */ + hw_mmu_event_disable(resources->dw_dmmu_base, + HW_MMU_TRANSLATION_FAULT); + } else { + hw_mmu_event_disable(resources->dw_dmmu_base, + HW_MMU_ALL_INTERRUPTS); } - return ret; + return IRQ_HANDLED; } From patchwork Wed Jul 21 09:45:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Carmody X-Patchwork-Id: 113323 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6L9jjHg019913 for ; Wed, 21 Jul 2010 09:45:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750765Ab0GUJpo (ORCPT ); Wed, 21 Jul 2010 05:45:44 -0400 Received: from smtp.nokia.com ([192.100.122.233]:26659 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750712Ab0GUJpo convert rfc822-to-8bit (ORCPT ); Wed, 21 Jul 2010 05:45:44 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o6L9jbgx006131; Wed, 21 Jul 2010 12:45:38 +0300 Received: from vaebh102.NOE.Nokia.com ([10.160.244.23]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 21 Jul 2010 12:45:37 +0300 Received: from smtp.mgd.nokia.com ([65.54.30.7]) by vaebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 21 Jul 2010 12:45:32 +0300 Received: from NOK-EUMSG-01.mgdnok.nokia.com ([65.54.30.86]) by nok-am1mhub-03.mgdnok.nokia.com ([65.54.30.7]) with mapi; Wed, 21 Jul 2010 11:45:31 +0200 From: To: , , , CC: Date: Wed, 21 Jul 2010 11:45:30 +0200 Subject: RE: [PATCH 2/2] omap:mailbox-provide multiple reader support Thread-Topic: [PATCH 2/2] omap:mailbox-provide multiple reader support Thread-Index: AcsoUy+WuFRkTH1JR1CTKCj3At5I1gAZSLiE Message-ID: <702744BC498BAE41B3AA631D95EC463058B3CFD799@NOK-EUMSG-01.mgdnok.nokia.com> References: <1279662096-3121-1-git-send-email-h-kanigeri2@ti.com>, <1279662096-3121-3-git-send-email-h-kanigeri2@ti.com> In-Reply-To: <1279662096-3121-3-git-send-email-h-kanigeri2@ti.com> Accept-Language: en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 X-OriginalArrivalTime: 21 Jul 2010 09:45:32.0240 (UTC) FILETIME=[75E82500:01CB28B9] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 09:45:46 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h index 0486d64..c8e47d8 100644 --- a/arch/arm/plat-omap/include/plat/mailbox.h +++ b/arch/arm/plat-omap/include/plat/mailbox.h @@ -68,13 +68,15 @@ struct omap_mbox { void *priv; void (*err_notify)(void); + atomic_t use_count; + struct blocking_notifier_head notifier; }; int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); void omap_mbox_init_seq(struct omap_mbox *); -struct omap_mbox *omap_mbox_get(const char *); -void omap_mbox_put(struct omap_mbox *); +struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb); +void omap_mbox_put(struct omap_mbox *, struct notifier_block *nb); int omap_mbox_register(struct device *parent, struct omap_mbox *); int omap_mbox_unregister(struct omap_mbox *); diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index baac315..f9f2af4 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -149,8 +149,8 @@ static void mbox_rx_work(struct work_struct *work) if (unlikely(len != sizeof(msg))) pr_err("%s: kfifo_out anomaly detected\n", __func__); - if (mq->callback) - mq->callback((void *)msg); + blocking_notifier_call_chain(&mq->mbox->notifier, len, + (void *)msg); } } @@ -252,28 +252,30 @@ static int omap_mbox_startup(struct omap_mbox *mbox) } } - ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, - mbox->name, mbox); - if (unlikely(ret)) { - printk(KERN_ERR - "failed to register mailbox interrupt:%d\n", ret); - goto fail_request_irq; - } + if (atomic_inc_return(&mbox->use_count) == 1) { + ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, + mbox->name, mbox); + if (unlikely(ret)) { + printk(KERN_ERR "failed to register mailbox interrupt:" + "%d\n", ret); + goto fail_request_irq; + } - mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); - if (!mq) { - ret = -ENOMEM; - goto fail_alloc_txq; - } - mbox->txq = mq; + mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); + if (!mq) { + ret = -ENOMEM; + goto fail_alloc_txq; + } + mbox->txq = mq; - mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); - if (!mq) { - ret = -ENOMEM; - goto fail_alloc_rxq; + mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); + if (!mq) { + ret = -ENOMEM; + goto fail_alloc_rxq; + } + mbox->rxq = mq; + mq->mbox = mbox; } - mbox->rxq = mq; - return 0; fail_alloc_rxq: @@ -281,6 +283,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox) fail_alloc_txq: free_irq(mbox->irq, mbox); fail_request_irq: + atomic_dec(&mbox->use_count); if (likely(mbox->ops->shutdown)) { if (atomic_dec_return(&mbox_refcount) == 0) mbox->ops->shutdown(mbox); @@ -291,10 +294,12 @@ static int omap_mbox_startup(struct omap_mbox *mbox) static void omap_mbox_fini(struct omap_mbox *mbox) { - mbox_queue_free(mbox->txq); - mbox_queue_free(mbox->rxq); - free_irq(mbox->irq, mbox); + if (atomic_dec_return(&mbox->use_count) == 0) { + mbox_queue_free(mbox->txq); + mbox_queue_free(mbox->rxq); + free_irq(mbox->irq, mbox); + } if (likely(mbox->ops->shutdown)) { if (atomic_dec_return(&mbox_refcount) == 0) @@ -314,7 +319,7 @@ static struct omap_mbox **find_mboxes(const char *name) return p; } -struct omap_mbox *omap_mbox_get(const char *name) +struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb) { struct omap_mbox *mbox; int ret; @@ -325,19 +330,21 @@ struct omap_mbox *omap_mbox_get(const char *name) spin_unlock(&mboxes_lock); return ERR_PTR(-ENOENT); } - spin_unlock(&mboxes_lock); ret = omap_mbox_startup(mbox); if (ret) return ERR_PTR(-ENODEV); + if (nb) + blocking_notifier_chain_register(&mbox->notifier, nb); return mbox; } EXPORT_SYMBOL(omap_mbox_get); -void omap_mbox_put(struct omap_mbox *mbox) +void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb) { + blocking_notifier_chain_unregister(&mbox->notifier, nb); omap_mbox_fini(mbox); } EXPORT_SYMBOL(omap_mbox_put); @@ -361,6 +368,8 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) } *tmp = mbox; spin_unlock(&mboxes_lock); + BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier); + atomic_set(&mbox->use_count, 0); return 0; From patchwork Thu Jun 17 10:40:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106662 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAfMKL010610 for ; Thu, 17 Jun 2010 10:41:22 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759799Ab0FQKk5 (ORCPT ); Thu, 17 Jun 2010 06:40:57 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:55630 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757970Ab0FQKk4 (ORCPT ); Thu, 17 Jun 2010 06:40:56 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAelvQ027219 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:50 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAejM0015343; Thu, 17 Jun 2010 16:10:45 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAej1a005310; Thu, 17 Jun 2010 16:10:45 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAejsE005307; Thu, 17 Jun 2010 16:10:45 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Maulik Mankad , David Brownell , Ajay Kumar Gupta Subject: [PATCH 8/8] usb: musb: Fix suspend interrupt issue in device mode Date: Thu, 17 Jun 2010 16:10:42 +0530 Message-Id: <1276771242-5201-10-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-9-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> <1276771242-5201-5-git-send-email-ajay.gupta@ti.com> <1276771242-5201-6-git-send-email-ajay.gupta@ti.com> <1276771242-5201-7-git-send-email-ajay.gupta@ti.com> <1276771242-5201-8-git-send-email-ajay.gupta@ti.com> <1276771242-5201-9-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:22 +0000 (UTC) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 4f43db7..64b08f9 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -635,7 +635,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, handled = IRQ_HANDLED; } - +#endif if (int_usb & MUSB_INTR_SUSPEND) { DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", otg_state_string(musb), devctl, power); @@ -698,6 +698,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, } } +#ifdef CONFIG_USB_MUSB_HDRC_HCD if (int_usb & MUSB_INTR_CONNECT) { struct usb_hcd *hcd = musb_to_hcd(musb); From patchwork Thu Jun 17 10:40:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106663 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAfRCL010627 for ; Thu, 17 Jun 2010 10:41:27 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759863Ab0FQKlW (ORCPT ); Thu, 17 Jun 2010 06:41:22 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:55632 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759733Ab0FQKk4 (ORCPT ); Thu, 17 Jun 2010 06:40:56 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAek19027218 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:49 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAeh1E015337; Thu, 17 Jun 2010 16:10:44 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAehW3005272; Thu, 17 Jun 2010 16:10:43 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAehHr005269; Thu, 17 Jun 2010 16:10:43 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Ajay Kumar Gupta Subject: [PATCH 3/8] musb: fix compilation warning in host only mode Date: Thu, 17 Jun 2010 16:10:36 +0530 Message-Id: <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:27 +0000 (UTC) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index f0ff893..7cc8398 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -455,6 +455,9 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, u8 devctl, u8 power) { irqreturn_t handled = IRQ_NONE; +#ifdef CONFIG_USB_MUSB_HDRC_HCD + void __iomem *mbase = musb->mregs; +#endif DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, int_usb); @@ -469,8 +472,6 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, if (devctl & MUSB_DEVCTL_HM) { #ifdef CONFIG_USB_MUSB_HDRC_HCD - void __iomem *mbase = musb->mregs; - switch (musb->xceiv->state) { case OTG_STATE_A_SUSPEND: /* remote wakeup? later, GetPortStatus @@ -548,8 +549,6 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, #ifdef CONFIG_USB_MUSB_HDRC_HCD /* see manual for the order of the tests */ if (int_usb & MUSB_INTR_SESSREQ) { - void __iomem *mbase = musb->mregs; - DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); /* IRQ arrives from ID pin sense or (later, if VBUS power @@ -598,8 +597,6 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, case OTG_STATE_A_WAIT_BCON: case OTG_STATE_A_WAIT_VRISE: if (musb->vbuserr_retry) { - void __iomem *mbase = musb->mregs; - musb->vbuserr_retry--; ignore = 1; devctl |= MUSB_DEVCTL_SESSION; @@ -703,7 +700,6 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, if (int_usb & MUSB_INTR_CONNECT) { struct usb_hcd *hcd = musb_to_hcd(musb); - void __iomem *mbase = musb->mregs; handled = IRQ_HANDLED; musb->is_active = 1; From patchwork Thu Jun 17 10:40:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106660 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAfIEL010591 for ; Thu, 17 Jun 2010 10:41:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932692Ab0FQKlO (ORCPT ); Thu, 17 Jun 2010 06:41:14 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:44623 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759754Ab0FQKk5 (ORCPT ); Thu, 17 Jun 2010 06:40:57 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAekeQ031879 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:49 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAeiG9015340; Thu, 17 Jun 2010 16:10:44 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAeiNk005292; Thu, 17 Jun 2010 16:10:44 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAeisv005289; Thu, 17 Jun 2010 16:10:44 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Hema HK , Anand Gadiyar , Ajay Kumar Gupta Subject: [PATCH 6/8] usb: musb: Enable the maximum supported burst mode for DMA Date: Thu, 17 Jun 2010 16:10:39 +0530 Message-Id: <1276771242-5201-7-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-6-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> <1276771242-5201-5-git-send-email-ajay.gupta@ti.com> <1276771242-5201-6-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:18 +0000 (UTC) diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index 1008044..dc66e43 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c @@ -132,18 +132,9 @@ static void configure_channel(struct dma_channel *channel, if (mode) { csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; BUG_ON(len < packet_sz); - - if (packet_sz >= 64) { - csr |= MUSB_HSDMA_BURSTMODE_INCR16 - << MUSB_HSDMA_BURSTMODE_SHIFT; - } else if (packet_sz >= 32) { - csr |= MUSB_HSDMA_BURSTMODE_INCR8 - << MUSB_HSDMA_BURSTMODE_SHIFT; - } else if (packet_sz >= 16) { - csr |= MUSB_HSDMA_BURSTMODE_INCR4 - << MUSB_HSDMA_BURSTMODE_SHIFT; - } } + csr |= MUSB_HSDMA_BURSTMODE_INCR16 + << MUSB_HSDMA_BURSTMODE_SHIFT; csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) | (1 << MUSB_HSDMA_ENABLE_SHIFT) From patchwork Thu Jun 17 10:40:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106661 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAfIEM010591 for ; Thu, 17 Jun 2010 10:41:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932535Ab0FQKlO (ORCPT ); Thu, 17 Jun 2010 06:41:14 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:40587 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757970Ab0FQKk6 (ORCPT ); Thu, 17 Jun 2010 06:40:58 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAelMG025791 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:50 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAeiMd015338; Thu, 17 Jun 2010 16:10:44 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAeivB005279; Thu, 17 Jun 2010 16:10:44 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAehPv005275; Thu, 17 Jun 2010 16:10:43 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Jon Povey , Ajay Kumar Gupta Subject: [PATCH 4/8] USB: musb: suppress warning about unused flags Date: Thu, 17 Jun 2010 16:10:37 +0530 Message-Id: <1276771242-5201-5-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:19 +0000 (UTC) diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c index 59dc3d3..e3753ba 100644 --- a/drivers/usb/musb/cppi_dma.c +++ b/drivers/usb/musb/cppi_dma.c @@ -1155,7 +1155,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id) struct musb_hw_ep *hw_ep = NULL; u32 rx, tx; int i, index; - unsigned long flags; + unsigned long uninitialized_var(flags); cppi = container_of(musb->dma_controller, struct cppi, controller); if (cppi->irq) From patchwork Sat May 15 18:21:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 99840 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4FILNQF001402 for ; Sat, 15 May 2010 18:21:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752322Ab0EOSVW (ORCPT ); Sat, 15 May 2010 14:21:22 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:44552 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751792Ab0EOSVV (ORCPT ); Sat, 15 May 2010 14:21:21 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4FILAVH031012 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 15 May 2010 13:21:10 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4FIL2SD002246; Sat, 15 May 2010 13:21:03 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099945); by dbdmail.itg.ti.com with HTTP; Sat, 15 May 2010 23:51:06 +0530 (IST) Message-ID: <22485.10.24.255.17.1273947666.squirrel@dbdmail.itg.ti.com> Date: Sat, 15 May 2010 23:51:06 +0530 (IST) Subject: [PATCH v4 1/5] OMAP4 HSMMC: Adding hsmmc support to board file From: "kishore kadiyala" To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: tony@atomide.com, madhu.cr@ti.com, jarkko.lavinen@nokia.com, rmk@arm.linux.org.uk, paul@pwsan.com, adrian.hunter@nokia.com, santosh.shilimkar@ti.com User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 15 May 2010 18:21:23 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 203a414..a799453 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -137,7 +137,8 @@ obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o -obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o +obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 921cde3..e4a5d66 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include "hsmmc.h" #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 @@ -137,24 +139,66 @@ static struct omap_musb_board_data musb_board_data = { .mode = MUSB_PERIPHERAL, .power = 100, }; -static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { - { - .supply = "vmmc", - }, + +static struct omap2_hsmmc_info mmc[] = { { - .supply = "vmmc", + .mmc = 1, + .wires = 8, + .gpio_wp = -EINVAL, }, { - .supply = "vmmc", + .mmc = 2, + .wires = 8, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + .nonremovable = true, }, + {} /* Terminator */ +}; + +static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { { .supply = "vmmc", + .dev_name = "mmci-omap-hs.0", }, { .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", }, }; +static int omap4_twl6030_hsmmc_late_init(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_mmc_platform_data *pdata = dev->platform_data; + + /* Setting MMC1 Card detect Irq */ + if (pdev->id == 0) + pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + + MMCDETECT_INTR_OFFSET; + return ret; +} + +static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *pdata = dev->platform_data; + + pdata->init = omap4_twl6030_hsmmc_late_init; +} + +static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + + omap2_hsmmc_init(controllers); + for (c = controllers; c->mmc; c++) + omap4_twl6030_hsmmc_set_late_init(c->dev); + + return 0; +} + static struct regulator_init_data sdp4430_vaux1 = { .constraints = { .min_uV = 1000000, @@ -206,7 +250,7 @@ static struct regulator_init_data sdp4430_vmmc = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 5, + .num_consumer_supplies = 2, .consumer_supplies = sdp4430_vmmc_supply, }; @@ -329,6 +373,7 @@ static void __init omap_4430sdp_init(void) omap4_i2c_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); + omap4_twl6030_hsmmc_init(mmc); /* OMAP4 SDP uses internal transceiver so register nop transceiver */ usb_nop_xceiv_register(); /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ From patchwork Wed May 5 14:27:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97105 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5P9002693 for ; Wed, 5 May 2010 14:28:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934796Ab0EEO2H (ORCPT ); Wed, 5 May 2010 10:28:07 -0400 Received: from smtp.nokia.com ([192.100.122.230]:65000 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934695Ab0EEO2D (ORCPT ); Wed, 5 May 2010 10:28:03 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERY10008151; Wed, 5 May 2010 17:27:59 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:50 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:49 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfR6016232; Wed, 5 May 2010 17:27:48 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 04/21] OMAP: DSS2: Taal: Cosmetic improvement to backlight properties initialization Date: Wed, 5 May 2010 17:27:24 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:49.0694 (UTC) FILETIME=[239BC5E0:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:14 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 0eed328..53fc369 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -559,7 +559,7 @@ static int taal_probe(struct omap_dss_device *dssdev) /* if no platform set_backlight() defined, presume DSI backlight * control */ - memset(&props, 0, sizeof(struct backlight_properties)); + memset(&props, 0, sizeof(props)); if (!dssdev->set_backlight) td->use_dsi_bl = true; From patchwork Fri Mar 19 11:21:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 86916 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2JBLXrB013827 for ; Fri, 19 Mar 2010 11:21:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751618Ab0CSLVa (ORCPT ); Fri, 19 Mar 2010 07:21:30 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:36453 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751380Ab0CSLV3 (ORCPT ); Fri, 19 Mar 2010 07:21:29 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2JBLMnA016289 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 19 Mar 2010 06:21:24 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2JBLJ0c007720; Fri, 19 Mar 2010 16:51:19 +0530 (IST) From: hvaibhav@ti.com To: linux-omap@vger.kernel.org Cc: tomi.valkeinen@nokia.com, tony@atomide.com, Vaibhav Hiremath Subject: [PATCH-V2] OMAP3EVM: Replace vdvi regulator supply with vdds_dsi Date: Fri, 19 Mar 2010 16:51:19 +0530 Message-Id: <1268997679-27869-1-git-send-email-hvaibhav@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: References: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 19 Mar 2010 11:21:34 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 017bb2f..74bbdcb 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -514,14 +514,11 @@ static struct regulator_init_data omap3_evm_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_evm_vpll2_supply = { - .supply = "vdvi", - .dev = &omap3_evm_lcd_device.dev, -}; +static struct regulator_consumer_supply omap3_evm_vpll2_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); static struct regulator_init_data omap3_evm_vpll2 = { .constraints = { - .name = "VDVI", .min_uV = 1800000, .max_uV = 1800000, .apply_uV = true, From patchwork Mon Feb 1 22:10:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 76172 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o11MBLe1031133 for ; Mon, 1 Feb 2010 22:11:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753215Ab0BAWKm (ORCPT ); Mon, 1 Feb 2010 17:10:42 -0500 Received: from utopia.booyaka.com ([72.9.107.138]:47085 "EHLO utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752711Ab0BAWKl (ORCPT ); Mon, 1 Feb 2010 17:10:41 -0500 Received: (qmail 951 invoked by uid 1019); 1 Feb 2010 22:10:40 -0000 Date: Mon, 1 Feb 2010 15:10:40 -0700 (MST) From: Paul Walmsley To: Tero Kristo cc: linux-omap@vger.kernel.org Subject: Re: [PATCHv4 1/8] OMAP3: Clockdomain: Added API for checking if HWSUP is enabled In-Reply-To: <1264182951-9205-2-git-send-email-tero.kristo@nokia.com> Message-ID: References: <> <1264182951-9205-1-git-send-email-tero.kristo@nokia.com> <1264182951-9205-2-git-send-email-tero.kristo@nokia.com> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 01 Feb 2010 22:11:21 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index a38a615..8dce3c9 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -868,6 +868,36 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) } /** + * omap2_clkdm_read_hwsup - read the hwsup idle transition bit + * @clkdm: struct clockdomain * + * + * Checks whether hardware is allowed to switch the clockdomain @clkdm + * automatically into active or idle states. Returns -EINVAL if @clkdm + * is NULL; otherwise, 1 if hardware auto-idle is enabled, 0 if not. + */ +int omap2_clkdm_read_hwsup(struct clockdomain *clkdm) +{ + u32 u, v; + + if (!clkdm) + return -EINVAL; + + u = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + u &= clkdm->clktrctrl_mask; + + if (cpu_is_omap24xx()) + v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; + else if (cpu_is_omap34xx() || cpu_is_omap44xx()) + v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; + else + BUG(); + + v <<= __ffs(clkdm->clktrctrl_mask); + + return (u == v) ? 1 : 0; +} + +/** * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm * @clkdm: struct clockdomain * * diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h index ba0a6c0..9d25f4e 100644 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ b/arch/arm/plat-omap/include/plat/clockdomain.h @@ -129,6 +129,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); +int omap2_clkdm_read_hwsup(struct clockdomain *clkdm); void omap2_clkdm_allow_idle(struct clockdomain *clkdm); void omap2_clkdm_deny_idle(struct clockdomain *clkdm); From patchwork Tue Mar 2 10:29:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aggarwal, Anuj" X-Patchwork-Id: 83167 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o22AU0jO021182 for ; Tue, 2 Mar 2010 10:30:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752067Ab0CBK37 (ORCPT ); Tue, 2 Mar 2010 05:29:59 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:48873 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751646Ab0CBK37 (ORCPT ); Tue, 2 Mar 2010 05:29:59 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o22ATmmY024783 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 2 Mar 2010 04:29:51 -0600 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o22ATl1C028592; Tue, 2 Mar 2010 15:59:47 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o22ATlf2003201; Tue, 2 Mar 2010 15:59:47 +0530 Received: (from a0393534@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o22ATl3l003198; Tue, 2 Mar 2010 15:59:47 +0530 From: Anuj Aggarwal To: tony@atomide.com Cc: linux-omap@vger.kernel.org, broonie@opensource.wolfsonmicro.com, lrg@slimlogic.co.uk, Anuj Aggarwal Subject: [PATCHv3 2/4] Regulator: OMAP: Modifying Kconfig/Makefile to choose from available PMICs Date: Tue, 2 Mar 2010 15:59:47 +0530 Message-Id: <1267525787-3169-1-git-send-email-anuj.aggarwal@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 02 Mar 2010 10:30:00 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index a8a3d1e..1974dda 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -77,6 +77,15 @@ config MACH_OMAP3EVM depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB +config PMIC_TWL4030 + bool "TWL4030/TPS65950 Power Module" + default y + select TWL4030_CORE + select REGULATOR_TWL4030 if REGULATOR + help + Say yes here if you are using the TWL4030/TPS65950 based power module + for the EVM boards. + config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 2069fb3..c33e24d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -137,6 +137,7 @@ obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o +obj-$(CONFIG_PMIC_TWL4030) += twl4030-pmic.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o From patchwork Thu Jul 1 10:31:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 109047 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o61AW9NA022479 for ; Thu, 1 Jul 2010 10:32:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755212Ab0GAKcI (ORCPT ); Thu, 1 Jul 2010 06:32:08 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:44402 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755008Ab0GAKcH (ORCPT ); Thu, 1 Jul 2010 06:32:07 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o61AW4Ki010876 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 1 Jul 2010 05:32:04 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o61AW1lj017544; Thu, 1 Jul 2010 05:32:01 -0500 (CDT) Received: from localhost (omaplbp.india.ti.com [172.24.190.217]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o61AVwP16966; Thu, 1 Jul 2010 05:31:58 -0500 (CDT) From: Archit Taneja To: linux-omap@vger.kernel.org Cc: tomi.valkeinen@nokia.com, Mayuresh Janorkar , Sumit Semwal , Senthilvadivu Guruswamy , Mukund Mittal , Archit Taneja , Samreen Subject: [RFC][PATCH 7/8] OMAP: DSS2: Context Save and Restore of DISPC registers for Secondary LCD Date: Thu, 1 Jul 2010 16:01:24 +0530 Message-Id: <1277980285-20996-8-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1277980285-20996-7-git-send-email-archit@ti.com> References: <1277980285-20996-1-git-send-email-archit@ti.com> <1277980285-20996-2-git-send-email-archit@ti.com> <1277980285-20996-3-git-send-email-archit@ti.com> <1277980285-20996-4-git-send-email-archit@ti.com> <1277980285-20996-5-git-send-email-archit@ti.com> <1277980285-20996-6-git-send-email-archit@ti.com> <1277980285-20996-7-git-send-email-archit@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 10:32:10 +0000 (UTC) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 3dcd3fe..ca90593 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -237,6 +237,17 @@ void dispc_save_context(void) SR(SIZE_DIG); SR(SIZE_LCD); + if (cpu_is_omap44xx()) { + SR(CONTROL2); + SR(DEFAULT_COLOR2); + SR(TRANS_COLOR2); + SR(SIZE_LCD2); + SR(TIMING_H2); + SR(TIMING_V2); + SR(POL_FREQ2); + SR(DIVISOR2); + SR(CONFIG2); + } SR(GFX_BA0); SR(GFX_BA1); SR(GFX_POSITION); @@ -256,6 +267,15 @@ void dispc_save_context(void) SR(CPR_COEF_G); SR(CPR_COEF_B); + if (cpu_is_omap44xx()) { + SR(CPR2_COEF_B); + SR(CPR2_COEF_G); + SR(CPR2_COEF_R); + + SR(DATA2_CYCLE1); + SR(DATA2_CYCLE2); + SR(DATA2_CYCLE3); + } SR(GFX_PRELOAD); /* VID1 */ @@ -376,6 +396,22 @@ void dispc_restore_context(void) RR(SIZE_DIG); RR(SIZE_LCD); + if (cpu_is_omap44xx()) { + RR(DEFAULT_COLOR2); + RR(TRANS_COLOR2); + RR(CPR2_COEF_B); + RR(CPR2_COEF_G); + RR(CPR2_COEF_R); + RR(DATA2_CYCLE1); + RR(DATA2_CYCLE2); + RR(DATA2_CYCLE3); + RR(SIZE_LCD2); + RR(TIMING_H2); + RR(TIMING_V2); + RR(POL_FREQ2); + RR(DIVISOR2); + RR(CONFIG2); + } RR(GFX_BA0); RR(GFX_BA1); RR(GFX_POSITION); @@ -395,6 +431,15 @@ void dispc_restore_context(void) RR(CPR_COEF_G); RR(CPR_COEF_B); + if (cpu_is_omap44xx()) { + RR(CPR2_COEF_B); + RR(CPR2_COEF_G); + RR(CPR2_COEF_R); + + RR(DATA2_CYCLE1); + RR(DATA2_CYCLE2); + RR(DATA2_CYCLE3); + } RR(GFX_PRELOAD); /* VID1 */ @@ -497,7 +542,8 @@ void dispc_restore_context(void) /* enable last, because LCD & DIGIT enable are here */ RR(CONTROL); - + if (cpu_is_omap44xx()) + RR(CONTROL2); /* clear spurious SYNC_LOST_DIGIT interrupts */ dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); From patchwork Wed May 12 17:18:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Candelaria Villareal, Jorge" X-Patchwork-Id: 99065 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4CHUNXB007017 for ; Wed, 12 May 2010 17:30:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756771Ab0ELRaW (ORCPT ); Wed, 12 May 2010 13:30:22 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:54018 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754299Ab0ELRaV (ORCPT ); Wed, 12 May 2010 13:30:21 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4CHUHOq029509 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 12 May 2010 12:30:17 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4CHUGuO000079; Wed, 12 May 2010 12:30:16 -0500 (CDT) Received: from localhost.localdomain (x0107209-ubuntu.sasken-mty.naucm.ext.ti.com [10.87.231.217]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o4CHUBt8020576; Wed, 12 May 2010 12:30:15 -0500 (CDT) From: Jorge Eduardo Candelaria To: linux-omap@vger.kernel.org Cc: lrg@slimlogic.co.uk, broonie@opensource.wolfsonmicro.com, Jorge Eduardo Candelaria , Margarita Olaya Cabrera Subject: [PATCH v3 2/2] ARM: McBSP: Add support for omap4 in McBSP driver Date: Wed, 12 May 2010 12:18:40 -0500 Message-Id: <1273684720-16619-3-git-send-email-jorge.candelaria@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1273684720-16619-2-git-send-email-jorge.candelaria@ti.com> References: <1273684720-16619-1-git-send-email-jorge.candelaria@ti.com> <1273684720-16619-2-git-send-email-jorge.candelaria@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 12 May 2010 17:30:23 +0000 (UTC) diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 6696eb6..6dbe669 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -489,7 +489,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -511,7 +511,7 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -587,7 +587,7 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) * Enable wakup behavior, smart idle and all wakeups * REVISIT: some wakeups may be unnecessary */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -610,7 +610,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) /* * Disable wakup behavior, smart idle and all wakeups */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -859,7 +859,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { /* Release the transmitter and receiver */ w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); @@ -889,7 +889,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset transmitter */ tx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { w = MCBSP_READ_CACHE(mcbsp, XCCR); w |= (tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); @@ -899,7 +899,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset receiver */ rx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { w = MCBSP_READ_CACHE(mcbsp, RCCR); w |= (rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); From patchwork Thu Jun 10 11:23:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Senthilvadivu Guruswamy X-Patchwork-Id: 105371 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5ABObeP007547 for ; Thu, 10 Jun 2010 11:24:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758995Ab0FJLYJ (ORCPT ); Thu, 10 Jun 2010 07:24:09 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41635 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753738Ab0FJLYH (ORCPT ); Thu, 10 Jun 2010 07:24:07 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5ABO1Nj032069 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 10 Jun 2010 06:24:03 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5ABNwn7020590; Thu, 10 Jun 2010 16:53:59 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o5ABNwVI003058; Thu, 10 Jun 2010 16:53:58 +0530 Received: (from a0876342@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o5ABNv9M003056; Thu, 10 Jun 2010 16:53:57 +0530 From: Guruswamy Senthilvadivu To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, tony@atomide.com, tomi.valkeinen@nokia.com, hvaibhav@ti.com Cc: Senthilvadivu Guruswamy Subject: [PATCH v3 2/3] DSS2: make VRFB depends on OMAP2,3 Date: Thu, 10 Jun 2010 16:53:56 +0530 Message-Id: <1276169037-2598-2-git-send-email-svadivu@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1276169037-2598-1-git-send-email-svadivu@ti.com> References: <1276169037-2598-1-git-send-email-svadivu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 10 Jun 2010 11:24:38 +0000 (UTC) diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig index d877c36..18bb835 100644 --- a/drivers/video/omap2/Kconfig +++ b/drivers/video/omap2/Kconfig @@ -3,6 +3,10 @@ config OMAP2_VRAM config OMAP2_VRFB bool + depends on ARCH_OMAP2 || ARCH_OMAP3 + default y if FB_OMAP2 + help + OMAP VRFB buffer support is efficient for rotation source "drivers/video/omap2/dss/Kconfig" source "drivers/video/omap2/omapfb/Kconfig" diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig index a3ed15c..f186c2b 100644 --- a/drivers/video/omap2/omapfb/Kconfig +++ b/drivers/video/omap2/omapfb/Kconfig @@ -3,7 +3,6 @@ menuconfig FB_OMAP2 depends on FB && OMAP2_DSS select OMAP2_VRAM - select OMAP2_VRFB select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT From patchwork Sat May 15 06:04:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 99799 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4F64Nca011460 for ; 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Sat, 15 May 2010 11:34:15 +0530 From: Ajay Kumar Gupta To: linux-omap@vger.kernel.org Cc: felipe.balbi@nokia.com, Ajay Kumar Gupta Subject: [PATCH] OMAP3: musb: remove unneeded include files Date: Sat, 15 May 2010 11:34:15 +0530 Message-Id: <1273903455-8793-1-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 15 May 2010 06:04:24 +0000 (UTC) diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 63104dd..1929f3b 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -16,19 +16,11 @@ * published by the Free Software Foundation. */ -#include -#include -#include #include -#include #include -#include - #include -#include #include -#include #include #ifdef CONFIG_USB_MUSB_SOC From patchwork Fri Jul 23 08:36:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripathy, Vishwanath" X-Patchwork-Id: 113855 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6N8h0Tk023379 for ; Fri, 23 Jul 2010 08:46:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753701Ab0GWIg4 (ORCPT ); Fri, 23 Jul 2010 04:36:56 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:38228 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750877Ab0GWIgy (ORCPT ); Fri, 23 Jul 2010 04:36:54 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6N8aogb025229 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 23 Jul 2010 03:36:53 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6N8ancm000433; Fri, 23 Jul 2010 14:06:50 +0530 (IST) From: Vishwanath Sripathy To: linux-omap@vger.kernel.org Cc: Vishwanath Sripathy Subject: [PATCH] OMAP PM: MPU/DMA Latency constraints Date: Fri, 23 Jul 2010 14:06:49 +0530 Message-Id: <1279874209-7944-1-git-send-email-vishwanath.bs@ti.com> X-Mailer: git-send-email 1.5.4.7 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 08:46:51 +0000 (UTC) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 286b606..ce544b0 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -194,6 +194,9 @@ config OMAP_PM_NONE config OMAP_PM_NOOP bool "No-op/debug PM layer" +config OMAP_PM + depends on PM + bool "OMAP PM layer implementation" endchoice endmenu diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 2a15191..fad2475 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -32,3 +32,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +obj-$(CONFIG_OMAP_PM) += omap-pm.o diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index a5ce4f0..29dc45a --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -145,7 +145,8 @@ static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id) */ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) { - omap_pm_set_max_mpu_wakeup_lat(dev, t); + struct pm_qos_request_list *qos_handle = NULL; + omap_pm_set_max_mpu_wakeup_lat(&qos_handle, t); } static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 728fbb9..47ba9e6 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h @@ -19,6 +19,7 @@ #include #include "powerdomain.h" +#include /** * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU @@ -86,7 +87,7 @@ void omap_pm_if_exit(void); /** * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency - * @dev: struct device * requesting the constraint + * @qos_request: handle for the constraint. The pointer should be initialized to NULL * @t: maximum MPU wakeup latency in microseconds * * Request that the maximum interrupt latency for the MPU to be no @@ -118,7 +119,7 @@ void omap_pm_if_exit(void); * Returns -EINVAL for an invalid argument, -ERANGE if the constraint * is not satisfiable, or 0 upon success. */ -int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); +int omap_pm_set_max_mpu_wakeup_lat(struct pm_qos_request_list **qos_request, long t); /** @@ -185,7 +186,7 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, /** * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency - * @dev: struct device * + * @qos_request: handle for the constraint. The pointer should be initialized to NULL * @t: maximum DMA transfer start latency in microseconds * * Request that the maximum system DMA transfer start latency for this @@ -210,7 +211,7 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, * Returns -EINVAL for an invalid argument, -ERANGE if the constraint * is not satisfiable, or 0 upon success. */ -int omap_pm_set_max_sdma_lat(struct device *dev, long t); +int omap_pm_set_max_sdma_lat(struct pm_qos_request_list **qos_request, long t); /** diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index e129ce8..af2fe43 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -34,19 +34,17 @@ struct omap_opp *l3_opps; * Device-driver-originated constraints (via board-*.c files) */ -int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) +int omap_pm_set_max_mpu_wakeup_lat(struct pm_qos_request_list **pmqos_req, long t) { - if (!dev || t < -1) { + if (!pmqos_req || t < -1) { WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); return -EINVAL; }; if (t == -1) - pr_debug("OMAP PM: remove max MPU wakeup latency constraint: " - "dev %s\n", dev_name(dev)); + pr_debug("OMAP PM: remove max MPU wakeup latency constraint\n"); else - pr_debug("OMAP PM: add max MPU wakeup latency constraint: " - "dev %s, t = %ld usec\n", dev_name(dev), t); + pr_debug("OMAP PM: add max MPU wakeup latency constraint: t = %ld usec\n", t); /* * For current Linux, this needs to map the MPU to a @@ -120,19 +118,17 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, return 0; } -int omap_pm_set_max_sdma_lat(struct device *dev, long t) +int omap_pm_set_max_sdma_lat(struct pm_qos_request_list **qos_request, long t) { - if (!dev || t < -1) { + if (!qos_request || t < -1) { WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); return -EINVAL; }; if (t == -1) - pr_debug("OMAP PM: remove max DMA latency constraint: " - "dev %s\n", dev_name(dev)); + pr_debug("OMAP PM: remove max DMA latency constraint:\n"); else - pr_debug("OMAP PM: add max DMA latency constraint: " - "dev %s, t = %ld usec\n", dev_name(dev), t); + pr_debug("OMAP PM: add max DMA latency constraint: t = %ld usec\n", t); /* * For current Linux PM QOS params, this code should scan the diff --git a/arch/arm/plat-omap/omap-pm.c b/arch/arm/plat-omap/omap-pm.c new file mode 100755 index 0000000..937196a --- /dev/null +++ b/arch/arm/plat-omap/omap-pm.c @@ -0,0 +1,309 @@ +/* + * omap-pm.c - OMAP power management interface + * + * Copyright (C) 2008-2010 Texas Instruments, Inc. + * Copyright (C) 2008-2009 Nokia Corporation + * Vishwanath BS + * + * This code is based on plat-omap/omap-pm-noop.c. + * + * Interface developed by (in alphabetical order): + * Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan + * Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff + */ + +#undef DEBUG + +#include +#include +#include + +/* Interface documentation is in mach/omap-pm.h */ +#include + +#include + +struct omap_opp *dsp_opps; +struct omap_opp *mpu_opps; +struct omap_opp *l3_opps; + +/* + * Device-driver-originated constraints (via board-*.c files) + */ + +int omap_pm_set_max_mpu_wakeup_lat(struct pm_qos_request_list **qos_request, long t) +{ + if (!qos_request || t < -1) { + pr_warning("Warning: invalid params to omap_pm_set_max_mpu_wakeup_lat \n:"); + return -EINVAL; + }; + + if (t == -1) { + pm_qos_remove_request(*qos_request); + *qos_request = NULL; + } else if (*qos_request == NULL) + *qos_request = pm_qos_add_request(PM_QOS_CPU_DMA_LATENCY, t); + else + pm_qos_update_request(*qos_request, t); + + return 0; +} + + +int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) +{ + if (!dev || (agent_id != OCP_INITIATOR_AGENT && + agent_id != OCP_TARGET_AGENT)) { + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; + }; + + if (r == 0) + pr_debug("OMAP PM: remove min bus tput constraint: " + "dev %s for agent_id %d\n", dev_name(dev), agent_id); + else + pr_debug("OMAP PM: add min bus tput constraint: " + "dev %s for agent_id %d: rate %ld KiB\n", + dev_name(dev), agent_id, r); + + /* + * This code should model the interconnect and compute the + * required clock frequency, convert that to a VDD2 OPP ID, then + * set the VDD2 OPP appropriately. + * + * TI CDP code can call constraint_set here on the VDD2 OPP. + */ + + return 0; +} + +int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, + long t) +{ + if (!req_dev || !dev || t < -1) { + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; + }; + + if (t == -1) + pr_debug("OMAP PM: remove max device latency constraint: " + "dev %s\n", dev_name(dev)); + else + pr_debug("OMAP PM: add max device latency constraint: " + "dev %s, t = %ld usec\n", dev_name(dev), t); + + /* + * For current Linux, this needs to map the device to a + * powerdomain, then go through the list of current max lat + * constraints on that powerdomain and find the smallest. If + * the latency constraint has changed, the code should + * recompute the state to enter for the next powerdomain + * state. Conceivably, this code should also determine + * whether to actually disable the device clocks or not, + * depending on how long it takes to re-enable the clocks. + * + * TI CDP code can call constraint_set here. + */ + + return 0; +} + +int omap_pm_set_max_sdma_lat(struct pm_qos_request_list **qos_request, long t) +{ + if (!qos_request || t < -1) { + pr_warning("Warning: invalid params to omap_pm_set_max_sdma_lat\n:"); + return -EINVAL; + }; + + if (t == -1) { + pm_qos_remove_request(*qos_request); + *qos_request = NULL; + } else if (*qos_request == NULL) + *qos_request = pm_qos_add_request(PM_QOS_CPU_DMA_LATENCY, t); + else + pm_qos_update_request(*qos_request, t); + + return 0; +} + +int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r) +{ + if (!dev || !c || r < 0) { + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; + } + + if (r == 0) + pr_debug("OMAP PM: remove min clk rate constraint: " + "dev %s\n", dev_name(dev)); + else + pr_debug("OMAP PM: add min clk rate constraint: " + "dev %s, rate = %ld Hz\n", dev_name(dev), r); + + /* + * Code in a real implementation should keep track of these + * constraints on the clock, and determine the highest minimum + * clock rate. It should iterate over each OPP and determine + * whether the OPP will result in a clock rate that would + * satisfy this constraint (and any other PM constraint in effect + * at that time). Once it finds the lowest-voltage OPP that + * meets those conditions, it should switch to it, or return + * an error if the code is not capable of doing so. + */ + + return 0; +} + +/* + * DSP Bridge-specific constraints + */ + +const struct omap_opp *omap_pm_dsp_get_opp_table(void) +{ + pr_debug("OMAP PM: DSP request for OPP table\n"); + + /* + * Return DSP frequency table here: The final item in the + * array should have .rate = .opp_id = 0. + */ + + return NULL; +} + +void omap_pm_dsp_set_min_opp(u8 opp_id) +{ + if (opp_id == 0) { + WARN_ON(1); + return; + } + + pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id); + + /* + * + * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we + * can just test to see which is higher, the CPU's desired OPP + * ID or the DSP's desired OPP ID, and use whichever is + * highest. + * + * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP + * rate is keyed on MPU speed, not the OPP ID. So we need to + * map the OPP ID to the MPU speed for use with clk_set_rate() + * if it is higher than the current OPP clock rate. + * + */ +} + + +u8 omap_pm_dsp_get_opp(void) +{ + pr_debug("OMAP PM: DSP requests current DSP OPP ID\n"); + + /* + * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock + * + * CDP12.14+: + * Call clk_get_rate() on the OPP custom clock, map that to an + * OPP ID using the tables defined in board-*.c/chip-*.c files. + */ + + return 0; +} + +/* + * CPUFreq-originated constraint + * + * In the future, this should be handled by custom OPP clocktype + * functions. + */ + +struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void) +{ + pr_debug("OMAP PM: CPUFreq request for frequency table\n"); + + /* + * Return CPUFreq frequency table here: loop over + * all VDD1 clkrates, pull out the mpu_ck frequencies, build + * table + */ + + return NULL; +} + +void omap_pm_cpu_set_freq(unsigned long f) +{ + if (f == 0) { + WARN_ON(1); + return; + } + + pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n", + f); + + /* + * For l-o dev tree, determine whether MPU freq or DSP OPP id + * freq is higher. Find the OPP ID corresponding to the + * higher frequency. Call clk_round_rate() and clk_set_rate() + * on the OPP custom clock. + * + * CDP should just be able to set the VDD1 OPP clock rate here. + */ +} + +unsigned long omap_pm_cpu_get_freq(void) +{ + pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n"); + + /* + * Call clk_get_rate() on the mpu_ck. + */ + + return 0; +} + +/* + * Device context loss tracking + */ + +int omap_pm_get_dev_context_loss_count(struct device *dev) +{ + if (!dev) { + WARN_ON(1); + return -EINVAL; + }; + + pr_debug("OMAP PM: returning context loss count for dev %s\n", + dev_name(dev)); + + /* + * Map the device to the powerdomain. Return the powerdomain + * off counter. + */ + + return 0; +} + + +/* Should be called before clk framework init */ +int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table, + struct omap_opp *dsp_opp_table, + struct omap_opp *l3_opp_table) +{ + mpu_opps = mpu_opp_table; + dsp_opps = dsp_opp_table; + l3_opps = l3_opp_table; + return 0; +} + +/* Must be called after clock framework is initialized */ +int __init omap_pm_if_init(void) +{ + return 0; +} + +void omap_pm_if_exit(void) +{ + /* Deallocate CPUFreq frequency table here */ +} + + From patchwork Sat Jul 3 05:38:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zach Pfeffer X-Patchwork-Id: 109985 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o635cnve015569 for ; Sat, 3 Jul 2010 05:38:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753165Ab0GCFie (ORCPT ); Sat, 3 Jul 2010 01:38:34 -0400 Received: from wolverine01.qualcomm.com ([199.106.114.254]:44896 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751239Ab0GCFid (ORCPT ); Sat, 3 Jul 2010 01:38:33 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6031"; a="46364645" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine01.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 02 Jul 2010 22:38:30 -0700 Received: from localhost.localdomain (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 77F1410004BF; Fri, 2 Jul 2010 22:38:32 -0700 (PDT) From: Zach Pfeffer To: mel@csn.ul.ie Cc: andi@firstfloor.org, dwalker@codeaurora.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zach Pfeffer Subject: [RFC 1/3 v3] mm: iommu: An API to unify IOMMU, CPU and device memory management Date: Fri, 2 Jul 2010 22:38:27 -0700 Message-Id: <1278135507-20294-1-git-send-email-zpfeffer@codeaurora.org> X-Mailer: git-send-email 1.7.0.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 03 Jul 2010 05:38:50 +0000 (UTC) diff --git a/Documentation/vcm.txt b/Documentation/vcm.txt new file mode 100644 index 0000000..1c6a8be --- /dev/null +++ b/Documentation/vcm.txt @@ -0,0 +1,587 @@ +What is this document about? +============================ + +This document covers how to use the Virtual Contiguous Memory Manager +(VCMM), how the first implementation works with a specific low-level +Input/Output Memory Management Unit (IOMMU) and the way the VCMM is used +from user-space. It also contains a section that describes why something +like the VCMM is needed in the kernel. + +If anything in this document is wrong, please send patches to the +maintainer of this file, listed at the bottom of the document. + + +The Virtual Contiguous Memory Manager +===================================== + +The VCMM was built to solve the system-wide memory mapping issues that +occur when many bus-masters have IOMMUs. + +An IOMMU maps device addresses to physical addresses. It also insulates +the system from spurious or malicious device bus transactions and allows +fine-grained mapping attribute control. The Linux kernel core does not +contain a generic API to handle IOMMU mapped memory; device driver writers +must implement device specific code to interoperate with the Linux kernel +core. As the number of IOMMUs increases, coordinating the many address +spaces mapped by all discrete IOMMUs becomes difficult without in-kernel +support. + +The VCMM API enables device independent IOMMU control, virtual memory +manager (VMM) interoperation and non-IOMMU enabled device interoperation +by treating devices with or without IOMMUs and all CPUs with or without +MMUs, their mapping contexts and their mappings using common +abstractions. Physical hardware is given a generic device type and mapping +contexts are abstracted into Virtual Contiguous Memory (VCM) +regions. Users "reserve" memory from VCMs and "back" their reservations +with physical memory. + +Why the VCMM is Needed +---------------------- + +Driver writers who control devices with IOMMUs must contend with device +control and memory management. Driver writers have a large device driver +API that they can leverage to control their devices, but they are lacking +a unified API to help them program mappings into IOMMUs and share those +mappings with other devices and CPUs in the system. + +Sharing is complicated by Linux's CPU-centric VMM. The CPU-centric model +generally makes sense because average hardware only contains a MMU for the +CPU and possibly a graphics MMU. If every device in the system has one or +more MMUs the CPU-centric memory management (MM) programming model breaks +down. + +Abstracting IOMMU device programming into a common API has already begun +in the Linux kernel. It was built to abstract the difference between AMD +and Intel IOMMUs to support x86 virtualization on both platforms. The +interface is listed in include/linux/iommu.h. It contains +interfaces for mapping and unmapping as well as domain management. This +interface has not gained widespread use outside the x86; PA-RISC, Alpha +and SPARC architectures and ARM and PowerPC platforms all use their own +mapping modules to control their IOMMUs. The VCMM contains an IOMMU +programming layer, but since its abstraction supports map management +independent of device control, the layer is not used directly. This +higher-level view enables a new kernel service, not just an IOMMU +interoperation layer. + +The General Idea: Map Management using Graphs +--------------------------------------------- + +Looking at mapping from a system-wide perspective reveals a general graph +problem. The VCMM's API is built to manage the general mapping graph. Each +node that talks to memory, either through an MMU or directly (physically +mapped) can be thought of as the device-end of a mapping edge. The other +edge is the physical memory (or intermediate virtual space) that is +mapped. + +In the direct-mapped case the device is assigned a one-to-one MMU. This +scheme allows direct mapped devices to participate in general graph +management. + +The CPU nodes can also be brought under the same mapping abstraction with +the use of a light overlay on the existing VMM. This light overlay allows +VMM-managed mappings to interoperate with the common API. The light +overlay enables this without substantial modifications to the existing +VMM. + +In addition to CPU nodes that are running Linux (and the VMM), remote CPU +nodes that may be running other operating systems can be brought into the +general abstraction. Routing all memory management requests from a remote +node through the central memory management framework enables new features +like system-wide memory migration. This feature may only be feasible for +large buffers that are managed outside of the fast-path, but having remote +allocation in a system enables features that are impossible to build +without it. + +The fundamental objects that support graph-based map management are: + +1) Virtual Contiguous Memory Regions + +2) Reservations + +3) Associated Virtual Contiguous Memory Regions + +4) Memory Targets + +5) Physical Memory Allocations + +Usage Overview +-------------- + +In a nutshell, users allocate Virtual Contiguous Memory Regions and +associate those regions with one or more devices by creating an Associated +Virtual Contiguous Memory Region. Users then create Reservations from the +Virtual Contiguous Memory Region. At this point no physical memory has +been committed to the reservation. To associate physical memory with a +reservation a Physical Memory Allocation is created and the Reservation is +backed with this allocation. + +include/linux/vcm.h includes comments documenting each API. + +Virtual Contiguous Memory Regions +--------------------------------- + +A Virtual Contiguous Memory Region (VCM) abstracts the memory space a +device sees. The addresses of the region are only used by the devices +which are associated with the region. This address space would normally be +implemented as a device page table. + +A VCM is created and destroyed with three functions: + + struct vcm *vcm_create(unsigned long start_addr, unsigned long len); + + struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id); + + int vcm_free(struct vcm *vcm); + +start_addr is an offset into the address space where allocations will +start from. len is the length from start_addr of the VCM. Both functions +generate an instance of a VCM. + +ext_vcm_id is used to pass a request to the VMM to generate a VCM +instance. In the current implementation the call simply makes a note that +the VCM instance is a VMM VCM instance for other interfaces usage. This +muxing is seen throughout the implementation. + +vcm_create() and vcm_create_from_prebuilt() produce VCM instances for +virtually mapped devices (IOMMUs and CPUs). To create a one-to-one mapped +VCM, users pass the start_addr and len of the physical region. The VCMM +matches this and records that the VCM instance is a one-to-one VCM. + +The newly created VCM instance can be passed to any function that needs to +operate on or with a virtual contiguous memory region. Its main attributes +are a start_addr and a len as well as an internal setting that allows the +implementation to mux between true virtual spaces, one-to-one mapped +spaces and VMM managed spaces. + +The current implementation uses the genalloc library to manage the VCM for +IOMMU devices. Return values and more in-depth per-function documentation +for these and the ones listed below are in include/linux/vcm.h. + +Reservations +------------ + +A Reservation is a contiguous region allocated from a VCM. There is no +physical memory associated with it. + +A Reservation is created and destroyed with: + + struct res *vcm_reserve(struct vcm *vcm, size_t len, u32 attr); + + int vcm_unreserve(struct res *res); + +A vcm is a VCM created above. len is the length of the request. It can be +up to the length of the VCM region the reservation is being created +from. attr are mapping attributes: read, write, execute, user, supervisor, +secure, not-cached, write-back/write-allocate, write-back/no +write-allocate, write-through. These attrs are appropriate for ARM but can +be changed to match to any architecture. + +The implementation calls gen_pool_alloc() for IOMMU devices, +alloc_vm_area() for VMM areas and is a pass-through for one-to-one mapped +areas. + +Associated Virtual Contiguous Memory Regions and Activation +----------------------------------------------------------- + +An Associated Virtual Contiguous Memory Region (AVCM) is a mapping of a +VCM to a device. The mapping can be active or inactive. + +An AVCM is managed with: + + struct avcm *vcm_assoc(struct vcm *vcm, struct device *dev, u32 attr); + + int vcm_deassoc(struct avcm *avcm); + + int vcm_activate(struct avcm *avcm); + + int vcm_deactivate(struct avcm *avcm); + +A VCM instance is a VCM created above. A dev is an opaque device handle +thats passed down to the device driver the VCMM muxes in to handle a +request. attr are association attributes: split, use-high or +use-low. split controls which transactions hit a high-address page-table +and which transactions hit a low-address page-table. For instance, all +transactions whose most significant address bit is one would use the +high-address page-table, any other transaction would use the low address +page-table. This scheme is ARM-specific and could be changed in other +architectures. One VCM instance can be associated with many devices and +many VCM instances can be associated with one device. + +An AVCM is only a link. To program and deprogram a device with a VCM the +user calls vcm_activate() and vcm_deactivate(). For IOMMU devices, +activating a mapping programs the base address of a page table into an +IOMMU. For VMM and one-to-one based devices, mappings are active +immediately but the API does require an activation call for them for +internal reference counting. + +Memory Targets +-------------- + +A Memory Target is a platform independent way of specifying a physical +pool; it abstracts a pool of physical memory. The physical memory pool may +be physically discontiguous, need to be allocated from in a unique way or +have other user-defined attributes. + +Physical Memory Allocation and Reservation Backing +-------------------------------------------------- + +Physical memory is allocated as a separate step from reserving +memory. This allows multiple reservations to back the same physical +memory. + +A Physical Memory Allocation is managed using the following functions: + + struct physmem *vcm_phys_alloc(enum memtype_t memtype, + size_t len, u32 attr); + + int vcm_phys_free(struct physmem *physmem); + + int vcm_back(struct res *res, struct physmem *physmem); + + int vcm_unback(struct res *res); + +attr can include an alignment request, a specification to map memory using +various block sizes and/or to use physically contiguous memory. memtype is +one of the memory types listed in Memory Targets. + +The current implementation manages two pools of memory. One pool is a +contiguous block of memory and the other is a set of contiguous block +pools. In the current implementation the block pools contain 4K, 64K and +1M blocks. The physical allocator does not try to split blocks from the +contiguous block pools to satisfy requests. + +The use of 4K, 64K and 1M blocks solves a problem with some IOMMU +hardware. IOMMUs are placed in front of multimedia engines to provide a +contiguous address space to the device. Multimedia devices need large +buffers and large buffers may map to a large number of physical +blocks. IOMMUs tend to have small translation lookaside buffers +(TLBs). Since the TLB is small the number of physical blocks that map a +given range needs to be small or else the IOMMU will continually fetch new +translations during a typical streamed multimedia flow. By using a 1 MB +mapping (or 64K mapping) instead of a 4K mapping the number of misses can +be minimized, allowing the multimedia block to meet its performance goals. + +Low Level Control +----------------- + +It is necessary in some instances to access attributes and provide +higher-level control of the low-level hardware abstraction. The API +contains many members and functions for this task but the two that are +typically used are: + + res->dev_addr; + + int vcm_hook(struct device *dev, vcm_handler handler, void *data); + +res->dev_addr is the device address given a reservation. This device +address is a virtual IOMMU address for reservations on IOMMU VCMs, a +virtual VMM address for reservations on VMM VCMs and a virtual (really +physical since its one-to-one mapped) address for one-to-one devices. + +The function, vcm_hook, allows a caller in the kernel to register a +user_handler. The handler is passed the data member passed to vcm_hook +during a fault. The user can return 1 to indicate that the underlying +driver should handle the fault and retry the transaction or they can +return 0 to halt the transaction. If the user doesn't register a +handler the low-level driver will print a warning and terminate the +transaction. + +A Detailed Walk Through +----------------------- + +The following call sequence walks through a typical allocation +sequence. In the first stage the memory for a device is reserved and +backed. This occurs without mapping the memory into a VMM VCM region. The +second stage maps the first VCM region into a VMM VCM region so the kernel +can read or write it. The second stage is not necessary if the VMM does +not need to read or modify the contents of the original mapping. + + Stage 1: Map and Allocate Memory for a Device + + The call sequence starts by creating a VCM region: + + vcm = vcm_create(start_addr, len); + + The next call associates a VCM region with a device: + + avcm = vcm_assoc(vcm, dev, attr); + + To activate the association, users call vcm_activate() on the avcm from + the associate call. This programs the underlining device with the + mappings. + + ret = vcm_activate(avcm); + + Once a VCM region is created and associated it can be reserved from + with: + + res = vcm_reserve(vcm, res_len, res_attr); + + A user then allocates physical memory with: + + physmem = vcm_phys_alloc(memtype, len, phys_attr); + + To back the reservation with the physical memory allocation the user + calls: + + vcm_back(res, physmem); + + + Stage 2: Map the Device's Memory into the VMM's VCM region + + If the VMM needs to read and/or write the region that was just created, + the following calls are made. + + The first call creates a prebuilt VCM with: + + vcm_vmm = vcm_from_prebuilt(ext_vcm_id); + + The prebuilt VCM is associated with the CPU device and activated with: + + avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr); + vcm_activate(avcm_vmm); + + A reservation is made on the VMM VCM with: + + res_vmm = vcm_reserve(vcm_vmm, res_len, attr); + + Finally, once the topology has been set up a vcm_back() allows the VMM + to read the memory using the physmem generated in stage 1: + + vcm_back(res_vmm, physmem); + +Mapping IOMMU, one-to-one and VMM Reservations +---------------------------------------------- + +The following example demonstrates mapping IOMMU, one-to-one and VMM +reservations to the same physical memory. It shows the use of phys_addr +and phys_size to create a contiguous VCM for one-to-one mapped devices. + + The user allocates physical memory: + + physmem = vcm_phys_alloc(memtype, SZ_2MB + SZ_4K, CONTIGUOUS); + + Creates an IOMMU VCM: + + vcm_iommu = vcm_create(SZ_1K, SZ_16M); + + Creates a one-to-one VCM: + + vcm_onetoone = vcm_create(phys_addr, phys_size); + + Creates a Prebuit VCM: + + vcm_vmm = vcm_from_prebuit(ext_vcm_id); + + Associate and activate all three to their respective devices: + + avcm_iommu = vcm_assoc(vcm_iommu, dev_iommu, attr0); + avcm_onetoone = vcm_assoc(vcm_onetoone, dev_onetoone, attr1); + avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr2); + vcm_activate(avcm_iommu); + vcm_activate(avcm_onetoone); + vcm_activate(avcm_vmm); + + Associations that fail return 0. + + And finally, creates and backs reservations on all 3 such that they + all point to the same memory: + + res_iommu = vcm_reserve(vcm_iommu, SZ_2MB + SZ_4K, attr); + res_onetoone = vcm_reserve(vcm_onetoone, SZ_2MB + SZ_4K, attr); + res_vmm = vcm_reserve(vcm_vmm, SZ_2MB + SZ_4K, attr); + vcm_back(res_iommu, physmem); + vcm_back(res_onetoone, physmem); + vcm_back(res_vmm, physmem); + + Like associations, reservations that fail return 0. + +VCM Summary +----------- + +The VCMM is an attempt to abstract attributes of three distinct classes of +mappings into one API. The VCMM allows users to reason about mappings as +first class objects. It also allows memory mappings to flow from the +traditional 4K mappings prevalent on systems today to more efficient block +sizes. Finally, it allows users to manage mapping interoperation without +becoming VMM experts. These features will allow future systems with many +MMU mapped devices to interoperate simply and therefore correctly. + + +IOMMU Hardware Control +====================== + +The VCM currently supports a single type of IOMMU, a Qualcomm System MMU +(SMMU). The SMMU interface contains functions to map and unmap virtual +addresses, perform address translations and initialize hardware. A +Qualcomm SMMU can contain multiple MMU contexts. Each context can +translate in parallel. All contexts in a SMMU share one global translation +look-aside buffer (TLB). + +To support context muxing the SMMU module creates and manages device +independent virtual contexts. These context abstractions are bound to +actual contexts at run-time. Once bound, a context can be activated. This +activation programs the underlying context with the virtual context +affecting a context switch. + +The following functions are all documented in: + + arch/arm/mach-msm/include/mach/smmu_driver.h. + +Mapping +------- + +To map and unmap a virtual page into physical space the VCM calls: + + int smmu_map(struct smmu_dev *dev, unsigned long pa, + unsigned long va, unsigned long len, unsigned int attr); + + int smmu_unmap(struct smmu_dev *dev, unsigned long va, + unsigned long len); + + int smmu_update_start(struct smmu_dev *dev); + + int smmu_update_done(struct smmu_dev *dev); + +The size given to map must be 4K, 64K, 1M or 16M and the VA and PA must be +aligned to the given size. smmu_update_start() and smmu_update_done() +should be called before and after each map or unmap. + +Translation +----------- + +To request a hardware VA to PA translation on a single address the VCM +calls: + + unsigned long smmu_translate(struct smmu_dev *dev, + unsigned long va); + +Fault Handling +-------------- + +To register an interrupt handler for a context the VCM calls: + + int smmu_hook_interrupt(struct smmu_dev *dev, vcm_handler handler, + void *data); + +The registered interrupt handler should return 1 if it wants the SMMU +driver to retry the transaction again and 0 if it wants the SMMU driver to +terminate the transaction. + +Managing SMMU Initialization and Contexts +----------------------------------------- + +SMMU hardware initialization and management happens in 2 steps. The first +step initializes global SMMU devices and abstract device contexts. The +second step binds contexts and devices. + +An SMMU hardware instance is built with: + + int smmu_drvdata_init(struct smmu_driver *drv, unsigned long base, + int irq); + +An SMMU context is initialized and deinitialized with: + + struct smmu_dev *smmu_ctx_init(int ctx); + int smmu_ctx_deinit(struct smmu_dev *dev); + +An abstract SMMU context is bound to a particular SMMU with: + + int smmu_ctx_bind(struct smmu_dev *ctx, struct smmu_driver *drv); + +Activation +---------- + +Activation affects a context switch. + +Activation, deactivation and activation state testing are done with: + + int smmu_activate(struct smmu_dev *dev); + int smmu_deactivate(struct smmu_dev *dev); + int smmu_is_active(struct smmu_dev *dev); + + +Userspace Access to Devices with IOMMUs +======================================= + +A device that issues transactions through an IOMMU must work with two +APIs. The first API is the VCM. The VCM API is device independent. Users +pass the VCM a dev_id and the VCM makes calls on the hardware device it +has been configured with using this dev_id. The second API is whatever +device topology has been created to organize the particular IOMMUs in a +system. The only constraint on this second API is that it must give the +user a single dev_id that it can pass through the VCM. + +For the Qualcomm SMMUs the second API consists of a tree of platform +devices and two platform drivers as well as a context lookup function that +traverses the device tree and returns a dev_id given a context name. + +Qualcomm SMMU Device Tree +------------------------- + +The current tree organizes the devices into a tree that looks like the +following: + +smmu/ + smmu0/ + ctx0 + ctx1 + ctx2 + smmu1/ + ctx3 + + +Each context, ctx[n] and each smmu, smmu[n] is given a name. Since users +are interested in contexts not smmus, the context name is passed to a +function to find the dev_id associated with that name. The functions to +find, free and get the base address (since the device probe function calls +ioremap to map the SMMUs configuration registers into the kernel) are +listed here: + + struct smmu_dev *smmu_get_ctx_instance(char *ctx_name); + int smmu_free_ctx_instance(struct smmu_dev *dev); + unsigned long smmu_get_base_addr(struct smmu_dev *dev); + +Documentation for these functions is in: + + arch/arm/mach-msm/include/mach/smmu_device.h + +Each context is given a dev node named after the context. For example: + + /dev/vcodec_a_mm1 + /dev/vcodec_b_mm2 + /dev/vcodec_stream + etc... + +Users open, close and mmap these nodes to access VCM buffers from +userspace in the same way that they used to open, close and mmap /dev +nodes that represented large physically contiguous buffers (called PMEM +buffers on Android). + +Example +------- + +An abbreviated example is shown here: + +Users get the dev_id associated with their target context, create a VCM +topology appropriate for their device and finally associate the VCMs of +the topology with the contexts that will take the VCMs: + + dev_id = smmu_get_ctx_instance(vcodec_a_stream); + +create vcm and needed topology + + avcm = vcm_assoc(vcm, dev_id, attr); + +Tying it all Together +--------------------- + +VCMs, IOMMUs and the device tree all work to support system-wide memory +mappings. The use of each API in this system allows users to concentrate +on the relevant details without needing to worry about low-level +details. The API's clear separation of memory spaces and the devices that +support those memory spaces continues the Linux tradition of abstracting the +what from the how. + + +Maintainer: Zach Pfeffer From patchwork Sat May 15 04:07:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 99794 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4F47w1x014803 for ; Sat, 15 May 2010 04:07:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750822Ab0EOEH4 (ORCPT ); Sat, 15 May 2010 00:07:56 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:60294 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750758Ab0EOEHz (ORCPT ); Sat, 15 May 2010 00:07:55 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4F47pDu024464 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 14 May 2010 23:07:54 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4F47nsD013769; Sat, 15 May 2010 09:37:50 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o4F47nvg009718; Sat, 15 May 2010 09:37:49 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o4F47nit009715; Sat, 15 May 2010 09:37:49 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, Ajay Kumar Gupta Subject: [PATCH] musb: host: release dma channels if no active io Date: Sat, 15 May 2010 09:37:49 +0530 Message-Id: <1273896469-9686-1-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 15 May 2010 04:07:59 +0000 (UTC) diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index 877d20b..d78b887 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -387,11 +387,21 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb, */ if (list_empty(&qh->hep->urb_list)) { struct list_head *head; + struct dma_controller *dma = musb->dma_controller; - if (is_in) + if (is_in) { ep->rx_reinit = 1; - else + if (ep->rx_channel) { + dma->channel_release(ep->rx_channel); + ep->rx_channel = NULL; + } + } else { ep->tx_reinit = 1; + if (ep->tx_channel) { + dma->channel_release(ep->tx_channel); + ep->tx_channel = NULL; + } + } /* Clobber old pointers to this qh */ musb_ep_set_qh(ep, is_in, NULL); From patchwork Sat May 15 04:59:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 99795 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4F4xvQ2012022 for ; Sat, 15 May 2010 04:59:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751210Ab0EOE7z (ORCPT ); Sat, 15 May 2010 00:59:55 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:44448 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751169Ab0EOE7y (ORCPT ); Sat, 15 May 2010 00:59:54 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4F4xiOU031533 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 14 May 2010 23:59:47 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4F4xg16016802; Sat, 15 May 2010 10:29:42 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o4F4xgmN026663; Sat, 15 May 2010 10:29:42 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o4F4xfEn026659; Sat, 15 May 2010 10:29:41 +0530 From: Ajay Kumar Gupta To: linux-omap@vger.kernel.org Cc: felipe.balbi@nokia.com, Ajay Kumar Gupta Subject: [PATCH] OMAP3: musb: remove unneeded inits in musb_plat Date: Sat, 15 May 2010 10:29:41 +0530 Message-Id: <1273899581-26622-1-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 15 May 2010 04:59:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 6d41fa7..63104dd 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -55,21 +55,8 @@ static struct musb_hdrc_config musb_config = { }; static struct musb_hdrc_platform_data musb_plat = { -#ifdef CONFIG_USB_MUSB_OTG - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC_HCD) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif /* .clock is set dynamically */ .config = &musb_config, - - /* REVISIT charge pump on TWL4030 can supply up to - * 100 mA ... but this value is board-specific, like - * "mode", and should be passed to usb_musb_init(). - */ - .power = 50, /* up to 100 mA */ }; static u64 musb_dmamask = DMA_BIT_MASK(32); From patchwork Sat Jul 3 05:38:45 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zach Pfeffer X-Patchwork-Id: 109988 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o635dX6g015709 for ; Sat, 3 Jul 2010 05:39:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754023Ab0GCFix (ORCPT ); Sat, 3 Jul 2010 01:38:53 -0400 Received: from wolverine02.qualcomm.com ([199.106.114.251]:26493 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751239Ab0GCFiv (ORCPT ); Sat, 3 Jul 2010 01:38:51 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6031"; a="46215394" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 02 Jul 2010 22:38:48 -0700 Received: from localhost.localdomain (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 41A0910004BF; Fri, 2 Jul 2010 22:38:50 -0700 (PDT) From: Zach Pfeffer To: mel@csn.ul.ie Cc: andi@firstfloor.org, dwalker@codeaurora.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zach Pfeffer Subject: [RFC 3/3 v3] mm: iommu: The Virtual Contiguous Memory Manager Date: Fri, 2 Jul 2010 22:38:45 -0700 Message-Id: <1278135525-20327-1-git-send-email-zpfeffer@codeaurora.org> X-Mailer: git-send-email 1.7.0.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 03 Jul 2010 05:39:33 +0000 (UTC) different pools. This allows fine grained control of block and physical placement, a feature many advanced IOMMU devices need. Once a user has made a reservation on a VCM and allocated physical memory, the two graph end-points are joined in a backing step. This step allows multiple reservations to map the same physical location. Many of the functions in the API take various attributes that provide fine grained control of the objects they create. For instance, reservations can map cachable memory and physical allocations can be constrained to use a particular subset of block sizes. Signed-off-by: Zach Pfeffer --- arch/arm/mm/vcm.c | 1877 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/vcm.h | 661 ++++++++++++++++ include/linux/vcm_types.h | 338 ++++++++ 3 files changed, 2876 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mm/vcm.c create mode 100644 include/linux/vcm.h create mode 100644 include/linux/vcm_types.h diff --git a/arch/arm/mm/vcm.c b/arch/arm/mm/vcm.c new file mode 100644 index 0000000..2c951c3 --- /dev/null +++ b/arch/arm/mm/vcm.c @@ -0,0 +1,1877 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_SMMU +#include +#endif + +/* alloc_vm_area */ +#include +#include +#include + +/* may be temporary */ +#include + +#include +#include + +#define BOOTMEM_SZ SZ_32M +#define BOOTMEM_ALIGN SZ_1M + +#define CONT_SZ SZ_8M +#define CONT_ALIGN SZ_1M + +#define ONE_TO_ONE_CHK 1 + +#define vcm_err(a, ...) \ + pr_err("ERROR %s %i " a, __func__, __LINE__, ##__VA_ARGS__) + +static void *bootmem; +static void *bootmem_cont; +static struct vcm *cont_vcm; +static struct phys_chunk *cont_phys_chunk; + +DEFINE_SPINLOCK(vcmlock); + +static int vcm_no_res(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + return list_empty(&vcm->res_head); +fail: + return -EINVAL; +} + +static int vcm_no_assoc(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + return list_empty(&vcm->assoc_head); +fail: + return -EINVAL; +} + +static int vcm_all_activated(struct vcm *vcm) +{ + struct avcm *avcm; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm) + if (!avcm->is_active) + return 0; + + return 1; +fail: + return -1; +} + +static void vcm_destroy_common(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return; + } + + memset(vcm, 0, sizeof(*vcm)); + kfree(vcm); +} + +static struct vcm *vcm_create_common(void) +{ + struct vcm *vcm = 0; + + vcm = kzalloc(sizeof(*vcm), GFP_KERNEL); + if (!vcm) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret 0\n", + sizeof(*vcm)); + goto fail; + } + + INIT_LIST_HEAD(&vcm->res_head); + INIT_LIST_HEAD(&vcm->assoc_head); + + return vcm; + +fail: + return NULL; +} + + +static int vcm_create_pool(struct vcm *vcm, size_t start_addr, size_t len) +{ + int ret = 0; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + vcm->start_addr = start_addr; + vcm->len = len; + + vcm->pool = gen_pool_create(PAGE_SHIFT, -1); + if (!vcm->pool) { + vcm_err("gen_pool_create(%x, -1) ret 0\n", PAGE_SHIFT); + goto fail; + } + + ret = gen_pool_add(vcm->pool, start_addr, len, -1); + if (ret) { + vcm_err("gen_pool_add(%p, %p, %i, -1) ret %i\n", vcm->pool, + (void *) start_addr, len, ret); + goto fail2; + } + + return 0; + +fail2: + gen_pool_destroy(vcm->pool); +fail: + return -1; +} + + +static struct vcm *vcm_create_flagged(int flag, size_t start_addr, size_t len) +{ + int ret = 0; + struct vcm *vcm = 0; + + vcm = vcm_create_common(); + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + /* special one-to-one mapping case */ + if ((flag & ONE_TO_ONE_CHK) && + bootmem_cont && + __pa(bootmem_cont) && + start_addr == __pa(bootmem_cont) && + len == CONT_SZ) { + vcm->type = VCM_ONE_TO_ONE; + } else { + ret = vcm_create_pool(vcm, start_addr, len); + vcm->type = VCM_DEVICE; + } + + if (ret) { + vcm_err("vcm_create_pool(%p, %p, %i) ret %i\n", vcm, + (void *) start_addr, len, ret); + goto fail2; + } + + return vcm; + +fail2: + vcm_destroy_common(vcm); +fail: + return NULL; +} + +struct vcm *vcm_create(unsigned long start_addr, size_t len) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + vcm = vcm_create_flagged(ONE_TO_ONE_CHK, start_addr, len); + spin_unlock_irqrestore(&vcmlock, flags); + return vcm; +} + + +static int ext_vcm_id_valid(size_t ext_vcm_id) +{ + return ((ext_vcm_id == VCM_PREBUILT_KERNEL) || + (ext_vcm_id == VCM_PREBUILT_USER)); +} + + +struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id) +{ + unsigned long flags; + struct vcm *vcm = 0; + + spin_lock_irqsave(&vcmlock, flags); + + if (!ext_vcm_id_valid(ext_vcm_id)) { + vcm_err("ext_vcm_id_valid(%i) ret 0\n", ext_vcm_id); + goto fail; + } + + vcm = vcm_create_common(); + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (ext_vcm_id == VCM_PREBUILT_KERNEL) + vcm->type = VCM_EXT_KERNEL; + else if (ext_vcm_id == VCM_PREBUILT_USER) + vcm->type = VCM_EXT_USER; + else { + vcm_err("UNREACHABLE ext_vcm_id is illegal\n"); + goto fail_free; + } + + /* TODO: set kernel and userspace start_addr and len, if this + * makes sense */ + + spin_unlock_irqrestore(&vcmlock, flags); + return vcm; + +fail_free: + vcm_destroy_common(vcm); +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return NULL; +} + + +struct vcm *vcm_clone(struct vcm *vcm) +{ + return 0; +} + + +/* No lock needed, vcm->start_addr is never updated after creation */ +size_t vcm_get_start_addr(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return 1; + } + + return vcm->start_addr; +} + + +/* No lock needed, vcm->len is never updated after creation */ +size_t vcm_get_len(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return 0; + } + + return vcm->len; +} + + +static int vcm_free_common_rule(struct vcm *vcm) +{ + int ret; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + ret = vcm_no_res(vcm); + if (!ret) { + vcm_err("vcm_no_res(%p) ret 0\n", vcm); + goto fail_busy; + } + + if (ret == -EINVAL) { + vcm_err("vcm_no_res(%p) ret -EINVAL\n", vcm); + goto fail; + } + + ret = vcm_no_assoc(vcm); + if (!ret) { + vcm_err("vcm_no_assoc(%p) ret 0\n", vcm); + goto fail_busy; + } + + if (ret == -EINVAL) { + vcm_err("vcm_no_assoc(%p) ret -EINVAL\n", vcm); + goto fail; + } + + return 0; + +fail_busy: + return -EBUSY; +fail: + return -EINVAL; +} + + +static int vcm_free_pool_rule(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + /* A vcm always has a valid pool, don't free the vcm because + what we got is probably invalid. + */ + if (!vcm->pool) { + vcm_err("NULL vcm->pool\n"); + goto fail; + } + + return 0; + +fail: + return -EINVAL; +} + + +static void vcm_free_common(struct vcm *vcm) +{ + memset(vcm, 0, sizeof(*vcm)); + + kfree(vcm); +} + + +static int vcm_free_pool(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + gen_pool_destroy(vcm->pool); + + return 0; + +fail: + return -1; +} + + +static int __vcm_free(struct vcm *vcm) +{ + int ret; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + ret = vcm_free_common_rule(vcm); + if (ret != 0) { + vcm_err("vcm_free_common_rule(%p) ret %i\n", vcm, ret); + goto fail; + } + + if (vcm->type == VCM_DEVICE) { + ret = vcm_free_pool_rule(vcm); + if (ret != 0) { + vcm_err("vcm_free_pool_rule(%p) ret %i\n", + (void *) vcm, ret); + goto fail; + } + + ret = vcm_free_pool(vcm); + if (ret != 0) { + vcm_err("vcm_free_pool(%p) ret %i", (void *) vcm, ret); + goto fail; + } + } + + vcm_free_common(vcm); + + return 0; + +fail: + return -EINVAL; +} + +int vcm_free(struct vcm *vcm) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + ret = __vcm_free(vcm); + spin_unlock_irqrestore(&vcmlock, flags); + + return ret; +} + + +static struct res *__vcm_reserve(struct vcm *vcm, size_t len, u32 attr) +{ + struct res *res = NULL; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (len == 0) { + vcm_err("len is 0\n"); + goto fail; + } + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret 0", sizeof(*res)); + goto fail; + } + + INIT_LIST_HEAD(&res->res_elm); + res->vcm = vcm; + res->len = len; + res->attr = attr; + + if (len/SZ_1M) + res->alignment_req = SZ_1M; + else if (len/SZ_64K) + res->alignment_req = SZ_64K; + else + res->alignment_req = SZ_4K; + + res->aligned_len = res->alignment_req + len; + + switch (vcm->type) { + case VCM_DEVICE: + /* should always be not zero */ + if (!vcm->pool) { + vcm_err("NULL vcm->pool\n"); + goto fail2; + } + + res->ptr = gen_pool_alloc(vcm->pool, res->aligned_len); + if (!res->ptr) { + vcm_err("gen_pool_alloc(%p, %i) ret 0\n", + vcm->pool, res->aligned_len); + goto fail2; + } + + /* Calculate alignment... this will all change anyway */ + res->dev_addr = res->ptr + + (res->alignment_req - + (res->ptr & (res->alignment_req - 1))); + + break; + case VCM_EXT_KERNEL: + res->vm_area = alloc_vm_area(res->aligned_len); + res->mapped = 0; /* be explicit */ + if (!res->vm_area) { + vcm_err("NULL res->vm_area\n"); + goto fail2; + } + + res->dev_addr = (size_t) res->vm_area->addr + + (res->alignment_req - + ((size_t) res->vm_area->addr & + (res->alignment_req - 1))); + + break; + case VCM_ONE_TO_ONE: + break; + default: + vcm_err("%i is an invalid vcm->type\n", vcm->type); + goto fail2; + } + + list_add_tail(&res->res_elm, &vcm->res_head); + + return res; + +fail2: + kfree(res); +fail: + return 0; +} + + +struct res *vcm_reserve(struct vcm *vcm, size_t len, u32 attr) +{ + unsigned long flags; + struct res *res; + + spin_lock_irqsave(&vcmlock, flags); + res = __vcm_reserve(vcm, len, attr); + spin_unlock_irqrestore(&vcmlock, flags); + + return res; +} + + +struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm* vcm, + size_t len, u32 attr) +{ + return 0; +} + + +/* No lock needed, res->vcm is never updated after creation */ +struct vcm *vcm_get_vcm_from_res(struct res *res) +{ + if (!res) { + vcm_err("NULL res\n"); + return 0; + } + + return res->vcm; +} + + +static int __vcm_unreserve(struct res *res) +{ + struct vcm *vcm; + + if (!res) { + vcm_err("NULL res\n"); + goto fail; + } + + if (!res->vcm) { + vcm_err("NULL res->vcm\n"); + goto fail; + } + + vcm = res->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + switch (vcm->type) { + case VCM_DEVICE: + if (!res->vcm->pool) { + vcm_err("NULL (res->vcm))->pool\n"); + goto fail; + } + + /* res->ptr could be zero, this isn't an error */ + gen_pool_free(res->vcm->pool, res->ptr, + res->aligned_len); + break; + case VCM_EXT_KERNEL: + if (res->mapped) { + vcm_err("res->mapped is true\n"); + goto fail; + } + + /* This may take a little explaining. + * In the kernel vunmap will free res->vm_area + * so if we've called it then we shouldn't call + * free_vm_area(). If we've called it we set + * res->vm_area to 0. + */ + if (res->vm_area) { + free_vm_area(res->vm_area); + res->vm_area = 0; + } + + break; + case VCM_ONE_TO_ONE: + break; + default: + vcm_err("%i is an invalid vcm->type\n", vcm->type); + goto fail; + } + + list_del(&res->res_elm); + + /* be extra careful by clearing the memory before freeing it */ + memset(res, 0, sizeof(*res)); + + kfree(res); + + return 0; + +fail: + return -EINVAL; +} + + +int vcm_unreserve(struct res *res) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + ret = __vcm_unreserve(res); + spin_unlock_irqrestore(&vcmlock, flags); + + return ret; +} + + +/* No lock needed, res->len is never updated after creation */ +size_t vcm_get_res_len(struct res *res) +{ + if (!res) { + vcm_err("res is 0\n"); + return 0; + } + + return res->len; +} + + +int vcm_set_res_attr(struct res *res, u32 attr) +{ + return 0; +} + + +size_t vcm_get_num_res(struct vcm *vcm) +{ + return 0; +} + + +struct res *vcm_get_next_res(struct vcm *vcm, struct res *res) +{ + return 0; +} + + +size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, + size_t from_off, size_t len) +{ + return 0; +} + + +size_t vcm_get_min_page_size(void) +{ + return PAGE_SIZE; +} + + +static int vcm_to_smmu_attr(u32 attr) +{ + int smmu_attr = 0; + + switch (attr & VCM_CACHE_POLICY) { + case VCM_NOTCACHED: + smmu_attr = VCM_DEV_ATTR_NONCACHED; + break; + case VCM_WB_WA: + smmu_attr = VCM_DEV_ATTR_CACHED_WB_WA; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + case VCM_WB_NWA: + smmu_attr = VCM_DEV_ATTR_CACHED_WB_NWA; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + case VCM_WT: + smmu_attr = VCM_DEV_ATTR_CACHED_WT; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + default: + return -1; + } + + return smmu_attr; +} + + +/* TBD if you vcm_back again what happens? */ +int vcm_back(struct res *res, struct physmem *physmem) +{ + unsigned long flags; + struct vcm *vcm; + struct phys_chunk *chunk; + size_t va = 0; + int ret; + int attr; + + spin_lock_irqsave(&vcmlock, flags); + + if (!res) { + vcm_err("NULL res\n"); + goto fail; + } + + vcm = res->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + switch (vcm->type) { + case VCM_DEVICE: + case VCM_EXT_KERNEL: /* hack part 1 */ + attr = vcm_to_smmu_attr(res->attr); + if (attr == -1) { + vcm_err("Bad SMMU attr\n"); + goto fail; + } + break; + default: + attr = 0; + break; + } + + if (!physmem) { + vcm_err("NULL physmem\n"); + goto fail; + } + + if (res->len == 0) { + vcm_err("res->len is 0\n"); + goto fail; + } + + if (physmem->len == 0) { + vcm_err("physmem->len is 0\n"); + goto fail; + } + + if (res->len != physmem->len) { + vcm_err("res->len (%i) != physmem->len (%i)\n", + res->len, physmem->len); + goto fail; + } + + if (physmem->is_cont) { + if (physmem->res == 0) { + vcm_err("cont physmem->res is 0"); + goto fail; + } + } else { + /* fail if no physmem */ + if (list_empty(&physmem->alloc_head.allocated)) { + vcm_err("no allocated phys memory"); + goto fail; + } + } + + ret = vcm_no_assoc(res->vcm); + if (ret == 1) { + vcm_err("can't back un associated VCM\n"); + goto fail; + } + + if (ret == -1) { + vcm_err("vcm_no_assoc() ret -1\n"); + goto fail; + } + + ret = vcm_all_activated(res->vcm); + if (ret == 0) { + vcm_err("can't back, not all associations are activated\n"); + goto fail_eagain; + } + + if (ret == -1) { + vcm_err("vcm_all_activated() ret -1\n"); + goto fail; + } + + va = res->dev_addr; + + list_for_each_entry(chunk, &physmem->alloc_head.allocated, + allocated) { + struct vcm *vcm = res->vcm; + size_t chunk_size = vcm_alloc_idx_to_size(chunk->size_idx); + + switch (vcm->type) { + case VCM_DEVICE: + { +#ifdef CONFIG_SMMU + struct avcm *avcm; + /* map all */ + list_for_each_entry(avcm, &vcm->assoc_head, + assoc_elm) { + + ret = smmu_map( + (struct smmu_dev *) avcm->dev, + chunk->pa, va, chunk_size, attr); + if (ret != 0) { + vcm_err("smmu_map(%p, %p, %p, 0x%x," + "0x%x)" + " ret %i", + (void *) avcm->dev, + (void *) chunk->pa, + (void *) va, + (int) chunk_size, attr, ret); + goto fail; + /* TODO handle weird inter-map case */ + } + } + break; +#else + vcm_err("No SMMU support - VCM_DEVICE not supported\n"); + goto fail; +#endif + } + + case VCM_EXT_KERNEL: + { + unsigned int pages_in_chunk = chunk_size / PAGE_SIZE; + unsigned long loc_va = va; + unsigned long loc_pa = chunk->pa; + + const struct mem_type *mtype; + + /* TODO: get this based on MEMTYPE */ + mtype = get_mem_type(MT_DEVICE); + if (!mtype) { + vcm_err("mtype is 0\n"); + goto fail; + } + + /* TODO: Map with the same chunk size */ + while (pages_in_chunk--) { + ret = ioremap_page(loc_va, + loc_pa, + mtype); + if (ret != 0) { + vcm_err("ioremap_page(%p, %p, %p) ret" + " %i", (void *) loc_va, + (void *) loc_pa, + (void *) mtype, ret); + goto fail; + /* TODO handle weird + inter-map case */ + } + + /* hack part 2 */ + /* we're changing the PT entry behind + * linux's back + */ + ret = cpu_set_attr(loc_va, PAGE_SIZE, attr); + if (ret != 0) { + vcm_err("cpu_set_attr(%p, %lu, %x)" + "ret %i\n", + (void *) loc_va, PAGE_SIZE, + attr, ret); + goto fail; + /* TODO handle weird + inter-map case */ + } + + res->mapped = 1; + + loc_va += PAGE_SIZE; + loc_pa += PAGE_SIZE; + } + + flush_cache_vmap(va, loc_va); + break; + } + case VCM_ONE_TO_ONE: + va = chunk->pa; + break; + default: + /* this should never happen */ + goto fail; + } + + va += chunk_size; + /* also add res to the allocated chunk list of refs */ + } + + /* note the reservation */ + res->physmem = physmem; + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_eagain: + spin_unlock_irqrestore(&vcmlock, flags); + return -EAGAIN; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_unback(struct res *res) +{ + unsigned long flags; + struct vcm *vcm; + struct physmem *physmem; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + + if (!res) + goto fail; + + vcm = res->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!res->physmem) { + vcm_err("can't unback a non-backed reservation\n"); + goto fail; + } + + physmem = res->physmem; + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + if (list_empty(&physmem->alloc_head.allocated)) { + vcm_err("physmem allocation is empty\n"); + goto fail; + } + + ret = vcm_no_assoc(res->vcm); + if (ret == 1) { + vcm_err("can't unback a unassociated reservation\n"); + goto fail; + } + + if (ret == -1) { + vcm_err("vcm_no_assoc(%p) ret -1\n", (void *) res->vcm); + goto fail; + } + + ret = vcm_all_activated(res->vcm); + if (ret == 0) { + vcm_err("can't unback, not all associations are active\n"); + goto fail_eagain; + } + + if (ret == -1) { + vcm_err("vcm_all_activated(%p) ret -1\n", (void *) res->vcm); + goto fail; + } + + + switch (vcm->type) { + case VCM_EXT_KERNEL: + if (!res->mapped) { + vcm_err("can't unback an unmapped VCM_EXT_KERNEL" + " VCM\n"); + goto fail; + } + + /* vunmap free's vm_area */ + vunmap(res->vm_area->addr); + res->vm_area = 0; + + res->mapped = 0; + break; + + case VCM_DEVICE: + { +#ifdef CONFIG_SMMU + struct phys_chunk *chunk; + size_t va = res->dev_addr; + + list_for_each_entry(chunk, &physmem->alloc_head.allocated, + allocated) { + struct vcm *vcm = res->vcm; + size_t chunk_size = + vcm_alloc_idx_to_size(chunk->size_idx); + struct avcm *avcm; + + /* un map all */ + list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm) { + ret = smmu_unmap( + (struct smmu_dev *) avcm->dev, + va, chunk_size); + if (ret != 0) { + vcm_err("smmu_unmap(%p, %p, 0x%x)" + " ret %i", + (void *) avcm->dev, + (void *) va, + (int) chunk_size, ret); + goto fail; + /* TODO handle weird inter-unmap state*/ + } + } + va += chunk_size; + /* may to a light unback, depending on the requested + * functionality + */ + } +#else + vcm_err("No SMMU support - VCM_DEVICE memory not supported\n"); + goto fail; +#endif + break; + } + + case VCM_ONE_TO_ONE: + break; + default: + /* this should never happen */ + goto fail; + } + + /* clear the reservation */ + res->physmem = 0; + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_eagain: + spin_unlock_irqrestore(&vcmlock, flags); + return -EAGAIN; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +enum memtarget_t vcm_get_memtype_of_res(struct res *res) +{ + return VCM_INVALID; +} + +static int vcm_free_max_munch_cont(struct phys_chunk *head) +{ + struct phys_chunk *chunk, *tmp; + + if (!head) + return -1; + + list_for_each_entry_safe(chunk, tmp, &head->allocated, + allocated) { + list_del_init(&chunk->allocated); + } + + return 0; +} + +static int vcm_alloc_max_munch_cont(size_t start_addr, size_t len, + struct phys_chunk *head) +{ + /* this function should always succeed, since it + parallels a VCM */ + + int i, j; + + if (!head) { + vcm_err("head is NULL in continuous map.\n"); + goto fail; + } + + if (start_addr < __pa(bootmem_cont)) { + vcm_err("phys start addr (%p) < base (%p)\n", + (void *) start_addr, (void *) __pa(bootmem_cont)); + goto fail; + } + + if ((start_addr + len) >= (__pa(bootmem_cont) + CONT_SZ)) { + vcm_err("requested region (%p + %i) > " + " available region (%p + %i)", + (void *) start_addr, (int) len, + (void *) __pa(bootmem_cont), CONT_SZ); + goto fail; + } + + i = (start_addr - __pa(bootmem_cont))/SZ_4K; + + for (j = 0; j < ARRAY_SIZE(chunk_sizes); ++j) { + while (len/chunk_sizes[j]) { + if (!list_empty(&cont_phys_chunk[i].allocated)) { + vcm_err("chunk %i ( addr %p) already mapped\n", + i, (void *) (start_addr + + (i*chunk_sizes[j]))); + goto fail_free; + } + list_add_tail(&cont_phys_chunk[i].allocated, + &head->allocated); + cont_phys_chunk[i].size_idx = j; + + len -= chunk_sizes[j]; + i += chunk_sizes[j]/SZ_4K; + } + } + + if (len % SZ_4K) { + if (!list_empty(&cont_phys_chunk[i].allocated)) { + vcm_err("chunk %i (addr %p) already mapped\n", + i, (void *) (start_addr + (i*SZ_4K))); + goto fail_free; + } + len -= SZ_4K; + list_add_tail(&cont_phys_chunk[i].allocated, + &head->allocated); + + i++; + } + + return i; + +fail_free: + { + struct phys_chunk *chunk, *tmp; + /* just remove from list, if we're double alloc'ing + we don't want to stamp on the other guy */ + list_for_each_entry_safe(chunk, tmp, &head->allocated, + allocated) { + list_del(&chunk->allocated); + } + } +fail: + return 0; +} + +struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len, + u32 attr) +{ + unsigned long flags; + int ret; + struct physmem *physmem = NULL; + int blocks_allocated; + + spin_lock_irqsave(&vcmlock, flags); + + physmem = kzalloc(sizeof(*physmem), GFP_KERNEL); + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + physmem->memtype = memtype; + physmem->len = len; + physmem->attr = attr; + + INIT_LIST_HEAD(&physmem->alloc_head.allocated); + + if (attr & VCM_PHYS_CONT) { + if (!cont_vcm) { + vcm_err("cont_vcm is NULL\n"); + goto fail2; + } + + physmem->is_cont = 1; + + /* TODO: get attributes */ + physmem->res = __vcm_reserve(cont_vcm, len, 0); + if (physmem->res == 0) { + vcm_err("contiguous space allocation failed\n"); + goto fail2; + } + + /* if we're here we know we have memory, create + the shadow physmem links*/ + blocks_allocated = + vcm_alloc_max_munch_cont( + physmem->res->dev_addr, + len, + &physmem->alloc_head); + + if (blocks_allocated == 0) { + vcm_err("shadow physmem allocation failed\n"); + goto fail3; + } + } else { + blocks_allocated = vcm_alloc_max_munch(len, + &physmem->alloc_head); + if (blocks_allocated == 0) { + vcm_err("physical allocation failed:" + " vcm_alloc_max_munch(%i, %p) ret 0\n", + len, &physmem->alloc_head); + goto fail2; + } + } + + spin_unlock_irqrestore(&vcmlock, flags); + return physmem; + +fail3: + ret = __vcm_unreserve(physmem->res); + if (ret != 0) { + vcm_err("vcm_unreserve(%p) ret %i during cleanup", + (void *) physmem->res, ret); + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + } +fail2: + kfree(physmem); +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +} + + +int vcm_phys_free(struct physmem *physmem) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + if (physmem->is_cont) { + if (physmem->res == 0) { + vcm_err("contiguous reservation is NULL\n"); + goto fail; + } + + ret = vcm_free_max_munch_cont(&physmem->alloc_head); + if (ret != 0) { + vcm_err("failed to free physical blocks:" + " vcm_free_max_munch_cont(%p) ret %i\n", + (void *) &physmem->alloc_head, ret); + goto fail; + } + + ret = __vcm_unreserve(physmem->res); + if (ret != 0) { + vcm_err("failed to free virtual blocks:" + " vcm_unreserve(%p) ret %i\n", + (void *) physmem->res, ret); + goto fail; + } + + } else { + + ret = vcm_alloc_free_blocks(&physmem->alloc_head); + if (ret != 0) { + vcm_err("failed to free physical blocks:" + " vcm_alloc_free_blocks(%p) ret %i\n", + (void *) &physmem->alloc_head, ret); + goto fail; + } + } + + memset(physmem, 0, sizeof(*physmem)); + + kfree(physmem); + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +struct avcm *vcm_assoc(struct vcm *vcm, struct device *dev, u32 attr) +{ + unsigned long flags; + struct avcm *avcm = NULL; + + spin_lock_irqsave(&vcmlock, flags); + + if (!vcm) { + vcm_err("vcm is NULL\n"); + goto fail; + } + + if (!dev) { + vcm_err("dev is NULL\n"); + goto fail; + } + + if (vcm->type == VCM_EXT_KERNEL && !list_empty(&vcm->assoc_head)) { + vcm_err("only one device may be assocoated with a" + " VCM_EXT_KERNEL\n"); + goto fail; + } + + avcm = kzalloc(sizeof(*avcm), GFP_KERNEL); + if (!avcm) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret NULL\n", sizeof(*avcm)); + goto fail; + } + + avcm->dev = dev; + + avcm->vcm = vcm; + avcm->attr = attr; + avcm->is_active = 0; + + INIT_LIST_HEAD(&avcm->assoc_elm); + list_add(&avcm->assoc_elm, &vcm->assoc_head); + + spin_unlock_irqrestore(&vcmlock, flags); + return avcm; + +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +} + + +int vcm_deassoc(struct avcm *avcm) +{ + unsigned long flags; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) { + vcm_err("avcm is NULL\n"); + goto fail; + } + + if (list_empty(&avcm->assoc_elm)) { + vcm_err("nothing to deassociate\n"); + goto fail; + } + + if (avcm->is_active) { + vcm_err("association still activated\n"); + goto fail_busy; + } + + list_del(&avcm->assoc_elm); + + memset(avcm, 0, sizeof(*avcm)); + + kfree(avcm); + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_busy: + spin_unlock_irqrestore(&vcmlock, flags); + return -EBUSY; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_set_assoc_attr(struct avcm *avcm, u32 attr) +{ + return 0; +} + + +int vcm_activate(struct avcm *avcm) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) { + vcm_err("avcm is NULL\n"); + goto fail; + } + + vcm = avcm->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!avcm->dev) { + vcm_err("cannot activate without a device\n"); + goto fail_nodev; + } + + if (avcm->is_active) { + vcm_err("double activate\n"); + goto fail_busy; + } + + if (vcm->type == VCM_DEVICE) { +#ifdef CONFIG_SMMU + int ret = smmu_is_active((struct smmu_dev *) avcm->dev); + if (ret == -1) { + vcm_err("smmu_is_active(%p) ret -1\n", + (void *) avcm->dev); + goto fail_dev; + } + + if (ret == 1) { + vcm_err("SMMU is already active\n"); + goto fail_busy; + } + + /* TODO, pmem check */ + ret = smmu_activate((struct smmu_dev *) avcm->dev); + if (ret != 0) { + vcm_err("smmu_activate(%p) ret %i" + " SMMU failed to activate\n", + (void *) avcm->dev, ret); + goto fail_dev; + } +#else + vcm_err("No SMMU support - cannot activate/deactivate\n"); + goto fail_nodev; +#endif + } + + avcm->is_active = 1; + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + +#ifdef CONFIG_SMMU +fail_dev: + spin_unlock_irqrestore(&vcmlock, flags); + return -1; +#endif +fail_busy: + spin_unlock_irqrestore(&vcmlock, flags); + return -EBUSY; +fail_nodev: + spin_unlock_irqrestore(&vcmlock, flags); + return -ENODEV; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_deactivate(struct avcm *avcm) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) + goto fail; + + vcm = avcm->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!avcm->dev) { + vcm_err("cannot deactivate without a device\n"); + goto fail; + } + + if (!avcm->is_active) { + vcm_err("double deactivate\n"); + goto fail_nobusy; + } + + if (vcm->type == VCM_DEVICE) { +#ifdef CONFIG_SMMU + int ret = smmu_is_active((struct smmu_dev *) avcm->dev); + if (ret == -1) { + vcm_err("smmu_is_active(%p) ret %i\n", + (void *) avcm->dev, ret); + goto fail_dev; + } + + if (ret == 0) { + vcm_err("double SMMU deactivation\n"); + goto fail_nobusy; + } + + /* TODO, pmem check */ + ret = smmu_deactivate((struct smmu_dev *) avcm->dev); + if (ret != 0) { + vcm_err("smmu_deactivate(%p) ret %i\n", + (void *) avcm->dev, ret); + goto fail_dev; + } +#else + vcm_err("No SMMU support - cannot activate/deactivate\n"); + goto fail; +#endif + } + + avcm->is_active = 0; + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +#ifdef CONFIG_SMMU +fail_dev: + spin_unlock_irqrestore(&vcmlock, flags); + return -1; +#endif +fail_nobusy: + spin_unlock_irqrestore(&vcmlock, flags); + return -ENOENT; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + +struct bound *vcm_create_bound(struct vcm *vcm, size_t len) +{ + return 0; +} + + +int vcm_free_bound(struct bound *bound) +{ + return -1; +} + + +struct res *vcm_reserve_from_bound(struct bound *bound, size_t len, + u32 attr) +{ + return 0; +} + + +size_t vcm_get_bound_start_addr(struct bound *bound) +{ + return 0; +} + + +size_t vcm_get_bound_len(struct bound *bound) +{ + return 0; +} + + +struct physmem *vcm_map_phys_addr(size_t phys, size_t len) +{ + return 0; +} + + +size_t vcm_get_next_phys_addr(struct physmem *physmem, size_t phys, size_t *len) +{ + return 0; +} + +struct res *vcm_get_res(unsigned long dev_addr, struct vcm *vcm) +{ + return 0; +} + + +size_t vcm_translate(size_t src_dev, struct vcm *src_vcm, struct vcm *dst_vcm) +{ + return 0; +} + + +size_t vcm_get_phys_num_res(size_t phys) +{ + return 0; +} + + +struct res *vcm_get_next_phys_res(size_t phys, struct res *res, size_t *len) +{ + return 0; +} + + +size_t vcm_get_pgtbl_pa(struct vcm *vcm) +{ + return 0; +} + + +/* No lock needed, smmu_translate has its own lock */ +size_t vcm_dev_addr_to_phys_addr(struct device *dev, unsigned long dev_addr) +{ +#ifdef CONFIG_SMMU + int ret; + ret = smmu_translate((struct smmu_dev *) dev, dev_addr); + if (ret == -1) + vcm_err("smmu_translate(%p, %p) ret %i\n", + (void *) dev, (void *) dev_addr, ret); + + return ret; +#else + vcm_err("No support for SMMU - manual translation not supported\n"); + return -1; +#endif +} + + +/* No lock needed, bootmem_cont never changes after */ +size_t vcm_get_cont_memtype_pa(enum memtype_t memtype) +{ + if (memtype != VCM_MEMTYPE_0) { + vcm_err("memtype != VCM_MEMTYPE_0\n"); + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont 0\n"); + goto fail; + } + + return (size_t) __pa(bootmem_cont); +fail: + return 0; +} + + +/* No lock needed, constant */ +size_t vcm_get_cont_memtype_len(enum memtype_t memtype) +{ + if (memtype != VCM_MEMTYPE_0) { + vcm_err("memtype != VCM_MEMTYPE_0\n"); + return 0; + } + + return CONT_SZ; +} + +int vcm_hook(struct device *dev, vcm_handler handler, void *data) +{ +#ifdef CONFIG_SMMU + int ret; + + ret = smmu_hook_irpt((struct smmu_dev *) dev, handler, data); + if (ret != 0) + vcm_err("smmu_hook_irpt(%p, %p, %p) ret %i\n", (void *) dev, + (void *) handler, (void *) data, ret); + + return ret; +#else + vcm_err("No support for SMMU - interrupts not supported\n"); + return -1; +#endif +} + + +size_t vcm_hw_ver(struct device *dev) +{ + return 0; +} + + +static int vcm_cont_phys_chunk_init(void) +{ + int i; + int cont_pa; + + if (!cont_phys_chunk) { + vcm_err("cont_phys_chunk 0\n"); + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont 0\n"); + goto fail; + } + + cont_pa = (int) __pa(bootmem_cont); + + for (i = 0; i < CONT_SZ/PAGE_SIZE; ++i) { + cont_phys_chunk[i].pa = (int) cont_pa; cont_pa += PAGE_SIZE; + cont_phys_chunk[i].size_idx = IDX_4K; + INIT_LIST_HEAD(&cont_phys_chunk[i].allocated); + } + + return 0; + +fail: + return -1; +} + + +int vcm_sys_init(void) +{ + int ret; + printk(KERN_INFO "VCM Initialization\n"); + if (!bootmem) { + vcm_err("bootmem is 0\n"); + ret = -1; + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont is 0\n"); + ret = -1; + goto fail; + } + + ret = vcm_setup_tex_classes(); + if (ret != 0) { + printk(KERN_INFO "Could not determine TEX attribute mapping\n"); + ret = -1; + goto fail; + } + + + ret = vcm_alloc_init(__pa(bootmem)); + if (ret != 0) { + vcm_err("vcm_alloc_init(%p) ret %i\n", (void *) __pa(bootmem), + ret); + ret = -1; + goto fail; + } + + cont_phys_chunk = kzalloc(sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE), + GFP_KERNEL); + if (!cont_phys_chunk) { + vcm_err("kzalloc(%lu, GFP_KERNEL) ret 0", + sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE)); + goto fail_free; + } + + /* the address and size will hit our special case unless we + pass an override */ + cont_vcm = vcm_create_flagged(0, __pa(bootmem_cont), CONT_SZ); + if (cont_vcm == 0) { + vcm_err("vcm_create_flagged(0, %p, %i) ret 0\n", + (void *) __pa(bootmem_cont), CONT_SZ); + ret = -1; + goto fail_free2; + } + + ret = vcm_cont_phys_chunk_init(); + if (ret != 0) { + vcm_err("vcm_cont_phys_chunk_init() ret %i\n", ret); + goto fail_free3; + } + + printk(KERN_INFO "VCM Initialization OK\n"); + return 0; + +fail_free3: + ret = __vcm_free(cont_vcm); + if (ret != 0) { + vcm_err("vcm_free(%p) ret %i during failure path\n", + (void *) cont_vcm, ret); + return -1; + } + +fail_free2: + kfree(cont_phys_chunk); + cont_phys_chunk = 0; + +fail_free: + ret = vcm_alloc_destroy(); + if (ret != 0) + vcm_err("vcm_alloc_destroy() ret %i during failure path\n", + ret); + + ret = -1; +fail: + return ret; +} + + +int vcm_sys_destroy(void) +{ + int ret = 0; + + if (!cont_phys_chunk) { + vcm_err("cont_phys_chunk is 0\n"); + return -1; + } + + if (!cont_vcm) { + vcm_err("cont_vcm is 0\n"); + return -1; + } + + ret = __vcm_free(cont_vcm); + if (ret != 0) { + vcm_err("vcm_free(%p) ret %i\n", (void *) cont_vcm, ret); + return -1; + } + + cont_vcm = 0; + + kfree(cont_phys_chunk); + cont_phys_chunk = 0; + + ret = vcm_alloc_destroy(); + if (ret != 0) { + vcm_err("vcm_alloc_destroy() ret %i\n", ret); + return -1; + } + + return ret; +} + +int vcm_init(void) +{ + int ret; + + bootmem = __alloc_bootmem(BOOTMEM_SZ, BOOTMEM_ALIGN, 0); + if (!bootmem) { + vcm_err("segregated block pool alloc failed:" + " __alloc_bootmem(%i, %i, 0)\n", + BOOTMEM_SZ, BOOTMEM_ALIGN); + goto fail; + } + + bootmem_cont = __alloc_bootmem(CONT_SZ, CONT_ALIGN, 0); + if (!bootmem_cont) { + vcm_err("contiguous pool alloc failed:" + " __alloc_bootmem(%i, %i, 0)\n", + CONT_SZ, CONT_ALIGN); + goto fail_free; + } + + ret = vcm_sys_init(); + if (ret != 0) { + vcm_err("vcm_sys_init() ret %i\n", ret); + goto fail_free2; + } + + return 0; + +fail_free2: + free_bootmem(__pa(bootmem_cont), CONT_SZ); +fail_free: + free_bootmem(__pa(bootmem), BOOTMEM_SZ); +fail: + return -1; +}; + +/* Useful for testing, and if VCM is ever unloaded */ +void vcm_exit(void) +{ + int ret; + + if (!bootmem_cont) { + vcm_err("bootmem_cont is 0\n"); + goto fail; + } + + if (!bootmem) { + vcm_err("bootmem is 0\n"); + goto fail; + } + + ret = vcm_sys_destroy(); + if (ret != 0) { + vcm_err("vcm_sys_destroy() ret %i\n", ret); + goto fail; + } + + free_bootmem(__pa(bootmem_cont), CONT_SZ); + free_bootmem(__pa(bootmem), BOOTMEM_SZ); +fail: + return; +} +early_initcall(vcm_init); +module_exit(vcm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Zach Pfeffer "); diff --git a/include/linux/vcm.h b/include/linux/vcm.h new file mode 100644 index 0000000..b95dab5 --- /dev/null +++ b/include/linux/vcm.h @@ -0,0 +1,661 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef _VCM_H_ +#define _VCM_H_ + + +/* All undefined types must be defined using platform specific headers */ + +#include + + +/* + * Virtual contiguous memory (VCM) region primitives. + * + * Current memory mapping software uses a CPU centric management + * model. This makes sense in general, average hardware only contains an + * CPU MMU and possibly a graphics MMU. If every device in the system + * has one or more MMUs a CPU centric MM programming model breaks down. + * + * Looking at mapping from a system-wide perspective reveals a general + * graph problem. Each node that talks to memory, either through an MMU + * or directly (via physical memory) can be thought of as the device end + * of a mapping edge. The other edge is the physical memory that is + * mapped. + * + * In the direct mapped case, it is useful to give the device an + * MMU. This one-to-one MMU allows direct mapped devices to + * participate in graph management, they simply see memory through a + * one-to-one mapping. + * + * The CPU nodes can also be brought under the same mapping + * abstraction with the use of a light overlay on the existing + * VMM. This light overlay brings the VMM's page table abstraction for + * each process and the kernel into the graph management API. + * + * Taken together this system wide approach provides a capability that + * is greater than the sum of its parts by allowing users to reason + * about system wide mapping issues without getting bogged down in CPU + * centric device page table management issues. + */ + + +/* + * Creating, freeing and managing VCMs. + * + * A VCM region is a virtual space that can be reserved from and + * associated with one or more devices. At creation the user can + * specify an offset to start addresses and a length of the entire VCM + * region. Reservations out of a VCM region are always contiguous. + */ + + +/** + * vcm_create() - Create a VCM region + * @start_addr: The starting address of the VCM region. + * @len: The len of the VCM region. This must be at least + * vcm_get_min_page_size() bytes. + * + * A VCM typically abstracts a page table. + * + * All functions in this API are passed and return opaque things + * because the underlying implementations will vary. The goal + * is really graph management. vcm_create() creates the "device end" + * of an edge in the mapping graph. + * + * The return value is non-zero if a VCM has successfully been + * created. It will return zero if a VCM region cannot be created or + * len is invalid. + */ +struct vcm *vcm_create(unsigned long start_addr, size_t len); + + +/** + * vcm_create_from_prebuilt() - Create a VCM region from an existing region + * @ext_vcm_id: An external opaque value that allows the + * implementation to reference an already built table. + * + * The ext_vcm_id will probably reference a page table that's been built + * by the VM. + * + * The platform specific implementation will provide this. + * + * The return value is non-zero if a VCM has successfully been created. + */ +struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id); + + +/** + * vcm_clone() - Clone a VCM + * @vcm: A VCM to clone from. + * + * Perform a VCM "deep copy." The resulting VCM will match the original at + * the point of cloning. Subsequent updates to either VCM will only be + * seen by that VCM. + * + * The return value is non-zero if a VCM has been successfully cloned. + */ +struct vcm *vcm_clone(struct vcm *vcm); + + +/** + * vcm_get_start_addr() - Get the starting address of the VCM region. + * @vcm: The VCM we're interested in getting the starting + * address of. + * + * The return value will be 1 if an error has occurred. + */ +size_t vcm_get_start_addr(struct vcm *vcm); + + +/** + * vcm_get_len() - Get the length of the VCM region. + * @vcm: The VCM we're interested in reading the length from. + * + * The return value will be non-zero for a valid VCM. VCM regions + * cannot have 0 len. + */ +size_t vcm_get_len(struct vcm *vcm); + + +/** + * vcm_free() - Free a VCM. + * @vcm: The VCM we're interested in freeing. + * + * The return value is 0 if the VCM has been freed or: + * -EBUSY The VCM region contains reservations or has been + * associated (active or not) and cannot be freed. + * -EINVAL The vcm argument is invalid. + */ +int vcm_free(struct vcm *vcm); + + +/* + * Creating, freeing and managing reservations out of a VCM. + * + */ + +/** + * vcm_reserve() - Create a reservation from a VCM region. + * @vcm: The VCM region to reserve from. + * @len: The length of the reservation. Must be at least + * vcm_get_min_page_size() bytes. + * @attr: See 'Reservation Attributes'. + * + * A reservation, res_t, is a contiguous range from a VCM region. + * + * The return value is non-zero if a reservation has been successfully + * created. It is 0 if any of the parameters are invalid. + */ +struct res *vcm_reserve(struct vcm *vcm, size_t len, u32 attr); + + +/** + * vcm_reserve_at() - Make a reservation at a given logical location. + * @memtarget: A logical location to start the reservation from. + * @vcm: The VCM region to start the reservation from. + * @len: The length of the reservation. + * @attr: See 'Reservation Attributes'. + * + * The return value is non-zero if a reservation has been successfully + * created. + */ +struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm *vcm, + size_t len, u32 attr); + + +/** + * vcm_get_vcm_from_res() - Return the VCM region of a reservation. + * @res: The reservation to return the VCM region of. + * + * Te return value will be non-zero if the reservation is valid. A valid + * reservation is always associated with a VCM region; there is no such + * thing as an orphan reservation. + */ +struct vcm *vcm_get_vcm_from_res(struct res *res); + + +/** + * vcm_unreserve() - Unreserve the reservation. + * @res: The reservation to unreserve. + * + * The return value will be 0 if the reservation was successfully + * unreserved and: + * -EBUSY The reservation is still backed, + * -EINVAL The vcm argument is invalid. + */ +int vcm_unreserve(struct res *res); + + +/** + * vcm_set_res_attr() - Set attributes of an existing reservation. + * @res: An existing reservation of interest. + * @attr: See 'Reservation Attributes'. + * + * This function can only be used on an existing reservation; there + * are no orphan reservations. All attributes can be set on a existing + * reservation. + * + * The return value will be 0 for a success, otherwise it will be: + * -EINVAL res or attr are invalid. + */ +int vcm_set_res_attr(struct res *res, u32 attr); + + +/** + * vcm_get_num_res() - Return the number of reservations in a VCM region. + * @vcm: The VCM region of interest. + */ +size_t vcm_get_num_res(struct vcm *vcm); + + +/** + * vcm_get_next_res() - Read each reservation one at a time. + * @vcm: The VCM region of interest. + * @res: Contains the last reservation. Pass NULL on the + * first call. + * + * This function works like a foreach reservation in a VCM region. + * + * The return value will be non-zero for each reservation in a VCM. A + * zero indicates no further reservations. + */ +struct res *vcm_get_next_res(struct vcm *vcm, struct res *res); + + +/** + * vcm_res_copy() - Copy len bytes from one reservation to another. + * @to: The reservation to copy to. + * @from: The reservation to copy from. + * @len: The length of bytes to copy. + * + * The return value is the number of bytes copied. + */ +size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, size_t + from_off, size_t len); + + +/** + * vcm_get_min_page_size() - Return the minimum page size supported by + * the architecture. + */ +size_t vcm_get_min_page_size(void); + + +/** + * vcm_back() - Physically back a reservation. + * @res: The reservation containing the virtual contiguous + * region to back. + * @physmem: The physical memory that will back the virtual + * contiguous memory region. + * + * One VCM can be associated with multiple devices. When you vcm_back() + * each association must be active. This is not strictly necessary. It may + * be changed in the future. + * + * This function returns 0 on a successful physical backing. Otherwise + * it returns: + * -EINVAL res or physmem is invalid or res's len + * is different from physmem's len. + * -EAGAIN Try again, one of the devices hasn't been activated. + */ +int vcm_back(struct res *res, struct physmem *physmem); + + +/** + * vcm_unback() - Unback a reservation. + * @res: The reservation to unback. + * + * One VCM can be associated with multiple devices. When you vcm_unback() + * each association must be active. + * + * This function returns 0 on a successful unbacking. Otherwise + * it returns: + * -EINVAL res is invalid. + * -EAGAIN Try again, one of the devices hasn't been activated. + */ +int vcm_unback(struct res *res); + + +/** + * vcm_phys_alloc() - Allocate physical memory for the VCM region. + * @memtype: The memory type to allocate. + * @len: The length of the allocation. + * @attr: See 'Physical Allocation Attributes'. + * + * This function will allocate chunks of memory according to the attr + * it is passed. + * + * The return value is non-zero if physical memory has been + * successfully allocated. + */ +struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len, + u32 attr); + + +/** + * vcm_phys_free() - Free a physical allocation. + * @physmem: The physical allocation to free. + * + * The return value is 0 if the physical allocation has been freed or: + * -EBUSY Their are reservation mapping the physical memory. + * -EINVAL The physmem argument is invalid. + */ +int vcm_phys_free(struct physmem *physmem); + + +/** + * vcm_get_physmem_from_res() - Return a reservation's physmem + * @res: An existing reservation of interest. + * + * The return value will be non-zero on success, otherwise it will be: + * -EINVAL res is invalid + * -ENOMEM res is unbacked + */ +struct physmem *vcm_get_physmem_from_res(struct res *res); + + +/** + * vcm_get_memtype_of_physalloc() - Return the memtype of a reservation. + * @physmem: The physical allocation of interest. + * + * This function returns the memtype of a reservation or VCM_INVALID + * if res is invalid. + */ +enum memtype_t vcm_get_memtype_of_physalloc(struct physmem *physmem); + + +/* + * Associate a VCM with a device, activate that association and remove it. + * + */ + +/** + * vcm_assoc() - Associate a VCM with a device. + * @vcm: The VCM region of interest. + * @dev: The device to associate the VCM with. + * @attr: See 'Association Attributes'. + * + * This function returns non-zero if a association is made. It returns 0 + * if any of its parameters are invalid or VCM_ATTR_VALID is not present. + */ +struct avcm *vcm_assoc(struct vcm *vcm, struct device *dev, u32 attr); + + +/** + * vcm_deassoc() - Deassociate a VCM from a device. + * @avcm: The association we want to break. + * + * The function returns 0 on success or: + * -EBUSY The association is currently activated. + * -EINVAL The avcm parameter is invalid. + */ +int vcm_deassoc(struct avcm *avcm); + + +/** + * vcm_set_assoc_attr() - Set an AVCM's attributes. + * @avcm: The AVCM of interest. + * @attr: The new attr. See 'Association Attributes'. + * + * Every attribute can be set at runtime if an association isn't activated. + * + * This function returns 0 on success or: + * -EBUSY The association is currently activated. + * -EINVAL The avcm parameter is invalid. + */ +int vcm_set_assoc_attr(struct avcm *avcm, u32 attr); + + +/** + * vcm_get_assoc_attr() - Return an AVCM's attributes. + * @avcm: The AVCM of interest. + * + * This function returns 0 on error. + */ +u32 vcm_get_assoc_attr(struct avcm *avcm); + + +/** + * vcm_activate() - Activate an AVCM. + * @avcm: The AVCM to activate. + * + * You have to deactivate, before you activate. + * + * This function returns 0 on success or: + * -EINVAL avcm is invalid + * -ENODEV no device + * -EBUSY device is already active + * -1 hardware failure + */ +int vcm_activate(struct avcm *avcm); + + +/** + * vcm_deactivate() - Deactivate an association. + * @avcm: The AVCM to deactivate. + * + * This function returns 0 on success or: + * -ENOENT avcm is not activate + * -EINVAL avcm is invalid + * -1 Hardware failure + */ +int vcm_deactivate(struct avcm *avcm); + + +/** + * vcm_is_active() - Query if an AVCM is active. + * @avcm: The AVCM of interest. + * + * returns 0 for not active, 1 for active or -EINVAL for error. + * + */ +int vcm_is_active(struct avcm *avcm); + + +/* + * Create, manage and remove a boundary in a VCM. + */ + +/** + * vcm_create_bound() - Create a bound in a VCM. + * @vcm: The VCM that needs a bound. + * @len: The len of the bound. + * + * The allocator picks the virtual addresses of the bound. + * + * This function returns non-zero if a bound was created. + */ +struct bound *vcm_create_bound(struct vcm *vcm, size_t len); + + +/** + * vcm_free_bound() - Free a bound. + * @bound: The bound to remove. + * + * This function returns 0 if bound has been removed or: + * -EBUSY The bound contains reservations and cannot be] + * removed. + * -EINVAL The bound is invalid. + */ +int vcm_free_bound(struct bound *bound); + + +/** + * vcm_reserve_from_bound() - Make a reservation from a bounded area. + * @bound: The bound to reserve from. + * @len: The len of the reservation. + * @attr: See 'Reservation Attributes'. + * + * The return value is non-zero on success. It is 0 if any parameter + * is invalid. + */ +struct res *vcm_reserve_from_bound(struct bound *bound, size_t len, + u32 attr); + + +/** + * vcm_get_bound_start_addr() - Return the starting device address of the bound + * @bound: The bound of interest. + * + * On success this function returns the starting addres of the bound. On error + * it returns: + * 1 bound is invalid. + */ +size_t vcm_get_bound_start_addr(struct bound *bound); + + +/* + * Perform low-level control over VCM regions and reservations. + */ + +/** + * vcm_map_phys_addr() - Produce a physmem from a contiguous + * physical address + * + * @phys: The physical address of the contiguous range. + * @len: The len of the contiguous address range. + * + * Returns non-zero on success, 0 on failure. + */ +struct physmem *vcm_map_phys_addr(phys_addr_t phys, size_t len); + + +/** + * vcm_get_next_phys_addr() - Get the next physical addr and len of a + * physmem. + * @res: The physmem of interest. + * @phys: The current physical address. Set this to NULL to + * start the iteration. + * @len: An output: the len of the next physical segment. + * + * physmem's may contain physically discontiguous sections. This + * function returns the next physical address and len. Pass NULL to + * phys to get the first physical address. The len of the physical + * segment is returned in *len. + * + * Returns 0 if there is no next physical address. + */ +size_t vcm_get_next_phys_addr(struct physmem *physmem, phys_addr_t phys, + size_t *len); + + +/** + * vcm_get_res() - Return the reservation from a device address and a VCM + * @dev_addr: The device address of interest. + * @vcm: The VCM that contains the reservation + * + * This function returns 0 if there is no reservation whose device + * address is dev_addr. + */ +struct res *vcm_get_res(unsigned long dev_addr, struct vcm *vcm); + + +/** + * vcm_translate() - Translate from one device address to another. + * @src_dev: The source device address. + * @src_vcm: The source VCM region. + * @dst_vcm: The destination VCM region. + * + * Derive the device address from a VCM region that maps the same physical + * memory as a device address from another VCM region. + * + * On success this function returns the device address of a translation. On + * error it returns: + * 1 res is invalid. + */ +size_t vcm_translate(size_t src_dev, struct vcm *src_vcm, + struct vcm *dst_vcm); + + +/** + * vcm_get_phys_num_res() - Return the number of reservations mapping a + * physical address. + * @phys: The physical address to read. + */ +size_t vcm_get_phys_num_res(size_t phys); + + +/** + * vcm_get_next_phys_res() - Return the next reservation mapped to a physical + * address. + * @phys: The physical address to map. + * @res: The starting reservation. Set this to NULL for the first + * reservation. + * @len: The virtual length of the reservation + * + * This function returns 0 for the last reservation or no reservation. + */ +struct res *vcm_get_next_phys_res(size_t phys, struct res *res, size_t *len); + + +/** + * vcm_get_pgtbl_pa() - Return the physcial address of a VCM's page table. + * @vcm: The VCM region of interest. + * + * This function returns non-zero on success. + */ +size_t vcm_get_pgtbl_pa(struct vcm *vcm); + + +/** + * vcm_get_cont_memtype_pa() - Return the phys base addr of a memtype's + * first contiguous region. + * @memtype: The memtype of interest. + * + * This function returns non-zero on success. A zero return indicates that + * the given memtype does not have a contiguous region or that the memtype + * is invalid. + */ +size_t vcm_get_cont_memtype_pa(enum memtype_t memtype); + + +/** + * vcm_get_cont_memtype_len() - Return the len of a memtype's + * first contiguous region. + * @memtype: The memtype of interest. + * + * This function returns non-zero on success. A zero return indicates that + * the given memtype does not have a contiguous region or that the memtype + * is invalid. + */ +size_t vcm_get_cont_memtype_len(enum memtype_t memtype); + + +/** + * vcm_dev_addr_to_phys_addr() - Perform a device address page-table lookup. + * @dev: The device that has the table. + * @dev_addr: The device address to map. + * + * This function returns the pa of a va from a device's page-table. It will + * fault if the dev_addr is not mapped. + */ +size_t vcm_dev_addr_to_phys_addr(struct device *dev, unsigned long dev_addr); + + +/* + * Fault Hooks + * + * vcm_hook() + */ + +/** + * vcm_hook() - Add a fault handler. + * @dev: The device. + * @handler: The handler. + * @data: A private piece of data that will get passed to the + * handler. + * + * This function returns 0 for a successful registration or: + * -EINVAL The arguments are invalid. + */ +int vcm_hook(struct device *dev, vcm_handler handler, void *data); + + +/* + * Low level, platform agnostic, HW control. + * + * vcm_hw_ver() + */ + +/** + * vcm_hw_ver() - Return the hardware version of a device, if it has one. + * @dev: The device. + */ +size_t vcm_hw_ver(struct device *dev); + + +/* bring-up init, destroy */ +int vcm_sys_init(void); +int vcm_sys_destroy(void); + +#endif /* _VCM_H_ */ + diff --git a/include/linux/vcm_types.h b/include/linux/vcm_types.h new file mode 100644 index 0000000..671e80f --- /dev/null +++ b/include/linux/vcm_types.h @@ -0,0 +1,338 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef VCM_TYPES_H +#define VCM_TYPES_H + +#include +#include +#include +#include +#include +#include +#include + +/* + * Reservation Attributes + * + * Used in vcm_reserve(), vcm_reserve_at(), vcm_set_res_attr() and + * vcm_reserve_bound(). + * + * VCM_READ Specifies that the reservation can be read. + * VCM_WRITE Specifies that the reservation can be written. + * VCM_EXECUTE Specifies that the reservation can be executed. + * VCM_USER Specifies that this reservation is used for + * userspace access. + * VCM_SUPERVISOR Specifies that this reservation is used for + * supervisor access. + * VCM_SECURE Specifies that the target of the reservation is + * secure. The usage of this setting is TBD. + * + * Caching behavior as a 4 bit field: + * VCM_NOTCACHED The VCM region is not cached. + * VCM_INNER_WB_WA The VCM region is inner cached + * and is write-back and write-allocate. + * VCM_INNER_WT_NWA The VCM region is inner cached and is + * write-through and no-write-allocate. + * VCM_INNER_WB_NWA The VCM region is inner cached and is + * write-back and no-write-allocate. + * VCM_OUTER_WB_WA The VCM region is outer cached and is + * write-back and write-allocate. + * VCM_OUTER_WT_NWA The VCM region is outer cached and is + * write-through and no-write-allocate. + * VCM_OUTER_WB_NWA The VCM region is outer cached and is + * write-back and no-write-allocate. + * VCM_WB_WA The VCM region is cached and is write + * -back and write-allocate. + * VCM_WT_NWA The VCM region is cached and is write + * -through and no-write-allocate. + * VCM_WB_NWA The VCM region is cached and is write + * -back and no-write-allocate. + */ + +#define VCM_CACHE_POLICY (0xF << 0) + +#define VCM_READ (1UL << 9) +#define VCM_WRITE (1UL << 8) +#define VCM_EXECUTE (1UL << 7) +#define VCM_USER (1UL << 6) +#define VCM_SUPERVISOR (1UL << 5) +#define VCM_SECURE (1UL << 4) +#define VCM_NOTCACHED (0UL << 0) +#define VCM_WB_WA (1UL << 0) +#define VCM_WB_NWA (2UL << 0) +#define VCM_WT (3UL << 0) + + +/* + * Physical Allocation Attributes + * + * Used in vcm_phys_alloc(). + * + * Alignment as a power of 2 starting at 4 KB. 5 bit field. + * 1 = 4KB, 2 = 8KB, etc. + * + * Specifies that the reservation should have the + * alignment specified. + * + * VCM_4KB Specifies that the reservation should use 4KB pages. + * VCM_64KB Specifies that the reservation should use 64KB pages. + * VCM_1MB specifies that the reservation should use 1MB pages. + * VCM_ALL Specifies that the reservation should use all + * available page sizes. + * VCM_PHYS_CONT Specifies that a reservation should be backed with + * physically contiguous memory. + * VCM_COHERENT Specifies that the reservation must be kept coherent + * because it's shared. + */ + +#define VCM_ALIGNMENT_MASK (0x1FUL << 6) /* 5-bit field */ +#define VCM_4KB (1UL << 5) +#define VCM_64KB (1UL << 4) +#define VCM_1MB (1UL << 3) +#define VCM_ALL (1UL << 2) +#define VCM_PAGE_SEL_MASK (0xFUL << 2) +#define VCM_PHYS_CONT (1UL << 1) +#define VCM_COHERENT (1UL << 0) + + +#define SHIFT_4KB (12) + +#define ALIGN_REQ_BYTES(attr) (1UL << (((attr & VCM_ALIGNMENT_MASK) >> 6) + 12)) +/* set the alignment in pow 2, 0 = 4KB */ +#define SET_ALIGN_REQ_BYTES(attr, align) \ + ((attr & ~VCM_ALIGNMENT_MASK) | ((align << 6) & VCM_ALIGNMENT_MASK)) + +/* + * Association Attributes + * + * Used in vcm_assoc(), vcm_set_assoc_attr(). + * + * VCM_USE_LOW_BASE Use the low base register. + * VCM_USE_HIGH_BASE Use the high base register. + * + * VCM_SPLIT A 5 bit field that defines the + * high/low split. This value defines + * the number of 0's left-filled into the + * split register. Addresses that match + * this will use VCM_USE_LOW_BASE + * otherwise they'll use + * VCM_USE_HIGH_BASE. An all 0's value + * directs all translations to + * VCM_USE_LOW_BASE. + */ + +#define VCM_SPLIT (1UL << 3) +#define VCM_USE_LOW_BASE (1UL << 2) +#define VCM_USE_HIGH_BASE (1UL << 1) + +/* + * External VCMs + * + * Used in vcm_create_from_prebuilt() + * + * Externally created VCM IDs for creating kernel and user space + * mappings to VCMs and kernel and user space buffers out of + * VCM_MEMTYPE_0,1,2, etc. + * + */ +#define VCM_PREBUILT_KERNEL 1 +#define VCM_PREBUILT_USER 2 + +/** + * enum memtarget_t - A logical location in a VCM. + * @vcm_start: Indicates the start of a VCM_REGION. + */ +enum memtarget_t { + VCM_START +}; + + +/** + * enum memtype_t - A logical location in a VCM. + * @vcm_memtype_0: Generic memory type 0 + * @vcm_memtype_1: Generic memory type 1 + * @vcm_memtype_2: Generic memory type 2 + * + * A memtype encapsulates a platform specific memory arrangement. The + * memtype needn't refer to a single type of memory, it can refer to a + * set of memories that can back a reservation. + * + */ +enum memtype_t { + VCM_INVALID, + VCM_MEMTYPE_0, + VCM_MEMTYPE_1, + VCM_MEMTYPE_2, +}; + + +/** + * vcm_handler - The signature of the fault hook. + * @dev: The device id of the faulting device. + * @data: The generic data pointer. + * @fault_data: System specific common fault data. + * + * The handler should return 0 for success. This indicates that the + * fault was handled. A non-zero return value is an error and will be + * propagated up the stack. + */ +typedef int (*vcm_handler)(size_t dev, void *data, void *fault_data); + + +/** + * enum vcm_type - The type of VCM. + * @vcm_memtype_0: Generic memory type 0 + * @vcm_memtype_1: Generic memory type 1 + * @vcm_memtype_2: Generic memory type 2 + * + * A memtype encapsulates a platform specific memory arrangement. The + * memtype needn't refer to a single type of memory, it can refer to a + * set of memories that can back a reservation. + * + */ +enum vcm_type { + VCM_DEVICE, + VCM_EXT_KERNEL, + VCM_EXT_USER, + VCM_ONE_TO_ONE, +}; + +/** + * struct vcm - A Virtually Contiguous Memory region. + * @start_addr: The starting address of the VCM region. + * @len: The len of the VCM region. This must be at least + * vcm_min() bytes. + */ +struct vcm { + /* public */ + unsigned long start_addr; + size_t len; + + + /* private */ + enum vcm_type type; + + struct device *dev; /* opaque device control */ + + /* allocator dependent */ + struct gen_pool *pool; + + struct list_head res_head; + + /* this will be a very short list */ + struct list_head assoc_head; +}; + +/** + * struct avcm - A VCM to device association + * @vcm: The VCM region of interest. + * @dev: The device to associate the VCM with. + * @attr: See 'Association Attributes'. + */ +struct avcm { + /* public */ + struct vcm *vcm; + struct device *dev; + u32 attr; + + /* private */ + struct list_head assoc_elm; + + int is_active; /* is this particular association active */ +}; + + +/** + * struct bound - A boundary to reserve from in a VCM region. + * @vcm: The VCM that needs a bound. + * @len: The len of the bound. + */ +struct bound { + struct vcm *vcm; + size_t len; +}; + + +/** + * struct physmem - A physical memory allocation. + * @memtype: The memory type of the VCM region. + * @len: The len of the physical memory allocation. + * @attr: See 'Physical Allocation Attributes'. + * + */ +struct physmem { + /* public */ + enum memtype_t memtype; + size_t len; +b u32 attr; + + /* private */ + struct phys_chunk alloc_head; + + /* if the physmem is cont then use the built in VCM */ + int is_cont; + struct res *res; +}; + + +/** + * struct res - A reservation in a VCM region. + * @vcm: The VCM region to reserve from. + * @len: The length of the reservation. Must be at least vcm_min() + * bytes. + * @attr: See 'Reservation Attributes'. + * @dev_addr: The device-side address. + */ +struct res { + /* public */ + struct vcm *vcm; + size_t len; + u32 attr; + unsigned long dev_addr; + + + /* private */ + struct physmem *physmem; + + /* allocator dependent */ + size_t alignment_req; + size_t aligned_len; + unsigned long ptr; + + struct list_head res_elm; + + /* type VCM_EXT_KERNEL */ + struct vm_struct *vm_area; + int mapped; +}; + +extern int chunk_sizes[NUM_CHUNK_SIZES]; + +#endif /* VCM_TYPES_H */ From patchwork Fri Jun 4 13:54:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindraj.R" X-Patchwork-Id: 104280 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o54DsGx2020224 for ; Fri, 4 Jun 2010 13:54:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754302Ab0FDNyN (ORCPT ); Fri, 4 Jun 2010 09:54:13 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:38553 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752849Ab0FDNyL (ORCPT ); Fri, 4 Jun 2010 09:54:11 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o54Ds7xS008304 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 4 Jun 2010 08:54:07 -0500 Received: from webmail.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o54Ds34D022743; Fri, 4 Jun 2010 08:54:04 -0500 (CDT) Received: from 192.168.10.88 (proxying for 10.24.255.18) (SquirrelMail authenticated user x0100947); by dbdmail.itg.ti.com with HTTP; Fri, 4 Jun 2010 19:24:06 +0530 (IST) Message-ID: <33418.192.168.10.88.1275659646.squirrel@dbdmail.itg.ti.com> Date: Fri, 4 Jun 2010 19:24:06 +0530 (IST) Subject: [PATCH v3] serial: Add OMAP high-speed UART driver From: "Govindraj.R" To: linux-omap@vger.kernel.org, linux-serial@vger.kernel.org Cc: "Kevin Hilman" , "Tony Lindgren" User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 04 Jun 2010 13:54:17 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h new file mode 100644 index 0000000..0d6f076 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -0,0 +1,129 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __OMAP_SERIAL_H__ +#define __OMAP_SERIAL_H__ + +#include +#include + +#include +#include + +#define DRIVER_NAME "omap-hsuart" + +/* + * Use tty device name as ttyO, [O -> OMAP] + * in bootargs we specify as console=ttyO0 if uart1 + * is used as console uart. + */ +#define OMAP_SERIAL_NAME "ttyO" + +#define OMAP_MDR1_DISABLE 0x07 +#define OMAP_MDR1_MODE13X 0x03 +#define OMAP_MDR1_MODE16X 0x00 +#define OMAP_MODE13X_SPEED 230400 + +/* + * LCR = 0XBF: Switch to Configuration Mode B. + * In configuration mode b allow access + * to EFR,DLL,DLH. + * Reference OMAP TRM Chapter 17 + * Section: 1.4.3 Mode Selection + */ +#define OMAP_UART_LCR_CONF_MDB 0XBF + +/* WER = 0x7F + * Enable module level wakeup in WER reg + */ +#define OMAP_UART_WER_MOD_WKUP 0X7F + +/* Enable XON/XOFF flow control on output */ +#define OMAP_UART_SW_TX 0x04 + +/* Enable XON/XOFF flow control on input */ +#define OMAP_UART_SW_RX 0x04 + +#define OMAP_UART_SYSC_RESET 0X07 +#define OMAP_UART_TCR_TRIG 0X0F +#define OMAP_UART_SW_CLR 0XF0 +#define OMAP_UART_FIFO_CLR 0X06 + +#define OMAP_UART_DMA_CH_FREE -1 + +#define RX_TIMEOUT (3 * HZ) +#define OMAP_MAX_HSUART_PORTS 4 + +#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA + +struct omap_uart_port_info { + bool dma_enabled; /* To specify DMA Mode */ + unsigned int uartclk; /* UART clock rate */ + void __iomem *membase; /* ioremap cookie or NULL */ + resource_size_t mapbase; /* resource base */ + unsigned long irqflags; /* request_irq flags */ + upf_t flags; /* UPF_* flags */ +}; + +struct uart_omap_dma { + u8 uart_dma_tx; + u8 uart_dma_rx; + int rx_dma_channel; + int tx_dma_channel; + dma_addr_t rx_buf_dma_phys; + dma_addr_t tx_buf_dma_phys; + unsigned int uart_base; + /* + * Buffer for rx dma.It is not required for tx because the buffer + * comes from port structure. + */ + unsigned char *rx_buf; + unsigned int prev_rx_dma_pos; + int tx_buf_size; + int tx_dma_used; + int rx_dma_used; + spinlock_t tx_lock; + spinlock_t rx_lock; + /* timer to poll activity on rx dma */ + struct timer_list rx_timer; + int rx_buf_size; + int rx_timeout; +}; + +struct uart_omap_port { + struct uart_port port; + struct uart_omap_dma uart_dma; + struct platform_device *pdev; + + unsigned char ier; + unsigned char lcr; + unsigned char mcr; + unsigned char fcr; + unsigned char efr; + + int use_dma; + /* + * Some bits in registers are cleared on a read, so they must + * be saved whenever the register is read but the bits will not + * be immediately processed. + */ + unsigned int lsr_break_flag; + unsigned char msr_saved_flags; + char name[20]; + unsigned long port_activity; +}; + +#endif /* __OMAP_SERIAL_H__ */ diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b23165..c5386c7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1380,6 +1380,33 @@ config SERIAL_OF_PLATFORM Currently, only 8250 compatible ports are supported, but others can easily be added. +config SERIAL_OMAP + tristate "OMAP serial port support" + depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 + select SERIAL_CORE + help + If you have a machine based on an Texas Instruments OMAP CPU you + can enable its onboard serial ports by enabling this option. + + By enabling this option you take advantage of dma feature available + with the omap-serial driver. DMA support can be enabled from platform + data. + +config SERIAL_OMAP_CONSOLE + bool "Console on OMAP serial port" + depends on SERIAL_OMAP + select SERIAL_CORE_CONSOLE + help + Select this option if you would like to use omap serial port as + console. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyOx". (Try "man bootparam" or see the documentation of + your boot loader about how to pass options to the kernel at + boot time.) + config SERIAL_OF_PLATFORM_NWPSERIAL tristate "NWP serial port driver" depends on PPC_OF && PPC_DCR diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 208a855..c4d7304 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -84,3 +84,4 @@ obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o +obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o diff --git a/drivers/serial/omap-serial.c b/drivers/serial/omap-serial.c new file mode 100644 index 0000000..b907616 --- /dev/null +++ b/drivers/serial/omap-serial.c @@ -0,0 +1,1318 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Note: This driver is made seperate from 8250 driver as we cannot + * over load 8250 driver with omap platform specific configuration for + * features like DMA, it makes easier to implement features like DMA and + * hardware flow control and software flow control configuration with + * this driver as required for the omap-platform. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; + +/* Forward declaration of functions */ +static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); +static void serial_omap_rx_timeout(unsigned long uart_no); +static int serial_omap_start_rxdma(struct uart_omap_port *up); + +static inline unsigned int serial_in(struct uart_omap_port *up, int offset) +{ + offset <<= up->port.regshift; + return readw(up->port.membase + offset); +} + +static inline void serial_out(struct uart_omap_port *up, int offset, int value) +{ + offset <<= up->port.regshift; + writew(value, up->port.membase + offset); +} + +static inline void serial_omap_clear_fifos(struct uart_omap_port *up) +{ + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + serial_out(up, UART_FCR, 0); +} + +/** + * serial_omap_get_divisor() - calculate divisor value + * @port: uart port info + * @baud: baudrate for which divisor needs to be calculated. + * + * We have written our own function to get the divisor so as to support + * 13x mode. 3Mbps Baudrate as an different divisor. + * Reference OMAP TRM Chapter 17: + * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates + * referring to oversampling - divisor value + * baudrate 460,800 to 3,686,400 all have divisor 13 + * except 3,000,000 which has divisor value 16 + */ +static unsigned int +serial_omap_get_divisor(struct uart_port *port, unsigned int baud) +{ + unsigned int divisor; + + if (baud > OMAP_MODE13X_SPEED && baud != 3000000) + divisor = 13; + else + divisor = 16; + return port->uartclk/(baud * divisor); +} + +static void serial_omap_stop_rxdma(struct uart_omap_port *up) +{ + if (up->uart_dma.rx_dma_used) { + del_timer(&up->uart_dma.rx_timer); + omap_stop_dma(up->uart_dma.rx_dma_channel); + omap_free_dma(up->uart_dma.rx_dma_channel); + up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; + up->uart_dma.rx_dma_used = false; + } +} + +static void serial_omap_enable_ms(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); + up->ier |= UART_IER_MSI; + serial_out(up, UART_IER, up->ier); +} + +static void serial_omap_stop_tx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + if (up->use_dma && + up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { + /* + * Check if dma is still active. If yes do nothing, + * return. Else stop dma + */ + if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) + return; + omap_stop_dma(up->uart_dma.tx_dma_channel); + omap_free_dma(up->uart_dma.tx_dma_channel); + up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; + } + + if (up->ier & UART_IER_THRI) { + up->ier &= ~UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serial_omap_stop_rx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + if (up->use_dma) + serial_omap_stop_rxdma(up); + up->ier &= ~UART_IER_RLSI; + up->port.read_status_mask &= ~UART_LSR_DR; + serial_out(up, UART_IER, up->ier); +} + +static inline void receive_chars(struct uart_omap_port *up, int *status) +{ + struct tty_struct *tty = up->port.state->port.tty; + unsigned int flag; + unsigned char ch, lsr = *status; + int max_count = 256; + + do { + if (likely(lsr & UART_LSR_DR)) + ch = serial_in(up, UART_RX); + flag = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { + /* + * For statistics only + */ + if (lsr & UART_LSR_BI) { + lsr &= ~(UART_LSR_FE | UART_LSR_PE); + up->port.icount.brk++; + /* + * We do the SysRQ and SAK checking + * here because otherwise the break + * may get masked by ignore_status_mask + * or read_status_mask. + */ + if (uart_handle_break(&up->port)) + goto ignore_char; + } else if (lsr & UART_LSR_PE) + up->port.icount.parity++; + else if (lsr & UART_LSR_FE) + up->port.icount.frame++; + if (lsr & UART_LSR_OE) + up->port.icount.overrun++; + + /* + * Mask off conditions which should be ignored. + */ + lsr &= up->port.read_status_mask; + +#ifdef CONFIG_SERIAL_OMAP_CONSOLE + if (up->port.line == up->port.cons->index) { + /* Recover the break flag from console xmit */ + lsr |= up->lsr_break_flag; + up->lsr_break_flag = 0; + } +#endif + if (lsr & UART_LSR_BI) + flag = TTY_BREAK; + else if (lsr & UART_LSR_PE) + flag = TTY_PARITY; + else if (lsr & UART_LSR_FE) + flag = TTY_FRAME; + } + + if (uart_handle_sysrq_char(&up->port, ch)) + goto ignore_char; + uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); +ignore_char: + lsr = serial_in(up, UART_LSR); + } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); + spin_unlock(&up->port.lock); + tty_flip_buffer_push(tty); + spin_lock(&up->port.lock); +} + +static void transmit_chars(struct uart_omap_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count; + + if (up->port.x_char) { + serial_out(up, UART_TX, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { + serial_omap_stop_tx(&up->port); + return; + } + count = up->port.fifosize / 4; + do { + serial_out(up, UART_TX, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (uart_circ_empty(xmit)) + serial_omap_stop_tx(&up->port); +} + +static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) +{ + if (!(up->ier & UART_IER_THRI)) { + up->ier |= UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serial_omap_start_tx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + struct circ_buf *xmit; + unsigned int start; + int ret = 0; + + if (!up->use_dma) { + serial_omap_enable_ier_thri(up); + return; + } + + xmit = &up->port.state->xmit; + if (uart_circ_empty(xmit) || up->uart_dma.tx_dma_used) + return; + + if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) + ret = omap_request_dma(up->uart_dma.uart_dma_tx, + "UART Tx DMA", + (void *)uart_tx_dma_callback, up, + &(up->uart_dma.tx_dma_channel)); + + if (ret < 0) { + serial_omap_enable_ier_thri(up); + return; + } + + start = up->uart_dma.tx_buf_dma_phys + + (xmit->tail & (UART_XMIT_SIZE - 1)); + spin_lock(&(up->uart_dma.tx_lock)); + up->uart_dma.tx_dma_used = true; + spin_unlock(&(up->uart_dma.tx_lock)); + + up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); + /* + * It is a circular buffer. See if the buffer has wounded back. + * If yes it will have to be transferred in two separate dma + * transfers + */ + if (start + up->uart_dma.tx_buf_size >= + up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) + up->uart_dma.tx_buf_size = + (up->uart_dma.tx_buf_dma_phys + + UART_XMIT_SIZE) - start; + + omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, start, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.tx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_tx, 0); + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.tx_dma_channel); +} + +static unsigned int check_modem_status(struct uart_omap_port *up) +{ + int status; + status = serial_in(up, UART_MSR); + + status |= up->msr_saved_flags; + up->msr_saved_flags = 0; + + if ((status & UART_MSR_ANY_DELTA) == 0) + return status; + if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && + up->port.state != NULL) { + if (status & UART_MSR_TERI) + up->port.icount.rng++; + if (status & UART_MSR_DDSR) + up->port.icount.dsr++; + if (status & UART_MSR_DDCD) + uart_handle_dcd_change + (&up->port, status & UART_MSR_DCD); + if (status & UART_MSR_DCTS) + uart_handle_cts_change + (&up->port, status & UART_MSR_CTS); + wake_up_interruptible(&up->port.state->port.delta_msr_wait); + } + + return status; +} + +/** + * serial_omap_irq() - This handles the interrupt from one port + * @irq: uart port irq number + * @dev_id: uart port info + */ +static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) +{ + struct uart_omap_port *up = dev_id; + unsigned int iir, lsr; + unsigned long flags; + + iir = serial_in(up, UART_IIR); + if (iir & UART_IIR_NO_INT) + return IRQ_NONE; + + spin_lock_irqsave(&up->port.lock, flags); + lsr = serial_in(up, UART_LSR); + if (iir & UART_IER_RLSI) { + if (!up->use_dma) { + if (lsr & UART_LSR_DR) + receive_chars(up, &lsr); + } else { + up->ier &= ~UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + if (serial_omap_start_rxdma(up) != 0) + if (lsr & UART_LSR_DR) + receive_chars(up, &lsr); + } + } + + check_modem_status(up); + if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) + transmit_chars(up); + + spin_unlock_irqrestore(&up->port.lock, flags); + up->port_activity = jiffies; + return IRQ_HANDLED; +} + +static unsigned int serial_omap_tx_empty(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + unsigned int ret = 0; + + dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); + spin_lock_irqsave(&up->port.lock, flags); + ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; + spin_unlock_irqrestore(&up->port.lock, flags); + + return ret; +} + +static unsigned int serial_omap_get_mctrl(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char status; + unsigned int ret = 0; + + status = check_modem_status(up); + dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); + + if (status & UART_MSR_DCD) + ret |= TIOCM_CAR; + if (status & UART_MSR_RI) + ret |= TIOCM_RNG; + if (status & UART_MSR_DSR) + ret |= TIOCM_DSR; + if (status & UART_MSR_CTS) + ret |= TIOCM_CTS; + return ret; +} + +static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char mcr = 0; + + dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); + if (mctrl & TIOCM_RTS) + mcr |= UART_MCR_RTS; + if (mctrl & TIOCM_DTR) + mcr |= UART_MCR_DTR; + if (mctrl & TIOCM_OUT1) + mcr |= UART_MCR_OUT1; + if (mctrl & TIOCM_OUT2) + mcr |= UART_MCR_OUT2; + if (mctrl & TIOCM_LOOP) + mcr |= UART_MCR_LOOP; + + mcr |= up->mcr; + serial_out(up, UART_MCR, mcr); +} + +static void serial_omap_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + + dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); + spin_lock_irqsave(&up->port.lock, flags); + if (break_state == -1) + up->lcr |= UART_LCR_SBC; + else + up->lcr &= ~UART_LCR_SBC; + serial_out(up, UART_LCR, up->lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int serial_omap_startup(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + int retval; + + /* + * Allocate the IRQ + */ + retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, + up->name, up); + if (retval) + return retval; + + dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); + + /* + * Clear the FIFO buffers and disable them. + * (they will be reenabled in set_termios()) + */ + serial_omap_clear_fifos(up); + /* For Hardware flow control */ + serial_out(up, UART_MCR, UART_MCR_RTS); + + /* + * Clear the interrupt registers. + */ + (void) serial_in(up, UART_LSR); + if (serial_in(up, UART_LSR) & UART_LSR_DR) + (void) serial_in(up, UART_RX); + (void) serial_in(up, UART_IIR); + (void) serial_in(up, UART_MSR); + + /* + * Now, initialize the UART + */ + serial_out(up, UART_LCR, UART_LCR_WLEN8); + spin_lock_irqsave(&up->port.lock, flags); + /* + * Most PC uarts need OUT2 raised to enable interrupts. + */ + up->port.mctrl |= TIOCM_OUT2; + serial_omap_set_mctrl(&up->port, up->port.mctrl); + spin_unlock_irqrestore(&up->port.lock, flags); + + up->msr_saved_flags = 0; + if (up->use_dma) { + free_page((unsigned long)up->port.state->xmit.buf); + up->port.state->xmit.buf = dma_alloc_coherent(NULL, + UART_XMIT_SIZE, + (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), + 0); + init_timer(&(up->uart_dma.rx_timer)); + up->uart_dma.rx_timer.function = serial_omap_rx_timeout; + up->uart_dma.rx_timer.data = up->pdev->id; + /* Currently the buffer size is 4KB. Can increase it */ + up->uart_dma.rx_buf = dma_alloc_coherent(NULL, + up->uart_dma.rx_buf_size, + (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); + } + /* + * Finally, enable interrupts. Note: Modem status interrupts + * are set via set_termios(), which will be occurring imminently + * anyway, so we don't enable them here. + */ + up->ier = UART_IER_RLSI | UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + + up->port_activity = jiffies; + return 0; +} + +static void serial_omap_shutdown(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + + dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); + /* + * Disable interrupts from this port + */ + up->ier = 0; + serial_out(up, UART_IER, 0); + + spin_lock_irqsave(&up->port.lock, flags); + up->port.mctrl &= ~TIOCM_OUT2; + serial_omap_set_mctrl(&up->port, up->port.mctrl); + spin_unlock_irqrestore(&up->port.lock, flags); + + /* + * Disable break condition and FIFOs + */ + serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); + serial_omap_clear_fifos(up); + + /* + * Read data port to reset things, and then free the irq + */ + if (serial_in(up, UART_LSR) & UART_LSR_DR) + (void) serial_in(up, UART_RX); + if (up->use_dma) { + int tmp; + dma_free_coherent(up->port.dev, + UART_XMIT_SIZE, up->port.state->xmit.buf, + up->uart_dma.tx_buf_dma_phys); + up->port.state->xmit.buf = NULL; + serial_omap_stop_rx(port); + dma_free_coherent(up->port.dev, + up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, + up->uart_dma.rx_buf_dma_phys); + up->uart_dma.rx_buf = NULL; + tmp = serial_in(up, UART_OMAP_SYSC) & OMAP_UART_SYSC_RESET; + serial_out(up, UART_OMAP_SYSC, tmp); /* force-idle */ + } + free_irq(up->port.irq, up); +} + +static inline void +serial_omap_configure_xonxoff + (struct uart_omap_port *up, struct ktermios *termios) +{ + unsigned char efr = 0; + + up->lcr = serial_in(up, UART_LCR); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); + + serial_out(up, UART_XON1, termios->c_cc[VSTART]); + serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); + + /* clear SW control mode bits */ + efr = up->efr; + efr &= OMAP_UART_SW_CLR; + + /* + * IXON Flag: + * Enable XON/XOFF flow control on output. + * Transmit XON1, XOFF1 + */ + if (termios->c_iflag & IXON) + efr |= OMAP_UART_SW_TX; + + /* + * IXOFF Flag: + * Enable XON/XOFF flow control on input. + * Receiver compares XON1, XOFF1. + */ + if (termios->c_iflag & IXOFF) + efr |= OMAP_UART_SW_RX; + + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + up->mcr = serial_in(up, UART_MCR); + + /* + * IXANY Flag: + * Enable any character to restart output. + * Operation resumes after receiving any + * character after recognition of the XOFF character + */ + if (termios->c_iflag & IXANY) + up->mcr |= UART_MCR_XONANY; + + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); + /* Enable special char function UARTi.EFR_REG[5] and + * load the new software flow control mode IXON or IXOFF + * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. + */ + serial_out(up, UART_EFR, efr | UART_EFR_SCD); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); + serial_out(up, UART_LCR, up->lcr); +} + +static void +serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char cval = 0; + unsigned char efr = 0; + unsigned long flags = 0; + unsigned int baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + cval = UART_LCR_WLEN5; + break; + case CS6: + cval = UART_LCR_WLEN6; + break; + case CS7: + cval = UART_LCR_WLEN7; + break; + default: + case CS8: + cval = UART_LCR_WLEN8; + break; + } + + if (termios->c_cflag & CSTOPB) + cval |= UART_LCR_STOP; + if (termios->c_cflag & PARENB) + cval |= UART_LCR_PARITY; + if (!(termios->c_cflag & PARODD)) + cval |= UART_LCR_EPAR; + + /* + * Ask the core to calculate the divisor for us. + */ + + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); + quot = serial_omap_get_divisor(port, baud); + + up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | + UART_FCR_ENABLE_FIFO; + if (up->use_dma) + up->fcr |= UART_FCR_DMA_SELECT; + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= UART_LSR_BI; + + /* + * Characters to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= UART_LSR_BI; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_OE; + } + + /* + * ignore all characters if CREAD is not set + */ + if ((termios->c_cflag & CREAD) == 0) + up->port.ignore_status_mask |= UART_LSR_DR; + + /* + * Modem status interrupts + */ + up->ier &= ~UART_IER_MSI; + if (UART_ENABLE_MS(&up->port, termios->c_cflag)) + up->ier |= UART_IER_MSI; + serial_out(up, UART_IER, up->ier); + serial_out(up, UART_LCR, cval); /* reset DLAB */ + + /* FIFOs and DMA Settings */ + + /* FCR can be changed only when the + * baud clock is not running + * DLL_REG and DLH_REG set to 0. + */ + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_DLL, 0); + serial_out(up, UART_DLM, 0); + serial_out(up, UART_LCR, 0); + + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_LCR, 0); + up->mcr = serial_in(up, UART_MCR); + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + /* FIFO ENABLE, DMA MODE */ + serial_out(up, UART_FCR, up->fcr); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + if (up->use_dma) { + serial_out(up, UART_TI752_TLR, 0); + serial_out(up, UART_OMAP_SCR, + (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8)); + } + + serial_out(up, UART_EFR, up->efr); + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_MCR, up->mcr); + + /* Protocol, Baud Rate, and Interrupt Settings */ + + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_DISABLE); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_LCR, 0); + serial_out(up, UART_IER, 0); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ + serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ + + serial_out(up, UART_LCR, 0); + serial_out(up, UART_IER, up->ier); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + serial_out(up, UART_EFR, up->efr); + serial_out(up, UART_LCR, cval); + + if (baud > 230400 && baud != 3000000) + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE13X); + else + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE16X); + + /* Hardware Flow Control Configuration */ + + if (termios->c_cflag & CRTSCTS) { + efr |= (UART_EFR_CTS | UART_EFR_RTS); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + up->mcr = serial_in(up, UART_MCR); + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); + serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); + serial_out(up, UART_LCR, cval); + } + + serial_omap_set_mctrl(&up->port, up->port.mctrl); + /* Software Flow Control Configuration */ + if (termios->c_iflag & (IXON | IXOFF)) + serial_omap_configure_xonxoff(up, termios); + + spin_unlock_irqrestore(&up->port.lock, flags); + dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); +} + +static void +serial_omap_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char efr; + + dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, efr | UART_EFR_ECB); + serial_out(up, UART_LCR, 0); + + serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_EFR, efr); + serial_out(up, UART_LCR, 0); + /* Enable module level wake up */ + serial_out(up, UART_OMAP_WER, + (state != 0) ? OMAP_UART_WER_MOD_WKUP : 0); +} + +static void serial_omap_release_port(struct uart_port *port) +{ + dev_dbg(port->dev, "serial_omap_release_port+\n"); +} + +static int serial_omap_request_port(struct uart_port *port) +{ + dev_dbg(port->dev, "serial_omap_request_port+\n"); + return 0; +} + +static void serial_omap_config_port(struct uart_port *port, int flags) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", + up->pdev->id); + up->port.type = PORT_OMAP; +} + +static int +serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + /* we don't want the core code to modify any port params */ + dev_dbg(port->dev, "serial_omap_verify_port+\n"); + return -EINVAL; +} + +static const char * +serial_omap_type(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); + return up->name; +} + +#ifdef CONFIG_SERIAL_OMAP_CONSOLE + +static struct uart_omap_port *serial_omap_console_ports[4]; + +static struct uart_driver serial_omap_reg; + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void wait_for_xmitr(struct uart_omap_port *up) +{ + unsigned int status, tmout = 10000; + + /* Wait up to 10ms for the character(s) to be sent. */ + do { + status = serial_in(up, UART_LSR); + + if (status & UART_LSR_BI) + up->lsr_break_flag = UART_LSR_BI; + + if (--tmout == 0) + break; + udelay(1); + } while ((status & BOTH_EMPTY) != BOTH_EMPTY); + + /* Wait up to 1s for flow control if necessary */ + if (up->port.flags & UPF_CONS_FLOW) { + tmout = 1000000; + for (tmout = 1000000; tmout; tmout--) { + unsigned int msr = serial_in(up, UART_MSR); + up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; + if (msr & UART_MSR_CTS) + break; + udelay(1); + } + } +} + +static void serial_omap_console_putchar(struct uart_port *port, int ch) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + wait_for_xmitr(up); + serial_out(up, UART_TX, ch); +} + +static void +serial_omap_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_omap_port *up = serial_omap_console_ports[co->index]; + unsigned int ier; + + /* + * First save the IER then disable the interrupts + */ + ier = serial_in(up, UART_IER); + serial_out(up, UART_IER, 0); + + uart_console_write(&up->port, s, count, serial_omap_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + wait_for_xmitr(up); + serial_out(up, UART_IER, ier); + /* + * The receive handling will happen properly because the + * receive ready bit will still be set; it is not cleared + * on read. However, modem control will not, we must + * call it if we have saved something in the saved flags + * while processing with interrupts off. + */ + if (up->msr_saved_flags) + check_modem_status(up); +} + +static int __init +serial_omap_console_setup(struct console *co, char *options) +{ + struct uart_omap_port *up; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + int r; + + if (serial_omap_console_ports[co->index] == NULL) + return -ENODEV; + up = serial_omap_console_ports[co->index]; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + r = uart_set_options(&up->port, co, baud, parity, bits, flow); + + return r; +} + +static struct console serial_omap_console = { + .name = OMAP_SERIAL_NAME, + .write = serial_omap_console_write, + .device = uart_console_device, + .setup = serial_omap_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &serial_omap_reg, +}; + +static void serial_omap_add_console_port(struct uart_omap_port *up) +{ + serial_omap_console_ports[up->pdev->id] = up; +} + +#define OMAP_CONSOLE (&serial_omap_console) + +#else + +#define OMAP_CONSOLE NULL + +static inline void serial_omap_add_console_port(struct uart_omap_port *up) +{} + +#endif + +struct uart_ops serial_omap_pops = { + .tx_empty = serial_omap_tx_empty, + .set_mctrl = serial_omap_set_mctrl, + .get_mctrl = serial_omap_get_mctrl, + .stop_tx = serial_omap_stop_tx, + .start_tx = serial_omap_start_tx, + .stop_rx = serial_omap_stop_rx, + .enable_ms = serial_omap_enable_ms, + .break_ctl = serial_omap_break_ctl, + .startup = serial_omap_startup, + .shutdown = serial_omap_shutdown, + .set_termios = serial_omap_set_termios, + .pm = serial_omap_pm, + .type = serial_omap_type, + .release_port = serial_omap_release_port, + .request_port = serial_omap_request_port, + .config_port = serial_omap_config_port, + .verify_port = serial_omap_verify_port, +}; + +static struct uart_driver serial_omap_reg = { + .owner = THIS_MODULE, + .driver_name = "OMAP-SERIAL", + .dev_name = OMAP_SERIAL_NAME, + .nr = OMAP_MAX_HSUART_PORTS, + .cons = OMAP_CONSOLE, +}; + +static int +serial_omap_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct uart_omap_port *up = platform_get_drvdata(pdev); + + if (up) + uart_suspend_port(&serial_omap_reg, &up->port); + return 0; +} + +static int serial_omap_resume(struct platform_device *dev) +{ + struct uart_omap_port *up = platform_get_drvdata(dev); + + if (up) + uart_resume_port(&serial_omap_reg, &up->port); + return 0; +} + +static void serial_omap_rx_timeout(unsigned long uart_no) +{ + struct uart_omap_port *up = ui[uart_no]; + unsigned int curr_dma_pos, curr_transmitted_size; + unsigned int ret = 0; + + curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); + if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || + (curr_dma_pos == 0)) { + if (jiffies_to_msecs(jiffies - up->port_activity) < + RX_TIMEOUT) { + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + } else { + serial_omap_stop_rxdma(up); + up->ier |= UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + } + return; + } + + curr_transmitted_size = curr_dma_pos - + up->uart_dma.prev_rx_dma_pos; + up->port.icount.rx += curr_transmitted_size; + tty_insert_flip_string(up->port.state->port.tty, + up->uart_dma.rx_buf + + (up->uart_dma.prev_rx_dma_pos - + up->uart_dma.rx_buf_dma_phys), + curr_transmitted_size); + tty_flip_buffer_push(up->port.state->port.tty); + up->uart_dma.prev_rx_dma_pos = curr_dma_pos; + if (up->uart_dma.rx_buf_size + + up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { + ret = serial_omap_start_rxdma(up); + if (ret < 0) { + serial_omap_stop_rxdma(up); + up->ier |= UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + } + } else { + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + } + up->port_activity = jiffies; +} + +static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) +{ + return; +} + +static int serial_omap_start_rxdma(struct uart_omap_port *up) +{ + int ret = 0; + + if (up->uart_dma.rx_dma_channel == -1) { + ret = omap_request_dma(up->uart_dma.uart_dma_rx, + "UART Rx DMA", + (void *)uart_rx_dma_callback, up, + &(up->uart_dma.rx_dma_channel)); + if (ret < 0) + return ret; + + omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, + up->uart_dma.rx_buf_dma_phys, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.rx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_rx, 0); + } + up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.rx_dma_channel); + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + up->uart_dma.rx_dma_used = true; + return ret; +} + +static void serial_omap_continue_tx(struct uart_omap_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int start = up->uart_dma.tx_buf_dma_phys + + (xmit->tail & (UART_XMIT_SIZE - 1)); + + if (uart_circ_empty(xmit)) + return; + + up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); + /* + * It is a circular buffer. See if the buffer has wounded back. + * If yes it will have to be transferred in two separate dma + * transfers + */ + if (start + up->uart_dma.tx_buf_size >= + up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) + up->uart_dma.tx_buf_size = + (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; + omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, start, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.tx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_tx, 0); + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.tx_dma_channel); +} + +static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) +{ + struct uart_omap_port *up = (struct uart_omap_port *)data; + struct circ_buf *xmit = &up->port.state->xmit; + + xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ + (UART_XMIT_SIZE - 1); + up->port.icount.tx += up->uart_dma.tx_buf_size; + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (uart_circ_empty(xmit)) { + spin_lock(&(up->uart_dma.tx_lock)); + serial_omap_stop_tx(&up->port); + up->uart_dma.tx_dma_used = false; + spin_unlock(&(up->uart_dma.tx_lock)); + } else { + omap_stop_dma(up->uart_dma.tx_dma_channel); + serial_omap_continue_tx(up); + } + up->port_activity = jiffies; + return; +} + +static int serial_omap_probe(struct platform_device *pdev) +{ + struct uart_omap_port *up; + struct resource *mem, *irq, *dma_tx, *dma_rx; + struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; + int ret = -ENOSPC; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "no mem resource?\n"); + return -ENODEV; + } + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!irq) { + dev_err(&pdev->dev, "no irq resource?\n"); + return -ENODEV; + } + + if (!request_mem_region(mem->start, (mem->end - mem->start) + 1, + pdev->dev.driver->name)) { + dev_err(&pdev->dev, "memory region already claimed\n"); + return -EBUSY; + } + + dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); + if (!dma_rx) { + ret = -EINVAL; + goto err; + } + + dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); + if (!dma_tx) { + ret = -EINVAL; + goto err; + } + + up = kzalloc(sizeof(*up), GFP_KERNEL); + if (up == NULL) { + ret = -ENOMEM; + goto do_release_region; + } + sprintf(up->name, "OMAP UART%d", pdev->id); + up->pdev = pdev; + up->port.dev = &pdev->dev; + up->port.type = PORT_OMAP; + up->port.iotype = UPIO_MEM; + up->port.irq = irq->start; + + up->port.regshift = 2; + up->port.fifosize = 64; + up->port.ops = &serial_omap_pops; + up->port.line = pdev->id; + + up->port.membase = omap_up_info->membase; + up->port.mapbase = omap_up_info->mapbase; + up->port.flags = omap_up_info->flags; + up->port.irqflags = omap_up_info->irqflags; + up->port.uartclk = omap_up_info->uartclk; + up->uart_dma.uart_base = mem->start; + + if (omap_up_info->dma_enabled) { + up->uart_dma.uart_dma_tx = dma_tx->start; + up->uart_dma.uart_dma_rx = dma_rx->start; + up->use_dma = 1; + up->uart_dma.rx_buf_size = 4096; + up->uart_dma.rx_timeout = 1; + spin_lock_init(&(up->uart_dma.tx_lock)); + spin_lock_init(&(up->uart_dma.rx_lock)); + up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; + up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; + } + + ui[pdev->id] = up; + serial_omap_add_console_port(up); + + ret = uart_add_one_port(&serial_omap_reg, &up->port); + if (ret != 0) + goto do_release_region; + + platform_set_drvdata(pdev, up); + return 0; +err: + dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", + pdev->id, __func__, ret); +do_release_region: + release_mem_region(mem->start, (mem->end - mem->start) + 1); + return ret; +} + +static int serial_omap_remove(struct platform_device *dev) +{ + struct uart_omap_port *up = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + if (up) { + uart_remove_one_port(&serial_omap_reg, &up->port); + kfree(up); + } + return 0; +} + +static struct platform_driver serial_omap_driver = { + .probe = serial_omap_probe, + .remove = serial_omap_remove, + + .suspend = serial_omap_suspend, + .resume = serial_omap_resume, + .driver = { + .name = DRIVER_NAME, + }, +}; + +int __init serial_omap_init(void) +{ + int ret; + + ret = uart_register_driver(&serial_omap_reg); + if (ret != 0) + return ret; + ret = platform_driver_register(&serial_omap_driver); + if (ret != 0) + uart_unregister_driver(&serial_omap_reg); + return ret; +} + +void __exit serial_omap_exit(void) +{ + platform_driver_unregister(&serial_omap_driver); + uart_unregister_driver(&serial_omap_reg); +} + +module_init(serial_omap_init); +module_exit(serial_omap_exit); + +MODULE_DESCRIPTION("OMAP High Speed UART driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index f10db6e..300720f 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -186,6 +186,9 @@ #define PORT_ALTERA_JTAGUART 91 #define PORT_ALTERA_UART 92 +/* TI OMAP-UART */ +#define PORT_OMAP 93 + #ifdef __KERNEL__ #include From patchwork Mon Aug 10 10:25:09 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjeev Premi X-Patchwork-Id: 40385 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n7AAO8uq024448 for ; Mon, 10 Aug 2009 10:25:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752484AbZHJKZR (ORCPT ); Mon, 10 Aug 2009 06:25:17 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752706AbZHJKZR (ORCPT ); Mon, 10 Aug 2009 06:25:17 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:35886 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752484AbZHJKZQ (ORCPT ); Mon, 10 Aug 2009 06:25:16 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id n7AAPADX010267 for ; Mon, 10 Aug 2009 05:25:16 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id n7AAP9Hu017034; Mon, 10 Aug 2009 15:55:10 +0530 (IST) From: Sanjeev Premi To: linux-omap@vger.kernel.org Cc: Sanjeev Premi Subject: [PATCH] OMAP3: PM : Set DSP frequency corresponding to mpurate Date: Mon, 10 Aug 2009 15:55:09 +0530 Message-Id: <1249899909-5848-1-git-send-email-premi@ti.com> X-Mailer: git-send-email 1.6.2.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Argument 'mpurate' is used to change the MPU frequency at boot time. This patch changes the DSP frequency as per the OPP definition corresponding to the mpurate It also verifies if the specified mpurate is valid in the OPP table. Signed-off-by: Sanjeev Premi --- arch/arm/mach-omap2/clock34xx.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index c956fdc..b22d1f7 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -43,6 +43,7 @@ #include "prm-regbits-34xx.h" #include "cm.h" #include "cm-regbits-34xx.h" +#include "omap3-opp.h" static const struct clkops clkops_noncore_dpll_ops; @@ -1103,6 +1104,11 @@ void omap2_clk_prepare_for_reboot(void) */ static int __init omap2_clk_arch_init(void) { + short opp=0, valid=0; + short i; + unsigned long dsprate; + struct omap_opp *opp_table; + if (!mpurate) return -EINVAL; @@ -1111,16 +1117,53 @@ static int __init omap2_clk_arch_init(void) if (clk_set_rate(&virt_prcm_set, mpurate)) printk(KERN_ERR "Could not find matching MPU rate\n"); #endif + /* Check if mpurate is valid */ + if (mpu_opps) { + opp_table = mpu_opps; + + for (i = 1; opp_table[i].opp_id <= MAX_VDD1_OPP; i++) { + if (opp_table[i].rate == mpurate) { + valid = 1; + break; + } + } + + if (valid) { + opp = opp_table[i].opp_id; + pr_debug("Switching to OPP:%d\n", opp); + } else { + printk(KERN_ERR "*** Invalid MPU rate specified\n"); + return 1; + } + } + if (clk_set_rate(&dpll1_ck, mpurate)) printk(KERN_ERR "*** Unable to set MPU rate\n"); omap3_dpll_recalc(&dpll1_ck); + /* Get dsprate corresponding to the opp */ + if ((dsp_opps) && (opp >= VDD1_OPP1) && (opp <= VDD1_OPP5)) { + opp_table = dsp_opps; + + for (i=0; opp_table[i].opp_id <= MAX_VDD1_OPP; i++) + if (opp_table[i].opp_id == opp) + break; + + dsprate = opp_table[i].rate; + + if (clk_set_rate(&dpll2_ck, dsprate)) + printk(KERN_ERR "*** Unable to set IVA2 rate\n"); + omap3_dpll_recalc(&dpll2_ck); + } + recalculate_root_clocks(); printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " "%ld.%01ld/%ld/%ld MHz\n", (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; + printk(KERN_INFO "IVA2 clocking rate: %ld MHz\n", + (iva2_ck.rate / 1000000)) ; calibrate_delay(); @@ -1185,6 +1228,8 @@ int __init omap2_clk_init(void) "%ld.%01ld/%ld/%ld MHz\n", (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); + printk(KERN_INFO "IVA2 clocking rate: %ld MHz\n", + (iva2_ck.rate / 1000000)) ; /* * Only enable those clocks we will need, let the drivers From patchwork Wed May 5 14:27:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97104 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5P8002693 for ; Wed, 5 May 2010 14:28:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934764Ab0EEO2F (ORCPT ); Wed, 5 May 2010 10:28:05 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34104 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934681Ab0EEO2B (ORCPT ); Wed, 5 May 2010 10:28:01 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERs3N005616; Wed, 5 May 2010 09:27:59 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:56 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:56 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRB016232; Wed, 5 May 2010 17:27:55 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 09/21] OMAP: DSS2: Taal: Ensure panel is enabled in enable_te() and run_test() Date: Wed, 5 May 2010 17:27:29 +0300 Message-Id: <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:56.0726 (UTC) FILETIME=[27CCC560:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:12 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index a093eda..214d3cf 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -946,11 +946,8 @@ static int taal_sync(struct omap_dss_device *dssdev) static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) { - struct taal_data *td = dev_get_drvdata(&dssdev->dev); int r; - td->te_enabled = enable; - if (enable) r = taal_dcs_write_1(DCS_TEAR_ON, 0); else @@ -973,11 +970,22 @@ static int taal_enable_te(struct omap_dss_device *dssdev, bool enable) mutex_lock(&td->lock); dsi_bus_lock(); - r = _taal_enable_te(dssdev, enable); + if (td->enabled) { + r = _taal_enable_te(dssdev, enable); + if (r) + goto err; + } + + td->te_enabled = enable; dsi_bus_unlock(); mutex_unlock(&td->lock); + return 0; +err: + dsi_bus_unlock(); + mutex_unlock(&td->lock); + return r; } @@ -1077,23 +1085,30 @@ static int taal_run_test(struct omap_dss_device *dssdev, int test_num) int r; mutex_lock(&td->lock); + + if (!td->enabled) { + r = -ENODEV; + goto err1; + } + dsi_bus_lock(); r = taal_dcs_read_1(DCS_GET_ID1, &id1); if (r) - goto err; + goto err2; r = taal_dcs_read_1(DCS_GET_ID2, &id2); if (r) - goto err; + goto err2; r = taal_dcs_read_1(DCS_GET_ID3, &id3); if (r) - goto err; + goto err2; dsi_bus_unlock(); mutex_unlock(&td->lock); return 0; -err: +err2: dsi_bus_unlock(); +err1: mutex_unlock(&td->lock); return r; } From patchwork Wed Jul 21 17:33:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113397 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONE007938 for ; Wed, 21 Jul 2010 17:35:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757814Ab0GURe1 (ORCPT ); Wed, 21 Jul 2010 13:34:27 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756699Ab0GURe0 (ORCPT ); Wed, 21 Jul 2010 13:34:26 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:25 -0700 (PDT) Received: by 10.204.152.4 with SMTP id e4mr369893bkw.120.1279733663522; Wed, 21 Jul 2010 10:34:23 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:22 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 01/20] sdio: add TI + wl1271 ids Date: Wed, 21 Jul 2010 20:33:35 +0300 Message-Id: <1279733634-21974-2-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:08 +0000 (UTC) diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h index 33b2ea0..0d313c6 100644 --- a/include/linux/mmc/sdio_ids.h +++ b/include/linux/mmc/sdio_ids.h @@ -43,4 +43,7 @@ #define SDIO_DEVICE_ID_SIANO_NOVA_A0 0x1100 #define SDIO_DEVICE_ID_SIANO_STELLAR 0x5347 +#define SDIO_VENDOR_ID_TI 0x0097 +#define SDIO_DEVICE_ID_TI_WL1271 0x4076 + #endif From patchwork Sat May 8 04:31:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Weber X-Patchwork-Id: 97872 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o484Vr8Z020180 for ; Sat, 8 May 2010 04:31:54 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751138Ab0EHEbx (ORCPT ); Sat, 8 May 2010 00:31:53 -0400 Received: from mail-out.m-online.net ([212.18.0.9]:56948 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751078Ab0EHEbw (ORCPT ); Sat, 8 May 2010 00:31:52 -0400 Received: from mail01.m-online.net (mail.m-online.net [192.168.3.149]) by mail-out.m-online.net (Postfix) with ESMTP id D7B011C156B5; Sat, 8 May 2010 06:31:51 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.8.164]) by mail.m-online.net (Postfix) with ESMTP id D244D90273; Sat, 8 May 2010 06:31:51 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.3.149]) by localhost (dynscan1.mnet-online.de [192.168.8.164]) (amavisd-new, port 10024) with ESMTP id YvyQWc95Pq9K; Sat, 8 May 2010 06:31:50 +0200 (CEST) Received: from localhost.localdomain (ppp-93-104-151-100.dynamic.mnet-online.de [93.104.151.100]) by mail.mnet-online.de (Postfix) with ESMTP; Sat, 8 May 2010 06:31:50 +0200 (CEST) From: Thomas Weber To: linux-omap@vger.kernel.org Cc: Thomas Weber Subject: [PATCH 6/6] Devkit8000: Change twl4030 to tps65930 Date: Sat, 8 May 2010 06:31:23 +0200 Message-Id: <1273293083-24063-7-git-send-email-weber@corscience.de> X-Mailer: git-send-email 1.6.4.4 In-Reply-To: <1273293083-24063-1-git-send-email-weber@corscience.de> References: <1273293083-24063-1-git-send-email-weber@corscience.de> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 08 May 2010 04:31:54 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 4ca87f8..03332e8 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -369,7 +369,7 @@ static struct twl4030_platform_data devkit8000_twldata = { static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = { { - I2C_BOARD_INFO("twl4030", 0x48), + I2C_BOARD_INFO("tps65930", 0x48), .flags = I2C_CLIENT_WAKE, .irq = INT_34XX_SYS_NIRQ, .platform_data = &devkit8000_twldata, From patchwork Thu Jul 1 10:31:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 109043 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o61AVotn022390 for ; Thu, 1 Jul 2010 10:31:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755209Ab0GAKbt (ORCPT ); Thu, 1 Jul 2010 06:31:49 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50279 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755044Ab0GAKbs (ORCPT ); Thu, 1 Jul 2010 06:31:48 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o61AVix5000695 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 1 Jul 2010 05:31:44 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o61AVg87017488; Thu, 1 Jul 2010 05:31:42 -0500 (CDT) Received: from localhost (omaplbp.india.ti.com [172.24.190.217]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o61AVdP16950; Thu, 1 Jul 2010 05:31:39 -0500 (CDT) From: Archit Taneja To: linux-omap@vger.kernel.org Cc: tomi.valkeinen@nokia.com, Sumit Semwal , Senthilvadivu Guruswamy , Mukund Mittal , Archit Taneja , Samreen Subject: [RFC][PATCH 3/8] OMAP: DSS2: Modify dss_recheck_connections Date: Thu, 1 Jul 2010 16:01:20 +0530 Message-Id: <1277980285-20996-4-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1277980285-20996-3-git-send-email-archit@ti.com> References: <1277980285-20996-1-git-send-email-archit@ti.com> <1277980285-20996-2-git-send-email-archit@ti.com> <1277980285-20996-3-git-send-email-archit@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 10:31:50 +0000 (UTC) diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 8233658..c7ad1d1 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -627,12 +627,22 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) int i; struct omap_overlay_manager *lcd_mgr; struct omap_overlay_manager *tv_mgr; + struct omap_overlay_manager *lcd2_mgr = NULL; struct omap_overlay_manager *mgr = NULL; lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD); tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV); - - if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) { + if (cpu_is_omap44xx()) + lcd2_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD2); + + if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) { + if (!lcd2_mgr->device || force) { + if (lcd2_mgr->device) + lcd2_mgr->unset_device(lcd2_mgr); + lcd2_mgr->set_device(lcd2_mgr, dssdev); + mgr = lcd2_mgr; + } + } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) { if (!lcd_mgr->device || force) { if (lcd_mgr->device) lcd_mgr->unset_device(lcd_mgr); From patchwork Wed Jul 21 17:33:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113398 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONI007938 for ; Wed, 21 Jul 2010 17:35:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758215Ab0GURee (ORCPT ); Wed, 21 Jul 2010 13:34:34 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756699Ab0GURec (ORCPT ); Wed, 21 Jul 2010 13:34:32 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:30 -0700 (PDT) Received: by 10.204.115.132 with SMTP id i4mr366874bkq.129.1279733670640; Wed, 21 Jul 2010 10:34:30 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:29 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 03/20] mmc: support embedded data field in mmc_host Date: Wed, 21 Jul 2010 20:33:37 +0300 Message-Id: <1279733634-21974-4-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:09 +0000 (UTC) diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index f65913c..80db597 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -209,6 +209,8 @@ struct mmc_host { struct led_trigger *led; /* activity led */ #endif + void *embedded_data; + struct dentry *debugfs_root; unsigned long private[0] ____cacheline_aligned; @@ -264,5 +266,15 @@ static inline void mmc_set_disable_delay(struct mmc_host *host, host->disable_delay = disable_delay; } +static inline void *mmc_get_embedded_data(struct mmc_host *host) +{ + return host->embedded_data; +} + +static inline void mmc_set_embedded_data(struct mmc_host *host, void *data) +{ + host->embedded_data = data; +} + #endif From patchwork Sat May 8 04:31:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Weber X-Patchwork-Id: 97871 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o484VoZY020150 for ; Sat, 8 May 2010 04:31:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751113Ab0EHEbv (ORCPT ); Sat, 8 May 2010 00:31:51 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:56960 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751078Ab0EHEbu (ORCPT ); Sat, 8 May 2010 00:31:50 -0400 Received: from mail01.m-online.net (mail.m-online.net [192.168.3.149]) by mail-out.m-online.net (Postfix) with ESMTP id 0184D1C00209; Sat, 8 May 2010 06:31:50 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.8.164]) by mail.m-online.net (Postfix) with ESMTP id F26F8902B1; Sat, 8 May 2010 06:31:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.3.149]) by localhost (dynscan1.mnet-online.de [192.168.8.164]) (amavisd-new, port 10024) with ESMTP id gr69GtZXWu9t; Sat, 8 May 2010 06:31:49 +0200 (CEST) Received: from localhost.localdomain (ppp-93-104-151-100.dynamic.mnet-online.de [93.104.151.100]) by mail.mnet-online.de (Postfix) with ESMTP; Sat, 8 May 2010 06:31:49 +0200 (CEST) From: Thomas Weber To: linux-omap@vger.kernel.org Cc: Thomas Weber Subject: [PATCH 5/6] Devkit8000: Fix comment Date: Sat, 8 May 2010 06:31:22 +0200 Message-Id: <1273293083-24063-6-git-send-email-weber@corscience.de> X-Mailer: git-send-email 1.6.4.4 In-Reply-To: <1273293083-24063-1-git-send-email-weber@corscience.de> References: <1273293083-24063-1-git-send-email-weber@corscience.de> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 08 May 2010 04:31:52 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index c0905b0..4ca87f8 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -281,7 +281,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { static struct regulator_consumer_supply devkit8000_vpll1_supply = REGULATOR_SUPPLY("vdds_dsi", "omapdss"); -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ +/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT7 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data devkit8000_vmmc1 = { .constraints = { .min_uV = 1850000, From patchwork Wed May 19 16:38:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 100932 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4JGcUVq007203 for ; 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Wed, 19 May 2010 22:08:07 +0530 From: Santosh Shilimkar To: linux-omap@vger.kernel.org Cc: Santosh Shilimkar , Paul Walmsley Subject: [PATCH v2] omap4: Fix multi-omap boot with reset un-used clocks Date: Wed, 19 May 2010 22:08:07 +0530 Message-Id: <1274287087-4049-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 19 May 2010 16:38:30 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index a5c0c9c..a1b4cae 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1369,6 +1369,7 @@ static struct clk emif1_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .flags = ENABLE_ON_INIT, .clkdm_name = "l3_emif_clkdm", .parent = &ddrphy_ck, .recalc = &followparent_recalc, @@ -1379,6 +1380,7 @@ static struct clk emif2_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .flags = ENABLE_ON_INIT, .clkdm_name = "l3_emif_clkdm", .parent = &ddrphy_ck, .recalc = &followparent_recalc, From patchwork Sat Mar 13 01:52:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Olaya, Margarita" X-Patchwork-Id: 85668 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2D1qNq7001636 for ; Sat, 13 Mar 2010 01:52:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751973Ab0CMBwe (ORCPT ); Fri, 12 Mar 2010 20:52:34 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:43410 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751367Ab0CMBwc convert rfc822-to-8bit (ORCPT ); Fri, 12 Mar 2010 20:52:32 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2D1qL8M007595 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 12 Mar 2010 19:52:23 -0600 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o2D1qLh2012979; Fri, 12 Mar 2010 19:52:21 -0600 (CST) Received: from dsbe71.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2D1qLRH020861; Fri, 12 Mar 2010 19:52:21 -0600 (CST) Received: from dlee06.ent.ti.com ([157.170.170.11]) by dsbe71.ent.ti.com ([156.117.232.23]) with mapi; Fri, 12 Mar 2010 19:52:21 -0600 From: "Olaya, Margarita" To: "alsa-devel@alsa-project.org" , "linux-omap@vger.kernel.org" CC: "broonie@opensource.wolfsonmicro.com" , "lrg@slimlogic.co.uk" Date: Fri, 12 Mar 2010 19:52:20 -0600 Subject: [PATCHv5 2/2] ASoC: TWL6040: Add twl6040 codec driver Thread-Topic: [PATCHv5 2/2] ASoC: TWL6040: Add twl6040 codec driver Thread-Index: AcrCT9EbWE6vorhXS+CzZSeByeVR2g== Message-ID: <1889FA7136B567478A67D4B0F85B0CCE66173AF7@dlee06.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 13 Mar 2010 01:52:35 +0000 (UTC) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 16c47ed..398cbb0 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -35,6 +35,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_TPA6130A2 if I2C select SND_SOC_TLV320DAC33 if I2C select SND_SOC_TWL4030 if TWL4030_CORE + select SND_SOC_TWL6040 if TWL4030_CORE select SND_SOC_UDA134X select SND_SOC_UDA1380 if I2C select SND_SOC_WM2000 if I2C @@ -168,6 +169,9 @@ config SND_SOC_TWL4030 select TWL4030_CODEC tristate +config SND_SOC_TWL6040 + tristate + config SND_SOC_UDA134X tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 6981777..98bd10c 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -22,6 +22,7 @@ snd-soc-tlv320aic26-objs := tlv320aic26.o snd-soc-tlv320aic3x-objs := tlv320aic3x.o snd-soc-tlv320dac33-objs := tlv320dac33.o snd-soc-twl4030-objs := twl4030.o +snd-soc-twl6040-objs := twl6040.o snd-soc-uda134x-objs := uda134x.o snd-soc-uda1380-objs := uda1380.o snd-soc-wm8350-objs := wm8350.o @@ -85,6 +86,7 @@ obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c new file mode 100644 index 0000000..54835cc --- /dev/null +++ b/sound/soc/codecs/twl6040.c @@ -0,0 +1,1223 @@ +/* + * ALSA SoC TWL6040 codec driver + * + * Author: Misael Lopez Cruz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "twl6040.h" + +#define TWL6040_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) +#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) + +/* codec private data */ +struct twl6040_data { + struct snd_soc_codec codec; + int audpwron; + int naudint; + int codec_powered; + int pll; + int non_lp; + unsigned int sysclk; + struct snd_pcm_hw_constraint_list *sysclk_constraints; + struct completion ready; +}; + +/* + * twl6040 register cache & default register settings + */ +static const u8 twl6040_reg[TWL6040_CACHEREGNUM] = { + 0x00, /* not used 0x00 */ + 0x4B, /* TWL6040_ASICID (ro) 0x01 */ + 0x00, /* TWL6040_ASICREV (ro) 0x02 */ + 0x00, /* TWL6040_INTID 0x03 */ + 0x00, /* TWL6040_INTMR 0x04 */ + 0x00, /* TWL6040_NCPCTRL 0x05 */ + 0x00, /* TWL6040_LDOCTL 0x06 */ + 0x00, /* TWL6040_HPPLLCTL 0x07 */ + 0x00, /* TWL6040_LPPLLCTL 0x08 */ + 0x00, /* TWL6040_LPPLLDIV 0x09 */ + 0x00, /* TWL6040_AMICBCTL 0x0A */ + 0x00, /* TWL6040_DMICBCTL 0x0B */ + 0x18, /* TWL6040_MICLCTL 0x0C */ + 0x18, /* TWL6040_MICRCTL 0x0D */ + 0x00, /* TWL6040_MICGAIN 0x0E */ + 0x1B, /* TWL6040_LINEGAIN 0x0F */ + 0x00, /* TWL6040_HSLCTL 0x10 */ + 0x00, /* TWL6040_HSRCTL 0x11 */ + 0x00, /* TWL6040_HSGAIN 0x12 */ + 0x06, /* TWL6040_EARCTL 0x13 */ + 0x00, /* TWL6040_HFLCTL 0x14 */ + 0x03, /* TWL6040_HFLGAIN 0x15 */ + 0x00, /* TWL6040_HFRCTL 0x16 */ + 0x03, /* TWL6040_HFRGAIN 0x17 */ + 0x00, /* TWL6040_VIBCTLL 0x18 */ + 0x00, /* TWL6040_VIBDATL 0x19 */ + 0x00, /* TWL6040_VIBCTLR 0x1A */ + 0x00, /* TWL6040_VIBDATR 0x1B */ + 0x00, /* TWL6040_HKCTL1 0x1C */ + 0x00, /* TWL6040_HKCTL2 0x1D */ + 0x00, /* TWL6040_GPOCTL 0x1E */ + 0x00, /* TWL6040_ALB 0x1F */ + 0x00, /* TWL6040_DLB 0x20 */ + 0x00, /* not used 0x21 */ + 0x00, /* not used 0x22 */ + 0x00, /* not used 0x23 */ + 0x00, /* not used 0x24 */ + 0x00, /* not used 0x25 */ + 0x00, /* not used 0x26 */ + 0x00, /* not used 0x27 */ + 0x00, /* TWL6040_TRIM1 0x28 */ + 0x00, /* TWL6040_TRIM2 0x29 */ + 0x00, /* TWL6040_TRIM3 0x2A */ + 0x00, /* TWL6040_HSOTRIM 0x2B */ + 0x00, /* TWL6040_HFOTRIM 0x2C */ + 0x09, /* TWL6040_ACCCTL 0x2D */ + 0x00, /* TWL6040_STATUS (ro) 0x2E */ +}; + +/* + * twl6040 vio/gnd registers: + * registers under vio/gnd supply can be accessed + * before the power-up sequence, after NRESPWRON goes high + */ +static const int twl6040_vio_reg[TWL6040_VIOREGNUM] = { + TWL6040_REG_ASICID, + TWL6040_REG_ASICREV, + TWL6040_REG_INTID, + TWL6040_REG_INTMR, + TWL6040_REG_NCPCTL, + TWL6040_REG_LDOCTL, + TWL6040_REG_AMICBCTL, + TWL6040_REG_DMICBCTL, + TWL6040_REG_HKCTL1, + TWL6040_REG_HKCTL2, + TWL6040_REG_GPOCTL, + TWL6040_REG_TRIM1, + TWL6040_REG_TRIM2, + TWL6040_REG_TRIM3, + TWL6040_REG_HSOTRIM, + TWL6040_REG_HFOTRIM, + TWL6040_REG_ACCCTL, + TWL6040_REG_STATUS, +}; + +/* + * twl6040 vdd/vss registers: + * registers under vdd/vss supplies can only be accessed + * after the power-up sequence + */ +static const int twl6040_vdd_reg[TWL6040_VDDREGNUM] = { + TWL6040_REG_HPPLLCTL, + TWL6040_REG_LPPLLCTL, + TWL6040_REG_LPPLLDIV, + TWL6040_REG_MICLCTL, + TWL6040_REG_MICRCTL, + TWL6040_REG_MICGAIN, + TWL6040_REG_LINEGAIN, + TWL6040_REG_HSLCTL, + TWL6040_REG_HSRCTL, + TWL6040_REG_HSGAIN, + TWL6040_REG_EARCTL, + TWL6040_REG_HFLCTL, + TWL6040_REG_HFLGAIN, + TWL6040_REG_HFRCTL, + TWL6040_REG_HFRGAIN, + TWL6040_REG_VIBCTLL, + TWL6040_REG_VIBDATL, + TWL6040_REG_VIBCTLR, + TWL6040_REG_VIBDATR, + TWL6040_REG_ALB, + TWL6040_REG_DLB, +}; + +/* + * read twl6040 register cache + */ +static inline unsigned int twl6040_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 *cache = codec->reg_cache; + + if (reg >= TWL6040_CACHEREGNUM) + return -EIO; + + return cache[reg]; +} + +/* + * write twl6040 register cache + */ +static inline void twl6040_write_reg_cache(struct snd_soc_codec *codec, + u8 reg, u8 value) +{ + u8 *cache = codec->reg_cache; + + if (reg >= TWL6040_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * read from twl6040 hardware register + */ +static int twl6040_read_reg_volatile(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 value; + + if (reg >= TWL6040_CACHEREGNUM) + return -EIO; + + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg); + twl6040_write_reg_cache(codec, reg, value); + + return value; +} + +/* + * write to the twl6040 register space + */ +static int twl6040_write(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + if (reg >= TWL6040_CACHEREGNUM) + return -EIO; + + twl6040_write_reg_cache(codec, reg, value); + return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); +} + +static void twl6040_init_vio_regs(struct snd_soc_codec *codec) +{ + u8 *cache = codec->reg_cache; + int reg, i; + + /* allow registers to be accessed by i2c */ + twl6040_write(codec, TWL6040_REG_ACCCTL, cache[TWL6040_REG_ACCCTL]); + + for (i = 0; i < TWL6040_VIOREGNUM; i++) { + reg = twl6040_vio_reg[i]; + /* skip read-only registers (ASICID, ASICREV, STATUS) */ + switch (reg) { + case TWL6040_REG_ASICID: + case TWL6040_REG_ASICREV: + case TWL6040_REG_STATUS: + continue; + default: + break; + } + twl6040_write(codec, reg, cache[reg]); + } +} + +static void twl6040_init_vdd_regs(struct snd_soc_codec *codec) +{ + u8 *cache = codec->reg_cache; + int reg, i; + + for (i = 0; i < TWL6040_VDDREGNUM; i++) { + reg = twl6040_vdd_reg[i]; + twl6040_write(codec, reg, cache[reg]); + } +} + +/* twl6040 codec manual power-up sequence */ +static void twl6040_power_up(struct snd_soc_codec *codec) +{ + u8 ncpctl, ldoctl, lppllctl, accctl; + + ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL); + ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL); + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL); + + /* enable reference system */ + ldoctl |= TWL6040_REFENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + msleep(10); + /* enable internal oscillator */ + ldoctl |= TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(10); + /* enable high-side ldo */ + ldoctl |= TWL6040_HSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* enable negative charge pump */ + ncpctl |= TWL6040_NCPENA | TWL6040_NCPOPEN; + twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl); + udelay(488); + /* enable low-side ldo */ + ldoctl |= TWL6040_LSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* enable low-power pll */ + lppllctl |= TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + /* reset state machine */ + accctl |= TWL6040_RESETSPLIT; + twl6040_write(codec, TWL6040_REG_ACCCTL, accctl); + mdelay(5); + accctl &= ~TWL6040_RESETSPLIT; + twl6040_write(codec, TWL6040_REG_ACCCTL, accctl); + /* disable internal oscillator */ + ldoctl &= ~TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); +} + +/* twl6040 codec manual power-down sequence */ +static void twl6040_power_down(struct snd_soc_codec *codec) +{ + u8 ncpctl, ldoctl, lppllctl, accctl; + + ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL); + ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL); + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL); + + /* enable internal oscillator */ + ldoctl |= TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(10); + /* disable low-power pll */ + lppllctl &= ~TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + /* disable low-side ldo */ + ldoctl &= ~TWL6040_LSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* disable negative charge pump */ + ncpctl &= ~(TWL6040_NCPENA | TWL6040_NCPOPEN); + twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl); + udelay(488); + /* disable high-side ldo */ + ldoctl &= ~TWL6040_HSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* disable internal oscillator */ + ldoctl &= ~TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + /* disable reference system */ + ldoctl &= ~TWL6040_REFENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + msleep(10); +} + +/* set headset dac and driver power mode */ +static int headset_power_mode(struct snd_soc_codec *codec, int high_perf) +{ + int hslctl, hsrctl; + int mask = TWL6040_HSDRVMODEL | TWL6040_HSDACMODEL; + + hslctl = twl6040_read_reg_cache(codec, TWL6040_REG_HSLCTL); + hsrctl = twl6040_read_reg_cache(codec, TWL6040_REG_HSRCTL); + + if (high_perf) { + hslctl &= ~mask; + hsrctl &= ~mask; + } else { + hslctl |= mask; + hsrctl |= mask; + } + + twl6040_write(codec, TWL6040_REG_HSLCTL, hslctl); + twl6040_write(codec, TWL6040_REG_HSRCTL, hsrctl); + + return 0; +} + +static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct twl6040_data *priv = codec->private_data; + + if (SND_SOC_DAPM_EVENT_ON(event)) + priv->non_lp++; + else + priv->non_lp--; + + return 0; +} + +/* audio interrupt handler */ +static irqreturn_t twl6040_naudint_handler(int irq, void *data) +{ + struct snd_soc_codec *codec = data; + struct twl6040_data *priv = codec->private_data; + u8 intid; + + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); + + switch (intid) { + case TWL6040_THINT: + dev_alert(codec->dev, "die temp over-limit detection\n"); + break; + case TWL6040_PLUGINT: + case TWL6040_UNPLUGINT: + case TWL6040_HOOKINT: + break; + case TWL6040_HFINT: + dev_alert(codec->dev, "hf drivers over current detection\n"); + break; + case TWL6040_VIBINT: + dev_alert(codec->dev, "vib drivers over current detection\n"); + break; + case TWL6040_READYINT: + complete(&priv->ready); + break; + default: + dev_err(codec->dev, "unknown audio interrupt %d\n", intid); + break; + } + + return IRQ_HANDLED; +} + +/* + * MICATT volume control: + * from -6 to 0 dB in 6 dB steps + */ +static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0); + +/* + * MICGAIN volume control: + * from 6 to 30 dB in 6 dB steps + */ +static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0); + +/* + * HSGAIN volume control: + * from -30 to 0 dB in 2 dB steps + */ +static DECLARE_TLV_DB_SCALE(hs_tlv, -3000, 200, 0); + +/* + * HFGAIN volume control: + * from -52 to 6 dB in 2 dB steps + */ +static DECLARE_TLV_DB_SCALE(hf_tlv, -5200, 200, 0); + +/* Left analog microphone selection */ +static const char *twl6040_amicl_texts[] = + {"Headset Mic", "Main Mic", "Aux/FM Left", "Off"}; + +/* Right analog microphone selection */ +static const char *twl6040_amicr_texts[] = + {"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"}; + +static const struct soc_enum twl6040_enum[] = { + SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 3, twl6040_amicl_texts), + SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 3, twl6040_amicr_texts), +}; + +static const struct snd_kcontrol_new amicl_control = + SOC_DAPM_ENUM("Route", twl6040_enum[0]); + +static const struct snd_kcontrol_new amicr_control = + SOC_DAPM_ENUM("Route", twl6040_enum[1]); + +/* Headset DAC playback switches */ +static const struct snd_kcontrol_new hsdacl_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSLCTL, 5, 1, 0); + +static const struct snd_kcontrol_new hsdacr_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSRCTL, 5, 1, 0); + +/* Handsfree DAC playback switches */ +static const struct snd_kcontrol_new hfdacl_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 2, 1, 0); + +static const struct snd_kcontrol_new hfdacr_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 2, 1, 0); + +/* Headset driver switches */ +static const struct snd_kcontrol_new hsl_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSLCTL, 2, 1, 0); + +static const struct snd_kcontrol_new hsr_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSRCTL, 2, 1, 0); + +/* Handsfree driver switches */ +static const struct snd_kcontrol_new hfl_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 4, 1, 0); + +static const struct snd_kcontrol_new hfr_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 4, 1, 0); + +static const struct snd_kcontrol_new twl6040_snd_controls[] = { + /* Capture gains */ + SOC_DOUBLE_TLV("Capture Preamplifier Volume", + TWL6040_REG_MICGAIN, 6, 7, 1, 1, mic_preamp_tlv), + SOC_DOUBLE_TLV("Capture Volume", + TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv), + + /* Playback gains */ + SOC_DOUBLE_TLV("Headset Playback Volume", + TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv), + SOC_DOUBLE_R_TLV("Handsfree Playback Volume", + TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv), + +}; + +static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = { + /* Inputs */ + SND_SOC_DAPM_INPUT("MAINMIC"), + SND_SOC_DAPM_INPUT("HSMIC"), + SND_SOC_DAPM_INPUT("SUBMIC"), + SND_SOC_DAPM_INPUT("AFML"), + SND_SOC_DAPM_INPUT("AFMR"), + + /* Outputs */ + SND_SOC_DAPM_OUTPUT("HSOL"), + SND_SOC_DAPM_OUTPUT("HSOR"), + SND_SOC_DAPM_OUTPUT("HFL"), + SND_SOC_DAPM_OUTPUT("HFR"), + + /* Analog input muxes for the capture amplifiers */ + SND_SOC_DAPM_MUX("Analog Left Capture Route", + SND_SOC_NOPM, 0, 0, &amicl_control), + SND_SOC_DAPM_MUX("Analog Right Capture Route", + SND_SOC_NOPM, 0, 0, &amicr_control), + + /* Analog capture PGAs */ + SND_SOC_DAPM_PGA("MicAmpL", + TWL6040_REG_MICLCTL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("MicAmpR", + TWL6040_REG_MICRCTL, 0, 0, NULL, 0), + + /* ADCs */ + SND_SOC_DAPM_ADC("ADC Left", "Left Front Capture", + TWL6040_REG_MICLCTL, 2, 0), + SND_SOC_DAPM_ADC("ADC Right", "Right Front Capture", + TWL6040_REG_MICRCTL, 2, 0), + + /* Microphone bias */ + SND_SOC_DAPM_MICBIAS("Headset Mic Bias", + TWL6040_REG_AMICBCTL, 0, 0), + SND_SOC_DAPM_MICBIAS("Main Mic Bias", + TWL6040_REG_AMICBCTL, 4, 0), + SND_SOC_DAPM_MICBIAS("Digital Mic1 Bias", + TWL6040_REG_DMICBCTL, 0, 0), + SND_SOC_DAPM_MICBIAS("Digital Mic2 Bias", + TWL6040_REG_DMICBCTL, 4, 0), + + /* DACs */ + SND_SOC_DAPM_DAC("HSDAC Left", "Headset Playback", + TWL6040_REG_HSLCTL, 0, 0), + SND_SOC_DAPM_DAC("HSDAC Right", "Headset Playback", + TWL6040_REG_HSRCTL, 0, 0), + SND_SOC_DAPM_DAC_E("HFDAC Left", "Handsfree Playback", + TWL6040_REG_HFLCTL, 0, 0, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_DAC_E("HFDAC Right", "Handsfree Playback", + TWL6040_REG_HFRCTL, 0, 0, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + /* Analog playback switches */ + SND_SOC_DAPM_SWITCH("HSDAC Left Playback", + SND_SOC_NOPM, 0, 0, &hsdacl_switch_controls), + SND_SOC_DAPM_SWITCH("HSDAC Right Playback", + SND_SOC_NOPM, 0, 0, &hsdacr_switch_controls), + SND_SOC_DAPM_SWITCH("HFDAC Left Playback", + SND_SOC_NOPM, 0, 0, &hfdacl_switch_controls), + SND_SOC_DAPM_SWITCH("HFDAC Right Playback", + SND_SOC_NOPM, 0, 0, &hfdacr_switch_controls), + + SND_SOC_DAPM_SWITCH("Headset Left Driver", + SND_SOC_NOPM, 0, 0, &hsl_driver_switch_controls), + SND_SOC_DAPM_SWITCH("Headset Right Driver", + SND_SOC_NOPM, 0, 0, &hsr_driver_switch_controls), + SND_SOC_DAPM_SWITCH_E("Handsfree Left Driver", + SND_SOC_NOPM, 0, 0, &hfl_driver_switch_controls, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SWITCH_E("Handsfree Right Driver", + SND_SOC_NOPM, 0, 0, &hfr_driver_switch_controls, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + /* Analog playback PGAs */ + SND_SOC_DAPM_PGA("HFDAC Left PGA", + TWL6040_REG_HFLCTL, 1, 0, NULL, 0), + SND_SOC_DAPM_PGA("HFDAC Right PGA", + TWL6040_REG_HFRCTL, 1, 0, NULL, 0), + +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* Capture path */ + {"Analog Left Capture Route", "Headset Mic", "HSMIC"}, + {"Analog Left Capture Route", "Main Mic", "MAINMIC"}, + {"Analog Left Capture Route", "Aux/FM Left", "AFML"}, + + {"Analog Right Capture Route", "Headset Mic", "HSMIC"}, + {"Analog Right Capture Route", "Sub Mic", "SUBMIC"}, + {"Analog Right Capture Route", "Aux/FM Right", "AFMR"}, + + {"MicAmpL", NULL, "Analog Left Capture Route"}, + {"MicAmpR", NULL, "Analog Right Capture Route"}, + + {"ADC Left", NULL, "MicAmpL"}, + {"ADC Right", NULL, "MicAmpR"}, + + /* Headset playback path */ + {"HSDAC Left Playback", "Switch", "HSDAC Left"}, + {"HSDAC Right Playback", "Switch", "HSDAC Right"}, + + {"Headset Left Driver", "Switch", "HSDAC Left Playback"}, + {"Headset Right Driver", "Switch", "HSDAC Right Playback"}, + + {"HSOL", NULL, "Headset Left Driver"}, + {"HSOR", NULL, "Headset Right Driver"}, + + /* Handsfree playback path */ + {"HFDAC Left Playback", "Switch", "HFDAC Left"}, + {"HFDAC Right Playback", "Switch", "HFDAC Right"}, + + {"HFDAC Left PGA", NULL, "HFDAC Left Playback"}, + {"HFDAC Right PGA", NULL, "HFDAC Right Playback"}, + + {"Handsfree Left Driver", "Switch", "HFDAC Left PGA"}, + {"Handsfree Right Driver", "Switch", "HFDAC Right PGA"}, + + {"HFL", NULL, "Handsfree Left Driver"}, + {"HFR", NULL, "Handsfree Right Driver"}, +}; + +static int twl6040_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, twl6040_dapm_widgets, + ARRAY_SIZE(twl6040_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(codec); + + return 0; +} + +static int twl6040_power_up_completion(struct snd_soc_codec *codec, + int naudint) +{ + struct twl6040_data *priv = codec->private_data; + int time_left; + u8 intid; + + time_left = wait_for_completion_timeout(&priv->ready, + msecs_to_jiffies(48)); + + if (!time_left) { + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, + TWL6040_REG_INTID); + if (!(intid & TWL6040_READYINT)) { + dev_err(codec->dev, "timeout waiting for READYINT\n"); + return -ETIMEDOUT; + } + } + + priv->codec_powered = 1; + + return 0; +} + +static int twl6040_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct twl6040_data *priv = codec->private_data; + int audpwron = priv->audpwron; + int naudint = priv->naudint; + int ret; + + switch (level) { + case SND_SOC_BIAS_ON: + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + if (priv->codec_powered) + break; + + if (gpio_is_valid(audpwron)) { + /* use AUDPWRON line */ + gpio_set_value(audpwron, 1); + + /* wait for power-up completion */ + ret = twl6040_power_up_completion(codec, naudint); + if (ret) + return ret; + + /* sync registers updated during power-up sequence */ + twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL); + twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL); + twl6040_read_reg_volatile(codec, TWL6040_REG_LPPLLCTL); + } else { + /* use manual power-up sequence */ + twl6040_power_up(codec); + priv->codec_powered = 1; + } + + /* initialize vdd/vss registers with reg_cache */ + twl6040_init_vdd_regs(codec); + break; + case SND_SOC_BIAS_OFF: + if (!priv->codec_powered) + break; + + if (gpio_is_valid(audpwron)) { + /* use AUDPWRON line */ + gpio_set_value(audpwron, 0); + + /* power-down sequence latency */ + udelay(500); + + /* sync registers updated during power-down sequence */ + twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL); + twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL); + twl6040_write_reg_cache(codec, TWL6040_REG_LPPLLCTL, + 0x00); + } else { + /* use manual power-down sequence */ + twl6040_power_down(codec); + } + + priv->codec_powered = 0; + break; + } + + codec->bias_level = level; + + return 0; +} + +/* set of rates for each pll: low-power and high-performance */ + +static unsigned int lp_rates[] = { + 88200, + 96000, +}; + +static struct snd_pcm_hw_constraint_list lp_constraints = { + .count = ARRAY_SIZE(lp_rates), + .list = lp_rates, +}; + +static unsigned int hp_rates[] = { + 96000, +}; + +static struct snd_pcm_hw_constraint_list hp_constraints = { + .count = ARRAY_SIZE(hp_rates), + .list = hp_rates, +}; + +static int twl6040_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct twl6040_data *priv = codec->private_data; + + if (!priv->sysclk) { + dev_err(codec->dev, + "no mclk configured, call set_sysclk() on init\n"); + return -EINVAL; + } + + /* + * capture is not supported at 17.64 MHz, + * it's reserved for headset low-power playback scenario + */ + if ((priv->sysclk == 17640000) && substream->stream) { + dev_err(codec->dev, + "capture mode is not supported at %dHz\n", + priv->sysclk); + return -EINVAL; + } + + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + priv->sysclk_constraints); + + return 0; +} + +static int twl6040_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct twl6040_data *priv = codec->private_data; + u8 lppllctl; + int rate; + + /* nothing to do for high-perf pll, it supports only 48 kHz */ + if (priv->pll == TWL6040_HPPLL_ID) + return 0; + + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + + rate = params_rate(params); + switch (rate) { + case 88200: + lppllctl |= TWL6040_LPLLFIN; + priv->sysclk = 17640000; + break; + case 96000: + lppllctl &= ~TWL6040_LPLLFIN; + priv->sysclk = 19200000; + break; + default: + dev_err(codec->dev, "unsupported rate %d\n", rate); + return -EINVAL; + } + + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + + return 0; +} + +static int twl6040_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct twl6040_data *priv = codec->private_data; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + /* + * low-power playback mode is restricted + * for headset path only + */ + if ((priv->sysclk == 17640000) && priv->non_lp) { + dev_err(codec->dev, + "some enabled paths aren't supported at %dHz\n", + priv->sysclk); + return -EPERM; + } + break; + default: + break; + } + + return 0; +} + +static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct twl6040_data *priv = codec->private_data; + u8 hppllctl, lppllctl; + + hppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_HPPLLCTL); + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + + switch (clk_id) { + case TWL6040_SYSCLK_SEL_LPPLL: + switch (freq) { + case 32768: + /* headset dac and driver must be in low-power mode */ + headset_power_mode(codec, 0); + + /* clk32k input requires low-power pll */ + lppllctl |= TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + mdelay(5); + lppllctl &= ~TWL6040_HPLLSEL; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + hppllctl &= ~TWL6040_HPLLENA; + twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl); + break; + default: + dev_err(codec->dev, "unknown mclk freq %d\n", freq); + return -EINVAL; + } + + /* lppll divider */ + switch (priv->sysclk) { + case 17640000: + lppllctl |= TWL6040_LPLLFIN; + break; + case 19200000: + lppllctl &= ~TWL6040_LPLLFIN; + break; + default: + /* sysclk not yet configured */ + lppllctl &= ~TWL6040_LPLLFIN; + priv->sysclk = 19200000; + break; + } + + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + + priv->pll = TWL6040_LPPLL_ID; + priv->sysclk_constraints = &lp_constraints; + break; + case TWL6040_SYSCLK_SEL_HPPLL: + hppllctl &= ~TWL6040_MCLK_MSK; + + switch (freq) { + case 12000000: + /* mclk input, pll enabled */ + hppllctl |= TWL6040_MCLK_12000KHZ | + TWL6040_HPLLSQRBP | + TWL6040_HPLLENA; + break; + case 19200000: + /* mclk input, pll disabled */ + hppllctl |= TWL6040_MCLK_19200KHZ | + TWL6040_HPLLSQRBP | + TWL6040_HPLLBP; + break; + case 26000000: + /* mclk input, pll enabled */ + hppllctl |= TWL6040_MCLK_26000KHZ | + TWL6040_HPLLSQRBP | + TWL6040_HPLLENA; + break; + case 38400000: + /* clk slicer, pll disabled */ + hppllctl |= TWL6040_MCLK_38400KHZ | + TWL6040_HPLLSQRENA | + TWL6040_HPLLBP; + break; + default: + dev_err(codec->dev, "unknown mclk freq %d\n", freq); + return -EINVAL; + } + + /* headset dac and driver must be in high-performance mode */ + headset_power_mode(codec, 1); + + twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl); + udelay(500); + lppllctl |= TWL6040_HPLLSEL; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + lppllctl &= ~TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + + /* high-performance pll can provide only 19.2 MHz */ + priv->pll = TWL6040_HPPLL_ID; + priv->sysclk = 19200000; + priv->sysclk_constraints = &hp_constraints; + break; + default: + dev_err(codec->dev, "unknown clk_id %d\n", clk_id); + return -EINVAL; + } + + return 0; +} + +static struct snd_soc_dai_ops twl6040_dai_ops = { + .startup = twl6040_startup, + .hw_params = twl6040_hw_params, + .trigger = twl6040_trigger, + .set_sysclk = twl6040_set_dai_sysclk, +}; + +struct snd_soc_dai twl6040_dai = { + .name = "twl6040", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 4, + .rates = TWL6040_RATES, + .formats = TWL6040_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = TWL6040_RATES, + .formats = TWL6040_FORMATS, + }, + .ops = &twl6040_dai_ops, +}; +EXPORT_SYMBOL_GPL(twl6040_dai); + +static int twl6040_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int twl6040_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + twl6040_set_bias_level(codec, codec->suspend_bias_level); + + return 0; +} + +static struct snd_soc_codec *twl6040_codec; + +static int twl6040_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + int ret = 0; + + BUG_ON(!twl6040_codec); + + codec = twl6040_codec; + socdev->card->codec = codec; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(&pdev->dev, "failed to create pcms\n"); + return ret; + } + + snd_soc_add_controls(codec, twl6040_snd_controls, + ARRAY_SIZE(twl6040_snd_controls)); + twl6040_add_widgets(codec); + + if (ret < 0) { + dev_err(&pdev->dev, "failed to register card\n"); + goto card_err; + } + + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + return ret; +} + +static int twl6040_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_twl6040 = { + .probe = twl6040_probe, + .remove = twl6040_remove, + .suspend = twl6040_suspend, + .resume = twl6040_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_twl6040); + +static int __devinit twl6040_codec_probe(struct platform_device *pdev) +{ + struct twl4030_codec_data *twl_codec = pdev->dev.platform_data; + struct snd_soc_codec *codec; + struct twl6040_data *priv; + int audpwron, naudint; + int ret = 0; + + priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + if (twl_codec) { + audpwron = twl_codec->audpwron_gpio; + naudint = twl_codec->naudint_irq; + } else { + audpwron = -EINVAL; + naudint = 0; + } + + priv->audpwron = audpwron; + priv->naudint = naudint; + + codec = &priv->codec; + codec->dev = &pdev->dev; + twl6040_dai.dev = &pdev->dev; + + codec->name = "twl6040"; + codec->owner = THIS_MODULE; + codec->read = twl6040_read_reg_cache; + codec->write = twl6040_write; + codec->set_bias_level = twl6040_set_bias_level; + codec->private_data = priv; + codec->dai = &twl6040_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(twl6040_reg); + codec->reg_cache = kmemdup(twl6040_reg, sizeof(twl6040_reg), + GFP_KERNEL); + if (codec->reg_cache == NULL) { + ret = -ENOMEM; + goto cache_err; + } + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + init_completion(&priv->ready); + + if (gpio_is_valid(audpwron)) { + ret = gpio_request(audpwron, "audpwron"); + if (ret) + goto gpio1_err; + + ret = gpio_direction_output(audpwron, 0); + if (ret) + goto gpio2_err; + + priv->codec_powered = 0; + } + + if (naudint) { + /* audio interrupt */ + ret = request_threaded_irq(naudint, NULL, + twl6040_naudint_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "twl6040_codec", codec); + if (ret) + goto gpio2_err; + } else { + if (gpio_is_valid(audpwron)) { + /* enable only codec ready interrupt */ + twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, + ~TWL6040_READYMSK & TWL6040_ALLINT_MSK); + } else { + /* no interrupts at all */ + twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, + TWL6040_ALLINT_MSK); + } + } + + /* init vio registers */ + twl6040_init_vio_regs(codec); + + /* power on device */ + ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + if (ret) + goto irq_err; + + ret = snd_soc_register_codec(codec); + if (ret) + goto reg_err; + + twl6040_codec = codec; + + ret = snd_soc_register_dai(&twl6040_dai); + if (ret) + goto dai_err; + + return 0; + +dai_err: + snd_soc_unregister_codec(codec); + twl6040_codec = NULL; +reg_err: + twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); +irq_err: + if (naudint) + free_irq(naudint, codec); +gpio2_err: + if (gpio_is_valid(audpwron)) + gpio_free(audpwron); +gpio1_err: + kfree(codec->reg_cache); +cache_err: + kfree(priv); + return ret; +} + +static int __devexit twl6040_codec_remove(struct platform_device *pdev) +{ + struct twl6040_data *priv = twl6040_codec->private_data; + int audpwron = priv->audpwron; + int naudint = priv->naudint; + + if (gpio_is_valid(audpwron)) + gpio_free(audpwron); + + if (naudint) + free_irq(naudint, twl6040_codec); + + snd_soc_unregister_dai(&twl6040_dai); + snd_soc_unregister_codec(twl6040_codec); + + kfree(twl6040_codec); + twl6040_codec = NULL; + + return 0; +} + +static struct platform_driver twl6040_codec_driver = { + .driver = { + .name = "twl6040_codec", + .owner = THIS_MODULE, + }, + .probe = twl6040_codec_probe, + .remove = __devexit_p(twl6040_codec_remove), +}; + +static int __init twl6040_codec_init(void) +{ + return platform_driver_register(&twl6040_codec_driver); +} +module_init(twl6040_codec_init); + +static void __exit twl6040_codec_exit(void) +{ + platform_driver_unregister(&twl6040_codec_driver); +} +module_exit(twl6040_codec_exit); + +MODULE_DESCRIPTION("ASoC TWL6040 codec driver"); +MODULE_AUTHOR("Misael Lopez Cruz"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h new file mode 100644 index 0000000..c472070 --- /dev/null +++ b/sound/soc/codecs/twl6040.h @@ -0,0 +1,141 @@ +/* + * ALSA SoC TWL6040 codec driver + * + * Author: Misael Lopez Cruz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __TWL6040_H__ +#define __TWL6040_H__ + +#define TWL6040_REG_ASICID 0x01 +#define TWL6040_REG_ASICREV 0x02 +#define TWL6040_REG_INTID 0x03 +#define TWL6040_REG_INTMR 0x04 +#define TWL6040_REG_NCPCTL 0x05 +#define TWL6040_REG_LDOCTL 0x06 +#define TWL6040_REG_HPPLLCTL 0x07 +#define TWL6040_REG_LPPLLCTL 0x08 +#define TWL6040_REG_LPPLLDIV 0x09 +#define TWL6040_REG_AMICBCTL 0x0A +#define TWL6040_REG_DMICBCTL 0x0B +#define TWL6040_REG_MICLCTL 0x0C +#define TWL6040_REG_MICRCTL 0x0D +#define TWL6040_REG_MICGAIN 0x0E +#define TWL6040_REG_LINEGAIN 0x0F +#define TWL6040_REG_HSLCTL 0x10 +#define TWL6040_REG_HSRCTL 0x11 +#define TWL6040_REG_HSGAIN 0x12 +#define TWL6040_REG_EARCTL 0x13 +#define TWL6040_REG_HFLCTL 0x14 +#define TWL6040_REG_HFLGAIN 0x15 +#define TWL6040_REG_HFRCTL 0x16 +#define TWL6040_REG_HFRGAIN 0x17 +#define TWL6040_REG_VIBCTLL 0x18 +#define TWL6040_REG_VIBDATL 0x19 +#define TWL6040_REG_VIBCTLR 0x1A +#define TWL6040_REG_VIBDATR 0x1B +#define TWL6040_REG_HKCTL1 0x1C +#define TWL6040_REG_HKCTL2 0x1D +#define TWL6040_REG_GPOCTL 0x1E +#define TWL6040_REG_ALB 0x1F +#define TWL6040_REG_DLB 0x20 +#define TWL6040_REG_TRIM1 0x28 +#define TWL6040_REG_TRIM2 0x29 +#define TWL6040_REG_TRIM3 0x2A +#define TWL6040_REG_HSOTRIM 0x2B +#define TWL6040_REG_HFOTRIM 0x2C +#define TWL6040_REG_ACCCTL 0x2D +#define TWL6040_REG_STATUS 0x2E + +#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1) + +#define TWL6040_VIOREGNUM 18 +#define TWL6040_VDDREGNUM 21 + +/* INTID (0x03) fields */ + +#define TWL6040_THINT 0x01 +#define TWL6040_PLUGINT 0x02 +#define TWL6040_UNPLUGINT 0x04 +#define TWL6040_HOOKINT 0x08 +#define TWL6040_HFINT 0x10 +#define TWL6040_VIBINT 0x20 +#define TWL6040_READYINT 0x40 + +/* INTMR (0x04) fields */ + +#define TWL6040_READYMSK 0x40 +#define TWL6040_ALLINT_MSK 0x7B + +/* NCPCTL (0x05) fields */ + +#define TWL6040_NCPENA 0x01 +#define TWL6040_NCPOPEN 0x40 + +/* LDOCTL (0x06) fields */ + +#define TWL6040_LSLDOENA 0x01 +#define TWL6040_HSLDOENA 0x04 +#define TWL6040_REFENA 0x40 +#define TWL6040_OSCENA 0x80 + +/* HPPLLCTL (0x07) fields */ + +#define TWL6040_HPLLENA 0x01 +#define TWL6040_HPLLRST 0x02 +#define TWL6040_HPLLBP 0x04 +#define TWL6040_HPLLSQRENA 0x08 +#define TWL6040_HPLLSQRBP 0x10 +#define TWL6040_MCLK_12000KHZ (0 << 5) +#define TWL6040_MCLK_19200KHZ (1 << 5) +#define TWL6040_MCLK_26000KHZ (2 << 5) +#define TWL6040_MCLK_38400KHZ (3 << 5) +#define TWL6040_MCLK_MSK 0x60 + +/* LPPLLCTL (0x08) fields */ + +#define TWL6040_LPLLENA 0x01 +#define TWL6040_LPLLRST 0x02 +#define TWL6040_LPLLSEL 0x04 +#define TWL6040_LPLLFIN 0x08 +#define TWL6040_HPLLSEL 0x10 + +/* HSLCTL (0x10) fields */ + +#define TWL6040_HSDACMODEL 0x02 +#define TWL6040_HSDRVMODEL 0x08 + +/* HSRCTL (0x11) fields */ + +#define TWL6040_HSDACMODER 0x02 +#define TWL6040_HSDRVMODER 0x08 + +/* ACCCTL (0x2D) fields */ + +#define TWL6040_RESETSPLIT 0x04 + +#define TWL6040_SYSCLK_SEL_LPPLL 1 +#define TWL6040_SYSCLK_SEL_HPPLL 2 + +#define TWL6040_HPPLL_ID 1 +#define TWL6040_LPPLL_ID 2 + +extern struct snd_soc_dai twl6040_dai; +extern struct snd_soc_codec_device soc_codec_dev_twl6040; + +#endif /* End of __TWL6040_H__ */ From patchwork Fri Jul 2 06:27:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 109810 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o626SWCa006862 for ; Fri, 2 Jul 2010 06:28:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757323Ab0GBG1y (ORCPT ); Fri, 2 Jul 2010 02:27:54 -0400 Received: from smtp.nokia.com ([192.100.122.230]:62292 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757246Ab0GBG1v (ORCPT ); Fri, 2 Jul 2010 02:27:51 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o626RRWa030630; Fri, 2 Jul 2010 09:27:42 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 2 Jul 2010 09:27:38 +0300 Received: from mgw-da02.ext.nokia.com ([147.243.128.26]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 2 Jul 2010 09:27:37 +0300 Received: from localhost (esdhcp04075.research.nokia.com [172.21.40.75]) by mgw-da02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o626RVeu019482; Fri, 2 Jul 2010 09:27:32 +0300 Date: Fri, 02 Jul 2010 09:27:31 +0300 (EEST) Message-Id: <20100702.092731.39168665.Hiroshi.DOYU@nokia.com> To: x0095840@ti.com Cc: linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com Subject: Re: [PATCH 5/9] dspbridge: add mmufault support From: Hiroshi DOYU In-Reply-To: <1277943660-4112-6-git-send-email-x0095840@ti.com> References: <1277943660-4112-4-git-send-email-x0095840@ti.com> <1277943660-4112-5-git-send-email-x0095840@ti.com> <1277943660-4112-6-git-send-email-x0095840@ti.com> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 X-OriginalArrivalTime: 02 Jul 2010 06:27:38.0001 (UTC) FILETIME=[AA75D010:01CB19AF] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 02 Jul 2010 06:28:32 +0000 (UTC) diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index a202a2c..17407f1 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -800,7 +800,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) if (!stat) return IRQ_HANDLED; - iommu_disable(obj); + iommu_disable(obj); <- HERE! iopgd = iopgd_offset(obj, da); You can find the latest omap iommu code from: git://gitorious.org/~doyu/lk/mainline.git v2.6.35-rc3-iommu-for-next Also I just thought that, passing 'da' to user callback might be cleaner as below. Then you can avoid the direct access to IOMMU registers. Basically we should avoid the direct access to IOMMU registers from client. If you have to, then it would be better to modify omap iommu code itself. Modified arch/arm/plat-omap/iommu.c diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index a202a2c..64d918e 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -787,13 +787,6 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) if (!obj->refcount) return IRQ_NONE; - /* Dynamic loading TLB or PTE */ - if (obj->isr) - err = obj->isr(obj); - - if (!err) - return IRQ_HANDLED; - clk_enable(obj->clk); stat = iommu_report_fault(obj, &da); clk_disable(obj->clk); @@ -802,6 +795,13 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) iommu_disable(obj); + /* user registered callback */ + if (obj->isr) + err = obj->isr(obj, da); + + if (!err) + return IRQ_HANDLED; + iopgd = iopgd_offset(obj, da); > From patchwork Wed Jul 28 14:54:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114807 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SEpOuc013587 for ; Wed, 28 Jul 2010 14:51:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755265Ab0G1Ouu (ORCPT ); Wed, 28 Jul 2010 10:50:50 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:42925 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755331Ab0G1Oua (ORCPT ); Wed, 28 Jul 2010 10:50:30 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SEoMlc005737 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 09:50:23 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6SEoLeW018726; Wed, 28 Jul 2010 09:50:21 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SEo4N7024733; Wed, 28 Jul 2010 09:50:05 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH 1/4] staging:ti dspbridge: fix bridge_brd_stop so IVA2 is set OFF Date: Wed, 28 Jul 2010 09:54:52 -0500 Message-Id: <1280328895-31375-2-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 In-Reply-To: <1280328895-31375-1-git-send-email-ernesto@ti.com> References: <1280328895-31375-1-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 14:51:25 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 9673acb..77527bd 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -639,11 +639,11 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) & OMAP_POWERSTATEST_MASK; if (dsp_pwr_state != PWRDM_POWER_OFF) { + (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0, + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE); mdelay(10); - clk_status = dsp_clk_disable(DSP_CLK_IVA2); - /* IVA2 is not in OFF state */ /* Set PM_PWSTCTRL_IVA2 to OFF */ (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK, @@ -651,8 +651,6 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) /* Set the SW supervised state transition for Sleep */ (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); - } else { - clk_status = dsp_clk_disable(DSP_CLK_IVA2); } udelay(10); /* Release the Ext Base virtual Address as the next DSP Program @@ -682,6 +680,8 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + clk_status = dsp_clk_disable(DSP_CLK_IVA2); + return status; } From patchwork Sun May 16 15:47:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99981 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFlHkV025489 for ; Sun, 16 May 2010 15:47:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754041Ab0EPPrQ (ORCPT ); Sun, 16 May 2010 11:47:16 -0400 Received: from mail-fx0-f46.google.com ([209.85.161.46]:53342 "EHLO mail-fx0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753895Ab0EPPrP (ORCPT ); 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Sun, 16 May 2010 08:47:14 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 4/5] dspbridge: use CONFIG_OMAP_DSP_DEBUG for debug trace Date: Sun, 16 May 2010 18:47:00 +0300 Message-Id: <1274024821-21178-5-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024821-21178-1-git-send-email-felipe.contreras@gmail.com> References: <1274024821-21178-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:47:17 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/io_sm.h b/arch/arm/plat-omap/include/dspbridge/io_sm.h index 732aa4f..bc74dbf 100644 --- a/arch/arm/plat-omap/include/dspbridge/io_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/io_sm.h @@ -302,7 +302,7 @@ dsp_status dump_dsp_stack(struct bridge_dev_context *bridge_context); void dump_dl_modules(struct bridge_dev_context *bridge_context); -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG void print_dsp_debug_trace(struct io_mgr *hio_mgr); #endif diff --git a/drivers/dsp/bridge/core/io_sm.c b/drivers/dsp/bridge/core/io_sm.c index 161b598..268d4e6 100644 --- a/drivers/dsp/bridge/core/io_sm.c +++ b/drivers/dsp/bridge/core/io_sm.c @@ -113,7 +113,7 @@ struct io_mgr { struct mgr_processorextinfo ext_proc_info; struct cmm_object *hcmm_mgr; /* Shared Mem Mngr */ struct work_struct io_workq; /* workqueue */ -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG u32 ul_trace_buffer_begin; /* Trace message start address */ u32 ul_trace_buffer_end; /* Trace message end address */ u32 ul_trace_buffer_current; /* Trace message current address */ @@ -209,7 +209,7 @@ dsp_status bridge_io_create(OUT struct io_mgr **phIOMgr, } /* Initialize chnl_mgr object */ -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG pio_mgr->pmsg = NULL; #endif pio_mgr->hchnl_mgr = hchnl_mgr; @@ -264,7 +264,7 @@ dsp_status bridge_io_destroy(struct io_mgr *hio_mgr) /* Free IO DPC object */ tasklet_kill(&hio_mgr->dpc_tasklet); -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG kfree(hio_mgr->pmsg); #endif dsp_wdt_exit(); @@ -404,7 +404,7 @@ dsp_status bridge_io_on_loaded(struct io_mgr *hio_mgr) status = CHNL_E_NOMEMMAP; } if (DSP_SUCCEEDED(status)) { -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG status = cod_get_sym_value(cod_man, DSP_TRACESEC_END, &shm0_end); #else @@ -746,7 +746,7 @@ dsp_status bridge_io_on_loaded(struct io_mgr *hio_mgr) hmsg_mgr->max_msgs); memset((void *)hio_mgr->shared_mem, 0, sizeof(struct shm)); -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG /* Get the start address of trace buffer */ status = cod_get_sym_value(cod_man, SYS_PUTCBEG, &hio_mgr->ul_trace_buffer_begin); @@ -943,7 +943,7 @@ void io_dpc(IN OUT unsigned long pRefData) (pio_mgr->intr_val < DEH_LIMIT)) { /* Notify DSP/BIOS exception */ if (hdeh_mgr) { -#ifndef DSP_TRACE_BUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG print_dsp_debug_trace(pio_mgr); #endif bridge_deh_notify(hdeh_mgr, DSP_SYSERROR, @@ -955,7 +955,7 @@ void io_dpc(IN OUT unsigned long pRefData) if (msg_mgr_obj) io_dispatch_msg(pio_mgr, msg_mgr_obj); #endif -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG if (pio_mgr->intr_val & MBX_DBG_SYSPRINTF) { /* Notify DSP Trace message */ print_dsp_debug_trace(pio_mgr); @@ -1804,7 +1804,7 @@ dsp_status bridge_io_get_proc_load(IN struct io_mgr *hio_mgr, return DSP_SOK; } -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_OMAP_DSP_DEBUG void print_dsp_debug_trace(struct io_mgr *hio_mgr) { u32 ul_new_message_length = 0, ul_gpp_cur_pointer; From patchwork Sat Jul 3 00:19:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Que, Simon" X-Patchwork-Id: 109969 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o630JF7J000437 for ; Sat, 3 Jul 2010 00:19:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753073Ab0GCATK (ORCPT ); Fri, 2 Jul 2010 20:19:10 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:55419 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753267Ab0GCATJ (ORCPT ); Fri, 2 Jul 2010 20:19:09 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o630J8Dj020922 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 2 Jul 2010 19:19:08 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o630J8Xh021605; Fri, 2 Jul 2010 19:19:08 -0500 (CDT) Received: from dlee74.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o630J8d4014628; Fri, 2 Jul 2010 19:19:08 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dlee74.ent.ti.com ([157.170.170.8]) with mapi; Fri, 2 Jul 2010 19:19:07 -0500 From: "Que, Simon" To: "linux-omap@vger.kernel.org" CC: "Kanigeri, Hari" , Ohad Ben-Cohen Date: Fri, 2 Jul 2010 19:19:07 -0500 Subject: [RFC v.3] omap: hwspinlock: Added hwspinlock driver Thread-Topic: [RFC v.3] omap: hwspinlock: Added hwspinlock driver Thread-Index: AcsaRVnBic4tzJlzTXSC2whrLKA8+A== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 03 Jul 2010 00:19:16 +0000 (UTC) ================================================================ From 86223480bb46177b4c625b01122d0a4f40eb95c0 Mon Sep 17 00:00:00 2001 From: Simon Que Date: Wed, 23 Jun 2010 18:40:30 -0500 Subject: [PATCH] omap: hwspinlock: Added hwspinlock driver Created driver for OMAP hardware spinlock. This driver supports: - Reserved spinlocks for internal use - Dynamic allocation of unreserved locks - Lock, unlock, and trylock functions, with or without disabling irqs/preempt - Registered as a platform device driver The device initialization uses hwmod to configure the devices. One device will be created for each hardware spinlock. It will pass spinlock register addresses to the driver. The device initialization file is: arch/arm/mach-omap2/hwspinlocks.c The driver takes in data passed in device initialization. The function hwspinlock_probe() initializes the array of spinlock structures, each containing a spinlock register address provided by the device initialization. The device driver file is: arch/arm/plat-omap/hwspinlock.c Here's an API summary: int hwspinlock_lock(struct hwspinlock *); Attempt to lock a hardware spinlock. If it is busy, the function will keep trying until it succeeds. This is a blocking function. int hwspinlock_trylock(struct hwspinlock *); Attempt to lock a hardware spinlock. If it is busy, the function will return BUSY. If it succeeds in locking, the function will return ACQUIRED. This is a non-blocking function int hwspinlock_unlock(struct hwspinlock *); Unlock a hardware spinlock. struct hwspinlock *hwspinlock_request(void); Provides for "dynamic allocation" of a hardware spinlock. It returns the handle to the next available (unallocated) spinlock. If no more locks are available, it returns NULL. struct hwspinlock *hwspinlock_request_specific(unsigned int); Provides for "static allocation" of a specific hardware spinlock. This allows the system to use a specific spinlock, identified by an ID. If the ID is invalid or if the desired lock is already allocated, this will return NULL. Otherwise it returns a spinlock handle. int hwspinlock_free(struct hwspinlock *); Frees an allocated hardware spinlock (either reserved or unreserved). Signed-off-by: Simon Que --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/hwspinlocks.c | 72 ++++++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +- arch/arm/plat-omap/Makefile | 3 +- arch/arm/plat-omap/hwspinlock.c | 298 ++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/hwspinlock.h | 29 +++ arch/arm/plat-omap/include/plat/omap44xx.h | 2 + 7 files changed, 406 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/hwspinlocks.c create mode 100644 arch/arm/plat-omap/hwspinlock.c create mode 100644 arch/arm/plat-omap/include/plat/hwspinlock.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 6725b3a..5f5c87b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -170,3 +170,5 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) + +obj-$(CONFIG_ARCH_OMAP4) += hwspinlocks.o \ No newline at end of file diff --git a/arch/arm/mach-omap2/hwspinlocks.c b/arch/arm/mach-omap2/hwspinlocks.c new file mode 100644 index 0000000..f0b212b --- /dev/null +++ b/arch/arm/mach-omap2/hwspinlocks.c @@ -0,0 +1,72 @@ +/* + * OMAP hardware spinlock device initialization + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +/* Spinlock register offsets */ +#define REVISION_OFFSET 0x0000 +#define SYSCONFIG_OFFSET 0x0010 +#define SYSSTATUS_OFFSET 0x0014 +#define LOCK_BASE_OFFSET 0x0800 +#define LOCK_OFFSET(i) (LOCK_BASE_OFFSET + 0x4 * (i)) + +/* Initialization function */ +int __init hwspinlocks_init(void) +{ + int retval = 0; + + struct hwspinlock_plat_info *pdata; + struct omap_hwmod *oh; + char *oh_name, *pdev_name; + + oh_name = "spinlock"; + oh = omap_hwmod_lookup(oh_name); + if (WARN_ON(oh == NULL)) + return -EINVAL; + + pdev_name = "hwspinlock"; + + /* Pass data to device initialization */ + pdata = kzalloc(sizeof(struct hwspinlock_plat_info), GFP_KERNEL); + if (WARN_ON(pdata == NULL)) + return -ENOMEM; + pdata->sysstatus_offset = SYSSTATUS_OFFSET; + pdata->lock_base_offset = LOCK_BASE_OFFSET; + + omap_device_build(pdev_name, 0, oh, pdata, + sizeof(struct hwspinlock_plat_info), NULL, 0, false); + + return retval; +} +module_init(hwspinlocks_init); + diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index d8d6d58..ce6c5ff 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -4875,7 +4875,7 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* &omap44xx_smartreflex_iva_hwmod, */ /* &omap44xx_smartreflex_mpu_hwmod, */ /* spinlock class */ -/* &omap44xx_spinlock_hwmod, */ + &omap44xx_spinlock_hwmod, /* timer class */ &omap44xx_timer1_hwmod, &omap44xx_timer2_hwmod, diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index a37abf5..f725afc 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -32,4 +32,5 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o obj-$(CONFIG_OMAP_REMOTE_PROC) += remoteproc.o -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o \ No newline at end of file diff --git a/arch/arm/plat-omap/hwspinlock.c b/arch/arm/plat-omap/hwspinlock.c new file mode 100644 index 0000000..7cfd2c0 --- /dev/null +++ b/arch/arm/plat-omap/hwspinlock.c @@ -0,0 +1,298 @@ +/* + * OMAP hardware spinlock driver + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Spinlock count code */ +#define SPINLOCK_32_REGS 1 +#define SPINLOCK_64_REGS 2 +#define SPINLOCK_128_REGS 4 +#define SPINLOCK_256_REGS 8 +#define SPINLOCK_NUMLOCKS_OFFSET 24 + +/* for managing a hardware spinlock module */ +struct hwspinlock_state { + bool is_init; /* For first-time initialization */ + int num_locks; /* Total number of locks in system */ + spinlock_t local_lock; /* Local protection */ + void __iomem *io_base; /* Mapped base address */ +}; + +/* Points to the hardware spinlock module */ +static struct hwspinlock_state hwspinlock_state; +static struct hwspinlock_state *hwspinlock_module = &hwspinlock_state; + +/* Spinlock object */ +struct hwspinlock { + bool is_init; + int id; + void __iomem *lock_reg; + bool is_allocated; + struct platform_device *pdev; +}; + +/* Array of spinlocks */ +static struct hwspinlock *hwspinlocks; + +/* API functions */ + +/* Busy loop to acquire a spinlock */ +int hwspinlock_lock(struct hwspinlock *handle) +{ + int retval; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + if (pm_runtime_get(&handle->pdev->dev) < 0) + return -ENODEV; + + /* Attempt to acquire the lock by reading from it */ + do { + retval = readl(handle->lock_reg); + } while (retval == HWSPINLOCK_BUSY); + + if (retval == HWSPINLOCK_BUSY) + pm_runtime_put(&handle->pdev->dev); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_lock); + +/* Attempt to acquire a spinlock once */ +int hwspinlock_trylock(struct hwspinlock *handle) +{ + int retval = 0; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + if (pm_runtime_get(&handle->pdev->dev) < 0) + return -ENODEV; + + /* Attempt to acquire the lock by reading from it */ + retval = readl(handle->lock_reg); + + if (retval == HWSPINLOCK_BUSY) + pm_runtime_put(&handle->pdev->dev); + + return retval; +} +EXPORT_SYMBOL(hwspinlock_trylock); + +/* Release a spinlock */ +int hwspinlock_unlock(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + /* Release it by writing 0 to it */ + writel(0, handle->lock_reg); + + pm_runtime_put(&handle->pdev->dev); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_unlock); + +/* Request an unclaimed spinlock */ +struct hwspinlock *hwspinlock_request(void) +{ + int i; + bool found = false; + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + /* Search for an unclaimed, unreserved lock */ + for (i = 0; i < hwspinlock_module->num_locks && !found; i++) { + if (!hwspinlocks[i].is_allocated) { + found = true; + handle = &hwspinlocks[i]; + } + } + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + + /* Return error if no more locks available */ + if (!found) + return NULL; + + handle->is_allocated = true; + + return handle; +} +EXPORT_SYMBOL(hwspinlock_request); + +/* Request an unclaimed spinlock by ID */ +struct hwspinlock *hwspinlock_request_specific(unsigned int id) +{ + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + + if (WARN_ON(hwspinlocks[id].is_allocated)) + goto exit; + + handle = &hwspinlocks[id]; + handle->is_allocated = true; + +exit: + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + return handle; +} +EXPORT_SYMBOL(hwspinlock_request_specific); + +/* Release a claimed spinlock */ +int hwspinlock_free(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(!handle->is_allocated)) + return -ENOMEM; + + handle->is_allocated = false; + + return 0; +} +EXPORT_SYMBOL(hwspinlock_free); + +/* Probe function */ +static int __devinit hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_plat_info *pdata = pdev->dev.platform_data; + struct resource *res; + void __iomem *io_base; + int id; + + void __iomem *sysstatus_reg; + + /* Determine number of locks */ + sysstatus_reg = ioremap(OMAP44XX_SPINLOCK_BASE + + pdata->sysstatus_offset, sizeof(u32)); + switch (readl(sysstatus_reg) >> SPINLOCK_NUMLOCKS_OFFSET) { + case SPINLOCK_32_REGS: + hwspinlock_module->num_locks = 32; + break; + case SPINLOCK_64_REGS: + hwspinlock_module->num_locks = 64; + break; + case SPINLOCK_128_REGS: + hwspinlock_module->num_locks = 128; + break; + case SPINLOCK_256_REGS: + hwspinlock_module->num_locks = 256; + break; + default: + return -EINVAL; /* Invalid spinlock count code */ + } + iounmap(sysstatus_reg); + + /* Allocate spinlock device objects */ + hwspinlocks = kmalloc(sizeof(struct hwspinlock) * + hwspinlock_module->num_locks, GFP_KERNEL); + if (WARN_ON(hwspinlocks == NULL)) + return -ENOMEM; + + /* Initialize local lock */ + spin_lock_init(&hwspinlock_module->local_lock); + + /* Get address info */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + /* Map spinlock module address space */ + io_base = ioremap(res->start, resource_size(res)); + hwspinlock_module->io_base = io_base; + + /* Set up each individual lock handle */ + for (id = 0; id < hwspinlock_module->num_locks; id++) { + hwspinlocks[id].id = id; + hwspinlocks[id].pdev = pdev; + + hwspinlocks[id].is_init = true; + hwspinlocks[id].is_allocated = false; + + hwspinlocks[id].lock_reg = io_base + pdata-> + lock_base_offset + sizeof(u32) * id; + } + + return 0; +} + +static struct platform_driver hwspinlock_driver = { + .probe = hwspinlock_probe, + .driver = { + .name = "hwspinlock", + }, +}; + +/* Initialization function */ +static int __init hwspinlock_init(void) +{ + int retval = 0; + + /* Register spinlock driver */ + retval = platform_driver_register(&hwspinlock_driver); + + return retval; +} + +/* Cleanup function */ +static void __exit hwspinlock_exit(void) +{ + int id; + + platform_driver_unregister(&hwspinlock_driver); + + for (id = 0; id < hwspinlock_module->num_locks; id++) + hwspinlocks[id].is_init = false; + iounmap(hwspinlock_module->io_base); + + /* Free spinlock device objects */ + if (hwspinlock_module->is_init) + kfree(hwspinlocks); +} + +module_init(hwspinlock_init); +module_exit(hwspinlock_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver"); +MODULE_AUTHOR("Simon Que"); +MODULE_AUTHOR("Hari Kanigeri"); diff --git a/arch/arm/plat-omap/include/plat/hwspinlock.h b/arch/arm/plat-omap/include/plat/hwspinlock.h new file mode 100644 index 0000000..8c69ca5 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/hwspinlock.h @@ -0,0 +1,29 @@ +/* hwspinlock.h */ + +#ifndef HWSPINLOCK_H +#define HWSPINLOCK_H + +#include +#include + +/* Read values from the spinlock register */ +#define HWSPINLOCK_ACQUIRED 0 +#define HWSPINLOCK_BUSY 1 + +/* Device data */ +struct hwspinlock_plat_info { + u32 sysstatus_offset; /* System status register offset */ + u32 lock_base_offset; /* Offset of spinlock registers */ +}; + +struct hwspinlock; + +int hwspinlock_lock(struct hwspinlock *handle); +int hwspinlock_trylock(struct hwspinlock *handle); +int hwspinlock_unlock(struct hwspinlock *handle); + +struct hwspinlock *hwspinlock_request(void); +struct hwspinlock *hwspinlock_request_specific(unsigned int id); +int hwspinlock_free(struct hwspinlock *hwspinlock_ptr); + +#endif /* HWSPINLOCK_H */ diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index 8b3f12f..8016508 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -52,5 +52,7 @@ #define OMAP4_MMU1_BASE 0x55082000 #define OMAP4_MMU2_BASE 0x4A066000 +#define OMAP44XX_SPINLOCK_BASE (L4_44XX_BASE + 0xF6000) + #endif /* __ASM_ARCH_OMAP44XX_H */ From patchwork Wed Jul 28 14:54:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114803 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SEob2U013430 for ; Wed, 28 Jul 2010 14:50:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754822Ab0G1Ouc (ORCPT ); Wed, 28 Jul 2010 10:50:32 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:35830 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755265Ab0G1Ou3 (ORCPT ); Wed, 28 Jul 2010 10:50:29 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SEoMX9032758 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 09:50:22 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6SEoLZM028498; Wed, 28 Jul 2010 09:50:21 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SEo4NA024733; Wed, 28 Jul 2010 09:50:06 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH 4/4] staging:ti dspbridge: remove bridge_brd_delete function Date: Wed, 28 Jul 2010 09:54:55 -0500 Message-Id: <1280328895-31375-5-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 In-Reply-To: <1280328895-31375-4-git-send-email-ernesto@ti.com> References: <1280328895-31375-1-git-send-email-ernesto@ti.com> <1280328895-31375-2-git-send-email-ernesto@ti.com> <1280328895-31375-3-git-send-email-ernesto@ti.com> <1280328895-31375-4-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 14:50:38 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index e7584de..f914829 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -686,61 +686,6 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) } /* - * ======== bridge_brd_delete ======== - * purpose: - * Puts DSP in Low power mode - * - * Preconditions : - * a) None - */ -static int bridge_brd_delete(struct bridge_dev_context *dev_ctxt) -{ - int status = 0; - struct bridge_dev_context *dev_context = dev_ctxt; - struct pg_table_attrs *pt_attrs; - int clk_status; - struct dspbridge_platform_data *pdata = - omap_dspbridge_dev->dev.platform_data; - - if (dev_context->dw_brd_state == BRD_STOPPED) - return status; - - /* as per TRM, it is advised to first drive - * the IVA2 to 'Standby' mode, before turning off the clocks.. This is - * to ensure that there are no pending L3 or other transactons from - * IVA2 */ - status = sleep_dsp(dev_context, PWR_EMERGENCYDEEPSLEEP, NULL); - clk_status = dsp_clk_disable(DSP_CLK_IVA2); - - /* Release the Ext Base virtual Address as the next DSP Program - * may have a different load address */ - if (dev_context->dw_dsp_ext_base_addr) - dev_context->dw_dsp_ext_base_addr = 0; - - dev_context->dw_brd_state = BRD_STOPPED; /* update board state */ - - /* This is a good place to clear the MMU page tables as well */ - if (dev_context->pt_attrs) { - pt_attrs = dev_context->pt_attrs; - memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size); - memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size); - memset((u8 *) pt_attrs->pg_info, 0x00, - (pt_attrs->l2_num_pages * sizeof(struct page_info))); - } - /* Disable the mail box interrupts */ - if (dev_context->mbox) { - omap_mbox_disable_irq(dev_context->mbox, IRQ_RX); - omap_mbox_put(dev_context->mbox); - dev_context->mbox = NULL; - } - /* Reset IVA2 clocks*/ - (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | - OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); - - return status; -} - -/* * ======== bridge_brd_status ======== * Returns the board status. */ @@ -1023,7 +968,7 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt) return -EFAULT; /* first put the device to stop state */ - bridge_brd_delete(dev_context); + bridge_brd_stop(dev_context); if (dev_context->pt_attrs) { pt_attrs = dev_context->pt_attrs; kfree(pt_attrs->pg_info); From patchwork Wed Jul 28 14:54:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114802 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SEob2T013430 for ; Wed, 28 Jul 2010 14:50:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754914Ab0G1OuO (ORCPT ); Wed, 28 Jul 2010 10:50:14 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:58239 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752019Ab0G1OuM (ORCPT ); Wed, 28 Jul 2010 10:50:12 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SEo73g016353 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 09:50:07 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6SEo61B028265; Wed, 28 Jul 2010 09:50:07 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SEo4N9024733; Wed, 28 Jul 2010 09:50:06 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH 3/4] staging:ti dspbridge: make sure IVA2 is OFF when dev is created Date: Wed, 28 Jul 2010 09:54:54 -0500 Message-Id: <1280328895-31375-4-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 In-Reply-To: <1280328895-31375-3-git-send-email-ernesto@ti.com> References: <1280328895-31375-1-git-send-email-ernesto@ti.com> <1280328895-31375-2-git-send-email-ernesto@ti.com> <1280328895-31375-3-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 14:50:38 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 77527bd..e7584de 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -919,8 +919,10 @@ static int bridge_dev_create(struct bridge_dev_context if (!status) { dev_context->hdev_obj = hdev_obj; /* Store current board state. */ - dev_context->dw_brd_state = BRD_STOPPED; + dev_context->dw_brd_state = BRD_UNKNOWN; dev_context->resources = resources; + dsp_clk_enable(DSP_CLK_IVA2); + bridge_brd_stop(dev_context); /* Return ptr to our device state to the DSP API for storage */ *dev_cntxt = dev_context; } else { From patchwork Thu Jul 8 10:14:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 110816 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68AJjpj011666 for ; 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Thu, 8 Jul 2010 15:44:28 +0530 From: Hema HK To: linux-usb@vger.kernel.org, linux-omap@vger.kernel.org Cc: Hema HK , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH V2 3/4]usb: musb: HWMOD database structures addition for OMAP3 Date: Thu, 8 Jul 2010 15:44:28 +0530 Message-Id: <1278584068-15381-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 10:19:46 +0000 (UTC) Index: linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -82,6 +82,15 @@ static struct omap_hwmod omap3xxx_l3_mai }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; +static struct omap_hwmod omap3xxx_usbhsotg_hwmod; + +/* L3 <- USBHSOTG interface */ +static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { + .master = &omap3xxx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -90,6 +99,37 @@ static struct omap_hwmod_ocp_if omap3xxx .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* +* USBHSOTG interface data +*/ + +static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { + { + .pa_start = OMAP34XX_HSUSB_OTG_BASE, + .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* USBHSOTG <- L4_CORE interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = omap3xxx_usbhsotg_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs), + .user = OCP_USER_MPU, + +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { + &omap3xxx_usbhsotg__l3, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { + &omap3xxx_l4_core__usbhsotg, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -197,6 +237,56 @@ static struct omap_hwmod omap3xxx_iva_hw .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* + * USBHSOTG (USBHS) + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap3xxx_usbhsotg_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, + +}; + +static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs), + .main_clk = "hsotgusb_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_GRPSEL_HSOTGUSB_MASK, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT + }, + }, + .masters = omap3xxx_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), + .slaves = omap3xxx_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), + .class = &usbotg_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +294,7 @@ static __initdata struct omap_hwmod *oma &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_usbhsotg_hwmod, NULL, }; From patchwork Thu Jul 8 10:24:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 110817 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68AOTqY012486 for ; Thu, 8 Jul 2010 10:24:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754671Ab0GHKY1 (ORCPT ); Thu, 8 Jul 2010 06:24:27 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:46059 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753321Ab0GHKY0 (ORCPT ); Thu, 8 Jul 2010 06:24:26 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68AOJFU023786 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 05:24:22 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68AOIVd024352; Thu, 8 Jul 2010 15:54:18 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o68AOHlS019413; Thu, 8 Jul 2010 15:54:18 +0530 Received: (from a0876481@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o68AOHa8019411; Thu, 8 Jul 2010 15:54:17 +0530 From: Hema HK To: linux-usb@vger.kernel.org, linux-omap@vger.kernel.org Cc: Hema HK , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH V2 4/4]usb : musb:Using omap_device_build for musb device registration Date: Thu, 8 Jul 2010 15:54:17 +0530 Message-Id: <1278584657-18689-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 10:24:29 +0000 (UTC) Index: linux-omap-pm/arch/arm/mach-omap2/clock44xx_data.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/clock44xx_data.c +++ linux-omap-pm/arch/arm/mach-omap2/clock44xx_data.c @@ -2296,7 +2296,7 @@ static struct clk usb_host_fs_fck = { }; static struct clk usb_otg_ick = { - .name = "usb_otg_ick", + .name = "usb_otg_hs_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, Index: linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_44xx_data.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ linux-omap-pm/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -4884,7 +4884,7 @@ static __initdata struct omap_hwmod *oma /* usb_host_hs class */ /* &omap44xx_usb_host_hs_hwmod, */ /* usb_otg_hs class */ -/* &omap44xx_usb_otg_hs_hwmod, */ + &omap44xx_usb_otg_hs_hwmod, /* usb_tll_hs class */ /* &omap44xx_usb_tll_hs_hwmod, */ /* wd_timer class */ Index: linux-omap-pm/arch/arm/mach-omap2/usb-musb.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/usb-musb.c +++ linux-omap-pm/arch/arm/mach-omap2/usb-musb.c @@ -30,24 +30,12 @@ #include #include #include +#include #ifdef CONFIG_USB_MUSB_SOC -static struct resource musb_resources[] = { - [0] = { /* start and end set dynamically */ - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = INT_243X_HS_USB_MC, - .flags = IORESOURCE_IRQ, - .name = "mc", - }, - [2] = { /* DMA IRQ */ - .start = INT_243X_HS_USB_DMA, - .flags = IORESOURCE_IRQ, - .name = "dma", - }, -}; +static const char name[] = "musb_hdrc"; +#define MAX_OMAP_MUSB_HWMOD_NAME_LEN 16 static struct musb_hdrc_config musb_config = { .multipoint = 1, @@ -76,43 +64,60 @@ static struct musb_hdrc_platform_data mu static u64 musb_dmamask = DMA_BIT_MASK(32); -static struct platform_device musb_device = { - .name = "musb_hdrc", - .id = -1, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &musb_plat, +static struct omap_device_pm_latency omap_musb_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, }; void __init usb_musb_init(struct omap_musb_board_data *board_data) { - if (cpu_is_omap243x()) { - musb_resources[0].start = OMAP243X_HS_BASE; - } else if (cpu_is_omap34xx()) { - musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; - } else if (cpu_is_omap44xx()) { - musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; - musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; - musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; + char oh_name[MAX_OMAP_MUSB_HWMOD_NAME_LEN]; + struct omap_hwmod *oh; + struct omap_device *od; + struct platform_device *pdev; + struct device *dev; + int l, bus_id = -1; + struct musb_hdrc_platform_data *pdata; + + l = snprintf(oh_name, MAX_OMAP_MUSB_HWMOD_NAME_LEN, + "usb_otg_hs"); + WARN(l >= MAX_OMAP_MUSB_HWMOD_NAME_LEN, + "String buffer overflow in MUSB device setup\n"); + oh = omap_hwmod_lookup(oh_name); + + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + } else { + /* + * REVISIT: This line can be removed once all the platforms + * using musb_core.c have been converted to use use clkdev. + */ + musb_plat.clock = "ick"; + musb_plat.board_data = board_data; + musb_plat.power = board_data->power >> 1; + musb_plat.mode = board_data->mode; + pdata = &musb_plat; + + od = omap_device_build(name, bus_id, oh, pdata, + sizeof(struct musb_hdrc_platform_data), + omap_musb_latency, + ARRAY_SIZE(omap_musb_latency), false); + if (IS_ERR(od)) { + pr_err("Could not build omap_device for %s %s\n", + name, oh_name); + } else { + + pdev = &od->pdev; + dev = &pdev->dev; + get_device(dev); + dev->dma_mask = &musb_dmamask; + dev->coherent_dma_mask = musb_dmamask; + put_device(dev); + } } - musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; - - /* - * REVISIT: This line can be removed once all the platforms using - * musb_core.c have been converted to use use clkdev. - */ - musb_plat.clock = "ick"; - musb_plat.board_data = board_data; - musb_plat.power = board_data->power >> 1; - musb_plat.mode = board_data->mode; - musb_plat.extvbus = board_data->extvbus; - - if (platform_device_register(&musb_device) < 0) - printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); } #else From patchwork Wed Aug 4 11:32:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 117002 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74BWdBw023288 for ; Wed, 4 Aug 2010 11:32:39 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757604Ab0HDLcj (ORCPT ); Wed, 4 Aug 2010 07:32:39 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:61203 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755789Ab0HDLci (ORCPT ); Wed, 4 Aug 2010 07:32:38 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OgcD5-0000z7-0I; Wed, 04 Aug 2010 11:32:35 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19zBfpQk8UU93Wk2mU831g6 Subject: [PATCH 1/3] omap: device: improve errors handling To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Nishanth Menon , Artem Bityutskiy , Paul Walmsley , linux-omap@vger.kernel.org Date: Wed, 04 Aug 2010 14:32:59 +0300 Message-ID: <20100804113259.25027.47129.stgit@baageli.muru.com> In-Reply-To: <20100804112916.25027.94640.stgit@baageli.muru.com> References: <20100804112916.25027.94640.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 11:32:40 +0000 (UTC) diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index ea0d659..d2b1609 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -407,7 +407,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, od->pdev.num_resources = res_count; od->pdev.resource = res; - platform_device_add_data(&od->pdev, pdata, pdata_len); + ret = platform_device_add_data(&od->pdev, pdata, pdata_len); + if (ret) + goto odbs_exit4; od->pm_lats = pm_lats; od->pm_lats_cnt = pm_lats_cnt; From patchwork Wed Aug 4 11:33:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 117003 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74BWgfh023302 for ; Wed, 4 Aug 2010 11:32:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932565Ab0HDLcl (ORCPT ); Wed, 4 Aug 2010 07:32:41 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:62046 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932357Ab0HDLck (ORCPT ); Wed, 4 Aug 2010 07:32:40 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OgcD9-000Bqy-QI; Wed, 04 Aug 2010 11:32:40 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19FDi1RRiiyNE08kiVDYwM4 Subject: [PATCH 2/3] OMAP3630: Add ES1.1 and ES1.2 detection To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Nishanth Menon , Manjunatha GK , linux-omap@vger.kernel.org, Anand Gadiyar Date: Wed, 04 Aug 2010 14:33:07 +0300 Message-ID: <20100804113307.25027.8630.stgit@baageli.muru.com> In-Reply-To: <20100804112916.25027.94640.stgit@baageli.muru.com> References: <20100804112916.25027.94640.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 11:32:43 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index fd1904b..e8256a2 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -269,11 +269,27 @@ static void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; break; case 0xb891: - /* FALLTHROUGH */ + /* Handle 36xx devices */ + omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + break; + case 2: + default: + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + break; + } default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP3630ES1; + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; } } @@ -349,6 +365,12 @@ static void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index aa2f4f0..2e2ae53 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -66,6 +66,8 @@ unsigned int omap_rev(void); * family. This difference can be handled separately. */ #define OMAP_REVBITS_00 0x00 +#define OMAP_REVBITS_01 0x01 +#define OMAP_REVBITS_02 0x02 #define OMAP_REVBITS_10 0x10 #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 @@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3430_REV_ES3_1_2 0x34305034 #define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 +#define OMAP3630_REV_ES1_2 0x36300234 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) #define CHIP_IS_OMAP4430ES1 (1 << 8) +#define CHIP_IS_OMAP3630ES1_1 (1 << 9) +#define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517) */ #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ CHIP_IS_OMAP3430ES3_0 | \ - CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) + CHIP_GE_OMAP3430ES3_1) #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) - + CHIP_IS_OMAP3630ES1 | \ + CHIP_GE_OMAP3630ES1_1) +#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ + CHIP_IS_OMAP3630ES1_2) int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); From patchwork Wed Aug 4 11:33:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 117004 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74BWjVW023318 for ; Wed, 4 Aug 2010 11:32:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932648Ab0HDLco (ORCPT ); Wed, 4 Aug 2010 07:32:44 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:61256 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932641Ab0HDLco (ORCPT ); Wed, 4 Aug 2010 07:32:44 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OgcDD-00011I-Hf; Wed, 04 Aug 2010 11:32:43 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1882kxNbhGqoaj3eDoHqV0w Subject: [PATCH 3/3] omap: 3630: disable TLL SAR on 3630 ES1 To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Paul Walmsley , linux-omap@vger.kernel.org, Anand Gadiyar Date: Wed, 04 Aug 2010 14:33:12 +0300 Message-ID: <20100804113312.25027.93983.stgit@baageli.muru.com> In-Reply-To: <20100804112916.25027.94640.stgit@baageli.muru.com> References: <20100804112916.25027.94640.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 11:32:46 +0000 (UTC) diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index bd87112..fa90486 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h @@ -75,12 +75,19 @@ static struct powerdomain mpu_3xxx_pwrdm = { }, }; +/* + * The USBTLL Save-and-Restore mechanism is broken on + * 3430s upto ES3.0 and 3630ES1.0. Hence this feature + * needs to be disabled on these chips. + * Refer: 3430 errata ID i459 and 3630 errata ID i579 + */ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0), + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3630ES1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 2, @@ -97,7 +104,8 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { static struct powerdomain core_3xxx_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | + CHIP_GE_OMAP3630ES1_1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ From patchwork Wed Jul 28 14:54:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114808 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SEpOud013587 for ; Wed, 28 Jul 2010 14:51:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755421Ab0G1Ouv (ORCPT ); Wed, 28 Jul 2010 10:50:51 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:58265 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755329Ab0G1Oua (ORCPT ); Wed, 28 Jul 2010 10:50:30 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SEoMc3016383 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 09:50:22 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6SEoLcT013967; Wed, 28 Jul 2010 09:50:21 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SEo4N8024733; Wed, 28 Jul 2010 09:50:06 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH 2/4] staging:ti dspbridge: proc_load/start should set IVA2 to OFF in case of failure Date: Wed, 28 Jul 2010 09:54:53 -0500 Message-Id: <1280328895-31375-3-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 In-Reply-To: <1280328895-31375-2-git-send-email-ernesto@ti.com> References: <1280328895-31375-1-git-send-email-ernesto@ti.com> <1280328895-31375-2-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 14:51:25 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index 6258d8b..44c26e1 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -1302,9 +1302,10 @@ int proc_load(void *hprocessor, const s32 argc_index, } func_end: - if (status) + if (status) { pr_err("%s: Processor failed to load\n", __func__); - + proc_stop(p_proc_object); + } DBC_ENSURE((!status && p_proc_object->proc_state == PROC_LOADED) || status); @@ -1594,6 +1595,7 @@ func_cont: } } else { pr_err("%s: Failed to start the dsp\n", __func__); + proc_stop(p_proc_object); } func_end: From patchwork Thu Jul 8 10:08:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110811 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68A8DWG009840 for ; Thu, 8 Jul 2010 10:10:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756007Ab0GHKIS (ORCPT ); Thu, 8 Jul 2010 06:08:18 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:64312 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754631Ab0GHKIR (ORCPT ); Thu, 8 Jul 2010 06:08:17 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWo1h-0002YK-7n; Thu, 08 Jul 2010 10:08:17 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1/iRGUzLwHIx3LrqQxhNyj7 Subject: [PATCH 1/5] omap3: serial: Add context save and restore for mcr To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Nishanth Menon , Govindraj R , linux-omap@vger.kernel.org Date: Thu, 08 Jul 2010 13:08:12 +0300 Message-ID: <20100708100812.19285.48402.stgit@baageli.muru.com> In-Reply-To: <20100708100715.19285.30066.stgit@baageli.muru.com> References: <20100708100715.19285.30066.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 10:10:15 +0000 (UTC) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 3771254..804dbb2 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -74,6 +74,7 @@ struct omap_uart_state { u16 sysc; u16 scr; u16 wer; + u16 mcr; #endif }; @@ -197,6 +198,9 @@ static void omap_uart_save_context(struct omap_uart_state *uart) uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); uart->scr = serial_read_reg(p, UART_OMAP_SCR); uart->wer = serial_read_reg(p, UART_OMAP_WER); + serial_write_reg(p, UART_LCR, 0x80); + uart->mcr = serial_read_reg(p, UART_MCR); + serial_write_reg(p, UART_LCR, lcr); uart->context_valid = 1; } @@ -225,6 +229,8 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) serial_write_reg(p, UART_DLM, uart->dlh); serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ serial_write_reg(p, UART_IER, uart->ier); + serial_write_reg(p, UART_LCR, 0x80); + serial_write_reg(p, UART_MCR, uart->mcr); serial_write_reg(p, UART_FCR, 0xA1); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ serial_write_reg(p, UART_EFR, efr); From patchwork Wed May 5 14:27:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97103 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5P7002693 for ; Wed, 5 May 2010 14:28:07 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934752Ab0EEO2D (ORCPT ); Wed, 5 May 2010 10:28:03 -0400 Received: from smtp.nokia.com ([192.100.122.230]:64971 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932234Ab0EEO15 (ORCPT ); Wed, 5 May 2010 10:27:57 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERrlT008227; Wed, 5 May 2010 17:27:53 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:46 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:45 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfR3016232; Wed, 5 May 2010 17:27:44 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 01/21] OMAP: DSS2: Taal: Add panel hardware reset Date: Wed, 5 May 2010 17:27:21 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:45.0539 (UTC) FILETIME=[2121C530:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:08 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index aaf5d30..181dfe4 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -488,6 +488,22 @@ static struct attribute_group taal_attr_group = { .attrs = taal_attrs, }; +static void taal_hw_reset(struct omap_dss_device *dssdev) +{ + if (dssdev->reset_gpio == -1) + return; + + gpio_set_value(dssdev->reset_gpio, 1); + udelay(10); + /* reset the panel */ + gpio_set_value(dssdev->reset_gpio, 0); + /* assert reset for at least 10us */ + udelay(10); + gpio_set_value(dssdev->reset_gpio, 1); + /* wait 5ms after releasing reset */ + msleep(5); +} + static int taal_probe(struct omap_dss_device *dssdev) { struct backlight_properties props; @@ -525,6 +541,8 @@ static int taal_probe(struct omap_dss_device *dssdev) dev_set_drvdata(&dssdev->dev, td); + taal_hw_reset(dssdev); + /* if no platform set_backlight() defined, presume DSI backlight * control */ memset(&props, 0, sizeof(struct backlight_properties)); @@ -626,6 +644,9 @@ static void taal_remove(struct omap_dss_device *dssdev) cancel_delayed_work_sync(&td->esd_work); destroy_workqueue(td->esd_wq); + /* reset, to be sure that the panel is in a valid state */ + taal_hw_reset(dssdev); + kfree(td); } @@ -652,6 +673,8 @@ static int taal_power_on(struct omap_dss_device *dssdev) goto err0; } + taal_hw_reset(dssdev); + omapdss_dsi_vc_enable_hs(TCH, false); r = taal_sleep_out(td); @@ -702,6 +725,10 @@ static int taal_power_on(struct omap_dss_device *dssdev) return 0; err: + dev_err(&dssdev->dev, "error while enabling panel, issuing HW reset\n"); + + taal_hw_reset(dssdev); + omapdss_dsi_display_disable(dssdev); err0: dsi_bus_unlock(); @@ -714,16 +741,24 @@ err0: static void taal_power_off(struct omap_dss_device *dssdev) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + int r; dsi_bus_lock(); cancel_delayed_work(&td->esd_work); - taal_dcs_write_0(DCS_DISPLAY_OFF); - taal_sleep_in(td); + r = taal_dcs_write_0(DCS_DISPLAY_OFF); + if (!r) { + r = taal_sleep_in(td); + /* wait a bit so that the message goes through */ + msleep(10); + } - /* wait a bit so that the message goes through */ - msleep(10); + if (r) { + dev_err(&dssdev->dev, + "error disabling panel, issuing HW reset\n"); + taal_hw_reset(dssdev); + } omapdss_dsi_display_disable(dssdev); @@ -1184,6 +1219,7 @@ err: dev_err(&dssdev->dev, "performing LCD reset\n"); taal_power_off(dssdev); + taal_hw_reset(dssdev); taal_power_on(dssdev); dsi_bus_unlock(); From patchwork Tue Jun 29 19:27:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Que, Simon" X-Patchwork-Id: 108693 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5TJFIXI014655 for ; Tue, 29 Jun 2010 19:31:01 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755379Ab0F2T1w (ORCPT ); Tue, 29 Jun 2010 15:27:52 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:54572 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755299Ab0F2T1v (ORCPT ); Tue, 29 Jun 2010 15:27:51 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5TJRltS010415 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 29 Jun 2010 14:27:47 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o5TJRlIT006976; Tue, 29 Jun 2010 14:27:47 -0500 (CDT) Received: from dsbe71.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5TJRl62011718; Tue, 29 Jun 2010 14:27:47 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dsbe71.ent.ti.com ([156.117.232.23]) with mapi; Tue, 29 Jun 2010 14:27:47 -0500 From: "Que, Simon" To: "linux-omap@vger.kernel.org" , Kevin Hilman , "Cousson, Benoit" , "Shilimkar, Santosh" , "Pandita, Vikram" CC: "Kanigeri, Hari" , Ohad Ben-Cohen Date: Tue, 29 Jun 2010 14:27:46 -0500 Subject: [RFC v.2] omap: hwspinlock: Added hwspinlock driver Thread-Topic: [RFC v.2] omap: hwspinlock: Added hwspinlock driver Thread-Index: AcsT/uSyE+vCHOyESneG/KF0kTr/FgAAAmjwACTwLoAABDm0IABIUJyqAFCFkiA= Message-ID: References: , In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 29 Jun 2010 19:33:30 +0000 (UTC) ============================================================================ From a1aa1f5a85814bdf924d140b664a3305224392b2 Mon Sep 17 00:00:00 2001 From: Simon Que Date: Wed, 23 Jun 2010 18:40:30 -0500 Subject: [PATCH] omap: hwspinlock: Added hwspinlock driver Created driver for OMAP hardware spinlock. This driver supports: - Reserved spinlocks for internal use - Dynamic allocation of unreserved locks - Lock, unlock, and trylock functions, with or without disabling irqs/preempt - Registered as a platform device driver The device initialization uses hwmod to configure the devices. One device will be created for each hardware spinlock. It will pass spinlock register addresses to the driver. The device initialization file is: arch/arm/mach-omap2/hwspinlocks.c The driver takes in data passed in device initialization. The function hwspinlock_probe() initializes the array of spinlock structures, each containing a spinlock register address provided by the device initialization. The device driver file is: arch/arm/plat-omap/hwspinlock.c Here's an API summary: int hwspinlock_lock(struct hwspinlock *); Attempt to lock a hardware spinlock. If it is busy, the function will keep trying until it succeeds. This is a blocking function. int hwspinlock_trylock(struct hwspinlock *); Attempt to lock a hardware spinlock. If it is busy, the function will return BUSY. If it succeeds in locking, the function will return ACQUIRED. This is a non-blocking function int hwspinlock_unlock(struct hwspinlock *); Unlock a hardware spinlock. struct hwspinlock *hwspinlock_request(void); Provides for "dynamic allocation" of a hardware spinlock. It returns the handle to the next available (unallocated) spinlock. If no more locks are available, it returns NULL. struct hwspinlock *hwspinlock_request_specific(unsigned int); Provides for "static allocation" of a specific hardware spinlock. This allows the system to use a specific spinlock, identified by an ID. If the ID is invalid or if the desired lock is already allocated, this will return NULL. Otherwise it returns a spinlock handle. int hwspinlock_free(struct hwspinlock *); Frees an allocated hardware spinlock (either reserved or unreserved). Signed-off-by: Simon Que --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/hwspinlocks.c | 122 +++++++++++++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +- arch/arm/plat-omap/Makefile | 3 +- arch/arm/plat-omap/hwspinlock.c | 250 ++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/hwspinlock.h | 30 +++ arch/arm/plat-omap/include/plat/omap44xx.h | 2 + 7 files changed, 409 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/hwspinlocks.c create mode 100644 arch/arm/plat-omap/hwspinlock.c create mode 100644 arch/arm/plat-omap/include/plat/hwspinlock.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 6725b3a..5f5c87b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -170,3 +170,5 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) + +obj-$(CONFIG_ARCH_OMAP4) += hwspinlocks.o \ No newline at end of file diff --git a/arch/arm/mach-omap2/hwspinlocks.c b/arch/arm/mach-omap2/hwspinlocks.c new file mode 100644 index 0000000..868edea --- /dev/null +++ b/arch/arm/mach-omap2/hwspinlocks.c @@ -0,0 +1,122 @@ +/* + * OMAP hardware spinlock driver + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#define SPINLOCK_REGADDR(reg) (OMAP44XX_SPINLOCK_BASE + (reg)) + +/* Spinlock register offsets */ +#define REVISION_OFFSET 0x0000 +#define SYSCONFIG_OFFSET 0x0010 +#define SYSSTATUS_OFFSET 0x0014 +#define LOCK_BASE_OFFSET 0x0800 + +/* Spinlock register addresses */ +#define SPINLOCK_REVISION_REG \ + SPINLOCK_REGADDR(REVISION_OFFSET) +#define SPINLOCK_SYSCONFIG_REG \ + SPINLOCK_REGADDR(SYSCONFIG_OFFSET) +#define SPINLOCK_SYSSTATUS_REG \ + SPINLOCK_REGADDR(SYSSTATUS_OFFSET) +#define SPINLOCK_LOCK_REG(i) \ + SPINLOCK_REGADDR(LOCK_BASE_OFFSET + 0x4 * (i)) + +/* Spinlock count code */ +#define SPINLOCK_32_REGS 1 +#define SPINLOCK_64_REGS 2 +#define SPINLOCK_128_REGS 4 +#define SPINLOCK_256_REGS 8 +#define SPINLOCK_NUMLOCKS_OFFSET 24 + +/* Initialization function */ +int __init hwspinlocks_init(void) +{ + int i; + int retval = 0; + + struct hwspinlock_plat_info *pdata; + void __iomem *base; + int num_locks; + + void __iomem *sysstatus_reg = ioremap(SPINLOCK_SYSSTATUS_REG, + sizeof(u32)); + + struct omap_hwmod *oh; + char *oh_name, *pdev_name; + + /* Determine number of locks */ + switch (readl(sysstatus_reg) >> SPINLOCK_NUMLOCKS_OFFSET) { + case SPINLOCK_32_REGS: + num_locks = 32; + break; + case SPINLOCK_64_REGS: + num_locks = 64; + break; + case SPINLOCK_128_REGS: + num_locks = 128; + break; + case SPINLOCK_256_REGS: + num_locks = 256; + break; + default: + return -EINVAL; /* Invalid spinlock count code */ + } + + iounmap(sysstatus_reg); + + oh_name = "spinlock"; + oh = omap_hwmod_lookup(oh_name); + if (WARN_ON(oh == NULL)) + return -EINVAL; + + pdev_name = "hwspinlock"; + + /* Device drivers */ + for (i = 0; i < num_locks; i++) { + base = ioremap(SPINLOCK_LOCK_REG(i), sizeof(u32)); + + /* Pass data to device initialization */ + pdata = kzalloc(sizeof(struct hwspinlock_plat_info), + GFP_KERNEL); + pdata->num_locks = num_locks; + pdata->io_base = base; + + omap_device_build(pdev_name, i, oh, pdata, + sizeof(struct hwspinlock_plat_info), + NULL, 0, false); + } + + return retval; +} +module_init(hwspinlocks_init); + diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index d8d6d58..ce6c5ff 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -4875,7 +4875,7 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* &omap44xx_smartreflex_iva_hwmod, */ /* &omap44xx_smartreflex_mpu_hwmod, */ /* spinlock class */ -/* &omap44xx_spinlock_hwmod, */ + &omap44xx_spinlock_hwmod, /* timer class */ &omap44xx_timer1_hwmod, &omap44xx_timer2_hwmod, diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index a37abf5..f725afc 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -32,4 +32,5 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o obj-$(CONFIG_OMAP_REMOTE_PROC) += remoteproc.o -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o \ No newline at end of file diff --git a/arch/arm/plat-omap/hwspinlock.c b/arch/arm/plat-omap/hwspinlock.c new file mode 100644 index 0000000..dbbf543 --- /dev/null +++ b/arch/arm/plat-omap/hwspinlock.c @@ -0,0 +1,250 @@ +/* + * OMAP hardware spinlock driver + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* for managing a hardware spinlock module */ +struct hwspinlock_state { + bool is_init; /* For first-time initialization */ + int num_locks; /* Total number of locks in system */ + spinlock_t local_lock; /* Local protection */ +}; + +/* Points to the hardware spinlock module */ +static struct hwspinlock_state hwspinlock_state; +static struct hwspinlock_state *hwspinlock_module = &hwspinlock_state; + +/* Spinlock object */ +struct hwspinlock { + bool is_init; + void __iomem *io_base; + bool is_allocated; + struct platform_device *pdev; +}; + +/* Array of spinlocks */ +static struct hwspinlock *hwspinlocks; + +/* API functions */ + +/* Busy loop to acquire a spinlock */ +int hwspinlock_lock(struct hwspinlock *handle) +{ + int retval; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + /* Attempt to acquire the lock by reading from it */ + do { + retval = readl(handle->io_base); + } while (retval == HWSPINLOCK_BUSY); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_lock); + +/* Attempt to acquire a spinlock once */ +int hwspinlock_trylock(struct hwspinlock *handle) +{ + int retval = 0; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + /* Attempt to acquire the lock by reading from it */ + retval = readl(handle->io_base); + + return retval; +} +EXPORT_SYMBOL(hwspinlock_trylock); + +/* Release a spinlock */ +int hwspinlock_unlock(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + /* Release it by writing 0 to it */ + writel(0, handle->io_base); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_unlock); + +/* Request an unclaimed spinlock */ +struct hwspinlock *hwspinlock_request(void) +{ + int i; + bool found = false; + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + /* Search for an unclaimed, unreserved lock */ + for (i = 0; i < hwspinlock_module->num_locks && !found; i++) { + if (!hwspinlocks[i].is_allocated) { + found = true; + handle = &hwspinlocks[i]; + } + } + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + + /* Return error if no more locks available */ + if (!found) + return NULL; + + handle->is_allocated = true; + + return handle; +} +EXPORT_SYMBOL(hwspinlock_request); + +/* Request an unclaimed spinlock by ID */ +struct hwspinlock *hwspinlock_request_specific(unsigned int id) +{ + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + + if (WARN_ON(hwspinlocks[id].is_allocated)) + goto exit; + + handle = &hwspinlocks[id]; + handle->is_allocated = true; + +exit: + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + return handle; +} +EXPORT_SYMBOL(hwspinlock_request_specific); + +/* Release a claimed spinlock */ +int hwspinlock_free(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(!handle->is_allocated)) + return -ENOMEM; + + handle->is_allocated = false; + + return 0; +} +EXPORT_SYMBOL(hwspinlock_free); + +/* Probe function */ +static int __devinit hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_plat_info *pdata = pdev->dev.platform_data; + int id; + + /* Set up the spinlock count and array */ + if (!hwspinlock_module->is_init) { + hwspinlock_module->num_locks = pdata->num_locks; + + /* Allocate spinlock device objects */ + hwspinlocks = kmalloc(sizeof(struct hwspinlock) * + hwspinlock_module->num_locks, GFP_KERNEL); + if (WARN_ON(hwspinlocks == NULL)) + return -ENOMEM; + + /* Initialize local lock */ + spin_lock_init(&hwspinlock_module->local_lock); + + /* Only do initialization once */ + hwspinlock_module->is_init = true; + + for (id = 0; id < pdata->num_locks; id++) + hwspinlocks[id].is_init = false; + } + + id = pdev->id; + + hwspinlocks[id].pdev = pdev; + + hwspinlocks[id].is_allocated = false; + hwspinlocks[id].io_base = pdata->io_base; + hwspinlocks[id].is_init = true; + + return 0; +} + +static struct platform_driver hwspinlock_driver = { + .probe = hwspinlock_probe, + .driver = { + .name = "hwspinlock", + }, +}; + +/* Initialization function */ +static int __init hwspinlock_init(void) +{ + int retval = 0; + + /* Register spinlock driver */ + retval = platform_driver_register(&hwspinlock_driver); + + return retval; +} + +/* Cleanup function */ +static void __exit hwspinlock_exit(void) +{ + int id; + + platform_driver_unregister(&hwspinlock_driver); + + for (id = 0; id < hwspinlock_module->num_locks; id++) { + iounmap(hwspinlocks[id].io_base); + hwspinlocks[id].is_init = false; + } + + /* Free spinlock device objects */ + if (hwspinlock_module->is_init) + kfree(hwspinlocks); +} + +module_init(hwspinlock_init); +module_exit(hwspinlock_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver"); +MODULE_AUTHOR("Simon Que"); +MODULE_AUTHOR("Hari Kanigeri"); diff --git a/arch/arm/plat-omap/include/plat/hwspinlock.h b/arch/arm/plat-omap/include/plat/hwspinlock.h new file mode 100644 index 0000000..6de2cb9 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/hwspinlock.h @@ -0,0 +1,30 @@ +/* hwspinlock.h */ + +#ifndef HWSPINLOCK_H +#define HWSPINLOCK_H + +#include +#include + +/* Read values from the spinlock register */ +#define HWSPINLOCK_ACQUIRED 0 +#define HWSPINLOCK_BUSY 1 + +/* Device data */ +struct hwspinlock_plat_info { + int num_locks; /* Number of locks (initialization) */ + void __iomem *io_base; /* Address of spinlock register */ + bool is_reserved; /* Reserved for system use? */ +}; + +struct hwspinlock; + +int hwspinlock_lock(struct hwspinlock *handle); +int hwspinlock_trylock(struct hwspinlock *handle); +int hwspinlock_unlock(struct hwspinlock *handle); + +struct hwspinlock *hwspinlock_request(void); +struct hwspinlock *hwspinlock_request_specific(unsigned int id); +int hwspinlock_free(struct hwspinlock *hwspinlock_ptr); + +#endif /* HWSPINLOCK_H */ diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index 8b3f12f..8016508 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -52,5 +52,7 @@ #define OMAP4_MMU1_BASE 0x55082000 #define OMAP4_MMU2_BASE 0x4A066000 +#define OMAP44XX_SPINLOCK_BASE (L4_44XX_BASE + 0xF6000) + #endif /* __ASM_ARCH_OMAP44XX_H */ From patchwork Sun May 23 20:10:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Gelmini X-Patchwork-Id: 101769 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4NKALQ5006995 for ; Sun, 23 May 2010 20:10:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753610Ab0EWUKT (ORCPT ); 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Sun, 23 May 2010 13:10:13 -0700 (PDT) Received: from localhost.localdomain (net-93-145-200-9.t2.dsl.vodafone.it [93.145.200.9]) by mx.google.com with ESMTPS id d4sm8324360fga.0.2010.05.23.13.10.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 23 May 2010 13:10:12 -0700 (PDT) From: Andrea Gelmini To: andrea.gelmini@gelma.net Cc: Tomi Valkeinen , Tony Lindgren , Andrew Morton , Koen Kooi , David Brownell , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH 015/199] Video omap lcd_omap3beagle.c: duplicated include Date: Sun, 23 May 2010 22:10:01 +0200 Message-Id: <1274645401-27734-4-git-send-email-andrea.gelmini@gelma.net> X-Mailer: git-send-email 1.7.1.251.gf80a2 In-Reply-To: <1274645401-27734-1-git-send-email-andrea.gelmini@gelma.net> References: <1274645401-27734-1-git-send-email-andrea.gelmini@gelma.net> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 23 May 2010 20:10:21 +0000 (UTC) diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c index ca75cc2..ac715f9 100644 --- a/drivers/video/omap/lcd_omap3beagle.c +++ b/drivers/video/omap/lcd_omap3beagle.c @@ -26,7 +26,6 @@ #include #include -#include #include #include "omapfb.h" From patchwork Fri Mar 12 15:27:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 85311 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2CFMwtK024947 for ; Fri, 12 Mar 2010 15:28:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934345Ab0CLP2a (ORCPT ); Fri, 12 Mar 2010 10:28:30 -0500 Received: from smtp.nokia.com ([192.100.122.233]:41352 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934328Ab0CLP23 (ORCPT ); Fri, 12 Mar 2010 10:28:29 -0500 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CFRwIN030816; Fri, 12 Mar 2010 17:28:17 +0200 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 17:27:57 +0200 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 17:27:58 +0200 Received: from localhost.localdomain (esdhcp041162.research.nokia.com [172.21.41.162]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CFRqbf004595; Fri, 12 Mar 2010 17:27:56 +0200 From: Roger Quadros To: Tomi.Valkeinen@nokia.com Cc: linux-fbdev-devel@lists.sourceforge.net, linux-omap@vger.kernel.org Subject: [RFC][PATCH 3/3] OMAP: DSS2: Use vdds_sdi regulator supply in SDI Date: Fri, 12 Mar 2010 17:27:24 +0200 Message-Id: <1268407644-31230-4-git-send-email-roger.quadros@nokia.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1268407644-31230-3-git-send-email-roger.quadros@nokia.com> References: <1268407644-31230-1-git-send-email-roger.quadros@nokia.com> <1268407644-31230-2-git-send-email-roger.quadros@nokia.com> <1268407644-31230-3-git-send-email-roger.quadros@nokia.com> X-OriginalArrivalTime: 12 Mar 2010 15:27:58.0233 (UTC) FILETIME=[9828A090:01CAC1F8] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 12 Mar 2010 15:28:31 +0000 (UTC) diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c index 45aab89..e816e80 100644 --- a/drivers/video/omap2/dss/sdi.c +++ b/drivers/video/omap2/dss/sdi.c @@ -23,13 +23,16 @@ #include #include #include +#include #include +#include #include "dss.h" static struct { bool skip_init; bool update_enabled; + struct regulator *vdds_sdi_reg; } sdi; static void sdi_basic_init(void) @@ -57,6 +60,12 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) goto err0; } + if (cpu_is_omap34xx()) { + r = regulator_enable(sdi.vdds_sdi_reg); + if (r) + goto err1; + } + /* In case of skip_init sdi_init has already enabled the clocks */ if (!sdi.skip_init) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); @@ -118,10 +127,10 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) sdi.skip_init = 0; return 0; -err3: - dssdev->manager->disable(dssdev->manager); err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + if (cpu_is_omap34xx()) + regulator_enable(sdi.vdds_sdi_reg); err1: omap_dss_stop_device(dssdev); err0: @@ -137,6 +146,9 @@ void omapdss_sdi_display_disable(struct omap_dss_device *dssdev) dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + if (cpu_is_omap34xx()) + regulator_enable(sdi.vdds_sdi_reg); + omap_dss_stop_device(dssdev); } EXPORT_SYMBOL(omapdss_sdi_display_disable); @@ -144,6 +156,13 @@ EXPORT_SYMBOL(omapdss_sdi_display_disable); int sdi_init_display(struct omap_dss_device *dssdev) { DSSDBG("SDI init\n"); + if (cpu_is_omap34xx()) { + sdi.vdds_sdi_reg = dss_get_vdds_sdi(); + if (IS_ERR(sdi.vdds_sdi_reg)) { + DSSERR("can't get VDDS_SDI regulator\n"); + return PTR_ERR(sdi.vdds_sdi_reg); + } + } return 0; } From patchwork Thu Jul 8 22:51:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110952 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsW5U011297 for ; Thu, 8 Jul 2010 22:54:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932100Ab0GHWyb (ORCPT ); Thu, 8 Jul 2010 18:54:31 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:37490 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932088Ab0GHWya (ORCPT ); Thu, 8 Jul 2010 18:54:30 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms2Fv026348 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:27 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaH022017; Fri, 9 Jul 2010 04:24:00 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 07/10] OMAP2/3/4: DMA: Move chain API's to mach-omap2 Date: Fri, 9 Jul 2010 04:21:19 +0530 Message-Id: <1278629482-32501-8-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:32 +0000 (UTC) The DMA chaining feature is supported from omap2 plus processors and not supported in omap1. Moving DMA chain API's to mach-omap2. Note: Existing DMA chain API's in plat-omap will be cleaned up in another patch. This make sure that build is not broken with individual patches. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap2/dma.c | 663 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/include/mach/dma.h | 27 ++ 2 files changed, 690 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 548321b..f5fe0f5 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -30,6 +30,59 @@ #include #include +#define omap2_dma_read(reg) __raw_readl(dma_base + reg) +#define omap2_dma_write(val, reg) __raw_writel(val, dma_base + reg) + +enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, + DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED +}; + +enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; + +/* Chain handling macros */ +#define OMAP_DMA_CHAIN_QINIT(chain_id) \ + do { \ + dma_linked_lch[chain_id].q_head = \ + dma_linked_lch[chain_id].q_tail = \ + dma_linked_lch[chain_id].q_count = 0; \ + } while (0) +#define OMAP_DMA_CHAIN_QFULL(chain_id) \ + (dma_linked_lch[chain_id].no_of_lchs_linked == \ + dma_linked_lch[chain_id].q_count) +#define OMAP_DMA_CHAIN_QLAST(chain_id) \ + do { \ + ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ + dma_linked_lch[chain_id].q_count) \ + } while (0) +#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ + (0 == dma_linked_lch[chain_id].q_count) +#define __OMAP_DMA_CHAIN_INCQ(end) \ + ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) +#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ + do { \ + __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ + dma_linked_lch[chain_id].q_count--; \ + } while (0) + +#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ + do { \ + __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ + dma_linked_lch[chain_id].q_count++; \ + } while (0) + +struct dma_link_info { + int *linked_dmach_q; + int no_of_lchs_linked; + + int q_count; + int q_tail; + int q_head; + + int chain_state; + int chain_mode; + +}; + struct omap_device_pm_latency omap2_dma_latency[] = { { .deactivate_func = omap_device_idle_hwmods, @@ -81,6 +134,616 @@ static void __iomem *dma_base; static struct dma_link_info *dma_linked_lch; static u32 dma_chan_count; +/* Create chain of DMA channesls */ +static void create_dma_lch_chain(int lch_head, int lch_queue) +{ + u32 reg, ch_reg_base, l; + + /* Check if this is the first link in chain */ + if (dma_chan[lch_head].next_linked_ch == -1) { + dma_chan[lch_head].next_linked_ch = lch_queue; + dma_chan[lch_head].prev_linked_ch = lch_queue; + dma_chan[lch_queue].next_linked_ch = lch_head; + dma_chan[lch_queue].prev_linked_ch = lch_head; + } + + /* a link exists, link the new channel in circular chain */ + else { + dma_chan[lch_queue].next_linked_ch = + dma_chan[lch_head].next_linked_ch; + dma_chan[lch_queue].prev_linked_ch = lch_head; + dma_chan[lch_head].next_linked_ch = lch_queue; + dma_chan[dma_chan[lch_queue].next_linked_ch]. + prev_linked_ch = lch_queue; + } + + ch_reg_base = r->lch_base * lch_head; + reg = ch_reg_base + r->common_ch.clnk_ctrl; + l = omap2_dma_read(reg); + l &= ~(0x1f); + l |= lch_queue; + omap2_dma_write(l, reg); + + ch_reg_base = r->lch_base * lch_queue; + reg = ch_reg_base + r->common_ch.clnk_ctrl; + l = omap2_dma_read(reg); + l &= ~(0x1f); + l |= (dma_chan[lch_queue].next_linked_ch); + omap2_dma_write(l, reg); +} + +/** + * @brief omap_request_dma_chain : Request a chain of DMA channels + * + * @param dev_id - Device id using the dma channel + * @param dev_name - Device name + * @param callback - Call back function + * @chain_id - + * @no_of_chans - Number of channels requested + * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN + * OMAP_DMA_DYNAMIC_CHAIN + * @params - Channel parameters + * + * @return - Success : 0 + * Failure: -EINVAL/-ENOMEM + */ +int omap_request_dma_chain(int dev_id, const char *dev_name, + void (*callback) (int lch, u16 ch_status, + void *data), + int *chain_id, int no_of_chans, int chain_mode, + struct omap_dma_channel_params params) +{ + int *channels; + int i, err; + + /* Is the chain mode valid ? */ + if (chain_mode != OMAP_DMA_STATIC_CHAIN + && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) { + printk(KERN_ERR "Invalid chain mode requested\n"); + return -EINVAL; + } + + if (unlikely((no_of_chans < 1 + || no_of_chans > d->dma_lch_count))) { + printk(KERN_ERR "Invalid Number of channels requested\n"); + return -EINVAL; + } + + /* + * Allocate a queue to maintain the status of the channels + * in the chain + */ + channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); + if (channels == NULL) { + printk(KERN_ERR "omap_dma: No memory for channel queue\n"); + return -ENOMEM; + } + + /* request and reserve DMA channels for the chain */ + for (i = 0; i < no_of_chans; i++) { + err = omap_request_dma(dev_id, dev_name, + callback, NULL, &channels[i]); + if (err < 0) { + int j; + for (j = 0; j < i; j++) + omap_free_dma(channels[j]); + kfree(channels); + printk(KERN_ERR "omap_dma: Request failed %d\n", err); + return err; + } + dma_chan[channels[i]].prev_linked_ch = -1; + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; + + /* + * Allowing client drivers to set common parameters now, + * so that later only relevant (src_start, dest_start + * and element count) can be set + */ + omap_set_dma_params(channels[i], ¶ms); + } + + *chain_id = channels[0]; + dma_linked_lch[*chain_id].linked_dmach_q = channels; + dma_linked_lch[*chain_id].chain_mode = chain_mode; + dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED; + dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans; + + for (i = 0; i < no_of_chans; i++) + dma_chan[channels[i]].chain_id = *chain_id; + + /* Reset the Queue pointers */ + OMAP_DMA_CHAIN_QINIT(*chain_id); + + /* Set up the chain */ + if (no_of_chans == 1) + create_dma_lch_chain(channels[0], channels[0]); + else { + for (i = 0; i < (no_of_chans - 1); i++) + create_dma_lch_chain(channels[i], channels[i + 1]); + } + + return 0; +} +EXPORT_SYMBOL(omap_request_dma_chain); + +/** + * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the + * params after setting it. Dont do this while dma is running!! + * + * @param chain_id - Chained logical channel id. + * @param params + * + * @return - Success : 0 + * Failure : -EINVAL + */ +int omap_modify_dma_chain_params(int chain_id, + struct omap_dma_channel_params params) +{ + int *channels; + u32 i; + + /* Check for input params */ + if (unlikely((chain_id < 0 + || chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + channels = dma_linked_lch[chain_id].linked_dmach_q; + + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { + /* + * Allowing client drivers to set common parameters now, + * so that later only relevant (src_start, dest_start + * and element count) can be set + */ + omap_set_dma_params(channels[i], ¶ms); + } + + return 0; +} +EXPORT_SYMBOL(omap_modify_dma_chain_params); + +/** + * @brief omap_free_dma_chain - Free all the logical channels in a chain. + * + * @param chain_id + * + * @return - Success : 0 + * Failure : -EINVAL + */ +int omap_free_dma_chain(int chain_id) +{ + int *channels; + u32 i; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { + dma_chan[channels[i]].next_linked_ch = -1; + dma_chan[channels[i]].prev_linked_ch = -1; + dma_chan[channels[i]].chain_id = -1; + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; + omap_free_dma(channels[i]); + } + + kfree(channels); + + dma_linked_lch[chain_id].linked_dmach_q = NULL; + dma_linked_lch[chain_id].chain_mode = -1; + dma_linked_lch[chain_id].chain_state = -1; + + return 0; +} +EXPORT_SYMBOL(omap_free_dma_chain); + +/** + * @brief omap_dma_chain_status - Check if the chain is in + * active / inactive state. + * @param chain_id + * + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE + * Failure : -EINVAL + */ +int omap_dma_chain_status(int chain_id) +{ + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + pr_debug("CHAINID=%d, qcnt=%d\n", chain_id, + dma_linked_lch[chain_id].q_count); + + if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) + return OMAP_DMA_CHAIN_INACTIVE; + + return OMAP_DMA_CHAIN_ACTIVE; +} +EXPORT_SYMBOL(omap_dma_chain_status); + +/** + * @brief omap_dma_chain_a_transfer - Get a free channel from a chain, + * set the params and start the transfer. + * + * @param chain_id + * @param src_start - buffer start address + * @param dest_start - Dest address + * @param elem_count + * @param frame_count + * @param callbk_data - channel callback parameter data. + * + * @return - Success : 0 + * Failure: -EINVAL/-EBUSY + */ +int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, + int elem_count, int frame_count, void *callbk_data) +{ + int *channels; + u32 reg, ch_reg_base, l, lch; + int start_dma = 0; + + /* + * if buffer size is less than 1 then there is + * no use of starting the chain + */ + if (elem_count < 1) { + printk(KERN_ERR "Invalid buffer size\n"); + return -EINVAL; + } + + /* Check for input params */ + if (unlikely((chain_id < 0 + || chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exist\n"); + return -EINVAL; + } + + /* Check if all the channels in chain are in use */ + if (OMAP_DMA_CHAIN_QFULL(chain_id)) + return -EBUSY; + + /* Frame count may be negative in case of indexed transfers */ + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get a free channel */ + lch = channels[dma_linked_lch[chain_id].q_tail]; + + /* Store the callback data */ + dma_chan[lch].data = callbk_data; + + /* Increment the q_tail */ + OMAP_DMA_CHAIN_INCQTAIL(chain_id); + + ch_reg_base = r->lch_base * lch; + /* Set the params to the free channel */ + if (src_start != 0) { + reg = ch_reg_base + r->ch_specific.cssa; + omap2_dma_write(src_start, reg); + } + if (dest_start != 0) { + reg = ch_reg_base + r->ch_specific.cdsa; + omap2_dma_write(src_start, reg); + } + + /* Write the buffer size */ + reg = ch_reg_base + r->common_ch.cen; + omap2_dma_write(elem_count, reg); + reg = ch_reg_base + r->common_ch.cfn; + omap2_dma_write(frame_count, reg); + + /* + * If the chain is dynamically linked, + * then we may have to start the chain if its not active + */ + if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { + + /* + * In Dynamic chain, if the chain is not started, + * queue the channel + */ + if (dma_linked_lch[chain_id].chain_state == + DMA_CHAIN_NOTSTARTED) { + /* Enable the link in previous channel */ + if (dma_chan[dma_chan[lch].prev_linked_ch].state == + DMA_CH_QUEUED) + omap_enable_lnk(dma_chan[lch].prev_linked_ch); + dma_chan[lch].state = DMA_CH_QUEUED; + } + + /* + * Chain is already started, make sure its active, + * if not then start the chain + */ + else { + start_dma = 1; + + if (dma_chan[dma_chan[lch].prev_linked_ch].state == + DMA_CH_STARTED) { + ch_reg_base = r->lch_base * + dma_chan[lch].prev_linked_ch; + + omap_enable_lnk(dma_chan[lch].prev_linked_ch); + dma_chan[lch].state = DMA_CH_QUEUED; + start_dma = 0; + reg = ch_reg_base + r->common_ch.ccr; + if (0 == ((1 << 7) & omap2_dma_read(reg))) { + omap_disable_lnk(dma_chan[lch]. + prev_linked_ch); + pr_debug("\n prev ch is stopped\n"); + start_dma = 1; + } + } + + else if (dma_chan[dma_chan[lch].prev_linked_ch].state + == DMA_CH_QUEUED) { + omap_enable_lnk(dma_chan[lch].prev_linked_ch); + dma_chan[lch].state = DMA_CH_QUEUED; + start_dma = 0; + } + omap_enable_channel_irq(lch); + ch_reg_base = r->lch_base * lch; + reg = ch_reg_base + r->common_ch.ccr; + l = omap2_dma_read(reg); + + if ((0 == (l & (1 << 24)))) + l &= ~(1 << 25); + else + l |= (1 << 25); + if (start_dma == 1) { + if (0 == (l & (1 << 7))) { + l |= (1 << 7); + dma_chan[lch].state = DMA_CH_STARTED; + pr_debug("starting %d\n", lch); + omap2_dma_write(l, reg); + } else + start_dma = 0; + } else { + if (0 == (l & (1 << 7))) + omap2_dma_write(l, reg); + } + dma_chan[lch].flags |= OMAP_DMA_ACTIVE; + } + } + + return 0; +} +EXPORT_SYMBOL(omap_dma_chain_a_transfer); + +/** + * @brief omap_start_dma_chain_transfers - Start the chain + * + * @param chain_id + * + * @return - Success : 0 + * Failure : -EINVAL/-EBUSY + */ +int omap_start_dma_chain_transfers(int chain_id) +{ + int *channels; + u32 reg, ch_reg_base, l, i; + + if (unlikely((chain_id < 0 || chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) { + printk(KERN_ERR "Chain is already started\n"); + return -EBUSY; + } + + if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) { + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; + i++) { + omap_enable_lnk(channels[i]); + omap_enable_channel_irq(channels[i]); + } + } else { + omap_enable_channel_irq(channels[0]); + } + + ch_reg_base = r->lch_base * channels[0]; + reg = ch_reg_base + r->common_ch.ccr; + l = omap2_dma_read(reg); + l |= (1 << 7); + dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; + dma_chan[channels[0]].state = DMA_CH_STARTED; + + if ((0 == (l & (1 << 24)))) + l &= ~(1 << 25); + else + l |= (1 << 25); + omap2_dma_write(l, reg); + + dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; + + return 0; +} +EXPORT_SYMBOL(omap_start_dma_chain_transfers); + + +/** + * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain. + * + * @param chain_id + * + * @return - Success : 0 + * Failure : EINVAL + */ +int omap_stop_dma_chain_transfers(int chain_id) +{ + /* Check for input params */ + if (unlikely((chain_id < 0 || + chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + + if (omap2_pdata->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(chain_id); + + return 0; +} +EXPORT_SYMBOL(omap_stop_dma_chain_transfers); + +/* Get the index of the ongoing DMA in chain */ +/** + * @brief omap_get_dma_chain_index - Get the element and frame index + * of the ongoing DMA in chain + * + * @param chain_id + * @param ei - Element index + * @param fi - Frame index + * + * @return - Success : 0 + * Failure : -EINVAL + */ +int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) +{ + int lch; + int *channels; + u32 reg; + + /* Check for input params */ + if (unlikely((chain_id < 0 || + chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + if ((!ei) || (!fi)) + return -EINVAL; + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get the current channel */ + lch = channels[dma_linked_lch[chain_id].q_head]; + + reg = (r->lch_base * lch) + r->ch_specific.ccen; + *ei = omap2_dma_read(reg); + reg = (r->lch_base * lch) + r->ch_specific.ccfn; + *fi = omap2_dma_read(reg); + + return 0; +} +EXPORT_SYMBOL(omap_get_dma_chain_index); + +/** + * @brief omap_get_dma_chain_dst_pos - Get the destination position of the + * ongoing DMA in chain + * + * @param chain_id + * + * @return - Success : Destination position + * Failure : -EINVAL + */ +int omap_get_dma_chain_dst_pos(int chain_id) +{ + int lch; + int *channels; + u32 reg; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get the current channel */ + lch = channels[dma_linked_lch[chain_id].q_head]; + reg = (r->lch_base * lch) + r->common_ch.cdac; + + return omap2_dma_read(reg); +} +EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); + +/** + * @brief omap_get_dma_chain_src_pos - Get the source position + * of the ongoing DMA in chain + * @param chain_id + * + * @return - Success : Destination position + * Failure : -EINVAL + */ +int omap_get_dma_chain_src_pos(int chain_id) +{ + int lch; + int *channels; + u32 reg; + + /* Check for input params */ + if (unlikely((chain_id < 0 || chain_id >= d->dma_lch_count))) { + printk(KERN_ERR "Invalid chain id\n"); + return -EINVAL; + } + + /* Check if the chain exists */ + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { + printk(KERN_ERR "Chain doesn't exists\n"); + return -EINVAL; + } + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + /* Get the current channel */ + lch = channels[dma_linked_lch[chain_id].q_head]; + reg = (r->lch_base * lch) + r->common_ch.csac; + + return omap2_dma_read(reg); +} +EXPORT_SYMBOL(omap_get_dma_chain_src_pos); + /* One time initializations */ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) { diff --git a/arch/arm/mach-omap2/include/mach/dma.h b/arch/arm/mach-omap2/include/mach/dma.h index a8d8fee..c7a67b3 100644 --- a/arch/arm/mach-omap2/include/mach/dma.h +++ b/arch/arm/mach-omap2/include/mach/dma.h @@ -73,4 +73,31 @@ #define OMAP_DMA4_CNDP (0xd4) #define OMAP_DMA4_CCDN (0xd8) +/* Chaining modes*/ +#define OMAP_DMA_STATIC_CHAIN 0x1 +#define OMAP_DMA_DYNAMIC_CHAIN 0x2 +#define OMAP_DMA_CHAIN_ACTIVE 0x1 +#define OMAP_DMA_CHAIN_INACTIVE 0x0 + +/* Chaining APIs */ +extern int omap_request_dma_chain(int dev_id, const char *dev_name, + void (*callback) (int lch, u16 ch_status, + void *data), + int *chain_id, int no_of_chans, + int chain_mode, + struct omap_dma_channel_params params); +extern int omap_free_dma_chain(int chain_id); +extern int omap_dma_chain_a_transfer(int chain_id, int src_start, + int dest_start, int elem_count, + int frame_count, void *callbk_data); +extern int omap_start_dma_chain_transfers(int chain_id); +extern int omap_stop_dma_chain_transfers(int chain_id); +extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); +extern int omap_get_dma_chain_dst_pos(int chain_id); +extern int omap_get_dma_chain_src_pos(int chain_id); + +extern int omap_modify_dma_chain_params(int chain_id, + struct omap_dma_channel_params params); +extern int omap_dma_chain_status(int chain_id); + #endif /* __ASM_ARCH_OMAP2_DMA_H */ From patchwork Thu Jul 8 22:51:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110951 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsNOq011265 for ; Thu, 8 Jul 2010 22:54:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932084Ab0GHWyR (ORCPT ); Thu, 8 Jul 2010 18:54:17 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59498 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758730Ab0GHWyQ (ORCPT ); Thu, 8 Jul 2010 18:54:16 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms4gj002423 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:14 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaE022017; Fri, 9 Jul 2010 04:23:59 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 04/10] OMAP4: DMA: HWMOD: update OMAP4 data base Date: Fri, 9 Jul 2010 04:21:16 +0530 Message-Id: <1278629482-32501-5-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:23 +0000 (UTC) The OMAP4 hwmod data base is updated with DMA controller attributes. Also, irq name are changed from 0 to dma_0, 1->dma_1 ... in order provide meaningful name to irq names. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 21 ++++++++++++++++----- 1 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 20f5f8c..46d83f5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -22,6 +22,9 @@ #include #include +#include + +#include #include "omap_hwmod_common_data.h" @@ -750,12 +753,19 @@ static struct omap_hwmod_class omap44xx_dma_hwmod_class = { .sysc = &omap44xx_dma_sysc, }; +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dma_dev_attr = DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT, +}; + /* dma_system */ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { - { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, - { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, - { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, - { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, + { .name = "dma_0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, + { .name = "dma_1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, + { .name = "dma_2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, + { .name = "dma_3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, }; static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { @@ -801,6 +811,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), .masters = omap44xx_dma_system_masters, .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), + .dev_attr = &dma_dev_attr, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -4789,7 +4800,7 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* counter class */ &omap44xx_counter_32k_hwmod, /* dma class */ -/* &omap44xx_dma_system_hwmod, */ + &omap44xx_dma_system_hwmod, /* dmic class */ /* &omap44xx_dmic_hwmod, */ /* dsp class */ From patchwork Thu Jul 8 22:51:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110950 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsMqG011250 for ; Thu, 8 Jul 2010 22:54:22 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932096Ab0GHWyT (ORCPT ); Thu, 8 Jul 2010 18:54:19 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59502 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932088Ab0GHWyS (ORCPT ); Thu, 8 Jul 2010 18:54:18 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms1w7002420 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:10 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaD022017; Fri, 9 Jul 2010 04:23:59 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 03/10] OMAP3: DMA: HWMOD: Add hwmod data structures Date: Fri, 9 Jul 2010 04:21:15 +0530 Message-Id: <1278629482-32501-4-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:22 +0000 (UTC) This patch adds OMAP3 DMA hwmod structures. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 90 ++++++++++++++++++++++++++++ 1 files changed, 90 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index d3bf85b..ca23219 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -36,6 +37,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod; static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; +static struct omap_hwmod omap3xxx_dma_system_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -69,6 +71,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { &omap3xxx_l3_main__l4_per, }; +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { + .master = &omap3xxx_dma_system_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* L3 */ static struct omap_hwmod omap3xxx_l3_main_hwmod = { .name = "l3_main", @@ -197,6 +207,85 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dma_dev_attr = DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT, +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap3xxx_dma_sysc, +}; + +/* dma_system */ +static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { + { .name = "dma_0", .irq = INT_24XX_SDMA_IRQ0 }, + { .name = "dma_1", .irq = INT_24XX_SDMA_IRQ1 }, + { .name = "dma_2", .irq = INT_24XX_SDMA_IRQ2 }, + { .name = "dma_3", .irq = INT_24XX_SDMA_IRQ3 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { + &omap3xxx_dma_system__l3, +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap3xxx_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { + &omap3xxx_l4_core__dma_system, +}; + +static struct omap_hwmod omap3xxx_dma_system_hwmod = { + .name = "dma", + .class = &omap3xxx_dma_hwmod_class, + .mpu_irqs = omap3xxx_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs), + .main_clk = "l3_div_ck", + .prcm = { + .omap2 = { + /* .clkctrl_reg = NULL, */ + }, + }, + .slaves = omap3xxx_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), + .masters = omap3xxx_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +293,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_dma_system_hwmod, NULL, }; From patchwork Tue Nov 24 19:03:23 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 62550 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nAOJ3Z2b031504 for ; Tue, 24 Nov 2009 19:03:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933946AbZKXTDY (ORCPT ); Tue, 24 Nov 2009 14:03:24 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S933910AbZKXTDY (ORCPT ); Tue, 24 Nov 2009 14:03:24 -0500 Received: from ey-out-2122.google.com ([74.125.78.24]:19685 "EHLO ey-out-2122.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933903AbZKXTDX (ORCPT ); Tue, 24 Nov 2009 14:03:23 -0500 Received: by ey-out-2122.google.com with SMTP id 4so1337313eyf.19 for ; Tue, 24 Nov 2009 11:03:29 -0800 (PST) Received: by 10.216.88.195 with SMTP id a45mr2127598wef.63.1259089408862; Tue, 24 Nov 2009 11:03:28 -0800 (PST) Received: from localhost ([216.254.16.51]) by mx.google.com with ESMTPS id m5sm12668717gve.12.2009.11.24.11.03.26 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 24 Nov 2009 11:03:28 -0800 (PST) To: Paul Walmsley Cc: linux-omap@vger.kernel.org Subject: hwmod and PER going idle before WFI From: Kevin Hilman Organization: Deep Root Systems, LLC Date: Tue, 24 Nov 2009 11:03:23 -0800 Message-ID: <87fx83vj7o.fsf@deeprootsystems.com> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 627a509..da32764 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -398,7 +398,6 @@ void omap_sram_idle(void) per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); if (per_next_state < PWRDM_POWER_ON) { - omap_uart_prepare_idle(2); omap2_gpio_prepare_for_idle(per_next_state); if (per_next_state == PWRDM_POWER_OFF) { if (core_next_state == PWRDM_POWER_ON) { @@ -408,6 +407,7 @@ void omap_sram_idle(void) } else omap3_per_save_context(); } + omap_uart_prepare_idle(2); } if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) From patchwork Tue Mar 30 14:37:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkatraman S X-Patchwork-Id: 89327 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2UEbRBZ014424 for ; Tue, 30 Mar 2010 14:37:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755867Ab0C3Oh0 (ORCPT ); Tue, 30 Mar 2010 10:37:26 -0400 Received: from mail-pw0-f46.google.com ([209.85.160.46]:52398 "EHLO mail-pw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756202Ab0C3OhY (ORCPT ); Tue, 30 Mar 2010 10:37:24 -0400 Received: by pwi5 with SMTP id 5so7763652pwi.19 for ; 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Tue, 30 Mar 2010 07:37:19 -0700 (PDT) Message-ID: <618f0c911003300737w5562c18as1bfcb21671919718@mail.gmail.com> Subject: [PATCH]omap hsmmc: fix incorrect capability reporting From: Venkatraman S To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org, kishore.kadiyala@ti.com Cc: Madhusudhan Chikkature Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 30 Mar 2010 14:37:28 +0000 (UTC) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 83f0aff..dbf83a6 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2093,7 +2093,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) if (mmc_slot(host).wires >= 8) mmc->caps |= MMC_CAP_8_BIT_DATA; - else if (mmc_slot(host).wires >= 4) + if (mmc_slot(host).wires >= 4) mmc->caps |= MMC_CAP_4_BIT_DATA; From patchwork Thu Aug 5 22:24:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117574 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75Mfmtj029707 for ; Thu, 5 Aug 2010 22:41:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760836Ab0HEWl3 (ORCPT ); Thu, 5 Aug 2010 18:41:29 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:57516 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760835Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOJmk032466 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:19 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o75MOGMu024052; Thu, 5 Aug 2010 17:24:17 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOFf27291; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 27D16C26B; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 02/12] omap3: voltage: make required variables static Date: Thu, 5 Aug 2010 17:24:02 -0500 Message-Id: <1281047052-21346-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:41:51 +0000 (UTC) diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 3431fa3..1a3d00d 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -39,14 +39,14 @@ #define VP_TRANXDONE_TIMEOUT 300 #ifdef CONFIG_PM_DEBUG -struct dentry *voltage_dir; +static struct dentry *voltage_dir; #endif /* VP SR debug support */ u32 enable_sr_vp_debug; /* PRM voltage module */ -u32 volt_mod; +static u32 volt_mod; /* Voltage processor register offsets */ struct vp_reg_offs { @@ -127,7 +127,7 @@ static struct omap_vdd_info *vdd_info; static int no_scalable_vdd; /* OMAP3 VP register offsets and other definitions */ -struct __init vp_reg_offs omap3_vp_offs[] = { +static struct __init vp_reg_offs omap3_vp_offs[] = { /* VP1 */ { .vpconfig_reg = OMAP3_PRM_VP1_CONFIG_OFFSET, From patchwork Thu Aug 5 22:24:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117575 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75Mfmtk029707 for ; Thu, 5 Aug 2010 22:41:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760835Ab0HEWlb (ORCPT ); Thu, 5 Aug 2010 18:41:31 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:57510 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760820Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOHtX032455 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:17 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o75MOEV0028211; Thu, 5 Aug 2010 17:24:14 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOEf27247; Thu, 5 Aug 2010 17:24:14 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id E19BA416BB8; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 07/12] omap3: sr: device: make omap_sr_latency static Date: Thu, 5 Aug 2010 17:24:07 -0500 Message-Id: <1281047052-21346-8-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:41:51 +0000 (UTC) diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 8fb60d8..e816666 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -29,7 +29,7 @@ #include "voltage.h" -struct omap_device_pm_latency omap_sr_latency[] = { +static struct omap_device_pm_latency omap_sr_latency[] = { { .deactivate_func = omap_device_idle_hwmods, .activate_func = omap_device_enable_hwmods, From patchwork Thu Aug 5 22:24:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117576 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75Mfmtl029707 for ; Thu, 5 Aug 2010 22:41:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761048Ab0HEWlh (ORCPT ); Thu, 5 Aug 2010 18:41:37 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:47367 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760827Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOH22023639 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:18 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o75MOEOS007447; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOEf27261; Thu, 5 Aug 2010 17:24:14 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 09A89C260; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 09/12] omap3: sr: enable/disable sr only if required Date: Thu, 5 Aug 2010 17:24:09 -0500 Message-Id: <1281047052-21346-10-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:41:51 +0000 (UTC) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index d63691b..9b5a10e 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -778,15 +778,26 @@ static int omap_sr_autocomp_show(void *data, u64 *val) static int omap_sr_autocomp_store(void *data, u64 val) { struct omap_sr *sr_info = (struct omap_sr *) data; + u32 value = (u32) val; if (!sr_info) { pr_warning("%s: omap_sr struct for SR not found\n", __func__); return -EINVAL; } - if (!val) - sr_stop_vddautocomp(sr_info); - else - sr_start_vddautocomp(sr_info); + + /* Sanity check */ + if (value && (value != 1)) { + pr_err("%s: invalid value %d\n", __func__, value); + return -EINVAL; + } + + /* change only if needed */ + if (sr_info->is_autocomp_active ^ value) { + if (!val) + sr_stop_vddautocomp(sr_info); + else + sr_start_vddautocomp(sr_info); + } return 0; } From patchwork Wed May 19 00:13:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 100649 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4J0D89e027680 for ; Wed, 19 May 2010 00:13:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753225Ab0ESANI (ORCPT ); Tue, 18 May 2010 20:13:08 -0400 Received: from mail-pw0-f46.google.com ([209.85.160.46]:64175 "EHLO mail-pw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752565Ab0ESANH (ORCPT ); Tue, 18 May 2010 20:13:07 -0400 Received: by pwi5 with SMTP id 5so1255474pwi.19 for ; Tue, 18 May 2010 17:13:04 -0700 (PDT) Received: by 10.143.20.41 with SMTP id x41mr5520720wfi.216.1274227983811; Tue, 18 May 2010 17:13:03 -0700 (PDT) Received: from localhost (deeprootsystems.com [216.254.16.51]) by mx.google.com with ESMTPS id 21sm5404784pzk.4.2010.05.18.17.13.02 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 18 May 2010 17:13:03 -0700 (PDT) From: Kevin Hilman To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org Subject: [RFC/PATCH] arm: oprofile: remove locking from suspend/resume Date: Tue, 18 May 2010 17:13:01 -0700 Message-Id: <1274227981-20130-1-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.7.0.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 19 May 2010 00:13:09 +0000 (UTC) diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index 3fcd752..ea005d8 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -79,19 +79,15 @@ static void op_arm_stop(void) #ifdef CONFIG_PM static int op_arm_suspend(struct sys_device *dev, pm_message_t state) { - mutex_lock(&op_arm_mutex); if (op_arm_enabled) op_arm_model->stop(); - mutex_unlock(&op_arm_mutex); return 0; } static int op_arm_resume(struct sys_device *dev) { - mutex_lock(&op_arm_mutex); if (op_arm_enabled && op_arm_model->start()) op_arm_enabled = 0; - mutex_unlock(&op_arm_mutex); return 0; } From patchwork Thu Jun 17 15:26:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 106697 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HFRCGD025202 for ; Thu, 17 Jun 2010 15:27:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932898Ab0FQP1L (ORCPT ); Thu, 17 Jun 2010 11:27:11 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:60331 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760202Ab0FQP1K (ORCPT ); Thu, 17 Jun 2010 11:27:10 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HFR1cX029571 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 10:27:01 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HFQtKS027347; Thu, 17 Jun 2010 10:26:57 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099945); by dbdmail.itg.ti.com with HTTP; Thu, 17 Jun 2010 20:56:58 +0530 (IST) Message-ID: <43583.10.24.255.17.1276788418.squirrel@dbdmail.itg.ti.com> Date: Thu, 17 Jun 2010 20:56:58 +0530 (IST) Subject: [PATCH v5 1/2] OMAP HSMMC: Adding a Flag to determine the type of Card detect From: "kishore kadiyala" To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: tony@atomide.com, madhu.cr@ti.com, akpm@linux-foundation.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 15:27:13 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index f474a80..bd6f81d 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -40,6 +40,7 @@ #include #include +#include #include @@ -354,11 +355,13 @@ static struct omap2_hsmmc_info mmc[] = { * so the SIM card isn't used; else 4 bits. */ .wires = 8, + .cd_type = GPIO, .gpio_wp = 4, }, { .mmc = 2, .wires = 8, + .cd_type = GPIO, .gpio_wp = 7, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index e679a2c..ddf6968 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -46,6 +46,7 @@ #include #include #include +#include #include @@ -599,6 +600,7 @@ static struct omap2_hsmmc_info mmc[] = { .mmc = 1, .wires = 4, .gpio_cd = -EINVAL, + .cd_type = GPIO, .gpio_wp = -EINVAL, }, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 77022b5..114820f 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -122,6 +123,7 @@ static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 8, + .cd_type = GPIO, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d55c57b..bc1957f 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -250,6 +251,7 @@ static struct omap2_hsmmc_info mmc[] = { .mmc = 1, .wires = 4, .gpio_cd = -EINVAL, + .cd_type = GPIO, .gpio_wp = -EINVAL, }, { diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 69b154c..62d7fcb 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -184,6 +185,7 @@ static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 8, + .cd_type = GPIO, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index db06dc9..76752bf 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" @@ -232,6 +233,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { .mmc = 1, .wires = 4, .gpio_cd = -EINVAL, + .cd_type = GPIO, .gpio_wp = 126, .ext_clock = 0, }, @@ -239,6 +241,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { .mmc = 2, .wires = 4, .gpio_cd = -EINVAL, + .cd_type = GPIO, .gpio_wp = 127, .ext_clock = 1, .transceiver = true, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 2f5f823..83ccdcc 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -48,6 +48,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -126,6 +127,7 @@ static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 8, + .cd_type = GPIO, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index abdf321..130f745 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -284,6 +285,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { .wires = 4, .cover_only = true, .gpio_cd = 160, + .cd_type = GPIO, .gpio_wp = -EINVAL, .power_saving = true, }, diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b39849..f9c96e1 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -23,6 +23,7 @@ #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -156,6 +157,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { .name = "external", .mmc = 1, .wires = 4, + .cd_type = GPIO, .gpio_wp = -EINVAL, .power_saving = true, }, diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8..10690b9 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -17,6 +17,7 @@ struct omap2_hsmmc_info { bool no_off; /* power_saving and power is not to go off */ bool vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */ int gpio_cd; /* or -EINVAL */ + bool cd_type; /* GPIO or NON_GPIO */ int gpio_wp; /* or -EINVAL */ char *name; /* or NULL for default */ struct device *dev; /* returned: pointer to mmc adapter */ diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index c835f1e..ed60c0f 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -43,6 +43,9 @@ #define OMAP_MMC_MAX_SLOTS 2 +#define NON_GPIO 0 +#define GPIO 1 + struct omap_mmc_platform_data { /* back-link to device */ struct device *dev; @@ -107,6 +110,7 @@ struct omap_mmc_platform_data { unsigned features; int switch_pin; /* gpio (card detect) */ + unsigned cd_type:1; /* GPIO or NON_GPIO */ int gpio_wp; /* gpio (write protect) */ int (*set_bus_mode)(struct device *dev, int slot, int bus_mode); From patchwork Thu Aug 5 22:24:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117571 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75Mfmtg029707 for ; Thu, 5 Aug 2010 22:41:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934642Ab0HEWku (ORCPT ); Thu, 5 Aug 2010 18:40:50 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:36959 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760831Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOIpL014056 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:18 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o75MOGPH028229; Thu, 5 Aug 2010 17:24:16 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOFf27279; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 1F11DC269; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 05/12] omap3: sr: device: check for dev_attr Date: Thu, 5 Aug 2010 17:24:05 -0500 Message-Id: <1281047052-21346-6-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:41:49 +0000 (UTC) diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 7d13704..6f70da6 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -130,6 +130,12 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user) } sr_dev_data = (struct omap_sr_dev_data *)oh->dev_attr; + if (unlikely(!sr_dev_data)) { + pr_err("%s: Bad oh->dev_attr!\n", __func__); + kfree(sr_data); + return -EINVAL; + } + /* * OMAP3430 ES3.1 chips by default come with Efuse burnt * with parameters required for full functionality of From patchwork Thu Aug 5 22:24:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117572 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75Mfmth029707 for ; Thu, 5 Aug 2010 22:41:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760849Ab0HEWkw (ORCPT ); Thu, 5 Aug 2010 18:40:52 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:35502 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760833Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOJ6L004398 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:19 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o75MOGWD024047; Thu, 5 Aug 2010 17:24:16 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOFf27275; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 1D529C268; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 10/12] omap3: sr: export sr_dbg_dir Date: Thu, 5 Aug 2010 17:24:10 -0500 Message-Id: <1281047052-21346-11-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:41:50 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h index 1105db0..df58026 100644 --- a/arch/arm/plat-omap/include/plat/smartreflex.h +++ b/arch/arm/plat-omap/include/plat/smartreflex.h @@ -263,6 +263,11 @@ int omap_sr_register_class(struct omap_smartreflex_class_data *class_data); /* API to register the pmic specific data with the smartreflex driver. */ void omap_sr_register_pmic(struct omap_smartreflex_pmic_data *pmic_data); + +#ifdef CONFIG_PM_DEBUG +extern struct dentry *sr_dbg_dir; +#endif + #else static inline void omap_smartreflex_enable(int srid) {} static inline void omap_smartreflex_disable(int srid) {} From patchwork Thu Aug 5 22:24:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117573 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75Mfmti029707 for ; Thu, 5 Aug 2010 22:41:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934586Ab0HEWl2 (ORCPT ); Thu, 5 Aug 2010 18:41:28 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:47369 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760830Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOI5a023642 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:18 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o75MOFGJ028227; Thu, 5 Aug 2010 17:24:16 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOFf27287; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 231B2C26A; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 12/12] omap3: sr: class3: make class3_data static Date: Thu, 5 Aug 2010 17:24:12 -0500 Message-Id: <1281047052-21346-13-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:41:50 +0000 (UTC) diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c index f3b766f..530b2f0 100644 --- a/arch/arm/mach-omap2/smartreflex-class3.c +++ b/arch/arm/mach-omap2/smartreflex-class3.c @@ -47,7 +47,7 @@ static int sr_class3_configure(int id) } /* SR class3 structure */ -struct omap_smartreflex_class_data class3_data = { +static struct omap_smartreflex_class_data class3_data = { .enable = sr_class3_enable, .disable = sr_class3_disable, .configure = sr_class3_configure, From patchwork Tue Jul 13 10:24:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjeev Premi X-Patchwork-Id: 111780 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6DAQO9g027179 for ; Tue, 13 Jul 2010 10:26:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756760Ab0GMKYU (ORCPT ); Tue, 13 Jul 2010 06:24:20 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39714 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756719Ab0GMKYS (ORCPT ); Tue, 13 Jul 2010 06:24:18 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6DAOF0H024146 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 13 Jul 2010 05:24:17 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6DAOCuE015867; Tue, 13 Jul 2010 15:54:13 +0530 (IST) From: Sanjeev Premi To: linux-omap@vger.kernel.org Cc: Sanjeev Premi Subject: [PATCH] omap2: fix assorted compiler warnings Date: Tue, 13 Jul 2010 15:54:10 +0530 Message-Id: <1279016650-20459-1-git-send-email-premi@ti.com> X-Mailer: git-send-email 1.6.6.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 13 Jul 2010 10:26:25 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index c03d1d5..96f5bbb 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -274,8 +274,6 @@ static int __init omap4_panda_i2c_init(void) } static void __init omap4_panda_init(void) { - int status; - omap4_panda_i2c_init(); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index ab403b2..2ffacc1 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -87,7 +87,7 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; - struct omap_mux *gpio_mux; + struct omap_mux *gpio_mux=NULL; u16 old_mode; u16 mux_mode; int found = 0; diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 9b7e354..831e6bc 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2082,7 +2082,7 @@ void omap2_gpio_prepare_for_idle(int power_state) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l1, l2; + u32 l1=0, l2=0; if (bank->dbck_enable_mask) clk_disable(bank->dbck); @@ -2149,7 +2149,7 @@ void omap2_gpio_resume_after_idle(void) min = 1; for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l, gen, gen0, gen1; + u32 l=0, gen, gen0, gen1; if (bank->dbck_enable_mask) clk_enable(bank->dbck); From patchwork Tue Aug 3 11:56:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo Serra X-Patchwork-Id: 116733 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o73BuTTr009958 for ; Tue, 3 Aug 2010 11:56:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756083Ab0HCL41 (ORCPT ); Tue, 3 Aug 2010 07:56:27 -0400 Received: from mail-ww0-f44.google.com ([74.125.82.44]:39296 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753016Ab0HCL4Y (ORCPT ); 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Tue, 03 Aug 2010 04:56:23 -0700 (PDT) From: Enric Balletbo i Serra To: linux-omap@vger.kernel.org Cc: Enric Balletbo i Serra , Enric Balletbo i Serra Subject: [PATCH 2/4] omap3: configure GPIO's for external VBUS power switch and overcurrent detect on IGEP v2 board. Date: Tue, 3 Aug 2010 13:56:12 +0200 Message-Id: <1280836574-32467-3-git-send-email-eballetbo@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> References: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 03 Aug 2010 11:56:30 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 6b5f9c8..d88fc08 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -285,6 +285,16 @@ static int igep2_twl_gpio_setup(struct device *dev, igep2_vmmc1_supply.dev = mmc[0].dev; igep2_vmmc2_supply.dev = mmc[1].dev; + /* REVISIT: need ehci-omap hooks for external VBUS + * power switch and overcurrent detect + */ + gpio_request(gpio + 1, "GPIO_EHCI_NOC"); + gpio_direction_input(gpio + 1); + + /* TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN (out, active low) */ + gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USB_CPEN"); + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + return 0; }; From patchwork Thu Jun 17 15:27:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 106698 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HFSNBB025429 for ; Thu, 17 Jun 2010 15:29:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756282Ab0FQP2U (ORCPT ); Thu, 17 Jun 2010 11:28:20 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:55585 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753963Ab0FQP2T (ORCPT ); Thu, 17 Jun 2010 11:28:19 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HFRMOW002955 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 10:27:29 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o5HFRGtK015763; Thu, 17 Jun 2010 10:27:17 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099945); by dbdmail.itg.ti.com with HTTP; Thu, 17 Jun 2010 20:57:19 +0530 (IST) Message-ID: <43584.10.24.255.17.1276788439.squirrel@dbdmail.itg.ti.com> Date: Thu, 17 Jun 2010 20:57:19 +0530 (IST) Subject: [PATCH v5 2/2] OMAP4 HSMMC: Adding card detect support for MMC1 Controller From: "kishore kadiyala" To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: tony@atomide.com, madhu.cr@ti.com, akpm@linux-foundation.org, adrian.hunter@nokia.com User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 15:29:35 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index e4a5d66..1cf6f3b 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -144,6 +144,7 @@ static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 8, + .cd_type = NON_GPIO, .gpio_wp = -EINVAL, }, { @@ -174,10 +175,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) struct platform_device, dev); struct omap_mmc_platform_data *pdata = dev->platform_data; - /* Setting MMC1 Card detect Irq */ - if (pdev->id == 0) + /* MMC1 Card detect Configuration */ + if (pdev->id == 0) { + ret = omap4_hsmmc1_card_detect_config(); + if (ret < 0) + pr_err("Unable to configure Card detect for MMC1\n"); pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + - MMCDETECT_INTR_OFFSET; + MMCDETECT_INTR_OFFSET; + } return ret; } diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 1ef54b0..8a8f7b1 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -265,6 +265,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) mmc->get_context_loss_count = hsmmc_get_context_loss; mmc->slots[0].switch_pin = c->gpio_cd; + mmc->slots[0].cd_type = c->cd_type; mmc->slots[0].gpio_wp = c->gpio_wp; mmc->slots[0].remux = c->remux; diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index ed60c0f..cd42c77 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -14,6 +14,7 @@ #include #include #include +#include #include diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c index 10bf228..f17e4e7 100644 --- a/drivers/mfd/twl6030-irq.c +++ b/drivers/mfd/twl6030-irq.c @@ -223,6 +223,29 @@ int twl6030_interrupt_mask(u8 bit_mask, u8 offset) } EXPORT_SYMBOL(twl6030_interrupt_mask); +int twl6030_mmc_card_detect(int host_id, int slot) +{ + int ret = -ENOSYS; + u8 read_reg; + + switch (host_id) { + case 0: + /* + * BIT0 of REG_MMC_CTRL + * 0 - Card not present ,1 - Card present + */ + ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, + &read_reg, TWL6030_MMCCTRL); + if (ret >= 0) + ret = read_reg & STS_MMC; + break; + default: + pr_err("Unkown MMC controller %d in %s\n", host_id, __func__); + } + return ret; +} +EXPORT_SYMBOL(twl6030_mmc_card_detect); + int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) { diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b032828..5d5bd29 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -189,9 +189,16 @@ struct omap_hsmmc_host { static int omap_hsmmc_card_detect(struct device *dev, int slot) { struct omap_mmc_platform_data *mmc = dev->platform_data; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + int ret = -ENOSYS; - /* NOTE: assumes card detect signal is active-low */ - return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); + if (mmc->slots[0].cd_type == GPIO) + /* NOTE: assumes card detect signal is active-low */ + ret = !gpio_get_value_cansleep(mmc->slots[0].switch_pin); + else + ret = twl6030_mmc_card_detect(pdev->id, slot); + return ret; } static int omap_hsmmc_get_wp(struct device *dev, int slot) @@ -464,8 +471,6 @@ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) int ret; if (gpio_is_valid(pdata->slots[0].switch_pin)) { - pdata->suspend = omap_hsmmc_suspend_cdirq; - pdata->resume = omap_hsmmc_resume_cdirq; if (pdata->slots[0].cover) pdata->slots[0].get_cover_state = omap_hsmmc_get_cover_state; @@ -504,6 +509,15 @@ err_free_sp: return ret; } +static int omap_hsmmc_non_gpio_init(struct omap_mmc_platform_data *pdata) +{ + if (pdata->slots[0].switch_pin > 0) { + pdata->slots[0].card_detect = omap_hsmmc_card_detect; + pdata->slots[0].card_detect_irq = pdata->slots[0].switch_pin; + } + return 0; +} + static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) { if (gpio_is_valid(pdata->slots[0].gpio_wp)) @@ -1988,7 +2002,11 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) if (res == NULL) return -EBUSY; - ret = omap_hsmmc_gpio_init(pdata); + if (pdata->slots[0].cd_type == GPIO) + ret = omap_hsmmc_gpio_init(pdata); + else + ret = omap_hsmmc_non_gpio_init(pdata); + if (ret) goto err; @@ -2170,6 +2188,8 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) "Unable to grab MMC CD IRQ\n"); goto err_irq_cd; } + pdata->suspend = omap_hsmmc_suspend_cdirq; + pdata->resume = omap_hsmmc_resume_cdirq; } omap_hsmmc_disable_irq(host); diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 6de90bf..38ef529 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -141,6 +141,14 @@ #define TWL6030_CHARGER_CTRL_INT_MASK 0x10 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60 +#define TWL6030_MMCCTRL 0xEE +#define VMMC_AUTO_OFF (0x1 << 3) +#define SW_FC (0x1 << 2) +#define STS_MMC 0x1 + +#define TWL6030_CFG_INPUT_PUPD3 0xF2 +#define MMC_PU (0x1 << 3) +#define MMC_PD (0x1 << 2) #define TWL4030_CLASS_ID 0x4030 #define TWL6030_CLASS_ID 0x6030 @@ -173,6 +181,44 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); int twl6030_interrupt_mask(u8 bit_mask, u8 offset); +/* MMC1 Controller on OMAP4 uses Phoenix Irq for Card detect */ +int twl6030_mmc_card_detect(int host_id, int slot); + +/* Configuring Card Detect for MMC1 */ +static inline int omap4_hsmmc1_card_detect_config(void) +{ + int res = -1; + u8 reg_val = 0; + + /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */ + if (twl_class_is_6030()) { + twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, + REG_INT_MSK_LINE_B); + twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, + REG_INT_MSK_STS_B); + } + + /* + * Intially Configuring MMC_CTRL for receving interrupts & + * Card status on TWL6030 for MMC1 + */ + res = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL); + if (res < 0) + return res; + reg_val &= ~VMMC_AUTO_OFF; + reg_val |= SW_FC; + twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL); + + /* Configuring CFG_INPUT_PUPD3 */ + res = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, + TWL6030_CFG_INPUT_PUPD3); + if (res < 0) + return res; + reg_val &= ~(MMC_PU | MMC_PD); + twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_CFG_INPUT_PUPD3); + return res; +} + /*----------------------------------------------------------------------*/ /* From patchwork Tue Aug 3 11:56:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo Serra X-Patchwork-Id: 116735 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o73BuTTt009958 for ; Tue, 3 Aug 2010 11:56:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756108Ab0HCL4b (ORCPT ); Tue, 3 Aug 2010 07:56:31 -0400 Received: from mail-ww0-f44.google.com ([74.125.82.44]:45985 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756006Ab0HCL40 (ORCPT ); Tue, 3 Aug 2010 07:56:26 -0400 Received: by mail-ww0-f44.google.com with SMTP id 40so5028712wwj.1 for ; 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Tue, 03 Aug 2010 04:56:24 -0700 (PDT) From: Enric Balletbo i Serra To: linux-omap@vger.kernel.org Cc: Enric Balletbo i Serra , Enric Balletbo i Serra Subject: [PATCH 3/4] omap3: fix and improve the LED handling on IGEP v2 board. Date: Tue, 3 Aug 2010 13:56:13 +0200 Message-Id: <1280836574-32467-4-git-send-email-eballetbo@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> References: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 03 Aug 2010 11:56:32 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d88fc08..6868dda 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -272,6 +272,54 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include + +static struct gpio_led igep2_gpio_leds[] = { + [0] = { + .name = "led0:red", + .gpio = IGEP2_GPIO_LED0_RED, + .default_trigger = "default-off", + }, + [1] = { + .name = "led0:green", + .gpio = IGEP2_GPIO_LED0_GREEN, + .default_trigger = "default-off", + }, + [2] = { + .name = "led1:red", + .gpio = IGEP2_GPIO_LED1_RED, + .default_trigger = "default-off", + }, + [3] = { + .name = "led1:green", + .default_trigger = "heartbeat", + .gpio = -EINVAL, /* gets replaced */ + }, +}; + +static struct gpio_led_platform_data igep2_led_pdata = { + .leds = igep2_gpio_leds, + .num_leds = ARRAY_SIZE(igep2_gpio_leds), +}; + +static struct platform_device igep2_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep2_led_pdata, + }, +}; + +static void __init igep2_init_led(void) +{ + platform_device_register(&igep2_led_device); +} + +#else +static inline void igep2_init_led(void) {} +#endif + static int igep2_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -295,6 +343,18 @@ static int igep2_twl_gpio_setup(struct device *dev, gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USB_CPEN"); gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + if ((gpio_request(gpio + TWL4030_GPIO_MAX + 1, "led1:green") == 0) && + (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { + gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); + gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n"); +#else + igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + return 0; }; @@ -302,7 +362,7 @@ static struct twl4030_gpio_platform_data igep2_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = false, + .use_leds = true, .setup = igep2_twl_gpio_setup, }; @@ -376,47 +436,6 @@ static void __init igep2_display_init(void) pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n"); } -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -#include - -static struct gpio_led igep2_gpio_leds[] = { - { - .name = "led0:red", - .gpio = IGEP2_GPIO_LED0_RED, - }, - { - .name = "led0:green", - .default_trigger = "heartbeat", - .gpio = IGEP2_GPIO_LED0_GREEN, - }, - { - .name = "led1:red", - .gpio = IGEP2_GPIO_LED1_RED, - }, -}; - -static struct gpio_led_platform_data igep2_led_pdata = { - .leds = igep2_gpio_leds, - .num_leds = ARRAY_SIZE(igep2_gpio_leds), -}; - -static struct platform_device igep2_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &igep2_led_pdata, - }, -}; - -static void __init igep2_init_led(void) -{ - platform_device_register(&igep2_led_device); -} - -#else -static inline void igep2_init_led(void) {} -#endif - static struct platform_device *igep2_devices[] __initdata = { &igep2_dss_device, }; From patchwork Tue Aug 3 11:56:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo Serra X-Patchwork-Id: 116734 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o73BuTTs009958 for ; Tue, 3 Aug 2010 11:56:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755971Ab0HCL43 (ORCPT ); Tue, 3 Aug 2010 07:56:29 -0400 Received: from mail-ww0-f44.google.com ([74.125.82.44]:45985 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756021Ab0HCL4X (ORCPT ); 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Tue, 03 Aug 2010 04:56:21 -0700 (PDT) From: Enric Balletbo i Serra To: linux-omap@vger.kernel.org Cc: Enric Balletbo i Serra , Enric Balletbo i Serra Subject: [PATCH 1/4] omap3: GPIO's for W-LAN + Bluetooth combo depends on IGEP v2 hardware revision. Date: Tue, 3 Aug 2010 13:56:11 +0200 Message-Id: <1280836574-32467-2-git-send-email-eballetbo@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> References: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 03 Aug 2010 11:56:31 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d55c57b..6b5f9c8 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -42,8 +42,19 @@ #define IGEP2_GPIO_LED0_RED 27 #define IGEP2_GPIO_LED1_RED 28 #define IGEP2_GPIO_DVI_PUP 170 -#define IGEP2_GPIO_WIFI_NPD 94 -#define IGEP2_GPIO_WIFI_NRESET 95 + +/* HIGH : It is a rev. B or C (B-compatible) board + LOW : It is a rev. C (B-NON compatible) board */ +#define IGEP2_GPIO_HW_REV 28 + +/* Platform: IGEP v2 Hw Rev. B / C (B-compatible) */ +#define IGEP2_RB_GPIO_WIFI_NPD 94 +#define IGEP2_RB_GPIO_WIFI_NRESET 95 +#define IGEP2_RB_GPIO_BT_NRESET 137 +/* Platform: IGEP v2 Hw Rev. C (B-non compatible) */ +#define IGEP2_RC_GPIO_WIFI_NPD 138 +#define IGEP2_RC_GPIO_WIFI_NRESET 139 +#define IGEP2_RC_GPIO_BT_NRESET 137 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) @@ -476,8 +487,66 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +static int igep2_get_hw_rev(void) +{ + int ret = -1; + + if ((gpio_request(IGEP2_GPIO_HW_REV, "GPIO_HW_REV") == 0) && + (gpio_direction_input(IGEP2_GPIO_HW_REV) == 0)) + ret = gpio_get_value(IGEP2_GPIO_HW_REV); + else + pr_warning("IGEP v2: Could not obtain gpio GPIO_HW_REV\n"); + + gpio_free(IGEP2_GPIO_HW_REV); + + return ret; +} + +static void __init igep2_init_wifi_bt(void) +{ + int hwrev; + unsigned npd, wreset, btreset; + + hwrev = igep2_get_hw_rev(); + + /* GPIO's for W-LAN + Bluetooth combo depends on hardware revision */ + if (hwrev) { + npd = IGEP2_RB_GPIO_WIFI_NPD; + wreset = IGEP2_RB_GPIO_WIFI_NRESET; + btreset = IGEP2_RB_GPIO_BT_NRESET; + } else { + npd = IGEP2_RC_GPIO_WIFI_NPD; + wreset = IGEP2_RC_GPIO_WIFI_NRESET; + btreset = IGEP2_RC_GPIO_BT_NRESET; + } + + /* Set GPIO's for W-LAN + Bluetooth combo module */ + if ((gpio_request(npd, "GPIO_WIFI_NPD") == 0) && + (gpio_direction_output(npd, 1) == 0)) { + gpio_export(npd, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n"); + + if ((gpio_request(wreset, "GPIO_WIFI_NRESET") == 0) && + (gpio_direction_output(wreset, 1) == 0)) { + gpio_export(wreset, 0); + gpio_set_value(wreset, 0); + udelay(10); + gpio_set_value(wreset, 1); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); + + if ((gpio_request(btreset, "GPIO_BT_NRESET") == 0) && + (gpio_direction_output(btreset, 1) == 0)) { + gpio_export(btreset, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_BT_NRESET\n"); +} + static void __init igep2_init(void) { + int hwrev; + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); igep2_i2c_init(); platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); @@ -485,10 +554,19 @@ static void __init igep2_init(void) usb_musb_init(&musb_board_data); usb_ehci_init(&ehci_pdata); + hwrev = igep2_get_hw_rev(); + if (hwrev == 0) + pr_info("IGEP platform: IGEP v2 Hw Rev. C (B-NON compatible)\n"); + else if (hwrev == 1) + pr_info("IGEP platform: IGEP v2 Hw Rev. B/C (B compatible)\n"); + else + pr_err("IGEP platform: Unknow\n"); + igep2_flash_init(); igep2_init_led(); igep2_display_init(); igep2_init_smsc911x(); + igep2_init_wifi_bt(); /* GPIO userspace leds */ #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) @@ -513,23 +591,6 @@ static void __init igep2_init(void) } else pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); #endif - - /* GPIO W-LAN + Bluetooth combo module */ - if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && - (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) { - gpio_export(IGEP2_GPIO_WIFI_NPD, 0); -/* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */ - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n"); - - if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && - (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) { - gpio_export(IGEP2_GPIO_WIFI_NRESET, 0); - gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0); - udelay(10); - gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); } static void __init igep2_map_io(void) From patchwork Wed May 5 14:27:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97102 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5P6002693 for ; Wed, 5 May 2010 14:28:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934647Ab0EEO2A (ORCPT ); Wed, 5 May 2010 10:28:00 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34092 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934673Ab0EEO15 (ORCPT ); Wed, 5 May 2010 10:27:57 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERs3H005616; Wed, 5 May 2010 09:27:56 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:54 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:54 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfR9016232; Wed, 5 May 2010 17:27:52 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 07/21] OMAP: DSS2: Taal: Remove ESD work cancel from driver probe error handling Date: Wed, 5 May 2010 17:27:27 +0300 Message-Id: <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:54.0258 (UTC) FILETIME=[26542F20:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:06 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 788aa91..d0701e2 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -627,7 +627,6 @@ err4: err3: backlight_device_unregister(bldev); err2: - cancel_delayed_work_sync(&td->esd_work); destroy_workqueue(td->esd_wq); err1: kfree(td); From patchwork Tue Aug 3 11:56:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo Serra X-Patchwork-Id: 116736 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o73BuTTu009958 for ; Tue, 3 Aug 2010 11:56:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756136Ab0HCL4c (ORCPT ); Tue, 3 Aug 2010 07:56:32 -0400 Received: from mail-ww0-f44.google.com ([74.125.82.44]:39296 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756052Ab0HCL42 (ORCPT ); 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Tue, 03 Aug 2010 04:56:26 -0700 (PDT) From: Enric Balletbo i Serra To: linux-omap@vger.kernel.org Cc: Enric Balletbo i Serra Subject: [PATCH 4/4] omap3: Add minimal OMAP3 IGEP module support. Date: Tue, 3 Aug 2010 13:56:14 +0200 Message-Id: <1280836574-32467-5-git-send-email-eballetbo@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> References: <1280836574-32467-1-git-send-email-eballetbo@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 03 Aug 2010 11:56:33 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b31b6f1..db8bd18 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -142,6 +142,11 @@ config MACH_IGEP0020 depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB +config MACH_IGEP0030 + bool "IGEP OMAP3 module" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + config MACH_SBC3530 bool "OMAP3 SBC STALKER board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ea52b03..fab0222 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -136,6 +136,8 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ hsmmc.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o +obj-$(CONFIG_MACH_IGEP0030) += board-igep0030.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c new file mode 100644 index 0000000..936bf98 --- /dev/null +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -0,0 +1,436 @@ +/* + * Copyright (C) 2010 Integration Software and Electronic Engineering. + * + * Modified from mach-omap2/board-generic.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "mux.h" +#include "hsmmc.h" +#include "sdram-numonyx-m65kxxxxam.h" + +#define IGEP3_GPIO_LED0_GREEN 54 +#define IGEP3_GPIO_LED0_RED 53 +#define IGEP3_GPIO_LED1_RED 16 + +#define IGEP3_GPIO_WIFI_NPD 138 +#define IGEP3_GPIO_WIFI_NRESET 139 +#define IGEP3_GPIO_BT_NRESET 137 + +#define IGEP3_GPIO_USBH_NRESET 115 + + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) + +#define ONENAND_MAP 0x20000000 + +/* x2 Flash built-in COMBO POP MEMORY + * Since the device is equipped with two DataRAMs, and two-plane NAND + * Flash memory array, these two component enables simultaneous program + * of 4KiB. Plane1 has only even blocks such as block0, block2, block4 + * while Plane2 has only odd blocks such as block1, block3, block5. + * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048) + */ + +static struct mtd_partition igep3_onenand_partitions[] = { + { + .name = "X-Loader", + .offset = 0, + .size = 2 * (64*(2*2048)) + }, + { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = 6 * (64*(2*2048)), + }, + { + .name = "Environment", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64*(2*2048)), + }, + { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, + .size = 12 * (64*(2*2048)), + }, + { + .name = "File System", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static int igep3_onenand_setup(void __iomem *onenand_base, int freq) +{ + /* nothing is required to be setup for onenand as of now */ + return 0; +} + +static struct omap_onenand_platform_data igep3_onenand_data = { + .parts = igep3_onenand_partitions, + .nr_parts = ARRAY_SIZE(igep3_onenand_partitions), + .onenand_setup = igep3_onenand_setup, + .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ +}; + +static struct platform_device igep3_onenand_device = { + .name = "omap2-onenand", + .id = -1, + .dev = { + .platform_data = &igep3_onenand_data, + }, +}; + +void __init igep3_flash_init(void) +{ + u8 cs = 0; + u8 onenandcs = GPMC_CS_NUM + 1; + + while (cs < GPMC_CS_NUM) { + u32 ret = 0; + ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + + /* Check if NAND/oneNAND is configured */ + if ((ret & 0xC00) == 0x800) + /* NAND found */ + pr_err("IGEP: Unsupported NAND found\n"); + else { + ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + if ((ret & 0x3F) == (ONENAND_MAP >> 24)) + /* ONENAND found */ + onenandcs = cs; + } + cs++; + } + if (onenandcs > GPMC_CS_NUM) { + pr_err("IGEP: Unable to find configuration in GPMC\n"); + return; + } + + if (onenandcs < GPMC_CS_NUM) { + igep3_onenand_data.cs = onenandcs; + if (platform_device_register(&igep3_onenand_device) < 0) + pr_err("IGEP: Unable to register OneNAND device\n"); + } +} + +#else +void __init igep3_flash_init(void) {} +#endif + +static struct omap_board_config_kernel igep3_config[] __initdata = { +}; + +static struct regulator_consumer_supply igep3_vmmc1_supply = { + .supply = "vmmc", +}; + +static struct regulator_consumer_supply igep3_vmmc2_supply = { + .supply = "vmmc", +}; + +/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +static struct regulator_init_data igep3_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep3_vmmc1_supply, +}; + +/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */ +static struct regulator_init_data igep3_vmmc2 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep3_vmmc2_supply, +}; + +static struct omap2_hsmmc_info mmc[] = { + [0] = { + .mmc = 1, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + [1] = { + .mmc = 2, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include + +static struct gpio_led igep3_gpio_leds[] = { + [0] = { + .name = "led0:red", + .gpio = IGEP3_GPIO_LED0_RED, + .default_trigger = "default-off", + .active_low = true, + }, + [1] = { + .name = "led0:green", + .gpio = IGEP3_GPIO_LED0_GREEN, + .default_trigger = "default-off", + .active_low = true, + }, + [2] = { + .name = "led1:red", + .gpio = IGEP3_GPIO_LED1_RED, + .default_trigger = "default-off", + .active_low = true, + }, + [3] = { + .name = "led1:green", + .default_trigger = "heartbeat", + .gpio = -EINVAL, /* gets replaced */ + .active_low = true, + }, +}; + +static struct gpio_led_platform_data igep3_led_pdata = { + .leds = igep3_gpio_leds, + .num_leds = ARRAY_SIZE(igep3_gpio_leds), +}; + +static struct platform_device igep3_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep3_led_pdata, + }, +}; + +static void __init igep3_init_led(void) +{ + platform_device_register(&igep3_led_device); +} + +#else +static inline void igep3_init_led(void) +{ + if ((gpio_request(IGEP3_GPIO_LED0_RED, "led0:red") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED0_RED, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED0_RED, 0); + gpio_set_value(IGEP3_GPIO_LED0_RED, 1); + } else + pr_warning("IGEP: Could not obtain gpio GPIO_LED0_RED\n"); + + if ((gpio_request(IGEP3_GPIO_LED0_GREEN, "led0:green") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED0_GREEN, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED0_GREEN, 0); + gpio_set_value(IGEP3_GPIO_LED0_GREEN, 1); + } else + pr_warning("IGEP: Could not obtain gpio GPIO_LED0_GREEN\n"); + + if ((gpio_request(IGEP3_GPIO_LED1_RED, "led1:red") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED1_RED, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED1_RED, 0); + gpio_set_value(IGEP3_GPIO_LED1_RED, 1); + } else + pr_warning("IGEP: Could not obtain gpio GPIO_LED1_RED\n"); +} +#endif + +static int igep3_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + mmc[0].gpio_cd = gpio + 0; + omap2_hsmmc_init(mmc); + + /* link regulators to MMC adapters ... we "know" the + * regulators will be set up only *after* we return. + */ + igep3_vmmc1_supply.dev = mmc[0].dev; + igep3_vmmc2_supply.dev = mmc[1].dev; + + /* REVISIT: need ehci-omap hooks for external VBUS + * power switch and overcurrent detect + */ + gpio_request(gpio + 1, "GPIO_EHCI_NOC"); + gpio_direction_input(gpio + 1); + + /* TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN (out, active low) */ + gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USB_CPEN"); + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + if ((gpio_request(gpio + TWL4030_GPIO_MAX + 1, "led1:green") == 0) && + (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { + gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); + gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); + } else + pr_warning("IGEP: Could not obtain gpio GPIO_LED1_GREEN\n"); +#else + igep3_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + + return 0; +}; + +static struct twl4030_gpio_platform_data igep3_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, + .setup = igep3_twl_gpio_setup, +}; + +static struct twl4030_usb_data igep3_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + +static void __init igep3_init_irq(void) +{ + omap_board_config = igep3_config; + omap_board_config_size = ARRAY_SIZE(igep3_config); + omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); + omap_init_irq(); + omap_gpio_init(); +} + +static struct twl4030_platform_data igep3_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .usb = &igep3_usb_data, + .gpio = &igep3_gpio_data, + .vmmc1 = &igep3_vmmc1, + .vmmc2 = &igep3_vmmc2, +}; + +static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &igep3_twldata, + }, +}; + +static int __init igep3_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, igep3_i2c_boardinfo, + ARRAY_SIZE(igep3_i2c_boardinfo)); + + return 0; +} + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 100, +}; + +static void __init igep3_init_wifi_bt(void) +{ + /* Configure MUX values for W-LAN + Bluetooth GPIO's */ + omap_mux_init_gpio(IGEP3_GPIO_WIFI_NPD, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(IGEP3_GPIO_WIFI_NRESET, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(IGEP3_GPIO_BT_NRESET, OMAP_PIN_OUTPUT); + + /* Set GPIO's for W-LAN + Bluetooth combo module */ + if ((gpio_request(IGEP3_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && + (gpio_direction_output(IGEP3_GPIO_WIFI_NPD, 1) == 0)) { + gpio_export(IGEP3_GPIO_WIFI_NPD, 0); + } else + pr_warning("IGEP: Could not obtain gpio GPIO_WIFI_NPD\n"); + + if ((gpio_request(IGEP3_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && + (gpio_direction_output(IGEP3_GPIO_WIFI_NRESET, 1) == 0)) { + gpio_export(IGEP3_GPIO_WIFI_NRESET, 0); + gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 0); + udelay(10); + gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 1); + } else + pr_warning("IGEP: Could not obtain gpio GPIO_WIFI_NRESET\n"); + + if ((gpio_request(IGEP3_GPIO_BT_NRESET, "GPIO_BT_NRESET") == 0) && + (gpio_direction_output(IGEP3_GPIO_BT_NRESET, 1) == 0)) { + gpio_export(IGEP3_GPIO_BT_NRESET, 0); + } else + pr_warning("IGEP: Could not obtain gpio GPIO_BT_NRESET\n"); +} + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + +static void __init igep3_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + omap_serial_init(); + usb_musb_init(&musb_board_data); + + igep3_i2c_init(); + igep3_flash_init(); + igep3_init_wifi_bt(); + igep3_init_led(); +} + +static void __init igep3_map_io(void) +{ + omap2_set_globals_343x(); + omap34xx_map_common_io(); +} + +MACHINE_START(IGEP0030, "IGEP OMAP3 module") + .phys_io = 0x48000000, + .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = igep3_map_io, + .init_irq = igep3_init_irq, + .init_machine = igep3_init, + .timer = &omap_timer, +MACHINE_END From patchwork Tue Jul 6 04:03:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 110350 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6643J0f020438 for ; Tue, 6 Jul 2010 04:03:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750730Ab0GFEDS (ORCPT ); Tue, 6 Jul 2010 00:03:18 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:58116 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750721Ab0GFEDS (ORCPT ); Tue, 6 Jul 2010 00:03:18 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6643C2X031044 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 5 Jul 2010 23:03:12 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6643AZJ010044; Mon, 5 Jul 2010 23:03:10 -0500 (CDT) Received: from localhost (omaplbp.india.ti.com [172.24.190.217]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o66438P22419; Mon, 5 Jul 2010 23:03:08 -0500 (CDT) From: Archit Taneja To: tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Archit Taneja Subject: [PATCH] Replace strncmp() with sysfs_streq() in overlay_manager_store() Date: Tue, 6 Jul 2010 09:33:06 +0530 Message-Id: <1278388986-8324-1-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.5.4.7 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 06 Jul 2010 04:03:19 +0000 (UTC) diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 8233658..244dca8 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -65,7 +65,7 @@ static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf, for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { mgr = omap_dss_get_overlay_manager(i); - if (strncmp(buf, mgr->name, len) == 0) + if (sysfs_streq(buf, mgr->name)) break; mgr = NULL; From patchwork Mon May 3 21:41:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 96569 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o43LfFol016444 for ; Mon, 3 May 2010 21:41:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756747Ab0ECVlS (ORCPT ); Mon, 3 May 2010 17:41:18 -0400 Received: from mail-px0-f174.google.com ([209.85.212.174]:45892 "EHLO mail-px0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756680Ab0ECVlS (ORCPT ); Mon, 3 May 2010 17:41:18 -0400 Received: by pxi5 with SMTP id 5so454018pxi.19 for ; Mon, 03 May 2010 14:41:17 -0700 (PDT) Received: by 10.142.67.38 with SMTP id p38mr5066539wfa.167.1272922877053; Mon, 03 May 2010 14:41:17 -0700 (PDT) Received: from localhost (deeprootsystems.com [216.254.16.51]) by mx.google.com with ESMTPS id 22sm4974866pzk.5.2010.05.03.14.41.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 03 May 2010 14:41:15 -0700 (PDT) From: Kevin Hilman To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Tero Kristo Subject: [PATCH 1/3] OMAP3: Serial: Improved sleep logic Date: Mon, 3 May 2010 14:41:09 -0700 Message-Id: <1272922871-18847-2-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.7.0.2 In-Reply-To: <1272922871-18847-1-git-send-email-khilman@deeprootsystems.com> References: <1272922871-18847-1-git-send-email-khilman@deeprootsystems.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 21:41:19 +0000 (UTC) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 3771254..b709cf8 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -49,7 +50,10 @@ struct omap_uart_state { int num; int can_sleep; struct timer_list timer; + struct timer_list garbage_timer; + struct work_struct wakeup_work; u32 timeout; + u8 garbage_ignore; void __iomem *wk_st; void __iomem *wk_en; @@ -239,6 +243,11 @@ static inline void omap_uart_save_context(struct omap_uart_state *uart) {} static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ +#ifdef CONFIG_PM +static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, + int enable); +#endif + static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) { if (uart->clocked) @@ -248,6 +257,9 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) clk_enable(uart->fck); uart->clocked = 1; omap_uart_restore_context(uart); +#ifdef CONFIG_PM + omap_uart_smart_idle_enable(uart, 0); +#endif } #ifdef CONFIG_PM @@ -259,8 +271,13 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) omap_uart_save_context(uart); uart->clocked = 0; + omap_uart_smart_idle_enable(uart, 1); clk_disable(uart->ick); clk_disable(uart->fck); + if (uart->garbage_ignore) { + del_timer(&uart->garbage_timer); + uart->garbage_ignore = 0; + } } static void omap_uart_enable_wakeup(struct omap_uart_state *uart) @@ -316,7 +333,6 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart) { omap_uart_enable_clocks(uart); - omap_uart_smart_idle_enable(uart, 0); uart->can_sleep = 0; if (uart->timeout) mod_timer(&uart->timer, jiffies + uart->timeout); @@ -334,7 +350,6 @@ static void omap_uart_allow_sleep(struct omap_uart_state *uart) if (!uart->clocked) return; - omap_uart_smart_idle_enable(uart, 1); uart->can_sleep = 1; del_timer(&uart->timer); } @@ -346,18 +361,46 @@ static void omap_uart_idle_timer(unsigned long data) omap_uart_allow_sleep(uart); } +static void omap_uart_garbage_timer(unsigned long data) +{ + struct omap_uart_state *uart = (struct omap_uart_state *)data; + + uart->garbage_ignore = 0; +} + +static void omap_uart_wakeup_work(struct work_struct *work) +{ + struct omap_uart_state *uart = + container_of(work, struct omap_uart_state, wakeup_work); + + omap_uart_block_sleep(uart); + + /* Set up garbage timer to ignore RX during first jiffy */ + if (uart->timeout) + mod_timer(&uart->garbage_timer, jiffies + 1); +} + void omap_uart_prepare_idle(int num) { struct omap_uart_state *uart; list_for_each_entry(uart, &uart_list, node) { if (num == uart->num && uart->can_sleep) { - omap_uart_disable_clocks(uart); + if (serial_read_reg(uart->p, UART_LSR) & + UART_LSR_TEMT) + omap_uart_disable_clocks(uart); return; } } } +static void serial_wakeup(struct omap_uart_state *uart) +{ + if (uart->timeout) + uart->garbage_ignore = 1; + schedule_work(&uart->wakeup_work); +} + void omap_uart_resume_idle(int num) { struct omap_uart_state *uart; @@ -371,12 +414,12 @@ void omap_uart_resume_idle(int num) u16 p = omap_ctrl_readw(uart->padconf); if (p & OMAP3_PADCONF_WAKEUPEVENT0) - omap_uart_block_sleep(uart); + serial_wakeup(uart); } /* Check for normal UART wakeup */ if (__raw_readl(uart->wk_st) & uart->wk_mask) - omap_uart_block_sleep(uart); + serial_wakeup(uart); return; } } @@ -425,7 +468,14 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) { struct omap_uart_state *uart = dev_id; - omap_uart_block_sleep(uart); + /* Check for receive interrupt */ + while (serial_read_reg(uart->p, UART_LSR) & UART_LSR_DR) { + omap_uart_block_sleep(uart); + if (uart->garbage_ignore) + serial_read_reg(uart->p, UART_RX); + else + break; + } return IRQ_NONE; } @@ -439,6 +489,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) uart->timeout = DEFAULT_TIMEOUT; setup_timer(&uart->timer, omap_uart_idle_timer, (unsigned long) uart); + setup_timer(&uart->garbage_timer, omap_uart_garbage_timer, + (unsigned long) uart); + INIT_WORK(&uart->wakeup_work, omap_uart_wakeup_work); if (uart->timeout) mod_timer(&uart->timer, jiffies + uart->timeout); omap_uart_smart_idle_enable(uart, 0); @@ -503,15 +556,13 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) void omap_uart_enable_irqs(int enable) { - int ret; struct omap_uart_state *uart; list_for_each_entry(uart, &uart_list, node) { if (enable) - ret = request_irq(uart->p->irq, omap_uart_interrupt, - IRQF_SHARED, "serial idle", (void *)uart); + enable_irq(uart->p->irq); else - free_irq(uart->p->irq, (void *)uart); + disable_irq(uart->p->irq); } } From patchwork Sat Jul 10 02:24:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111198 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Skti002447 for ; Sat, 10 Jul 2010 02:28:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754613Ab0GJCZr (ORCPT ); Fri, 9 Jul 2010 22:25:47 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:45789 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753579Ab0GJCZb (ORCPT ); Fri, 9 Jul 2010 22:25:31 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PH38025256 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:17 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PGku009247; Fri, 9 Jul 2010 21:25:16 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68Q021595; Fri, 9 Jul 2010 21:25:16 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 14/15] staging:ti dspbridge: Rename words with camel case Date: Fri, 9 Jul 2010 21:24:08 -0500 Message-Id: <1278728649-21012-15-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-14-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> <1278728649-21012-10-git-send-email-rene.sapiens@ti.com> <1278728649-21012-11-git-send-email-rene.sapiens@ti.com> <1278728649-21012-12-git-send-email-rene.sapiens@ti.com> <1278728649-21012-13-git-send-email-rene.sapiens@ti.com> <1278728649-21012-14-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:51 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== validBit to valid_bit victimEntryNum to victim_entry_num virtualAddr to virtual_addr xType to xtype actualValue to actual_value EASIL1_MMUMMU_IRQSTATUSReadRegister32 to easil1_mmummu_irqstatus_read_register32 EASIL1_MMUMMU_LOCKBaseValueWrite32 to easil1_mmummu_lock_base_value_write32 easiNum to easi_num expectedValue to expected_value invalidValue to invalid_value L1_base to l1_base L2_base to l2_base lower16Bits to lower16_bits lower8Bits to lower8_bits lowerMiddle8Bits to lower_middle8_bits lowerUpper8Bits to lower_upper8_bits maxValidValue to max_valid_value minValidValue to min_valid_value newValue to new_value returnCodeIfMismatch to return_code_if_mismatch spyCodeIfMisMatch to spy_code_if_mis_match upper16Bits to upper16_bits upper8Bits to upper8_bits ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/hw/EasiGlobal.h | 2 +- drivers/staging/tidspbridge/hw/GlobalTypes.h | 72 ++++++++------- drivers/staging/tidspbridge/hw/MMURegAcM.h | 96 ++++++++++---------- drivers/staging/tidspbridge/hw/hw_mmu.c | 46 +++++----- drivers/staging/tidspbridge/hw/hw_mmu.h | 20 ++-- .../staging/tidspbridge/include/dspbridge/cmm.h | 6 +- drivers/staging/tidspbridge/pmgr/cmm.c | 14 ++-- 7 files changed, 129 insertions(+), 127 deletions(-) mode change 100644 => 100755 drivers/staging/tidspbridge/hw/GlobalTypes.h diff --git a/drivers/staging/tidspbridge/hw/EasiGlobal.h b/drivers/staging/tidspbridge/hw/EasiGlobal.h index 9b45aa7..e48d7f6 100644 --- a/drivers/staging/tidspbridge/hw/EasiGlobal.h +++ b/drivers/staging/tidspbridge/hw/EasiGlobal.h @@ -36,6 +36,6 @@ * * NOTE: We currently dont use this functionality. */ -#define _DEBUG_LEVEL1_EASI(easiNum) ((void)0) +#define _DEBUG_LEVEL1_EASI(easi_num) ((void)0) #endif /* _EASIGLOBAL_H */ diff --git a/drivers/staging/tidspbridge/hw/GlobalTypes.h b/drivers/staging/tidspbridge/hw/GlobalTypes.h index 9b55150..95fc8ca --- a/drivers/staging/tidspbridge/hw/GlobalTypes.h +++ b/drivers/staging/tidspbridge/hw/GlobalTypes.h @@ -94,39 +94,39 @@ #define LOWER8BIT_MASK 0x000000FF /* - * Definition: RETURN32BITS_FROM16LOWER_AND16UPPER(lower16Bits, upper16Bits) + * Definition: RETURN32BITS_FROM16LOWER_AND16UPPER(lower16_bits, upper16_bits) * * DESCRIPTION: Returns a 32 bit value given a 16 bit lower value and a 16 * bit upper value */ -#define RETURN32BITS_FROM16LOWER_AND16UPPER(lower16Bits, upper16Bits)\ - (((((u32)lower16Bits) & LOWER16BIT_MASK)) | \ - (((((u32)upper16Bits) & LOWER16BIT_MASK) << UPPER16BIT_SHIFT))) +#define RETURN32BITS_FROM16LOWER_AND16UPPER(lower16_bits, upper16_bits)\ + (((((u32)lower16_bits) & LOWER16BIT_MASK)) | \ + (((((u32)upper16_bits) & LOWER16BIT_MASK) << UPPER16BIT_SHIFT))) /* - * Definition: RETURN16BITS_FROM8LOWER_AND8UPPER(lower16Bits, upper16Bits) + * Definition: RETURN16BITS_FROM8LOWER_AND8UPPER(lower16_bits, upper16_bits) * * DESCRIPTION: Returns a 16 bit value given a 8 bit lower value and a 8 * bit upper value */ -#define RETURN16BITS_FROM8LOWER_AND8UPPER(lower8Bits, upper8Bits)\ - (((((u32)lower8Bits) & LOWER8BIT_MASK)) | \ - (((((u32)upper8Bits) & LOWER8BIT_MASK) << UPPER8BIT_OF16_SHIFT))) +#define RETURN16BITS_FROM8LOWER_AND8UPPER(lower8_bits, upper8_bits)\ + (((((u32)lower8_bits) & LOWER8BIT_MASK)) | \ + (((((u32)upper8_bits) & LOWER8BIT_MASK) << UPPER8BIT_OF16_SHIFT))) /* - * Definition: RETURN32BITS_FROM48BIT_VALUES(lower8Bits, lowerMiddle8Bits, - * lowerUpper8Bits, upper8Bits) + * Definition: RETURN32BITS_FROM48BIT_VALUES(lower8_bits, lower_middle8_bits, + * lower_upper8_bits, upper8_bits) * * DESCRIPTION: Returns a 32 bit value given four 8 bit values */ -#define RETURN32BITS_FROM48BIT_VALUES(lower8Bits, lowerMiddle8Bits,\ - lowerUpper8Bits, upper8Bits)\ - (((((u32)lower8Bits) & LOWER8BIT_MASK)) | \ - (((((u32)lowerMiddle8Bits) & LOWER8BIT_MASK) <<\ +#define RETURN32BITS_FROM48BIT_VALUES(lower8_bits, lower_middle8_bits,\ + lower_upper8_bits, upper8_bits)\ + (((((u32)lower8_bits) & LOWER8BIT_MASK)) | \ + (((((u32)lower_middle8_bits) & LOWER8BIT_MASK) <<\ LOWER_MIDDLE8BIT_SHIFT)) | \ - (((((u32)lowerUpper8Bits) & LOWER8BIT_MASK) <<\ + (((((u32)lower_upper8_bits) & LOWER8BIT_MASK) <<\ UPPER_MIDDLE8BIT_SHIFT)) | \ - (((((u32)upper8Bits) & LOWER8BIT_MASK) <<\ + (((((u32)upper8_bits) & LOWER8BIT_MASK) <<\ UPPER8BIT_SHIFT))) /* @@ -285,24 +285,26 @@ enum return_code_label { /* Not sure if this all belongs here */ -#define CHECK_RETURN_VALUE(actualValue, expectedValue, returnCodeIfMismatch,\ - spyCodeIfMisMatch) -#define CHECK_RETURN_VALUE_RET(actualValue, expectedValue, returnCodeIfMismatch) -#define CHECK_RETURN_VALUE_RES(actualValue, expectedValue, spyCodeIfMisMatch) -#define CHECK_RETURN_VALUE_RET_VOID(actualValue, expectedValue,\ - spyCodeIfMisMatch) - -#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\ - spyCodeIfMisMatch) -#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue,\ - returnCodeIfMismatch) -#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue,\ - returnCodeIfMismatch, spyCodeIfMisMatch) -#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue, maxValidValue,\ - returnCodeIfMismatch) -#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue,\ - returnCodeIfMismatch, spyCodeIfMisMatch) -#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, maxValidValue,\ - returnCodeIfMismatch) +#define CHECK_RETURN_VALUE(actual_value, expected_value,\ + return_code_if_mismatch, spy_code_if_mis_match) +#define CHECK_RETURN_VALUE_RET(actual_value, expected_value,\ + return_code_if_mismatch) +#define CHECK_RETURN_VALUE_RES(actual_value, expected_value,\ + spy_code_if_mis_match) +#define CHECK_RETURN_VALUE_RET_VOID(actual_value, expected_value,\ + spy_code_if_mis_match) + +#define CHECK_INPUT_PARAM(actual_value, invalid_value,\ + return_code_if_mismatch, spy_code_if_mis_match) +#define CHECK_INPUT_PARAM_NO_SPY(actual_value, invalid_value,\ + return_code_if_mismatch) +#define CHECK_INPUT_RANGE(actual_value, min_valid_value, max_valid_value,\ + return_code_if_mismatch, spy_code_if_mis_match) +#define CHECK_INPUT_RANGE_NO_SPY(actual_value, min_valid_value,\ + max_valid_value, return_code_if_mismatch) +#define CHECK_INPUT_RANGE_MIN0(actual_value, max_valid_value,\ + return_code_if_mismatch, spy_code_if_mis_match) +#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actual_value, max_valid_value,\ + return_code_if_mismatch) #endif /* _GLOBALTYPES_H */ diff --git a/drivers/staging/tidspbridge/hw/MMURegAcM.h b/drivers/staging/tidspbridge/hw/MMURegAcM.h index c341060..39db036 100644 --- a/drivers/staging/tidspbridge/hw/MMURegAcM.h +++ b/drivers/staging/tidspbridge/hw/MMURegAcM.h @@ -33,38 +33,38 @@ {\ const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ register u32 data = __raw_readl((base_address)+offset);\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32);\ data &= ~(MMU_MMU_SYSCONFIG_IDLE_MODE_MASK);\ - newValue <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\ - newValue &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, base_address+offset);\ + new_value <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\ + new_value &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\ + new_value |= data;\ + __raw_writel(new_value, base_address+offset);\ } #define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(base_address, value)\ {\ const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ register u32 data = __raw_readl((base_address)+offset);\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32);\ data &= ~(MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK);\ - newValue <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\ - newValue &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, base_address+offset);\ + new_value <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\ + new_value &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\ + new_value |= data;\ + __raw_writel(new_value, base_address+offset);\ } #define MMUMMU_IRQSTATUS_READ_REGISTER32(base_address)\ - (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\ + (_DEBUG_LEVEL1_EASI(easil1_mmummu_irqstatus_read_register32),\ __raw_readl((base_address)+MMU_MMU_IRQSTATUS_OFFSET)) #define MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #define MMUMMU_IRQENABLE_READ_REGISTER32(base_address)\ @@ -74,9 +74,9 @@ #define MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #define MMUMMU_WALKING_STTWL_RUNNING_READ32(base_address)\ @@ -95,26 +95,26 @@ {\ const u32 offset = MMU_MMU_CNTL_OFFSET;\ register u32 data = __raw_readl((base_address)+offset);\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32);\ data &= ~(MMU_MMU_CNTL_TWL_ENABLE_MASK);\ - newValue <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\ - newValue &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, base_address+offset);\ + new_value <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\ + new_value &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\ + new_value |= data;\ + __raw_writel(new_value, base_address+offset);\ } #define MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, value)\ {\ const u32 offset = MMU_MMU_CNTL_OFFSET;\ register u32 data = __raw_readl((base_address)+offset);\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32);\ data &= ~(MMU_MMU_CNTL_MMU_ENABLE_MASK);\ - newValue <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\ - newValue &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, base_address+offset);\ + new_value <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\ + new_value &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\ + new_value |= data;\ + __raw_writel(new_value, base_address+offset);\ } #define MMUMMU_FAULT_AD_READ_REGISTER32(base_address)\ @@ -124,9 +124,9 @@ #define MMUMMU_TTB_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_TTB_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_TTB_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #define MMUMMU_LOCK_READ_REGISTER32(base_address)\ @@ -136,9 +136,9 @@ #define MMUMMU_LOCK_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_LOCK_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #define MMUMMU_LOCK_BASE_VALUE_READ32(base_address)\ @@ -151,13 +151,13 @@ {\ const u32 offset = MMU_MMU_LOCK_OFFSET;\ register u32 data = __raw_readl((base_address)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\ + register u32 new_value = (value);\ + _DEBUG_LEVEL1_EASI(easil1_mmummu_lock_base_value_write32);\ data &= ~(MMU_MMU_LOCK_BASE_VALUE_MASK);\ - newValue <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\ - newValue &= MMU_MMU_LOCK_BASE_VALUE_MASK;\ - newValue |= data;\ - __raw_writel(newValue, base_address+offset);\ + new_value <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\ + new_value &= MMU_MMU_LOCK_BASE_VALUE_MASK;\ + new_value |= data;\ + __raw_writel(new_value, base_address+offset);\ } #define MMUMMU_LOCK_CURRENT_VICTIM_READ32(base_address)\ @@ -170,13 +170,13 @@ {\ const u32 offset = MMU_MMU_LOCK_OFFSET;\ register u32 data = __raw_readl((base_address)+offset);\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32);\ data &= ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK);\ - newValue <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\ - newValue &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\ - newValue |= data;\ - __raw_writel(newValue, base_address+offset);\ + new_value <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\ + new_value &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\ + new_value |= data;\ + __raw_writel(new_value, base_address+offset);\ } #define MMUMMU_LOCK_CURRENT_VICTIM_SET32(var, value)\ @@ -192,33 +192,33 @@ #define MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_LD_TLB_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #define MMUMMU_CAM_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_CAM_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CAM_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #define MMUMMU_RAM_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_RAM_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_RAM_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, value)\ {\ const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\ - register u32 newValue = (value);\ + register u32 new_value = (value);\ _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32);\ - __raw_writel(newValue, (base_address)+offset);\ + __raw_writel(new_value, (base_address)+offset);\ } #endif /* USE_LEVEL_1_MACROS */ diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index 705cbe3..969b5fc 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -90,7 +90,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); * Description : It indicates the TLB entry is preserved entry * or not * - * Identifier : validBit + * Identifier : valid_bit * Type : const u32 * Description : It indicates the TLB entry is valid entry or not * @@ -115,7 +115,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); static hw_status mmu_set_cam_entry(const void __iomem *base_address, const u32 page_sz, const u32 preserved_bit, - const u32 validBit, + const u32 valid_bit, const u32 virtual_addr_tag); /* @@ -194,11 +194,11 @@ hw_status hw_mmu_num_locked_set(const void __iomem *base_address, } hw_status hw_mmu_victim_num_set(const void __iomem *base_address, - u32 victimEntryNum) + u32 victim_entry_num) { hw_status status = RET_OK; - MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, victimEntryNum); + MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, victim_entry_num); return status; } @@ -293,7 +293,7 @@ hw_status hw_mmu_twl_disable(const void __iomem *base_address) return status; } -hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, +hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr, u32 page_sz) { hw_status status = RET_OK; @@ -322,7 +322,7 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, } /* Generate the 20-bit tag from virtual address */ - virtual_addr_tag = ((virtualAddr & MMU_ADDR_MASK) >> 12); + virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12); mmu_set_cam_entry(base_address, pg_size_bits, 0, 0, virtual_addr_tag); @@ -333,11 +333,11 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, hw_status hw_mmu_tlb_add(const void __iomem *base_address, u32 physical_addr, - u32 virtualAddr, + u32 virtual_addr, u32 page_sz, u32 entry_num, struct hw_mmu_map_attrs_t *map_attrs, - s8 preserved_bit, s8 validBit) + s8 preserved_bit, s8 valid_bit) { hw_status status = RET_OK; u32 lock_reg; @@ -377,10 +377,10 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, lock_reg = MMUMMU_LOCK_READ_REGISTER32(base_address); /* Generate the 20-bit tag from virtual address */ - virtual_addr_tag = ((virtualAddr & MMU_ADDR_MASK) >> 12); + virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12); /* Write the fields in the CAM Entry Register */ - mmu_set_cam_entry(base_address, mmu_pg_size, preserved_bit, validBit, + mmu_set_cam_entry(base_address, mmu_pg_size, preserved_bit, valid_bit, virtual_addr_tag); /* Write the different fields of the RAM Entry Register */ @@ -403,7 +403,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, hw_status hw_mmu_pte_set(const u32 pg_tbl_va, u32 physical_addr, - u32 virtualAddr, + u32 virtual_addr, u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs) { hw_status status = RET_OK; @@ -413,7 +413,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, switch (page_sz) { case HW_PAGE_SIZE4KB: pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_SMALL_PAGE_MASK); pte_val = ((physical_addr & MMU_SMALL_PAGE_MASK) | @@ -425,7 +425,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, case HW_PAGE_SIZE64KB: num_entries = 16; pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_LARGE_PAGE_MASK); pte_val = ((physical_addr & MMU_LARGE_PAGE_MASK) | @@ -436,7 +436,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, case HW_PAGE_SIZE1MB: pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_SECTION_ADDR_MASK); pte_val = ((((physical_addr & MMU_SECTION_ADDR_MASK) | @@ -448,7 +448,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, case HW_PAGE_SIZE16MB: num_entries = 16; pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_SSECTION_ADDR_MASK); pte_val = (((physical_addr & MMU_SSECTION_ADDR_MASK) | @@ -460,7 +460,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, case HW_MMU_COARSE_PAGE_SIZE: pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_SECTION_ADDR_MASK); pte_val = (physical_addr & MMU_PAGE_TABLE_MASK) | 1; break; @@ -475,7 +475,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, return status; } -hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtualAddr, u32 page_size) +hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size) { hw_status status = RET_OK; u32 pte_addr; @@ -484,28 +484,28 @@ hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtualAddr, u32 page_size) switch (page_size) { case HW_PAGE_SIZE4KB: pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_SMALL_PAGE_MASK); break; case HW_PAGE_SIZE64KB: num_entries = 16; pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_LARGE_PAGE_MASK); break; case HW_PAGE_SIZE1MB: case HW_MMU_COARSE_PAGE_SIZE: pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_SECTION_ADDR_MASK); break; case HW_PAGE_SIZE16MB: num_entries = 16; pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, - virtualAddr & + virtual_addr & MMU_SSECTION_ADDR_MASK); break; @@ -539,7 +539,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address) static hw_status mmu_set_cam_entry(const void __iomem *base_address, const u32 page_sz, const u32 preserved_bit, - const u32 validBit, + const u32 valid_bit, const u32 virtual_addr_tag) { hw_status status = RET_OK; @@ -550,7 +550,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, RES_MMU_BASE + RES_INVALID_INPUT_PARAM); mmu_cam_reg = (virtual_addr_tag << 12); - mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (validBit << 2) | + mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (valid_bit << 2) | (preserved_bit << 3); /* write values to register */ diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h index 554b52e..6ba133e 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.h +++ b/drivers/staging/tidspbridge/hw/hw_mmu.h @@ -50,7 +50,7 @@ extern hw_status hw_mmu_num_locked_set(const void __iomem *base_address, u32 num_locked_entries); extern hw_status hw_mmu_victim_num_set(const void __iomem *base_address, - u32 victimEntryNum); + u32 victim_entry_num); /* For MMU faults */ extern hw_status hw_mmu_event_ack(const void __iomem *base_address, @@ -77,45 +77,45 @@ extern hw_status hw_mmu_twl_enable(const void __iomem *base_address); extern hw_status hw_mmu_twl_disable(const void __iomem *base_address); extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address, - u32 virtualAddr, u32 page_sz); + u32 virtual_addr, u32 page_sz); extern hw_status hw_mmu_tlb_add(const void __iomem *base_address, u32 physical_addr, - u32 virtualAddr, + u32 virtual_addr, u32 page_sz, u32 entry_num, struct hw_mmu_map_attrs_t *map_attrs, - s8 preserved_bit, s8 validBit); + s8 preserved_bit, s8 valid_bit); /* For PTEs */ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, u32 physical_addr, - u32 virtualAddr, + u32 virtual_addr, u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs); extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, - u32 page_size, u32 virtualAddr); + u32 page_size, u32 virtual_addr); void hw_mmu_tlb_flush_all(const void __iomem *base); -static inline u32 hw_mmu_pte_addr_l1(u32 L1_base, u32 va) +static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va) { u32 pte_addr; u32 va31_to20; va31_to20 = va >> (20 - 2); /* Left-shift by 2 here itself */ va31_to20 &= 0xFFFFFFFCUL; - pte_addr = L1_base + va31_to20; + pte_addr = l1_base + va31_to20; return pte_addr; } -static inline u32 hw_mmu_pte_addr_l2(u32 L2_base, u32 va) +static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va) { u32 pte_addr; - pte_addr = (L2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC); + pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC); return pte_addr; } diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index 3944a1e..086ca25 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -370,17 +370,17 @@ extern int cmm_xlator_info(struct cmm_xlatorobject *xlator, * Parameters: * xlator: handle to translator. * paddr address of buffer to translate. - * xType Type of address xlation. CMM_PA2VA or CMM_VA2PA. + * xtype Type of address xlation. CMM_PA2VA or CMM_VA2PA. * Returns: * Valid address on success, else NULL. * Requires: * refs > 0 * paddr != NULL - * xType >= CMM_VA2PA) && (xType <= CMM_DSPPA2PA) + * xtype >= CMM_VA2PA) && (xtype <= CMM_DSPPA2PA) * Ensures: * */ extern void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, - void *paddr, enum cmm_xlatetype xType); + void *paddr, enum cmm_xlatetype xtype); #endif /* CMM_ */ diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index 2381984..d054e53 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -1103,7 +1103,7 @@ int cmm_xlator_info(struct cmm_xlatorobject *xlator, IN OUT u8 ** paddr, * ======== cmm_xlator_translate ======== */ void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, void *paddr, - enum cmm_xlatetype xType) + enum cmm_xlatetype xtype) { u32 dw_addr_xlate = 0; struct cmm_xlator *xlator_obj = (struct cmm_xlator *)xlator; @@ -1113,7 +1113,7 @@ void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, void *paddr, DBC_REQUIRE(refs > 0); DBC_REQUIRE(paddr != NULL); - DBC_REQUIRE((xType >= CMM_VA2PA) && (xType <= CMM_DSPPA2PA)); + DBC_REQUIRE((xtype >= CMM_VA2PA) && (xtype <= CMM_DSPPA2PA)); if (!xlator_obj) goto loop_cont; @@ -1125,9 +1125,9 @@ void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, void *paddr, if (!allocator) goto loop_cont; - if ((xType == CMM_VA2DSPPA) || (xType == CMM_VA2PA) || - (xType == CMM_PA2VA)) { - if (xType == CMM_PA2VA) { + if ((xtype == CMM_VA2DSPPA) || (xtype == CMM_VA2PA) || + (xtype == CMM_PA2VA)) { + if (xtype == CMM_PA2VA) { /* Gpp Va = Va Base + offset */ dw_offset = (u8 *) paddr - (u8 *) (allocator->shm_base - allocator-> @@ -1152,14 +1152,14 @@ void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, void *paddr, dw_addr_xlate = (u32) paddr; } /*Now convert address to proper target physical address if needed */ - if ((xType == CMM_VA2DSPPA) || (xType == CMM_PA2DSPPA)) { + if ((xtype == CMM_VA2DSPPA) || (xtype == CMM_PA2DSPPA)) { /* Got Gpp Pa now, convert to DSP Pa */ dw_addr_xlate = GPPPA2DSPPA((allocator->shm_base - allocator->ul_dsp_size), dw_addr_xlate, allocator->dw_dsp_phys_addr_offset * allocator->c_factor); - } else if (xType == CMM_DSPPA2PA) { + } else if (xtype == CMM_DSPPA2PA) { /* Got DSP Pa, convert to GPP Pa */ dw_addr_xlate = DSPPA2GPPPA(allocator->shm_base - allocator->ul_dsp_size, From patchwork Sat Jul 10 02:24:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111199 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Sktj002447 for ; Sat, 10 Jul 2010 02:28:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754540Ab0GJCZr (ORCPT ); Fri, 9 Jul 2010 22:25:47 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:55233 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753397Ab0GJCZa (ORCPT ); Fri, 9 Jul 2010 22:25:30 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PFa2006474 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:15 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PECK014577; Fri, 9 Jul 2010 21:25:14 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68M021595; Fri, 9 Jul 2010 21:25:14 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 10/15] staging:ti dspbridge: Rename words with camel case Date: Fri, 9 Jul 2010 21:24:04 -0500 Message-Id: <1278728649-21012-11-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-10-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> <1278728649-21012-10-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:51 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== pstrFxn to str_fxn pstrLibName to str_lib_name pstrSect to str_sect pstrSym to str_sym pstrZLFileName to str_zl_file_name pstrZLFile to str_zl_file pszCoffPath to sz_coff_path pszMode to sz_mode pszName to sz_name pszSectName to sz_sect_name pszUuid to sz_uuid pszZlDllName to sz_zl_dll_name puAddr to addr pulAddr to addr pulBufSize to buff_size pulBytes to nbytes ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/gen/uuidutil.c | 40 ++++++------ .../staging/tidspbridge/include/dspbridge/cfg.h | 8 +- .../staging/tidspbridge/include/dspbridge/cod.h | 50 ++++++++-------- .../staging/tidspbridge/include/dspbridge/dbdcd.h | 24 ++++---- .../tidspbridge/include/dspbridge/dblldefs.h | 4 +- .../staging/tidspbridge/include/dspbridge/dev.h | 6 +- .../staging/tidspbridge/include/dspbridge/nldr.h | 2 +- .../tidspbridge/include/dspbridge/nldrdefs.h | 10 ++-- .../staging/tidspbridge/include/dspbridge/strm.h | 10 ++-- .../tidspbridge/include/dspbridge/uuidutil.h | 16 +++--- drivers/staging/tidspbridge/pmgr/cod.c | 64 ++++++++++---------- drivers/staging/tidspbridge/pmgr/dev.c | 6 +- drivers/staging/tidspbridge/rmgr/dbdcd.c | 32 +++++----- drivers/staging/tidspbridge/rmgr/nldr.c | 20 +++--- drivers/staging/tidspbridge/rmgr/strm.c | 14 ++-- 15 files changed, 153 insertions(+), 153 deletions(-) diff --git a/drivers/staging/tidspbridge/gen/uuidutil.c b/drivers/staging/tidspbridge/gen/uuidutil.c index 070761b..840da42 100755 --- a/drivers/staging/tidspbridge/gen/uuidutil.c +++ b/drivers/staging/tidspbridge/gen/uuidutil.c @@ -36,14 +36,14 @@ * Note: snprintf format specifier is: * %[flags] [width] [.precision] [{h | l | I64 | L}]type */ -void uuid_uuid_to_string(IN struct dsp_uuid *uuid_obj, OUT char *pszUuid, +void uuid_uuid_to_string(IN struct dsp_uuid *uuid_obj, OUT char *sz_uuid, IN s32 size) { s32 i; /* return result from snprintf. */ - DBC_REQUIRE(uuid_obj && pszUuid); + DBC_REQUIRE(uuid_obj && sz_uuid); - i = snprintf(pszUuid, size, + i = snprintf(sz_uuid, size, "%.8X_%.4X_%.4X_%.2X%.2X_%.2X%.2X%.2X%.2X%.2X%.2X", uuid_obj->ul_data1, uuid_obj->us_data2, uuid_obj->us_data3, uuid_obj->uc_data4, uuid_obj->uc_data5, @@ -75,39 +75,39 @@ static s32 uuid_hex_to_bin(char *buf, s32 len) * Purpose: * Converts a string to a struct dsp_uuid. */ -void uuid_uuid_from_string(IN char *pszUuid, OUT struct dsp_uuid *uuid_obj) +void uuid_uuid_from_string(IN char *sz_uuid, OUT struct dsp_uuid *uuid_obj) { s32 j; - uuid_obj->ul_data1 = uuid_hex_to_bin(pszUuid, 8); - pszUuid += 8; + uuid_obj->ul_data1 = uuid_hex_to_bin(sz_uuid, 8); + sz_uuid += 8; /* Step over underscore */ - pszUuid++; + sz_uuid++; - uuid_obj->us_data2 = (u16) uuid_hex_to_bin(pszUuid, 4); - pszUuid += 4; + uuid_obj->us_data2 = (u16) uuid_hex_to_bin(sz_uuid, 4); + sz_uuid += 4; /* Step over underscore */ - pszUuid++; + sz_uuid++; - uuid_obj->us_data3 = (u16) uuid_hex_to_bin(pszUuid, 4); - pszUuid += 4; + uuid_obj->us_data3 = (u16) uuid_hex_to_bin(sz_uuid, 4); + sz_uuid += 4; /* Step over underscore */ - pszUuid++; + sz_uuid++; - uuid_obj->uc_data4 = (u8) uuid_hex_to_bin(pszUuid, 2); - pszUuid += 2; + uuid_obj->uc_data4 = (u8) uuid_hex_to_bin(sz_uuid, 2); + sz_uuid += 2; - uuid_obj->uc_data5 = (u8) uuid_hex_to_bin(pszUuid, 2); - pszUuid += 2; + uuid_obj->uc_data5 = (u8) uuid_hex_to_bin(sz_uuid, 2); + sz_uuid += 2; /* Step over underscore */ - pszUuid++; + sz_uuid++; for (j = 0; j < 6; j++) { - uuid_obj->uc_data6[j] = (u8) uuid_hex_to_bin(pszUuid, 2); - pszUuid += 2; + uuid_obj->uc_data6[j] = (u8) uuid_hex_to_bin(sz_uuid, 2); + sz_uuid += 2; } } diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfg.h b/drivers/staging/tidspbridge/include/dspbridge/cfg.h index 98cadb1..1422ed0 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cfg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cfg.h @@ -155,20 +155,20 @@ extern void cfg_get_perf_value(OUT bool *enable_perf); * Parameters: * dev_node_obj: Handle to the dev_node who's driver we are querying. * buf_size: Size of buffer. - * pstrZLFileName: Ptr to character buf to hold ZLFileName. + * str_zl_file_name: Ptr to character buf to hold ZLFileName. * Returns: * 0: Success. - * -EFAULT: pstrZLFileName is invalid or dev_node_obj is invalid. + * -EFAULT: str_zl_file_name is invalid or dev_node_obj is invalid. * -ENODATA: couldn't find the ZLFileName. * Requires: * CFG initialized. * Ensures: * 0: Not more than buf_size bytes were copied into - * pstrZLFileName, and *pstrZLFileName contains ZLFileName + * str_zl_file_name, and *str_zl_file_name contains ZLFileName * for this devnode. */ extern int cfg_get_zl_file(IN struct cfg_devnode *dev_node_obj, - IN u32 buf_size, OUT char *pstrZLFileName); + IN u32 buf_size, OUT char *str_zl_file_name); /* * ======== cfg_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index f8cbb21..c84761e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -78,7 +78,7 @@ extern void cod_close(struct cod_libraryobj *lib); * using the cod_get_sym_value() function. * Parameters: * manager: created manager object - * pstrZLFile: ZL DLL filename, of length < COD_MAXPATHLENGTH. + * str_zl_file: ZL DLL filename, of length < COD_MAXPATHLENGTH. * attrs: attributes to be used by this object. A NULL value * will cause default attrs to be used. * Returns: @@ -88,11 +88,11 @@ extern void cod_close(struct cod_libraryobj *lib); * non default values of attrs. * Requires: * COD module initialized. - * pstrZLFile != NULL + * str_zl_file != NULL * Ensures: */ extern int cod_create(OUT struct cod_manager **manager, - char *pstrZLFile, + char *str_zl_file, IN OPTIONAL CONST struct cod_attrs *attrs); /* @@ -149,7 +149,7 @@ extern int cod_get_base_lib(struct cod_manager *cod_mgr_obj, * Get the name of the base image DBL library. * Parameters: * cod_mgr_obj: handle of manager to be deleted - * pszName: location to store library name on output. + * sz_name: location to store library name on output. * usize: size of name buffer. * Returns: * 0: Success. @@ -157,11 +157,11 @@ extern int cod_get_base_lib(struct cod_manager *cod_mgr_obj, * Requires: * COD module initialized. * valid cod_mgr_obj. - * pszName != NULL. + * sz_name != NULL. * Ensures: */ extern int cod_get_base_name(struct cod_manager *cod_mgr_obj, - char *pszName, u32 usize); + char *sz_name, u32 usize); /* * ======== cod_get_entry ======== @@ -206,8 +206,8 @@ extern int cod_get_loader(struct cod_manager *cod_mgr_obj, * given the section name. * Parameters: * lib Library handle returned from cod_open(). - * pstrSect: name of the section, with or without leading "." - * puAddr: Location to store address. + * str_sect: name of the section, with or without leading "." + * addr: Location to store address. * puLen: Location to store length. * Returns: * 0: Success @@ -216,18 +216,18 @@ extern int cod_get_loader(struct cod_manager *cod_mgr_obj, * Requires: * COD module initialized. * valid cod_mgr_obj. - * pstrSect != NULL; - * puAddr != NULL; + * str_sect != NULL; + * addr != NULL; * puLen != NULL; * Ensures: - * 0: *puAddr and *puLen contain the address and length of the + * 0: *addr and *puLen contain the address and length of the * section. - * else: *puAddr == 0 and *puLen == 0; + * else: *addr == 0 and *puLen == 0; * */ extern int cod_get_section(struct cod_libraryobj *lib, - IN char *pstrSect, - OUT u32 *puAddr, OUT u32 *puLen); + IN char *str_sect, + OUT u32 *addr, OUT u32 *puLen); /* * ======== cod_get_sym_value ======== @@ -246,12 +246,12 @@ extern int cod_get_section(struct cod_libraryobj *lib, * Requires: * COD module initialized. * Valid cod_mgr_obj. - * pstrSym != NULL. + * str_sym != NULL. * pul_value != NULL. * Ensures: */ extern int cod_get_sym_value(struct cod_manager *cod_mgr_obj, - IN char *pstrSym, OUT u32 * pul_value); + IN char *str_sym, OUT u32 * pul_value); /* * ======== cod_init ======== @@ -304,7 +304,7 @@ extern int cod_load_base(struct cod_manager *cod_mgr_obj, * Open a library for reading sections. Does not load or set the base. * Parameters: * hmgr: manager to load the code with - * pszCoffPath: Coff file to open. + * sz_coff_path: Coff file to open. * flags: COD_NOLOAD (don't load symbols) or COD_SYMB (load * symbols). * lib_obj: Handle returned that can be used in calls to cod_close @@ -316,11 +316,11 @@ extern int cod_load_base(struct cod_manager *cod_mgr_obj, * COD module initialized. * hmgr is valid. * flags == COD_NOLOAD || flags == COD_SYMB. - * pszCoffPath != NULL. + * sz_coff_path != NULL. * Ensures: */ extern int cod_open(struct cod_manager *hmgr, - IN char *pszCoffPath, + IN char *sz_coff_path, u32 flags, OUT struct cod_libraryobj **lib_obj); /* @@ -329,7 +329,7 @@ extern int cod_open(struct cod_manager *hmgr, * Open base image for reading sections. Does not load the base. * Parameters: * hmgr: manager to load the code with - * pszCoffPath: Coff file to open. + * sz_coff_path: Coff file to open. * flags: Specifies whether to load symbols. * Returns: * 0: Success. @@ -337,10 +337,10 @@ extern int cod_open(struct cod_manager *hmgr, * Requires: * COD module initialized. * hmgr is valid. - * pszCoffPath != NULL. + * sz_coff_path != NULL. * Ensures: */ -extern int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, +extern int cod_open_base(struct cod_manager *hmgr, IN char *sz_coff_path, dbll_flags flags); /* @@ -349,7 +349,7 @@ extern int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, * Retrieve the content of a code section given the section name. * Parameters: * cod_mgr_obj - manager in which to search for the symbol - * pstrSect - name of the section, with or without leading "." + * str_sect - name of the section, with or without leading "." * str_content - buffer to store content of the section. * Returns: * 0: on success, error code on failure @@ -357,13 +357,13 @@ extern int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, * Requires: * COD module initialized. * valid cod_mgr_obj. - * pstrSect != NULL; + * str_sect != NULL; * str_content != NULL; * Ensures: * 0: *str_content stores the content of the named section. */ extern int cod_read_section(struct cod_libraryobj *lib, - IN char *pstrSect, + IN char *str_sect, OUT char *str_content, IN u32 content_size); #endif /* COD_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h index 8d1fc68..c798e72 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h @@ -30,7 +30,7 @@ * special COFF section called ".dcd_register" * Parameters: * hdcd_mgr: A DCD manager handle. - * pszCoffPath: Pointer to name of COFF file containing DCD + * sz_coff_path: Pointer to name of COFF file containing DCD * objects to be registered. * Returns: * 0: Success. @@ -45,7 +45,7 @@ * ".dcd_register", which is used for auto registration. */ extern int dcd_auto_register(IN struct dcd_manager *hdcd_mgr, - IN char *pszCoffPath); + IN char *sz_coff_path); /* * ======== dcd_auto_unregister ======== @@ -54,7 +54,7 @@ extern int dcd_auto_register(IN struct dcd_manager *hdcd_mgr, * special COFF section called ".dcd_register" * Parameters: * hdcd_mgr: A DCD manager handle. - * pszCoffPath: Pointer to name of COFF file containing + * sz_coff_path: Pointer to name of COFF file containing * DCD objects to be unregistered. * Returns: * 0: Success. @@ -69,14 +69,14 @@ extern int dcd_auto_register(IN struct dcd_manager *hdcd_mgr, * ".dcd_register", which is used for auto unregistration. */ extern int dcd_auto_unregister(IN struct dcd_manager *hdcd_mgr, - IN char *pszCoffPath); + IN char *sz_coff_path); /* * ======== dcd_create_manager ======== * Purpose: * This function creates a DCD module manager. * Parameters: - * pszZlDllName: Pointer to a DLL name string. + * sz_zl_dll_name: Pointer to a DLL name string. * dcd_mgr: A pointer to a DCD manager handle. * Returns: * 0: Success. @@ -84,12 +84,12 @@ extern int dcd_auto_unregister(IN struct dcd_manager *hdcd_mgr, * -EPERM: General failure. * Requires: * DCD initialized. - * pszZlDllName is non-NULL. + * sz_zl_dll_name is non-NULL. * dcd_mgr is non-NULL. * Ensures: * A DCD manager handle is created. */ -extern int dcd_create_manager(IN char *pszZlDllName, +extern int dcd_create_manager(IN char *sz_zl_dll_name, OUT struct dcd_manager **dcd_mgr); /* @@ -214,7 +214,7 @@ extern int dcd_get_num_dep_libs(IN struct dcd_manager *hdcd_mgr, * hdcd_mgr: A DCD manager handle. * uuid_obj: Pointer to a dsp_uuid that represents a unique DSP/BIOS * Bridge object. - * pstrLibName: Buffer to hold library name. + * str_lib_name: Buffer to hold library name. * buff_size: Contains buffer size. Set to string size on output. * phase: Which phase to load * phase_split: Are phases in multiple libraries @@ -224,14 +224,14 @@ extern int dcd_get_num_dep_libs(IN struct dcd_manager *hdcd_mgr, * Requires: * DCD initialized. * Valid hdcd_mgr. - * pstrLibName != NULL. + * str_lib_name != NULL. * uuid_obj != NULL * buff_size != NULL. * Ensures: */ extern int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - IN OUT char *pstrLibName, + IN OUT char *str_lib_name, IN OUT u32 *buff_size, IN enum nldr_phase phase, OUT bool *phase_split); @@ -276,7 +276,7 @@ extern int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, * unregister nodes from the node database, and 3) add overlay nodes. * Parameters: * hdcd_mgr: A DCD manager handle. - * pszCoffPath: Pointer to name of COFF file containing DCD + * sz_coff_path: Pointer to name of COFF file containing DCD * objects. * registerFxn: Callback fxn to be applied on each located * DCD object. @@ -295,7 +295,7 @@ extern int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, * ".dcd_register", which is used for auto registration. */ extern int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, - IN char *pszCoffPath, + IN char *sz_coff_path, dcd_registerfxn registerFxn, void *handle); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h index b827320..8446e0e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h @@ -368,7 +368,7 @@ typedef int(*dbll_load_fxn) (struct dbll_library_obj *lib, * Ensures: */ typedef int(*dbll_load_sect_fxn) (struct dbll_library_obj *lib, - char *pszSectName, + char *sz_sect_name, struct dbll_attrs *attrs); /* @@ -471,7 +471,7 @@ typedef void (*dbll_unload_fxn) (struct dbll_library_obj *library, * Ensures: */ typedef int(*dbll_unload_sect_fxn) (struct dbll_library_obj *lib, - char *pszSectName, + char *sz_sect_name, struct dbll_attrs *attrs); struct dbll_fxns { diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index d658df5..0cdbcb2 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -475,7 +475,7 @@ extern int dev_get_node_manager(struct dev_object * Parameters: * hdev_obj: Handle to device object created with * dev_create_device(). - * pstrSym: Name of symbol to look up. + * str_sym: Name of symbol to look up. * pul_value: Ptr to symbol value. * Returns: * 0: Success. @@ -483,14 +483,14 @@ extern int dev_get_node_manager(struct dev_object * -ESPIPE: Symbols couldn not be found or have not been loaded onto * the board. * Requires: - * pstrSym != NULL. + * str_sym != NULL. * pul_value != NULL. * DEV Initialized. * Ensures: * 0: *pul_value contains the symbol value; */ extern int dev_get_symbol(struct dev_object *hdev_obj, - IN CONST char *pstrSym, OUT u32 * pul_value); + IN CONST char *str_sym, OUT u32 * pul_value); /* * ======== dev_get_bridge_context ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldr.h b/drivers/staging/tidspbridge/include/dspbridge/nldr.h index b2bfb5e..986ebc8 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldr.h @@ -39,7 +39,7 @@ extern void nldr_delete(struct nldr_object *nldr_obj); extern void nldr_exit(void); extern int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, - char *pstrFxn, u32 * pulAddr); + char *str_fxn, u32 * addr); extern int nldr_get_rmm_manager(struct nldr_object *nldr, OUT struct rmm_target_obj **rmm_mgr); diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h index e15ef67..ed20dc0 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h @@ -210,21 +210,21 @@ typedef void (*nldr_freefxn) (struct nldr_nodeobject *nldr_node_obj); * * Parameters: * nldr_node_obj: Handle returned from nldr_allocate(). - * pstrFxn: Name of function. - * pulAddr: Location to store function address. + * str_fxn: Name of function. + * addr: Location to store function address. * Returns: * 0: Success. * -ESPIPE: Address of function not found. * Requires: * nldr_init(void) called. * Valid nldr_node_obj. - * pulAddr != NULL; - * pstrFxn != NULL; + * addr != NULL; + * str_fxn != NULL; * Ensures: */ typedef int(*nldr_getfxnaddrfxn) (struct nldr_nodeobject * nldr_node_obj, - char *pstrFxn, u32 * pulAddr); + char *str_fxn, u32 * addr); /* * ======== nldr_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/strm.h b/drivers/staging/tidspbridge/include/dspbridge/strm.h index 6572442..e028518 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/strm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/strm.h @@ -303,9 +303,9 @@ extern int strm_prepare_buffer(struct strm_object *stream_obj, * Parameters: * stream_obj: Stream handle returned from strm_open(). * buf_ptr: Location to store pointer to reclaimed buffer. - * pulBytes: Location where number of bytes of data in the + * nbytes: Location where number of bytes of data in the * buffer will be written. - * pulBufSize: Location where actual buffer size will be written. + * buff_size: Location where actual buffer size will be written. * pdw_arg: Location where user argument that travels with * the buffer will be written. * Returns: @@ -317,13 +317,13 @@ extern int strm_prepare_buffer(struct strm_object *stream_obj, * Requires: * strm_init(void) called. * buf_ptr != NULL. - * pulBytes != NULL. + * nbytes != NULL. * pdw_arg != NULL. * Ensures: */ extern int strm_reclaim(struct strm_object *stream_obj, - OUT u8 **buf_ptr, u32 * pulBytes, - u32 *pulBufSize, u32 *pdw_arg); + OUT u8 **buf_ptr, u32 * nbytes, + u32 *buff_size, u32 *pdw_arg); /* * ======== strm_register_notify ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h b/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h index d7d0962..dde76c9 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h +++ b/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h @@ -27,18 +27,18 @@ * Converts a dsp_uuid to an ANSI string. * Parameters: * uuid_obj: Pointer to a dsp_uuid object. - * pszUuid: Pointer to a buffer to receive a NULL-terminated UUID + * sz_uuid: Pointer to a buffer to receive a NULL-terminated UUID * string. - * size: Maximum size of the pszUuid string. + * size: Maximum size of the sz_uuid string. * Returns: * Requires: - * uuid_obj & pszUuid are non-NULL values. + * uuid_obj & sz_uuid are non-NULL values. * Ensures: - * Lenghth of pszUuid is less than MAXUUIDLEN. + * Lenghth of sz_uuid is less than MAXUUIDLEN. * Details: * UUID string limit currently set at MAXUUIDLEN. */ -void uuid_uuid_to_string(IN struct dsp_uuid *uuid_obj, OUT char *pszUuid, +void uuid_uuid_to_string(IN struct dsp_uuid *uuid_obj, OUT char *sz_uuid, s32 size); /* @@ -46,17 +46,17 @@ void uuid_uuid_to_string(IN struct dsp_uuid *uuid_obj, OUT char *pszUuid, * Purpose: * Converts an ANSI string to a dsp_uuid. * Parameters: - * pszUuid: Pointer to a string that represents a dsp_uuid object. + * sz_uuid: Pointer to a string that represents a dsp_uuid object. * uuid_obj: Pointer to a dsp_uuid object. * Returns: * Requires: - * uuid_obj & pszUuid are non-NULL values. + * uuid_obj & sz_uuid are non-NULL values. * Ensures: * Details: * We assume the string representation of a UUID has the following format: * "12345678_1234_1234_1234_123456789abc". */ -extern void uuid_uuid_from_string(IN char *pszUuid, +extern void uuid_uuid_from_string(IN char *sz_uuid, OUT struct dsp_uuid *uuid_obj); #endif /* UUIDUTIL_ */ diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index e4fc065..ae44bed 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -109,7 +109,7 @@ static s32 cod_f_close(struct file *filp) return 0; } -static struct file *cod_f_open(CONST char *psz_file_name, CONST char *pszMode) +static struct file *cod_f_open(CONST char *psz_file_name, CONST char *sz_mode) { mm_segment_t fs; struct file *filp; @@ -337,17 +337,17 @@ int cod_get_base_lib(struct cod_manager *cod_mgr_obj, /* * ======== cod_get_base_name ======== */ -int cod_get_base_name(struct cod_manager *cod_mgr_obj, char *pszName, +int cod_get_base_name(struct cod_manager *cod_mgr_obj, char *sz_name, u32 usize) { int status = 0; DBC_REQUIRE(refs > 0); DBC_REQUIRE(IS_VALID(cod_mgr_obj)); - DBC_REQUIRE(pszName != NULL); + DBC_REQUIRE(sz_name != NULL); if (usize <= COD_MAXPATHLENGTH) - strncpy(pszName, cod_mgr_obj->sz_zl_file, usize); + strncpy(sz_name, cod_mgr_obj->sz_zl_file, usize); else status = -EPERM; @@ -396,8 +396,8 @@ int cod_get_loader(struct cod_manager *cod_mgr_obj, * Retrieve the starting address and length of a section in the COFF file * given the section name. */ -int cod_get_section(struct cod_libraryobj *lib, IN char *pstrSect, - OUT u32 *puAddr, OUT u32 *puLen) +int cod_get_section(struct cod_libraryobj *lib, IN char *str_sect, + OUT u32 *addr, OUT u32 *puLen) { struct cod_manager *cod_mgr_obj; int status = 0; @@ -405,21 +405,21 @@ int cod_get_section(struct cod_libraryobj *lib, IN char *pstrSect, DBC_REQUIRE(refs > 0); DBC_REQUIRE(lib != NULL); DBC_REQUIRE(IS_VALID(lib->cod_mgr)); - DBC_REQUIRE(pstrSect != NULL); - DBC_REQUIRE(puAddr != NULL); + DBC_REQUIRE(str_sect != NULL); + DBC_REQUIRE(addr != NULL); DBC_REQUIRE(puLen != NULL); - *puAddr = 0; + *addr = 0; *puLen = 0; if (lib != NULL) { cod_mgr_obj = lib->cod_mgr; - status = cod_mgr_obj->fxns.get_sect_fxn(lib->dbll_lib, pstrSect, - puAddr, puLen); + status = cod_mgr_obj->fxns.get_sect_fxn(lib->dbll_lib, str_sect, + addr, puLen); } else { status = -ESPIPE; } - DBC_ENSURE(DSP_SUCCEEDED(status) || ((*puAddr == 0) && (*puLen == 0))); + DBC_ENSURE(DSP_SUCCEEDED(status) || ((*addr == 0) && (*puLen == 0))); return status; } @@ -432,23 +432,23 @@ int cod_get_section(struct cod_libraryobj *lib, IN char *pstrSect, * C symbol. * */ -int cod_get_sym_value(struct cod_manager *hmgr, char *pstrSym, +int cod_get_sym_value(struct cod_manager *hmgr, char *str_sym, u32 *pul_value) { struct dbll_sym_val *dbll_sym; DBC_REQUIRE(refs > 0); DBC_REQUIRE(IS_VALID(hmgr)); - DBC_REQUIRE(pstrSym != NULL); + DBC_REQUIRE(str_sym != NULL); DBC_REQUIRE(pul_value != NULL); - dev_dbg(bridge, "%s: hmgr: %p pstrSym: %s pul_value: %p\n", - __func__, hmgr, pstrSym, pul_value); + dev_dbg(bridge, "%s: hmgr: %p str_sym: %s pul_value: %p\n", + __func__, hmgr, str_sym, pul_value); if (hmgr->base_lib) { if (!hmgr->fxns. - get_addr_fxn(hmgr->base_lib, pstrSym, &dbll_sym)) { + get_addr_fxn(hmgr->base_lib, str_sym, &dbll_sym)) { if (!hmgr->fxns. - get_c_addr_fxn(hmgr->base_lib, pstrSym, &dbll_sym)) + get_c_addr_fxn(hmgr->base_lib, str_sym, &dbll_sym)) return -ESPIPE; } } else { @@ -550,7 +550,7 @@ int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], * ======== cod_open ======== * Open library for reading sections. */ -int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, +int cod_open(struct cod_manager *hmgr, IN char *sz_coff_path, u32 flags, struct cod_libraryobj **lib_obj) { int status = 0; @@ -558,7 +558,7 @@ int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, DBC_REQUIRE(refs > 0); DBC_REQUIRE(IS_VALID(hmgr)); - DBC_REQUIRE(pszCoffPath != NULL); + DBC_REQUIRE(sz_coff_path != NULL); DBC_REQUIRE(flags == COD_NOLOAD || flags == COD_SYMB); DBC_REQUIRE(lib_obj != NULL); @@ -570,15 +570,15 @@ int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, if (DSP_SUCCEEDED(status)) { lib->cod_mgr = hmgr; - status = hmgr->fxns.open_fxn(hmgr->target, pszCoffPath, flags, + status = hmgr->fxns.open_fxn(hmgr->target, sz_coff_path, flags, &lib->dbll_lib); if (DSP_SUCCEEDED(status)) *lib_obj = lib; } if (DSP_FAILED(status)) - pr_err("%s: error status 0x%x, pszCoffPath: %s flags: 0x%x\n", - __func__, status, pszCoffPath, flags); + pr_err("%s: error status 0x%x, sz_coff_path: %s flags: 0x%x\n", + __func__, status, sz_coff_path, flags); return status; } @@ -587,7 +587,7 @@ int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, * Purpose: * Open base image for reading sections. */ -int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, +int cod_open_base(struct cod_manager *hmgr, IN char *sz_coff_path, dbll_flags flags) { int status = 0; @@ -595,7 +595,7 @@ int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, DBC_REQUIRE(refs > 0); DBC_REQUIRE(IS_VALID(hmgr)); - DBC_REQUIRE(pszCoffPath != NULL); + DBC_REQUIRE(sz_coff_path != NULL); /* if we previously opened a base image, close it now */ if (hmgr->base_lib) { @@ -606,17 +606,17 @@ int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, hmgr->fxns.close_fxn(hmgr->base_lib); hmgr->base_lib = NULL; } - status = hmgr->fxns.open_fxn(hmgr->target, pszCoffPath, flags, &lib); + status = hmgr->fxns.open_fxn(hmgr->target, sz_coff_path, flags, &lib); if (DSP_SUCCEEDED(status)) { /* hang onto the library for subsequent sym table usage */ hmgr->base_lib = lib; - strncpy(hmgr->sz_zl_file, pszCoffPath, COD_MAXPATHLENGTH - 1); + strncpy(hmgr->sz_zl_file, sz_coff_path, COD_MAXPATHLENGTH - 1); hmgr->sz_zl_file[COD_MAXPATHLENGTH - 1] = '\0'; } if (DSP_FAILED(status)) - pr_err("%s: error status 0x%x pszCoffPath: %s\n", __func__, - status, pszCoffPath); + pr_err("%s: error status 0x%x sz_coff_path: %s\n", __func__, + status, sz_coff_path); return status; } @@ -625,7 +625,7 @@ int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, * Purpose: * Retrieve the content of a code section given the section name. */ -int cod_read_section(struct cod_libraryobj *lib, IN char *pstrSect, +int cod_read_section(struct cod_libraryobj *lib, IN char *str_sect, OUT char *str_content, IN u32 content_size) { int status = 0; @@ -633,12 +633,12 @@ int cod_read_section(struct cod_libraryobj *lib, IN char *pstrSect, DBC_REQUIRE(refs > 0); DBC_REQUIRE(lib != NULL); DBC_REQUIRE(IS_VALID(lib->cod_mgr)); - DBC_REQUIRE(pstrSect != NULL); + DBC_REQUIRE(str_sect != NULL); DBC_REQUIRE(str_content != NULL); if (lib != NULL) status = - lib->cod_mgr->fxns.read_sect_fxn(lib->dbll_lib, pstrSect, + lib->cod_mgr->fxns.read_sect_fxn(lib->dbll_lib, str_sect, str_content, content_size); else status = -ESPIPE; diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index 5098f7f..55e2a5e 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -691,18 +691,18 @@ int dev_get_node_manager(struct dev_object *hdev_obj, * ======== dev_get_symbol ======== */ int dev_get_symbol(struct dev_object *hdev_obj, - IN CONST char *pstrSym, OUT u32 * pul_value) + IN CONST char *str_sym, OUT u32 * pul_value) { int status = 0; struct cod_manager *cod_mgr; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(pstrSym != NULL && pul_value != NULL); + DBC_REQUIRE(str_sym != NULL && pul_value != NULL); if (hdev_obj) { status = dev_get_cod_mgr(hdev_obj, &cod_mgr); if (cod_mgr) - status = cod_get_sym_value(cod_mgr, (char *)pstrSym, + status = cod_get_sym_value(cod_mgr, (char *)str_sym, pul_value); else status = -EFAULT; diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 2f32ece..a5cef43 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -81,16 +81,16 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, * Parses the supplied image and resigsters with DCD. */ int dcd_auto_register(IN struct dcd_manager *hdcd_mgr, - IN char *pszCoffPath) + IN char *sz_coff_path) { int status = 0; DBC_REQUIRE(refs > 0); if (hdcd_mgr) - status = dcd_get_objects(hdcd_mgr, pszCoffPath, + status = dcd_get_objects(hdcd_mgr, sz_coff_path, (dcd_registerfxn) dcd_register_object, - (void *)pszCoffPath); + (void *)sz_coff_path); else status = -EFAULT; @@ -103,14 +103,14 @@ int dcd_auto_register(IN struct dcd_manager *hdcd_mgr, * Parses the supplied DSP image and unresiters from DCD. */ int dcd_auto_unregister(IN struct dcd_manager *hdcd_mgr, - IN char *pszCoffPath) + IN char *sz_coff_path) { int status = 0; DBC_REQUIRE(refs > 0); if (hdcd_mgr) - status = dcd_get_objects(hdcd_mgr, pszCoffPath, + status = dcd_get_objects(hdcd_mgr, sz_coff_path, (dcd_registerfxn) dcd_register_object, NULL); else @@ -124,7 +124,7 @@ int dcd_auto_unregister(IN struct dcd_manager *hdcd_mgr, * Purpose: * Creates DCD manager. */ -int dcd_create_manager(IN char *pszZlDllName, +int dcd_create_manager(IN char *sz_zl_dll_name, OUT struct dcd_manager **dcd_mgr) { struct cod_manager *cod_mgr; /* COD manager handle */ @@ -134,7 +134,7 @@ int dcd_create_manager(IN char *pszZlDllName, DBC_REQUIRE(refs >= 0); DBC_REQUIRE(dcd_mgr); - status = cod_create(&cod_mgr, pszZlDllName, NULL); + status = cod_create(&cod_mgr, sz_zl_dll_name, NULL); if (DSP_FAILED(status)) goto func_end; @@ -534,7 +534,7 @@ func_end: * ======== dcd_get_objects ======== */ int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, - IN char *pszCoffPath, dcd_registerfxn registerFxn, + IN char *sz_coff_path, dcd_registerfxn registerFxn, void *handle) { struct dcd_manager *dcd_mgr_obj = hdcd_mgr; @@ -556,7 +556,7 @@ int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, } /* Open DSP coff file, don't load symbols. */ - status = cod_open(dcd_mgr_obj->cod_mgr, pszCoffPath, COD_NOLOAD, &lib); + status = cod_open(dcd_mgr_obj->cod_mgr, sz_coff_path, COD_NOLOAD, &lib); if (DSP_FAILED(status)) { status = -EACCES; goto func_cont; @@ -572,7 +572,7 @@ int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, /* Allocate zeroed buffer. */ psz_coff_buf = kzalloc(ul_len + 4, GFP_KERNEL); #ifdef _DB_TIOMAP - if (strstr(pszCoffPath, "iva") == NULL) { + if (strstr(sz_coff_path, "iva") == NULL) { /* Locate section by objectID and read its content. */ status = cod_read_section(lib, DCD_REGISTER_SECTION, psz_coff_buf, ul_len); @@ -587,7 +587,7 @@ int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, #endif if (DSP_SUCCEEDED(status)) { /* Compress DSP buffer to conform to PC format. */ - if (strstr(pszCoffPath, "iva") == NULL) { + if (strstr(sz_coff_path, "iva") == NULL) { compress_buf(psz_coff_buf, ul_len, DSPWORDSIZE); } else { compress_buf(psz_coff_buf, ul_len, 1); @@ -644,7 +644,7 @@ func_end: */ int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - IN OUT char *pstrLibName, + IN OUT char *str_lib_name, IN OUT u32 *buff_size, enum nldr_phase phase, OUT bool *phase_split) { @@ -656,12 +656,12 @@ int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, struct dcd_key_elem *dcd_key = NULL; DBC_REQUIRE(uuid_obj != NULL); - DBC_REQUIRE(pstrLibName != NULL); + DBC_REQUIRE(str_lib_name != NULL); DBC_REQUIRE(buff_size != NULL); DBC_REQUIRE(hdcd_mgr); - dev_dbg(bridge, "%s: hdcd_mgr %p, uuid_obj %p, pstrLibName %p," - " buff_size %p\n", __func__, hdcd_mgr, uuid_obj, pstrLibName, + dev_dbg(bridge, "%s: hdcd_mgr %p, uuid_obj %p, str_lib_name %p," + " buff_size %p\n", __func__, hdcd_mgr, uuid_obj, str_lib_name, buff_size); /* @@ -768,7 +768,7 @@ int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, } if (DSP_SUCCEEDED(status)) - memcpy(pstrLibName, dcd_key->path, strlen(dcd_key->path) + 1); + memcpy(str_lib_name, dcd_key->path, strlen(dcd_key->path) + 1); return status; } diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 0c8a165..3eb1ae3 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -682,7 +682,7 @@ void nldr_exit(void) * ======== nldr_get_fxn_addr ======== */ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, - char *pstrFxn, u32 * pulAddr) + char *str_fxn, u32 * addr) { struct dbll_sym_val *dbll_sym; struct nldr_object *nldr_obj; @@ -692,8 +692,8 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, struct lib_node root = { NULL, 0, NULL }; DBC_REQUIRE(refs > 0); DBC_REQUIRE(nldr_node_obj); - DBC_REQUIRE(pulAddr != NULL); - DBC_REQUIRE(pstrFxn != NULL); + DBC_REQUIRE(addr != NULL); + DBC_REQUIRE(str_fxn != NULL); nldr_obj = nldr_node_obj->nldr_obj; /* Called from node_create(), node_delete(), or node_run(). */ @@ -717,10 +717,10 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, root = nldr_node_obj->root; } status1 = - nldr_obj->ldr_fxns.get_c_addr_fxn(root.lib, pstrFxn, &dbll_sym); + nldr_obj->ldr_fxns.get_c_addr_fxn(root.lib, str_fxn, &dbll_sym); if (!status1) status1 = - nldr_obj->ldr_fxns.get_addr_fxn(root.lib, pstrFxn, + nldr_obj->ldr_fxns.get_addr_fxn(root.lib, str_fxn, &dbll_sym); /* If symbol not found, check dependent libraries */ @@ -728,13 +728,13 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, for (i = 0; i < root.dep_libs; i++) { status1 = nldr_obj->ldr_fxns.get_addr_fxn(root.dep_libs_tree - [i].lib, pstrFxn, + [i].lib, str_fxn, &dbll_sym); if (!status1) { status1 = nldr_obj->ldr_fxns. get_c_addr_fxn(root.dep_libs_tree[i].lib, - pstrFxn, &dbll_sym); + str_fxn, &dbll_sym); } if (status1) { /* Symbol found */ @@ -748,12 +748,12 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, status1 = nldr_obj->ldr_fxns. get_addr_fxn(nldr_node_obj->pers_lib_table[i].lib, - pstrFxn, &dbll_sym); + str_fxn, &dbll_sym); if (!status1) { status1 = nldr_obj->ldr_fxns. get_c_addr_fxn(nldr_node_obj->pers_lib_table - [i].lib, pstrFxn, &dbll_sym); + [i].lib, str_fxn, &dbll_sym); } if (status1) { /* Symbol found */ @@ -763,7 +763,7 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, } if (status1) - *pulAddr = dbll_sym->value; + *addr = dbll_sym->value; else status = -ESPIPE; diff --git a/drivers/staging/tidspbridge/rmgr/strm.c b/drivers/staging/tidspbridge/rmgr/strm.c index f6922f4..ad3b50c 100644 --- a/drivers/staging/tidspbridge/rmgr/strm.c +++ b/drivers/staging/tidspbridge/rmgr/strm.c @@ -620,7 +620,7 @@ func_cont: * Relcaims a buffer from a stream. */ int strm_reclaim(struct strm_object *stream_obj, OUT u8 ** buf_ptr, - u32 *pulBytes, u32 *pulBufSize, u32 *pdw_arg) + u32 *nbytes, u32 *buff_size, u32 *pdw_arg) { struct bridge_drv_interface *intf_fxns; struct chnl_ioc chnl_ioc_obj; @@ -629,7 +629,7 @@ int strm_reclaim(struct strm_object *stream_obj, OUT u8 ** buf_ptr, DBC_REQUIRE(refs > 0); DBC_REQUIRE(buf_ptr != NULL); - DBC_REQUIRE(pulBytes != NULL); + DBC_REQUIRE(nbytes != NULL); DBC_REQUIRE(pdw_arg != NULL); if (!stream_obj) { @@ -643,9 +643,9 @@ int strm_reclaim(struct strm_object *stream_obj, OUT u8 ** buf_ptr, stream_obj->utimeout, &chnl_ioc_obj); if (DSP_SUCCEEDED(status)) { - *pulBytes = chnl_ioc_obj.byte_size; - if (pulBufSize) - *pulBufSize = chnl_ioc_obj.buf_size; + *nbytes = chnl_ioc_obj.byte_size; + if (buff_size) + *buff_size = chnl_ioc_obj.buf_size; *pdw_arg = chnl_ioc_obj.dw_arg; if (!CHNL_IS_IO_COMPLETE(chnl_ioc_obj)) { @@ -692,9 +692,9 @@ func_end: status == -ETIME || status == -ESRCH || status == -EPERM); - dev_dbg(bridge, "%s: stream_obj: %p buf_ptr: %p pulBytes: %p " + dev_dbg(bridge, "%s: stream_obj: %p buf_ptr: %p nbytes: %p " "pdw_arg: %p status 0x%x\n", __func__, stream_obj, - buf_ptr, pulBytes, pdw_arg, status); + buf_ptr, nbytes, pdw_arg, status); return status; } From patchwork Tue May 4 07:45:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 96685 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o447jabG003517 for ; Tue, 4 May 2010 07:45:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756980Ab0EDHpe (ORCPT ); Tue, 4 May 2010 03:45:34 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:42497 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756658Ab0EDHpd (ORCPT ); Tue, 4 May 2010 03:45:33 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o447jP82001512 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 4 May 2010 02:45:27 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o447jORU018917; Tue, 4 May 2010 13:15:24 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o447jOHO031398; Tue, 4 May 2010 13:15:24 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o447jN6V031394; Tue, 4 May 2010 13:15:23 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, Ajay Kumar Gupta Subject: [PATCH 1/2] usb: ehci-omap: fix compilation warning Date: Tue, 4 May 2010 13:15:22 +0530 Message-Id: <1272959123-31362-1-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 04 May 2010 07:45:36 +0000 (UTC) diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 40a8583..e55fd58 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -659,6 +659,8 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev) goto err_add_hcd; } + ehci_port_power(omap->ehci, 0); + return 0; err_add_hcd: From patchwork Fri Jun 25 23:36:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 108199 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5PNaOxS003486 for ; Fri, 25 Jun 2010 23:36:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755703Ab0FYXgW (ORCPT ); Fri, 25 Jun 2010 19:36:22 -0400 Received: from mail-pv0-f174.google.com ([74.125.83.174]:50822 "EHLO mail-pv0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751245Ab0FYXgW (ORCPT ); Fri, 25 Jun 2010 19:36:22 -0400 Received: by pvg2 with SMTP id 2so1080708pvg.19 for ; Fri, 25 Jun 2010 16:36:21 -0700 (PDT) Received: by 10.142.67.34 with SMTP id p34mr1874230wfa.335.1277508981500; Fri, 25 Jun 2010 16:36:21 -0700 (PDT) Received: from localhost (c-24-18-179-55.hsd1.wa.comcast.net [24.18.179.55]) by mx.google.com with ESMTPS id e32sm575590wfj.15.2010.06.25.16.36.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 25 Jun 2010 16:36:20 -0700 (PDT) From: Kevin Hilman To: Charulatha V Cc: linux-omap@vger.kernel.org, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com Subject: Re: [PATCH:v4 12/13] OMAP: GPIO: Implement GPIO as a platform device Organization: Deep Root Systems, LLC References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> <1277218916-15213-3-git-send-email-charu@ti.com> <1277218916-15213-4-git-send-email-charu@ti.com> <1277218916-15213-5-git-send-email-charu@ti.com> <1277218916-15213-6-git-send-email-charu@ti.com> <1277218916-15213-7-git-send-email-charu@ti.com> <1277218916-15213-8-git-send-email-charu@ti.com> <1277218916-15213-9-git-send-email-charu@ti.com> <1277218916-15213-10-git-send-email-charu@ti.com> <1277218916-15213-11-git-send-email-charu@ti.com> <1277218916-15213-12-git-send-email-charu@ti.com> <1277218916-15213-13-git-send-email-charu@ti.com> Date: Fri, 25 Jun 2010 16:36:18 -0700 In-Reply-To: <1277218916-15213-13-git-send-email-charu@ti.com> (Charulatha V.'s message of "Tue, 22 Jun 2010 20:31:55 +0530") Message-ID: <87lja28z2l.fsf@deeprootsystems.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (gnu/linux) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 25 Jun 2010 23:36:24 +0000 (UTC) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 6dc5e4b..6a5a8f4 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2091,10 +2091,44 @@ void omap_gpio_restore_context(void) } #endif +static int gpio_bank_suspend(struct device *dev) +{ + return 0; +} + +static int gpio_bank_resume(struct device *dev) +{ + return 0; +} + +static int gpio_bank_runtime_idle(struct device *dev) +{ + return 0; +} + +static int gpio_bank_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int gpio_bank_runtime_resume(struct device *dev) +{ + return 0; +} + +static struct dev_pm_ops gpio_pm_ops = { + .suspend = gpio_bank_suspend, + .resume = gpio_bank_resume, + .runtime_idle = gpio_bank_runtime_idle, + .runtime_suspend = gpio_bank_runtime_suspend, + .runtime_resume = gpio_bank_runtime_resume, +}; + static struct platform_driver omap_gpio_driver = { .probe = omap_gpio_probe, .driver = { .name = "omap-gpio", + .pm = &gpio_pm_ops, }, }; From patchwork Sat Jul 10 02:24:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111194 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Skte002447 for ; Sat, 10 Jul 2010 02:28:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754147Ab0GJCZm (ORCPT ); Fri, 9 Jul 2010 22:25:42 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:45779 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753004Ab0GJCZZ (ORCPT ); Fri, 9 Jul 2010 22:25:25 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PGOj025253 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:16 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6A2PFCd026443; Fri, 9 Jul 2010 21:25:15 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68O021595; Fri, 9 Jul 2010 21:25:15 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 12/15] staging:ti dspbridge: Rename words with camel case Date: Fri, 9 Jul 2010 21:24:06 -0500 Message-Id: <1278728649-21012-13-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-12-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> <1278728649-21012-10-git-send-email-rene.sapiens@ti.com> <1278728649-21012-11-git-send-email-rene.sapiens@ti.com> <1278728649-21012-12-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:49 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== segmentId to segmnt_id SetPageDirty to set_page_dirty sizeInBytes to size_in_bytes sleepCode to sleep_code Status to status symName to sym_name szVar to sz_var Trapped_Args to trapped_args TTBPhysAddr to ttb_phys_addr uChirps to chirps uChnlId to ch_id uChnlID to ch_id uContentSize to cont_size uDDMAChnlId to ddma_chnl_id uEvents to events ulAlign to align_mask ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/chnl_sm.c | 30 +++--- drivers/staging/tidspbridge/core/tiomap3430.c | 4 +- drivers/staging/tidspbridge/hw/hw_mmu.c | 4 +- drivers/staging/tidspbridge/hw/hw_mmu.h | 2 +- .../staging/tidspbridge/include/dspbridge/dbdefs.h | 4 +- .../tidspbridge/include/dspbridge/dblldefs.h | 2 +- .../staging/tidspbridge/include/dspbridge/drv.h | 4 +- .../tidspbridge/include/dspbridge/dspapi-ioctl.h | 2 +- .../staging/tidspbridge/include/dspbridge/dspapi.h | 112 ++++++++++---------- .../tidspbridge/include/dspbridge/dspchnl.h | 4 +- .../tidspbridge/include/dspbridge/dspdefs.h | 8 +- .../staging/tidspbridge/include/dspbridge/io_sm.h | 20 ++-- .../staging/tidspbridge/include/dspbridge/proc.h | 12 +- .../staging/tidspbridge/include/dspbridge/pwr.h | 6 +- drivers/staging/tidspbridge/pmgr/dspapi.c | 116 ++++++++++---------- drivers/staging/tidspbridge/rmgr/drv.c | 5 +- drivers/staging/tidspbridge/rmgr/drv_interface.c | 6 +- drivers/staging/tidspbridge/rmgr/nldr.c | 12 +- drivers/staging/tidspbridge/rmgr/proc.c | 18 ++-- drivers/staging/tidspbridge/rmgr/pwr.c | 6 +- 20 files changed, 189 insertions(+), 188 deletions(-) mode change 100644 => 100755 drivers/staging/tidspbridge/rmgr/drv_interface.c diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 97eeda9..ac393b8 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -73,7 +73,7 @@ #define MAILBOX_IRQ INT_MAIL_MPU_IRQ /* ----------------------------------- Function Prototypes */ -static struct lst_list *create_chirp_list(u32 uChirps); +static struct lst_list *create_chirp_list(u32 chirps); static void free_chirp_list(struct lst_list *lst); @@ -709,18 +709,18 @@ func_end: * ======== bridge_chnl_get_mgr_info ======== * Retrieve information related to the channel manager. */ -int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 uChnlID, +int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 ch_id, OUT struct chnl_mgrinfo *mgr_info) { int status = 0; struct chnl_mgr *chnl_mgr_obj = (struct chnl_mgr *)hchnl_mgr; if (mgr_info != NULL) { - if (uChnlID <= CHNL_MAXCHANNELS) { + if (ch_id <= CHNL_MAXCHANNELS) { if (hchnl_mgr) { /* Return the requested information: */ mgr_info->chnl_obj = - chnl_mgr_obj->ap_channel[uChnlID]; + chnl_mgr_obj->ap_channel[ch_id]; mgr_info->open_channels = chnl_mgr_obj->open_channels; mgr_info->dw_type = chnl_mgr_obj->dw_type; @@ -776,7 +776,7 @@ int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 timeout, */ int bridge_chnl_open(OUT struct chnl_object **chnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, - u32 uChnlId, CONST IN struct chnl_attr *pattrs) + u32 ch_id, CONST IN struct chnl_attr *pattrs) { int status = 0; struct chnl_mgr *chnl_mgr_obj = hchnl_mgr; @@ -794,23 +794,23 @@ int bridge_chnl_open(OUT struct chnl_object **chnl, if (!hchnl_mgr) { status = -EFAULT; } else { - if (uChnlId != CHNL_PICKFREE) { - if (uChnlId >= chnl_mgr_obj->max_channels) + if (ch_id != CHNL_PICKFREE) { + if (ch_id >= chnl_mgr_obj->max_channels) status = -ECHRNG; - else if (chnl_mgr_obj->ap_channel[uChnlId] != + else if (chnl_mgr_obj->ap_channel[ch_id] != NULL) status = -EALREADY; } else { /* Check for free channel */ status = - search_free_channel(chnl_mgr_obj, &uChnlId); + search_free_channel(chnl_mgr_obj, &ch_id); } } } if (DSP_FAILED(status)) goto func_end; - DBC_ASSERT(uChnlId < chnl_mgr_obj->max_channels); + DBC_ASSERT(ch_id < chnl_mgr_obj->max_channels); /* Create channel object: */ pchnl = kzalloc(sizeof(struct chnl_object), GFP_KERNEL); if (!pchnl) { @@ -846,7 +846,7 @@ int bridge_chnl_open(OUT struct chnl_object **chnl, pchnl->free_packets_list) { /* Initialize CHNL object fields: */ pchnl->chnl_mgr_obj = chnl_mgr_obj; - pchnl->chnl_id = uChnlId; + pchnl->chnl_id = ch_id; pchnl->chnl_mode = chnl_mode; pchnl->user_event = sync_event; pchnl->sync_event = sync_event; @@ -926,13 +926,13 @@ int bridge_chnl_register_notify(struct chnl_object *chnl_obj, * Purpose: * Initialize a queue of channel I/O Request/Completion packets. * Parameters: - * uChirps: Number of Chirps to allocate. + * chirps: Number of Chirps to allocate. * Returns: * Pointer to queue of IRPs, or NULL. * Requires: * Ensures: */ -static struct lst_list *create_chirp_list(u32 uChirps) +static struct lst_list *create_chirp_list(u32 chirps) { struct lst_list *chirp_list; struct chnl_irp *chnl_packet_obj; @@ -943,14 +943,14 @@ static struct lst_list *create_chirp_list(u32 uChirps) if (chirp_list) { INIT_LIST_HEAD(&chirp_list->head); /* Make N chirps and place on queue. */ - for (i = 0; (i < uChirps) + for (i = 0; (i < chirps) && ((chnl_packet_obj = make_new_chirp()) != NULL); i++) { lst_put_tail(chirp_list, (struct list_head *)chnl_packet_obj); } /* If we couldn't allocate all chirps, free those allocated: */ - if (i != uChirps) { + if (i != chirps) { free_chirp_list(chirp_list); chirp_list = NULL; } diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index e759349..0fdec37 100755 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -1507,7 +1507,7 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt, "0x%x\n", paddr, ul_num_bytes); bad_page_dump(paddr, pg); } else { - SetPageDirty(pg); + set_page_dirty(pg); page_cache_release(pg); } paddr += HW_PAGE_SIZE4KB; @@ -1571,7 +1571,7 @@ skip_coarse_page: "0x%x\n", paddr, ul_num_bytes); bad_page_dump(paddr, pg); } else { - SetPageDirty(pg); + set_page_dirty(pg); page_cache_release(pg); } } diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index 668fb8a..705cbe3 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -259,7 +259,7 @@ hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr) return status; } -hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 TTBPhysAddr) +hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr) { hw_status status = RET_OK; u32 load_ttb; @@ -268,7 +268,7 @@ hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 TTBPhysAddr) CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM, RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - load_ttb = TTBPhysAddr & ~0x7FUL; + load_ttb = ttb_phys_addr & ~0x7FUL; /* write values to register */ MMUMMU_TTB_WRITE_REGISTER32(base_address, load_ttb); diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h index 25f1954..554b52e 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.h +++ b/drivers/staging/tidspbridge/hw/hw_mmu.h @@ -70,7 +70,7 @@ extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, /* Set the TT base address */ extern hw_status hw_mmu_ttb_set(const void __iomem *base_address, - u32 TTBPhysAddr); + u32 ttb_phys_addr); extern hw_status hw_mmu_twl_enable(const void __iomem *base_address); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h index 9462a96..fb168e6 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h @@ -94,8 +94,8 @@ #define DSPWORDSIZE sizeof(DSPWORD) /* Success & Failure macros */ -#define DSP_SUCCEEDED(Status) likely((s32)(Status) >= 0) -#define DSP_FAILED(Status) unlikely((s32)(Status) < 0) +#define DSP_SUCCEEDED(status) likely((s32)(status) >= 0) +#define DSP_FAILED(status) unlikely((s32)(status) < 0) /* Power control enumerations */ #define PROC_PWRCONTROL 0x8070 diff --git a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h index fa4c99f..d2b4fda 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h @@ -420,7 +420,7 @@ typedef int(*dbll_open_fxn) (struct dbll_tar_obj *target, char *file, */ typedef int(*dbll_read_sect_fxn) (struct dbll_library_obj *lib, char *name, char *content, - u32 uContentSize); + u32 cont_size); /* * ======== dbll_set_attrs ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index efdc29c..c180a7c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -450,7 +450,7 @@ extern void mem_ext_phys_pool_release(void); * Allocate physically contiguous, uncached memory * Parameters: * byte_size: Number of bytes to allocate. - * ulAlign: Alignment Mask. + * align_mask: Alignment Mask. * physical_address: Physical address of allocated memory. * Returns: * Pointer to a block of memory; @@ -463,7 +463,7 @@ extern void mem_ext_phys_pool_release(void); * location of memory. */ extern void *mem_alloc_phys_mem(IN u32 byte_size, - IN u32 ulAlign, OUT u32 *physical_address); + IN u32 align_mask, OUT u32 *physical_address); /* * ======== mem_free_phys_mem ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h b/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h index cc4e75b..fa3ba6b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h @@ -24,7 +24,7 @@ #include #include -union Trapped_Args { +union trapped_args { /* MGR Module */ struct { diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspapi.h b/drivers/staging/tidspbridge/include/dspbridge/dspapi.h index 765a175..c99c687 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspapi.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspapi.h @@ -50,7 +50,7 @@ * Ensures: */ extern int api_call_dev_ioctl(unsigned int cmd, - union Trapped_Args *args, + union trapped_args *args, u32 *result, void *pr_ctxt); /* @@ -98,70 +98,70 @@ extern int api_init_complete2(void); extern void api_exit(void); /* MGR wrapper functions */ -extern u32 mgrwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt); -extern u32 mgrwrap_enum_proc_info(union Trapped_Args *args, void *pr_ctxt); -extern u32 mgrwrap_register_object(union Trapped_Args *args, void *pr_ctxt); -extern u32 mgrwrap_unregister_object(union Trapped_Args *args, void *pr_ctxt); -extern u32 mgrwrap_wait_for_bridge_events(union Trapped_Args *args, +extern u32 mgrwrap_enum_node_info(union trapped_args *args, void *pr_ctxt); +extern u32 mgrwrap_enum_proc_info(union trapped_args *args, void *pr_ctxt); +extern u32 mgrwrap_register_object(union trapped_args *args, void *pr_ctxt); +extern u32 mgrwrap_unregister_object(union trapped_args *args, void *pr_ctxt); +extern u32 mgrwrap_wait_for_bridge_events(union trapped_args *args, void *pr_ctxt); -extern u32 mgrwrap_get_process_resources_info(union Trapped_Args *args, +extern u32 mgrwrap_get_process_resources_info(union trapped_args *args, void *pr_ctxt); /* CPRC (Processor) wrapper Functions */ -extern u32 procwrap_attach(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_ctrl(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_detach(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_enum_resources(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_get_state(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_get_trace(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_load(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_register_notify(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_start(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_reserve_memory(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_un_reserve_memory(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_map(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_un_map(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_flush_memory(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_stop(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_invalidate_memory(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_begin_dma(union Trapped_Args *args, void *pr_ctxt); -extern u32 procwrap_end_dma(union Trapped_Args *args, void *pr_ctxt); +extern u32 procwrap_attach(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_ctrl(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_detach(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_enum_node_info(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_enum_resources(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_get_state(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_get_trace(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_load(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_register_notify(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_start(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_reserve_memory(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_un_reserve_memory(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_map(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_un_map(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_flush_memory(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_stop(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_invalidate_memory(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_begin_dma(union trapped_args *args, void *pr_ctxt); +extern u32 procwrap_end_dma(union trapped_args *args, void *pr_ctxt); /* NODE wrapper functions */ -extern u32 nodewrap_allocate(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_alloc_msg_buf(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_change_priority(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_connect(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_create(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_delete(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_free_msg_buf(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_get_attr(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_get_message(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_pause(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_put_message(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_register_notify(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_run(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_terminate(union Trapped_Args *args, void *pr_ctxt); -extern u32 nodewrap_get_uuid_props(union Trapped_Args *args, void *pr_ctxt); +extern u32 nodewrap_allocate(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_alloc_msg_buf(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_change_priority(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_connect(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_create(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_delete(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_free_msg_buf(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_get_attr(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_get_message(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_pause(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_put_message(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_register_notify(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_run(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_terminate(union trapped_args *args, void *pr_ctxt); +extern u32 nodewrap_get_uuid_props(union trapped_args *args, void *pr_ctxt); /* STRM wrapper functions */ -extern u32 strmwrap_allocate_buffer(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_close(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_free_buffer(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_get_event_handle(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_get_info(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_idle(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_issue(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_open(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_reclaim(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_register_notify(union Trapped_Args *args, void *pr_ctxt); -extern u32 strmwrap_select(union Trapped_Args *args, void *pr_ctxt); +extern u32 strmwrap_allocate_buffer(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_close(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_free_buffer(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_get_event_handle(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_get_info(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_idle(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_issue(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_open(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_reclaim(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_register_notify(union trapped_args *args, void *pr_ctxt); +extern u32 strmwrap_select(union trapped_args *args, void *pr_ctxt); -extern u32 cmmwrap_calloc_buf(union Trapped_Args *args, void *pr_ctxt); -extern u32 cmmwrap_free_buf(union Trapped_Args *args, void *pr_ctxt); -extern u32 cmmwrap_get_handle(union Trapped_Args *args, void *pr_ctxt); -extern u32 cmmwrap_get_info(union Trapped_Args *args, void *pr_ctxt); +extern u32 cmmwrap_calloc_buf(union trapped_args *args, void *pr_ctxt); +extern u32 cmmwrap_free_buf(union trapped_args *args, void *pr_ctxt); +extern u32 cmmwrap_get_handle(union trapped_args *args, void *pr_ctxt); +extern u32 cmmwrap_get_info(union trapped_args *args, void *pr_ctxt); #endif /* DSPAPI_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h index cb7e18b..c08cc00 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h @@ -34,7 +34,7 @@ extern int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr); extern int bridge_chnl_open(OUT struct chnl_object **chnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, - u32 uChnlId, + u32 ch_id, CONST IN OPTIONAL struct chnl_attr *pattrs); @@ -57,7 +57,7 @@ extern int bridge_chnl_get_info(struct chnl_object *chnl_obj, OUT struct chnl_info *channel_info); extern int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, - u32 uChnlID, OUT struct chnl_mgrinfo + u32 ch_id, OUT struct chnl_mgrinfo *mgr_info); extern int bridge_chnl_idle(struct chnl_object *chnl_obj, diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index ed6388e..1e4049b 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -373,7 +373,7 @@ typedef void (*fxn_deh_notify) (struct deh_mgr *hdeh_mgr, * CHNL_GetMgr(). * chnl_mode: One of {CHNL_MODETODSP, CHNL_MODEFROMDSP} specifies * direction of data transfer. - * uChnlId: If CHNL_PICKFREE is specified, the channel manager will + * ch_id: If CHNL_PICKFREE is specified, the channel manager will * select a free channel id (default); * otherwise this field specifies the id of the channel. * pattrs: Channel attributes. Attribute fields are as follows: @@ -411,7 +411,7 @@ typedef int(*fxn_chnl_open) (OUT struct chnl_object **chnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, - u32 uChnlId, + u32 ch_id, CONST IN OPTIONAL struct chnl_attr * pattrs); @@ -569,7 +569,7 @@ typedef int(*fxn_chnl_getinfo) (struct chnl_object *chnl_obj, * Retrieve information related to the channel manager. * Parameters: * hchnl_mgr: Handle to a valid channel manager, or NULL. - * uChnlID: Channel ID. + * ch_id: Channel ID. * mgr_info: Location to store channel manager info. * Returns: * 0: Success; @@ -582,7 +582,7 @@ typedef int(*fxn_chnl_getinfo) (struct chnl_object *chnl_obj, */ typedef int(*fxn_chnl_getmgrinfo) (struct chnl_mgr * hchnl_mgr, - u32 uChnlID, + u32 ch_id, OUT struct chnl_mgrinfo *mgr_info); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index a7fded7..538fbcd 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -141,20 +141,20 @@ extern void iosm_schedule(struct io_mgr *hio_mgr); * Initialize DSP DMA channel descriptor. * Parameters: * hio_mgr: Handle to a I/O manager. - * uDDMAChnlId: DDMA channel identifier. + * ddma_chnl_id: DDMA channel identifier. * uNumDesc: Number of buffer descriptors(equals # of IOReqs & * Chirps) * dsp: Dsp address; * Returns: * Requires: - * uDDMAChnlId < DDMA_MAXDDMACHNLS + * ddma_chnl_id < DDMA_MAXDDMACHNLS * uNumDesc > 0 * pVa != NULL * pDspPa != NULL * * Ensures: */ -extern void io_ddma_init_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId, +extern void io_ddma_init_chnl_desc(struct io_mgr *hio_mgr, u32 ddma_chnl_id, u32 uNumDesc, void *dsp); /* @@ -163,13 +163,13 @@ extern void io_ddma_init_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId, * Clear DSP DMA channel descriptor. * Parameters: * hio_mgr: Handle to a I/O manager. - * uDDMAChnlId: DDMA channel identifier. + * ddma_chnl_id: DDMA channel identifier. * Returns: * Requires: - * uDDMAChnlId < DDMA_MAXDDMACHNLS + * ddma_chnl_id < DDMA_MAXDDMACHNLS * Ensures: */ -extern void io_ddma_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId); +extern void io_ddma_clear_chnl_desc(struct io_mgr *hio_mgr, u32 ddma_chnl_id); /* * ======== io_ddma_request_chnl ======== @@ -205,7 +205,7 @@ extern void io_ddma_request_chnl(struct io_mgr *hio_mgr, * uZId: zero-copy channel identifier. * Returns: * Requires: - * uDDMAChnlId < DDMA_MAXZCPYCHNLS + * ddma_chnl_id < DDMA_MAXZCPYCHNLS * hio_mgr != Null * Ensures: */ @@ -217,14 +217,14 @@ extern void io_ddzc_init_chnl_desc(struct io_mgr *hio_mgr, u32 uZId); * Clear DSP ZC channel descriptor. * Parameters: * hio_mgr: Handle to a I/O manager. - * uChnlId: ZC channel identifier. + * ch_id: ZC channel identifier. * Returns: * Requires: * hio_mgr is valid - * uChnlId < DDMA_MAXZCPYCHNLS + * ch_id < DDMA_MAXZCPYCHNLS * Ensures: */ -extern void io_ddzc_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uChnlId); +extern void io_ddzc_clear_chnl_desc(struct io_mgr *hio_mgr, u32 ch_id); /* * ======== io_ddzc_request_chnl ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/proc.h b/drivers/staging/tidspbridge/include/dspbridge/proc.h index 5583bd5..e7a9510 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/proc.h +++ b/drivers/staging/tidspbridge/include/dspbridge/proc.h @@ -365,18 +365,18 @@ extern int proc_register_notify(void *hprocessor, * Notify the Processor Clients * Parameters: * proc : The processor handle. - * uEvents : Event to be notified about. + * events : Event to be notified about. * Returns: * 0 : Success. * -EFAULT : Invalid processor handle. * -EPERM : Failure to Set or Reset the Event * Requires: - * uEvents is Supported or Valid type of Event + * events is Supported or Valid type of Event * proc is a valid handle * PROC Initialized. * Ensures: */ -extern int proc_notify_clients(void *proc, u32 uEvents); +extern int proc_notify_clients(void *proc, u32 events); /* * ======== proc_notify_all_clients ======== @@ -384,13 +384,13 @@ extern int proc_notify_clients(void *proc, u32 uEvents); * Notify the Processor Clients * Parameters: * proc : The processor handle. - * uEvents : Event to be notified about. + * events : Event to be notified about. * Returns: * 0 : Success. * -EFAULT : Invalid processor handle. * -EPERM : Failure to Set or Reset the Event * Requires: - * uEvents is Supported or Valid type of Event + * events is Supported or Valid type of Event * proc is a valid handle * PROC Initialized. * Ensures: @@ -398,7 +398,7 @@ extern int proc_notify_clients(void *proc, u32 uEvents); * NODE And STRM would use this function to notify their clients * about the state changes in NODE or STRM. */ -extern int proc_notify_all_clients(void *proc, u32 uEvents); +extern int proc_notify_all_clients(void *proc, u32 events); /* * ======== proc_start ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/pwr.h b/drivers/staging/tidspbridge/include/dspbridge/pwr.h index 63ccf8c..9f32c89 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/pwr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/pwr.h @@ -25,7 +25,7 @@ * Signal the DSP to go to sleep. * * Parameters: - * sleepCode: New sleep state for DSP. (Initially, valid codes + * sleep_code: New sleep state for DSP. (Initially, valid codes * are PWR_DEEPSLEEP or PWR_EMERGENCYDEEPSLEEP; both of * these codes will simply put the DSP in deep sleep.) * @@ -39,13 +39,13 @@ * Returns: * 0: Success. * 0: Success, but the DSP was already asleep. - * -EINVAL: The specified sleepCode is not supported. + * -EINVAL: The specified sleep_code is not supported. * -ETIME: A timeout occured while waiting for DSP sleep * confirmation. * -EPERM: General failure, unable to send sleep command to * the DSP. */ -extern int pwr_sleep_dsp(IN CONST u32 sleepCode, IN CONST u32 timeout); +extern int pwr_sleep_dsp(IN CONST u32 sleep_code, IN CONST u32 timeout); /* * ======== pwr_wake_dsp ======== diff --git a/drivers/staging/tidspbridge/pmgr/dspapi.c b/drivers/staging/tidspbridge/pmgr/dspapi.c index 7597210..7ff2bd0 100644 --- a/drivers/staging/tidspbridge/pmgr/dspapi.c +++ b/drivers/staging/tidspbridge/pmgr/dspapi.c @@ -69,7 +69,7 @@ /* Device IOCtl function pointer */ struct api_cmd { - u32(*fxn) (union Trapped_Args *args, void *pr_ctxt); + u32(*fxn) (union trapped_args *args, void *pr_ctxt); u32 dw_index; }; @@ -208,10 +208,10 @@ static inline void _cp_to_usr(void __user *to, const void *from, * Purpose: * Call the (wrapper) function for the corresponding API IOCTL. */ -inline int api_call_dev_ioctl(u32 cmd, union Trapped_Args *args, +inline int api_call_dev_ioctl(u32 cmd, union trapped_args *args, u32 *result, void *pr_ctxt) { - u32(*ioctl_cmd) (union Trapped_Args *args, void *pr_ctxt) = NULL; + u32(*ioctl_cmd) (union trapped_args *args, void *pr_ctxt) = NULL; int i; if (_IOC_TYPE(cmd) != DB) { @@ -411,7 +411,7 @@ int api_init_complete2(void) /* * ======== mgrwrap_enum_node_info ======== */ -u32 mgrwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt) +u32 mgrwrap_enum_node_info(union trapped_args *args, void *pr_ctxt) { u8 *pndb_props; u32 num_nodes; @@ -443,7 +443,7 @@ u32 mgrwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt) /* * ======== mgrwrap_enum_proc_info ======== */ -u32 mgrwrap_enum_proc_info(union Trapped_Args *args, void *pr_ctxt) +u32 mgrwrap_enum_proc_info(union trapped_args *args, void *pr_ctxt) { u8 *processor_info; u8 num_procs; @@ -477,7 +477,7 @@ u32 mgrwrap_enum_proc_info(union Trapped_Args *args, void *pr_ctxt) /* * ======== mgrwrap_register_object ======== */ -u32 mgrwrap_register_object(union Trapped_Args *args, void *pr_ctxt) +u32 mgrwrap_register_object(union trapped_args *args, void *pr_ctxt) { u32 ret; struct dsp_uuid uuid_obj; @@ -517,7 +517,7 @@ func_end: /* * ======== mgrwrap_unregister_object ======== */ -u32 mgrwrap_unregister_object(union Trapped_Args *args, void *pr_ctxt) +u32 mgrwrap_unregister_object(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_uuid uuid_obj; @@ -537,7 +537,7 @@ func_end: /* * ======== mgrwrap_wait_for_bridge_events ======== */ -u32 mgrwrap_wait_for_bridge_events(union Trapped_Args *args, void *pr_ctxt) +u32 mgrwrap_wait_for_bridge_events(union trapped_args *args, void *pr_ctxt) { int status = 0, real_status = 0; struct dsp_notification *anotifications[MAX_EVENTS]; @@ -572,7 +572,7 @@ u32 mgrwrap_wait_for_bridge_events(union Trapped_Args *args, void *pr_ctxt) /* * ======== MGRWRAP_GetProcessResourceInfo ======== */ -u32 __deprecated mgrwrap_get_process_resources_info(union Trapped_Args * args, +u32 __deprecated mgrwrap_get_process_resources_info(union trapped_args * args, void *pr_ctxt) { pr_err("%s: deprecated dspbridge ioctl\n", __func__); @@ -582,7 +582,7 @@ u32 __deprecated mgrwrap_get_process_resources_info(union Trapped_Args * args, /* * ======== procwrap_attach ======== */ -u32 procwrap_attach(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_attach(union trapped_args *args, void *pr_ctxt) { void *processor; int status = 0; @@ -608,7 +608,7 @@ func_end: /* * ======== procwrap_ctrl ======== */ -u32 procwrap_ctrl(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_ctrl(union trapped_args *args, void *pr_ctxt) { u32 cb_data_size, __user * psize = (u32 __user *) args->args_proc_ctrl.pargs; @@ -645,7 +645,7 @@ func_end: /* * ======== procwrap_detach ======== */ -u32 __deprecated procwrap_detach(union Trapped_Args * args, void *pr_ctxt) +u32 __deprecated procwrap_detach(union trapped_args * args, void *pr_ctxt) { /* proc_detach called at bridge_release only */ pr_err("%s: deprecated dspbridge ioctl\n", __func__); @@ -655,7 +655,7 @@ u32 __deprecated procwrap_detach(union Trapped_Args * args, void *pr_ctxt) /* * ======== procwrap_enum_node_info ======== */ -u32 procwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_enum_node_info(union trapped_args *args, void *pr_ctxt) { int status; void *node_tab[MAX_NODES]; @@ -678,7 +678,7 @@ u32 procwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt) return status; } -u32 procwrap_end_dma(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_end_dma(union trapped_args *args, void *pr_ctxt) { int status; @@ -692,7 +692,7 @@ u32 procwrap_end_dma(union Trapped_Args *args, void *pr_ctxt) return status; } -u32 procwrap_begin_dma(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_begin_dma(union trapped_args *args, void *pr_ctxt) { int status; @@ -709,7 +709,7 @@ u32 procwrap_begin_dma(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_flush_memory ======== */ -u32 procwrap_flush_memory(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_flush_memory(union trapped_args *args, void *pr_ctxt) { int status; @@ -727,7 +727,7 @@ u32 procwrap_flush_memory(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_invalidate_memory ======== */ -u32 procwrap_invalidate_memory(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_invalidate_memory(union trapped_args *args, void *pr_ctxt) { int status; @@ -741,7 +741,7 @@ u32 procwrap_invalidate_memory(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_enum_resources ======== */ -u32 procwrap_enum_resources(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_enum_resources(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_resourceinfo resource_info; @@ -767,7 +767,7 @@ u32 procwrap_enum_resources(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_get_state ======== */ -u32 procwrap_get_state(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_get_state(union trapped_args *args, void *pr_ctxt) { int status; struct dsp_processorstate proc_state; @@ -788,7 +788,7 @@ u32 procwrap_get_state(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_get_trace ======== */ -u32 procwrap_get_trace(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_get_trace(union trapped_args *args, void *pr_ctxt) { int status; u8 *pbuf; @@ -814,7 +814,7 @@ u32 procwrap_get_trace(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_load ======== */ -u32 procwrap_load(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_load(union trapped_args *args, void *pr_ctxt) { s32 i, len; int status = 0; @@ -930,7 +930,7 @@ func_cont: /* * ======== procwrap_map ======== */ -u32 procwrap_map(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_map(union trapped_args *args, void *pr_ctxt) { int status; void *map_addr; @@ -957,7 +957,7 @@ u32 procwrap_map(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_register_notify ======== */ -u32 procwrap_register_notify(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_register_notify(union trapped_args *args, void *pr_ctxt) { int status; struct dsp_notification notification; @@ -979,7 +979,7 @@ u32 procwrap_register_notify(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_reserve_memory ======== */ -u32 procwrap_reserve_memory(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_reserve_memory(union trapped_args *args, void *pr_ctxt) { int status; void *prsv_addr; @@ -1004,7 +1004,7 @@ u32 procwrap_reserve_memory(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_start ======== */ -u32 procwrap_start(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_start(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1015,7 +1015,7 @@ u32 procwrap_start(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_un_map ======== */ -u32 procwrap_un_map(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_un_map(union trapped_args *args, void *pr_ctxt) { int status; @@ -1027,7 +1027,7 @@ u32 procwrap_un_map(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_un_reserve_memory ======== */ -u32 procwrap_un_reserve_memory(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_un_reserve_memory(union trapped_args *args, void *pr_ctxt) { int status; @@ -1040,7 +1040,7 @@ u32 procwrap_un_reserve_memory(union Trapped_Args *args, void *pr_ctxt) /* * ======== procwrap_stop ======== */ -u32 procwrap_stop(union Trapped_Args *args, void *pr_ctxt) +u32 procwrap_stop(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1052,7 +1052,7 @@ u32 procwrap_stop(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_allocate ======== */ -u32 nodewrap_allocate(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_allocate(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_uuid node_uuid; @@ -1111,7 +1111,7 @@ func_cont: /* * ======== nodewrap_alloc_msg_buf ======== */ -u32 nodewrap_alloc_msg_buf(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_alloc_msg_buf(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_bufferattr *pattr = NULL; @@ -1141,7 +1141,7 @@ u32 nodewrap_alloc_msg_buf(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_change_priority ======== */ -u32 nodewrap_change_priority(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_change_priority(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1154,7 +1154,7 @@ u32 nodewrap_change_priority(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_connect ======== */ -u32 nodewrap_connect(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_connect(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_strmattr attrs; @@ -1204,7 +1204,7 @@ func_cont: /* * ======== nodewrap_create ======== */ -u32 nodewrap_create(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_create(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1216,7 +1216,7 @@ u32 nodewrap_create(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_delete ======== */ -u32 nodewrap_delete(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_delete(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1228,7 +1228,7 @@ u32 nodewrap_delete(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_free_msg_buf ======== */ -u32 nodewrap_free_msg_buf(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_free_msg_buf(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_bufferattr *pattr = NULL; @@ -1255,7 +1255,7 @@ u32 nodewrap_free_msg_buf(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_get_attr ======== */ -u32 nodewrap_get_attr(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_get_attr(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_nodeattr attr; @@ -1270,7 +1270,7 @@ u32 nodewrap_get_attr(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_get_message ======== */ -u32 nodewrap_get_message(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_get_message(union trapped_args *args, void *pr_ctxt) { int status; struct dsp_msg msg; @@ -1286,7 +1286,7 @@ u32 nodewrap_get_message(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_pause ======== */ -u32 nodewrap_pause(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_pause(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1298,7 +1298,7 @@ u32 nodewrap_pause(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_put_message ======== */ -u32 nodewrap_put_message(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_put_message(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_msg msg; @@ -1317,7 +1317,7 @@ u32 nodewrap_put_message(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_register_notify ======== */ -u32 nodewrap_register_notify(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_register_notify(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_notification notification; @@ -1343,7 +1343,7 @@ u32 nodewrap_register_notify(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_run ======== */ -u32 nodewrap_run(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_run(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1355,7 +1355,7 @@ u32 nodewrap_run(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_terminate ======== */ -u32 nodewrap_terminate(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_terminate(union trapped_args *args, void *pr_ctxt) { int status; int tempstatus; @@ -1370,7 +1370,7 @@ u32 nodewrap_terminate(union Trapped_Args *args, void *pr_ctxt) /* * ======== nodewrap_get_uuid_props ======== */ -u32 nodewrap_get_uuid_props(union Trapped_Args *args, void *pr_ctxt) +u32 nodewrap_get_uuid_props(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_uuid node_uuid; @@ -1397,7 +1397,7 @@ func_cont: /* * ======== strmwrap_allocate_buffer ======== */ -u32 strmwrap_allocate_buffer(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_allocate_buffer(union trapped_args *args, void *pr_ctxt) { int status; u8 **ap_buffer = NULL; @@ -1428,7 +1428,7 @@ u32 strmwrap_allocate_buffer(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_close ======== */ -u32 strmwrap_close(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_close(union trapped_args *args, void *pr_ctxt) { return strm_close(args->args_strm_close.hstream, pr_ctxt); } @@ -1436,7 +1436,7 @@ u32 strmwrap_close(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_free_buffer ======== */ -u32 strmwrap_free_buffer(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_free_buffer(union trapped_args *args, void *pr_ctxt) { int status = 0; u8 **ap_buffer = NULL; @@ -1464,7 +1464,7 @@ u32 strmwrap_free_buffer(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_get_event_handle ======== */ -u32 __deprecated strmwrap_get_event_handle(union Trapped_Args * args, +u32 __deprecated strmwrap_get_event_handle(union trapped_args * args, void *pr_ctxt) { pr_err("%s: deprecated dspbridge ioctl\n", __func__); @@ -1474,7 +1474,7 @@ u32 __deprecated strmwrap_get_event_handle(union Trapped_Args * args, /* * ======== strmwrap_get_info ======== */ -u32 strmwrap_get_info(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_get_info(union trapped_args *args, void *pr_ctxt) { int status = 0; struct stream_info strm_info; @@ -1501,7 +1501,7 @@ u32 strmwrap_get_info(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_idle ======== */ -u32 strmwrap_idle(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_idle(union trapped_args *args, void *pr_ctxt) { u32 ret; @@ -1514,7 +1514,7 @@ u32 strmwrap_idle(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_issue ======== */ -u32 strmwrap_issue(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_issue(union trapped_args *args, void *pr_ctxt) { int status = 0; @@ -1536,7 +1536,7 @@ u32 strmwrap_issue(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_open ======== */ -u32 strmwrap_open(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_open(union trapped_args *args, void *pr_ctxt) { int status = 0; struct strm_attr attr; @@ -1565,7 +1565,7 @@ u32 strmwrap_open(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_reclaim ======== */ -u32 strmwrap_reclaim(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_reclaim(union trapped_args *args, void *pr_ctxt) { int status = 0; u8 *buf_ptr; @@ -1590,7 +1590,7 @@ u32 strmwrap_reclaim(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_register_notify ======== */ -u32 strmwrap_register_notify(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_register_notify(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_notification notification; @@ -1612,7 +1612,7 @@ u32 strmwrap_register_notify(union Trapped_Args *args, void *pr_ctxt) /* * ======== strmwrap_select ======== */ -u32 strmwrap_select(union Trapped_Args *args, void *pr_ctxt) +u32 strmwrap_select(union trapped_args *args, void *pr_ctxt) { u32 mask; struct strm_object *strm_tab[MAX_STREAMS]; @@ -1636,7 +1636,7 @@ u32 strmwrap_select(union Trapped_Args *args, void *pr_ctxt) /* * ======== cmmwrap_calloc_buf ======== */ -u32 __deprecated cmmwrap_calloc_buf(union Trapped_Args * args, void *pr_ctxt) +u32 __deprecated cmmwrap_calloc_buf(union trapped_args * args, void *pr_ctxt) { /* This operation is done in kernel */ pr_err("%s: deprecated dspbridge ioctl\n", __func__); @@ -1646,7 +1646,7 @@ u32 __deprecated cmmwrap_calloc_buf(union Trapped_Args * args, void *pr_ctxt) /* * ======== cmmwrap_free_buf ======== */ -u32 __deprecated cmmwrap_free_buf(union Trapped_Args * args, void *pr_ctxt) +u32 __deprecated cmmwrap_free_buf(union trapped_args * args, void *pr_ctxt) { /* This operation is done in kernel */ pr_err("%s: deprecated dspbridge ioctl\n", __func__); @@ -1656,7 +1656,7 @@ u32 __deprecated cmmwrap_free_buf(union Trapped_Args * args, void *pr_ctxt) /* * ======== cmmwrap_get_handle ======== */ -u32 cmmwrap_get_handle(union Trapped_Args *args, void *pr_ctxt) +u32 cmmwrap_get_handle(union trapped_args *args, void *pr_ctxt) { int status = 0; struct cmm_object *hcmm_mgr; @@ -1671,7 +1671,7 @@ u32 cmmwrap_get_handle(union Trapped_Args *args, void *pr_ctxt) /* * ======== cmmwrap_get_info ======== */ -u32 cmmwrap_get_info(union Trapped_Args *args, void *pr_ctxt) +u32 cmmwrap_get_info(union trapped_args *args, void *pr_ctxt) { int status = 0; struct cmm_info cmm_info_obj; diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index dc0c629..03a2317 100755 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -1012,14 +1012,15 @@ static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * phys_addr) * Purpose: * Allocate physically contiguous, uncached memory */ -void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, OUT u32 * physical_address) +void *mem_alloc_phys_mem(u32 byte_size, u32 align_mask, + OUT u32 *physical_address) { void *va_mem = NULL; dma_addr_t pa_mem; if (byte_size > 0) { if (ext_phys_mem_pool_enabled) { - va_mem = mem_ext_phys_mem_alloc(byte_size, ulAlign, + va_mem = mem_ext_phys_mem_alloc(byte_size, align_mask, (u32 *) &pa_mem); } else va_mem = dma_alloc_coherent(NULL, byte_size, &pa_mem, diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c b/drivers/staging/tidspbridge/rmgr/drv_interface.c index b0fd38e..dae16f8 --- a/drivers/staging/tidspbridge/rmgr/drv_interface.c +++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c @@ -561,7 +561,7 @@ static long bridge_ioctl(struct file *filp, unsigned int code, { int status; u32 retval = 0; - union Trapped_Args buf_in; + union trapped_args buf_in; DBC_REQUIRE(filp != NULL); #ifdef CONFIG_TIDSPBRIDGE_RECOVERY @@ -581,8 +581,8 @@ static long bridge_ioctl(struct file *filp, unsigned int code, goto err; } - status = copy_from_user(&buf_in, (union Trapped_Args *)args, - sizeof(union Trapped_Args)); + status = copy_from_user(&buf_in, (union trapped_args *)args, + sizeof(union trapped_args)); if (!status) { status = api_call_dev_ioctl(code, &buf_in, &retval, diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 198b698..46fc765 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -296,7 +296,7 @@ static s32 fake_ovly_write(void *handle, u32 dsp_address, void *buf, u32 bytes, static void free_sects(struct nldr_object *nldr_obj, struct ovly_sect *phase_sects, u16 alloc_num); static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, - char *symName, struct dbll_sym_val **sym); + char *sym_name, struct dbll_sym_val **sym); static int load_lib(struct nldr_nodeobject *nldr_node_obj, struct lib_node *root, struct dsp_uuid uuid, bool root_prstnt, @@ -306,7 +306,7 @@ static int load_ovly(struct nldr_nodeobject *nldr_node_obj, enum nldr_phase phase); static int remote_alloc(void **ref, u16 mem_sect_type, u32 size, u32 align, u32 *dsp_address, - OPTIONAL s32 segmentId, + OPTIONAL s32 segmnt_id, OPTIONAL s32 req, bool reserve); static int remote_free(void **ref, u16 space, u32 dsp_address, u32 size, bool reserve); @@ -1625,7 +1625,7 @@ func_end: */ static int remote_alloc(void **ref, u16 space, u32 size, u32 align, u32 *dsp_address, - OPTIONAL s32 segmentId, OPTIONAL s32 req, + OPTIONAL s32 segmnt_id, OPTIONAL s32 req, bool reserve) { struct nldr_nodeobject *hnode = (struct nldr_nodeobject *)ref; @@ -1651,9 +1651,9 @@ static int remote_alloc(void **ref, u16 space, u32 size, /* Modify memory 'align' to account for DSP cache line size */ align = find_lcm(GEM_CACHE_LINE_SIZE, align); dev_dbg(bridge, "%s: memory align to 0x%x\n", __func__, align); - if (segmentId != -1) { - rmm_addr_obj->segid = segmentId; - segid = segmentId; + if (segmnt_id != -1) { + rmm_addr_obj->segid = segmnt_id; + segid = segmnt_id; mem_load_req = req; } else { switch (hnode->phase) { diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index eb81645..aa48fa8 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -111,7 +111,7 @@ DEFINE_MUTEX(proc_lock); /* For critical sections */ static int proc_monitor(struct proc_object *hprocessor); static s32 get_envp_count(char **envp); static char **prepend_envp(char **new_envp, char **envp, s32 envp_elems, - s32 cnew_envp, char *szVar); + s32 cnew_envp, char *sz_var); /* remember mapping information */ static struct dmm_map_object *add_mapping_info(struct process_context *pr_ctxt, @@ -1848,14 +1848,14 @@ static s32 get_envp_count(char **envp) * copy in the existing var=value pairs in the old envp array. */ static char **prepend_envp(char **new_envp, char **envp, s32 envp_elems, - s32 cnew_envp, char *szVar) + s32 cnew_envp, char *sz_var) { char **pp_envp = new_envp; DBC_REQUIRE(new_envp); /* Prepend new environ var=value string */ - *new_envp++ = szVar; + *new_envp++ = sz_var; /* Copy user's environment into our own. */ while (envp_elems--) @@ -1873,20 +1873,20 @@ static char **prepend_envp(char **new_envp, char **envp, s32 envp_elems, * Purpose: * Notify the processor the events. */ -int proc_notify_clients(void *proc, u32 uEvents) +int proc_notify_clients(void *proc, u32 events) { int status = 0; struct proc_object *p_proc_object = (struct proc_object *)proc; DBC_REQUIRE(p_proc_object); - DBC_REQUIRE(IS_VALID_PROC_EVENT(uEvents)); + DBC_REQUIRE(IS_VALID_PROC_EVENT(events)); DBC_REQUIRE(refs > 0); if (!p_proc_object) { status = -EFAULT; goto func_end; } - ntfy_notify(p_proc_object->ntfy_obj, uEvents); + ntfy_notify(p_proc_object->ntfy_obj, events); func_end: return status; } @@ -1897,12 +1897,12 @@ func_end: * Notify the processor the events. This includes notifying all clients * attached to a particulat DSP. */ -int proc_notify_all_clients(void *proc, u32 uEvents) +int proc_notify_all_clients(void *proc, u32 events) { int status = 0; struct proc_object *p_proc_object = (struct proc_object *)proc; - DBC_REQUIRE(IS_VALID_PROC_EVENT(uEvents)); + DBC_REQUIRE(IS_VALID_PROC_EVENT(events)); DBC_REQUIRE(refs > 0); if (!p_proc_object) { @@ -1910,7 +1910,7 @@ int proc_notify_all_clients(void *proc, u32 uEvents) goto func_end; } - dev_notify_clients(p_proc_object->hdev_obj, uEvents); + dev_notify_clients(p_proc_object->hdev_obj, events); func_end: return status; diff --git a/drivers/staging/tidspbridge/rmgr/pwr.c b/drivers/staging/tidspbridge/rmgr/pwr.c index ec6d181..2d81743 100644 --- a/drivers/staging/tidspbridge/rmgr/pwr.c +++ b/drivers/staging/tidspbridge/rmgr/pwr.c @@ -36,7 +36,7 @@ * ======== pwr_sleep_dsp ======== * Send command to DSP to enter sleep state. */ -int pwr_sleep_dsp(IN CONST u32 sleepCode, IN CONST u32 timeout) +int pwr_sleep_dsp(IN CONST u32 sleep_code, IN CONST u32 timeout) { struct bridge_drv_interface *intf_fxns; struct bridge_dev_context *dw_context; @@ -59,9 +59,9 @@ int pwr_sleep_dsp(IN CONST u32 sleepCode, IN CONST u32 timeout) &intf_fxns))) { continue; } - if (sleepCode == PWR_DEEPSLEEP) + if (sleep_code == PWR_DEEPSLEEP) ioctlcode = BRDIOCTL_DEEPSLEEP; - else if (sleepCode == PWR_EMERGENCYDEEPSLEEP) + else if (sleep_code == PWR_EMERGENCYDEEPSLEEP) ioctlcode = BRDIOCTL_EMERGENCYSLEEP; else status = -EINVAL; From patchwork Sat Jul 10 02:24:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111195 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Sktf002447 for ; Sat, 10 Jul 2010 02:28:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753437Ab0GJCZo (ORCPT ); Fri, 9 Jul 2010 22:25:44 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:45294 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752892Ab0GJCZX (ORCPT ); Fri, 9 Jul 2010 22:25:23 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PIKR007091 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:18 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PH3Z009820; Fri, 9 Jul 2010 21:25:17 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68R021595; Fri, 9 Jul 2010 21:25:16 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 15/15] staging:ti dspbridge: make variables in prototypes match within functions definitions Date: Fri, 9 Jul 2010 21:24:09 -0500 Message-Id: <1278728649-21012-16-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-15-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> <1278728649-21012-10-git-send-email-rene.sapiens@ti.com> <1278728649-21012-11-git-send-email-rene.sapiens@ti.com> <1278728649-21012-12-git-send-email-rene.sapiens@ti.com> <1278728649-21012-13-git-send-email-rene.sapiens@ti.com> <1278728649-21012-14-git-send-email-rene.sapiens@ti.com> <1278728649-21012-15-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:50 +0000 (UTC) This patch renames the variables in the parameter lists and in the function definitions to make them match. Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/chnl_sm.c | 2 +- drivers/staging/tidspbridge/core/io_sm.c | 20 +++--- drivers/staging/tidspbridge/core/tiomap3430.c | 18 +++--- drivers/staging/tidspbridge/core/tiomap_io.c | 8 +- drivers/staging/tidspbridge/core/tiomap_io.h | 2 +- drivers/staging/tidspbridge/dynload/reloc.c | 4 +- drivers/staging/tidspbridge/hw/hw_mmu.h | 2 +- .../staging/tidspbridge/include/dspbridge/cmm.h | 2 +- .../staging/tidspbridge/include/dspbridge/cod.h | 2 +- .../staging/tidspbridge/include/dspbridge/dbll.h | 10 ++-- .../staging/tidspbridge/include/dspbridge/disp.h | 8 +- .../staging/tidspbridge/include/dspbridge/drv.h | 12 ++-- .../staging/tidspbridge/include/dspbridge/dspmsg.h | 2 +- .../staging/tidspbridge/include/dspbridge/io_sm.h | 4 +- .../staging/tidspbridge/include/dspbridge/mgr.h | 2 +- .../staging/tidspbridge/include/dspbridge/proc.h | 4 +- .../include/dspbridge/resourcecleanup.h | 29 +++++---- .../staging/tidspbridge/include/dspbridge/rmm.h | 4 +- drivers/staging/tidspbridge/pmgr/cmm.c | 12 ++-- drivers/staging/tidspbridge/pmgr/cod.c | 63 ++++++++++--------- drivers/staging/tidspbridge/pmgr/dbll.c | 33 +++++----- drivers/staging/tidspbridge/pmgr/dmm.c | 4 +- drivers/staging/tidspbridge/rmgr/drv.c | 20 +++--- drivers/staging/tidspbridge/rmgr/drv_interface.h | 7 +- drivers/staging/tidspbridge/rmgr/dspdrv.c | 6 +- drivers/staging/tidspbridge/rmgr/nldr.c | 44 ++++++++------ drivers/staging/tidspbridge/rmgr/node.c | 18 +++--- drivers/staging/tidspbridge/rmgr/proc.c | 20 +++--- drivers/staging/tidspbridge/rmgr/rmm.c | 11 ++-- drivers/staging/tidspbridge/services/cfg.c | 6 +- 30 files changed, 195 insertions(+), 184 deletions(-) mode change 100644 => 100755 drivers/staging/tidspbridge/hw/hw_mmu.h diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index ac393b8..813ea35 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -75,7 +75,7 @@ /* ----------------------------------- Function Prototypes */ static struct lst_list *create_chirp_list(u32 chirps); -static void free_chirp_list(struct lst_list *lst); +static void free_chirp_list(struct lst_list *chirp_list); static struct chnl_irp *make_new_chirp(void); diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 0292881..74835c5 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -1013,7 +1013,7 @@ void io_mbox_msg(u32 msg) * Request chanenel I/O from the DSP. Sets flags in shared memory, then * interrupts the DSP. */ -void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, +void io_request_chnl(struct io_mgr *io_manager, struct chnl_object *pchnl, u8 io_mode, OUT u16 *mbx_val) { struct chnl_mgr *chnl_mgr_obj; @@ -1021,8 +1021,8 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, if (!pchnl || !mbx_val) goto func_end; - chnl_mgr_obj = pio_mgr->hchnl_mgr; - sm = pio_mgr->shared_mem; + chnl_mgr_obj = io_manager->hchnl_mgr; + sm = io_manager->shared_mem; if (io_mode == IO_INPUT) { /* * Assertion fires if CHNL_AddIOReq() called on a stream @@ -1031,7 +1031,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, DBC_ASSERT((pchnl->dw_state == CHNL_STATEREADY) || (pchnl->dw_state == CHNL_STATEEOS)); /* Indicate to the DSP we have a buffer available for input */ - IO_OR_VALUE(pio_mgr->hbridge_context, struct shm, sm, + IO_OR_VALUE(io_manager->hbridge_context, struct shm, sm, host_free_mask, (1 << pchnl->chnl_id)); *mbx_val = MBX_PCPY_CLASS; } else if (io_mode == IO_OUTPUT) { @@ -1057,20 +1057,20 @@ func_end: * ======== iosm_schedule ======== * Schedule DPC for IO. */ -void iosm_schedule(struct io_mgr *pio_mgr) +void iosm_schedule(struct io_mgr *io_manager) { unsigned long flags; - if (!pio_mgr) + if (!io_manager) return; /* Increment count of DPC's pending. */ - spin_lock_irqsave(&pio_mgr->dpc_lock, flags); - pio_mgr->dpc_req++; - spin_unlock_irqrestore(&pio_mgr->dpc_lock, flags); + spin_lock_irqsave(&io_manager->dpc_lock, flags); + io_manager->dpc_req++; + spin_unlock_irqrestore(&io_manager->dpc_lock, flags); /* Schedule DPC */ - tasklet_schedule(&pio_mgr->dpc_tasklet); + tasklet_schedule(&io_manager->dpc_tasklet); } /* diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 8e3d92a..cf65af4 100755 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -74,17 +74,17 @@ #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT) /* Forward Declarations: */ -static int bridge_brd_monitor(struct bridge_dev_context *dev_context); -static int bridge_brd_read(struct bridge_dev_context *dev_context, +static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt); +static int bridge_brd_read(struct bridge_dev_context *dev_ctxt, OUT u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 mem_type); -static int bridge_brd_start(struct bridge_dev_context *dev_context, +static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, u32 dsp_addr); -static int bridge_brd_status(struct bridge_dev_context *dev_context, +static int bridge_brd_status(struct bridge_dev_context *dev_ctxt, int *board_state); -static int bridge_brd_stop(struct bridge_dev_context *dev_context); -static int bridge_brd_write(struct bridge_dev_context *dev_context, +static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt); +static int bridge_brd_write(struct bridge_dev_context *dev_ctxt, IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 mem_type); @@ -93,7 +93,7 @@ static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt, static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt, u32 dsp_dest_addr, u32 dsp_src_addr, u32 ul_num_bytes, u32 mem_type); -static int bridge_brd_mem_write(struct bridge_dev_context *dev_context, +static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt, IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 mem_type); static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt, @@ -108,14 +108,14 @@ static int bridge_dev_create(OUT struct bridge_dev_context IN struct cfg_hostres *config_param); static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, u32 dw_cmd, IN OUT void *pargs); -static int bridge_dev_destroy(struct bridge_dev_context *dev_context); +static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt); static u32 user_va2_pa(struct mm_struct *mm, u32 address); static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa, u32 va, u32 size, struct hw_mmu_map_attrs_t *map_attrs); static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va, u32 size, struct hw_mmu_map_attrs_t *attrs); -static int mem_map_vmalloc(struct bridge_dev_context *dev_ctxt, +static int mem_map_vmalloc(struct bridge_dev_context *dev_context, u32 ul_mpu_addr, u32 virt_addr, u32 ul_num_bytes, struct hw_mmu_map_attrs_t *hw_attrs); diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c index a3fcb02..3f6d084 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.c +++ b/drivers/staging/tidspbridge/core/tiomap_io.c @@ -178,13 +178,13 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt, * purpose: * Copies buffers to the DSP internal/external memory. */ -int write_dsp_data(struct bridge_dev_context *dev_ctxt, +int write_dsp_data(struct bridge_dev_context *dev_context, IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 mem_type) { u32 offset; - u32 dw_base_addr = dev_ctxt->dw_dsp_base_addr; - struct cfg_hostres *resources = dev_ctxt->resources; + u32 dw_base_addr = dev_context->dw_dsp_base_addr; + struct cfg_hostres *resources = dev_context->resources; int status = 0; u32 base1, base2, base3; base1 = OMAP_DSP_MEM1_SIZE; @@ -194,7 +194,7 @@ int write_dsp_data(struct bridge_dev_context *dev_ctxt, if (!resources) return -EPERM; - offset = dsp_addr - dev_ctxt->dw_dsp_start_add; + offset = dsp_addr - dev_context->dw_dsp_start_add; if (offset < base1) { dw_base_addr = MEM_LINEAR_ADDRESS(resources->dw_mem_base[2], resources->dw_mem_length[2]); diff --git a/drivers/staging/tidspbridge/core/tiomap_io.h b/drivers/staging/tidspbridge/core/tiomap_io.h index 8f9d072..5a26ea0 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.h +++ b/drivers/staging/tidspbridge/core/tiomap_io.h @@ -47,7 +47,7 @@ * Reads it from DSP External memory. The external memory for the DSP * is configured by the combination of DSP MMU and shm Memory manager in the CDB */ -extern int read_ext_dsp_data(struct bridge_dev_context *dev_context, +extern int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt, OUT u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 mem_type); diff --git a/drivers/staging/tidspbridge/dynload/reloc.c b/drivers/staging/tidspbridge/dynload/reloc.c index 316a38c..ec59777 100644 --- a/drivers/staging/tidspbridge/dynload/reloc.c +++ b/drivers/staging/tidspbridge/dynload/reloc.c @@ -162,7 +162,7 @@ static const u8 c60_scale[SCALE_MASK + 1] = { * Performs the specified relocation operation ************************************************************************* */ void dload_relocate(struct dload_state *dlthis, tgt_au_t * data, - struct reloc_record_t *rp, bool * tramps_genereted, + struct reloc_record_t *rp, bool *tramps_generated, bool second_pass) { rvalue val, reloc_amt, orig_val = 0; @@ -470,7 +470,7 @@ void dload_relocate(struct dload_state *dlthis, tgt_au_t * data, dlthis->image_offset + rp->vaddr); } else - *tramps_genereted = true; + *tramps_generated = true; } else { dload_error(dlthis, "Relocation value " FMT_UI32 " overflows %d bits in %s" diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h index 6ba133e..1458a2c --- a/drivers/staging/tidspbridge/hw/hw_mmu.h +++ b/drivers/staging/tidspbridge/hw/hw_mmu.h @@ -95,7 +95,7 @@ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, struct hw_mmu_map_attrs_t *map_attrs); extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, - u32 page_size, u32 virtual_addr); + u32 virtual_addr, u32 page_size); void hw_mmu_tlb_flush_all(const void __iomem *base); diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index 086ca25..24423cd 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -232,7 +232,7 @@ extern int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, s8 c_factor, unsigned int dw_dsp_base, u32 ul_dsp_size, - u32 *sgmt_id, u32 gpp_base_ba); + u32 *sgmt_id, u32 gpp_base_va); /* * ======== cmm_un_register_gppsm_seg ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index 3827646..abf3b38 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -91,7 +91,7 @@ extern void cod_close(struct cod_libraryobj *lib); * str_zl_file != NULL * Ensures: */ -extern int cod_create(OUT struct cod_manager **manager, +extern int cod_create(OUT struct cod_manager **mgr, char *str_zl_file, IN OPTIONAL CONST struct cod_attrs *attrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbll.h b/drivers/staging/tidspbridge/include/dspbridge/dbll.h index a197115..b018676 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dbll.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbll.h @@ -25,16 +25,16 @@ extern bool symbols_reloaded; -extern void dbll_close(struct dbll_library_obj *lib); +extern void dbll_close(struct dbll_library_obj *zl_lib); extern int dbll_create(struct dbll_tar_obj **target_obj, struct dbll_attrs *pattrs); extern void dbll_delete(struct dbll_tar_obj *target); extern void dbll_exit(void); -extern bool dbll_get_addr(struct dbll_library_obj *lib, char *name, +extern bool dbll_get_addr(struct dbll_library_obj *zl_lib, char *name, struct dbll_sym_val **sym_val); extern void dbll_get_attrs(struct dbll_tar_obj *target, struct dbll_attrs *pattrs); -extern bool dbll_get_c_addr(struct dbll_library_obj *lib, char *name, +extern bool dbll_get_c_addr(struct dbll_library_obj *zl_lib, char *name, struct dbll_sym_val **sym_val); extern int dbll_get_sect(struct dbll_library_obj *lib, char *name, u32 *paddr, u32 *psize); @@ -42,13 +42,13 @@ extern bool dbll_init(void); extern int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, struct dbll_attrs *attrs, u32 * entry); -extern int dbll_load_sect(struct dbll_library_obj *lib, +extern int dbll_load_sect(struct dbll_library_obj *zl_lib, char *sec_name, struct dbll_attrs *attrs); extern int dbll_open(struct dbll_tar_obj *target, char *file, dbll_flags flags, struct dbll_library_obj **lib_obj); extern int dbll_read_sect(struct dbll_library_obj *lib, - char *name, char *pbuf, u32 size); + char *name, char *buf, u32 size); extern void dbll_set_attrs(struct dbll_tar_obj *target, struct dbll_attrs *pattrs); extern void dbll_unload(struct dbll_library_obj *lib, struct dbll_attrs *attrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/disp.h b/drivers/staging/tidspbridge/include/dspbridge/disp.h index 9f694a4..77fc92e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/disp.h +++ b/drivers/staging/tidspbridge/include/dspbridge/disp.h @@ -115,7 +115,7 @@ extern bool disp_init(void); extern int disp_node_change_priority(struct disp_object *disp_obj, struct node_object *hnode, - u32 ul_fxn_addr, + u32 rms_fxn, nodeenv node_env, s32 prio); /* @@ -145,7 +145,7 @@ extern int disp_node_change_priority(struct disp_object */ extern int disp_node_create(struct disp_object *disp_obj, struct node_object *hnode, - u32 ul_fxn_addr, + u32 rms_fxn, u32 ul_create_fxn, IN CONST struct node_createargs *pargs, OUT nodeenv *node_env); @@ -172,7 +172,7 @@ extern int disp_node_create(struct disp_object *disp_obj, */ extern int disp_node_delete(struct disp_object *disp_obj, struct node_object *hnode, - u32 ul_fxn_addr, + u32 rms_fxn, u32 ul_delete_fxn, nodeenv node_env); /* @@ -198,7 +198,7 @@ extern int disp_node_delete(struct disp_object *disp_obj, */ extern int disp_node_run(struct disp_object *disp_obj, struct node_object *hnode, - u32 ul_fxn_addr, + u32 rms_fxn, u32 ul_execute_fxn, nodeenv node_env); #endif /* DISP_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index c180a7c..5827ea1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -213,7 +213,7 @@ extern int drv_create(struct drv_object **drv_obj); * and destroy the DRV object * Called upon driver unLoading.or unsuccesful loading of the driver. * Parameters: - * hdrv_obj: Handle to Driver object . + * driver_obj: Handle to Driver object . * Returns: * 0: Success. * -EPERM: Failed to destroy DRV Object @@ -227,7 +227,7 @@ extern int drv_create(struct drv_object **drv_obj); * DRV handle. * - Registry is updated with "0" as the DRV Object. */ -extern int drv_destroy(struct drv_object *hdrv_obj); +extern int drv_destroy(struct drv_object *driver_obj); /* * ======== drv_exit ======== @@ -341,7 +341,7 @@ extern int drv_init(void); * Purpose: * Insert a DeviceObject into the list of Driver object. * Parameters: - * hdrv_obj: Handle to DrvObject + * driver_obj: Handle to DrvObject * hdev_obj: Handle to DeviceObject to insert. * Returns: * 0: If successful. @@ -352,7 +352,7 @@ extern int drv_init(void); * Ensures: * 0: Device Object is inserted and the List is not empty. */ -extern int drv_insert_dev_object(struct drv_object *hdrv_obj, +extern int drv_insert_dev_object(struct drv_object *driver_obj, struct dev_object *hdev_obj); /* @@ -361,7 +361,7 @@ extern int drv_insert_dev_object(struct drv_object *hdrv_obj, * Search for and remove a Device object from the given list of Device Obj * objects. * Parameters: - * hdrv_obj: Handle to DrvObject + * driver_obj: Handle to DrvObject * hdev_obj: Handle to DevObject to Remove * Returns: * 0: Success. @@ -373,7 +373,7 @@ extern int drv_insert_dev_object(struct drv_object *hdrv_obj, * Ensures: * List either does not exist (NULL), or is not empty if it does exist. */ -extern int drv_remove_dev_object(struct drv_object *hdrv_obj, +extern int drv_remove_dev_object(struct drv_object *driver_obj, struct dev_object *hdev_obj); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h index a40b0ff..6a6c4bf 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h @@ -32,7 +32,7 @@ extern int bridge_msg_create(OUT struct msg_mgr **msg_man, extern int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, OUT struct msg_queue **msgq, - u32 msgq_id, u32 max_msgs, void *h); + u32 msgq_id, u32 max_msgs, void *arg); extern void bridge_msg_delete(struct msg_mgr *hmsg_mgr); diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index 7fff2b3..a79fc6e 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -114,7 +114,7 @@ void io_mbox_msg(u32 msg); * pchnl != NULL * Ensures: */ -extern void io_request_chnl(struct io_mgr *hio_mgr, +extern void io_request_chnl(struct io_mgr *io_manager, struct chnl_object *pchnl, u8 io_mode, OUT u16 *mbx_val); @@ -129,7 +129,7 @@ extern void io_request_chnl(struct io_mgr *hio_mgr, * pchnl != NULL * Ensures: */ -extern void iosm_schedule(struct io_mgr *hio_mgr); +extern void iosm_schedule(struct io_mgr *io_manager); /* * DSP-DMA IO functions diff --git a/drivers/staging/tidspbridge/include/dspbridge/mgr.h b/drivers/staging/tidspbridge/include/dspbridge/mgr.h index b90457b..1191330 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/mgr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/mgr.h @@ -66,7 +66,7 @@ int mgr_wait_for_bridge_events(struct dsp_notification * Details: * DCD Dll is loaded and MGR Object stores the handle of the DLL. */ -extern int mgr_create(OUT struct mgr_object **hmgr_obj, +extern int mgr_create(OUT struct mgr_object **mgr_obj, struct cfg_devnode *dev_node_obj); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/proc.h b/drivers/staging/tidspbridge/include/dspbridge/proc.h index e7a9510..f91f11f 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/proc.h +++ b/drivers/staging/tidspbridge/include/dspbridge/proc.h @@ -99,7 +99,7 @@ extern int proc_auto_start(struct cfg_devnode *dev_node_obj, * This function Calls bridge_dev_ctrl. */ extern int proc_ctrl(void *hprocessor, - u32 dw_cmd, IN struct dsp_cbdata *pargs); + u32 dw_cmd, IN struct dsp_cbdata *arg); /* * ======== proc_detach ======== @@ -278,7 +278,7 @@ extern int proc_get_state(void *hprocessor, OUT struct dsp_processorstate * Ensures: * Details: */ -extern int proc_get_processor_id(void *hprocessor, u32 * proc_id); +extern int proc_get_processor_id(void *proc, u32 * proc_id); /* * ======== proc_get_trace ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h index 48aebff..4e1b8a2 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h +++ b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h @@ -23,41 +23,42 @@ extern int drv_get_proc_ctxt_list(struct process_context **pctxt, extern int drv_insert_proc_context(struct drv_object *driver_obj, void *process_ctxt); -extern int drv_remove_all_dmm_res_elements(void *ctxt); +extern int drv_remove_all_dmm_res_elements(void *process_ctxt); -extern int drv_remove_all_node_res_elements(void *ctxt); +extern int drv_remove_all_node_res_elements(void *process_ctxt); extern int drv_proc_set_pid(void *ctxt, s32 process); -extern int drv_remove_all_resources(void *pctxt); +extern int drv_remove_all_resources(void *process_ctxt); extern int drv_remove_proc_context(struct drv_object *driver_obj, void *pr_ctxt); -extern int drv_get_node_res_element(void *hnode, void *node_res, - void *ctxt); +extern int drv_get_node_res_element(void *hnode, void *node_resource, + void *process_ctx); -extern int drv_insert_node_res_element(void *hnode, void *node_res, - void *ctxt); +extern int drv_insert_node_res_element(void *hnode, void *node_resource, + void *process_ctxt); extern void drv_proc_node_update_heap_status(void *node_resource, s32 status); -extern int drv_remove_node_res_element(void *node_res, void *status); +extern int drv_remove_node_res_element(void *node_resource, + void *process_ctxt); extern void drv_proc_node_update_status(void *node_resource, s32 status); -extern int drv_proc_update_strm_res(u32 num_bufs, void *strm_res); +extern int drv_proc_update_strm_res(u32 num_bufs, void *strm_resources); extern int drv_proc_insert_strm_res_element(void *stream_obj, void *strm_res, - void *pctxt); + void *process_ctxt); -extern int drv_get_strm_res_element(void *stream_obj, void *strm_res, - void *ctxt); +extern int drv_get_strm_res_element(void *stream_obj, void *strm_resources, + void *process_ctxt); extern int drv_proc_remove_strm_res_element(void *strm_res, - void *ctxt); + void *process_ctxt); -extern int drv_remove_all_strm_res_elements(void *ctxt); +extern int drv_remove_all_strm_res_elements(void *process_ctxt); extern enum node_state node_get_state(void *hnode); diff --git a/drivers/staging/tidspbridge/include/dspbridge/rmm.h b/drivers/staging/tidspbridge/include/dspbridge/rmm.h index f6b78d7..baea536 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/rmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/rmm.h @@ -74,7 +74,7 @@ struct rmm_target_obj; * Ensures: */ extern int rmm_alloc(struct rmm_target_obj *target, u32 segid, u32 size, - u32 align, u32 *dsp_adr, bool reserve); + u32 align, u32 *dsp_address, bool reserve); /* * ======== rmm_create ======== @@ -144,7 +144,7 @@ extern void rmm_exit(void); * reserve || [dsp_address, dsp_address + size] is a valid memory range. * Ensures: */ -extern bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 dsp_address, +extern bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 dsp_addr, u32 size, bool reserved); /* diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index d054e53..4861c51 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -149,7 +149,7 @@ static struct cmm_mnode *get_free_block(struct cmm_allocator *allocator, static struct cmm_mnode *get_node(struct cmm_object *cmm_mgr_obj, u32 dw_pa, u32 dw_va, u32 ul_size); /* get available slot for new allocator */ -static s32 get_slot(struct cmm_object *hcmm_mgr); +static s32 get_slot(struct cmm_object *cmm_mgr_obj); static void un_register_gppsm_seg(struct cmm_allocator *psma); /* @@ -540,7 +540,7 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, u32 dw_gpp_base_pa, u32 ul_size, u32 dsp_addr_offset, s8 c_factor, u32 dw_dsp_base, u32 ul_dsp_size, - u32 *sgmt_id, u32 dw_gpp_base_va) + u32 *sgmt_id, u32 gpp_base_va) { struct cmm_object *cmm_mgr_obj = (struct cmm_object *)hcmm_mgr; struct cmm_allocator *psma = NULL; @@ -551,13 +551,13 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, DBC_REQUIRE(ul_size > 0); DBC_REQUIRE(sgmt_id != NULL); DBC_REQUIRE(dw_gpp_base_pa != 0); - DBC_REQUIRE(dw_gpp_base_va != 0); + DBC_REQUIRE(gpp_base_va != 0); DBC_REQUIRE((c_factor <= CMM_ADDTODSPPA) && (c_factor >= CMM_SUBFROMDSPPA)); dev_dbg(bridge, "%s: dw_gpp_base_pa %x ul_size %x dsp_addr_offset %x " - "dw_dsp_base %x ul_dsp_size %x dw_gpp_base_va %x\n", __func__, + "dw_dsp_base %x ul_dsp_size %x gpp_base_va %x\n", __func__, dw_gpp_base_pa, ul_size, dsp_addr_offset, dw_dsp_base, - ul_dsp_size, dw_gpp_base_va); + ul_dsp_size, gpp_base_va); if (!hcmm_mgr) { status = -EFAULT; return status; @@ -585,7 +585,7 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, psma->hcmm_mgr = hcmm_mgr; /* ref to parent */ psma->shm_base = dw_gpp_base_pa; /* SM Base phys */ psma->ul_sm_size = ul_size; /* SM segment size in bytes */ - psma->dw_vm_base = dw_gpp_base_va; + psma->dw_vm_base = gpp_base_va; psma->dw_dsp_phys_addr_offset = dsp_addr_offset; psma->c_factor = c_factor; psma->dw_dsp_base = dw_dsp_base; diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index d9501eb..21aad31 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -215,7 +215,7 @@ void cod_close(struct cod_libraryobj *lib) * dynamically loaded object files. * */ -int cod_create(OUT struct cod_manager **mgr, char *str_dummy_file, +int cod_create(OUT struct cod_manager **mgr, char *str_zl_file, IN OPTIONAL CONST struct cod_attrs *attrs) { struct cod_manager *mgr_new; @@ -281,23 +281,24 @@ int cod_create(OUT struct cod_manager **mgr, char *str_dummy_file, * Purpose: * Delete a code manager object. */ -void cod_delete(struct cod_manager *hmgr) +void cod_delete(struct cod_manager *cod_mgr_obj) { DBC_REQUIRE(refs > 0); - DBC_REQUIRE(IS_VALID(hmgr)); + DBC_REQUIRE(IS_VALID(cod_mgr_obj)); - if (hmgr->base_lib) { - if (hmgr->loaded) - hmgr->fxns.unload_fxn(hmgr->base_lib, &hmgr->attrs); + if (cod_mgr_obj->base_lib) { + if (cod_mgr_obj->loaded) + cod_mgr_obj->fxns.unload_fxn(cod_mgr_obj->base_lib, + &cod_mgr_obj->attrs); - hmgr->fxns.close_fxn(hmgr->base_lib); + cod_mgr_obj->fxns.close_fxn(cod_mgr_obj->base_lib); } - if (hmgr->target) { - hmgr->fxns.delete_fxn(hmgr->target); - hmgr->fxns.exit_fxn(); + if (cod_mgr_obj->target) { + cod_mgr_obj->fxns.delete_fxn(cod_mgr_obj->target); + cod_mgr_obj->fxns.exit_fxn(); } - hmgr->ul_magic = ~MAGIC; - kfree(hmgr); + cod_mgr_obj->ul_magic = ~MAGIC; + kfree(cod_mgr_obj); } /* @@ -432,23 +433,24 @@ int cod_get_section(struct cod_libraryobj *lib, IN char *str_sect, * C symbol. * */ -int cod_get_sym_value(struct cod_manager *hmgr, char *str_sym, +int cod_get_sym_value(struct cod_manager *cod_mgr_obj, char *str_sym, u32 *pul_value) { struct dbll_sym_val *dbll_sym; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(IS_VALID(hmgr)); + DBC_REQUIRE(IS_VALID(cod_mgr_obj)); DBC_REQUIRE(str_sym != NULL); DBC_REQUIRE(pul_value != NULL); - dev_dbg(bridge, "%s: hmgr: %p str_sym: %s pul_value: %p\n", - __func__, hmgr, str_sym, pul_value); - if (hmgr->base_lib) { - if (!hmgr->fxns. - get_addr_fxn(hmgr->base_lib, str_sym, &dbll_sym)) { - if (!hmgr->fxns. - get_c_addr_fxn(hmgr->base_lib, str_sym, &dbll_sym)) + dev_dbg(bridge, "%s: cod_mgr_obj: %p str_sym: %s pul_value: %p\n", + __func__, cod_mgr_obj, str_sym, pul_value); + if (cod_mgr_obj->base_lib) { + if (!cod_mgr_obj->fxns. + get_addr_fxn(cod_mgr_obj->base_lib, str_sym, &dbll_sym)) { + if (!cod_mgr_obj->fxns. + get_c_addr_fxn(cod_mgr_obj->base_lib, str_sym, + &dbll_sym)) return -ESPIPE; } } else { @@ -492,7 +494,7 @@ bool cod_init(void) * recalculated to reflect this. In this way, we can support NULL * terminating args arrays, if num_argc is very large. */ -int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], +int cod_load_base(struct cod_manager *cod_mgr_obj, u32 num_argc, char *args[], cod_writefxn pfn_write, void *arb, char *envp[]) { dbll_flags flags; @@ -502,12 +504,12 @@ int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], u32 i; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(IS_VALID(hmgr)); + DBC_REQUIRE(IS_VALID(cod_mgr_obj)); DBC_REQUIRE(num_argc > 0); DBC_REQUIRE(args != NULL); DBC_REQUIRE(args[0] != NULL); DBC_REQUIRE(pfn_write != NULL); - DBC_REQUIRE(hmgr->base_lib != NULL); + DBC_REQUIRE(cod_mgr_obj->base_lib != NULL); /* * Make sure every argv[] stated in argc has a value, or change argc to @@ -521,7 +523,7 @@ int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], } /* set the write function for this operation */ - hmgr->fxns.get_attrs_fxn(hmgr->target, &save_attrs); + cod_mgr_obj->fxns.get_attrs_fxn(cod_mgr_obj->target, &save_attrs); new_attrs = save_attrs; new_attrs.write = (dbll_write_fxn) pfn_write; @@ -533,15 +535,16 @@ int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], /* Load the image */ flags = DBLL_CODE | DBLL_DATA | DBLL_SYMB; - status = hmgr->fxns.load_fxn(hmgr->base_lib, flags, &new_attrs, - &hmgr->ul_entry); + status = cod_mgr_obj->fxns.load_fxn(cod_mgr_obj->base_lib, flags, + &new_attrs, + &cod_mgr_obj->ul_entry); if (DSP_FAILED(status)) - hmgr->fxns.close_fxn(hmgr->base_lib); + cod_mgr_obj->fxns.close_fxn(cod_mgr_obj->base_lib); if (DSP_SUCCEEDED(status)) - hmgr->loaded = true; + cod_mgr_obj->loaded = true; else - hmgr->base_lib = NULL; + cod_mgr_obj->base_lib = NULL; return status; } diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index cb4d2a7..16dbde8 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -140,7 +140,8 @@ struct dbll_symbol { static void dof_close(struct dbll_library_obj *zl_lib); static int dof_open(struct dbll_library_obj *zl_lib); static s32 no_op(struct dynamic_loader_initialize *thisptr, void *bufr, - ldr_addr locn, struct ldr_section_info *info, unsigned bytsiz); + ldr_addr locn, struct ldr_section_info *info, + unsigned bytsize); /* * Functions called by dynamic loader @@ -176,20 +177,20 @@ static void rmm_dealloc(struct dynamic_loader_allocate *this, static int connect(struct dynamic_loader_initialize *this); static int read_mem(struct dynamic_loader_initialize *this, void *buf, ldr_addr addr, struct ldr_section_info *info, - unsigned nbytes); + unsigned bytes); static int write_mem(struct dynamic_loader_initialize *this, void *buf, ldr_addr addr, struct ldr_section_info *info, unsigned nbytes); static int fill_mem(struct dynamic_loader_initialize *this, ldr_addr addr, - struct ldr_section_info *info, unsigned nbytes, + struct ldr_section_info *info, unsigned bytes, unsigned val); static int execute(struct dynamic_loader_initialize *this, ldr_addr start); static void release(struct dynamic_loader_initialize *this); /* symbol table hash functions */ -static u16 name_hash(void *name, u16 max_bucket); -static bool name_match(void *name, void *sp); -static void sym_delete(void *sp); +static u16 name_hash(void *key, u16 max_bucket); +static bool name_match(void *key, void *sp); +static void sym_delete(void *value); static u32 refs; /* module reference count */ @@ -728,7 +729,7 @@ func_cont: * Get the content of a COFF section. */ int dbll_read_sect(struct dbll_library_obj *lib, char *name, - char *content, u32 size) + char *buf, u32 size) { struct dbll_library_obj *zl_lib = (struct dbll_library_obj *)lib; bool opened_doff = false; @@ -740,7 +741,7 @@ int dbll_read_sect(struct dbll_library_obj *lib, char *name, DBC_REQUIRE(refs > 0); DBC_REQUIRE(zl_lib); DBC_REQUIRE(name != NULL); - DBC_REQUIRE(content != NULL); + DBC_REQUIRE(buf != NULL); DBC_REQUIRE(size != 0); /* If DOFF file is not open, we open it. */ @@ -768,7 +769,7 @@ int dbll_read_sect(struct dbll_library_obj *lib, char *name, } /* * Ensure the supplied buffer size is sufficient to store - * the section content to be read. + * the section buf to be read. */ ul_sect_size = sect->size * byte_size; /* Make sure size is even for good swap */ @@ -780,7 +781,7 @@ int dbll_read_sect(struct dbll_library_obj *lib, char *name, if (ul_sect_size > size) { status = -EPERM; } else { - if (!dload_get_section(zl_lib->desc, sect, content)) + if (!dload_get_section(zl_lib->desc, sect, buf)) status = -EBADF; } @@ -790,8 +791,8 @@ func_cont: opened_doff = false; } - dev_dbg(bridge, "%s: lib: %p name: %s content: %p size: 0x%x, " - "status 0x%x\n", __func__, lib, name, content, size, status); + dev_dbg(bridge, "%s: lib: %p name: %s buf: %p size: 0x%x, " + "status 0x%x\n", __func__, lib, name, buf, size, status); return status; } @@ -935,13 +936,13 @@ static u16 name_hash(void *key, u16 max_bucket) /* * ======== name_match ======== */ -static bool name_match(void *key, void *value) +static bool name_match(void *key, void *sp) { DBC_REQUIRE(key != NULL); - DBC_REQUIRE(value != NULL); + DBC_REQUIRE(sp != NULL); - if ((key != NULL) && (value != NULL)) { - if (strcmp((char *)key, ((struct dbll_symbol *)value)->name) == + if ((key != NULL) && (sp != NULL)) { + if (strcmp((char *)key, ((struct dbll_symbol *)sp)->name) == 0) return true; } diff --git a/drivers/staging/tidspbridge/pmgr/dmm.c b/drivers/staging/tidspbridge/pmgr/dmm.c index c661e58..c4d6cbc 100644 --- a/drivers/staging/tidspbridge/pmgr/dmm.c +++ b/drivers/staging/tidspbridge/pmgr/dmm.c @@ -405,14 +405,14 @@ int dmm_un_reserve_memory(struct dmm_object *dmm_mgr, u32 rsv_addr) * Purpose: * Returns a region containing the specified memory region */ -static struct map_page *get_region(u32 addrs) +static struct map_page *get_region(u32 addr) { struct map_page *curr_region = NULL; u32 i = 0; if (virtual_mapping_table != NULL) { /* find page mapped by this address */ - i = DMM_ADDR_TO_INDEX(addrs); + i = DMM_ADDR_TO_INDEX(addr); if (i < table_size) curr_region = virtual_mapping_table + i; } diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 03a2317..a6bbb24 100755 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -269,11 +269,11 @@ int drv_get_node_res_element(void *hnode, void *node_resource, /* Allocate the STRM resource element * This is called after the actual resource is allocated */ -int drv_proc_insert_strm_res_element(void *stream_handle, - void *hstrm_res, void *process_ctxt) +int drv_proc_insert_strm_res_element(void *stream_obj, + void *strm_res, void *process_ctxt) { struct strm_res_object **pstrm_res = - (struct strm_res_object **)hstrm_res; + (struct strm_res_object **)strm_res; struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct strm_res_object *temp_strm_res = NULL; @@ -287,7 +287,7 @@ int drv_proc_insert_strm_res_element(void *stream_handle, kfree(*pstrm_res); return -EPERM; } - (*pstrm_res)->hstream = stream_handle; + (*pstrm_res)->hstream = stream_obj; if (ctxt->pstrm_list != NULL) { temp_strm_res = ctxt->pstrm_list; while (temp_strm_res->next != NULL) @@ -305,9 +305,9 @@ int drv_proc_insert_strm_res_element(void *stream_handle, /* Release Stream resource element context * This function called after the actual resource is freed */ -int drv_proc_remove_strm_res_element(void *hstrm_res, void *process_ctxt) +int drv_proc_remove_strm_res_element(void *strm_res, void *process_ctxt) { - struct strm_res_object *pstrm_res = (struct strm_res_object *)hstrm_res; + struct strm_res_object *pstrm_res = (struct strm_res_object *)strm_res; struct process_context *ctxt = (struct process_context *)process_ctxt; struct strm_res_object *temp_strm_res; int status = 0; @@ -375,11 +375,11 @@ int drv_remove_all_strm_res_elements(void *process_ctxt) } /* Getting the stream resource element */ -int drv_get_strm_res_element(void *stream_obj, void *hstrm_res, +int drv_get_strm_res_element(void *stream_obj, void *strm_resources, void *process_ctxt) { struct strm_res_object **strm_res = - (struct strm_res_object **)hstrm_res; + (struct strm_res_object **)strm_resources; struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct strm_res_object *temp_strm2 = NULL; @@ -405,11 +405,11 @@ int drv_get_strm_res_element(void *stream_obj, void *hstrm_res, } /* Updating the stream resource element */ -int drv_proc_update_strm_res(u32 num_bufs, void *hstrm_res) +int drv_proc_update_strm_res(u32 num_bufs, void *strm_resources) { int status = 0; struct strm_res_object **strm_res = - (struct strm_res_object **)hstrm_res; + (struct strm_res_object **)strm_resources; (*strm_res)->num_bufs = num_bufs; return status; diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.h b/drivers/staging/tidspbridge/rmgr/drv_interface.h index fd6f489..ab07060 100644 --- a/drivers/staging/tidspbridge/rmgr/drv_interface.h +++ b/drivers/staging/tidspbridge/rmgr/drv_interface.h @@ -20,8 +20,9 @@ /* Prototypes for all functions in this bridge */ static int __init bridge_init(void); /* Initialize bridge */ static void __exit bridge_exit(void); /* Opposite of initialize */ -static int bridge_open(struct inode *, struct file *); /* Open */ -static int bridge_release(struct inode *, struct file *); /* Release */ -static long bridge_ioctl(struct file *, unsigned int, unsigned long); +static int bridge_open(struct inode *ip, struct file *filp); /* Open */ +static int bridge_release(struct inode *ip, struct file *filp); /* Release */ +static long bridge_ioctl(struct file *filp, unsigned int code, + unsigned long args); static int bridge_mmap(struct file *filp, struct vm_area_struct *vma); #endif /* ifndef _DRV_INTERFACE_H_ */ diff --git a/drivers/staging/tidspbridge/rmgr/dspdrv.c b/drivers/staging/tidspbridge/rmgr/dspdrv.c index 19a7471..8a28248 100644 --- a/drivers/staging/tidspbridge/rmgr/dspdrv.c +++ b/drivers/staging/tidspbridge/rmgr/dspdrv.c @@ -116,7 +116,7 @@ func_cont: * ======== dsp_deinit ======== * Frees the resources allocated for bridge. */ -bool dsp_deinit(u32 device_ctxt) +bool dsp_deinit(u32 device_context) { bool ret = true; u32 device_node; @@ -126,10 +126,10 @@ bool dsp_deinit(u32 device_ctxt) (void)dev_remove_device((struct cfg_devnode *)device_node); (void)drv_release_resources((u32) device_node, - (struct drv_object *)device_ctxt); + (struct drv_object *)device_context); } - (void)drv_destroy((struct drv_object *)device_ctxt); + (void)drv_destroy((struct drv_object *)device_context); /* Get the Manager Object from Registry * MGR Destroy will unload the DCD dll */ diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 46fc765..e96f507 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -304,7 +304,7 @@ static int load_lib(struct nldr_nodeobject *nldr_node_obj, enum nldr_phase phase, u16 depth); static int load_ovly(struct nldr_nodeobject *nldr_node_obj, enum nldr_phase phase); -static int remote_alloc(void **ref, u16 mem_sect_type, u32 size, +static int remote_alloc(void **ref, u16 mem_sect, u32 size, u32 align, u32 *dsp_address, OPTIONAL s32 segmnt_id, OPTIONAL s32 req, bool reserve); @@ -1161,7 +1161,7 @@ static void free_sects(struct nldr_object *nldr_obj, * libraries. */ static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, - char *name, struct dbll_sym_val **sym) + char *sym_name, struct dbll_sym_val **sym) { struct nldr_object *nldr_obj = (struct nldr_object *)handle; struct nldr_nodeobject *nldr_node_obj = @@ -1171,11 +1171,12 @@ static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, bool status = false; /* check the base image */ - status = nldr_obj->ldr_fxns.get_addr_fxn(nldr_obj->base_lib, name, sym); + status = nldr_obj->ldr_fxns.get_addr_fxn(nldr_obj->base_lib, + sym_name, sym); if (!status) status = - nldr_obj->ldr_fxns.get_c_addr_fxn(nldr_obj->base_lib, name, - sym); + nldr_obj->ldr_fxns.get_c_addr_fxn(nldr_obj->base_lib, + sym_name, sym); /* * Check in root lib itself. If the library consists of @@ -1183,11 +1184,12 @@ static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, * library may need to be resolved. */ if (!status) { - status = nldr_obj->ldr_fxns.get_addr_fxn(root->lib, name, sym); + status = nldr_obj->ldr_fxns.get_addr_fxn(root->lib, sym_name, + sym); if (!status) { status = - nldr_obj->ldr_fxns.get_c_addr_fxn(root->lib, name, - sym); + nldr_obj->ldr_fxns.get_c_addr_fxn(root->lib, + sym_name, sym); } } @@ -1198,13 +1200,15 @@ static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, if (!status) { for (i = 0; i < root->dep_libs; i++) { status = - nldr_obj->ldr_fxns.get_addr_fxn(root->dep_libs_tree - [i].lib, name, sym); + nldr_obj->ldr_fxns.get_addr_fxn(root-> + dep_libs_tree + [i].lib, + sym_name, sym); if (!status) { status = nldr_obj->ldr_fxns. get_c_addr_fxn(root->dep_libs_tree[i].lib, - name, sym); + sym_name, sym); } if (status) { /* Symbol found */ @@ -1220,11 +1224,11 @@ static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, status = nldr_obj->ldr_fxns. get_addr_fxn(nldr_node_obj->pers_lib_table[i].lib, - name, sym); + sym_name, sym); if (!status) { status = nldr_obj->ldr_fxns.get_c_addr_fxn - (nldr_node_obj->pers_lib_table[i].lib, name, - sym); + (nldr_node_obj->pers_lib_table[i].lib, + sym_name, sym); } if (status) { /* Symbol found */ @@ -1623,7 +1627,7 @@ func_end: /* * ======== remote_alloc ======== */ -static int remote_alloc(void **ref, u16 space, u32 size, +static int remote_alloc(void **ref, u16 mem_sect, u32 size, u32 align, u32 *dsp_address, OPTIONAL s32 segmnt_id, OPTIONAL s32 req, bool reserve) @@ -1640,8 +1644,8 @@ static int remote_alloc(void **ref, u16 space, u32 size, bool mem_load_req = false; int status = -ENOMEM; /* Set to fail */ DBC_REQUIRE(hnode); - DBC_REQUIRE(space == DBLL_CODE || space == DBLL_DATA || - space == DBLL_BSS); + DBC_REQUIRE(mem_sect == DBLL_CODE || mem_sect == DBLL_DATA || + mem_sect == DBLL_BSS); nldr_obj = hnode->nldr_obj; rmm = nldr_obj->rmm; /* Convert size to DSP words */ @@ -1670,7 +1674,7 @@ static int remote_alloc(void **ref, u16 space, u32 size, DBC_ASSERT(false); break; } - if (space == DBLL_CODE) + if (mem_sect == DBLL_CODE) mem_phase_bit++; if (mem_phase_bit < MAXFLAGS) @@ -1681,9 +1685,9 @@ static int remote_alloc(void **ref, u16 space, u32 size, mem_load_req = true; } - mem_sect_type = (space == DBLL_CODE) ? DYNM_CODE : DYNM_DATA; + mem_sect_type = (mem_sect == DBLL_CODE) ? DYNM_CODE : DYNM_DATA; - /* Find an appropriate segment based on space */ + /* Find an appropriate segment based on mem_sect */ if (segid == NULLID) { /* No memory requirements of preferences */ DBC_ASSERT(!mem_load_req); diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index e788f31..7601108 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -1804,7 +1804,7 @@ int node_get_channel_id(struct node_object *hnode, u32 dir, u32 index, * Retrieve a message from a node on the DSP. */ int node_get_message(struct node_object *hnode, - OUT struct dsp_msg *pmsg, u32 utimeout) + OUT struct dsp_msg *message, u32 utimeout) { struct node_mgr *hnode_mgr; enum node_type node_type; @@ -1815,7 +1815,7 @@ int node_get_message(struct node_object *hnode, struct proc_object *hprocessor; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(pmsg != NULL); + DBC_REQUIRE(message != NULL); if (!hnode) { status = -EFAULT; @@ -1846,14 +1846,14 @@ int node_get_message(struct node_object *hnode, * available. */ intf_fxns = hnode_mgr->intf_fxns; status = - (*intf_fxns->pfn_msg_get) (hnode->msg_queue_obj, pmsg, utimeout); + (*intf_fxns->pfn_msg_get) (hnode->msg_queue_obj, message, utimeout); /* Check if message contains SM descriptor */ - if (DSP_FAILED(status) || !(pmsg->dw_cmd & DSP_RMSBUFDESC)) + if (DSP_FAILED(status) || !(message->dw_cmd & DSP_RMSBUFDESC)) goto func_end; /* Translate DSP byte addr to GPP Va. */ tmp_buf = cmm_xlator_translate(hnode->xlator, - (void *)(pmsg->dw_arg1 * + (void *)(message->dw_arg1 * hnode->hnode_mgr-> udsp_word_size), CMM_DSPPA2PA); if (tmp_buf != NULL) { @@ -1862,8 +1862,8 @@ int node_get_message(struct node_object *hnode, CMM_PA2VA); if (tmp_buf != NULL) { /* Adjust SM size in msg */ - pmsg->dw_arg1 = (u32) tmp_buf; - pmsg->dw_arg2 *= hnode->hnode_mgr->udsp_word_size; + message->dw_arg1 = (u32) tmp_buf; + message->dw_arg2 *= hnode->hnode_mgr->udsp_word_size; } else { status = -ESRCH; } @@ -1871,8 +1871,8 @@ int node_get_message(struct node_object *hnode, status = -ESRCH; } func_end: - dev_dbg(bridge, "%s: hnode: %p pmsg: %p utimeout: 0x%x\n", __func__, - hnode, pmsg, utimeout); + dev_dbg(bridge, "%s: hnode: %p message: %p utimeout: 0x%x\n", __func__, + hnode, message, utimeout); return status; } diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index aa48fa8..9ed42eb 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -108,7 +108,7 @@ static u32 refs; DEFINE_MUTEX(proc_lock); /* For critical sections */ /* ----------------------------------- Function Prototypes */ -static int proc_monitor(struct proc_object *hprocessor); +static int proc_monitor(struct proc_object *proc_obj); static s32 get_envp_count(char **envp); static char **prepend_envp(char **new_envp, char **envp, s32 envp_elems, s32 cnew_envp, char *sz_var); @@ -1788,32 +1788,32 @@ func_end: * Ensures: * Success: ProcObject state is PROC_IDLE */ -static int proc_monitor(struct proc_object *p_proc_object) +static int proc_monitor(struct proc_object *proc_obj) { int status = -EPERM; struct msg_mgr *hmsg_mgr; int brd_state; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(p_proc_object); + DBC_REQUIRE(proc_obj); /* This is needed only when Device is loaded when it is * already 'ACTIVE' */ /* Destory the Node Manager, msg_ctrl Manager */ - if (DSP_SUCCEEDED(dev_destroy2(p_proc_object->hdev_obj))) { + if (DSP_SUCCEEDED(dev_destroy2(proc_obj->hdev_obj))) { /* Destroy the msg_ctrl by calling msg_delete */ - dev_get_msg_mgr(p_proc_object->hdev_obj, &hmsg_mgr); + dev_get_msg_mgr(proc_obj->hdev_obj, &hmsg_mgr); if (hmsg_mgr) { msg_delete(hmsg_mgr); - dev_set_msg_mgr(p_proc_object->hdev_obj, NULL); + dev_set_msg_mgr(proc_obj->hdev_obj, NULL); } } /* Place the Board in the Monitor State */ - if (DSP_SUCCEEDED((*p_proc_object->intf_fxns->pfn_brd_monitor) - (p_proc_object->hbridge_context))) { + if (DSP_SUCCEEDED((*proc_obj->intf_fxns->pfn_brd_monitor) + (proc_obj->hbridge_context))) { status = 0; - if (DSP_SUCCEEDED((*p_proc_object->intf_fxns->pfn_brd_status) - (p_proc_object->hbridge_context, &brd_state))) + if (DSP_SUCCEEDED((*proc_obj->intf_fxns->pfn_brd_status) + (proc_obj->hbridge_context, &brd_state))) DBC_ASSERT(brd_state == BRD_IDLE); } diff --git a/drivers/staging/tidspbridge/rmgr/rmm.c b/drivers/staging/tidspbridge/rmgr/rmm.c index 0354b0f..910132f 100644 --- a/drivers/staging/tidspbridge/rmgr/rmm.c +++ b/drivers/staging/tidspbridge/rmgr/rmm.c @@ -307,7 +307,7 @@ void rmm_exit(void) /* * ======== rmm_free ======== */ -bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 addr, u32 size, +bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 dsp_addr, u32 size, bool reserved) { struct rmm_ovly_sect *sect; @@ -316,8 +316,9 @@ bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 addr, u32 size, DBC_REQUIRE(target); DBC_REQUIRE(reserved || segid < target->num_segs); - DBC_REQUIRE(reserved || (addr >= target->seg_tab[segid].base && - (addr + size) <= (target->seg_tab[segid].base + + DBC_REQUIRE(reserved || (dsp_addr >= target->seg_tab[segid].base && + (dsp_addr + size) <= (target->seg_tab[segid]. + base + target->seg_tab[segid]. length))); @@ -325,7 +326,7 @@ bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 addr, u32 size, * Free or unreserve memory. */ if (!reserved) { - ret = free_block(target, segid, addr, size); + ret = free_block(target, segid, dsp_addr, size); if (ret) target->seg_tab[segid].number--; @@ -333,7 +334,7 @@ bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 addr, u32 size, /* Unreserve memory */ sect = (struct rmm_ovly_sect *)lst_first(target->ovly_list); while (sect != NULL) { - if (addr == sect->addr) { + if (dsp_addr == sect->addr) { DBC_ASSERT(size == sect->size); /* Remove from list */ lst_remove_elem(target->ovly_list, diff --git a/drivers/staging/tidspbridge/services/cfg.c b/drivers/staging/tidspbridge/services/cfg.c index ac23b09..86c8da4 100644 --- a/drivers/staging/tidspbridge/services/cfg.c +++ b/drivers/staging/tidspbridge/services/cfg.c @@ -111,7 +111,7 @@ int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, * Purpose: * Retreive the default executable, if any, for this board. */ -int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, +int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 buf_size, OUT char *str_exec_file) { int status = 0; @@ -123,7 +123,7 @@ int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, else if (!str_exec_file || !drv_datap) status = -EFAULT; - if (strlen(drv_datap->base_img) > ul_buf_size) + if (strlen(drv_datap->base_img) > buf_size) status = -EINVAL; if (DSP_SUCCEEDED(status) && drv_datap->base_img) @@ -132,7 +132,7 @@ int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, if (DSP_FAILED(status)) pr_err("%s: Failed, status 0x%x\n", __func__, status); DBC_ENSURE(((status == 0) && - (strlen(str_exec_file) <= ul_buf_size)) + (strlen(str_exec_file) <= buf_size)) || (status != 0)); return status; } From patchwork Sat Jul 10 02:24:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111196 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Sktg002447 for ; Sat, 10 Jul 2010 02:28:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752652Ab0GJCZp (ORCPT ); Fri, 9 Jul 2010 22:25:45 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:52943 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752965Ab0GJCZX (ORCPT ); Fri, 9 Jul 2010 22:25:23 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PETf000571 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:14 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PDDa009803; Fri, 9 Jul 2010 21:25:13 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68K021595; Fri, 9 Jul 2010 21:25:13 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 08/15] staging:ti dspbridge: Rename words with camel case Date: Fri, 9 Jul 2010 21:24:02 -0500 Message-Id: <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:50 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== pMemStatBuf to mem_stat_buf pMgrAttrs to mgr_attrts pMgrInfo to mgr_info pNodeEnv to node_env pNodeId to node_uuid pNodeInfo to node_info pNumLibs to num_libs pNumPersLibs to num_pers_libs pObjDef to obj_def pObjUuid to obj_uuid poolPhysBase to pool_phys_base poolSize to pool_size pPctxt to pctxt ppDevContext to dev_cntxt ppDrvInterface to drv_intf pPersistentDepLibs to prstnt_dep_libs pPhyAddr to phy_addr ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/chnl_sm.c | 28 +++++----- drivers/staging/tidspbridge/core/io_sm.c | 8 ++-- drivers/staging/tidspbridge/core/tiomap3430.c | 10 ++-- .../staging/tidspbridge/include/dspbridge/chnl.h | 14 +++--- .../staging/tidspbridge/include/dspbridge/cmm.h | 6 +- .../staging/tidspbridge/include/dspbridge/dbdcd.h | 24 +++++----- .../staging/tidspbridge/include/dspbridge/disp.h | 6 +- .../staging/tidspbridge/include/dspbridge/dmm.h | 2 +- .../staging/tidspbridge/include/dspbridge/drv.h | 8 ++-- .../tidspbridge/include/dspbridge/dspchnl.h | 4 +- .../tidspbridge/include/dspbridge/dspdefs.h | 40 ++++++++-------- .../staging/tidspbridge/include/dspbridge/dspio.h | 2 +- drivers/staging/tidspbridge/include/dspbridge/io.h | 12 ++-- .../staging/tidspbridge/include/dspbridge/node.h | 8 ++-- .../tidspbridge/include/dspbridge/nodepriv.h | 2 +- .../include/dspbridge/resourcecleanup.h | 6 +- .../staging/tidspbridge/include/dspbridge/rmm.h | 4 +- drivers/staging/tidspbridge/pmgr/chnl.c | 14 +++--- drivers/staging/tidspbridge/pmgr/cmm.c | 10 ++-- drivers/staging/tidspbridge/pmgr/dmm.c | 2 +- drivers/staging/tidspbridge/pmgr/io.c | 10 ++-- drivers/staging/tidspbridge/rmgr/dbdcd.c | 52 ++++++++++---------- drivers/staging/tidspbridge/rmgr/disp.c | 6 +- drivers/staging/tidspbridge/rmgr/drv.c | 10 ++-- drivers/staging/tidspbridge/rmgr/node.c | 50 +++++++++--------- drivers/staging/tidspbridge/rmgr/rmm.c | 14 +++--- 26 files changed, 176 insertions(+), 176 deletions(-) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 4c61a31..97eeda9 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -382,7 +382,7 @@ func_cont: */ int bridge_chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, - IN CONST struct chnl_mgrattrs *pMgrAttrs) + IN CONST struct chnl_mgrattrs *mgr_attrts) { int status = 0; struct chnl_mgr *chnl_mgr_obj = NULL; @@ -390,10 +390,10 @@ int bridge_chnl_create(OUT struct chnl_mgr **channel_mgr, /* Check DBC requirements: */ DBC_REQUIRE(channel_mgr != NULL); - DBC_REQUIRE(pMgrAttrs != NULL); - DBC_REQUIRE(pMgrAttrs->max_channels > 0); - DBC_REQUIRE(pMgrAttrs->max_channels <= CHNL_MAXCHANNELS); - DBC_REQUIRE(pMgrAttrs->word_size != 0); + DBC_REQUIRE(mgr_attrts != NULL); + DBC_REQUIRE(mgr_attrts->max_channels > 0); + DBC_REQUIRE(mgr_attrts->max_channels <= CHNL_MAXCHANNELS); + DBC_REQUIRE(mgr_attrts->word_size != 0); /* Allocate channel manager object */ chnl_mgr_obj = kzalloc(sizeof(struct chnl_mgr), GFP_KERNEL); @@ -401,10 +401,10 @@ int bridge_chnl_create(OUT struct chnl_mgr **channel_mgr, /* * The max_channels attr must equal the # of supported chnls for * each transport(# chnls for PCPY = DDMA = ZCPY): i.e. - * pMgrAttrs->max_channels = CHNL_MAXCHANNELS = + * mgr_attrts->max_channels = CHNL_MAXCHANNELS = * DDMA_MAXDDMACHNLS = DDMA_MAXZCPYCHNLS. */ - DBC_ASSERT(pMgrAttrs->max_channels == CHNL_MAXCHANNELS); + DBC_ASSERT(mgr_attrts->max_channels == CHNL_MAXCHANNELS); max_channels = CHNL_MAXCHANNELS + CHNL_MAXCHANNELS * CHNL_PCPY; /* Create array of channels */ chnl_mgr_obj->ap_channel = kzalloc(sizeof(struct chnl_object *) @@ -412,7 +412,7 @@ int bridge_chnl_create(OUT struct chnl_mgr **channel_mgr, if (chnl_mgr_obj->ap_channel) { /* Initialize chnl_mgr object */ chnl_mgr_obj->dw_type = CHNL_TYPESM; - chnl_mgr_obj->word_size = pMgrAttrs->word_size; + chnl_mgr_obj->word_size = mgr_attrts->word_size; /* Total # chnls supported */ chnl_mgr_obj->max_channels = max_channels; chnl_mgr_obj->open_channels = 0; @@ -710,22 +710,22 @@ func_end: * Retrieve information related to the channel manager. */ int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 uChnlID, - OUT struct chnl_mgrinfo *pMgrInfo) + OUT struct chnl_mgrinfo *mgr_info) { int status = 0; struct chnl_mgr *chnl_mgr_obj = (struct chnl_mgr *)hchnl_mgr; - if (pMgrInfo != NULL) { + if (mgr_info != NULL) { if (uChnlID <= CHNL_MAXCHANNELS) { if (hchnl_mgr) { /* Return the requested information: */ - pMgrInfo->chnl_obj = + mgr_info->chnl_obj = chnl_mgr_obj->ap_channel[uChnlID]; - pMgrInfo->open_channels = + mgr_info->open_channels = chnl_mgr_obj->open_channels; - pMgrInfo->dw_type = chnl_mgr_obj->dw_type; + mgr_info->dw_type = chnl_mgr_obj->dw_type; /* total # of chnls */ - pMgrInfo->max_channels = + mgr_info->max_channels = chnl_mgr_obj->max_channels; } else { status = -EFAULT; diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 7f34510..5090ff1 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -163,7 +163,7 @@ static int register_shm_segs(struct io_mgr *hio_mgr, */ int bridge_io_create(OUT struct io_mgr **io_man, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs) + IN CONST struct io_attrs *mgr_attrts) { int status = 0; struct io_mgr *pio_mgr = NULL; @@ -174,7 +174,7 @@ int bridge_io_create(OUT struct io_mgr **io_man, u8 dev_type; /* Check requirements */ - if (!io_man || !pMgrAttrs || pMgrAttrs->word_size == 0) { + if (!io_man || !mgr_attrts || mgr_attrts->word_size == 0) { status = -EFAULT; goto func_end; } @@ -214,7 +214,7 @@ int bridge_io_create(OUT struct io_mgr **io_man, pio_mgr->pmsg = NULL; #endif pio_mgr->hchnl_mgr = hchnl_mgr; - pio_mgr->word_size = pMgrAttrs->word_size; + pio_mgr->word_size = mgr_attrts->word_size; pio_mgr->shared_mem = shared_mem; if (dev_type == DSP_UNIT) { @@ -233,7 +233,7 @@ int bridge_io_create(OUT struct io_mgr **io_man, if (DSP_SUCCEEDED(status)) { pio_mgr->hbridge_context = hbridge_context; - pio_mgr->shared_irq = pMgrAttrs->irq_shared; + pio_mgr->shared_irq = mgr_attrts->irq_shared; if (dsp_wdt_init()) status = -EPERM; } else { diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index dc20cad..e759349 100755 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -103,7 +103,7 @@ static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt, static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt, u32 ulVirtAddr, u32 ul_num_bytes); static int bridge_dev_create(OUT struct bridge_dev_context - **ppDevContext, + **dev_cntxt, struct dev_object *hdev_obj, IN struct cfg_hostres *config_param); static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, @@ -236,7 +236,7 @@ static void bad_page_dump(u32 pa, struct page *pg) * purpose: * Bridge Driver entry point. */ -void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, +void bridge_drv_entry(OUT struct bridge_drv_interface **drv_intf, IN CONST char *driver_file_name) { @@ -245,7 +245,7 @@ void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, io_sm_init(); /* Initialization of io_sm module */ if (strcmp(driver_file_name, "UMA") == 0) - *ppDrvInterface = &drv_interface_fxns; + *drv_intf = &drv_interface_fxns; else dev_dbg(bridge, "%s Unknown Bridge file name", __func__); @@ -792,7 +792,7 @@ static int bridge_brd_write(struct bridge_dev_context *dev_ctxt, * Creates a driver object. Puts DSP in self loop. */ static int bridge_dev_create(OUT struct bridge_dev_context - **ppDevContext, + **dev_cntxt, struct dev_object *hdev_obj, IN struct cfg_hostres *config_param) { @@ -930,7 +930,7 @@ static int bridge_dev_create(OUT struct bridge_dev_context dev_context->dw_brd_state = BRD_STOPPED; dev_context->resources = resources; /* Return ptr to our device state to the DSP API for storage */ - *ppDevContext = dev_context; + *dev_cntxt = dev_context; } else { if (pt_attrs != NULL) { kfree(pt_attrs->pg_info); diff --git a/drivers/staging/tidspbridge/include/dspbridge/chnl.h b/drivers/staging/tidspbridge/include/dspbridge/chnl.h index 7b0352e..4c2020c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/chnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/chnl.h @@ -53,11 +53,11 @@ extern int chnl_close(struct chnl_object *chnl_obj); * Parameters: * channel_mgr: Location to store a channel manager object on output. * hdev_obj: Handle to a device object. - * pMgrAttrs: Channel manager attributes. - * pMgrAttrs->max_channels: Max channels - * pMgrAttrs->birq: Channel's I/O IRQ number. - * pMgrAttrs->irq_shared: TRUE if the IRQ is shareable. - * pMgrAttrs->word_size: DSP Word size in equivalent PC bytes.. + * mgr_attrts: Channel manager attributes. + * mgr_attrts->max_channels: Max channels + * mgr_attrts->birq: Channel's I/O IRQ number. + * mgr_attrts->irq_shared: TRUE if the IRQ is shareable. + * mgr_attrts->word_size: DSP Word size in equivalent PC bytes.. * Returns: * 0: Success; * -EFAULT: hdev_obj is invalid. @@ -71,7 +71,7 @@ extern int chnl_close(struct chnl_object *chnl_obj); * Requires: * chnl_init(void) called. * channel_mgr != NULL. - * pMgrAttrs != NULL. + * mgr_attrts != NULL. * Ensures: * 0: Subsequent calls to chnl_create() for the same * board without an intervening call to @@ -79,7 +79,7 @@ extern int chnl_close(struct chnl_object *chnl_obj); */ extern int chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, - IN CONST struct chnl_mgrattrs *pMgrAttrs); + IN CONST struct chnl_mgrattrs *mgr_attrts); /* * ======== chnl_destroy ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index 22d053b..9d773aa 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -72,7 +72,7 @@ extern void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, * ph_cmm_mgr: Location to store a communication manager handle on * output. * hdev_obj: Handle to a device object. - * pMgrAttrs: Comm mem manager attributes. + * mgr_attrts: Comm mem manager attributes. * Returns: * 0: Success; * -ENOMEM: Insufficient memory for requested resources. @@ -81,13 +81,13 @@ extern void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, * Requires: * cmm_init(void) called. * ph_cmm_mgr != NULL. - * pMgrAttrs->ul_min_block_size >= 4 bytes. + * mgr_attrts->ul_min_block_size >= 4 bytes. * Ensures: * */ extern int cmm_create(OUT struct cmm_object **ph_cmm_mgr, struct dev_object *hdev_obj, - IN CONST struct cmm_mgrattrs *pMgrAttrs); + IN CONST struct cmm_mgrattrs *mgr_attrts); /* * ======== cmm_destroy ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h index 8c06272..8d1fc68 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h @@ -155,7 +155,7 @@ extern void dcd_exit(void); * uuid_obj: Pointer to a dsp_uuid for a library. * num_libs: Size of uuid array (number of library uuids). * dep_lib_uuids: Array of dependent library uuids to be filled in. - * pPersistentDepLibs: Array indicating if corresponding lib is persistent. + * prstnt_dep_libs: Array indicating if corresponding lib is persistent. * phase: phase to obtain correct input library * Returns: * 0: Success. @@ -173,7 +173,7 @@ extern int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, u16 num_libs, OUT struct dsp_uuid *dep_lib_uuids, - OUT bool *pPersistentDepLibs, + OUT bool *prstnt_dep_libs, IN enum nldr_phase phase); /* @@ -184,8 +184,8 @@ extern int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, * Parameters: * hdcd_mgr: A DCD manager handle. * uuid_obj: Pointer to a dsp_uuid for a library. - * pNumLibs: Size of uuid array (number of library uuids). - * pNumPersLibs: number of persistent dependent library. + * num_libs: Size of uuid array (number of library uuids). + * num_pers_libs: number of persistent dependent library. * phase: Phase to obtain correct input library * Returns: * 0: Success. @@ -196,13 +196,13 @@ extern int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, * DCD initialized. * Valid hdcd_mgr. * uuid_obj != NULL - * pNumLibs != NULL. + * num_libs != NULL. * Ensures: */ extern int dcd_get_num_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - OUT u16 *pNumLibs, - OUT u16 *pNumPersLibs, + OUT u16 *num_libs, + OUT u16 *num_pers_libs, IN enum nldr_phase phase); /* @@ -247,7 +247,7 @@ extern int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, * DSP/BIOS Bridge object. * obj_type: The type of DSP/BIOS Bridge object to be * referenced (node, processor, etc). - * pObjDef: Pointer to an object definition structure. A + * obj_def: Pointer to an object definition structure. A * union of various possible DCD object types. * Returns: * 0: Success. @@ -257,14 +257,14 @@ extern int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, * -EFAULT: Invalid DCD_HMANAGER handle. * Requires: * DCD initialized. - * pObjUuid is non-NULL. - * pObjDef is non-NULL. + * obj_uuid is non-NULL. + * obj_def is non-NULL. * Ensures: */ extern int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, - IN struct dsp_uuid *pObjUuid, + IN struct dsp_uuid *obj_uuid, IN enum dsp_dcdobjtype obj_type, - OUT struct dcd_genericobj *pObjDef); + OUT struct dcd_genericobj *obj_def); /* * ======== dcd_get_objects ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/disp.h b/drivers/staging/tidspbridge/include/dspbridge/disp.h index 03467bb..9f694a4 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/disp.h +++ b/drivers/staging/tidspbridge/include/dspbridge/disp.h @@ -128,7 +128,7 @@ extern int disp_node_change_priority(struct disp_object * ul_fxn_addr: Address or RMS create node function. * ul_create_fxn: Address of node's create function. * pargs: Arguments to pass to RMS node create function. - * pNodeEnv: Location to store node environment pointer on + * node_env: Location to store node environment pointer on * output. * Returns: * 0: Success. @@ -139,7 +139,7 @@ extern int disp_node_change_priority(struct disp_object * Valid disp_obj. * pargs != NULL. * hnode != NULL. - * pNodeEnv != NULL. + * node_env != NULL. * node_get_type(hnode) != NODE_DEVICE. * Ensures: */ @@ -148,7 +148,7 @@ extern int disp_node_create(struct disp_object *disp_obj, u32 ul_fxn_addr, u32 ul_create_fxn, IN CONST struct node_createargs - *pargs, OUT nodeenv *pNodeEnv); + *pargs, OUT nodeenv *node_env); /* * ======== disp_node_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dmm.h b/drivers/staging/tidspbridge/include/dspbridge/dmm.h index 9be892f..8c9a3d4 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dmm.h @@ -59,7 +59,7 @@ extern int dmm_delete_tables(struct dmm_object *dmm_mgr); extern int dmm_create(OUT struct dmm_object **dmm_manager, struct dev_object *hdev_obj, - IN CONST struct dmm_mgrattrs *pMgrAttrs); + IN CONST struct dmm_mgrattrs *mgr_attrts); extern bool dmm_init(void); diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index 2f9d8d8..604c15b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -430,15 +430,15 @@ void bridge_recover_schedule(void); * allocations. * physical address based on the page frame address. * Parameters: - * poolPhysBase starting address of the physical memory pool. - * poolSize size of the physical memory pool. + * pool_phys_base starting address of the physical memory pool. + * pool_size size of the physical memory pool. * Returns: * none. * Requires: * - MEM initialized. * - valid physical address for the base and size > 0 */ -extern void mem_ext_phys_pool_init(IN u32 poolPhysBase, IN u32 poolSize); +extern void mem_ext_phys_pool_init(IN u32 pool_phys_base, IN u32 pool_size); /* * ======== mem_ext_phys_pool_release ======== @@ -502,7 +502,7 @@ extern void mem_free_phys_mem(void *pVirtualAddress, * If valid linear address is returned, be sure to call * MEM_UNMAP_LINEAR_ADDRESS(). */ -#define MEM_LINEAR_ADDRESS(pPhyAddr, byte_size) pPhyAddr +#define MEM_LINEAR_ADDRESS(phy_addr, byte_size) phy_addr /* * ======== MEM_UNMAP_LINEAR_ADDRESS ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h index a4e0c84..cb7e18b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h @@ -27,7 +27,7 @@ extern int bridge_chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, IN CONST struct chnl_mgrattrs - *pMgrAttrs); + *mgr_attrts); extern int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr); @@ -58,7 +58,7 @@ extern int bridge_chnl_get_info(struct chnl_object *chnl_obj, extern int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 uChnlID, OUT struct chnl_mgrinfo - *pMgrInfo); + *mgr_info); extern int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 timeout, bool flush_data); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index e3c7232..04df01d 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -300,13 +300,13 @@ typedef int(*fxn_brd_write) (struct bridge_dev_context *dev_ctxt, * Parameters: * channel_mgr: Location to store a channel manager object on output. * hdev_obj: Handle to a device object. - * pMgrAttrs: Channel manager attributes. - * pMgrAttrs->max_channels: Max channels - * pMgrAttrs->birq: Channel's I/O IRQ number. - * pMgrAttrs->irq_shared: TRUE if the IRQ is shareable. - * pMgrAttrs->word_size: DSP Word size in equivalent PC bytes.. - * pMgrAttrs->shm_base: Base physical address of shared memory, if any. - * pMgrAttrs->usm_length: Bytes of shared memory block. + * mgr_attrts: Channel manager attributes. + * mgr_attrts->max_channels: Max channels + * mgr_attrts->birq: Channel's I/O IRQ number. + * mgr_attrts->irq_shared: TRUE if the IRQ is shareable. + * mgr_attrts->word_size: DSP Word size in equivalent PC bytes.. + * mgr_attrts->shm_base: Base physical address of shared memory, if any. + * mgr_attrts->usm_length: Bytes of shared memory block. * Returns: * 0: Success; * -ENOMEM: Insufficient memory for requested resources. @@ -314,8 +314,8 @@ typedef int(*fxn_brd_write) (struct bridge_dev_context *dev_ctxt, * -EFAULT: Couldn't map physical address to a virtual one. * Requires: * channel_mgr != NULL. - * pMgrAttrs != NULL - * pMgrAttrs field are all valid: + * mgr_attrts != NULL + * mgr_attrts field are all valid: * 0 < max_channels <= CHNL_MAXCHANNELS. * birq <= 15. * word_size > 0. @@ -328,7 +328,7 @@ typedef int(*fxn_chnl_create) (OUT struct chnl_mgr struct dev_object * hdev_obj, IN CONST struct - chnl_mgrattrs * pMgrAttrs); + chnl_mgrattrs * mgr_attrts); /* * ======== bridge_chnl_destroy ======== @@ -570,20 +570,20 @@ typedef int(*fxn_chnl_getinfo) (struct chnl_object *chnl_obj, * Parameters: * hchnl_mgr: Handle to a valid channel manager, or NULL. * uChnlID: Channel ID. - * pMgrInfo: Location to store channel manager info. + * mgr_info: Location to store channel manager info. * Returns: * 0: Success; - * -EFAULT: Invalid hchnl_mgr or pMgrInfo. + * -EFAULT: Invalid hchnl_mgr or mgr_info. * -ECHRNG: Invalid channel ID. * Requires: * Ensures: - * 0: pMgrInfo points to a filled in chnl_mgrinfo - * struct, if (pMgrInfo != NULL). + * 0: mgr_info points to a filled in chnl_mgrinfo + * struct, if (mgr_info != NULL). */ typedef int(*fxn_chnl_getmgrinfo) (struct chnl_mgr * hchnl_mgr, u32 uChnlID, - OUT struct chnl_mgrinfo *pMgrInfo); + OUT struct chnl_mgrinfo *mgr_info); /* * ======== bridge_chnl_idle ======== @@ -740,13 +740,13 @@ typedef int(*fxn_dev_destroy) (struct bridge_dev_context *dev_ctxt); * hdev_obj != NULL; * Channel manager already created; * Message manager already created; - * pMgrAttrs != NULL; + * mgr_attrts != NULL; * io_man != NULL; * Ensures: */ typedef int(*fxn_io_create) (OUT struct io_mgr **io_man, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs); + IN CONST struct io_attrs *mgr_attrts); /* * ======== bridge_io_destroy ======== @@ -1036,19 +1036,19 @@ struct bridge_drv_interface { * compatibility, and then copy the interface functions into its own * memory space. * Parameters: - * ppDrvInterface Pointer to a location to receive a pointer to the + * drv_intf Pointer to a location to receive a pointer to the * Bridge driver interface. * Returns: * Requires: * The code segment this function resides in must expect to be discarded * after completion. * Ensures: - * ppDrvInterface pointer initialized to Bridge driver's function + * drv_intf pointer initialized to Bridge driver's function * interface. No system resources are acquired by this function. * Details: * Called during the Device_Init phase. */ -void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, +void bridge_drv_entry(OUT struct bridge_drv_interface **drv_intf, IN CONST char *driver_file_name); #endif /* DSPDEFS_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspio.h b/drivers/staging/tidspbridge/include/dspbridge/dspio.h index 7b33563..93dc592 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspio.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspio.h @@ -28,7 +28,7 @@ extern int bridge_io_create(OUT struct io_mgr **io_man, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs); + IN CONST struct io_attrs *mgr_attrts); extern int bridge_io_destroy(struct io_mgr *hio_mgr); diff --git a/drivers/staging/tidspbridge/include/dspbridge/io.h b/drivers/staging/tidspbridge/include/dspbridge/io.h index aa24535..b8670ca 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io.h @@ -33,10 +33,10 @@ * channel_mgr: Location to store a channel manager object on * output. * hdev_obj: Handle to a device object. - * pMgrAttrs: IO manager attributes. - * pMgrAttrs->birq: I/O IRQ number. - * pMgrAttrs->irq_shared: TRUE if the IRQ is shareable. - * pMgrAttrs->word_size: DSP Word size in equivalent PC bytes.. + * mgr_attrts: IO manager attributes. + * mgr_attrts->birq: I/O IRQ number. + * mgr_attrts->irq_shared: TRUE if the IRQ is shareable. + * mgr_attrts->word_size: DSP Word size in equivalent PC bytes.. * Returns: * 0: Success; * -ENOMEM: Insufficient memory for requested resources. @@ -46,12 +46,12 @@ * Requires: * io_init(void) called. * io_man != NULL. - * pMgrAttrs != NULL. + * mgr_attrts != NULL. * Ensures: */ extern int io_create(OUT struct io_mgr **io_man, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs); + IN CONST struct io_attrs *mgr_attrts); /* * ======== io_destroy ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index 70f3e89..e87708d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -32,7 +32,7 @@ * Allocate GPP resources to manage a node on the DSP. * Parameters: * hprocessor: Handle of processor that is allocating the node. - * pNodeId: Pointer to a dsp_uuid for the node. + * node_uuid: Pointer to a dsp_uuid for the node. * pargs: Optional arguments to be passed to the node. * attr_in: Optional pointer to node attributes (priority, * timeout...) @@ -49,14 +49,14 @@ * Requires: * node_init(void) called. * hprocessor != NULL. - * pNodeId != NULL. + * node_uuid != NULL. * ph_node != NULL. * Ensures: * 0: IsValidNode(*ph_node). * error: *ph_node == NULL. */ extern int node_allocate(struct proc_object *hprocessor, - IN CONST struct dsp_uuid *pNodeId, + IN CONST struct dsp_uuid *node_uuid, OPTIONAL IN CONST struct dsp_cbdata *pargs, OPTIONAL IN CONST struct dsp_nodeattrin *attr_in, @@ -554,7 +554,7 @@ extern int node_terminate(struct node_object *hnode, * */ extern int node_get_uuid_props(void *hprocessor, - IN CONST struct dsp_uuid *pNodeId, + IN CONST struct dsp_uuid *node_uuid, OUT struct dsp_ndbprops *node_props); diff --git a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h index 0dc6dc7..0b45094 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h @@ -163,7 +163,7 @@ extern enum node_type node_get_type(struct node_object *hnode); * Ensures: */ extern void get_node_info(struct node_object *hnode, - struct dsp_nodeinfo *pNodeInfo); + struct dsp_nodeinfo *node_info); /* * ======== node_get_load_type ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h index 6c78f2d..48aebff 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h +++ b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h @@ -17,7 +17,7 @@ #include #include -extern int drv_get_proc_ctxt_list(struct process_context **pPctxt, +extern int drv_get_proc_ctxt_list(struct process_context **pctxt, struct drv_object *hdrv_obj); extern int drv_insert_proc_context(struct drv_object *driver_obj, @@ -29,7 +29,7 @@ extern int drv_remove_all_node_res_elements(void *ctxt); extern int drv_proc_set_pid(void *ctxt, s32 process); -extern int drv_remove_all_resources(void *pPctxt); +extern int drv_remove_all_resources(void *pctxt); extern int drv_remove_proc_context(struct drv_object *driver_obj, void *pr_ctxt); @@ -50,7 +50,7 @@ extern int drv_proc_update_strm_res(u32 num_bufs, void *strm_res); extern int drv_proc_insert_strm_res_element(void *stream_obj, void *strm_res, - void *pPctxt); + void *pctxt); extern int drv_get_strm_res_element(void *stream_obj, void *strm_res, void *ctxt); diff --git a/drivers/staging/tidspbridge/include/dspbridge/rmm.h b/drivers/staging/tidspbridge/include/dspbridge/rmm.h index 468d8d8..f6b78d7 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/rmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/rmm.h @@ -166,7 +166,7 @@ extern bool rmm_init(void); * * Parameters: * segid: Segment ID of the dynamic loading segment. - * pMemStatBuf: Pointer to allocated buffer into which memory stats are + * mem_stat_buf: Pointer to allocated buffer into which memory stats are * placed. * Returns: * TRUE: Success. @@ -176,6 +176,6 @@ extern bool rmm_init(void); * Ensures: */ extern bool rmm_stat(struct rmm_target_obj *target, enum dsp_memtype segid, - struct dsp_memstat *pMemStatBuf); + struct dsp_memstat *mem_stat_buf); #endif /* RMM_ */ diff --git a/drivers/staging/tidspbridge/pmgr/chnl.c b/drivers/staging/tidspbridge/pmgr/chnl.c index 0ba5039..7da17c8 100644 --- a/drivers/staging/tidspbridge/pmgr/chnl.c +++ b/drivers/staging/tidspbridge/pmgr/chnl.c @@ -53,7 +53,7 @@ static u32 refs; */ int chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, - IN CONST struct chnl_mgrattrs *pMgrAttrs) + IN CONST struct chnl_mgrattrs *mgr_attrts) { int status; struct chnl_mgr *hchnl_mgr; @@ -61,20 +61,20 @@ int chnl_create(OUT struct chnl_mgr **channel_mgr, DBC_REQUIRE(refs > 0); DBC_REQUIRE(channel_mgr != NULL); - DBC_REQUIRE(pMgrAttrs != NULL); + DBC_REQUIRE(mgr_attrts != NULL); *channel_mgr = NULL; /* Validate args: */ - if ((0 < pMgrAttrs->max_channels) && - (pMgrAttrs->max_channels <= CHNL_MAXCHANNELS)) + if ((0 < mgr_attrts->max_channels) && + (mgr_attrts->max_channels <= CHNL_MAXCHANNELS)) status = 0; - else if (pMgrAttrs->max_channels == 0) + else if (mgr_attrts->max_channels == 0) status = -EINVAL; else status = -ECHRNG; - if (pMgrAttrs->word_size == 0) + if (mgr_attrts->word_size == 0) status = -EINVAL; if (DSP_SUCCEEDED(status)) { @@ -89,7 +89,7 @@ int chnl_create(OUT struct chnl_mgr **channel_mgr, dev_get_intf_fxns(hdev_obj, &intf_fxns); /* Let Bridge channel module finish the create: */ status = (*intf_fxns->pfn_chnl_create) (&hchnl_mgr, hdev_obj, - pMgrAttrs); + mgr_attrts); if (DSP_SUCCEEDED(status)) { /* Fill in DSP API channel module's fields of the * chnl_mgr structure */ diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index ffe724a..8fd9c26 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -242,7 +242,7 @@ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize, */ int cmm_create(OUT struct cmm_object **ph_cmm_mgr, struct dev_object *hdev_obj, - IN CONST struct cmm_mgrattrs *pMgrAttrs) + IN CONST struct cmm_mgrattrs *mgr_attrts) { struct cmm_object *cmm_obj = NULL; int status = 0; @@ -255,13 +255,13 @@ int cmm_create(OUT struct cmm_object **ph_cmm_mgr, /* create, zero, and tag a cmm mgr object */ cmm_obj = kzalloc(sizeof(struct cmm_object), GFP_KERNEL); if (cmm_obj != NULL) { - if (pMgrAttrs == NULL) - pMgrAttrs = &cmm_dfltmgrattrs; /* set defaults */ + if (mgr_attrts == NULL) + mgr_attrts = &cmm_dfltmgrattrs; /* set defaults */ /* 4 bytes minimum */ - DBC_ASSERT(pMgrAttrs->ul_min_block_size >= 4); + DBC_ASSERT(mgr_attrts->ul_min_block_size >= 4); /* save away smallest block allocation for this cmm mgr */ - cmm_obj->ul_min_block_size = pMgrAttrs->ul_min_block_size; + cmm_obj->ul_min_block_size = mgr_attrts->ul_min_block_size; /* save away the systems memory page size */ sys_info.dw_page_size = PAGE_SIZE; sys_info.dw_allocation_granularity = PAGE_SIZE; diff --git a/drivers/staging/tidspbridge/pmgr/dmm.c b/drivers/staging/tidspbridge/pmgr/dmm.c index 96af2cc..c661e58 100644 --- a/drivers/staging/tidspbridge/pmgr/dmm.c +++ b/drivers/staging/tidspbridge/pmgr/dmm.c @@ -119,7 +119,7 @@ int dmm_create_tables(struct dmm_object *dmm_mgr, u32 addr, u32 size) */ int dmm_create(OUT struct dmm_object **dmm_manager, struct dev_object *hdev_obj, - IN CONST struct dmm_mgrattrs *pMgrAttrs) + IN CONST struct dmm_mgrattrs *mgr_attrts) { struct dmm_object *dmm_obj = NULL; int status = 0; diff --git a/drivers/staging/tidspbridge/pmgr/io.c b/drivers/staging/tidspbridge/pmgr/io.c index fdd3390..6585050 100644 --- a/drivers/staging/tidspbridge/pmgr/io.c +++ b/drivers/staging/tidspbridge/pmgr/io.c @@ -47,7 +47,7 @@ static u32 refs; * CHNL and msg_ctrl */ int io_create(OUT struct io_mgr **io_man, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs) + IN CONST struct io_attrs *mgr_attrts) { struct bridge_drv_interface *intf_fxns; struct io_mgr *hio_mgr = NULL; @@ -56,15 +56,15 @@ int io_create(OUT struct io_mgr **io_man, struct dev_object *hdev_obj, DBC_REQUIRE(refs > 0); DBC_REQUIRE(io_man != NULL); - DBC_REQUIRE(pMgrAttrs != NULL); + DBC_REQUIRE(mgr_attrts != NULL); *io_man = NULL; /* A memory base of 0 implies no memory base: */ - if ((pMgrAttrs->shm_base != 0) && (pMgrAttrs->usm_length == 0)) + if ((mgr_attrts->shm_base != 0) && (mgr_attrts->usm_length == 0)) status = -EINVAL; - if (pMgrAttrs->word_size == 0) + if (mgr_attrts->word_size == 0) status = -EINVAL; if (DSP_SUCCEEDED(status)) { @@ -72,7 +72,7 @@ int io_create(OUT struct io_mgr **io_man, struct dev_object *hdev_obj, /* Let Bridge channel module finish the create: */ status = (*intf_fxns->pfn_io_create) (&hio_mgr, hdev_obj, - pMgrAttrs); + mgr_attrts); if (DSP_SUCCEEDED(status)) { pio_mgr = (struct io_mgr_ *)hio_mgr; diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 595f9ec..2f32ece 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -69,10 +69,10 @@ static void compress_buf(char *psz_buf, u32 ul_buf_size, s32 char_size); static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size); static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - IN OUT u16 *pNumLibs, - OPTIONAL OUT u16 *pNumPersLibs, + IN OUT u16 *num_libs, + OPTIONAL OUT u16 *num_pers_libs, OPTIONAL OUT struct dsp_uuid *dep_lib_uuids, - OPTIONAL OUT bool *pPersistentDepLibs, + OPTIONAL OUT bool *prstnt_dep_libs, IN enum nldr_phase phase); /* @@ -328,7 +328,7 @@ void dcd_exit(void) int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, u16 num_libs, OUT struct dsp_uuid *dep_lib_uuids, - OUT bool *pPersistentDepLibs, + OUT bool *prstnt_dep_libs, IN enum nldr_phase phase) { int status = 0; @@ -337,11 +337,11 @@ int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, DBC_REQUIRE(hdcd_mgr); DBC_REQUIRE(uuid_obj != NULL); DBC_REQUIRE(dep_lib_uuids != NULL); - DBC_REQUIRE(pPersistentDepLibs != NULL); + DBC_REQUIRE(prstnt_dep_libs != NULL); status = get_dep_lib_info(hdcd_mgr, uuid_obj, &num_libs, NULL, dep_lib_uuids, - pPersistentDepLibs, phase); + prstnt_dep_libs, phase); return status; } @@ -351,18 +351,18 @@ int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, */ int dcd_get_num_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - OUT u16 *pNumLibs, OUT u16 *pNumPersLibs, + OUT u16 *num_libs, OUT u16 *num_pers_libs, IN enum nldr_phase phase) { int status = 0; DBC_REQUIRE(refs > 0); DBC_REQUIRE(hdcd_mgr); - DBC_REQUIRE(pNumLibs != NULL); - DBC_REQUIRE(pNumPersLibs != NULL); + DBC_REQUIRE(num_libs != NULL); + DBC_REQUIRE(num_pers_libs != NULL); DBC_REQUIRE(uuid_obj != NULL); - status = get_dep_lib_info(hdcd_mgr, uuid_obj, pNumLibs, pNumPersLibs, + status = get_dep_lib_info(hdcd_mgr, uuid_obj, num_libs, num_pers_libs, NULL, NULL, phase); return status; @@ -375,9 +375,9 @@ int dcd_get_num_dep_libs(IN struct dcd_manager *hdcd_mgr, * object type. */ int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, - IN struct dsp_uuid *pObjUuid, + IN struct dsp_uuid *obj_uuid, IN enum dsp_dcdobjtype obj_type, - OUT struct dcd_genericobj *pObjDef) + OUT struct dcd_genericobj *obj_def) { struct dcd_manager *dcd_mgr_obj = hdcd_mgr; /* ptr to DCD mgr */ struct cod_libraryobj *lib = NULL; @@ -394,8 +394,8 @@ int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, char sz_obj_type[MAX_INT2CHAR_LENGTH]; /* str. rep. of obj_type. */ DBC_REQUIRE(refs > 0); - DBC_REQUIRE(pObjDef != NULL); - DBC_REQUIRE(pObjUuid != NULL); + DBC_REQUIRE(obj_def != NULL); + DBC_REQUIRE(obj_uuid != NULL); sz_uuid = kzalloc(MAXUUIDLEN, GFP_KERNEL); if (!sz_uuid) { @@ -436,7 +436,7 @@ int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, } /* Create UUID value to set in registry. */ - uuid_uuid_to_string(pObjUuid, sz_uuid, MAXUUIDLEN); + uuid_uuid_to_string(obj_uuid, sz_uuid, MAXUUIDLEN); if ((strlen(sz_reg_key) + MAXUUIDLEN) < DCD_MAXPATHLENGTH) strncat(sz_reg_key, sz_uuid, MAXUUIDLEN); @@ -512,7 +512,7 @@ int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, /* Parse the content of the COFF buffer. */ status = - get_attrs_from_buf(psz_coff_buf, ul_len, obj_type, pObjDef); + get_attrs_from_buf(psz_coff_buf, ul_len, obj_type, obj_def); if (DSP_FAILED(status)) status = -EACCES; } else { @@ -1393,10 +1393,10 @@ static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size) */ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - IN OUT u16 *pNumLibs, - OPTIONAL OUT u16 *pNumPersLibs, + IN OUT u16 *num_libs, + OPTIONAL OUT u16 *num_pers_libs, OPTIONAL OUT struct dsp_uuid *dep_lib_uuids, - OPTIONAL OUT bool *pPersistentDepLibs, + OPTIONAL OUT bool *prstnt_dep_libs, enum nldr_phase phase) { struct dcd_manager *dcd_mgr_obj = hdcd_mgr; @@ -1416,14 +1416,14 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, DBC_REQUIRE(refs > 0); DBC_REQUIRE(hdcd_mgr); - DBC_REQUIRE(pNumLibs != NULL); + DBC_REQUIRE(num_libs != NULL); DBC_REQUIRE(uuid_obj != NULL); /* Initialize to 0 dependent libraries, if only counting number of * dependent libraries */ if (!get_uuids) { - *pNumLibs = 0; - *pNumPersLibs = 0; + *num_libs = 0; + *num_pers_libs = 0; } /* Allocate a buffer for file name */ @@ -1472,7 +1472,7 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, psz_cur = psz_coff_buf; while ((token = strsep(&psz_cur, seps)) && *token != '\0') { if (get_uuids) { - if (dep_libs >= *pNumLibs) { + if (dep_libs >= *num_libs) { /* Gone beyond the limit */ break; } else { @@ -1482,17 +1482,17 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, [dep_libs])); /* Is this library persistent? */ token = strsep(&psz_cur, seps); - pPersistentDepLibs[dep_libs] = atoi(token); + prstnt_dep_libs[dep_libs] = atoi(token); dep_libs++; } } else { /* Advanc to next token */ token = strsep(&psz_cur, seps); if (atoi(token)) - (*pNumPersLibs)++; + (*num_pers_libs)++; /* Just counting number of dependent libraries */ - (*pNumLibs)++; + (*num_libs)++; } } func_cont: diff --git a/drivers/staging/tidspbridge/rmgr/disp.c b/drivers/staging/tidspbridge/rmgr/disp.c index 9ebdf1e..d2cb558 100644 --- a/drivers/staging/tidspbridge/rmgr/disp.c +++ b/drivers/staging/tidspbridge/rmgr/disp.c @@ -252,7 +252,7 @@ int disp_node_create(struct disp_object *disp_obj, struct node_object *hnode, u32 ulRMSFxn, u32 ul_create_fxn, IN CONST struct node_createargs *pargs, - OUT nodeenv *pNodeEnv) + OUT nodeenv *node_env) { struct node_msgargs node_msg_args; struct node_taskargs task_arg_obj; @@ -282,7 +282,7 @@ int disp_node_create(struct disp_object *disp_obj, DBC_REQUIRE(disp_obj); DBC_REQUIRE(hnode != NULL); DBC_REQUIRE(node_get_type(hnode) != NODE_DEVICE); - DBC_REQUIRE(pNodeEnv != NULL); + DBC_REQUIRE(node_env != NULL); status = dev_get_dev_type(disp_obj->hdev_obj, &dev_type); @@ -461,7 +461,7 @@ int disp_node_create(struct disp_object *disp_obj, ul_bytes = total * sizeof(rms_word); DBC_ASSERT(ul_bytes < (RMS_COMMANDBUFSIZE * sizeof(rms_word))); status = send_message(disp_obj, node_get_timeout(hnode), - ul_bytes, pNodeEnv); + ul_bytes, node_env); if (DSP_SUCCEEDED(status)) { /* * Message successfully received from RMS. diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index b08341b..ef147b7 100755 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -936,21 +936,21 @@ int drv_request_bridge_res_dsp(void **phost_resources) return status; } -void mem_ext_phys_pool_init(u32 poolPhysBase, u32 poolSize) +void mem_ext_phys_pool_init(u32 pool_phys_base, u32 pool_size) { u32 pool_virt_base; /* get the virtual address for the physical memory pool passed */ - pool_virt_base = (u32) ioremap(poolPhysBase, poolSize); + pool_virt_base = (u32) ioremap(pool_phys_base, pool_size); if ((void **)pool_virt_base == NULL) { pr_err("%s: external physical memory map failed\n", __func__); ext_phys_mem_pool_enabled = false; } else { - ext_mem_pool.phys_mem_base = poolPhysBase; - ext_mem_pool.phys_mem_size = poolSize; + ext_mem_pool.phys_mem_base = pool_phys_base; + ext_mem_pool.phys_mem_size = pool_size; ext_mem_pool.virt_mem_base = pool_virt_base; - ext_mem_pool.next_phys_alloc_ptr = poolPhysBase; + ext_mem_pool.next_phys_alloc_ptr = pool_phys_base; ext_phys_mem_pool_enabled = true; } } diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 5e586d4..91a5d8c 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -252,7 +252,7 @@ static int get_fxn_address(struct node_object *hnode, u32 * pulFxnAddr, u32 uPhase); static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, - CONST struct dsp_uuid *pNodeId, + CONST struct dsp_uuid *node_uuid, struct dcd_genericobj *dcd_prop); static int get_proc_props(struct node_mgr *hnode_mgr, struct dev_object *hdev_obj); @@ -291,7 +291,7 @@ enum node_state node_get_state(void *hnode) * Allocate GPP resources to manage a node on the DSP. */ int node_allocate(struct proc_object *hprocessor, - IN CONST struct dsp_uuid *pNodeId, + IN CONST struct dsp_uuid *node_uuid, OPTIONAL IN CONST struct dsp_cbdata *pargs, OPTIONAL IN CONST struct dsp_nodeattrin *attr_in, OUT struct node_object **ph_node, @@ -328,7 +328,7 @@ int node_allocate(struct proc_object *hprocessor, DBC_REQUIRE(refs > 0); DBC_REQUIRE(hprocessor != NULL); DBC_REQUIRE(ph_node != NULL); - DBC_REQUIRE(pNodeId != NULL); + DBC_REQUIRE(node_uuid != NULL); *ph_node = NULL; @@ -393,12 +393,12 @@ int node_allocate(struct proc_object *hprocessor, mutex_lock(&hnode_mgr->node_mgr_lock); /* Get dsp_ndbprops from node database */ - status = get_node_props(hnode_mgr->hdcd_mgr, pnode, pNodeId, + status = get_node_props(hnode_mgr->hdcd_mgr, pnode, node_uuid, &(pnode->dcd_props)); if (DSP_FAILED(status)) goto func_cont; - pnode->node_uuid = *pNodeId; + pnode->node_uuid = *node_uuid; pnode->hprocessor = hprocessor; pnode->ntype = pnode->dcd_props.obj_data.node_obj.ndb_props.ntype; pnode->utimeout = pnode->dcd_props.obj_data.node_obj.ndb_props.utimeout; @@ -675,9 +675,9 @@ func_cont: DBC_ENSURE((DSP_FAILED(status) && (*ph_node == NULL)) || (DSP_SUCCEEDED(status) && *ph_node)); func_end: - dev_dbg(bridge, "%s: hprocessor: %p pNodeId: %p pargs: %p attr_in: %p " - "ph_node: %p status: 0x%x\n", __func__, hprocessor, - pNodeId, pargs, attr_in, ph_node, status); + dev_dbg(bridge, "%s: hprocessor: %p node_uuid: %p pargs: %p attr_in:" + " %p ph_node: %p status: 0x%x\n", __func__, hprocessor, + node_uuid, pargs, attr_in, ph_node, status); return status; } @@ -2860,26 +2860,26 @@ static int get_fxn_address(struct node_object *hnode, u32 * pulFxnAddr, * Purpose: * Retrieves the node information. */ -void get_node_info(struct node_object *hnode, struct dsp_nodeinfo *pNodeInfo) +void get_node_info(struct node_object *hnode, struct dsp_nodeinfo *node_info) { u32 i; DBC_REQUIRE(hnode); - DBC_REQUIRE(pNodeInfo != NULL); + DBC_REQUIRE(node_info != NULL); - pNodeInfo->cb_struct = sizeof(struct dsp_nodeinfo); - pNodeInfo->nb_node_database_props = + node_info->cb_struct = sizeof(struct dsp_nodeinfo); + node_info->nb_node_database_props = hnode->dcd_props.obj_data.node_obj.ndb_props; - pNodeInfo->execution_priority = hnode->prio; - pNodeInfo->device_owner = hnode->device_owner; - pNodeInfo->number_streams = hnode->num_inputs + hnode->num_outputs; - pNodeInfo->node_env = hnode->node_env; + node_info->execution_priority = hnode->prio; + node_info->device_owner = hnode->device_owner; + node_info->number_streams = hnode->num_inputs + hnode->num_outputs; + node_info->node_env = hnode->node_env; - pNodeInfo->ns_execution_state = node_get_state(hnode); + node_info->ns_execution_state = node_get_state(hnode); /* Copy stream connect data */ for (i = 0; i < hnode->num_inputs + hnode->num_outputs; i++) - pNodeInfo->sc_stream_connection[i] = hnode->stream_connect[i]; + node_info->sc_stream_connection[i] = hnode->stream_connect[i]; } @@ -2890,7 +2890,7 @@ void get_node_info(struct node_object *hnode, struct dsp_nodeinfo *pNodeInfo) */ static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, - CONST struct dsp_uuid *pNodeId, + CONST struct dsp_uuid *node_uuid, struct dcd_genericobj *dcd_prop) { u32 len; @@ -2902,14 +2902,14 @@ static int get_node_props(struct dcd_manager *hdcd_mgr, int status = 0; char sz_uuid[MAXUUIDLEN]; - status = dcd_get_object_def(hdcd_mgr, (struct dsp_uuid *)pNodeId, + status = dcd_get_object_def(hdcd_mgr, (struct dsp_uuid *)node_uuid, DSP_DCDNODETYPE, dcd_prop); if (DSP_SUCCEEDED(status)) { hnode->ntype = node_type = pndb_props->ntype; /* Create UUID value to set in registry. */ - uuid_uuid_to_string((struct dsp_uuid *)pNodeId, sz_uuid, + uuid_uuid_to_string((struct dsp_uuid *)node_uuid, sz_uuid, MAXUUIDLEN); dev_dbg(bridge, "(node) UUID: %s\n", sz_uuid); @@ -3006,7 +3006,7 @@ static int get_proc_props(struct node_mgr *hnode_mgr, * Fetch Node UUID properties from DCD/DOF file. */ int node_get_uuid_props(void *hprocessor, - IN CONST struct dsp_uuid *pNodeId, + IN CONST struct dsp_uuid *node_uuid, OUT struct dsp_ndbprops *node_props) { struct node_mgr *hnode_mgr = NULL; @@ -3017,9 +3017,9 @@ int node_get_uuid_props(void *hprocessor, DBC_REQUIRE(refs > 0); DBC_REQUIRE(hprocessor != NULL); - DBC_REQUIRE(pNodeId != NULL); + DBC_REQUIRE(node_uuid != NULL); - if (hprocessor == NULL || pNodeId == NULL) { + if (hprocessor == NULL || node_uuid == NULL) { status = -EFAULT; goto func_end; } @@ -3057,7 +3057,7 @@ int node_get_uuid_props(void *hprocessor, dcd_node_props.pstr_i_alg_name = NULL; status = dcd_get_object_def(hnode_mgr->hdcd_mgr, - (struct dsp_uuid *)pNodeId, DSP_DCDNODETYPE, + (struct dsp_uuid *)node_uuid, DSP_DCDNODETYPE, (struct dcd_genericobj *)&dcd_node_props); if (DSP_SUCCEEDED(status)) { diff --git a/drivers/staging/tidspbridge/rmgr/rmm.c b/drivers/staging/tidspbridge/rmgr/rmm.c index 96c61dd..0354b0f 100644 --- a/drivers/staging/tidspbridge/rmgr/rmm.c +++ b/drivers/staging/tidspbridge/rmgr/rmm.c @@ -369,7 +369,7 @@ bool rmm_init(void) * ======== rmm_stat ======== */ bool rmm_stat(struct rmm_target_obj *target, enum dsp_memtype segid, - struct dsp_memstat *pMemStatBuf) + struct dsp_memstat *mem_stat_buf) { struct rmm_header *head; bool ret = false; @@ -377,7 +377,7 @@ bool rmm_stat(struct rmm_target_obj *target, enum dsp_memtype segid, u32 total_free_size = 0; u32 free_blocks = 0; - DBC_REQUIRE(pMemStatBuf != NULL); + DBC_REQUIRE(mem_stat_buf != NULL); DBC_ASSERT(target != NULL); if ((u32) segid < target->num_segs) { @@ -392,19 +392,19 @@ bool rmm_stat(struct rmm_target_obj *target, enum dsp_memtype segid, } /* ul_size */ - pMemStatBuf->ul_size = target->seg_tab[segid].length; + mem_stat_buf->ul_size = target->seg_tab[segid].length; /* ul_num_free_blocks */ - pMemStatBuf->ul_num_free_blocks = free_blocks; + mem_stat_buf->ul_num_free_blocks = free_blocks; /* ul_total_free_size */ - pMemStatBuf->ul_total_free_size = total_free_size; + mem_stat_buf->ul_total_free_size = total_free_size; /* ul_len_max_free_block */ - pMemStatBuf->ul_len_max_free_block = max_free_size; + mem_stat_buf->ul_len_max_free_block = max_free_size; /* ul_num_alloc_blocks */ - pMemStatBuf->ul_num_alloc_blocks = + mem_stat_buf->ul_num_alloc_blocks = target->seg_tab[segid].number; ret = true; From patchwork Sat Jul 10 02:23:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111197 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Skth002447 for ; Sat, 10 Jul 2010 02:28:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754406Ab0GJCZq (ORCPT ); Fri, 9 Jul 2010 22:25:46 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:55228 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752998Ab0GJCZY (ORCPT ); Fri, 9 Jul 2010 22:25:24 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PDJW006467 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:13 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6A2PCT7026425; Fri, 9 Jul 2010 21:25:12 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68H021595; Fri, 9 Jul 2010 21:25:11 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 05/15] staging:ti dspbridge: Rename words with camel case. Date: Fri, 9 Jul 2010 21:23:59 -0500 Message-Id: <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:50 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== pdwSize to buff_size pdwState to board_state pdwValue to value pdwVersion to version pElemExisting to elem_existing pEntry to entry pExists to exists pfEnablePerf to enable_perf pGenObj to gen_obj phChnlMgr to channel_mgr phChnl to chnl phCodMgr to cod_mgr phDCDHandle to dcd_handle phDcdMgr to dcd_mgr phDehMgr to deh_manager ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/chnl_sm.c | 18 ++-- drivers/staging/tidspbridge/core/tiomap3430.c | 6 +- .../staging/tidspbridge/include/dspbridge/cfg.h | 30 +++--- .../staging/tidspbridge/include/dspbridge/chnl.h | 6 +- .../staging/tidspbridge/include/dspbridge/dbdcd.h | 12 +- .../staging/tidspbridge/include/dspbridge/dbll.h | 2 +- .../tidspbridge/include/dspbridge/dblldefs.h | 2 +- .../staging/tidspbridge/include/dspbridge/dev.h | 20 ++-- .../tidspbridge/include/dspbridge/dspchnl.h | 4 +- .../tidspbridge/include/dspbridge/dspdefs.h | 25 ++-- drivers/staging/tidspbridge/include/dspbridge/io.h | 2 +- .../staging/tidspbridge/include/dspbridge/list.h | 10 +- .../staging/tidspbridge/include/dspbridge/mgr.h | 10 +- drivers/staging/tidspbridge/pmgr/chnl.c | 8 +- drivers/staging/tidspbridge/pmgr/dbll.c | 10 +- drivers/staging/tidspbridge/pmgr/dev.c | 20 ++-- drivers/staging/tidspbridge/rmgr/dbdcd.c | 134 ++++++++++---------- drivers/staging/tidspbridge/rmgr/mgr.c | 12 +- drivers/staging/tidspbridge/rmgr/nldr.c | 8 +- drivers/staging/tidspbridge/services/cfg.c | 22 ++-- 20 files changed, 182 insertions(+), 179 deletions(-) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 834172d..cec3bb5 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -380,7 +380,7 @@ func_cont: * Create a channel manager object, responsible for opening new channels * and closing old ones for a given board. */ -int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, +int bridge_chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, IN CONST struct chnl_mgrattrs *pMgrAttrs) { @@ -389,7 +389,7 @@ int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, u8 max_channels; /* Check DBC requirements: */ - DBC_REQUIRE(phChnlMgr != NULL); + DBC_REQUIRE(channel_mgr != NULL); DBC_REQUIRE(pMgrAttrs != NULL); DBC_REQUIRE(pMgrAttrs->max_channels > 0); DBC_REQUIRE(pMgrAttrs->max_channels <= CHNL_MAXCHANNELS); @@ -430,10 +430,10 @@ int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, if (DSP_FAILED(status)) { bridge_chnl_destroy(chnl_mgr_obj); - *phChnlMgr = NULL; + *channel_mgr = NULL; } else { /* Return channel manager object to caller... */ - *phChnlMgr = chnl_mgr_obj; + *channel_mgr = chnl_mgr_obj; } return status; } @@ -774,7 +774,7 @@ int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 timeout, * ======== bridge_chnl_open ======== * Open a new half-duplex channel to the DSP board. */ -int bridge_chnl_open(OUT struct chnl_object **phChnl, +int bridge_chnl_open(OUT struct chnl_object **chnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, CONST IN struct chnl_attr *pattrs) { @@ -783,10 +783,10 @@ int bridge_chnl_open(OUT struct chnl_object **phChnl, struct chnl_object *pchnl = NULL; struct sync_object *sync_event = NULL; /* Ensure DBC requirements: */ - DBC_REQUIRE(phChnl != NULL); + DBC_REQUIRE(chnl != NULL); DBC_REQUIRE(pattrs != NULL); DBC_REQUIRE(hchnl_mgr != NULL); - *phChnl = NULL; + *chnl = NULL; /* Validate Args: */ if (pattrs->uio_reqs == 0) { status = -EINVAL; @@ -893,10 +893,10 @@ int bridge_chnl_open(OUT struct chnl_object **phChnl, spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock); /* Return result... */ pchnl->dw_state = CHNL_STATEREADY; - *phChnl = pchnl; + *chnl = pchnl; } func_end: - DBC_ENSURE((DSP_SUCCEEDED(status) && pchnl) || (*phChnl == NULL)); + DBC_ENSURE((DSP_SUCCEEDED(status) && pchnl) || (*chnl == NULL)); return status; } diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index dd7436d..dc20cad 100755 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -82,7 +82,7 @@ static int bridge_brd_read(struct bridge_dev_context *dev_context, static int bridge_brd_start(struct bridge_dev_context *dev_context, u32 dsp_addr); static int bridge_brd_status(struct bridge_dev_context *dev_context, - int *pdwState); + int *board_state); static int bridge_brd_stop(struct bridge_dev_context *dev_context); static int bridge_brd_write(struct bridge_dev_context *dev_context, IN u8 *host_buff, @@ -753,10 +753,10 @@ static int bridge_brd_delete(struct bridge_dev_context *dev_ctxt) * Returns the board status. */ static int bridge_brd_status(struct bridge_dev_context *dev_ctxt, - int *pdwState) + int *board_state) { struct bridge_dev_context *dev_context = dev_ctxt; - *pdwState = dev_context->dw_brd_state; + *board_state = dev_context->dw_brd_state; return 0; } diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfg.h b/drivers/staging/tidspbridge/include/dspbridge/cfg.h index 0eadd71..29f9024 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cfg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cfg.h @@ -58,9 +58,9 @@ extern int cfg_get_auto_start(IN struct cfg_devnode *dev_node_obj, * Purpose: * Retrieves the version of the PM Class Driver. * Parameters: - * pdwVersion: Ptr to u32 to contain version number upon return. + * version: Ptr to u32 to contain version number upon return. * Returns: - * 0: Success. pdwVersion contains Class Driver version in + * 0: Success. version contains Class Driver version in * the form: 0xAABBCCDD where AABB is Major version and * CCDD is Minor. * -EPERM: Failure. @@ -68,9 +68,9 @@ extern int cfg_get_auto_start(IN struct cfg_devnode *dev_node_obj, * CFG initialized. * Ensures: * 0: Success. - * else: *pdwVersion is NULL. + * else: *version is NULL. */ -extern int cfg_get_cd_version(OUT u32 *pdwVersion); +extern int cfg_get_cd_version(OUT u32 *version); /* * ======== cfg_get_dev_object ======== @@ -79,7 +79,7 @@ extern int cfg_get_cd_version(OUT u32 *pdwVersion); * Parameters: * dev_node_obj: Platform's dev_node handle from which to retrieve * value. - * pdwValue: Ptr to location to store the value. + * value: Ptr to location to store the value. * Returns: * 0: Success. * -EFAULT: dev_node_obj is invalid or phDevObject is invalid. @@ -87,11 +87,11 @@ extern int cfg_get_cd_version(OUT u32 *pdwVersion); * Requires: * CFG initialized. * Ensures: - * 0: *pdwValue is set to the retrieved u32. - * else: *pdwValue is set to 0L. + * 0: *value is set to the retrieved u32. + * else: *value is set to 0L. */ extern int cfg_get_dev_object(IN struct cfg_devnode *dev_node_obj, - OUT u32 *pdwValue); + OUT u32 *value); /* * ======== cfg_get_exec_file ======== @@ -120,17 +120,17 @@ extern int cfg_get_exec_file(IN struct cfg_devnode *dev_node_obj, * Purpose: * Retrieve the Driver Object handle From the Registry * Parameters: - * pdwValue: Ptr to location to store the value. + * value: Ptr to location to store the value. * dw_type Type of Object to Get * Returns: * 0: Success. * Requires: * CFG initialized. * Ensures: - * 0: *pdwValue is set to the retrieved u32(non-Zero). - * else: *pdwValue is set to 0L. + * 0: *value is set to the retrieved u32(non-Zero). + * else: *value is set to 0L. */ -extern int cfg_get_object(OUT u32 *pdwValue, u8 dw_type); +extern int cfg_get_object(OUT u32 *value, u8 dw_type); /* * ======== cfg_get_perf_value ======== @@ -138,15 +138,15 @@ extern int cfg_get_object(OUT u32 *pdwValue, u8 dw_type); * Retrieve a flag indicating whether PERF should log statistics for the * PM class driver. * Parameters: - * pfEnablePerf: Location to store flag. 0 indicates the key was + * enable_perf: Location to store flag. 0 indicates the key was * not found, or had a zero value. A nonzero value * means the key was found and had a nonzero value. * Returns: * Requires: - * pfEnablePerf != NULL; + * enable_perf != NULL; * Ensures: */ -extern void cfg_get_perf_value(OUT bool *pfEnablePerf); +extern void cfg_get_perf_value(OUT bool *enable_perf); /* * ======== cfg_get_zl_file ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/chnl.h b/drivers/staging/tidspbridge/include/dspbridge/chnl.h index 89315dc..7b0352e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/chnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/chnl.h @@ -51,7 +51,7 @@ extern int chnl_close(struct chnl_object *chnl_obj); * Create a channel manager object, responsible for opening new channels * and closing old ones for a given board. * Parameters: - * phChnlMgr: Location to store a channel manager object on output. + * channel_mgr: Location to store a channel manager object on output. * hdev_obj: Handle to a device object. * pMgrAttrs: Channel manager attributes. * pMgrAttrs->max_channels: Max channels @@ -70,14 +70,14 @@ extern int chnl_close(struct chnl_object *chnl_obj); * -EEXIST: Channel manager already exists for this device. * Requires: * chnl_init(void) called. - * phChnlMgr != NULL. + * channel_mgr != NULL. * pMgrAttrs != NULL. * Ensures: * 0: Subsequent calls to chnl_create() for the same * board without an intervening call to * chnl_destroy() will fail. */ -extern int chnl_create(OUT struct chnl_mgr **phChnlMgr, +extern int chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, IN CONST struct chnl_mgrattrs *pMgrAttrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h index 2a2b655..8c06272 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h @@ -77,7 +77,7 @@ extern int dcd_auto_unregister(IN struct dcd_manager *hdcd_mgr, * This function creates a DCD module manager. * Parameters: * pszZlDllName: Pointer to a DLL name string. - * phDcdMgr: A pointer to a DCD manager handle. + * dcd_mgr: A pointer to a DCD manager handle. * Returns: * 0: Success. * -ENOMEM: Unable to allocate memory for DCD manager handle. @@ -85,12 +85,12 @@ extern int dcd_auto_unregister(IN struct dcd_manager *hdcd_mgr, * Requires: * DCD initialized. * pszZlDllName is non-NULL. - * phDcdMgr is non-NULL. + * dcd_mgr is non-NULL. * Ensures: * A DCD manager handle is created. */ extern int dcd_create_manager(IN char *pszZlDllName, - OUT struct dcd_manager **phDcdMgr); + OUT struct dcd_manager **dcd_mgr); /* * ======== dcd_destroy_manager ======== @@ -215,7 +215,7 @@ extern int dcd_get_num_dep_libs(IN struct dcd_manager *hdcd_mgr, * uuid_obj: Pointer to a dsp_uuid that represents a unique DSP/BIOS * Bridge object. * pstrLibName: Buffer to hold library name. - * pdwSize: Contains buffer size. Set to string size on output. + * buff_size: Contains buffer size. Set to string size on output. * phase: Which phase to load * phase_split: Are phases in multiple libraries * Returns: @@ -226,13 +226,13 @@ extern int dcd_get_num_dep_libs(IN struct dcd_manager *hdcd_mgr, * Valid hdcd_mgr. * pstrLibName != NULL. * uuid_obj != NULL - * pdwSize != NULL. + * buff_size != NULL. * Ensures: */ extern int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, IN OUT char *pstrLibName, - IN OUT u32 *pdwSize, + IN OUT u32 *buff_size, IN enum nldr_phase phase, OUT bool *phase_split); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbll.h b/drivers/staging/tidspbridge/include/dspbridge/dbll.h index 0d03714..daf8105 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbll.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbll.h @@ -41,7 +41,7 @@ extern int dbll_get_sect(struct dbll_library_obj *lib, char *name, extern bool dbll_init(void); extern int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, - struct dbll_attrs *attrs, u32 * pEntry); + struct dbll_attrs *attrs, u32 * entry); extern int dbll_load_sect(struct dbll_library_obj *lib, char *sectName, struct dbll_attrs *attrs); extern int dbll_open(struct dbll_tar_obj *target, char *file, diff --git a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h index d780ee8..da8abf4 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h @@ -342,7 +342,7 @@ typedef bool(*dbll_init_fxn) (void); * Requires: * DBL initialized. * Valid lib. - * pEntry != NULL. + * entry != NULL. * Ensures: */ typedef int(*dbll_load_fxn) (struct dbll_library_obj *lib, diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index 2e18edf..3d7a08a 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -263,19 +263,19 @@ extern int dev_get_dmm_mgr(struct dev_object *hdev_obj, * Parameters: * hdev_obj: Handle to device object created with * dev_create_device(). - * *phCodMgr: Ptr to location to store handle. + * *cod_mgr: Ptr to location to store handle. * Returns: * 0: Success. * -EFAULT: Invalid hdev_obj. * Requires: - * phCodMgr != NULL. + * cod_mgr != NULL. * DEV Initialized. * Ensures: - * 0: *phCodMgr contains a handle to a COD manager object. - * else: *phCodMgr is NULL. + * 0: *cod_mgr contains a handle to a COD manager object. + * else: *cod_mgr is NULL. */ extern int dev_get_cod_mgr(struct dev_object *hdev_obj, - OUT struct cod_manager **phCodMgr); + OUT struct cod_manager **cod_mgr); /* * ======== dev_get_deh_mgr ======== @@ -283,19 +283,19 @@ extern int dev_get_cod_mgr(struct dev_object *hdev_obj, * Retrieve the DEH manager created for this device. * Parameters: * hdev_obj: Handle to device object created with dev_create_device(). - * *phDehMgr: Ptr to location to store handle. + * *deh_manager: Ptr to location to store handle. * Returns: * 0: Success. * -EFAULT: Invalid hdev_obj. * Requires: - * phDehMgr != NULL. + * deh_manager != NULL. * DEH Initialized. * Ensures: - * 0: *phDehMgr contains a handle to a DEH manager object. - * else: *phDehMgr is NULL. + * 0: *deh_manager contains a handle to a DEH manager object. + * else: *deh_manager is NULL. */ extern int dev_get_deh_mgr(struct dev_object *hdev_obj, - OUT struct deh_mgr **phDehMgr); + OUT struct deh_mgr **deh_manager); /* * ======== dev_get_dev_node ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h index 34ce4e8..c009204 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h @@ -24,14 +24,14 @@ #ifndef DSPCHNL_ #define DSPCHNL_ -extern int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, +extern int bridge_chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, IN CONST struct chnl_mgrattrs *pMgrAttrs); extern int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr); -extern int bridge_chnl_open(OUT struct chnl_object **phChnl, +extern int bridge_chnl_open(OUT struct chnl_object **chnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 19301b2..f8146cc 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -228,17 +228,18 @@ typedef int(*fxn_brd_stop) (struct bridge_dev_context *dev_ctxt); * Report the current state of the board. * Parameters: * dev_ctxt: Handle to Bridge driver defined device context. - * pdwState: Ptr to BRD status variable. + * board_state: Ptr to BRD status variable. * Returns: * 0: * Requires: - * pdwState != NULL; + * board_state != NULL; * dev_ctxt != NULL * Ensures: - * *pdwState is one of {BRD_STOPPED, BRD_IDLE, BRD_RUNNING, BRD_UNKNOWN}; + * *board_state is one of + * {BRD_STOPPED, BRD_IDLE, BRD_RUNNING, BRD_UNKNOWN}; */ typedef int(*fxn_brd_status) (struct bridge_dev_context *dev_ctxt, - int *pdwState); + int *board_state); /* * ======== bridge_brd_read ======== @@ -297,7 +298,7 @@ typedef int(*fxn_brd_write) (struct bridge_dev_context *dev_ctxt, * Create a channel manager object, responsible for opening new channels * and closing old ones for a given 'Bridge board. * Parameters: - * phChnlMgr: Location to store a channel manager object on output. + * channel_mgr: Location to store a channel manager object on output. * hdev_obj: Handle to a device object. * pMgrAttrs: Channel manager attributes. * pMgrAttrs->max_channels: Max channels @@ -312,7 +313,7 @@ typedef int(*fxn_brd_write) (struct bridge_dev_context *dev_ctxt, * -EIO: Unable to plug ISR for given IRQ. * -EFAULT: Couldn't map physical address to a virtual one. * Requires: - * phChnlMgr != NULL. + * channel_mgr != NULL. * pMgrAttrs != NULL * pMgrAttrs field are all valid: * 0 < max_channels <= CHNL_MAXCHANNELS. @@ -323,7 +324,7 @@ typedef int(*fxn_brd_write) (struct bridge_dev_context *dev_ctxt, * Ensures: */ typedef int(*fxn_chnl_create) (OUT struct chnl_mgr - **phChnlMgr, + **channel_mgr, struct dev_object * hdev_obj, IN CONST struct @@ -367,7 +368,7 @@ typedef void (*fxn_deh_notify) (struct deh_mgr *hdeh_mgr, * Purpose: * Open a new half-duplex channel to the DSP board. * Parameters: - * phChnl: Location to store a channel object handle. + * chnl: Location to store a channel object handle. * hchnl_mgr: Handle to channel manager, as returned by * CHNL_GetMgr(). * chnl_mode: One of {CHNL_MODETODSP, CHNL_MODEFROMDSP} specifies @@ -398,16 +399,16 @@ typedef void (*fxn_deh_notify) (struct deh_mgr *hdeh_mgr, * -EIO: No free IO request packets available for * queuing. * Requires: - * phChnl != NULL. + * chnl != NULL. * pattrs != NULL. * pattrs->event_obj is a valid event handle. * pattrs->hReserved is the kernel mode handle for pattrs->event_obj. * Ensures: - * 0: *phChnl is a valid channel. - * else: *phChnl is set to NULL if (phChnl != NULL); + * 0: *chnl is a valid channel. + * else: *chnl is set to NULL if (chnl != NULL); */ typedef int(*fxn_chnl_open) (OUT struct chnl_object - **phChnl, + **chnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, diff --git a/drivers/staging/tidspbridge/include/dspbridge/io.h b/drivers/staging/tidspbridge/include/dspbridge/io.h index e1610f1..123cf03 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io.h @@ -30,7 +30,7 @@ * Create an IO manager object, responsible for managing IO between * CHNL and msg_ctrl. * Parameters: - * phChnlMgr: Location to store a channel manager object on + * channel_mgr: Location to store a channel manager object on * output. * hdev_obj: Handle to a device object. * pMgrAttrs: IO manager attributes. diff --git a/drivers/staging/tidspbridge/include/dspbridge/list.h b/drivers/staging/tidspbridge/include/dspbridge/list.h index dc8ae09..2cf885d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/list.h +++ b/drivers/staging/tidspbridge/include/dspbridge/list.h @@ -123,21 +123,21 @@ static inline void lst_init_elem(struct list_head *elem_list) * Parameters: * pList: Pointer to list control structure. * elem_list: Pointer to element in list to insert. - * pElemExisting: Pointer to existing list element. + * elem_existing: Pointer to existing list element. * Returns: * Requires: * - LST initialized. * - pList != NULL. * - elem_list != NULL. - * - pElemExisting != NULL. + * - elem_existing != NULL. * Ensures: */ static inline void lst_insert_before(struct lst_list *pList, struct list_head *elem_list, - struct list_head *pElemExisting) + struct list_head *elem_existing) { - if (pList && elem_list && pElemExisting) - list_add_tail(elem_list, pElemExisting); + if (pList && elem_list && elem_existing) + list_add_tail(elem_list, elem_existing); } /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/mgr.h b/drivers/staging/tidspbridge/include/dspbridge/mgr.h index e225845..90e174c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/mgr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/mgr.h @@ -174,19 +174,19 @@ extern void mgr_exit(void); * Retrieves the MGR handle. Accessor Function * Parameters: * mgr_handle: Handle to the Manager Object - * phDCDHandle: Ptr to receive the DCD Handle. + * dcd_handle: Ptr to receive the DCD Handle. * Returns: * 0: Sucess * -EPERM: Failure to get the Handle * Requires: * MGR is initialized. - * phDCDHandle != NULL + * dcd_handle != NULL * Ensures: - * 0 and *phDCDHandle != NULL || - * -EPERM and *phDCDHandle == NULL + * 0 and *dcd_handle != NULL || + * -EPERM and *dcd_handle == NULL */ extern int mgr_get_dcd_handle(IN struct mgr_object - *mgr_handle, OUT u32 *phDCDHandle); + *mgr_handle, OUT u32 *dcd_handle); /* * ======== mgr_init ======== diff --git a/drivers/staging/tidspbridge/pmgr/chnl.c b/drivers/staging/tidspbridge/pmgr/chnl.c index bc969d8..0ba5039 100644 --- a/drivers/staging/tidspbridge/pmgr/chnl.c +++ b/drivers/staging/tidspbridge/pmgr/chnl.c @@ -51,7 +51,7 @@ static u32 refs; * Create a channel manager object, responsible for opening new channels * and closing old ones for a given 'Bridge board. */ -int chnl_create(OUT struct chnl_mgr **phChnlMgr, +int chnl_create(OUT struct chnl_mgr **channel_mgr, struct dev_object *hdev_obj, IN CONST struct chnl_mgrattrs *pMgrAttrs) { @@ -60,10 +60,10 @@ int chnl_create(OUT struct chnl_mgr **phChnlMgr, struct chnl_mgr_ *chnl_mgr_obj = NULL; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phChnlMgr != NULL); + DBC_REQUIRE(channel_mgr != NULL); DBC_REQUIRE(pMgrAttrs != NULL); - *phChnlMgr = NULL; + *channel_mgr = NULL; /* Validate args: */ if ((0 < pMgrAttrs->max_channels) && @@ -96,7 +96,7 @@ int chnl_create(OUT struct chnl_mgr **phChnlMgr, chnl_mgr_obj = (struct chnl_mgr_ *)hchnl_mgr; chnl_mgr_obj->intf_fxns = intf_fxns; /* Finally, return the new channel manager handle: */ - *phChnlMgr = hchnl_mgr; + *channel_mgr = hchnl_mgr; } } diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index 29918cc..530191a 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -451,7 +451,7 @@ bool dbll_init(void) * ======== dbll_load ======== */ int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, - struct dbll_attrs *attrs, u32 *pEntry) + struct dbll_attrs *attrs, u32 *entry) { struct dbll_library_obj *zl_lib = (struct dbll_library_obj *)lib; struct dbll_tar_obj *dbzl; @@ -461,7 +461,7 @@ int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, bool opened_doff = false; DBC_REQUIRE(refs > 0); DBC_REQUIRE(zl_lib); - DBC_REQUIRE(pEntry != NULL); + DBC_REQUIRE(entry != NULL); DBC_REQUIRE(attrs != NULL); /* @@ -550,7 +550,7 @@ int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, redefined_symbol = false; status = -EILSEQ; } else { - *pEntry = zl_lib->entry; + *entry = zl_lib->entry; } } } @@ -563,8 +563,8 @@ int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, DBC_ENSURE(DSP_FAILED(status) || zl_lib->load_ref > 0); - dev_dbg(bridge, "%s: lib: %p flags: 0x%x pEntry: %p, status 0x%x\n", - __func__, lib, flags, pEntry, status); + dev_dbg(bridge, "%s: lib: %p flags: 0x%x entry: %p, status 0x%x\n", + __func__, lib, flags, entry, status); return status; } diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index 2e4726e..1cb891f 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -500,23 +500,23 @@ int dev_get_dmm_mgr(struct dev_object *hdev_obj, * Retrieve the COD manager create for this device. */ int dev_get_cod_mgr(struct dev_object *hdev_obj, - OUT struct cod_manager **phCodMgr) + OUT struct cod_manager **cod_mgr) { int status = 0; struct dev_object *dev_obj = hdev_obj; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phCodMgr != NULL); + DBC_REQUIRE(cod_mgr != NULL); if (hdev_obj) { - *phCodMgr = dev_obj->cod_mgr; + *cod_mgr = dev_obj->cod_mgr; } else { - *phCodMgr = NULL; + *cod_mgr = NULL; status = -EFAULT; } - DBC_ENSURE(DSP_SUCCEEDED(status) || ((phCodMgr != NULL) && - (*phCodMgr == NULL))); + DBC_ENSURE(DSP_SUCCEEDED(status) || ((cod_mgr != NULL) && + (*cod_mgr == NULL))); return status; } @@ -524,17 +524,17 @@ int dev_get_cod_mgr(struct dev_object *hdev_obj, * ========= dev_get_deh_mgr ======== */ int dev_get_deh_mgr(struct dev_object *hdev_obj, - OUT struct deh_mgr **phDehMgr) + OUT struct deh_mgr **deh_manager) { int status = 0; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phDehMgr != NULL); + DBC_REQUIRE(deh_manager != NULL); DBC_REQUIRE(hdev_obj); if (hdev_obj) { - *phDehMgr = hdev_obj->hdeh_mgr; + *deh_manager = hdev_obj->hdeh_mgr; } else { - *phDehMgr = NULL; + *deh_manager = NULL; status = -EFAULT; } return status; diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index be98c4c..595f9ec 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -64,7 +64,7 @@ static u32 enum_refs; static s32 atoi(char *psz_buf); static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, enum dsp_dcdobjtype obj_type, - struct dcd_genericobj *pGenObj); + struct dcd_genericobj *gen_obj); static void compress_buf(char *psz_buf, u32 ul_buf_size, s32 char_size); static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size); static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, @@ -125,14 +125,14 @@ int dcd_auto_unregister(IN struct dcd_manager *hdcd_mgr, * Creates DCD manager. */ int dcd_create_manager(IN char *pszZlDllName, - OUT struct dcd_manager **phDcdMgr) + OUT struct dcd_manager **dcd_mgr) { struct cod_manager *cod_mgr; /* COD manager handle */ struct dcd_manager *dcd_mgr_obj = NULL; /* DCD Manager pointer */ int status = 0; DBC_REQUIRE(refs >= 0); - DBC_REQUIRE(phDcdMgr); + DBC_REQUIRE(dcd_mgr); status = cod_create(&cod_mgr, pszZlDllName, NULL); if (DSP_FAILED(status)) @@ -145,7 +145,7 @@ int dcd_create_manager(IN char *pszZlDllName, dcd_mgr_obj->cod_mgr = cod_mgr; /* Return handle to this DCD interface. */ - *phDcdMgr = dcd_mgr_obj; + *dcd_mgr = dcd_mgr_obj; } else { status = -ENOMEM; @@ -644,7 +644,8 @@ func_end: */ int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - IN OUT char *pstrLibName, IN OUT u32 * pdwSize, + IN OUT char *pstrLibName, + IN OUT u32 *buff_size, enum nldr_phase phase, OUT bool *phase_split) { char sz_reg_key[DCD_MAXPATHLENGTH]; @@ -656,11 +657,12 @@ int dcd_get_library_name(IN struct dcd_manager *hdcd_mgr, DBC_REQUIRE(uuid_obj != NULL); DBC_REQUIRE(pstrLibName != NULL); - DBC_REQUIRE(pdwSize != NULL); + DBC_REQUIRE(buff_size != NULL); DBC_REQUIRE(hdcd_mgr); - dev_dbg(bridge, "%s: hdcd_mgr %p, uuid_obj %p, pstrLibName %p, pdwSize " - "%p\n", __func__, hdcd_mgr, uuid_obj, pstrLibName, pdwSize); + dev_dbg(bridge, "%s: hdcd_mgr %p, uuid_obj %p, pstrLibName %p," + " buff_size %p\n", __func__, hdcd_mgr, uuid_obj, pstrLibName, + buff_size); /* * Pre-determine final key length. It's length of DCD_REGKEY + @@ -1033,7 +1035,7 @@ static s32 atoi(char *psz_buf) */ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, enum dsp_dcdobjtype obj_type, - struct dcd_genericobj *pGenObj) + struct dcd_genericobj *gen_obj) { int status = 0; char seps[] = ", "; @@ -1049,7 +1051,7 @@ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, DBC_REQUIRE(ul_buf_size != 0); DBC_REQUIRE((obj_type == DSP_DCDNODETYPE) || (obj_type == DSP_DCDPROCESSORTYPE)); - DBC_REQUIRE(pGenObj != NULL); + DBC_REQUIRE(gen_obj != NULL); switch (obj_type) { case DSP_DCDNODETYPE: @@ -1061,13 +1063,13 @@ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, token = strsep(&psz_cur, seps); /* u32 cb_struct */ - pGenObj->obj_data.node_obj.ndb_props.cb_struct = + gen_obj->obj_data.node_obj.ndb_props.cb_struct = (u32) atoi(token); token = strsep(&psz_cur, seps); /* dsp_uuid ui_node_id */ uuid_uuid_from_string(token, - &pGenObj->obj_data.node_obj.ndb_props. + &gen_obj->obj_data.node_obj.ndb_props. ui_node_id); token = strsep(&psz_cur, seps); @@ -1077,154 +1079,154 @@ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, if (token_len > DSP_MAXNAMELEN - 1) token_len = DSP_MAXNAMELEN - 1; - strncpy(pGenObj->obj_data.node_obj.ndb_props.ac_name, + strncpy(gen_obj->obj_data.node_obj.ndb_props.ac_name, token, token_len); - pGenObj->obj_data.node_obj.ndb_props.ac_name[token_len] = '\0'; + gen_obj->obj_data.node_obj.ndb_props.ac_name[token_len] = '\0'; token = strsep(&psz_cur, seps); /* u32 ntype */ - pGenObj->obj_data.node_obj.ndb_props.ntype = atoi(token); + gen_obj->obj_data.node_obj.ndb_props.ntype = atoi(token); token = strsep(&psz_cur, seps); /* u32 cache_on_gpp */ - pGenObj->obj_data.node_obj.ndb_props.cache_on_gpp = atoi(token); + gen_obj->obj_data.node_obj.ndb_props.cache_on_gpp = atoi(token); token = strsep(&psz_cur, seps); /* dsp_resourcereqmts dsp_resource_reqmts */ - pGenObj->obj_data.node_obj.ndb_props.dsp_resource_reqmts. + gen_obj->obj_data.node_obj.ndb_props.dsp_resource_reqmts. cb_struct = (u32) atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.static_data_size = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.global_data_size = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.program_mem_size = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.uwc_execution_time = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.uwc_period = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.uwc_deadline = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.avg_exection_time = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.node_obj.ndb_props. + gen_obj->obj_data.node_obj.ndb_props. dsp_resource_reqmts.minimum_period = atoi(token); token = strsep(&psz_cur, seps); /* s32 prio */ - pGenObj->obj_data.node_obj.ndb_props.prio = atoi(token); + gen_obj->obj_data.node_obj.ndb_props.prio = atoi(token); token = strsep(&psz_cur, seps); /* u32 stack_size */ - pGenObj->obj_data.node_obj.ndb_props.stack_size = atoi(token); + gen_obj->obj_data.node_obj.ndb_props.stack_size = atoi(token); token = strsep(&psz_cur, seps); /* u32 sys_stack_size */ - pGenObj->obj_data.node_obj.ndb_props.sys_stack_size = + gen_obj->obj_data.node_obj.ndb_props.sys_stack_size = atoi(token); token = strsep(&psz_cur, seps); /* u32 stack_seg */ - pGenObj->obj_data.node_obj.ndb_props.stack_seg = atoi(token); + gen_obj->obj_data.node_obj.ndb_props.stack_seg = atoi(token); token = strsep(&psz_cur, seps); /* u32 message_depth */ - pGenObj->obj_data.node_obj.ndb_props.message_depth = + gen_obj->obj_data.node_obj.ndb_props.message_depth = atoi(token); token = strsep(&psz_cur, seps); /* u32 num_input_streams */ - pGenObj->obj_data.node_obj.ndb_props.num_input_streams = + gen_obj->obj_data.node_obj.ndb_props.num_input_streams = atoi(token); token = strsep(&psz_cur, seps); /* u32 num_output_streams */ - pGenObj->obj_data.node_obj.ndb_props.num_output_streams = + gen_obj->obj_data.node_obj.ndb_props.num_output_streams = atoi(token); token = strsep(&psz_cur, seps); /* u32 utimeout */ - pGenObj->obj_data.node_obj.ndb_props.utimeout = atoi(token); + gen_obj->obj_data.node_obj.ndb_props.utimeout = atoi(token); token = strsep(&psz_cur, seps); /* char *pstr_create_phase_fxn */ DBC_REQUIRE(token); token_len = strlen(token); - pGenObj->obj_data.node_obj.pstr_create_phase_fxn = + gen_obj->obj_data.node_obj.pstr_create_phase_fxn = kzalloc(token_len + 1, GFP_KERNEL); - strncpy(pGenObj->obj_data.node_obj.pstr_create_phase_fxn, + strncpy(gen_obj->obj_data.node_obj.pstr_create_phase_fxn, token, token_len); - pGenObj->obj_data.node_obj.pstr_create_phase_fxn[token_len] = + gen_obj->obj_data.node_obj.pstr_create_phase_fxn[token_len] = '\0'; token = strsep(&psz_cur, seps); /* char *pstr_execute_phase_fxn */ DBC_REQUIRE(token); token_len = strlen(token); - pGenObj->obj_data.node_obj.pstr_execute_phase_fxn = + gen_obj->obj_data.node_obj.pstr_execute_phase_fxn = kzalloc(token_len + 1, GFP_KERNEL); - strncpy(pGenObj->obj_data.node_obj.pstr_execute_phase_fxn, + strncpy(gen_obj->obj_data.node_obj.pstr_execute_phase_fxn, token, token_len); - pGenObj->obj_data.node_obj.pstr_execute_phase_fxn[token_len] = + gen_obj->obj_data.node_obj.pstr_execute_phase_fxn[token_len] = '\0'; token = strsep(&psz_cur, seps); /* char *pstr_delete_phase_fxn */ DBC_REQUIRE(token); token_len = strlen(token); - pGenObj->obj_data.node_obj.pstr_delete_phase_fxn = + gen_obj->obj_data.node_obj.pstr_delete_phase_fxn = kzalloc(token_len + 1, GFP_KERNEL); - strncpy(pGenObj->obj_data.node_obj.pstr_delete_phase_fxn, + strncpy(gen_obj->obj_data.node_obj.pstr_delete_phase_fxn, token, token_len); - pGenObj->obj_data.node_obj.pstr_delete_phase_fxn[token_len] = + gen_obj->obj_data.node_obj.pstr_delete_phase_fxn[token_len] = '\0'; token = strsep(&psz_cur, seps); /* Segment id for message buffers */ - pGenObj->obj_data.node_obj.msg_segid = atoi(token); + gen_obj->obj_data.node_obj.msg_segid = atoi(token); token = strsep(&psz_cur, seps); /* Message notification type */ - pGenObj->obj_data.node_obj.msg_notify_type = atoi(token); + gen_obj->obj_data.node_obj.msg_notify_type = atoi(token); token = strsep(&psz_cur, seps); /* char *pstr_i_alg_name */ if (token) { token_len = strlen(token); - pGenObj->obj_data.node_obj.pstr_i_alg_name = + gen_obj->obj_data.node_obj.pstr_i_alg_name = kzalloc(token_len + 1, GFP_KERNEL); - strncpy(pGenObj->obj_data.node_obj.pstr_i_alg_name, + strncpy(gen_obj->obj_data.node_obj.pstr_i_alg_name, token, token_len); - pGenObj->obj_data.node_obj.pstr_i_alg_name[token_len] = + gen_obj->obj_data.node_obj.pstr_i_alg_name[token_len] = '\0'; token = strsep(&psz_cur, seps); } /* Load type (static, dynamic, or overlay) */ if (token) { - pGenObj->obj_data.node_obj.us_load_type = atoi(token); + gen_obj->obj_data.node_obj.us_load_type = atoi(token); token = strsep(&psz_cur, seps); } /* Dynamic load data requirements */ if (token) { - pGenObj->obj_data.node_obj.ul_data_mem_seg_mask = + gen_obj->obj_data.node_obj.ul_data_mem_seg_mask = atoi(token); token = strsep(&psz_cur, seps); } /* Dynamic load code requirements */ if (token) { - pGenObj->obj_data.node_obj.ul_code_mem_seg_mask = + gen_obj->obj_data.node_obj.ul_code_mem_seg_mask = atoi(token); token = strsep(&psz_cur, seps); } @@ -1232,16 +1234,16 @@ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, /* Extract node profiles into node properties */ if (token) { - pGenObj->obj_data.node_obj.ndb_props.count_profiles = + gen_obj->obj_data.node_obj.ndb_props.count_profiles = atoi(token); for (i = 0; i < - pGenObj->obj_data.node_obj. + gen_obj->obj_data.node_obj. ndb_props.count_profiles; i++) { token = strsep(&psz_cur, seps); if (token) { /* Heap Size for the node */ - pGenObj->obj_data.node_obj. + gen_obj->obj_data.node_obj. ndb_props.node_profiles[i]. ul_heap_size = atoi(token); } @@ -1249,7 +1251,7 @@ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, } token = strsep(&psz_cur, seps); if (token) { - pGenObj->obj_data.node_obj.ndb_props.stack_seg_name = + gen_obj->obj_data.node_obj.ndb_props.stack_seg_name = (u32) (token); } @@ -1263,45 +1265,45 @@ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, psz_cur = psz_buf; token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.cb_struct = atoi(token); + gen_obj->obj_data.proc_info.cb_struct = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.processor_family = atoi(token); + gen_obj->obj_data.proc_info.processor_family = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.processor_type = atoi(token); + gen_obj->obj_data.proc_info.processor_type = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.clock_rate = atoi(token); + gen_obj->obj_data.proc_info.clock_rate = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.ul_internal_mem_size = atoi(token); + gen_obj->obj_data.proc_info.ul_internal_mem_size = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.ul_external_mem_size = atoi(token); + gen_obj->obj_data.proc_info.ul_external_mem_size = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.processor_id = atoi(token); + gen_obj->obj_data.proc_info.processor_id = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.ty_running_rtos = atoi(token); + gen_obj->obj_data.proc_info.ty_running_rtos = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.node_min_priority = atoi(token); + gen_obj->obj_data.proc_info.node_min_priority = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.proc_info.node_max_priority = atoi(token); + gen_obj->obj_data.proc_info.node_max_priority = atoi(token); #ifdef _DB_TIOMAP /* Proc object may contain additional(extended) attributes. */ /* attr must match proc.hxx */ for (entry_id = 0; entry_id < 7; entry_id++) { token = strsep(&psz_cur, seps); - pGenObj->obj_data.ext_proc_obj.ty_tlb[entry_id]. + gen_obj->obj_data.ext_proc_obj.ty_tlb[entry_id]. ul_gpp_phys = atoi(token); token = strsep(&psz_cur, seps); - pGenObj->obj_data.ext_proc_obj.ty_tlb[entry_id]. + gen_obj->obj_data.ext_proc_obj.ty_tlb[entry_id]. ul_dsp_virt = atoi(token); } #endif diff --git a/drivers/staging/tidspbridge/rmgr/mgr.c b/drivers/staging/tidspbridge/rmgr/mgr.c index 52d7865..43be669 100644 --- a/drivers/staging/tidspbridge/rmgr/mgr.c +++ b/drivers/staging/tidspbridge/rmgr/mgr.c @@ -304,21 +304,21 @@ void mgr_exit(void) * Retrieves the MGR handle. Accessor Function. */ int mgr_get_dcd_handle(struct mgr_object *mgr_handle, - OUT u32 *phDCDHandle) + OUT u32 *dcd_handle) { int status = -EPERM; struct mgr_object *pmgr_obj = (struct mgr_object *)mgr_handle; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phDCDHandle != NULL); + DBC_REQUIRE(dcd_handle != NULL); - *phDCDHandle = (u32) NULL; + *dcd_handle = (u32) NULL; if (pmgr_obj) { - *phDCDHandle = (u32) pmgr_obj->hdcd_mgr; + *dcd_handle = (u32) pmgr_obj->hdcd_mgr; status = 0; } - DBC_ENSURE((DSP_SUCCEEDED(status) && *phDCDHandle != (u32) NULL) || - (DSP_FAILED(status) && *phDCDHandle == (u32) NULL)); + DBC_ENSURE((DSP_SUCCEEDED(status) && *dcd_handle != (u32) NULL) || + (DSP_FAILED(status) && *dcd_handle == (u32) NULL)); return status; } diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 91b32cb..51b9d03 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -290,7 +290,7 @@ static int add_ovly_node(struct dsp_uuid *uuid_obj, static int add_ovly_sect(struct nldr_object *nldr_obj, struct ovly_sect **pList, struct dbll_sect_info *pSectInfo, - bool *pExists, u32 addr, u32 bytes); + bool *exists, u32 addr, u32 bytes); static s32 fake_ovly_write(void *handle, u32 dsp_address, void *buf, u32 bytes, s32 mtype); static void free_sects(struct nldr_object *nldr_obj, @@ -1073,7 +1073,7 @@ func_end: static int add_ovly_sect(struct nldr_object *nldr_obj, struct ovly_sect **pList, struct dbll_sect_info *pSectInfo, - bool *pExists, u32 addr, u32 bytes) + bool *exists, u32 addr, u32 bytes) { struct ovly_sect *new_sect = NULL; struct ovly_sect *last_sect; @@ -1081,7 +1081,7 @@ static int add_ovly_sect(struct nldr_object *nldr_obj, int status = 0; ovly_section = last_sect = *pList; - *pExists = false; + *exists = false; while (ovly_section) { /* * Make sure section has not already been added. Multiple @@ -1089,7 +1089,7 @@ static int add_ovly_sect(struct nldr_object *nldr_obj, */ if (ovly_section->sect_load_addr == addr) { /* Already added */ - *pExists = true; + *exists = true; break; } last_sect = ovly_section; diff --git a/drivers/staging/tidspbridge/services/cfg.c b/drivers/staging/tidspbridge/services/cfg.c index cc138f7..53ede23 100644 --- a/drivers/staging/tidspbridge/services/cfg.c +++ b/drivers/staging/tidspbridge/services/cfg.c @@ -76,7 +76,7 @@ int cfg_get_auto_start(struct cfg_devnode *dev_node_obj, * Retrieve the Device Object handle for a given devnode. */ int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, - OUT u32 *pdwValue) + OUT u32 *value) { int status = 0; u32 dw_buf_size; @@ -88,10 +88,10 @@ int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, if (!dev_node_obj) status = -EFAULT; - if (!pdwValue) + if (!value) status = -EFAULT; - dw_buf_size = sizeof(pdwValue); + dw_buf_size = sizeof(value); if (DSP_SUCCEEDED(status)) { /* check the device string and then store dev object */ @@ -99,7 +99,7 @@ int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, (strcmp ((char *)((struct drv_ext *)dev_node_obj)->sz_string, "TIOMAP1510"))) - *pdwValue = (u32)drv_datap->dev_object; + *value = (u32)drv_datap->dev_object; } if (DSP_FAILED(status)) pr_err("%s: Failed, status 0x%x\n", __func__, status); @@ -142,12 +142,12 @@ int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, * Purpose: * Retrieve the Object handle from the Registry */ -int cfg_get_object(OUT u32 *pdwValue, u8 dw_type) +int cfg_get_object(OUT u32 *value, u8 dw_type) { int status = -EINVAL; struct drv_data *drv_datap = dev_get_drvdata(bridge); - DBC_REQUIRE(pdwValue != NULL); + DBC_REQUIRE(value != NULL); if (!drv_datap) return -EPERM; @@ -155,7 +155,7 @@ int cfg_get_object(OUT u32 *pdwValue, u8 dw_type) switch (dw_type) { case (REG_DRV_OBJECT): if (drv_datap->drv_object) { - *pdwValue = (u32)drv_datap->drv_object; + *value = (u32)drv_datap->drv_object; status = 0; } else { status = -ENODATA; @@ -163,7 +163,7 @@ int cfg_get_object(OUT u32 *pdwValue, u8 dw_type) break; case (REG_MGR_OBJECT): if (drv_datap->mgr_object) { - *pdwValue = (u32)drv_datap->mgr_object; + *value = (u32)drv_datap->mgr_object; status = 0; } else { status = -ENODATA; @@ -174,11 +174,11 @@ int cfg_get_object(OUT u32 *pdwValue, u8 dw_type) break; } if (DSP_FAILED(status)) { - *pdwValue = 0; + *value = 0; pr_err("%s: Failed, status 0x%x\n", __func__, status); } - DBC_ENSURE((DSP_SUCCEEDED(status) && *pdwValue != 0) || - (DSP_FAILED(status) && *pdwValue == 0)); + DBC_ENSURE((DSP_SUCCEEDED(status) && *value != 0) || + (DSP_FAILED(status) && *value == 0)); return status; } From patchwork Sat Jul 10 02:23:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111190 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Skta002447 for ; Sat, 10 Jul 2010 02:28:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753956Ab0GJCZi (ORCPT ); Fri, 9 Jul 2010 22:25:38 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:45292 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752416Ab0GJCZW (ORCPT ); Fri, 9 Jul 2010 22:25:22 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PACK007079 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:10 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6A2P9FK026413; Fri, 9 Jul 2010 21:25:09 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68E021595; Fri, 9 Jul 2010 21:25:09 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 02/15] staging:ti dspbridge: Rename words with camel case. Date: Fri, 9 Jul 2010 21:23:56 -0500 Message-Id: <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:48 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== hDevContext to dev_ctxt hDevExtension to dev_extension hdevObject to device_obj hDispObject to disp_obj hDrVObject to driver_obj hDRVObject to driver_obj hMGRHandle to mgr_handle hNldrObject to nldr hNode1 to node1 hNode2 to node2 hNodeRes to node_resource hPCtxt to process_ctxt hProc to proc hStreamHandle to stream_handle ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/io_sm.c | 8 +- drivers/staging/tidspbridge/core/tiomap3430.c | 94 +++++++------- drivers/staging/tidspbridge/core/tiomap_io.c | 12 +- .../staging/tidspbridge/include/dspbridge/dev.h | 4 +- .../staging/tidspbridge/include/dspbridge/disp.h | 32 +++--- .../staging/tidspbridge/include/dspbridge/drv.h | 6 +- .../tidspbridge/include/dspbridge/dspdefs.h | 72 +++++----- .../staging/tidspbridge/include/dspbridge/io_sm.h | 12 +- .../staging/tidspbridge/include/dspbridge/mgr.h | 4 +- .../staging/tidspbridge/include/dspbridge/nldr.h | 2 +- .../staging/tidspbridge/include/dspbridge/node.h | 26 ++-- .../staging/tidspbridge/include/dspbridge/proc.h | 12 +- .../include/dspbridge/resourcecleanup.h | 10 +- drivers/staging/tidspbridge/pmgr/dev.c | 4 +- drivers/staging/tidspbridge/rmgr/drv.c | 87 ++++++------ drivers/staging/tidspbridge/rmgr/drv_interface.c | 4 +- drivers/staging/tidspbridge/rmgr/mgr.c | 4 +- drivers/staging/tidspbridge/rmgr/nldr.c | 6 +- drivers/staging/tidspbridge/rmgr/node.c | 140 ++++++++++---------- drivers/staging/tidspbridge/rmgr/proc.c | 12 +- 20 files changed, 276 insertions(+), 275 deletions(-) mode change 100644 => 100755 drivers/staging/tidspbridge/include/dspbridge/dspdefs.h diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 06fec86..346f0aa 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -147,9 +147,9 @@ static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr); static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr); static u32 find_ready_output(struct chnl_mgr *chnl_mgr_obj, struct chnl_object *pchnl, u32 mask); -static u32 read_data(struct bridge_dev_context *hDevContext, void *dest, +static u32 read_data(struct bridge_dev_context *dev_ctxt, void *dest, void *pSrc, u32 usize); -static u32 write_data(struct bridge_dev_context *hDevContext, void *dest, +static u32 write_data(struct bridge_dev_context *dev_ctxt, void *dest, void *pSrc, u32 usize); /* Bus Addr (cached kernel) */ @@ -1701,7 +1701,7 @@ func_end: * ======== read_data ======== * Copies buffers from the shared memory to the host buffer. */ -static u32 read_data(struct bridge_dev_context *hDevContext, void *dest, +static u32 read_data(struct bridge_dev_context *dev_ctxt, void *dest, void *pSrc, u32 usize) { memcpy(dest, pSrc, usize); @@ -1712,7 +1712,7 @@ static u32 read_data(struct bridge_dev_context *hDevContext, void *dest, * ======== write_data ======== * Copies buffers from the host side buffer to the shared memory. */ -static u32 write_data(struct bridge_dev_context *hDevContext, void *dest, +static u32 write_data(struct bridge_dev_context *dev_ctxt, void *dest, void *pSrc, u32 usize) { memcpy(dest, pSrc, usize); diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index c6afd1e..7ed0382 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -88,19 +88,19 @@ static int bridge_brd_write(struct bridge_dev_context *dev_context, IN u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); -static int bridge_brd_set_state(struct bridge_dev_context *hDevContext, +static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt, u32 ulBrdState); -static int bridge_brd_mem_copy(struct bridge_dev_context *hDevContext, +static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt, u32 ulDspDestAddr, u32 ulDspSrcAddr, u32 ul_num_bytes, u32 ulMemType); static int bridge_brd_mem_write(struct bridge_dev_context *dev_context, IN u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); -static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext, +static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt, u32 ul_mpu_addr, u32 ulVirtAddr, u32 ul_num_bytes, u32 ul_map_attr, struct page **mapped_pages); -static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, +static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt, u32 ulVirtAddr, u32 ul_num_bytes); static int bridge_dev_create(OUT struct bridge_dev_context **ppDevContext, @@ -110,12 +110,12 @@ static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, u32 dw_cmd, IN OUT void *pargs); static int bridge_dev_destroy(struct bridge_dev_context *dev_context); static u32 user_va2_pa(struct mm_struct *mm, u32 address); -static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, +static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa, u32 va, u32 size, struct hw_mmu_map_attrs_t *map_attrs); static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va, u32 size, struct hw_mmu_map_attrs_t *attrs); -static int mem_map_vmalloc(struct bridge_dev_context *hDevContext, +static int mem_map_vmalloc(struct bridge_dev_context *dev_ctxt, u32 ul_mpu_addr, u32 ulVirtAddr, u32 ul_num_bytes, struct hw_mmu_map_attrs_t *hw_attrs); @@ -260,10 +260,10 @@ void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, * Preconditions: * Device in 'OFF' state. */ -static int bridge_brd_monitor(struct bridge_dev_context *hDevContext) +static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; u32 temp; struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; @@ -303,14 +303,14 @@ static int bridge_brd_monitor(struct bridge_dev_context *hDevContext) * purpose: * Reads buffers for DSP memory. */ -static int bridge_brd_read(struct bridge_dev_context *hDevContext, +static int bridge_brd_read(struct bridge_dev_context *dev_ctxt, OUT u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; u32 offset; - u32 dsp_base_addr = hDevContext->dw_dsp_base_addr; + u32 dsp_base_addr = dev_ctxt->dw_dsp_base_addr; if (dsp_addr < dev_context->dw_dsp_start_add) { status = -EPERM; @@ -335,11 +335,11 @@ static int bridge_brd_read(struct bridge_dev_context *hDevContext, * purpose: * This routine updates the Board status. */ -static int bridge_brd_set_state(struct bridge_dev_context *hDevContext, +static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt, u32 ulBrdState) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; dev_context->dw_brd_state = ulBrdState; return status; @@ -355,11 +355,11 @@ static int bridge_brd_set_state(struct bridge_dev_context *hDevContext, * b) DSP_RST1 is asserted. * b) DSP_RST2 is released. */ -static int bridge_brd_start(struct bridge_dev_context *hDevContext, +static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, u32 dsp_addr) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; u32 dw_sync_addr = 0; u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */ u32 ul_shm_base_virt; /* Dsp Virt SM base addr */ @@ -628,10 +628,10 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, * Preconditions : * a) None */ -static int bridge_brd_stop(struct bridge_dev_context *hDevContext) +static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; struct pg_table_attrs *pt_attrs; u32 dsp_pwr_state; int clk_status; @@ -701,10 +701,10 @@ static int bridge_brd_stop(struct bridge_dev_context *hDevContext) * Preconditions : * a) None */ -static int bridge_brd_delete(struct bridge_dev_context *hDevContext) +static int bridge_brd_delete(struct bridge_dev_context *dev_ctxt) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; struct pg_table_attrs *pt_attrs; int clk_status; struct dspbridge_platform_data *pdata = @@ -752,10 +752,10 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) * ======== bridge_brd_status ======== * Returns the board status. */ -static int bridge_brd_status(struct bridge_dev_context *hDevContext, +static int bridge_brd_status(struct bridge_dev_context *dev_ctxt, int *pdwState) { - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; *pdwState = dev_context->dw_brd_state; return 0; } @@ -764,12 +764,12 @@ static int bridge_brd_status(struct bridge_dev_context *hDevContext, * ======== bridge_brd_write ======== * Copies the buffers to DSP internal or external memory. */ -static int bridge_brd_write(struct bridge_dev_context *hDevContext, +static int bridge_brd_write(struct bridge_dev_context *dev_ctxt, IN u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; if (dsp_addr < dev_context->dw_dsp_start_add) { status = -EPERM; @@ -777,7 +777,7 @@ static int bridge_brd_write(struct bridge_dev_context *hDevContext, } if ((dsp_addr - dev_context->dw_dsp_start_add) < dev_context->dw_internal_size) { - status = write_dsp_data(hDevContext, pbHostBuf, dsp_addr, + status = write_dsp_data(dev_ctxt, pbHostBuf, dsp_addr, ul_num_bytes, ulMemType); } else { status = write_ext_dsp_data(dev_context, pbHostBuf, dsp_addr, @@ -1014,18 +1014,18 @@ static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, * ======== bridge_dev_destroy ======== * Destroys the driver object. */ -static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) +static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt) { struct pg_table_attrs *pt_attrs; int status = 0; struct bridge_dev_context *dev_context = (struct bridge_dev_context *) - hDevContext; + dev_ctxt; struct cfg_hostres *host_res; u32 shm_size; struct drv_data *drv_datap = dev_get_drvdata(bridge); /* It should never happen */ - if (!hDevContext) + if (!dev_ctxt) return -EFAULT; /* first put the device to stop state */ @@ -1102,11 +1102,11 @@ static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) kfree(drv_datap->base_img); kfree(drv_datap); dev_set_drvdata(bridge, NULL); - kfree((void *)hDevContext); + kfree((void *)dev_ctxt); return status; } -static int bridge_brd_mem_copy(struct bridge_dev_context *hDevContext, +static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt, u32 ulDspDestAddr, u32 ulDspSrcAddr, u32 ul_num_bytes, u32 ulMemType) { @@ -1116,24 +1116,24 @@ static int bridge_brd_mem_copy(struct bridge_dev_context *hDevContext, u32 copy_bytes = 0; u32 total_bytes = ul_num_bytes; u8 host_buf[BUFFERSIZE]; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; while ((total_bytes > 0) && DSP_SUCCEEDED(status)) { copy_bytes = total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes; /* Read from External memory */ - status = read_ext_dsp_data(hDevContext, host_buf, src_addr, + status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr, copy_bytes, ulMemType); if (DSP_SUCCEEDED(status)) { if (dest_addr < (dev_context->dw_dsp_start_add + dev_context->dw_internal_size)) { /* Write to Internal memory */ - status = write_dsp_data(hDevContext, host_buf, + status = write_dsp_data(dev_ctxt, host_buf, dest_addr, copy_bytes, ulMemType); } else { /* Write to External memory */ status = - write_ext_dsp_data(hDevContext, host_buf, + write_ext_dsp_data(dev_ctxt, host_buf, dest_addr, copy_bytes, ulMemType, false); } @@ -1146,12 +1146,12 @@ static int bridge_brd_mem_copy(struct bridge_dev_context *hDevContext, } /* Mem Write does not halt the DSP to write unlike bridge_brd_write */ -static int bridge_brd_mem_write(struct bridge_dev_context *hDevContext, +static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt, IN u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; u32 ul_remain_bytes = 0; u32 ul_bytes = 0; ul_remain_bytes = ul_num_bytes; @@ -1161,10 +1161,10 @@ static int bridge_brd_mem_write(struct bridge_dev_context *hDevContext, if (dsp_addr < (dev_context->dw_dsp_start_add + dev_context->dw_internal_size)) { status = - write_dsp_data(hDevContext, pbHostBuf, dsp_addr, + write_dsp_data(dev_ctxt, pbHostBuf, dsp_addr, ul_bytes, ulMemType); } else { - status = write_ext_dsp_data(hDevContext, pbHostBuf, + status = write_ext_dsp_data(dev_ctxt, pbHostBuf, dsp_addr, ul_bytes, ulMemType, true); } @@ -1184,14 +1184,14 @@ static int bridge_brd_mem_write(struct bridge_dev_context *hDevContext, * * TODO: Disable MMU while updating the page tables (but that'll stall DSP) */ -static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext, +static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt, u32 ul_mpu_addr, u32 ulVirtAddr, u32 ul_num_bytes, u32 ul_map_attr, struct page **mapped_pages) { u32 attrs; int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; struct hw_mmu_map_attrs_t hw_attrs; struct vm_area_struct *vma; struct mm_struct *mm = current->mm; @@ -1206,7 +1206,7 @@ static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext, dev_dbg(bridge, "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n", - __func__, hDevContext, ul_mpu_addr, ulVirtAddr, ul_num_bytes, + __func__, dev_ctxt, ul_mpu_addr, ulVirtAddr, ul_num_bytes, ul_map_attr); if (ul_num_bytes == 0) return -EINVAL; @@ -1253,7 +1253,7 @@ static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext, hw_attrs.donotlockmpupage = 0; if (attrs & DSP_MAPVMALLOCADDR) { - return mem_map_vmalloc(hDevContext, ul_mpu_addr, ulVirtAddr, + return mem_map_vmalloc(dev_ctxt, ul_mpu_addr, ulVirtAddr, ul_num_bytes, &hw_attrs); } /* @@ -1407,7 +1407,7 @@ func_cont: * So, instead of looking up the PTE address for every 4K block, * we clear consecutive PTEs until we unmap all the bytes */ -static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, +static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt, u32 ulVirtAddr, u32 ul_num_bytes) { u32 l1_base_va; @@ -1424,7 +1424,7 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, u32 va_curr; struct page *pg = NULL; int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; struct pg_table_attrs *pt = dev_context->pt_attrs; u32 temp; u32 paddr; @@ -1435,8 +1435,8 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, rem_bytes_l2 = 0; l1_base_va = pt->l1_base_va; pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr); - dev_dbg(bridge, "%s hDevContext %p, va %x, NumBytes %x l1_base_va %x, " - "pte_addr_l1 %x\n", __func__, hDevContext, ulVirtAddr, + dev_dbg(bridge, "%s dev_ctxt %p, va %x, NumBytes %x l1_base_va %x, " + "pte_addr_l1 %x\n", __func__, dev_ctxt, ulVirtAddr, ul_num_bytes, l1_base_va, pte_addr_l1); while (rem_bytes && (DSP_SUCCEEDED(status))) { @@ -1632,7 +1632,7 @@ static u32 user_va2_pa(struct mm_struct *mm, u32 address) * This function calculates the optimum page-aligned addresses and sizes * Caller must pass page-aligned values */ -static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, +static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa, u32 va, u32 size, struct hw_mmu_map_attrs_t *map_attrs) { @@ -1641,7 +1641,7 @@ static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, u32 pa_curr = pa; u32 va_curr = va; u32 num_bytes = size; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; int status = 0; u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB, HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c index ad1be89..945f871 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.c +++ b/drivers/staging/tidspbridge/core/tiomap_io.c @@ -50,12 +50,12 @@ bool symbols_reloaded = true; * ======== read_ext_dsp_data ======== * Copies DSP external memory buffers to the host side buffers. */ -int read_ext_dsp_data(struct bridge_dev_context *hDevContext, +int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt, OUT u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; - struct bridge_dev_context *dev_context = hDevContext; + struct bridge_dev_context *dev_context = dev_ctxt; u32 offset; u32 ul_tlb_base_virt = 0; u32 ul_shm_offset_virt = 0; @@ -178,13 +178,13 @@ int read_ext_dsp_data(struct bridge_dev_context *hDevContext, * purpose: * Copies buffers to the DSP internal/external memory. */ -int write_dsp_data(struct bridge_dev_context *hDevContext, +int write_dsp_data(struct bridge_dev_context *dev_ctxt, IN u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { u32 offset; - u32 dw_base_addr = hDevContext->dw_dsp_base_addr; - struct cfg_hostres *resources = hDevContext->resources; + u32 dw_base_addr = dev_ctxt->dw_dsp_base_addr; + struct cfg_hostres *resources = dev_ctxt->resources; int status = 0; u32 base1, base2, base3; base1 = OMAP_DSP_MEM1_SIZE; @@ -194,7 +194,7 @@ int write_dsp_data(struct bridge_dev_context *hDevContext, if (!resources) return -EPERM; - offset = dsp_addr - hDevContext->dw_dsp_start_add; + offset = dsp_addr - dev_ctxt->dw_dsp_start_add; if (offset < base1) { dw_base_addr = MEM_LINEAR_ADDRESS(resources->dw_mem_base[2], resources->dw_mem_length[2]); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index 87c1681..2ee1c41 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -41,7 +41,7 @@ * device's bridge_brd_write() function. * Parameters: * pArb: Handle to a Device Object. - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * dsp_addr: Address on DSP board (Destination). * pHostBuf: Pointer to host buffer (Source). * ul_num_bytes: Number of bytes to transfer. @@ -336,7 +336,7 @@ extern int dev_get_dev_node(struct dev_object *hdev_obj, * 0: *phDevNode contains a platform specific device ID; * else: *phDevNode is NULL. */ -extern int dev_get_dev_type(struct dev_object *hdevObject, +extern int dev_get_dev_type(struct dev_object *device_obj, u8 *dev_type); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/disp.h b/drivers/staging/tidspbridge/include/dspbridge/disp.h index 2fd14b0..2c63db9 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/disp.h +++ b/drivers/staging/tidspbridge/include/dspbridge/disp.h @@ -57,15 +57,15 @@ extern int disp_create(OUT struct disp_object **phDispObject, * Delete the NODE Dispatcher. * * Parameters: - * hDispObject: Node Dispatcher object. + * disp_obj: Node Dispatcher object. * Returns: * Requires: * disp_init(void) called. - * Valid hDispObject. + * Valid disp_obj. * Ensures: - * hDispObject is invalid. + * disp_obj is invalid. */ -extern void disp_delete(struct disp_object *hDispObject); +extern void disp_delete(struct disp_object *disp_obj); /* * ======== disp_exit ======== @@ -97,7 +97,7 @@ extern bool disp_init(void); * Change the priority of a node currently running on the target. * * Parameters: - * hDispObject: Node Dispatcher object. + * disp_obj: Node Dispatcher object. * hnode: Node object representing a node currently * allocated or running on the DSP. * ulFxnAddress: Address of RMS function for changing priority. @@ -108,12 +108,12 @@ extern bool disp_init(void); * -ETIME: A timeout occurred before the DSP responded. * Requires: * disp_init(void) called. - * Valid hDispObject. + * Valid disp_obj. * hnode != NULL. * Ensures: */ extern int disp_node_change_priority(struct disp_object - *hDispObject, + *disp_obj, struct node_object *hnode, u32 ul_fxn_addr, nodeenv node_env, s32 prio); @@ -123,7 +123,7 @@ extern int disp_node_change_priority(struct disp_object * Create a node on the DSP by remotely calling the node's create function. * * Parameters: - * hDispObject: Node Dispatcher object. + * disp_obj: Node Dispatcher object. * hnode: Node handle obtained from node_allocate(). * ul_fxn_addr: Address or RMS create node function. * ul_create_fxn: Address of node's create function. @@ -136,14 +136,14 @@ extern int disp_node_change_priority(struct disp_object * -EPERM: A failure occurred, unable to create node. * Requires: * disp_init(void) called. - * Valid hDispObject. + * Valid disp_obj. * pargs != NULL. * hnode != NULL. * pNodeEnv != NULL. * node_get_type(hnode) != NODE_DEVICE. * Ensures: */ -extern int disp_node_create(struct disp_object *hDispObject, +extern int disp_node_create(struct disp_object *disp_obj, struct node_object *hnode, u32 ul_fxn_addr, u32 ul_create_fxn, @@ -155,7 +155,7 @@ extern int disp_node_create(struct disp_object *hDispObject, * Delete a node on the DSP by remotely calling the node's delete function. * * Parameters: - * hDispObject: Node Dispatcher object. + * disp_obj: Node Dispatcher object. * hnode: Node object representing a node currently * loaded on the DSP. * ul_fxn_addr: Address or RMS delete node function. @@ -166,11 +166,11 @@ extern int disp_node_create(struct disp_object *hDispObject, * -ETIME: A timeout occurred before the DSP responded. * Requires: * disp_init(void) called. - * Valid hDispObject. + * Valid disp_obj. * hnode != NULL. * Ensures: */ -extern int disp_node_delete(struct disp_object *hDispObject, +extern int disp_node_delete(struct disp_object *disp_obj, struct node_object *hnode, u32 ul_fxn_addr, u32 ul_delete_fxn, nodeenv node_env); @@ -181,7 +181,7 @@ extern int disp_node_delete(struct disp_object *hDispObject, * that has been suspended (via DISP_NodePause()) on the DSP. * * Parameters: - * hDispObject: Node Dispatcher object. + * disp_obj: Node Dispatcher object. * hnode: Node object representing a node to be executed * on the DSP. * ul_fxn_addr: Address or RMS node execute function. @@ -192,11 +192,11 @@ extern int disp_node_delete(struct disp_object *hDispObject, * -ETIME: A timeout occurred before the DSP responded. * Requires: * disp_init(void) called. - * Valid hDispObject. + * Valid disp_obj. * hnode != NULL. * Ensures: */ -extern int disp_node_run(struct disp_object *hDispObject, +extern int disp_node_run(struct disp_object *disp_obj, struct node_object *hnode, u32 ul_fxn_addr, u32 ul_execute_fxn, nodeenv node_env); diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index 020bed0..f9b9634 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -313,16 +313,16 @@ extern u32 drv_get_next_dev_object(u32 hdev_obj); * Purpose: * Returns the Ptr to the Next Device Extension from the the List * Parameters: - * hDevExtension: Handle to the Device Extension + * dev_extension: Handle to the Device Extension * Requires: * DRV Initialized - * hDevExtension != 0. + * dev_extension != 0. * Returns: * dw_dev_extension: Ptr to the Next Dev Extension * 0: If it fail to Get the next Dev Extension * Ensures: */ -extern u32 drv_get_next_dev_extension(u32 hDevExtension); +extern u32 drv_get_next_dev_extension(u32 dev_extension); /* * ======== drv_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 23ef1d5..73034c3 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -55,52 +55,52 @@ struct bridge_dev_context; * Purpose: * Bring the board to the BRD_IDLE (monitor) state. * Parameters: - * hDevContext: Handle to Bridge driver defined device context. + * dev_ctxt: Handle to Bridge driver defined device context. * Returns: * 0: Success. * -ETIMEDOUT: Timeout occured waiting for a response from hardware. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL + * dev_ctxt != NULL * Ensures: * 0: Board is in BRD_IDLE state; * else: Board state is indeterminate. */ -typedef int(*fxn_brd_monitor) (struct bridge_dev_context *hDevContext); +typedef int(*fxn_brd_monitor) (struct bridge_dev_context *dev_ctxt); /* * ======== fxn_brd_setstate ======== * Purpose: * Sets the Bridge driver state * Parameters: - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * ulBrdState: Board state * Returns: * 0: Success. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL; + * dev_ctxt != NULL; * ulBrdState <= BRD_LASTSTATE. * Ensures: * ulBrdState <= BRD_LASTSTATE. * Update the Board state to the specified state. */ typedef int(*fxn_brd_setstate) (struct bridge_dev_context - * hDevContext, u32 ulBrdState); + * dev_ctxt, u32 ulBrdState); /* * ======== bridge_brd_start ======== * Purpose: * Bring board to the BRD_RUNNING (start) state. * Parameters: - * hDevContext: Handle to Bridge driver defined device context. + * dev_ctxt: Handle to Bridge driver defined device context. * dsp_addr: DSP address at which to start execution. * Returns: * 0: Success. * -ETIMEDOUT: Timeout occured waiting for a response from hardware. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL + * dev_ctxt != NULL * Board is in monitor (BRD_IDLE) state. * Ensures: * 0: Board is in BRD_RUNNING state. @@ -108,7 +108,7 @@ typedef int(*fxn_brd_setstate) (struct bridge_dev_context * else: Board state is indeterminate. */ typedef int(*fxn_brd_start) (struct bridge_dev_context - * hDevContext, u32 dsp_addr); + * dev_ctxt, u32 dsp_addr); /* * ======== bridge_brd_mem_copy ======== @@ -131,7 +131,7 @@ typedef int(*fxn_brd_start) (struct bridge_dev_context * else: Board state is indeterminate. */ typedef int(*fxn_brd_memcopy) (struct bridge_dev_context - * hDevContext, + * dev_ctxt, u32 ulDspDestAddr, u32 ulDspSrcAddr, u32 ul_num_bytes, u32 ulMemType); @@ -141,7 +141,7 @@ typedef int(*fxn_brd_memcopy) (struct bridge_dev_context * Write a block of host memory into a DSP address, into a given memory * space. Unlike bridge_brd_write, this API does reset the DSP * Parameters: - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * dsp_addr: Address on DSP board (Destination). * pHostBuf: Pointer to host buffer (Source). * ul_num_bytes: Number of bytes to transfer. @@ -151,12 +151,12 @@ typedef int(*fxn_brd_memcopy) (struct bridge_dev_context * -ETIMEDOUT: Timeout occured waiting for a response from hardware. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL; + * dev_ctxt != NULL; * pHostBuf != NULL. * Ensures: */ typedef int(*fxn_brd_memwrite) (struct bridge_dev_context - * hDevContext, + * dev_ctxt, IN u8 *pHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); @@ -166,7 +166,7 @@ typedef int(*fxn_brd_memwrite) (struct bridge_dev_context * Purpose: * Map a MPU memory region to a DSP/IVA memory space * Parameters: - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * ul_mpu_addr: MPU memory region start address. * ulVirtAddr: DSP/IVA memory region u8 address. * ul_num_bytes: Number of bytes to map. @@ -175,11 +175,11 @@ typedef int(*fxn_brd_memwrite) (struct bridge_dev_context * 0: Success. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL; + * dev_ctxt != NULL; * Ensures: */ typedef int(*fxn_brd_memmap) (struct bridge_dev_context - * hDevContext, u32 ul_mpu_addr, + * dev_ctxt, u32 ul_mpu_addr, u32 ulVirtAddr, u32 ul_num_bytes, u32 ulMapAttrs, struct page **mapped_pages); @@ -189,18 +189,18 @@ typedef int(*fxn_brd_memmap) (struct bridge_dev_context * Purpose: * UnMap an MPU memory region from DSP/IVA memory space * Parameters: - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * ulVirtAddr: DSP/IVA memory region u8 address. * ul_num_bytes: Number of bytes to unmap. * Returns: * 0: Success. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL; + * dev_ctxt != NULL; * Ensures: */ typedef int(*fxn_brd_memunmap) (struct bridge_dev_context - * hDevContext, + * dev_ctxt, u32 ulVirtAddr, u32 ul_num_bytes); /* @@ -208,36 +208,36 @@ typedef int(*fxn_brd_memunmap) (struct bridge_dev_context * Purpose: * Bring board to the BRD_STOPPED state. * Parameters: - * hDevContext: Handle to Bridge driver defined device context. + * dev_ctxt: Handle to Bridge driver defined device context. * Returns: * 0: Success. * -ETIMEDOUT: Timeout occured waiting for a response from hardware. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL + * dev_ctxt != NULL * Ensures: * 0: Board is in BRD_STOPPED (stop) state; * Interrupts to the PC are disabled. * else: Board state is indeterminate. */ -typedef int(*fxn_brd_stop) (struct bridge_dev_context *hDevContext); +typedef int(*fxn_brd_stop) (struct bridge_dev_context *dev_ctxt); /* * ======== bridge_brd_status ======== * Purpose: * Report the current state of the board. * Parameters: - * hDevContext: Handle to Bridge driver defined device context. + * dev_ctxt: Handle to Bridge driver defined device context. * pdwState: Ptr to BRD status variable. * Returns: * 0: * Requires: * pdwState != NULL; - * hDevContext != NULL + * dev_ctxt != NULL * Ensures: * *pdwState is one of {BRD_STOPPED, BRD_IDLE, BRD_RUNNING, BRD_UNKNOWN}; */ -typedef int(*fxn_brd_status) (struct bridge_dev_context *hDevContext, +typedef int(*fxn_brd_status) (struct bridge_dev_context *dev_ctxt, int *pdwState); /* @@ -246,7 +246,7 @@ typedef int(*fxn_brd_status) (struct bridge_dev_context *hDevContext, * Read a block of DSP memory, from a given memory space, into a host * buffer. * Parameters: - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * pHostBuf: Pointer to host buffer (Destination). * dsp_addr: Address on DSP board (Source). * ul_num_bytes: Number of bytes to transfer. @@ -256,12 +256,12 @@ typedef int(*fxn_brd_status) (struct bridge_dev_context *hDevContext, * -ETIMEDOUT: Timeout occured waiting for a response from hardware. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL; + * dev_ctxt != NULL; * pHostBuf != NULL. * Ensures: * Will not write more than ul_num_bytes bytes into pHostBuf. */ -typedef int(*fxn_brd_read) (struct bridge_dev_context *hDevContext, +typedef int(*fxn_brd_read) (struct bridge_dev_context *dev_ctxt, OUT u8 *pHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); @@ -272,7 +272,7 @@ typedef int(*fxn_brd_read) (struct bridge_dev_context *hDevContext, * Write a block of host memory into a DSP address, into a given memory * space. * Parameters: - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * dsp_addr: Address on DSP board (Destination). * pHostBuf: Pointer to host buffer (Source). * ul_num_bytes: Number of bytes to transfer. @@ -282,11 +282,11 @@ typedef int(*fxn_brd_read) (struct bridge_dev_context *hDevContext, * -ETIMEDOUT: Timeout occured waiting for a response from hardware. * -EPERM: Other, unspecified error. * Requires: - * hDevContext != NULL; + * dev_ctxt != NULL; * pHostBuf != NULL. * Ensures: */ -typedef int(*fxn_brd_write) (struct bridge_dev_context *hDevContext, +typedef int(*fxn_brd_write) (struct bridge_dev_context *dev_ctxt, IN u8 *pHostBuf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); @@ -690,7 +690,7 @@ typedef int(*fxn_dev_create) (OUT struct bridge_dev_context * Purpose: * Bridge driver specific interface. * Parameters: - * hDevContext: Handle to Bridge driver defined device info. + * dev_ctxt: Handle to Bridge driver defined device info. * dw_cmd: Bridge driver defined command code. * pargs: Pointer to an arbitrary argument structure. * Returns: @@ -701,7 +701,7 @@ typedef int(*fxn_dev_create) (OUT struct bridge_dev_context * IOCTL completion routines provided. * Ensures: */ -typedef int(*fxn_dev_ctrl) (struct bridge_dev_context *hDevContext, +typedef int(*fxn_dev_ctrl) (struct bridge_dev_context *dev_ctxt, u32 dw_cmd, IN OUT void *pargs); /* @@ -712,16 +712,16 @@ typedef int(*fxn_dev_ctrl) (struct bridge_dev_context *hDevContext, * No calls to other Bridge driver functions may subsequently * occur, except for bridge_dev_create(). * Parameters: - * hDevContext: Handle to Bridge driver defined device information. + * dev_ctxt: Handle to Bridge driver defined device information. * Returns: * 0: Success. * -EPERM: Failed to release a resource previously acquired. * Requires: - * hDevContext != NULL; + * dev_ctxt != NULL; * Ensures: * 0: Device context is freed. */ -typedef int(*fxn_dev_destroy) (struct bridge_dev_context *hDevContext); +typedef int(*fxn_dev_destroy) (struct bridge_dev_context *dev_ctxt); /* * ======== bridge_io_create ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index 8b03d4f..62899f2 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -270,21 +270,21 @@ extern int io_sh_msetting(struct io_mgr *hio_mgr, u8 desc, void *pargs); /* Maximum channel bufsize that can be used. */ extern u32 io_buf_size(struct io_mgr *hio_mgr); -extern u32 io_read_value(struct bridge_dev_context *hDevContext, u32 dsp_addr); +extern u32 io_read_value(struct bridge_dev_context *dev_ctxt, u32 dsp_addr); -extern void io_write_value(struct bridge_dev_context *hDevContext, +extern void io_write_value(struct bridge_dev_context *dev_ctxt, u32 dsp_addr, u32 value); -extern u32 io_read_value_long(struct bridge_dev_context *hDevContext, +extern u32 io_read_value_long(struct bridge_dev_context *dev_ctxt, u32 dsp_addr); -extern void io_write_value_long(struct bridge_dev_context *hDevContext, +extern void io_write_value_long(struct bridge_dev_context *dev_ctxt, u32 dsp_addr, u32 value); -extern void io_or_set_value(struct bridge_dev_context *hDevContext, +extern void io_or_set_value(struct bridge_dev_context *dev_ctxt, u32 dsp_addr, u32 value); -extern void io_and_set_value(struct bridge_dev_context *hDevContext, +extern void io_and_set_value(struct bridge_dev_context *dev_ctxt, u32 dsp_addr, u32 value); extern void io_intr_dsp2(IN struct io_mgr *pio_mgr, IN u16 mb_val); diff --git a/drivers/staging/tidspbridge/include/dspbridge/mgr.h b/drivers/staging/tidspbridge/include/dspbridge/mgr.h index ce418ae..e225845 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/mgr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/mgr.h @@ -173,7 +173,7 @@ extern void mgr_exit(void); * Purpose: * Retrieves the MGR handle. Accessor Function * Parameters: - * hMGRHandle: Handle to the Manager Object + * mgr_handle: Handle to the Manager Object * phDCDHandle: Ptr to receive the DCD Handle. * Returns: * 0: Sucess @@ -186,7 +186,7 @@ extern void mgr_exit(void); * -EPERM and *phDCDHandle == NULL */ extern int mgr_get_dcd_handle(IN struct mgr_object - *hMGRHandle, OUT u32 *phDCDHandle); + *mgr_handle, OUT u32 *phDCDHandle); /* * ======== mgr_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldr.h b/drivers/staging/tidspbridge/include/dspbridge/nldr.h index b1dbccd..492c826 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldr.h @@ -41,7 +41,7 @@ extern void nldr_exit(void); extern int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, char *pstrFxn, u32 * pulAddr); -extern int nldr_get_rmm_manager(struct nldr_object *hNldrObject, +extern int nldr_get_rmm_manager(struct nldr_object *nldr, OUT struct rmm_target_obj **phRmmMgr); extern bool nldr_init(void); diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index e9d8439..5358d77 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -118,32 +118,32 @@ extern int node_change_priority(struct node_object *hnode, s32 prio); * Delete all nodes whose owning processor is being destroyed. * Parameters: * hnode_mgr: Node manager object. - * hProc: Handle to processor object being destroyed. + * proc: Handle to processor object being destroyed. * Returns: * 0: Success. - * -EPERM: Unable to delete all nodes belonging to hProc. + * -EPERM: Unable to delete all nodes belonging to proc. * Requires: * Valid hnode_mgr. - * hProc != NULL. + * proc != NULL. * Ensures: */ extern int node_close_orphans(struct node_mgr *hnode_mgr, - struct proc_object *hProc); + struct proc_object *proc); /* * ======== node_connect ======== * Purpose: * Connect two nodes on the DSP, or a node on the DSP to the GPP. In the * case that the connnection is being made between a node on the DSP and - * the GPP, one of the node handles (either hNode1 or hNode2) must be + * the GPP, one of the node handles (either node1 or node2) must be * the constant NODE_HGPPNODE. * Parameters: - * hNode1: Handle of first node to connect to second node. If - * this is a connection from the GPP to hNode2, hNode1 - * must be the constant NODE_HGPPNODE. Otherwise, hNode1 + * node1: Handle of first node to connect to second node. If + * this is a connection from the GPP to node2, node1 + * must be the constant NODE_HGPPNODE. Otherwise, node1 * must be a node handle returned from a successful call * to Node_Allocate(). - * hNode2: Handle of second node. Must be either NODE_HGPPNODE + * node2: Handle of second node. Must be either NODE_HGPPNODE * if this is a connection from DSP node to GPP, or a * node handle returned from a successful call to * node_allocate(). @@ -163,12 +163,12 @@ extern int node_close_orphans(struct node_mgr *hnode_mgr, * pass binary data. * Returns: * 0: Success. - * -EFAULT: Invalid hNode1 or hNode2. + * -EFAULT: Invalid node1 or node2. * -ENOMEM: Insufficient host memory. * -EINVAL: A stream index parameter is invalid. * -EISCONN: A connection already exists for one of the * indices uStream1 or uStream2. - * -EBADR: Either hNode1 or hNode2 is not in the + * -EBADR: Either node1 or node2 is not in the * NODE_ALLOCATED state. * -ECONNREFUSED: No more connections available. * -EPERM: Attempt to make an illegal connection (eg, @@ -178,9 +178,9 @@ extern int node_close_orphans(struct node_mgr *hnode_mgr, * node_init(void) called. * Ensures: */ -extern int node_connect(struct node_object *hNode1, +extern int node_connect(struct node_object *node1, u32 uStream1, - struct node_object *hNode2, + struct node_object *node2, u32 uStream2, OPTIONAL IN struct dsp_strmattr *pattrs, OPTIONAL IN struct dsp_cbdata diff --git a/drivers/staging/tidspbridge/include/dspbridge/proc.h b/drivers/staging/tidspbridge/include/dspbridge/proc.h index 230828c..11fdc97 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/proc.h +++ b/drivers/staging/tidspbridge/include/dspbridge/proc.h @@ -364,7 +364,7 @@ extern int proc_register_notify(void *hprocessor, * Purpose: * Notify the Processor Clients * Parameters: - * hProc : The processor handle. + * proc : The processor handle. * uEvents : Event to be notified about. * Returns: * 0 : Success. @@ -372,18 +372,18 @@ extern int proc_register_notify(void *hprocessor, * -EPERM : Failure to Set or Reset the Event * Requires: * uEvents is Supported or Valid type of Event - * hProc is a valid handle + * proc is a valid handle * PROC Initialized. * Ensures: */ -extern int proc_notify_clients(void *hProc, u32 uEvents); +extern int proc_notify_clients(void *proc, u32 uEvents); /* * ======== proc_notify_all_clients ======== * Purpose: * Notify the Processor Clients * Parameters: - * hProc : The processor handle. + * proc : The processor handle. * uEvents : Event to be notified about. * Returns: * 0 : Success. @@ -391,14 +391,14 @@ extern int proc_notify_clients(void *hProc, u32 uEvents); * -EPERM : Failure to Set or Reset the Event * Requires: * uEvents is Supported or Valid type of Event - * hProc is a valid handle + * proc is a valid handle * PROC Initialized. * Ensures: * Details: * NODE And STRM would use this function to notify their clients * about the state changes in NODE or STRM. */ -extern int proc_notify_all_clients(void *hProc, u32 uEvents); +extern int proc_notify_all_clients(void *proc, u32 uEvents); /* * ======== proc_start ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h index b452a71..1fa7d13 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h +++ b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h @@ -20,8 +20,8 @@ extern int drv_get_proc_ctxt_list(struct process_context **pPctxt, struct drv_object *hdrv_obj); -extern int drv_insert_proc_context(struct drv_object *hDrVObject, - void *hPCtxt); +extern int drv_insert_proc_context(struct drv_object *driver_obj, + void *process_ctxt); extern int drv_remove_all_dmm_res_elements(void *ctxt); @@ -31,7 +31,7 @@ extern int drv_proc_set_pid(void *ctxt, s32 process); extern int drv_remove_all_resources(void *pPctxt); -extern int drv_remove_proc_context(struct drv_object *hDRVObject, +extern int drv_remove_proc_context(struct drv_object *driver_obj, void *pr_ctxt); extern int drv_get_node_res_element(void *hnode, void *node_res, @@ -40,11 +40,11 @@ extern int drv_get_node_res_element(void *hnode, void *node_res, extern int drv_insert_node_res_element(void *hnode, void *node_res, void *ctxt); -extern void drv_proc_node_update_heap_status(void *hNodeRes, s32 status); +extern void drv_proc_node_update_heap_status(void *node_resource, s32 status); extern int drv_remove_node_res_element(void *node_res, void *status); -extern void drv_proc_node_update_status(void *hNodeRes, s32 status); +extern void drv_proc_node_update_status(void *node_resource, s32 status); extern int drv_proc_update_strm_res(u32 num_bufs, void *strm_res); diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index 2c31f31..aac448e 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -1038,10 +1038,10 @@ int dev_remove_proc_object(struct dev_object *hdev_obj, u32 proc_obj) return status; } -int dev_get_dev_type(struct dev_object *hdevObject, u8 *dev_type) +int dev_get_dev_type(struct dev_object *device_obj, u8 *dev_type) { int status = 0; - struct dev_object *dev_obj = (struct dev_object *)hdevObject; + struct dev_object *dev_obj = (struct dev_object *)device_obj; *dev_type = dev_obj->dev_type; diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 72e2804..36ddfdf 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -73,16 +73,16 @@ static int request_bridge_resources(struct cfg_hostres *res); /* GPP PROCESS CLEANUP CODE */ -static int drv_proc_free_node_res(void *hPCtxt); +static int drv_proc_free_node_res(void *process_ctxt); /* Allocate and add a node resource element * This function is called from .Node_Allocate. */ -int drv_insert_node_res_element(void *hnode, void *hNodeRes, - void *hPCtxt) +int drv_insert_node_res_element(void *hnode, void *node_resource, + void *process_ctxt) { struct node_res_object **node_res_obj = - (struct node_res_object **)hNodeRes; - struct process_context *ctxt = (struct process_context *)hPCtxt; + (struct node_res_object **)node_resource; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct node_res_object *temp_node_res = NULL; @@ -113,11 +113,11 @@ int drv_insert_node_res_element(void *hnode, void *hNodeRes, /* Release all Node resources and its context * This is called from .Node_Delete. */ -int drv_remove_node_res_element(void *hNodeRes, void *hPCtxt) +int drv_remove_node_res_element(void *node_resource, void *process_ctxt) { struct node_res_object *node_res_obj = - (struct node_res_object *)hNodeRes; - struct process_context *ctxt = (struct process_context *)hPCtxt; + (struct node_res_object *)node_resource; + struct process_context *ctxt = (struct process_context *)process_ctxt; struct node_res_object *temp_node; int status = 0; @@ -140,9 +140,9 @@ int drv_remove_node_res_element(void *hNodeRes, void *hPCtxt) } /* Actual Node De-Allocation */ -static int drv_proc_free_node_res(void *hPCtxt) +static int drv_proc_free_node_res(void *process_ctxt) { - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct node_res_object *node_list = NULL; struct node_res_object *node_res_obj = NULL; @@ -169,9 +169,9 @@ static int drv_proc_free_node_res(void *hPCtxt) } /* Release all Mapped and Reserved DMM resources */ -int drv_remove_all_dmm_res_elements(void *hPCtxt) +int drv_remove_all_dmm_res_elements(void *process_ctxt) { - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct dmm_map_object *temp_map, *map_obj; struct dmm_rsv_object *temp_rsv, *rsv_obj; @@ -198,29 +198,29 @@ int drv_remove_all_dmm_res_elements(void *hPCtxt) } /* Update Node allocation status */ -void drv_proc_node_update_status(void *hNodeRes, s32 status) +void drv_proc_node_update_status(void *node_resource, s32 status) { struct node_res_object *node_res_obj = - (struct node_res_object *)hNodeRes; - DBC_ASSERT(hNodeRes != NULL); + (struct node_res_object *)node_resource; + DBC_ASSERT(node_resource != NULL); node_res_obj->node_allocated = status; } /* Update Node Heap status */ -void drv_proc_node_update_heap_status(void *hNodeRes, s32 status) +void drv_proc_node_update_heap_status(void *node_resource, s32 status) { struct node_res_object *node_res_obj = - (struct node_res_object *)hNodeRes; - DBC_ASSERT(hNodeRes != NULL); + (struct node_res_object *)node_resource; + DBC_ASSERT(node_resource != NULL); node_res_obj->heap_allocated = status; } /* Release all Node resources and its context * This is called from .bridge_release. */ -int drv_remove_all_node_res_elements(void *hPCtxt) +int drv_remove_all_node_res_elements(void *process_ctxt) { - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct node_res_object *temp_node2 = NULL; struct node_res_object *temp_node = NULL; @@ -237,11 +237,12 @@ int drv_remove_all_node_res_elements(void *hPCtxt) } /* Getting the node resource element */ -int drv_get_node_res_element(void *hnode, void *hNodeRes, - void *hPCtxt) +int drv_get_node_res_element(void *hnode, void *node_resource, + void *process_ctxt) { - struct node_res_object **node_res = (struct node_res_object **)hNodeRes; - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct node_res_object **node_res = + (struct node_res_object **)node_resource; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct node_res_object *temp_node2 = NULL; struct node_res_object *temp_node = NULL; @@ -268,12 +269,12 @@ int drv_get_node_res_element(void *hnode, void *hNodeRes, /* Allocate the STRM resource element * This is called after the actual resource is allocated */ -int drv_proc_insert_strm_res_element(void *hStreamHandle, - void *hstrm_res, void *hPCtxt) +int drv_proc_insert_strm_res_element(void *stream_handle, + void *hstrm_res, void *process_ctxt) { struct strm_res_object **pstrm_res = (struct strm_res_object **)hstrm_res; - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct strm_res_object *temp_strm_res = NULL; @@ -286,7 +287,7 @@ int drv_proc_insert_strm_res_element(void *hStreamHandle, kfree(*pstrm_res); return -EPERM; } - (*pstrm_res)->hstream = hStreamHandle; + (*pstrm_res)->hstream = stream_handle; if (ctxt->pstrm_list != NULL) { temp_strm_res = ctxt->pstrm_list; while (temp_strm_res->next != NULL) @@ -304,10 +305,10 @@ int drv_proc_insert_strm_res_element(void *hStreamHandle, /* Release Stream resource element context * This function called after the actual resource is freed */ -int drv_proc_remove_strm_res_element(void *hstrm_res, void *hPCtxt) +int drv_proc_remove_strm_res_element(void *hstrm_res, void *process_ctxt) { struct strm_res_object *pstrm_res = (struct strm_res_object *)hstrm_res; - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; struct strm_res_object *temp_strm_res; int status = 0; @@ -333,9 +334,9 @@ int drv_proc_remove_strm_res_element(void *hstrm_res, void *hPCtxt) /* Release all Stream resources and its context * This is called from .bridge_release. */ -int drv_remove_all_strm_res_elements(void *hPCtxt) +int drv_remove_all_strm_res_elements(void *process_ctxt) { - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct strm_res_object *strm_res = NULL; struct strm_res_object *strm_tmp = NULL; @@ -375,11 +376,11 @@ int drv_remove_all_strm_res_elements(void *hPCtxt) /* Getting the stream resource element */ int drv_get_strm_res_element(void *hStrm, void *hstrm_res, - void *hPCtxt) + void *process_ctxt) { struct strm_res_object **strm_res = (struct strm_res_object **)hstrm_res; - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; struct strm_res_object *temp_strm2 = NULL; struct strm_res_object *temp_strm; @@ -486,10 +487,10 @@ void drv_exit(void) * purpose: * Invoked during bridge de-initialization */ -int drv_destroy(struct drv_object *hDRVObject) +int drv_destroy(struct drv_object *driver_obj) { int status = 0; - struct drv_object *pdrv_object = (struct drv_object *)hDRVObject; + struct drv_object *pdrv_object = (struct drv_object *)driver_obj; DBC_REQUIRE(refs > 0); DBC_REQUIRE(pdrv_object); @@ -621,19 +622,19 @@ u32 drv_get_next_dev_object(u32 hdev_obj) * called drv_get_first_dev_extension() and zero or more * drv_get_next_dev_extension(). */ -u32 drv_get_next_dev_extension(u32 hDevExtension) +u32 drv_get_next_dev_extension(u32 dev_extension) { u32 dw_dev_extension = 0; struct drv_object *pdrv_obj; - DBC_REQUIRE(hDevExtension != 0); + DBC_REQUIRE(dev_extension != 0); if (DSP_SUCCEEDED(cfg_get_object((u32 *) &pdrv_obj, REG_DRV_OBJECT))) { if ((pdrv_obj->dev_node_string != NULL) && !LST_IS_EMPTY(pdrv_obj->dev_node_string)) { dw_dev_extension = (u32) lst_next(pdrv_obj->dev_node_string, - (struct list_head *)hDevExtension); + (struct list_head *)dev_extension); } } @@ -664,11 +665,11 @@ int drv_init(void) * Purpose: * Insert a DevObject into the list of Manager object. */ -int drv_insert_dev_object(struct drv_object *hDRVObject, +int drv_insert_dev_object(struct drv_object *driver_obj, struct dev_object *hdev_obj) { int status = 0; - struct drv_object *pdrv_object = (struct drv_object *)hDRVObject; + struct drv_object *pdrv_object = (struct drv_object *)driver_obj; DBC_REQUIRE(refs > 0); DBC_REQUIRE(hdev_obj != NULL); @@ -689,11 +690,11 @@ int drv_insert_dev_object(struct drv_object *hDRVObject, * Search for and remove a DeviceObject from the given list of DRV * objects. */ -int drv_remove_dev_object(struct drv_object *hDRVObject, +int drv_remove_dev_object(struct drv_object *driver_obj, struct dev_object *hdev_obj) { int status = -EPERM; - struct drv_object *pdrv_object = (struct drv_object *)hDRVObject; + struct drv_object *pdrv_object = (struct drv_object *)driver_obj; struct list_head *cur_elem; DBC_REQUIRE(refs > 0); diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c b/drivers/staging/tidspbridge/rmgr/drv_interface.c index 27db842..b0fd38e 100644 --- a/drivers/staging/tidspbridge/rmgr/drv_interface.c +++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c @@ -628,10 +628,10 @@ static int bridge_mmap(struct file *filp, struct vm_area_struct *vma) /* To remove all process resources before removing the process from the * process context list */ -int drv_remove_all_resources(void *hPCtxt) +int drv_remove_all_resources(void *process_ctxt) { int status = 0; - struct process_context *ctxt = (struct process_context *)hPCtxt; + struct process_context *ctxt = (struct process_context *)process_ctxt; drv_remove_all_strm_res_elements(ctxt); drv_remove_all_node_res_elements(ctxt); drv_remove_all_dmm_res_elements(ctxt); diff --git a/drivers/staging/tidspbridge/rmgr/mgr.c b/drivers/staging/tidspbridge/rmgr/mgr.c index b1a68ac..52d7865 100644 --- a/drivers/staging/tidspbridge/rmgr/mgr.c +++ b/drivers/staging/tidspbridge/rmgr/mgr.c @@ -303,11 +303,11 @@ void mgr_exit(void) * ======== mgr_get_dcd_handle ======== * Retrieves the MGR handle. Accessor Function. */ -int mgr_get_dcd_handle(struct mgr_object *hMGRHandle, +int mgr_get_dcd_handle(struct mgr_object *mgr_handle, OUT u32 *phDCDHandle) { int status = -EPERM; - struct mgr_object *pmgr_obj = (struct mgr_object *)hMGRHandle; + struct mgr_object *pmgr_obj = (struct mgr_object *)mgr_handle; DBC_REQUIRE(refs > 0); DBC_REQUIRE(phDCDHandle != NULL); diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 0757d9b..91b32cb 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -774,14 +774,14 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, * ======== nldr_get_rmm_manager ======== * Given a NLDR object, retrieve RMM Manager Handle */ -int nldr_get_rmm_manager(struct nldr_object *hNldrObject, +int nldr_get_rmm_manager(struct nldr_object *nldr, OUT struct rmm_target_obj **phRmmMgr) { int status = 0; - struct nldr_object *nldr_obj = hNldrObject; + struct nldr_object *nldr_obj = nldr; DBC_REQUIRE(phRmmMgr != NULL); - if (hNldrObject) { + if (nldr) { *phRmmMgr = nldr_obj->rmm; } else { *phRmmMgr = NULL; diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 1870b80..aaea5bb 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -241,8 +241,8 @@ static struct dsp_bufferattr node_dfltbufattrs = { static void delete_node(struct node_object *hnode, struct process_context *pr_ctxt); static void delete_node_mgr(struct node_mgr *hnode_mgr); -static void fill_stream_connect(struct node_object *hNode1, - struct node_object *hNode2, u32 uStream1, +static void fill_stream_connect(struct node_object *node1, + struct node_object *node2, u32 uStream1, u32 uStream2); static void fill_stream_def(struct node_object *hnode, struct node_strmdef *pstrm_def, @@ -833,8 +833,8 @@ func_end: * Purpose: * Connect two nodes on the DSP, or a node on the DSP to the GPP. */ -int node_connect(struct node_object *hNode1, u32 uStream1, - struct node_object *hNode2, +int node_connect(struct node_object *node1, u32 uStream1, + struct node_object *node2, u32 uStream2, OPTIONAL IN struct dsp_strmattr *pattrs, OPTIONAL IN struct dsp_cbdata *conn_param) { @@ -855,33 +855,33 @@ int node_connect(struct node_object *hNode1, u32 uStream1, int status = 0; DBC_REQUIRE(refs > 0); - if ((hNode1 != (struct node_object *)DSP_HGPPNODE && !hNode1) || - (hNode2 != (struct node_object *)DSP_HGPPNODE && !hNode2)) + if ((node1 != (struct node_object *)DSP_HGPPNODE && !node1) || + (node2 != (struct node_object *)DSP_HGPPNODE && !node2)) status = -EFAULT; if (DSP_SUCCEEDED(status)) { /* The two nodes must be on the same processor */ - if (hNode1 != (struct node_object *)DSP_HGPPNODE && - hNode2 != (struct node_object *)DSP_HGPPNODE && - hNode1->hnode_mgr != hNode2->hnode_mgr) + if (node1 != (struct node_object *)DSP_HGPPNODE && + node2 != (struct node_object *)DSP_HGPPNODE && + node1->hnode_mgr != node2->hnode_mgr) status = -EPERM; /* Cannot connect a node to itself */ - if (hNode1 == hNode2) + if (node1 == node2) status = -EPERM; } if (DSP_SUCCEEDED(status)) { /* node_get_type() will return NODE_GPP if hnode = * DSP_HGPPNODE. */ - node1_type = node_get_type(hNode1); - node2_type = node_get_type(hNode2); + node1_type = node_get_type(node1); + node2_type = node_get_type(node2); /* Check stream indices ranges */ if ((node1_type != NODE_GPP && node1_type != NODE_DEVICE && - uStream1 >= MAX_OUTPUTS(hNode1)) || (node2_type != NODE_GPP + uStream1 >= MAX_OUTPUTS(node1)) || (node2_type != NODE_GPP && node2_type != NODE_DEVICE && uStream2 >= - MAX_INPUTS(hNode2))) + MAX_INPUTS(node2))) status = -EINVAL; } if (DSP_SUCCEEDED(status)) { @@ -911,19 +911,19 @@ int node_connect(struct node_object *hNode1, u32 uStream1, goto func_end; if (node1_type != NODE_GPP) { - hnode_mgr = hNode1->hnode_mgr; + hnode_mgr = node1->hnode_mgr; } else { - DBC_ASSERT(hNode2 != (struct node_object *)DSP_HGPPNODE); - hnode_mgr = hNode2->hnode_mgr; + DBC_ASSERT(node2 != (struct node_object *)DSP_HGPPNODE); + hnode_mgr = node2->hnode_mgr; } /* Enter critical section */ mutex_lock(&hnode_mgr->node_mgr_lock); /* Nodes must be in the allocated state */ - if (node1_type != NODE_GPP && node_get_state(hNode1) != NODE_ALLOCATED) + if (node1_type != NODE_GPP && node_get_state(node1) != NODE_ALLOCATED) status = -EBADR; - if (node2_type != NODE_GPP && node_get_state(hNode2) != NODE_ALLOCATED) + if (node2_type != NODE_GPP && node_get_state(node2) != NODE_ALLOCATED) status = -EBADR; if (DSP_SUCCEEDED(status)) { @@ -931,7 +931,7 @@ int node_connect(struct node_object *hNode1, u32 uStream1, * are not already be used. (Device nodes checked later) */ if (node1_type == NODE_TASK || node1_type == NODE_DAISSOCKET) { output = - &(hNode1->create_args.asa. + &(node1->create_args.asa. task_arg_obj.strm_out_def[uStream1]); if (output->sz_device != NULL) status = -EISCONN; @@ -939,7 +939,7 @@ int node_connect(struct node_object *hNode1, u32 uStream1, } if (node2_type == NODE_TASK || node2_type == NODE_DAISSOCKET) { input = - &(hNode2->create_args.asa. + &(node2->create_args.asa. task_arg_obj.strm_in_def[uStream2]); if (input->sz_device != NULL) status = -EISCONN; @@ -956,10 +956,10 @@ int node_connect(struct node_object *hNode1, u32 uStream1, if (pipe_id == GB_NOBITS) { status = -ECONNREFUSED; } else { - hNode1->outputs[uStream1].type = NODECONNECT; - hNode2->inputs[uStream2].type = NODECONNECT; - hNode1->outputs[uStream1].dev_id = pipe_id; - hNode2->inputs[uStream2].dev_id = pipe_id; + node1->outputs[uStream1].type = NODECONNECT; + node2->inputs[uStream2].type = NODECONNECT; + node1->outputs[uStream1].dev_id = pipe_id; + node2->inputs[uStream2].dev_id = pipe_id; output->sz_device = kzalloc(PIPENAMELEN + 1, GFP_KERNEL); input->sz_device = kzalloc(PIPENAMELEN + 1, GFP_KERNEL); @@ -1050,13 +1050,13 @@ int node_connect(struct node_object *hNode1, u32 uStream1, status = -ENOMEM; func_cont2: if (DSP_SUCCEEDED(status)) { - if (hNode1 == (struct node_object *)DSP_HGPPNODE) { - hNode2->inputs[uStream2].type = HOSTCONNECT; - hNode2->inputs[uStream2].dev_id = chnl_id; + if (node1 == (struct node_object *)DSP_HGPPNODE) { + node2->inputs[uStream2].type = HOSTCONNECT; + node2->inputs[uStream2].dev_id = chnl_id; input->sz_device = pstr_dev_name; } else { - hNode1->outputs[uStream1].type = HOSTCONNECT; - hNode1->outputs[uStream1].dev_id = chnl_id; + node1->outputs[uStream1].type = HOSTCONNECT; + node1->outputs[uStream1].dev_id = chnl_id; output->sz_device = pstr_dev_name; } sprintf(pstr_dev_name, "%s%d", HOSTPREFIX, chnl_id); @@ -1067,15 +1067,15 @@ func_cont2: (node2_type == NODE_DEVICE))) { if (node2_type == NODE_DEVICE) { /* node1 == > device */ - dev_node_obj = hNode2; - hnode = hNode1; - pstream = &(hNode1->outputs[uStream1]); + dev_node_obj = node2; + hnode = node1; + pstream = &(node1->outputs[uStream1]); pstrm_def = output; } else { /* device == > node2 */ - dev_node_obj = hNode1; - hnode = hNode2; - pstream = &(hNode2->inputs[uStream2]); + dev_node_obj = node1; + hnode = node2; + pstream = &(node2->inputs[uStream2]); pstrm_def = input; } /* Set up create args */ @@ -1106,35 +1106,35 @@ func_cont2: if (DSP_SUCCEEDED(status)) { /* Fill in create args */ if (node1_type == NODE_TASK || node1_type == NODE_DAISSOCKET) { - hNode1->create_args.asa.task_arg_obj.num_outputs++; - fill_stream_def(hNode1, output, pattrs); + node1->create_args.asa.task_arg_obj.num_outputs++; + fill_stream_def(node1, output, pattrs); } if (node2_type == NODE_TASK || node2_type == NODE_DAISSOCKET) { - hNode2->create_args.asa.task_arg_obj.num_inputs++; - fill_stream_def(hNode2, input, pattrs); + node2->create_args.asa.task_arg_obj.num_inputs++; + fill_stream_def(node2, input, pattrs); } - /* Update hNode1 and hNode2 stream_connect */ + /* Update node1 and node2 stream_connect */ if (node1_type != NODE_GPP && node1_type != NODE_DEVICE) { - hNode1->num_outputs++; - if (uStream1 > hNode1->max_output_index) - hNode1->max_output_index = uStream1; + node1->num_outputs++; + if (uStream1 > node1->max_output_index) + node1->max_output_index = uStream1; } if (node2_type != NODE_GPP && node2_type != NODE_DEVICE) { - hNode2->num_inputs++; - if (uStream2 > hNode2->max_input_index) - hNode2->max_input_index = uStream2; + node2->num_inputs++; + if (uStream2 > node2->max_input_index) + node2->max_input_index = uStream2; } - fill_stream_connect(hNode1, hNode2, uStream1, uStream2); + fill_stream_connect(node1, node2, uStream1, uStream2); } /* end of sync_enter_cs */ /* Exit critical section */ mutex_unlock(&hnode_mgr->node_mgr_lock); func_end: - dev_dbg(bridge, "%s: hNode1: %p uStream1: %d hNode2: %p uStream2: %d" - "pattrs: %p status: 0x%x\n", __func__, hNode1, - uStream1, hNode2, uStream2, pattrs, status); + dev_dbg(bridge, "%s: node1: %p uStream1: %d node2: %p uStream2: %d" + "pattrs: %p status: 0x%x\n", __func__, node1, + uStream1, node2, uStream2, pattrs, status); return status; } @@ -2699,8 +2699,8 @@ static void delete_node_mgr(struct node_mgr *hnode_mgr) * Purpose: * Fills stream information. */ -static void fill_stream_connect(struct node_object *hNode1, - struct node_object *hNode2, +static void fill_stream_connect(struct node_object *node1, + struct node_object *node2, u32 uStream1, u32 uStream2) { u32 strm_index; @@ -2709,35 +2709,35 @@ static void fill_stream_connect(struct node_object *hNode1, enum node_type node1_type = NODE_TASK; enum node_type node2_type = NODE_TASK; - node1_type = node_get_type(hNode1); - node2_type = node_get_type(hNode2); - if (hNode1 != (struct node_object *)DSP_HGPPNODE) { + node1_type = node_get_type(node1); + node2_type = node_get_type(node2); + if (node1 != (struct node_object *)DSP_HGPPNODE) { if (node1_type != NODE_DEVICE) { - strm_index = hNode1->num_inputs + - hNode1->num_outputs - 1; - strm1 = &(hNode1->stream_connect[strm_index]); + strm_index = node1->num_inputs + + node1->num_outputs - 1; + strm1 = &(node1->stream_connect[strm_index]); strm1->cb_struct = sizeof(struct dsp_streamconnect); strm1->this_node_stream_index = uStream1; } - if (hNode2 != (struct node_object *)DSP_HGPPNODE) { + if (node2 != (struct node_object *)DSP_HGPPNODE) { /* NODE == > NODE */ if (node1_type != NODE_DEVICE) { - strm1->connected_node = hNode2; - strm1->ui_connected_node_id = hNode2->node_uuid; + strm1->connected_node = node2; + strm1->ui_connected_node_id = node2->node_uuid; strm1->connected_node_stream_index = uStream2; strm1->connect_type = CONNECTTYPE_NODEOUTPUT; } if (node2_type != NODE_DEVICE) { - strm_index = hNode2->num_inputs + - hNode2->num_outputs - 1; - strm2 = &(hNode2->stream_connect[strm_index]); + strm_index = node2->num_inputs + + node2->num_outputs - 1; + strm2 = &(node2->stream_connect[strm_index]); strm2->cb_struct = sizeof(struct dsp_streamconnect); strm2->this_node_stream_index = uStream2; - strm2->connected_node = hNode1; - strm2->ui_connected_node_id = hNode1->node_uuid; + strm2->connected_node = node1; + strm2->ui_connected_node_id = node1->node_uuid; strm2->connected_node_stream_index = uStream1; strm2->connect_type = CONNECTTYPE_NODEINPUT; } @@ -2745,9 +2745,9 @@ static void fill_stream_connect(struct node_object *hNode1, strm1->connect_type = CONNECTTYPE_GPPOUTPUT; } else { /* GPP == > NODE */ - DBC_ASSERT(hNode2 != (struct node_object *)DSP_HGPPNODE); - strm_index = hNode2->num_inputs + hNode2->num_outputs - 1; - strm2 = &(hNode2->stream_connect[strm_index]); + DBC_ASSERT(node2 != (struct node_object *)DSP_HGPPNODE); + strm_index = node2->num_inputs + node2->num_outputs - 1; + strm2 = &(node2->stream_connect[strm_index]); strm2->cb_struct = sizeof(struct dsp_streamconnect); strm2->this_node_stream_index = uStream2; strm2->connect_type = CONNECTTYPE_GPPINPUT; diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index 8bcb128..03497e2 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -1873,10 +1873,10 @@ static char **prepend_envp(char **new_envp, char **envp, s32 envp_elems, * Purpose: * Notify the processor the events. */ -int proc_notify_clients(void *hProc, u32 uEvents) +int proc_notify_clients(void *proc, u32 uEvents) { int status = 0; - struct proc_object *p_proc_object = (struct proc_object *)hProc; + struct proc_object *p_proc_object = (struct proc_object *)proc; DBC_REQUIRE(p_proc_object); DBC_REQUIRE(IS_VALID_PROC_EVENT(uEvents)); @@ -1897,10 +1897,10 @@ func_end: * Notify the processor the events. This includes notifying all clients * attached to a particulat DSP. */ -int proc_notify_all_clients(void *hProc, u32 uEvents) +int proc_notify_all_clients(void *proc, u32 uEvents) { int status = 0; - struct proc_object *p_proc_object = (struct proc_object *)hProc; + struct proc_object *p_proc_object = (struct proc_object *)proc; DBC_REQUIRE(IS_VALID_PROC_EVENT(uEvents)); DBC_REQUIRE(refs > 0); @@ -1921,10 +1921,10 @@ func_end: * Purpose: * Retrieves the processor ID. */ -int proc_get_processor_id(void *hProc, u32 * procID) +int proc_get_processor_id(void *proc, u32 * procID) { int status = 0; - struct proc_object *p_proc_object = (struct proc_object *)hProc; + struct proc_object *p_proc_object = (struct proc_object *)proc; if (p_proc_object) *procID = p_proc_object->processor_id; From patchwork Sat Jul 10 02:24:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111191 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Sktb002447 for ; Sat, 10 Jul 2010 02:28:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754009Ab0GJCZj (ORCPT ); Fri, 9 Jul 2010 22:25:39 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:55226 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752576Ab0GJCZX (ORCPT ); Fri, 9 Jul 2010 22:25:23 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PFJk006471 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:15 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PEiM009240; Fri, 9 Jul 2010 21:25:14 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68L021595; Fri, 9 Jul 2010 21:25:13 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 09/15] staging:ti dspbridge: Rename words with camel case. Date: Fri, 9 Jul 2010 21:24:03 -0500 Message-Id: <1278728649-21012-10-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:48 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== pPhysAddr to phys_addr pPhysicalAddress to physical_address ppIntfFxns to if_fxns pProcLoadStat to proc_load_stat pProcStat to proc_lstat ppSym to sym_val pRefData to ref_data pRef to ref preservedBit to preserved_bit pResult to result procID to proc_id pSectInfo to sect_inf pSrc to src pstrContent to str_content pstrDummyFile to str_dummy_file pstrExecFile to str_exec_file ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/io_sm.c | 33 ++++++++++--------- drivers/staging/tidspbridge/hw/hw_mmu.c | 12 +++--- drivers/staging/tidspbridge/hw/hw_mmu.h | 2 +- .../staging/tidspbridge/include/dspbridge/cfg.h | 10 +++--- .../staging/tidspbridge/include/dspbridge/cod.h | 8 ++-- .../staging/tidspbridge/include/dspbridge/dbll.h | 4 +- .../tidspbridge/include/dspbridge/dblldefs.h | 12 +++--- .../staging/tidspbridge/include/dspbridge/dev.h | 10 +++--- .../staging/tidspbridge/include/dspbridge/drv.h | 10 +++--- .../staging/tidspbridge/include/dspbridge/dspapi.h | 4 +- .../tidspbridge/include/dspbridge/dspdefs.h | 4 +- .../staging/tidspbridge/include/dspbridge/dspio.h | 2 +- .../staging/tidspbridge/include/dspbridge/io_sm.h | 6 ++-- .../staging/tidspbridge/include/dspbridge/proc.h | 4 +- drivers/staging/tidspbridge/pmgr/cod.c | 8 ++-- drivers/staging/tidspbridge/pmgr/dbll.c | 14 ++++---- drivers/staging/tidspbridge/pmgr/dev.c | 14 ++++---- drivers/staging/tidspbridge/rmgr/drv.c | 18 +++++----- drivers/staging/tidspbridge/rmgr/nldr.c | 22 ++++++------ drivers/staging/tidspbridge/rmgr/proc.c | 4 +- drivers/staging/tidspbridge/services/cfg.c | 8 ++-- 21 files changed, 105 insertions(+), 104 deletions(-) diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 5090ff1..6a8bdd2 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -148,9 +148,9 @@ static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr); static u32 find_ready_output(struct chnl_mgr *chnl_mgr_obj, struct chnl_object *pchnl, u32 mask); static u32 read_data(struct bridge_dev_context *dev_ctxt, void *dest, - void *pSrc, u32 usize); + void *src, u32 usize); static u32 write_data(struct bridge_dev_context *dev_ctxt, void *dest, - void *pSrc, u32 usize); + void *src, u32 usize); /* Bus Addr (cached kernel) */ static int register_shm_segs(struct io_mgr *hio_mgr, @@ -919,9 +919,9 @@ static void io_dispatch_pm(struct io_mgr *pio_mgr) * out the dispatch of I/O as a non-preemptible event.It can only be * pre-empted by an ISR. */ -void io_dpc(IN OUT unsigned long pRefData) +void io_dpc(IN OUT unsigned long ref_data) { - struct io_mgr *pio_mgr = (struct io_mgr *)pRefData; + struct io_mgr *pio_mgr = (struct io_mgr *)ref_data; struct chnl_mgr *chnl_mgr_obj; struct msg_mgr *msg_mgr_obj; struct deh_mgr *hdeh_mgr; @@ -1702,9 +1702,9 @@ func_end: * Copies buffers from the shared memory to the host buffer. */ static u32 read_data(struct bridge_dev_context *dev_ctxt, void *dest, - void *pSrc, u32 usize) + void *src, u32 usize) { - memcpy(dest, pSrc, usize); + memcpy(dest, src, usize); return usize; } @@ -1713,9 +1713,9 @@ static u32 read_data(struct bridge_dev_context *dev_ctxt, void *dest, * Copies buffers from the host side buffer to the shared memory. */ static u32 write_data(struct bridge_dev_context *dev_ctxt, void *dest, - void *pSrc, u32 usize) + void *src, u32 usize) { - memcpy(dest, pSrc, usize); + memcpy(dest, src, usize); return usize; } @@ -1793,20 +1793,21 @@ int io_sh_msetting(struct io_mgr *hio_mgr, u8 desc, void *pargs) * Gets the Processor's Load information */ int bridge_io_get_proc_load(IN struct io_mgr *hio_mgr, - OUT struct dsp_procloadstat *pProcStat) + OUT struct dsp_procloadstat *proc_lstat) { - pProcStat->curr_load = hio_mgr->shared_mem->load_mon_info.curr_dsp_load; - pProcStat->predicted_load = + proc_lstat->curr_load = + hio_mgr->shared_mem->load_mon_info.curr_dsp_load; + proc_lstat->predicted_load = hio_mgr->shared_mem->load_mon_info.pred_dsp_load; - pProcStat->curr_dsp_freq = + proc_lstat->curr_dsp_freq = hio_mgr->shared_mem->load_mon_info.curr_dsp_freq; - pProcStat->predicted_freq = + proc_lstat->predicted_freq = hio_mgr->shared_mem->load_mon_info.pred_dsp_freq; dev_dbg(bridge, "Curr Load = %d, Pred Load = %d, Curr Freq = %d, " - "Pred Freq = %d\n", pProcStat->curr_load, - pProcStat->predicted_load, pProcStat->curr_dsp_freq, - pProcStat->predicted_freq); + "Pred Freq = %d\n", proc_lstat->curr_load, + proc_lstat->predicted_load, proc_lstat->curr_dsp_freq, + proc_lstat->predicted_freq); return 0; } diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index 84a6332..668fb8a 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -85,7 +85,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); * TypE : const u32 * Description : It indicates the page size * - * Identifier : preservedBit + * Identifier : preserved_bit * Type : const u32 * Description : It indicates the TLB entry is preserved entry * or not @@ -114,7 +114,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); */ static hw_status mmu_set_cam_entry(const void __iomem *base_address, const u32 page_sz, - const u32 preservedBit, + const u32 preserved_bit, const u32 validBit, const u32 virtual_addr_tag); @@ -337,7 +337,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, u32 page_sz, u32 entry_num, struct hw_mmu_map_attrs_t *map_attrs, - s8 preservedBit, s8 validBit) + s8 preserved_bit, s8 validBit) { hw_status status = RET_OK; u32 lock_reg; @@ -380,7 +380,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, virtual_addr_tag = ((virtualAddr & MMU_ADDR_MASK) >> 12); /* Write the fields in the CAM Entry Register */ - mmu_set_cam_entry(base_address, mmu_pg_size, preservedBit, validBit, + mmu_set_cam_entry(base_address, mmu_pg_size, preserved_bit, validBit, virtual_addr_tag); /* Write the different fields of the RAM Entry Register */ @@ -538,7 +538,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address) /* mmu_set_cam_entry */ static hw_status mmu_set_cam_entry(const void __iomem *base_address, const u32 page_sz, - const u32 preservedBit, + const u32 preserved_bit, const u32 validBit, const u32 virtual_addr_tag) { @@ -551,7 +551,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, mmu_cam_reg = (virtual_addr_tag << 12); mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (validBit << 2) | - (preservedBit << 3); + (preserved_bit << 3); /* write values to register */ MMUMMU_CAM_WRITE_REGISTER32(base_address, mmu_cam_reg); diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h index 063efbb..25f1954 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.h +++ b/drivers/staging/tidspbridge/hw/hw_mmu.h @@ -85,7 +85,7 @@ extern hw_status hw_mmu_tlb_add(const void __iomem *base_address, u32 page_sz, u32 entry_num, struct hw_mmu_map_attrs_t *map_attrs, - s8 preservedBit, s8 validBit); + s8 preserved_bit, s8 validBit); /* For PTEs */ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfg.h b/drivers/staging/tidspbridge/include/dspbridge/cfg.h index 6fdd229..98cadb1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cfg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cfg.h @@ -100,20 +100,20 @@ extern int cfg_get_dev_object(IN struct cfg_devnode *dev_node_obj, * Parameters: * dev_node_obj: Handle to the dev_node who's driver we are querying. * buf_size: Size of buffer. - * pstrExecFile: Ptr to character buf to hold ExecFile. + * str_exec_file: Ptr to character buf to hold ExecFile. * Returns: * 0: Success. - * -EFAULT: dev_node_obj is invalid or pstrExecFile is invalid. + * -EFAULT: dev_node_obj is invalid or str_exec_file is invalid. * -ENODATA: The resource is not available. * Requires: * CFG initialized. * Ensures: - * 0: Not more than buf_size bytes were copied into pstrExecFile, - * and *pstrExecFile contains default executable for this + * 0: Not more than buf_size bytes were copied into str_exec_file, + * and *str_exec_file contains default executable for this * devnode. */ extern int cfg_get_exec_file(IN struct cfg_devnode *dev_node_obj, - IN u32 buf_size, OUT char *pstrExecFile); + IN u32 buf_size, OUT char *str_exec_file); /* * ======== cfg_get_object ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index 0cc1bd2..f8cbb21 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -350,7 +350,7 @@ extern int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, * Parameters: * cod_mgr_obj - manager in which to search for the symbol * pstrSect - name of the section, with or without leading "." - * pstrContent - buffer to store content of the section. + * str_content - buffer to store content of the section. * Returns: * 0: on success, error code on failure * -ESPIPE: Symbols have not been loaded onto the board. @@ -358,12 +358,12 @@ extern int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, * COD module initialized. * valid cod_mgr_obj. * pstrSect != NULL; - * pstrContent != NULL; + * str_content != NULL; * Ensures: - * 0: *pstrContent stores the content of the named section. + * 0: *str_content stores the content of the named section. */ extern int cod_read_section(struct cod_libraryobj *lib, IN char *pstrSect, - OUT char *pstrContent, IN u32 content_size); + OUT char *str_content, IN u32 content_size); #endif /* COD_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbll.h b/drivers/staging/tidspbridge/include/dspbridge/dbll.h index 6378555..a4dea0c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbll.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbll.h @@ -31,11 +31,11 @@ extern int dbll_create(struct dbll_tar_obj **target_obj, extern void dbll_delete(struct dbll_tar_obj *target); extern void dbll_exit(void); extern bool dbll_get_addr(struct dbll_library_obj *lib, char *name, - struct dbll_sym_val **ppSym); + struct dbll_sym_val **sym_val); extern void dbll_get_attrs(struct dbll_tar_obj *target, struct dbll_attrs *pattrs); extern bool dbll_get_c_addr(struct dbll_library_obj *lib, char *name, - struct dbll_sym_val **ppSym); + struct dbll_sym_val **sym_val); extern int dbll_get_sect(struct dbll_library_obj *lib, char *name, u32 *paddr, u32 *psize); extern bool dbll_init(void); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h index 23eca15..b827320 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h @@ -239,7 +239,7 @@ typedef void (*dbll_exit_fxn) (void); * Parameters: * lib - Handle returned from dbll_open(). * name - Name of symbol - * ppSym - Location to store symbol address on output. + * sym_val - Location to store symbol address on output. * Returns: * TRUE: Success. * FALSE: Symbol not found. @@ -247,11 +247,11 @@ typedef void (*dbll_exit_fxn) (void); * DBL initialized. * Valid library. * name != NULL. - * ppSym != NULL. + * sym_val != NULL. * Ensures: */ typedef bool(*dbll_get_addr_fxn) (struct dbll_library_obj *lib, char *name, - struct dbll_sym_val **ppSym); + struct dbll_sym_val **sym_val); /* * ======== dbll_get_attrs ======== @@ -275,7 +275,7 @@ typedef void (*dbll_get_attrs_fxn) (struct dbll_tar_obj *target, * Parameters: * lib - Handle returned from dbll_open(). * name - Name of symbol - * ppSym - Location to store symbol address on output. + * sym_val - Location to store symbol address on output. * Returns: * TRUE: Success. * FALSE: Symbol not found. @@ -283,11 +283,11 @@ typedef void (*dbll_get_attrs_fxn) (struct dbll_tar_obj *target, * DBL initialized. * Valid target. * name != NULL. - * ppSym != NULL. + * sym_val != NULL. * Ensures: */ typedef bool(*dbll_get_c_addr_fxn) (struct dbll_library_obj *lib, char *name, - struct dbll_sym_val **ppSym); + struct dbll_sym_val **sym_val); /* * ======== dbll_get_sect ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index a646402..d658df5 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -367,20 +367,20 @@ extern struct dev_object *dev_get_first(void); * Parameters: * hdev_obj: Handle to device object created with * dev_create_device(). - * *ppIntfFxns: Ptr to location to store fxn interface. + * *if_fxns: Ptr to location to store fxn interface. * Returns: * 0: Success. * -EFAULT: Invalid hdev_obj. * Requires: - * ppIntfFxns != NULL. + * if_fxns != NULL. * DEV Initialized. * Ensures: - * 0: *ppIntfFxns contains a pointer to the Bridge + * 0: *if_fxns contains a pointer to the Bridge * driver interface; - * else: *ppIntfFxns is NULL. + * else: *if_fxns is NULL. */ extern int dev_get_intf_fxns(struct dev_object *hdev_obj, - OUT struct bridge_drv_interface **ppIntfFxns); + OUT struct bridge_drv_interface **if_fxns); /* * ======== dev_get_io_mgr ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index 604c15b..b43d22f 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -451,7 +451,7 @@ extern void mem_ext_phys_pool_release(void); * Parameters: * byte_size: Number of bytes to allocate. * ulAlign: Alignment Mask. - * pPhysicalAddress: Physical address of allocated memory. + * physical_address: Physical address of allocated memory. * Returns: * Pointer to a block of memory; * NULL if memory couldn't be allocated, or if byte_size == 0. @@ -463,7 +463,7 @@ extern void mem_ext_phys_pool_release(void); * location of memory. */ extern void *mem_alloc_phys_mem(IN u32 byte_size, - IN u32 ulAlign, OUT u32 *pPhysicalAddress); + IN u32 ulAlign, OUT u32 *physical_address); /* * ======== mem_free_phys_mem ======== @@ -472,7 +472,7 @@ extern void *mem_alloc_phys_mem(IN u32 byte_size, * Parameters: * pVirtualAddress: Pointer to virtual memory region allocated * by mem_alloc_phys_mem(). - * pPhysicalAddress: Pointer to physical memory region allocated + * physical_address: Pointer to physical memory region allocated * by mem_alloc_phys_mem(). * byte_size: Size of the memory region allocated by mem_alloc_phys_mem(). * Returns: @@ -484,14 +484,14 @@ extern void *mem_alloc_phys_mem(IN u32 byte_size, * pVirtualAddress is no longer a valid pointer to memory. */ extern void mem_free_phys_mem(void *pVirtualAddress, - u32 pPhysicalAddress, u32 byte_size); + u32 physical_address, u32 byte_size); /* * ======== MEM_LINEAR_ADDRESS ======== * Purpose: * Get the linear address corresponding to the given physical address. * Parameters: - * pPhysAddr: Physical address to be mapped. + * phys_addr: Physical address to be mapped. * byte_size: Number of bytes in physical range to map. * Returns: * The corresponding linear address, or NULL if unsuccessful. diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspapi.h b/drivers/staging/tidspbridge/include/dspbridge/dspapi.h index f84ac69..765a175 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspapi.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspapi.h @@ -42,7 +42,7 @@ * Parameters: * cmd: IOCTL id, base 0. * args: Argument structure. - * pResult: + * result: * Returns: * 0 if command called; -EINVAL if command not in IOCTL * table. @@ -51,7 +51,7 @@ */ extern int api_call_dev_ioctl(unsigned int cmd, union Trapped_Args *args, - u32 *pResult, void *pr_ctxt); + u32 *result, void *pr_ctxt); /* * ======== api_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 04df01d..ed6388e 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -787,7 +787,7 @@ typedef int(*fxn_io_onloaded) (struct io_mgr *hio_mgr); * Called to get the Processor's current and predicted load * Parameters: * hio_mgr: IO Manager. - * pProcLoadStat Processor Load statistics + * proc_load_stat Processor Load statistics * Returns: * 0: Success. * -EPERM: Internal failure occurred. @@ -797,7 +797,7 @@ typedef int(*fxn_io_onloaded) (struct io_mgr *hio_mgr); */ typedef int(*fxn_io_getprocload) (struct io_mgr *hio_mgr, struct dsp_procloadstat * - pProcLoadStat); + proc_load_stat); /* * ======== bridge_msg_create ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspio.h b/drivers/staging/tidspbridge/include/dspbridge/dspio.h index 93dc592..2b9e19c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspio.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspio.h @@ -36,6 +36,6 @@ extern int bridge_io_on_loaded(struct io_mgr *hio_mgr); extern int iva_io_on_loaded(struct io_mgr *hio_mgr); extern int bridge_io_get_proc_load(IN struct io_mgr *hio_mgr, - OUT struct dsp_procloadstat *pProcStat); + OUT struct dsp_procloadstat *proc_lstat); #endif /* DSPIO_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index 7e598ee..1627e0a 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -68,7 +68,7 @@ extern void io_cancel_chnl(struct io_mgr *hio_mgr, u32 ulChnl); * Deferred procedure call for shared memory channel driver ISR. Carries * out the dispatch of I/O. * Parameters: - * pRefData: Pointer to reference data registered via a call to + * ref_data: Pointer to reference data registered via a call to * DPC_Create(). * Returns: * Requires: @@ -78,7 +78,7 @@ extern void io_cancel_chnl(struct io_mgr *hio_mgr, u32 ulChnl); * Ensures: * Non-preemptible (but interruptible). */ -extern void io_dpc(IN OUT unsigned long pRefData); +extern void io_dpc(IN OUT unsigned long ref_data); /* * ======== io_mbox_msg ======== @@ -87,7 +87,7 @@ extern void io_dpc(IN OUT unsigned long pRefData); * Calls the Bridge's chnlsm_isr to determine if this interrupt is ours, * then schedules a DPC to dispatch I/O. * Parameters: - * pRefData: Pointer to the channel manager object for this board. + * ref_data: Pointer to the channel manager object for this board. * Set in an initial call to ISR_Install(). * Returns: * TRUE if interrupt handled; FALSE otherwise. diff --git a/drivers/staging/tidspbridge/include/dspbridge/proc.h b/drivers/staging/tidspbridge/include/dspbridge/proc.h index cbd26dc..5583bd5 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/proc.h +++ b/drivers/staging/tidspbridge/include/dspbridge/proc.h @@ -265,7 +265,7 @@ extern int proc_get_state(void *hprocessor, OUT struct dsp_processorstate * Report the state of the specified DSP processor. * Parameters: * hprocessor : The processor handle. - * procID : Processor ID + * proc_id : Processor ID * * Returns: * 0 : Success. @@ -278,7 +278,7 @@ extern int proc_get_state(void *hprocessor, OUT struct dsp_processorstate * Ensures: * Details: */ -extern int proc_get_processor_id(void *hprocessor, u32 * procID); +extern int proc_get_processor_id(void *hprocessor, u32 * proc_id); /* * ======== proc_get_trace ======== diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index ab54388..e4fc065 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -215,7 +215,7 @@ void cod_close(struct cod_libraryobj *lib) * dynamically loaded object files. * */ -int cod_create(OUT struct cod_manager **mgr, char *pstrDummyFile, +int cod_create(OUT struct cod_manager **mgr, char *str_dummy_file, IN OPTIONAL CONST struct cod_attrs *attrs) { struct cod_manager *mgr_new; @@ -626,7 +626,7 @@ int cod_open_base(struct cod_manager *hmgr, IN char *pszCoffPath, * Retrieve the content of a code section given the section name. */ int cod_read_section(struct cod_libraryobj *lib, IN char *pstrSect, - OUT char *pstrContent, IN u32 content_size) + OUT char *str_content, IN u32 content_size) { int status = 0; @@ -634,12 +634,12 @@ int cod_read_section(struct cod_libraryobj *lib, IN char *pstrSect, DBC_REQUIRE(lib != NULL); DBC_REQUIRE(IS_VALID(lib->cod_mgr)); DBC_REQUIRE(pstrSect != NULL); - DBC_REQUIRE(pstrContent != NULL); + DBC_REQUIRE(str_content != NULL); if (lib != NULL) status = lib->cod_mgr->fxns.read_sect_fxn(lib->dbll_lib, pstrSect, - pstrContent, content_size); + str_content, content_size); else status = -ESPIPE; diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index 45133e0..e94ef6b 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -300,7 +300,7 @@ void dbll_exit(void) * Get address of name in the specified library. */ bool dbll_get_addr(struct dbll_library_obj *zl_lib, char *name, - struct dbll_sym_val **ppSym) + struct dbll_sym_val **sym_val) { struct dbll_symbol *sym; bool status = false; @@ -308,17 +308,17 @@ bool dbll_get_addr(struct dbll_library_obj *zl_lib, char *name, DBC_REQUIRE(refs > 0); DBC_REQUIRE(zl_lib); DBC_REQUIRE(name != NULL); - DBC_REQUIRE(ppSym != NULL); + DBC_REQUIRE(sym_val != NULL); DBC_REQUIRE(zl_lib->sym_tab != NULL); sym = (struct dbll_symbol *)gh_find(zl_lib->sym_tab, name); if (sym != NULL) { - *ppSym = &sym->value; + *sym_val = &sym->value; status = true; } dev_dbg(bridge, "%s: lib: %p name: %s paddr: %p, status 0x%x\n", - __func__, zl_lib, name, ppSym, status); + __func__, zl_lib, name, sym_val, status); return status; } @@ -344,7 +344,7 @@ void dbll_get_attrs(struct dbll_tar_obj *target, struct dbll_attrs *pattrs) * Get address of a "C" name in the specified library. */ bool dbll_get_c_addr(struct dbll_library_obj *zl_lib, char *name, - struct dbll_sym_val **ppSym) + struct dbll_sym_val **sym_val) { struct dbll_symbol *sym; char cname[MAXEXPR + 1]; @@ -352,7 +352,7 @@ bool dbll_get_c_addr(struct dbll_library_obj *zl_lib, char *name, DBC_REQUIRE(refs > 0); DBC_REQUIRE(zl_lib); - DBC_REQUIRE(ppSym != NULL); + DBC_REQUIRE(sym_val != NULL); DBC_REQUIRE(zl_lib->sym_tab != NULL); DBC_REQUIRE(name != NULL); @@ -365,7 +365,7 @@ bool dbll_get_c_addr(struct dbll_library_obj *zl_lib, char *name, sym = (struct dbll_symbol *)gh_find(zl_lib->sym_tab, cname); if (sym != NULL) { - *ppSym = &sym->value; + *sym_val = &sym->value; status = true; } diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index 50fedcc..5098f7f 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -585,26 +585,26 @@ struct dev_object *dev_get_first(void) * ======== dev_get_intf_fxns ======== * Purpose: * Retrieve the Bridge interface function structure for the loaded driver. - * ppIntfFxns != NULL. + * if_fxns != NULL. */ int dev_get_intf_fxns(struct dev_object *hdev_obj, - OUT struct bridge_drv_interface **ppIntfFxns) + OUT struct bridge_drv_interface **if_fxns) { int status = 0; struct dev_object *dev_obj = hdev_obj; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(ppIntfFxns != NULL); + DBC_REQUIRE(if_fxns != NULL); if (hdev_obj) { - *ppIntfFxns = &dev_obj->bridge_interface; + *if_fxns = &dev_obj->bridge_interface; } else { - *ppIntfFxns = NULL; + *if_fxns = NULL; status = -EFAULT; } - DBC_ENSURE(DSP_SUCCEEDED(status) || ((ppIntfFxns != NULL) && - (*ppIntfFxns == NULL))); + DBC_ENSURE(DSP_SUCCEEDED(status) || ((if_fxns != NULL) && + (*if_fxns == NULL))); return status; } diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index ef147b7..f38123d 100755 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -969,7 +969,7 @@ void mem_ext_phys_pool_release(void) * Allocate physically contiguous, uncached memory from external memory pool */ -static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * pPhysAddr) +static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * phys_addr) { u32 new_alloc_ptr; u32 offset; @@ -980,7 +980,7 @@ static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * pPhysAddr) if (bytes > ((ext_mem_pool.phys_mem_base + ext_mem_pool.phys_mem_size) - ext_mem_pool.next_phys_alloc_ptr)) { - pPhysAddr = NULL; + phys_addr = NULL; return NULL; } else { offset = (ext_mem_pool.next_phys_alloc_ptr & (align - 1)); @@ -992,7 +992,7 @@ static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * pPhysAddr) if ((new_alloc_ptr + bytes) <= (ext_mem_pool.phys_mem_base + ext_mem_pool.phys_mem_size)) { /* we can allocate */ - *pPhysAddr = new_alloc_ptr; + *phys_addr = new_alloc_ptr; ext_mem_pool.next_phys_alloc_ptr = new_alloc_ptr + bytes; virt_addr = @@ -1001,7 +1001,7 @@ static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * pPhysAddr) phys_mem_base); return (void *)virt_addr; } else { - *pPhysAddr = 0; + *phys_addr = 0; return NULL; } } @@ -1012,7 +1012,7 @@ static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * pPhysAddr) * Purpose: * Allocate physically contiguous, uncached memory */ -void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, OUT u32 * pPhysicalAddress) +void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, OUT u32 * physical_address) { void *va_mem = NULL; dma_addr_t pa_mem; @@ -1025,9 +1025,9 @@ void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, OUT u32 * pPhysicalAddress) va_mem = dma_alloc_coherent(NULL, byte_size, &pa_mem, GFP_KERNEL); if (va_mem == NULL) - *pPhysicalAddress = 0; + *physical_address = 0; else - *pPhysicalAddress = pa_mem; + *physical_address = pa_mem; } return va_mem; } @@ -1037,12 +1037,12 @@ void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, OUT u32 * pPhysicalAddress) * Purpose: * Free the given block of physically contiguous memory. */ -void mem_free_phys_mem(void *pVirtualAddress, u32 pPhysicalAddress, +void mem_free_phys_mem(void *pVirtualAddress, u32 physical_address, u32 byte_size) { DBC_REQUIRE(pVirtualAddress != NULL); if (!ext_phys_mem_pool_enabled) dma_free_coherent(NULL, byte_size, pVirtualAddress, - pPhysicalAddress); + physical_address); } diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index f385cbc..0c8a165 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -289,7 +289,7 @@ static int add_ovly_node(struct dsp_uuid *uuid_obj, enum dsp_dcdobjtype obj_type, IN void *handle); static int add_ovly_sect(struct nldr_object *nldr_obj, struct ovly_sect **lst, - struct dbll_sect_info *pSectInfo, + struct dbll_sect_info *sect_inf, bool *exists, u32 addr, u32 bytes); static s32 fake_ovly_write(void *handle, u32 dsp_address, void *buf, u32 bytes, s32 mtype); @@ -304,11 +304,11 @@ static int load_lib(struct nldr_nodeobject *nldr_node_obj, enum nldr_phase phase, u16 depth); static int load_ovly(struct nldr_nodeobject *nldr_node_obj, enum nldr_phase phase); -static int remote_alloc(void **pRef, u16 mem_sect_type, u32 size, +static int remote_alloc(void **ref, u16 mem_sect_type, u32 size, u32 align, u32 *dsp_address, OPTIONAL s32 segmentId, OPTIONAL s32 req, bool reserve); -static int remote_free(void **pRef, u16 space, u32 dsp_address, u32 size, +static int remote_free(void **ref, u16 space, u32 dsp_address, u32 size, bool reserve); static void unload_lib(struct nldr_nodeobject *nldr_node_obj, @@ -1072,7 +1072,7 @@ func_end: */ static int add_ovly_sect(struct nldr_object *nldr_obj, struct ovly_sect **lst, - struct dbll_sect_info *pSectInfo, + struct dbll_sect_info *sect_inf, bool *exists, u32 addr, u32 bytes) { struct ovly_sect *new_sect = NULL; @@ -1103,10 +1103,10 @@ static int add_ovly_sect(struct nldr_object *nldr_obj, status = -ENOMEM; } else { new_sect->sect_load_addr = addr; - new_sect->sect_run_addr = pSectInfo->sect_run_addr + - (addr - pSectInfo->sect_load_addr); + new_sect->sect_run_addr = sect_inf->sect_run_addr + + (addr - sect_inf->sect_load_addr); new_sect->size = bytes; - new_sect->page = pSectInfo->type; + new_sect->page = sect_inf->type; } /* Add to the list */ @@ -1623,12 +1623,12 @@ func_end: /* * ======== remote_alloc ======== */ -static int remote_alloc(void **pRef, u16 space, u32 size, +static int remote_alloc(void **ref, u16 space, u32 size, u32 align, u32 *dsp_address, OPTIONAL s32 segmentId, OPTIONAL s32 req, bool reserve) { - struct nldr_nodeobject *hnode = (struct nldr_nodeobject *)pRef; + struct nldr_nodeobject *hnode = (struct nldr_nodeobject *)ref; struct nldr_object *nldr_obj; struct rmm_target_obj *rmm; u16 mem_phase_bit = MAXFLAGS; @@ -1744,10 +1744,10 @@ func_cont: return status; } -static int remote_free(void **pRef, u16 space, u32 dsp_address, +static int remote_free(void **ref, u16 space, u32 dsp_address, u32 size, bool reserve) { - struct nldr_object *nldr_obj = (struct nldr_object *)pRef; + struct nldr_object *nldr_obj = (struct nldr_object *)ref; struct rmm_target_obj *rmm; u32 word_size; int status = -ENOMEM; /* Set to fail */ diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index 20f887b..eb81645 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -1921,13 +1921,13 @@ func_end: * Purpose: * Retrieves the processor ID. */ -int proc_get_processor_id(void *proc, u32 * procID) +int proc_get_processor_id(void *proc, u32 * proc_id) { int status = 0; struct proc_object *p_proc_object = (struct proc_object *)proc; if (p_proc_object) - *procID = p_proc_object->processor_id; + *proc_id = p_proc_object->processor_id; else status = -EFAULT; diff --git a/drivers/staging/tidspbridge/services/cfg.c b/drivers/staging/tidspbridge/services/cfg.c index 53ede23..ac23b09 100644 --- a/drivers/staging/tidspbridge/services/cfg.c +++ b/drivers/staging/tidspbridge/services/cfg.c @@ -112,7 +112,7 @@ int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, * Retreive the default executable, if any, for this board. */ int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, - OUT char *pstrExecFile) + OUT char *str_exec_file) { int status = 0; struct drv_data *drv_datap = dev_get_drvdata(bridge); @@ -120,19 +120,19 @@ int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, if (!dev_node_obj) status = -EFAULT; - else if (!pstrExecFile || !drv_datap) + else if (!str_exec_file || !drv_datap) status = -EFAULT; if (strlen(drv_datap->base_img) > ul_buf_size) status = -EINVAL; if (DSP_SUCCEEDED(status) && drv_datap->base_img) - strcpy(pstrExecFile, drv_datap->base_img); + strcpy(str_exec_file, drv_datap->base_img); if (DSP_FAILED(status)) pr_err("%s: Failed, status 0x%x\n", __func__, status); DBC_ENSURE(((status == 0) && - (strlen(pstrExecFile) <= ul_buf_size)) + (strlen(str_exec_file) <= ul_buf_size)) || (status != 0)); return status; } From patchwork Sat Jul 10 02:24:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111192 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Sktc002447 for ; Sat, 10 Jul 2010 02:28:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754023Ab0GJCZk (ORCPT ); Fri, 9 Jul 2010 22:25:40 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:45777 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752520Ab0GJCZX (ORCPT ); Fri, 9 Jul 2010 22:25:23 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PE0O025244 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:14 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6A2PDVW026429; Fri, 9 Jul 2010 21:25:13 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68J021595; Fri, 9 Jul 2010 21:25:12 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 07/15] staging:ti dspbridge: Rename words with camel case Date: Fri, 9 Jul 2010 21:24:01 -0500 Message-Id: <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:49 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== phNldrObj to nldr_ovlyobj phNldr to nldr phNodeMgr to node_man pHostBuf to host_buf pHostConfig to host_config phRmmMgr to rmm_mgr phStrmMgr to strm_man phStrm to strm_objct phXlator to xlator physicalAddr to physical_addr pInfo to channel_info pIOC to chan_ioc pLib to lib_obj pList to lst pMemBuf to mem_buf ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/chnl_sm.c | 50 ++++++++-------- drivers/staging/tidspbridge/hw/hw_mmu.c | 24 ++++---- drivers/staging/tidspbridge/hw/hw_mmu.h | 4 +- .../staging/tidspbridge/include/dspbridge/cmm.h | 6 +- .../staging/tidspbridge/include/dspbridge/cod.h | 4 +- .../staging/tidspbridge/include/dspbridge/dbll.h | 3 +- .../tidspbridge/include/dspbridge/dblldefs.h | 10 ++-- .../staging/tidspbridge/include/dspbridge/dev.h | 28 +++++----- .../tidspbridge/include/dspbridge/dspchnl.h | 6 +- .../tidspbridge/include/dspbridge/dspdefs.h | 42 +++++++------- .../staging/tidspbridge/include/dspbridge/list.h | 60 ++++++++++---------- .../staging/tidspbridge/include/dspbridge/nldr.h | 4 +- .../tidspbridge/include/dspbridge/nldrdefs.h | 10 ++-- .../staging/tidspbridge/include/dspbridge/node.h | 14 ++-- .../tidspbridge/include/dspbridge/nodepriv.h | 6 +- .../staging/tidspbridge/include/dspbridge/strm.h | 20 +++--- drivers/staging/tidspbridge/pmgr/cmm.c | 8 +- drivers/staging/tidspbridge/pmgr/cod.c | 8 +- drivers/staging/tidspbridge/pmgr/dbll.c | 16 +++--- drivers/staging/tidspbridge/pmgr/dev.c | 18 +++--- drivers/staging/tidspbridge/rmgr/nldr.c | 34 ++++++------ drivers/staging/tidspbridge/rmgr/node.c | 26 ++++---- drivers/staging/tidspbridge/rmgr/strm.c | 31 +++++----- 23 files changed, 217 insertions(+), 215 deletions(-) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index cec3bb5..4c61a31 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -75,7 +75,7 @@ /* ----------------------------------- Function Prototypes */ static struct lst_list *create_chirp_list(u32 uChirps); -static void free_chirp_list(struct lst_list *pList); +static void free_chirp_list(struct lst_list *lst); static struct chnl_irp *make_new_chirp(void); @@ -88,7 +88,7 @@ static int search_free_channel(struct chnl_mgr *chnl_mgr_obj, * The direction (mode) is specified in the channel object. Note the DSP * address is specified for channels opened in direct I/O mode. */ -int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *pHostBuf, +int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *host_buf, u32 byte_size, u32 buf_size, OPTIONAL u32 dw_dsp_addr, u32 dw_arg) { @@ -107,7 +107,7 @@ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *pHostBuf, is_eos = (byte_size == 0); /* Validate args */ - if (!pHostBuf || !pchnl) { + if (!host_buf || !pchnl) { status = -EFAULT; } else if (is_eos && CHNL_IS_INPUT(pchnl->chnl_mode)) { status = -EPERM; @@ -137,9 +137,9 @@ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *pHostBuf, if (DSP_FAILED(status)) goto func_end; - if (pchnl->chnl_type == CHNL_PCPY && pchnl->chnl_id > 1 && pHostBuf) { - if (!(pHostBuf < (void *)USERMODE_ADDR)) { - host_sys_buf = pHostBuf; + if (pchnl->chnl_type == CHNL_PCPY && pchnl->chnl_id > 1 && host_buf) { + if (!(host_buf < (void *)USERMODE_ADDR)) { + host_sys_buf = host_buf; goto func_cont; } /* if addr in user mode, then copy to kernel space */ @@ -149,7 +149,7 @@ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *pHostBuf, goto func_end; } if (CHNL_IS_OUTPUT(pchnl->chnl_mode)) { - status = copy_from_user(host_sys_buf, pHostBuf, + status = copy_from_user(host_sys_buf, host_buf, buf_size); if (status) { kfree(host_sys_buf); @@ -188,7 +188,7 @@ func_cont: if (DSP_SUCCEEDED(status)) { /* Enqueue the chirp on the chnl's IORequest queue: */ chnl_packet_obj->host_user_buf = chnl_packet_obj->host_sys_buf = - pHostBuf; + host_buf; if (pchnl->chnl_type == CHNL_PCPY && pchnl->chnl_id > 1) chnl_packet_obj->host_sys_buf = host_sys_buf; @@ -533,23 +533,23 @@ int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 timeout) * Retrieve information related to a channel. */ int bridge_chnl_get_info(struct chnl_object *chnl_obj, - OUT struct chnl_info *pInfo) + OUT struct chnl_info *channel_info) { int status = 0; struct chnl_object *pchnl = (struct chnl_object *)chnl_obj; - if (pInfo != NULL) { + if (channel_info != NULL) { if (pchnl) { /* Return the requested information: */ - pInfo->hchnl_mgr = pchnl->chnl_mgr_obj; - pInfo->event_obj = pchnl->user_event; - pInfo->cnhl_id = pchnl->chnl_id; - pInfo->dw_mode = pchnl->chnl_mode; - pInfo->bytes_tx = pchnl->bytes_moved; - pInfo->process = pchnl->process; - pInfo->sync_event = pchnl->sync_event; - pInfo->cio_cs = pchnl->cio_cs; - pInfo->cio_reqs = pchnl->cio_reqs; - pInfo->dw_state = pchnl->dw_state; + channel_info->hchnl_mgr = pchnl->chnl_mgr_obj; + channel_info->event_obj = pchnl->user_event; + channel_info->cnhl_id = pchnl->chnl_id; + channel_info->dw_mode = pchnl->chnl_mode; + channel_info->bytes_tx = pchnl->bytes_moved; + channel_info->process = pchnl->process; + channel_info->sync_event = pchnl->sync_event; + channel_info->cio_cs = pchnl->cio_cs; + channel_info->cio_reqs = pchnl->cio_reqs; + channel_info->dw_state = pchnl->dw_state; } else { status = -EFAULT; } @@ -567,7 +567,7 @@ int bridge_chnl_get_info(struct chnl_object *chnl_obj, * Note: Ensures Channel Invariant (see notes above). */ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout, - OUT struct chnl_ioc *pIOC) + OUT struct chnl_ioc *chan_ioc) { int status = 0; struct chnl_object *pchnl = (struct chnl_object *)chnl_obj; @@ -580,7 +580,7 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout, struct dev_object *dev_obj; /* Check args: */ - if (!pIOC || !pchnl) { + if (!chan_ioc || !pchnl) { status = -EFAULT; } else if (timeout == CHNL_IOCNOWAIT) { if (LST_IS_EMPTY(pchnl->pio_completions)) @@ -623,11 +623,11 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout, spin_lock_bh(&pchnl->chnl_mgr_obj->chnl_mgr_lock); omap_mbox_disable_irq(dev_ctxt->mbox, IRQ_RX); if (dequeue_ioc) { - /* Dequeue IOC and set pIOC; */ + /* Dequeue IOC and set chan_ioc; */ DBC_ASSERT(!LST_IS_EMPTY(pchnl->pio_completions)); chnl_packet_obj = (struct chnl_irp *)lst_get_head(pchnl->pio_completions); - /* Update pIOC from channel state and chirp: */ + /* Update chan_ioc from channel state and chirp: */ if (chnl_packet_obj) { pchnl->cio_cs--; /* If this is a zero-copy channel, then set IOC's pbuf @@ -700,7 +700,7 @@ func_cont1: } func_cont: /* Update User's IOC block: */ - *pIOC = ioc; + *chan_ioc = ioc; func_end: return status; } diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index 2bb64cd..84a6332 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -127,7 +127,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, * Type : const u32 * Description : Base Address of instance of MMU module * - * Identifier : physicalAddr + * Identifier : physical_addr * Type : const u32 * Description : Physical Address to which the corresponding * virtual Address shouldpoint @@ -158,7 +158,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, * METHOD: : Check the Input parameters and set the RAM entry. */ static hw_status mmu_set_ram_entry(const void __iomem *base_address, - const u32 physicalAddr, + const u32 physical_addr, enum hw_endianism_t endianism, enum hw_element_size_t element_size, enum hw_mmu_mixed_size_t mixed_size); @@ -332,7 +332,7 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, } hw_status hw_mmu_tlb_add(const void __iomem *base_address, - u32 physicalAddr, + u32 physical_addr, u32 virtualAddr, u32 page_sz, u32 entry_num, @@ -385,7 +385,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, /* Write the different fields of the RAM Entry Register */ /* endianism of the page,Element Size of the page (8, 16, 32, 64 bit) */ - mmu_set_ram_entry(base_address, physicalAddr, map_attrs->endianism, + mmu_set_ram_entry(base_address, physical_addr, map_attrs->endianism, map_attrs->element_size, map_attrs->mixed_size); /* Update the MMU Lock Register */ @@ -402,7 +402,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, } hw_status hw_mmu_pte_set(const u32 pg_tbl_va, - u32 physicalAddr, + u32 physical_addr, u32 virtualAddr, u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs) { @@ -416,7 +416,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, virtualAddr & MMU_SMALL_PAGE_MASK); pte_val = - ((physicalAddr & MMU_SMALL_PAGE_MASK) | + ((physical_addr & MMU_SMALL_PAGE_MASK) | (map_attrs->endianism << 9) | (map_attrs-> element_size << 4) | (map_attrs->mixed_size << 11) | 2); @@ -428,7 +428,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, virtualAddr & MMU_LARGE_PAGE_MASK); pte_val = - ((physicalAddr & MMU_LARGE_PAGE_MASK) | + ((physical_addr & MMU_LARGE_PAGE_MASK) | (map_attrs->endianism << 9) | (map_attrs-> element_size << 4) | (map_attrs->mixed_size << 11) | 1); @@ -439,7 +439,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, virtualAddr & MMU_SECTION_ADDR_MASK); pte_val = - ((((physicalAddr & MMU_SECTION_ADDR_MASK) | + ((((physical_addr & MMU_SECTION_ADDR_MASK) | (map_attrs->endianism << 15) | (map_attrs-> element_size << 10) | (map_attrs->mixed_size << 17)) & ~0x40000) | 0x2); @@ -451,7 +451,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, virtualAddr & MMU_SSECTION_ADDR_MASK); pte_val = - (((physicalAddr & MMU_SSECTION_ADDR_MASK) | + (((physical_addr & MMU_SSECTION_ADDR_MASK) | (map_attrs->endianism << 15) | (map_attrs-> element_size << 10) | (map_attrs->mixed_size << 17) @@ -462,7 +462,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, virtualAddr & MMU_SECTION_ADDR_MASK); - pte_val = (physicalAddr & MMU_PAGE_TABLE_MASK) | 1; + pte_val = (physical_addr & MMU_PAGE_TABLE_MASK) | 1; break; default: @@ -561,7 +561,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, /* mmu_set_ram_entry */ static hw_status mmu_set_ram_entry(const void __iomem *base_address, - const u32 physicalAddr, + const u32 physical_addr, enum hw_endianism_t endianism, enum hw_element_size_t element_size, enum hw_mmu_mixed_size_t mixed_size) @@ -576,7 +576,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address, RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE + RES_INVALID_INPUT_PARAM); - mmu_ram_reg = (physicalAddr & MMU_ADDR_MASK); + mmu_ram_reg = (physical_addr & MMU_ADDR_MASK); mmu_ram_reg = (mmu_ram_reg) | ((endianism << 9) | (element_size << 7) | (mixed_size << 6)); diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h index aeedbe2..063efbb 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.h +++ b/drivers/staging/tidspbridge/hw/hw_mmu.h @@ -80,7 +80,7 @@ extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, u32 page_sz); extern hw_status hw_mmu_tlb_add(const void __iomem *base_address, - u32 physicalAddr, + u32 physical_addr, u32 virtualAddr, u32 page_sz, u32 entry_num, @@ -89,7 +89,7 @@ extern hw_status hw_mmu_tlb_add(const void __iomem *base_address, /* For PTEs */ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, - u32 physicalAddr, + u32 physical_addr, u32 virtualAddr, u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index d36972e..22d053b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -281,7 +281,7 @@ extern void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, * address translation. Node messaging and streams use this to perform * inter-processor(GPP<->DSP) zero-copy data transfer. * Parameters: - * phXlator: Address to place handle to a new Xlator handle. + * xlator: Address to place handle to a new Xlator handle. * hcmm_mgr: Handle to Cmm Mgr associated with this translator. * pXlatorAttrs: Translator attributes used for the client NODE or STREAM. * Returns: @@ -289,13 +289,13 @@ extern void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, * -EINVAL: Bad input Attrs. * -ENOMEM: Insufficient memory(local) for requested resources. * Requires: - * phXlator != NULL + * xlator != NULL * hcmm_mgr != NULL * pXlatorAttrs != NULL * Ensures: * */ -extern int cmm_xlator_create(OUT struct cmm_xlatorobject **phXlator, +extern int cmm_xlator_create(OUT struct cmm_xlatorobject **xlator, struct cmm_object *hcmm_mgr, struct cmm_xlatorattrs *pXlatorAttrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index 63bb874..0cc1bd2 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -307,7 +307,7 @@ extern int cod_load_base(struct cod_manager *cod_mgr_obj, * pszCoffPath: Coff file to open. * flags: COD_NOLOAD (don't load symbols) or COD_SYMB (load * symbols). - * pLib: Handle returned that can be used in calls to cod_close + * lib_obj: Handle returned that can be used in calls to cod_close * and cod_get_section. * Returns: * S_OK: Success. @@ -321,7 +321,7 @@ extern int cod_load_base(struct cod_manager *cod_mgr_obj, */ extern int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, - u32 flags, OUT struct cod_libraryobj **pLib); + u32 flags, OUT struct cod_libraryobj **lib_obj); /* * ======== cod_open_base ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbll.h b/drivers/staging/tidspbridge/include/dspbridge/dbll.h index daf8105..6378555 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbll.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbll.h @@ -45,7 +45,8 @@ extern int dbll_load(struct dbll_library_obj *lib, extern int dbll_load_sect(struct dbll_library_obj *lib, char *sectName, struct dbll_attrs *attrs); extern int dbll_open(struct dbll_tar_obj *target, char *file, - dbll_flags flags, struct dbll_library_obj **pLib); + dbll_flags flags, + struct dbll_library_obj **lib_obj); extern int dbll_read_sect(struct dbll_library_obj *lib, char *name, char *pbuf, u32 size); extern void dbll_set_attrs(struct dbll_tar_obj *target, diff --git a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h index da8abf4..23eca15 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h @@ -379,7 +379,7 @@ typedef int(*dbll_load_sect_fxn) (struct dbll_library_obj *lib, * target - Handle returned from dbll_create(). * file - Name of file to open. * flags - If flags & DBLL_SYMB, load symbols. - * pLib - Location to store library handle on output. + * lib_obj - Location to store library handle on output. * Returns: * 0: Success. * -ENOMEM: Memory allocation failure. @@ -389,15 +389,15 @@ typedef int(*dbll_load_sect_fxn) (struct dbll_library_obj *lib, * DBL initialized. * Valid target. * file != NULL. - * pLib != NULL. + * lib_obj != NULL. * dbll_attrs fopen function non-NULL. * Ensures: - * Success: Valid *pLib. - * Failure: *pLib == NULL. + * Success: Valid *lib_obj. + * Failure: *lib_obj == NULL. */ typedef int(*dbll_open_fxn) (struct dbll_tar_obj *target, char *file, dbll_flags flags, - struct dbll_library_obj **pLib); + struct dbll_library_obj **lib_obj); /* * ======== dbll_read_sect ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index 68aa0b1..a646402 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -43,7 +43,7 @@ * arb: Handle to a Device Object. * dev_ctxt: Handle to Bridge driver defined device info. * dsp_addr: Address on DSP board (Destination). - * pHostBuf: Pointer to host buffer (Source). + * host_buf: Pointer to host buffer (Source). * ul_num_bytes: Number of bytes to transfer. * ulMemType: Memory space on DSP to which to transfer. * Returns: @@ -51,12 +51,12 @@ * arb is invalid. * Requires: * DEV Initialized. - * pHostBuf != NULL + * host_buf != NULL * Ensures: */ extern u32 dev_brd_write_fxn(void *arb, u32 ulDspAddr, - void *pHostBuf, u32 ul_num_bytes, u32 mem_space); + void *host_buf, u32 ul_num_bytes, u32 mem_space); /* * ======== dev_create_device ======== @@ -68,7 +68,7 @@ extern u32 dev_brd_write_fxn(void *arb, * driver_file_name: Name of Bridge driver PE DLL file to load. If the * absolute path is not provided, the file is loaded * through 'Bridge's module search path. - * pHostConfig: Host configuration information, to be passed down + * host_config: Host configuration information, to be passed down * to the Bridge driver when bridge_dev_create() is called. * pDspConfig: DSP resources, to be passed down to the Bridge driver * when bridge_dev_create() is called. @@ -82,7 +82,7 @@ extern u32 dev_brd_write_fxn(void *arb, * DEV Initialized. * device_obj != NULL. * driver_file_name != NULL. - * pHostConfig != NULL. + * host_config != NULL. * pDspConfig != NULL. * Ensures: * 0: *device_obj will contain handle to the new device object. @@ -103,7 +103,7 @@ extern int dev_create_device(OUT struct dev_object * driver_file_name: Name of Bridge driver PE DLL file to load. If the * absolute path is not provided, the file is loaded * through 'Bridge's module search path. - * pHostConfig: Host configuration information, to be passed down + * host_config: Host configuration information, to be passed down * to the Bridge driver when bridge_dev_create() is called. * pDspConfig: DSP resources, to be passed down to the Bridge driver * when bridge_dev_create() is called. @@ -117,7 +117,7 @@ extern int dev_create_device(OUT struct dev_object * DEV Initialized. * device_obj != NULL. * driver_file_name != NULL. - * pHostConfig != NULL. + * host_config != NULL. * pDspConfig != NULL. * Ensures: * 0: *device_obj will contain handle to the new device object. @@ -128,7 +128,7 @@ extern int dev_create_iva_device(OUT struct dev_object **device_obj, IN CONST char *driver_file_name, IN CONST struct cfg_hostres - *pHostConfig, + *host_config, struct cfg_devnode *dev_node_obj); /* @@ -439,7 +439,7 @@ extern struct dev_object *dev_get_next(struct dev_object * Requires: * DEV Initialized. * Valid hdev_obj. - * phNodeMgr != NULL. + * node_man != NULL. * Ensures: */ extern void dev_get_msg_mgr(struct dev_object *hdev_obj, @@ -452,21 +452,21 @@ extern void dev_get_msg_mgr(struct dev_object *hdev_obj, * accessor function * Parameters: * hdev_obj: Handle to the Dev Object - * phNodeMgr: Location where Handle to the Node Manager will be + * node_man: Location where Handle to the Node Manager will be * returned.. * Returns: * 0: Success * -EFAULT: Invalid Dev Object handle. * Requires: * DEV Initialized. - * phNodeMgr is not null + * node_man is not null * Ensures: - * 0: *phNodeMgr contains a handle to a Node manager object. - * else: *phNodeMgr is NULL. + * 0: *node_man contains a handle to a Node manager object. + * else: *node_man is NULL. */ extern int dev_get_node_manager(struct dev_object *hdev_obj, - OUT struct node_mgr **phNodeMgr); + OUT struct node_mgr **node_man); /* * ======== dev_get_symbol ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h index c009204..a4e0c84 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h @@ -41,12 +41,12 @@ extern int bridge_chnl_open(OUT struct chnl_object **chnl, extern int bridge_chnl_close(struct chnl_object *chnl_obj); extern int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, - void *pHostBuf, + void *host_buf, u32 byte_size, u32 buf_size, OPTIONAL u32 dw_dsp_addr, u32 dw_arg); extern int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, - u32 timeout, OUT struct chnl_ioc *pIOC); + u32 timeout, OUT struct chnl_ioc *chan_ioc); extern int bridge_chnl_cancel_io(struct chnl_object *chnl_obj); @@ -54,7 +54,7 @@ extern int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 timeout); extern int bridge_chnl_get_info(struct chnl_object *chnl_obj, - OUT struct chnl_info *pInfo); + OUT struct chnl_info *channel_info); extern int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 uChnlID, OUT struct chnl_mgrinfo diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 42930cc..e3c7232 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -143,7 +143,7 @@ typedef int(*fxn_brd_memcopy) (struct bridge_dev_context * Parameters: * dev_ctxt: Handle to Bridge driver defined device info. * dsp_addr: Address on DSP board (Destination). - * pHostBuf: Pointer to host buffer (Source). + * host_buf: Pointer to host buffer (Source). * ul_num_bytes: Number of bytes to transfer. * ulMemType: Memory space on DSP to which to transfer. * Returns: @@ -152,12 +152,12 @@ typedef int(*fxn_brd_memcopy) (struct bridge_dev_context * -EPERM: Other, unspecified error. * Requires: * dev_ctxt != NULL; - * pHostBuf != NULL. + * host_buf != NULL. * Ensures: */ typedef int(*fxn_brd_memwrite) (struct bridge_dev_context * dev_ctxt, - IN u8 *pHostBuf, + IN u8 *host_buf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); @@ -248,7 +248,7 @@ typedef int(*fxn_brd_status) (struct bridge_dev_context *dev_ctxt, * buffer. * Parameters: * dev_ctxt: Handle to Bridge driver defined device info. - * pHostBuf: Pointer to host buffer (Destination). + * host_buf: Pointer to host buffer (Destination). * dsp_addr: Address on DSP board (Source). * ul_num_bytes: Number of bytes to transfer. * ulMemType: Memory space on DSP from which to transfer. @@ -258,12 +258,12 @@ typedef int(*fxn_brd_status) (struct bridge_dev_context *dev_ctxt, * -EPERM: Other, unspecified error. * Requires: * dev_ctxt != NULL; - * pHostBuf != NULL. + * host_buf != NULL. * Ensures: - * Will not write more than ul_num_bytes bytes into pHostBuf. + * Will not write more than ul_num_bytes bytes into host_buf. */ typedef int(*fxn_brd_read) (struct bridge_dev_context *dev_ctxt, - OUT u8 *pHostBuf, + OUT u8 *host_buf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); @@ -275,7 +275,7 @@ typedef int(*fxn_brd_read) (struct bridge_dev_context *dev_ctxt, * Parameters: * dev_ctxt: Handle to Bridge driver defined device info. * dsp_addr: Address on DSP board (Destination). - * pHostBuf: Pointer to host buffer (Source). + * host_buf: Pointer to host buffer (Source). * ul_num_bytes: Number of bytes to transfer. * ulMemType: Memory space on DSP to which to transfer. * Returns: @@ -284,11 +284,11 @@ typedef int(*fxn_brd_read) (struct bridge_dev_context *dev_ctxt, * -EPERM: Other, unspecified error. * Requires: * dev_ctxt != NULL; - * pHostBuf != NULL. + * host_buf != NULL. * Ensures: */ typedef int(*fxn_brd_write) (struct bridge_dev_context *dev_ctxt, - IN u8 *pHostBuf, + IN u8 *host_buf, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); @@ -442,7 +442,7 @@ typedef int(*fxn_chnl_close) (struct chnl_object *chnl_obj); * address is specified for channels opened in direct I/O mode. * Parameters: * chnl_obj: Channel object handle. - * pHostBuf: Host buffer address source. + * host_buf: Host buffer address source. * byte_size: Number of PC bytes to transfer. A zero value indicates * that this buffer is the last in the output channel. * A zero value is invalid for an input channel. @@ -451,7 +451,7 @@ typedef int(*fxn_chnl_close) (struct chnl_object *chnl_obj); * dw_arg: A user argument that travels with the buffer. * Returns: * 0: Success; - * -EFAULT: Invalid chnl_obj or pHostBuf. + * -EFAULT: Invalid chnl_obj or host_buf. * -EPERM: User cannot mark EOS on an input channel. * -ECANCELED: I/O has been cancelled on this channel. No further * I/O is allowed. @@ -472,7 +472,7 @@ typedef int(*fxn_chnl_close) (struct chnl_object *chnl_obj); */ typedef int(*fxn_chnl_addioreq) (struct chnl_object * chnl_obj, - void *pHostBuf, + void *host_buf, u32 byte_size, u32 buf_size, OPTIONAL u32 dw_dsp_addr, u32 dw_arg); @@ -486,12 +486,12 @@ typedef int(*fxn_chnl_addioreq) (struct chnl_object * chnl_obj: Channel object handle. * timeout: A value of CHNL_IOCNOWAIT will simply dequeue the * first available IOC. - * pIOC: On output, contains host buffer address, bytes + * chan_ioc: On output, contains host buffer address, bytes * transferred, and status of I/O completion. - * pIOC->status: See chnldefs.h. + * chan_ioc->status: See chnldefs.h. * Returns: * 0: Success. - * -EFAULT: Invalid chnl_obj or pIOC. + * -EFAULT: Invalid chnl_obj or chan_ioc. * -EREMOTEIO: CHNL_IOCNOWAIT was specified as the timeout parameter * yet no I/O completions were queued. * Requires: @@ -503,7 +503,7 @@ typedef int(*fxn_chnl_addioreq) (struct chnl_object */ typedef int(*fxn_chnl_getioc) (struct chnl_object *chnl_obj, u32 timeout, - OUT struct chnl_ioc *pIOC); + OUT struct chnl_ioc *chan_ioc); /* * ======== bridge_chnl_cancel_io ======== @@ -551,14 +551,14 @@ typedef int(*fxn_chnl_flushio) (struct chnl_object *chnl_obj, * Retrieve information related to a channel. * Parameters: * chnl_obj: Handle to a valid channel object, or NULL. - * pInfo: Location to store channel info. + * channel_info: Location to store channel info. * Returns: * 0: Success; - * -EFAULT: Invalid chnl_obj or pInfo. + * -EFAULT: Invalid chnl_obj or channel_info. * Requires: * Ensures: - * 0: pInfo points to a filled in chnl_info struct, - * if (pInfo != NULL). + * 0: channel_info points to a filled in chnl_info struct, + * if (channel_info != NULL). */ typedef int(*fxn_chnl_getinfo) (struct chnl_object *chnl_obj, OUT struct chnl_info *channel_info); diff --git a/drivers/staging/tidspbridge/include/dspbridge/list.h b/drivers/staging/tidspbridge/include/dspbridge/list.h index 2cf885d..6837b61 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/list.h +++ b/drivers/staging/tidspbridge/include/dspbridge/list.h @@ -35,18 +35,18 @@ struct lst_list { * Returns a pointer to the first element of the list, or NULL if the list * is empty. * Parameters: - * pList: Pointer to list control structure. + * lst: Pointer to list control structure. * Returns: * Pointer to first list element, or NULL. * Requires: * - LST initialized. - * - pList != NULL. + * - lst != NULL. * Ensures: */ -static inline struct list_head *lst_first(struct lst_list *pList) +static inline struct list_head *lst_first(struct lst_list *lst) { - if (pList && !list_empty(&pList->head)) - return pList->head.next; + if (lst && !list_empty(&lst->head)) + return lst->head.next; return NULL; } @@ -64,30 +64,30 @@ static inline struct list_head *lst_first(struct lst_list *pList) * element. So the next element after the head becomes the new head of * the list. * Parameters: - * pList: Pointer to list control structure of list whose head + * lst: Pointer to list control structure of list whose head * element is to be removed * Returns: * Pointer to element that was at the head of the list (success) * NULL No elements in list * Requires: * - LST initialized. - * - pList != NULL. + * - lst != NULL. * Ensures: * Notes: * Because the tail of the list points forward (its "next" pointer) to * the head of the list, and the head of the list points backward (its * "prev" pointer) to the tail of the list, this list is circular. */ -static inline struct list_head *lst_get_head(struct lst_list *pList) +static inline struct list_head *lst_get_head(struct lst_list *lst) { struct list_head *elem_list; - if (!pList || list_empty(&pList->head)) + if (!lst || list_empty(&lst->head)) return NULL; - elem_list = pList->head.next; - pList->head.next = elem_list->next; - elem_list->next->prev = &pList->head; + elem_list = lst->head.next; + lst->head.next = elem_list->next; + elem_list->next->prev = &lst->head; return elem_list; } @@ -121,22 +121,22 @@ static inline void lst_init_elem(struct list_head *elem_list) * Purpose: * Insert the element before the existing element. * Parameters: - * pList: Pointer to list control structure. + * lst: Pointer to list control structure. * elem_list: Pointer to element in list to insert. * elem_existing: Pointer to existing list element. * Returns: * Requires: * - LST initialized. - * - pList != NULL. + * - lst != NULL. * - elem_list != NULL. * - elem_existing != NULL. * Ensures: */ -static inline void lst_insert_before(struct lst_list *pList, +static inline void lst_insert_before(struct lst_list *lst, struct list_head *elem_list, struct list_head *elem_existing) { - if (pList && elem_list && elem_existing) + if (lst && elem_list && elem_existing) list_add_tail(elem_list, elem_existing); } @@ -146,21 +146,21 @@ static inline void lst_insert_before(struct lst_list *pList, * Returns a pointer to the next element of the list, or NULL if the next * element is the head of the list or the list is empty. * Parameters: - * pList: Pointer to list control structure. + * lst: Pointer to list control structure. * cur_elem: Pointer to element in list to remove. * Returns: * Pointer to list element, or NULL. * Requires: * - LST initialized. - * - pList != NULL. + * - lst != NULL. * - cur_elem != NULL. * Ensures: */ -static inline struct list_head *lst_next(struct lst_list *pList, +static inline struct list_head *lst_next(struct lst_list *lst, struct list_head *cur_elem) { - if (pList && !list_empty(&pList->head) && cur_elem && - (cur_elem->next != &pList->head)) + if (lst && !list_empty(&lst->head) && cur_elem && + (cur_elem->next != &lst->head)) return cur_elem->next; return NULL; } @@ -179,13 +179,13 @@ static inline struct list_head *lst_next(struct lst_list *pList, * Sets new element's next pointer to the address of the head element. * Sets head's prev pointer to the address of the new element. * Parameters: - * pList: Pointer to list control structure to which *elem_list will be + * lst: Pointer to list control structure to which *elem_list will be * added * elem_list: Pointer to list element to be added * Returns: * Void * Requires: - * *elem_list and *pList must both exist. + * *elem_list and *lst must both exist. * LST initialized. * Ensures: * Notes: @@ -193,11 +193,11 @@ static inline struct list_head *lst_next(struct lst_list *pList, * tail's "next" pointer points at the head of the list, and the head's * "prev" pointer points at the tail of the list), the list is circular. */ -static inline void lst_put_tail(struct lst_list *pList, +static inline void lst_put_tail(struct lst_list *lst, struct list_head *elem_list) { - if (pList && elem_list) - list_add_tail(elem_list, &pList->head); + if (lst && elem_list) + list_add_tail(elem_list, &lst->head); } /* @@ -206,19 +206,19 @@ static inline void lst_put_tail(struct lst_list *pList, * Removes (unlinks) the given element from the list, if the list is not * empty. Does not free the list element. * Parameters: - * pList: Pointer to list control structure. + * lst: Pointer to list control structure. * cur_elem: Pointer to element in list to remove. * Returns: * Requires: * - LST initialized. - * - pList != NULL. + * - lst != NULL. * - cur_elem != NULL. * Ensures: */ -static inline void lst_remove_elem(struct lst_list *pList, +static inline void lst_remove_elem(struct lst_list *lst, struct list_head *cur_elem) { - if (pList && !list_empty(&pList->head) && cur_elem) + if (lst && !list_empty(&lst->head) && cur_elem) list_del_init(cur_elem); } diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldr.h b/drivers/staging/tidspbridge/include/dspbridge/nldr.h index 3482fe3..b2bfb5e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldr.h @@ -31,7 +31,7 @@ extern int nldr_allocate(struct nldr_object *nldr_obj, OUT struct nldr_nodeobject **nldr_nodeobj, IN bool *pf_phase_split); -extern int nldr_create(OUT struct nldr_object **phNldr, +extern int nldr_create(OUT struct nldr_object **nldr, struct dev_object *hdev_obj, IN CONST struct nldr_attrs *pattrs); @@ -42,7 +42,7 @@ extern int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, char *pstrFxn, u32 * pulAddr); extern int nldr_get_rmm_manager(struct nldr_object *nldr, - OUT struct rmm_target_obj **phRmmMgr); + OUT struct rmm_target_obj **rmm_mgr); extern bool nldr_init(void); extern int nldr_load(struct nldr_nodeobject *nldr_node_obj, diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h index 17c5d70..e15ef67 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h @@ -141,7 +141,7 @@ typedef int(*nldr_allocatefxn) (struct nldr_object *nldr_obj, * create, delete, and execute phase functions of nodes on the DSP target. * * Parameters: - * phNldr: Location to store loader handle on output. + * nldr: Location to store loader handle on output. * hdev_obj: Device for this processor. * pattrs: Loader attributes. * Returns: @@ -149,14 +149,14 @@ typedef int(*nldr_allocatefxn) (struct nldr_object *nldr_obj, * -ENOMEM: Insufficient memory for requested resources. * Requires: * nldr_init(void) called. - * phNldr != NULL. + * nldr != NULL. * hdev_obj != NULL. * pattrs != NULL. * Ensures: - * 0: Valid *phNldr. - * error: *phNldr == NULL. + * 0: Valid *nldr. + * error: *nldr == NULL. */ -typedef int(*nldr_createfxn) (OUT struct nldr_object **phNldr, +typedef int(*nldr_createfxn) (OUT struct nldr_object **nldr, struct dev_object *hdev_obj, IN CONST struct nldr_attrs *pattrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index 9dfa3a8..70f3e89 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -217,7 +217,7 @@ extern int node_create(struct node_object *hnode); * Each DEV object should have exactly one NODE Manager object. * * Parameters: - * phNodeMgr: Location to store node manager handle on output. + * node_man: Location to store node manager handle on output. * hdev_obj: Device for this processor. * Returns: * 0: Success; @@ -225,13 +225,13 @@ extern int node_create(struct node_object *hnode); * -EPERM: General failure. * Requires: * node_init(void) called. - * phNodeMgr != NULL. + * node_man != NULL. * hdev_obj != NULL. * Ensures: - * 0: Valide *phNodeMgr. - * error: *phNodeMgr == NULL. + * 0: Valide *node_man. + * error: *node_man == NULL. */ -extern int node_create_mgr(OUT struct node_mgr **phNodeMgr, +extern int node_create_mgr(OUT struct node_mgr **node_man, struct dev_object *hdev_obj); /* @@ -392,14 +392,14 @@ extern int node_get_message(struct node_object *hnode, * Retrieve the Nldr manager * Parameters: * hnode_mgr: Node Manager - * phNldrObj: Pointer to a Nldr manager handle + * nldr_ovlyobj: Pointer to a Nldr manager handle * Returns: * 0: Success. * -EFAULT: Invalid hnode. * Ensures: */ extern int node_get_nldr_obj(struct node_mgr *hnode_mgr, - OUT struct nldr_object **phNldrObj); + OUT struct nldr_object **nldr_ovlyobj); /* * ======== node_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h index 42e1a94..0dc6dc7 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h @@ -110,16 +110,16 @@ extern int node_get_channel_id(struct node_object *hnode, * Get the STRM manager for a node. * Parameters: * hnode: Node allocated with node_allocate(). - * phStrmMgr: Location to store STRM manager on output. + * strm_man: Location to store STRM manager on output. * Returns: * 0: Success. * -EFAULT: Invalid hnode. * Requires: - * phStrmMgr != NULL. + * strm_man != NULL. * Ensures: */ extern int node_get_strm_mgr(struct node_object *hnode, - struct strm_mgr **phStrmMgr); + struct strm_mgr **strm_man); /* * ======== node_get_timeout ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/strm.h b/drivers/staging/tidspbridge/include/dspbridge/strm.h index c4a4d65..6572442 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/strm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/strm.h @@ -75,7 +75,7 @@ extern int strm_close(struct strm_object *stream_obj, * Create a STRM manager object. This object holds information about the * device needed to open streams. * Parameters: - * phStrmMgr: Location to store handle to STRM manager object on + * strm_man: Location to store handle to STRM manager object on * output. * dev_obj: Device for this processor. * Returns: @@ -84,13 +84,13 @@ extern int strm_close(struct strm_object *stream_obj, * -EPERM: General failure. * Requires: * strm_init(void) called. - * phStrmMgr != NULL. + * strm_man != NULL. * dev_obj != NULL. * Ensures: - * 0: Valid *phStrmMgr. - * error: *phStrmMgr == NULL. + * 0: Valid *strm_man. + * error: *strm_man == NULL. */ -extern int strm_create(OUT struct strm_mgr **phStrmMgr, +extern int strm_create(OUT struct strm_mgr **strm_man, struct dev_object *dev_obj); /* @@ -254,7 +254,7 @@ extern int strm_issue(struct strm_object *stream_obj, IN u8 * pbuf, * index: Stream index. * pattr: Pointer to structure containing attributes to be * applied to stream. Cannot be NULL. - * phStrm: Location to store stream handle on output. + * strm_objct: Location to store stream handle on output. * Returns: * 0: Success. * -EFAULT: Invalid hnode. @@ -264,15 +264,15 @@ extern int strm_issue(struct strm_object *stream_obj, IN u8 * pbuf, * -EINVAL: Invalid index. * Requires: * strm_init(void) called. - * phStrm != NULL. + * strm_objct != NULL. * pattr != NULL. * Ensures: - * 0: *phStrm is valid. - * error: *phStrm == NULL. + * 0: *strm_objct is valid. + * error: *strm_objct == NULL. */ extern int strm_open(struct node_object *hnode, u32 dir, u32 index, IN struct strm_attr *pattr, - OUT struct strm_object **phStrm, + OUT struct strm_object **strm_objct, struct process_context *pr_ctxt); /* diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index ff1621c..ffe724a 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -954,7 +954,7 @@ static struct cmm_allocator *get_allocator(struct cmm_object *cmm_mgr_obj, * Purpose: * Create an address translator object. */ -int cmm_xlator_create(OUT struct cmm_xlatorobject **phXlator, +int cmm_xlator_create(OUT struct cmm_xlatorobject **xlator, struct cmm_object *hcmm_mgr, struct cmm_xlatorattrs *pXlatorAttrs) { @@ -962,10 +962,10 @@ int cmm_xlator_create(OUT struct cmm_xlatorobject **phXlator, int status = 0; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phXlator != NULL); + DBC_REQUIRE(xlator != NULL); DBC_REQUIRE(hcmm_mgr != NULL); - *phXlator = NULL; + *xlator = NULL; if (pXlatorAttrs == NULL) pXlatorAttrs = &cmm_dfltxlatorattrs; /* set defaults */ @@ -978,7 +978,7 @@ int cmm_xlator_create(OUT struct cmm_xlatorobject **phXlator, status = -ENOMEM; } if (DSP_SUCCEEDED(status)) - *phXlator = (struct cmm_xlatorobject *)xlator_object; + *xlator = (struct cmm_xlatorobject *)xlator_object; return status; } diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index e8d5b7e..ab54388 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -551,7 +551,7 @@ int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], * Open library for reading sections. */ int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, - u32 flags, struct cod_libraryobj **pLib) + u32 flags, struct cod_libraryobj **lib_obj) { int status = 0; struct cod_libraryobj *lib = NULL; @@ -560,9 +560,9 @@ int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, DBC_REQUIRE(IS_VALID(hmgr)); DBC_REQUIRE(pszCoffPath != NULL); DBC_REQUIRE(flags == COD_NOLOAD || flags == COD_SYMB); - DBC_REQUIRE(pLib != NULL); + DBC_REQUIRE(lib_obj != NULL); - *pLib = NULL; + *lib_obj = NULL; lib = kzalloc(sizeof(struct cod_libraryobj), GFP_KERNEL); if (lib == NULL) @@ -573,7 +573,7 @@ int cod_open(struct cod_manager *hmgr, IN char *pszCoffPath, status = hmgr->fxns.open_fxn(hmgr->target, pszCoffPath, flags, &lib->dbll_lib); if (DSP_SUCCEEDED(status)) - *pLib = lib; + *lib_obj = lib; } if (DSP_FAILED(status)) diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index 530191a..45133e0 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -585,7 +585,7 @@ int dbll_load_sect(struct dbll_library_obj *zl_lib, char *sectName, * ======== dbll_open ======== */ int dbll_open(struct dbll_tar_obj *target, char *file, dbll_flags flags, - struct dbll_library_obj **pLib) + struct dbll_library_obj **lib_obj) { struct dbll_tar_obj *zl_target = (struct dbll_tar_obj *)target; struct dbll_library_obj *zl_lib = NULL; @@ -596,7 +596,7 @@ int dbll_open(struct dbll_tar_obj *target, char *file, dbll_flags flags, DBC_REQUIRE(zl_target); DBC_REQUIRE(zl_target->attrs.fopen != NULL); DBC_REQUIRE(file != NULL); - DBC_REQUIRE(pLib != NULL); + DBC_REQUIRE(lib_obj != NULL); zl_lib = zl_target->head; while (zl_lib != NULL) { @@ -707,18 +707,18 @@ func_cont: zl_lib->next = zl_target->head; zl_target->head = zl_lib; } - *pLib = (struct dbll_library_obj *)zl_lib; + *lib_obj = (struct dbll_library_obj *)zl_lib; } else { - *pLib = NULL; + *lib_obj = NULL; if (zl_lib != NULL) dbll_close((struct dbll_library_obj *)zl_lib); } - DBC_ENSURE((DSP_SUCCEEDED(status) && (zl_lib->open_ref > 0) && *pLib) - || (DSP_FAILED(status) && *pLib == NULL)); + DBC_ENSURE((DSP_SUCCEEDED(status) && (zl_lib->open_ref > 0) && *lib_obj) + || (DSP_FAILED(status) && *lib_obj == NULL)); - dev_dbg(bridge, "%s: target: %p file: %s pLib: %p, status 0x%x\n", - __func__, target, file, pLib, status); + dev_dbg(bridge, "%s: target: %p file: %s lib_obj: %p, status 0x%x\n", + __func__, target, file, lib_obj, status); return status; } diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index f93d096..50fedcc 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -100,7 +100,7 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, * is passed a handle to a DEV_hObject, then calls the * device's bridge_brd_write() function. */ -u32 dev_brd_write_fxn(void *arb, u32 ulDspAddr, void *pHostBuf, +u32 dev_brd_write_fxn(void *arb, u32 ulDspAddr, void *host_buf, u32 ul_num_bytes, u32 mem_space) { struct dev_object *dev_obj = (struct dev_object *)arb; @@ -108,12 +108,12 @@ u32 dev_brd_write_fxn(void *arb, u32 ulDspAddr, void *pHostBuf, int status; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(pHostBuf != NULL); /* Required of BrdWrite(). */ + DBC_REQUIRE(host_buf != NULL); /* Required of BrdWrite(). */ if (dev_obj) { /* Require of BrdWrite() */ DBC_ASSERT(dev_obj->hbridge_context != NULL); status = (*dev_obj->bridge_interface.pfn_brd_write) ( - dev_obj->hbridge_context, pHostBuf, + dev_obj->hbridge_context, host_buf, ulDspAddr, ul_num_bytes, mem_space); /* Special case of getting the address only */ if (ul_num_bytes == 0) @@ -667,23 +667,23 @@ void dev_get_msg_mgr(struct dev_object *hdev_obj, OUT struct msg_mgr **msg_man) * Retrieve the Node Manager Handle */ int dev_get_node_manager(struct dev_object *hdev_obj, - OUT struct node_mgr **phNodeMgr) + OUT struct node_mgr **node_man) { int status = 0; struct dev_object *dev_obj = hdev_obj; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phNodeMgr != NULL); + DBC_REQUIRE(node_man != NULL); if (hdev_obj) { - *phNodeMgr = dev_obj->hnode_mgr; + *node_man = dev_obj->hnode_mgr; } else { - *phNodeMgr = NULL; + *node_man = NULL; status = -EFAULT; } - DBC_ENSURE(DSP_SUCCEEDED(status) || ((phNodeMgr != NULL) && - (*phNodeMgr == NULL))); + DBC_ENSURE(DSP_SUCCEEDED(status) || ((node_man != NULL) && + (*node_man == NULL))); return status; } diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 6129306..f385cbc 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -288,7 +288,7 @@ static int add_ovly_info(void *handle, struct dbll_sect_info *sect_info, static int add_ovly_node(struct dsp_uuid *uuid_obj, enum dsp_dcdobjtype obj_type, IN void *handle); static int add_ovly_sect(struct nldr_object *nldr_obj, - struct ovly_sect **pList, + struct ovly_sect **lst, struct dbll_sect_info *pSectInfo, bool *exists, u32 addr, u32 bytes); static s32 fake_ovly_write(void *handle, u32 dsp_address, void *buf, u32 bytes, @@ -424,7 +424,7 @@ int nldr_allocate(struct nldr_object *nldr_obj, void *priv_ref, /* * ======== nldr_create ======== */ -int nldr_create(OUT struct nldr_object **phNldr, +int nldr_create(OUT struct nldr_object **nldr, struct dev_object *hdev_obj, IN CONST struct nldr_attrs *pattrs) { @@ -444,7 +444,7 @@ int nldr_create(OUT struct nldr_object **phNldr, u16 i; int status = 0; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phNldr != NULL); + DBC_REQUIRE(nldr != NULL); DBC_REQUIRE(hdev_obj != NULL); DBC_REQUIRE(pattrs != NULL); DBC_REQUIRE(pattrs->pfn_ovly != NULL); @@ -593,16 +593,16 @@ int nldr_create(OUT struct nldr_object **phNldr, &save_attrs, &ul_entry); } if (DSP_SUCCEEDED(status)) { - *phNldr = (struct nldr_object *)nldr_obj; + *nldr = (struct nldr_object *)nldr_obj; } else { if (nldr_obj) nldr_delete((struct nldr_object *)nldr_obj); - *phNldr = NULL; + *nldr = NULL; } /* FIXME:Temp. Fix. Must be removed */ - DBC_ENSURE((DSP_SUCCEEDED(status) && *phNldr) - || (DSP_FAILED(status) && (*phNldr == NULL))); + DBC_ENSURE((DSP_SUCCEEDED(status) && *nldr) + || (DSP_FAILED(status) && (*nldr == NULL))); return status; } @@ -775,21 +775,21 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, * Given a NLDR object, retrieve RMM Manager Handle */ int nldr_get_rmm_manager(struct nldr_object *nldr, - OUT struct rmm_target_obj **phRmmMgr) + OUT struct rmm_target_obj **rmm_mgr) { int status = 0; struct nldr_object *nldr_obj = nldr; - DBC_REQUIRE(phRmmMgr != NULL); + DBC_REQUIRE(rmm_mgr != NULL); if (nldr) { - *phRmmMgr = nldr_obj->rmm; + *rmm_mgr = nldr_obj->rmm; } else { - *phRmmMgr = NULL; + *rmm_mgr = NULL; status = -EFAULT; } - DBC_ENSURE(DSP_SUCCEEDED(status) || ((phRmmMgr != NULL) && - (*phRmmMgr == NULL))); + DBC_ENSURE(DSP_SUCCEEDED(status) || ((rmm_mgr != NULL) && + (*rmm_mgr == NULL))); return status; } @@ -1071,7 +1071,7 @@ func_end: * ======== add_ovly_sect ======== */ static int add_ovly_sect(struct nldr_object *nldr_obj, - struct ovly_sect **pList, + struct ovly_sect **lst, struct dbll_sect_info *pSectInfo, bool *exists, u32 addr, u32 bytes) { @@ -1080,7 +1080,7 @@ static int add_ovly_sect(struct nldr_object *nldr_obj, struct ovly_sect *ovly_section; int status = 0; - ovly_section = last_sect = *pList; + ovly_section = last_sect = *lst; *exists = false; while (ovly_section) { /* @@ -1111,9 +1111,9 @@ static int add_ovly_sect(struct nldr_object *nldr_obj, /* Add to the list */ if (DSP_SUCCEEDED(status)) { - if (*pList == NULL) { + if (*lst == NULL) { /* First in the list */ - *pList = new_sect; + *lst = new_sect; } else { last_sect->next_sect = new_sect; } diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 7cffca4..5e586d4 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -1302,7 +1302,7 @@ func_end: * Purpose: * Create a NODE Manager object. */ -int node_create_mgr(OUT struct node_mgr **phNodeMgr, +int node_create_mgr(OUT struct node_mgr **node_man, struct dev_object *hdev_obj) { u32 i; @@ -1313,10 +1313,10 @@ int node_create_mgr(OUT struct node_mgr **phNodeMgr, int status = 0; u8 dev_type; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phNodeMgr != NULL); + DBC_REQUIRE(node_man != NULL); DBC_REQUIRE(hdev_obj != NULL); - *phNodeMgr = NULL; + *node_man = NULL; /* Allocate Node manager object */ node_mgr_obj = kzalloc(sizeof(struct node_mgr), GFP_KERNEL); if (node_mgr_obj) { @@ -1419,12 +1419,12 @@ int node_create_mgr(OUT struct node_mgr **phNodeMgr, &nldr_attrs_obj); } if (DSP_SUCCEEDED(status)) - *phNodeMgr = node_mgr_obj; + *node_man = node_mgr_obj; else delete_node_mgr(node_mgr_obj); - DBC_ENSURE((DSP_FAILED(status) && (*phNodeMgr == NULL)) || - (DSP_SUCCEEDED(status) && *phNodeMgr)); + DBC_ENSURE((DSP_FAILED(status) && (*node_man == NULL)) || + (DSP_SUCCEEDED(status) && *node_man)); return status; } @@ -1880,19 +1880,19 @@ func_end: * ======== node_get_nldr_obj ======== */ int node_get_nldr_obj(struct node_mgr *hnode_mgr, - struct nldr_object **phNldrObj) + struct nldr_object **nldr_ovlyobj) { int status = 0; struct node_mgr *node_mgr_obj = hnode_mgr; - DBC_REQUIRE(phNldrObj != NULL); + DBC_REQUIRE(nldr_ovlyobj != NULL); if (!hnode_mgr) status = -EFAULT; else - *phNldrObj = node_mgr_obj->nldr_obj; + *nldr_ovlyobj = node_mgr_obj->nldr_obj; - DBC_ENSURE(DSP_SUCCEEDED(status) || ((phNldrObj != NULL) && - (*phNldrObj == NULL))); + DBC_ENSURE(DSP_SUCCEEDED(status) || ((nldr_ovlyobj != NULL) && + (*nldr_ovlyobj == NULL))); return status; } @@ -1902,7 +1902,7 @@ int node_get_nldr_obj(struct node_mgr *hnode_mgr, * Returns the Stream manager. */ int node_get_strm_mgr(struct node_object *hnode, - struct strm_mgr **phStrmMgr) + struct strm_mgr **strm_man) { int status = 0; @@ -1911,7 +1911,7 @@ int node_get_strm_mgr(struct node_object *hnode, if (!hnode) status = -EFAULT; else - *phStrmMgr = hnode->hnode_mgr->strm_mgr_obj; + *strm_man = hnode->hnode_mgr->strm_mgr_obj; return status; } diff --git a/drivers/staging/tidspbridge/rmgr/strm.c b/drivers/staging/tidspbridge/rmgr/strm.c index 795332e..f6922f4 100644 --- a/drivers/staging/tidspbridge/rmgr/strm.c +++ b/drivers/staging/tidspbridge/rmgr/strm.c @@ -200,17 +200,17 @@ func_end: * Purpose: * Create a STRM manager object. */ -int strm_create(OUT struct strm_mgr **phStrmMgr, +int strm_create(OUT struct strm_mgr **strm_man, struct dev_object *dev_obj) { struct strm_mgr *strm_mgr_obj; int status = 0; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phStrmMgr != NULL); + DBC_REQUIRE(strm_man != NULL); DBC_REQUIRE(dev_obj != NULL); - *phStrmMgr = NULL; + *strm_man = NULL; /* Allocate STRM manager object */ strm_mgr_obj = kzalloc(sizeof(struct strm_mgr), GFP_KERNEL); if (strm_mgr_obj == NULL) @@ -229,12 +229,12 @@ int strm_create(OUT struct strm_mgr **phStrmMgr, } if (DSP_SUCCEEDED(status)) - *phStrmMgr = strm_mgr_obj; + *strm_man = strm_mgr_obj; else delete_strm_mgr(strm_mgr_obj); - DBC_ENSURE((DSP_SUCCEEDED(status) && *phStrmMgr) || - (DSP_FAILED(status) && *phStrmMgr == NULL)); + DBC_ENSURE((DSP_SUCCEEDED(status) && *strm_man) || + (DSP_FAILED(status) && *strm_man == NULL)); return status; } @@ -468,7 +468,7 @@ int strm_issue(struct strm_object *stream_obj, IN u8 *pbuf, u32 ul_bytes, */ int strm_open(struct node_object *hnode, u32 dir, u32 index, IN struct strm_attr *pattr, - OUT struct strm_object **phStrm, + OUT struct strm_object **strm_objct, struct process_context *pr_ctxt) { struct strm_mgr *strm_mgr_obj; @@ -483,9 +483,9 @@ int strm_open(struct node_object *hnode, u32 dir, u32 index, void *hstrm_res; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(phStrm != NULL); + DBC_REQUIRE(strm_objct != NULL); DBC_REQUIRE(pattr != NULL); - *phStrm = NULL; + *strm_objct = NULL; if (dir != DSP_TONODE && dir != DSP_FROMNODE) { status = -EPERM; } else { @@ -595,21 +595,22 @@ func_cont: } } if (DSP_SUCCEEDED(status)) { - *phStrm = strm_obj; - drv_proc_insert_strm_res_element(*phStrm, &hstrm_res, pr_ctxt); + *strm_objct = strm_obj; + drv_proc_insert_strm_res_element(*strm_objct, &hstrm_res, + pr_ctxt); } else { (void)delete_strm(strm_obj); } /* ensure we return a documented error code */ - DBC_ENSURE((DSP_SUCCEEDED(status) && *phStrm) || - (*phStrm == NULL && (status == -EFAULT || + DBC_ENSURE((DSP_SUCCEEDED(status) && *strm_objct) || + (*strm_objct == NULL && (status == -EFAULT || status == -EPERM || status == -EINVAL))); dev_dbg(bridge, "%s: hnode: %p dir: 0x%x index: 0x%x pattr: %p " - "phStrm: %p status: 0x%x\n", __func__, - hnode, dir, index, pattr, phStrm, status); + "strm_objct: %p status: 0x%x\n", __func__, + hnode, dir, index, pattr, strm_objct, status); return status; } From patchwork Sat Jul 10 02:24:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111193 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Sktd002447 for ; Sat, 10 Jul 2010 02:28:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754052Ab0GJCZl (ORCPT ); Fri, 9 Jul 2010 22:25:41 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:45778 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752880Ab0GJCZX (ORCPT ); Fri, 9 Jul 2010 22:25:23 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PG7M025250 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:16 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PFRe009807; Fri, 9 Jul 2010 21:25:15 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68N021595; Fri, 9 Jul 2010 21:25:14 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 11/15] staging:ti dspbridge: Rename words with camel case Date: Fri, 9 Jul 2010 21:24:05 -0500 Message-Id: <1278728649-21012-12-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-11-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> <1278728649-21012-6-git-send-email-rene.sapiens@ti.com> <1278728649-21012-7-git-send-email-rene.sapiens@ti.com> <1278728649-21012-8-git-send-email-rene.sapiens@ti.com> <1278728649-21012-9-git-send-email-rene.sapiens@ti.com> <1278728649-21012-10-git-send-email-rene.sapiens@ti.com> <1278728649-21012-11-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:28:49 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== puLen to len pulEntry to entry_pt pulFxnAddr to fxn_addr pulId to chan_id pulSegId to sgmt_id pVaBuf to va_buf pVirtualAddress to virtual_address pwMbVal to mbx_val pWord to word pXlatorAttrs to xlator_attrs registerFxn to register_fxn rootPersistent to root_prstnt sectionData to section_data sectionInfo to section_info sectionName to section_name sectName to sec_name ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/io_sm.c | 6 ++-- drivers/staging/tidspbridge/dynload/getsection.c | 24 ++++++++++---------- .../staging/tidspbridge/include/dspbridge/cmm.h | 20 ++++++++-------- .../staging/tidspbridge/include/dspbridge/cod.h | 16 ++++++------ .../staging/tidspbridge/include/dspbridge/dbdcd.h | 4 +- .../staging/tidspbridge/include/dspbridge/dbll.h | 4 +- .../tidspbridge/include/dspbridge/dblldefs.h | 10 ++++---- .../staging/tidspbridge/include/dspbridge/drv.h | 8 +++--- .../tidspbridge/include/dspbridge/getsection.h | 16 ++++++------ .../staging/tidspbridge/include/dspbridge/io_sm.h | 6 ++-- .../tidspbridge/include/dspbridge/nodepriv.h | 6 ++-- drivers/staging/tidspbridge/pmgr/cmm.c | 22 +++++++++--------- drivers/staging/tidspbridge/pmgr/cod.c | 16 ++++++------ drivers/staging/tidspbridge/pmgr/dbll.c | 6 ++-- drivers/staging/tidspbridge/rmgr/dbdcd.c | 12 +++++----- drivers/staging/tidspbridge/rmgr/drv.c | 6 ++-- drivers/staging/tidspbridge/rmgr/nldr.c | 12 +++++----- drivers/staging/tidspbridge/rmgr/node.c | 14 +++++----- 18 files changed, 104 insertions(+), 104 deletions(-) mode change 100644 => 100755 drivers/staging/tidspbridge/include/dspbridge/dbll.h diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 6a8bdd2..a8ff5f9 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -1014,12 +1014,12 @@ void io_mbox_msg(u32 msg) * interrupts the DSP. */ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, - u8 io_mode, OUT u16 *pwMbVal) + u8 io_mode, OUT u16 *mbx_val) { struct chnl_mgr *chnl_mgr_obj; struct shm *sm; - if (!pchnl || !pwMbVal) + if (!pchnl || !mbx_val) goto func_end; chnl_mgr_obj = pio_mgr->hchnl_mgr; sm = pio_mgr->shared_mem; @@ -1033,7 +1033,7 @@ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, /* Indicate to the DSP we have a buffer available for input */ IO_OR_VALUE(pio_mgr->hbridge_context, struct shm, sm, host_free_mask, (1 << pchnl->chnl_id)); - *pwMbVal = MBX_PCPY_CLASS; + *mbx_val = MBX_PCPY_CLASS; } else if (io_mode == IO_OUTPUT) { /* * This assertion fails if CHNL_AddIOReq() was called on a diff --git a/drivers/staging/tidspbridge/dynload/getsection.c b/drivers/staging/tidspbridge/dynload/getsection.c index 029898f..3086118 100644 --- a/drivers/staging/tidspbridge/dynload/getsection.c +++ b/drivers/staging/tidspbridge/dynload/getsection.c @@ -226,8 +226,8 @@ void *dload_module_open(struct dynamic_loader_stream *module, * * Parameters: * minfo Handle from dload_module_open for this module - * sectionName Pointer to the string name of the section desired - * sectionInfo Address of a section info structure pointer to be + * section_name Pointer to the string name of the section desired + * section_info Address of a section info structure pointer to be * initialized * * Effect: @@ -237,8 +237,8 @@ void *dload_module_open(struct dynamic_loader_stream *module, * Returns: * true for success, false for section not found ************************************************************************* */ -int dload_get_section_info(void *minfo, const char *sectionName, - const struct ldr_section_info **const sectionInfo) +int dload_get_section_info(void *minfo, const char *section_name, + const struct ldr_section_info **const section_info) { struct dload_state *dlthis; struct ldr_section_info *shp; @@ -250,8 +250,8 @@ int dload_get_section_info(void *minfo, const char *sectionName, for (sec = 0; sec < dlthis->dfile_hdr.df_no_scns; sec++) { shp = DOFFSEC_IS_LDRSEC(&dlthis->sect_hdrs[sec]); - if (strcmp(sectionName, shp->name) == 0) { - *sectionInfo = shp; + if (strcmp(section_name, shp->name) == 0) { + *section_info = shp; return true; } } @@ -267,9 +267,9 @@ int dload_get_section_info(void *minfo, const char *sectionName, * * Parameters: * minfo Handle from dload_module_open for this module - * sectionInfo Pointer to a section info structure for the desired + * section_info Pointer to a section info structure for the desired * section - * sectionData Buffer to contain the section initialized data + * section_data Buffer to contain the section initialized data * * Effect: * Copies the initialized data for the specified section into the @@ -279,8 +279,8 @@ int dload_get_section_info(void *minfo, const char *sectionName, * true for success, false for section not found ************************************************************************* */ int dload_get_section(void *minfo, - const struct ldr_section_info *sectionInfo, - void *sectionData) + const struct ldr_section_info *section_info, + void *section_data) { struct dload_state *dlthis; u32 pos; @@ -289,12 +289,12 @@ int dload_get_section(void *minfo, struct image_packet_t ipacket; s32 ipsize; u32 checks; - s8 *dest = (s8 *) sectionData; + s8 *dest = (s8 *) section_data; dlthis = (struct dload_state *)minfo; if (!dlthis) return false; - sptr = LDRSEC_IS_DOFFSEC(sectionInfo); + sptr = LDRSEC_IS_DOFFSEC(section_info); if (sptr == NULL) return false; diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index 9d773aa..78cc12a 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -209,17 +209,17 @@ extern bool cmm_init(void); * c_factor: Add offset if CMM_ADDTODSPPA, sub if CMM_SUBFROMDSPPA. * dw_dsp_base: DSP virtual base byte address. * ul_dsp_size: Size of DSP segment in bytes. - * pulSegId: Address to store segment Id. + * sgmt_id: Address to store segment Id. * * Returns: * 0: Success. * -EFAULT: Invalid hcmm_mgr handle. * -EINVAL: Invalid input argument. * -EPERM: Unable to register. - * - On success *pulSegId is a valid SM segment ID. + * - On success *sgmt_id is a valid SM segment ID. * Requires: * ul_size > 0 - * pulSegId != NULL + * sgmt_id != NULL * dw_gpp_base_pa != 0 * c_factor = CMM_ADDTODSPPA || c_factor = CMM_SUBFROMDSPPA * Ensures: @@ -232,7 +232,7 @@ extern int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, s8 c_factor, unsigned int dw_dsp_base, u32 ul_dsp_size, - u32 *pulSegId, u32 gpp_base_ba); + u32 *sgmt_id, u32 gpp_base_ba); /* * ======== cmm_un_register_gppsm_seg ======== @@ -261,18 +261,18 @@ extern int cmm_un_register_gppsm_seg(struct cmm_object *hcmm_mgr, * Place on the descriptor on the translator's HaQ (Host Alloc'd Queue). * Parameters: * xlator: Handle to a Xlator object. - * pVaBuf: Virtual address ptr(client context) + * va_buf: Virtual address ptr(client context) * uPaSize: Size of SM memory to allocate. * Returns: * Ptr to valid physical address(Pa) of uPaSize bytes, NULL if failed. * Requires: - * pVaBuf != 0. + * va_buf != 0. * uPaSize != 0. * Ensures: * */ extern void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, - void *pVaBuf, u32 uPaSize); + void *va_buf, u32 uPaSize); /* * ======== cmm_xlator_create ======== @@ -283,7 +283,7 @@ extern void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, * Parameters: * xlator: Address to place handle to a new Xlator handle. * hcmm_mgr: Handle to Cmm Mgr associated with this translator. - * pXlatorAttrs: Translator attributes used for the client NODE or STREAM. + * xlator_attrs: Translator attributes used for the client NODE or STREAM. * Returns: * 0: Success. * -EINVAL: Bad input Attrs. @@ -291,13 +291,13 @@ extern void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, * Requires: * xlator != NULL * hcmm_mgr != NULL - * pXlatorAttrs != NULL + * xlator_attrs != NULL * Ensures: * */ extern int cmm_xlator_create(OUT struct cmm_xlatorobject **xlator, struct cmm_object *hcmm_mgr, - struct cmm_xlatorattrs *pXlatorAttrs); + struct cmm_xlatorattrs *xlator_attrs); /* * ======== cmm_xlator_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index c84761e..2d5f41a 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -169,17 +169,17 @@ extern int cod_get_base_name(struct cod_manager *cod_mgr_obj, * Retrieve the entry point of a loaded DSP program image * Parameters: * cod_mgr_obj: handle of manager to be deleted - * pulEntry: pointer to location for entry point + * entry_pt: pointer to location for entry point * Returns: * 0: Success. * Requires: * COD module initialized. * valid cod_mgr_obj. - * pulEntry != NULL. + * entry_pt != NULL. * Ensures: */ extern int cod_get_entry(struct cod_manager *cod_mgr_obj, - u32 *pulEntry); + u32 *entry_pt); /* * ======== cod_get_loader ======== @@ -208,7 +208,7 @@ extern int cod_get_loader(struct cod_manager *cod_mgr_obj, * lib Library handle returned from cod_open(). * str_sect: name of the section, with or without leading "." * addr: Location to store address. - * puLen: Location to store length. + * len: Location to store length. * Returns: * 0: Success * -ESPIPE: Symbols could not be found or have not been loaded onto @@ -218,16 +218,16 @@ extern int cod_get_loader(struct cod_manager *cod_mgr_obj, * valid cod_mgr_obj. * str_sect != NULL; * addr != NULL; - * puLen != NULL; + * len != NULL; * Ensures: - * 0: *addr and *puLen contain the address and length of the + * 0: *addr and *len contain the address and length of the * section. - * else: *addr == 0 and *puLen == 0; + * else: *addr == 0 and *len == 0; * */ extern int cod_get_section(struct cod_libraryobj *lib, IN char *str_sect, - OUT u32 *addr, OUT u32 *puLen); + OUT u32 *addr, OUT u32 *len); /* * ======== cod_get_sym_value ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h index c798e72..5e3b7f7 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h @@ -278,7 +278,7 @@ extern int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, * hdcd_mgr: A DCD manager handle. * sz_coff_path: Pointer to name of COFF file containing DCD * objects. - * registerFxn: Callback fxn to be applied on each located + * register_fxn: Callback fxn to be applied on each located * DCD object. * handle: Handle to pass to callback. * Returns: @@ -296,7 +296,7 @@ extern int dcd_get_object_def(IN struct dcd_manager *hdcd_mgr, */ extern int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, IN char *sz_coff_path, - dcd_registerfxn registerFxn, void *handle); + dcd_registerfxn register_fxn, void *handle); /* * ======== dcd_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbll.h b/drivers/staging/tidspbridge/include/dspbridge/dbll.h index a4dea0c..a197115 --- a/drivers/staging/tidspbridge/include/dspbridge/dbll.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbll.h @@ -43,7 +43,7 @@ extern int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, struct dbll_attrs *attrs, u32 * entry); extern int dbll_load_sect(struct dbll_library_obj *lib, - char *sectName, struct dbll_attrs *attrs); + char *sec_name, struct dbll_attrs *attrs); extern int dbll_open(struct dbll_tar_obj *target, char *file, dbll_flags flags, struct dbll_library_obj **lib_obj); @@ -53,7 +53,7 @@ extern void dbll_set_attrs(struct dbll_tar_obj *target, struct dbll_attrs *pattrs); extern void dbll_unload(struct dbll_library_obj *lib, struct dbll_attrs *attrs); extern int dbll_unload_sect(struct dbll_library_obj *lib, - char *sectName, struct dbll_attrs *attrs); + char *sect_name, struct dbll_attrs *attrs); #ifdef CONFIG_TIDSPBRIDGE_BACKTRACE bool dbll_find_dsp_symbol(struct dbll_library_obj *zl_lib, u32 address, u32 offset_range, u32 *sym_addr_output, char *name_output); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h index 8446e0e..fa4c99f 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h @@ -334,7 +334,7 @@ typedef bool(*dbll_init_fxn) (void); * lib - Library handle returned from dbll_open(). * flags - Load code, data and/or symbols. * attrs - May contain alloc, free, and write function. - * pulEntry - Location to store program entry on output. + * entry_pt - Location to store program entry on output. * Returns: * 0: Success. * -EBADF: File read failed. @@ -354,7 +354,7 @@ typedef int(*dbll_load_fxn) (struct dbll_library_obj *lib, * Load a named section from an library (for overlay support). * Parameters: * lib - Handle returned from dbll_open(). - * sectName - Name of section to load. + * sec_name - Name of section to load. * attrs - Contains write function and handle to pass to it. * Returns: * 0: Success. @@ -362,7 +362,7 @@ typedef int(*dbll_load_fxn) (struct dbll_library_obj *lib, * -ENOSYS: Function not implemented. * Requires: * Valid lib. - * sectName != NULL. + * sec_name != NULL. * attrs != NULL. * attrs->write != NULL. * Ensures: @@ -458,7 +458,7 @@ typedef void (*dbll_unload_fxn) (struct dbll_library_obj *library, * Unload a named section from an library (for overlay support). * Parameters: * lib - Handle returned from dbll_open(). - * sectName - Name of section to load. + * sec_name - Name of section to load. * attrs - Contains free() function and handle to pass to it. * Returns: * 0: Success. @@ -467,7 +467,7 @@ typedef void (*dbll_unload_fxn) (struct dbll_library_obj *library, * Requires: * DBL initialized. * Valid lib. - * sectName != NULL. + * sec_name != NULL. * Ensures: */ typedef int(*dbll_unload_sect_fxn) (struct dbll_library_obj *lib, diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index b43d22f..efdc29c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -470,7 +470,7 @@ extern void *mem_alloc_phys_mem(IN u32 byte_size, * Purpose: * Free the given block of physically contiguous memory. * Parameters: - * pVirtualAddress: Pointer to virtual memory region allocated + * virtual_address: Pointer to virtual memory region allocated * by mem_alloc_phys_mem(). * physical_address: Pointer to physical memory region allocated * by mem_alloc_phys_mem(). @@ -478,12 +478,12 @@ extern void *mem_alloc_phys_mem(IN u32 byte_size, * Returns: * Requires: * MEM initialized. - * pVirtualAddress is a valid memory address returned by + * virtual_address is a valid memory address returned by * mem_alloc_phys_mem() * Ensures: - * pVirtualAddress is no longer a valid pointer to memory. + * virtual_address is no longer a valid pointer to memory. */ -extern void mem_free_phys_mem(void *pVirtualAddress, +extern void mem_free_phys_mem(void *virtual_address, u32 physical_address, u32 byte_size); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/getsection.h b/drivers/staging/tidspbridge/include/dspbridge/getsection.h index bdd8e20..626063d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/getsection.h +++ b/drivers/staging/tidspbridge/include/dspbridge/getsection.h @@ -54,8 +54,8 @@ extern void *dload_module_open(struct dynamic_loader_stream * * Parameters: * minfo Handle from dload_module_open for this module - * sectionName Pointer to the string name of the section desired - * sectionInfo Address of a section info structure pointer to be initialized + * section_name Pointer to the string name of the section desired + * section_info Address of a section info structure pointer to be initialized * * Effect: * Finds the specified section in the module information, and fills in @@ -65,17 +65,17 @@ extern void *dload_module_open(struct dynamic_loader_stream * TRUE for success, FALSE for section not found */ extern int dload_get_section_info(void *minfo, - const char *sectionName, + const char *section_name, const struct ldr_section_info - **const sectionInfo); + **const section_info); /* * Procedure dload_get_section * * Parameters: * minfo Handle from dload_module_open for this module - * sectionInfo Pointer to a section info structure for the desired section - * sectionData Buffer to contain the section initialized data + * section_info Pointer to a section info structure for the desired section + * section_data Buffer to contain the section initialized data * * Effect: * Copies the initialized data for the specified section into the @@ -85,8 +85,8 @@ extern int dload_get_section_info(void *minfo, * TRUE for success, FALSE for section not found */ extern int dload_get_section(void *minfo, - const struct ldr_section_info *sectionInfo, - void *sectionData); + const struct ldr_section_info *section_info, + void *section_data); /* * Procedure dload_module_close diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index 1627e0a..a7fded7 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -116,7 +116,7 @@ void io_mbox_msg(u32 msg); */ extern void io_request_chnl(struct io_mgr *hio_mgr, struct chnl_object *pchnl, - u8 io_mode, OUT u16 *pwMbVal); + u8 io_mode, OUT u16 *mbx_val); /* * ======== iosm_schedule ======== @@ -190,7 +190,7 @@ extern void io_ddma_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId); extern void io_ddma_request_chnl(struct io_mgr *hio_mgr, struct chnl_object *pchnl, struct chnl_irp *chnl_packet_obj, - OUT u16 *pwMbVal); + OUT u16 *mbx_val); /* * Zero-copy IO functions @@ -245,7 +245,7 @@ extern void io_ddzc_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uChnlId); extern void io_ddzc_request_chnl(struct io_mgr *hio_mgr, struct chnl_object *pchnl, struct chnl_irp *chnl_packet_obj, - OUT u16 *pwMbVal); + OUT u16 *mbx_val); /* * ======== io_sh_msetting ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h index 0b45094..7c2e7a9 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h @@ -88,7 +88,7 @@ struct node_createargs { * hnode: Node object allocated from node_allocate(). * dir: Input (DSP_TONODE) or output (DSP_FROMNODE). * index: Stream index. - * pulId: Location to store channel index. + * chan_id: Location to store channel index. * Returns: * 0: Success. * -EFAULT: Invalid hnode. @@ -98,11 +98,11 @@ struct node_createargs { * Requires: * node_init(void) called. * Valid dir. - * pulId != NULL. + * chan_id != NULL. * Ensures: */ extern int node_get_channel_id(struct node_object *hnode, - u32 dir, u32 index, OUT u32 *pulId); + u32 dir, u32 index, OUT u32 *chan_id); /* * ======== node_get_strm_mgr ======== diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index 8fd9c26..0a36085 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -540,7 +540,7 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, u32 dw_gpp_base_pa, u32 ul_size, u32 dsp_addr_offset, s8 c_factor, u32 dw_dsp_base, u32 ul_dsp_size, - u32 *pulSegId, u32 dw_gpp_base_va) + u32 *sgmt_id, u32 dw_gpp_base_va) { struct cmm_object *cmm_mgr_obj = (struct cmm_object *)hcmm_mgr; struct cmm_allocator *psma = NULL; @@ -549,7 +549,7 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, s32 slot_seg; DBC_REQUIRE(ul_size > 0); - DBC_REQUIRE(pulSegId != NULL); + DBC_REQUIRE(sgmt_id != NULL); DBC_REQUIRE(dw_gpp_base_pa != 0); DBC_REQUIRE(dw_gpp_base_va != 0); DBC_REQUIRE((c_factor <= CMM_ADDTODSPPA) && @@ -596,7 +596,7 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr, } if (DSP_SUCCEEDED(status)) { /* return the actual segment identifier */ - *pulSegId = (u32) slot_seg + 1; + *sgmt_id = (u32) slot_seg + 1; /* create memory free list */ psma->free_list_head = kzalloc(sizeof(struct lst_list), GFP_KERNEL); @@ -956,7 +956,7 @@ static struct cmm_allocator *get_allocator(struct cmm_object *cmm_mgr_obj, */ int cmm_xlator_create(OUT struct cmm_xlatorobject **xlator, struct cmm_object *hcmm_mgr, - struct cmm_xlatorattrs *pXlatorAttrs) + struct cmm_xlatorattrs *xlator_attrs) { struct cmm_xlator *xlator_object = NULL; int status = 0; @@ -966,14 +966,14 @@ int cmm_xlator_create(OUT struct cmm_xlatorobject **xlator, DBC_REQUIRE(hcmm_mgr != NULL); *xlator = NULL; - if (pXlatorAttrs == NULL) - pXlatorAttrs = &cmm_dfltxlatorattrs; /* set defaults */ + if (xlator_attrs == NULL) + xlator_attrs = &cmm_dfltxlatorattrs; /* set defaults */ xlator_object = kzalloc(sizeof(struct cmm_xlator), GFP_KERNEL); if (xlator_object != NULL) { xlator_object->hcmm_mgr = hcmm_mgr; /* ref back to CMM */ /* SM seg_id */ - xlator_object->ul_seg_id = pXlatorAttrs->ul_seg_id; + xlator_object->ul_seg_id = xlator_attrs->ul_seg_id; } else { status = -ENOMEM; } @@ -1007,7 +1007,7 @@ int cmm_xlator_delete(struct cmm_xlatorobject *xlator, bool force) /* * ======== cmm_xlator_alloc_buf ======== */ -void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, void *pVaBuf, +void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, void *va_buf, u32 uPaSize) { struct cmm_xlator *xlator_obj = (struct cmm_xlator *)xlator; @@ -1017,20 +1017,20 @@ void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, void *pVaBuf, DBC_REQUIRE(refs > 0); DBC_REQUIRE(xlator != NULL); DBC_REQUIRE(xlator_obj->hcmm_mgr != NULL); - DBC_REQUIRE(pVaBuf != NULL); + DBC_REQUIRE(va_buf != NULL); DBC_REQUIRE(uPaSize > 0); DBC_REQUIRE(xlator_obj->ul_seg_id > 0); if (xlator_obj) { attrs.ul_seg_id = xlator_obj->ul_seg_id; - *(volatile u32 *)pVaBuf = 0; + *(volatile u32 *)va_buf = 0; /* Alloc SM */ pbuf = cmm_calloc_buf(xlator_obj->hcmm_mgr, uPaSize, &attrs, NULL); if (pbuf) { /* convert to translator(node/strm) process Virtual * address */ - *(volatile u32 **)pVaBuf = + *(volatile u32 **)va_buf = (u32 *) cmm_xlator_translate(xlator, pbuf, CMM_PA2VA); } diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index ae44bed..d9501eb 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -360,13 +360,13 @@ int cod_get_base_name(struct cod_manager *cod_mgr_obj, char *sz_name, * Retrieve the entry point of a loaded DSP program image * */ -int cod_get_entry(struct cod_manager *cod_mgr_obj, u32 *pulEntry) +int cod_get_entry(struct cod_manager *cod_mgr_obj, u32 *entry_pt) { DBC_REQUIRE(refs > 0); DBC_REQUIRE(IS_VALID(cod_mgr_obj)); - DBC_REQUIRE(pulEntry != NULL); + DBC_REQUIRE(entry_pt != NULL); - *pulEntry = cod_mgr_obj->ul_entry; + *entry_pt = cod_mgr_obj->ul_entry; return 0; } @@ -397,7 +397,7 @@ int cod_get_loader(struct cod_manager *cod_mgr_obj, * given the section name. */ int cod_get_section(struct cod_libraryobj *lib, IN char *str_sect, - OUT u32 *addr, OUT u32 *puLen) + OUT u32 *addr, OUT u32 *len) { struct cod_manager *cod_mgr_obj; int status = 0; @@ -407,19 +407,19 @@ int cod_get_section(struct cod_libraryobj *lib, IN char *str_sect, DBC_REQUIRE(IS_VALID(lib->cod_mgr)); DBC_REQUIRE(str_sect != NULL); DBC_REQUIRE(addr != NULL); - DBC_REQUIRE(puLen != NULL); + DBC_REQUIRE(len != NULL); *addr = 0; - *puLen = 0; + *len = 0; if (lib != NULL) { cod_mgr_obj = lib->cod_mgr; status = cod_mgr_obj->fxns.get_sect_fxn(lib->dbll_lib, str_sect, - addr, puLen); + addr, len); } else { status = -ESPIPE; } - DBC_ENSURE(DSP_SUCCEEDED(status) || ((*addr == 0) && (*puLen == 0))); + DBC_ENSURE(DSP_SUCCEEDED(status) || ((*addr == 0) && (*len == 0))); return status; } diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index e94ef6b..cb4d2a7 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -573,7 +573,7 @@ int dbll_load(struct dbll_library_obj *lib, dbll_flags flags, * ======== dbll_load_sect ======== * Not supported for COFF. */ -int dbll_load_sect(struct dbll_library_obj *zl_lib, char *sectName, +int dbll_load_sect(struct dbll_library_obj *zl_lib, char *sec_name, struct dbll_attrs *attrs) { DBC_REQUIRE(zl_lib); @@ -853,11 +853,11 @@ func_end: * ======== dbll_unload_sect ======== * Not supported for COFF. */ -int dbll_unload_sect(struct dbll_library_obj *lib, char *sectName, +int dbll_unload_sect(struct dbll_library_obj *lib, char *sec_name, struct dbll_attrs *attrs) { DBC_REQUIRE(refs > 0); - DBC_REQUIRE(sectName != NULL); + DBC_REQUIRE(sec_name != NULL); return -ENOSYS; } diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index a5cef43..992ff73 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -66,7 +66,7 @@ static int get_attrs_from_buf(char *psz_buf, u32 ul_buf_size, enum dsp_dcdobjtype obj_type, struct dcd_genericobj *gen_obj); static void compress_buf(char *psz_buf, u32 ul_buf_size, s32 char_size); -static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size); +static char dsp_char2_gpp_char(char *word, s32 dsp_char_size); static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, IN OUT u16 *num_libs, @@ -534,7 +534,7 @@ func_end: * ======== dcd_get_objects ======== */ int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, - IN char *sz_coff_path, dcd_registerfxn registerFxn, + IN char *sz_coff_path, dcd_registerfxn register_fxn, void *handle) { struct dcd_manager *dcd_mgr_obj = hdcd_mgr; @@ -608,7 +608,7 @@ int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, object_type = atoi(token); /* - * Apply registerFxn to the found DCD object. + * Apply register_fxn to the found DCD object. * Possible actions include: * * 1) Register found DCD object. @@ -616,7 +616,7 @@ int dcd_get_objects(IN struct dcd_manager *hdcd_mgr, * 3) Add overlay node. */ status = - registerFxn(&dsp_uuid_obj, object_type, handle); + register_fxn(&dsp_uuid_obj, object_type, handle); if (DSP_FAILED(status)) { /* if error occurs, break from while loop. */ break; @@ -1376,13 +1376,13 @@ static void compress_buf(char *psz_buf, u32 ul_buf_size, s32 char_size) * Purpose: * Convert DSP char to host GPP char in a portable manner */ -static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size) +static char dsp_char2_gpp_char(char *word, s32 dsp_char_size) { char ch = '\0'; char *ch_src; s32 i; - for (ch_src = pWord, i = dsp_char_size; i > 0; i--) + for (ch_src = word, i = dsp_char_size; i > 0; i--) ch |= *ch_src++; return ch; diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index f38123d..dc0c629 100755 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -1037,12 +1037,12 @@ void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, OUT u32 * physical_address) * Purpose: * Free the given block of physically contiguous memory. */ -void mem_free_phys_mem(void *pVirtualAddress, u32 physical_address, +void mem_free_phys_mem(void *virtual_address, u32 physical_address, u32 byte_size) { - DBC_REQUIRE(pVirtualAddress != NULL); + DBC_REQUIRE(virtual_address != NULL); if (!ext_phys_mem_pool_enabled) - dma_free_coherent(NULL, byte_size, pVirtualAddress, + dma_free_coherent(NULL, byte_size, virtual_address, physical_address); } diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 3eb1ae3..198b698 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -299,7 +299,7 @@ static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, char *symName, struct dbll_sym_val **sym); static int load_lib(struct nldr_nodeobject *nldr_node_obj, struct lib_node *root, struct dsp_uuid uuid, - bool rootPersistent, + bool root_prstnt, struct dbll_library_obj **lib_path, enum nldr_phase phase, u16 depth); static int load_ovly(struct nldr_nodeobject *nldr_node_obj, @@ -1243,7 +1243,7 @@ static bool get_symbol_value(void *handle, void *parg, void *rmm_handle, */ static int load_lib(struct nldr_nodeobject *nldr_node_obj, struct lib_node *root, struct dsp_uuid uuid, - bool rootPersistent, + bool root_prstnt, struct dbll_library_obj **lib_path, enum nldr_phase phase, u16 depth) { @@ -1300,7 +1300,7 @@ static int load_lib(struct nldr_nodeobject *nldr_node_obj, kfree(psz_file_name); /* Check to see if library not already loaded */ - if (DSP_SUCCEEDED(status) && rootPersistent) { + if (DSP_SUCCEEDED(status) && root_prstnt) { lib_status = find_in_persistent_lib_array(nldr_node_obj, root->lib); /* Close library */ @@ -1374,7 +1374,7 @@ static int load_lib(struct nldr_nodeobject *nldr_node_obj, /* If root library is NOT persistent, and dep library * is, then record it. If root library IS persistent, * the deplib is already included */ - if (!rootPersistent && persistent_dep_libs[i] && + if (!root_prstnt && persistent_dep_libs[i] && *nldr_node_obj->pf_phase_split) { if ((nldr_node_obj->pers_libs) >= MAXLIBS) { status = -EILSEQ; @@ -1386,7 +1386,7 @@ static int load_lib(struct nldr_nodeobject *nldr_node_obj, &nldr_node_obj->pers_lib_table [nldr_node_obj->pers_libs]; } else { - if (rootPersistent) + if (root_prstnt) persistent_dep_libs[i] = true; /* Allocate library within phase */ @@ -1400,7 +1400,7 @@ static int load_lib(struct nldr_nodeobject *nldr_node_obj, if (DSP_SUCCEEDED(status)) { if ((status != 0) && - !rootPersistent && persistent_dep_libs[i] && + !root_prstnt && persistent_dep_libs[i] && *nldr_node_obj->pf_phase_split) { (nldr_node_obj->pers_libs)++; } else { diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 91a5d8c..cdae2c8 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -248,7 +248,7 @@ static void fill_stream_def(struct node_object *hnode, struct node_strmdef *pstrm_def, struct dsp_strmattr *pattrs); static void free_stream(struct node_mgr *hnode_mgr, struct stream_chnl stream); -static int get_fxn_address(struct node_object *hnode, u32 * pulFxnAddr, +static int get_fxn_address(struct node_object *hnode, u32 * fxn_addr, u32 uPhase); static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, @@ -1762,13 +1762,13 @@ int node_get_attr(struct node_object *hnode, * host and a node. */ int node_get_channel_id(struct node_object *hnode, u32 dir, u32 index, - OUT u32 *pulId) + OUT u32 *chan_id) { enum node_type node_type; int status = -EINVAL; DBC_REQUIRE(refs > 0); DBC_REQUIRE(dir == DSP_TONODE || dir == DSP_FROMNODE); - DBC_REQUIRE(pulId != NULL); + DBC_REQUIRE(chan_id != NULL); if (!hnode) { status = -EFAULT; @@ -1782,7 +1782,7 @@ int node_get_channel_id(struct node_object *hnode, u32 dir, u32 index, if (dir == DSP_TONODE) { if (index < MAX_INPUTS(hnode)) { if (hnode->inputs[index].type == HOSTCONNECT) { - *pulId = hnode->inputs[index].dev_id; + *chan_id = hnode->inputs[index].dev_id; status = 0; } } @@ -1790,7 +1790,7 @@ int node_get_channel_id(struct node_object *hnode, u32 dir, u32 index, DBC_ASSERT(dir == DSP_FROMNODE); if (index < MAX_OUTPUTS(hnode)) { if (hnode->outputs[index].type == HOSTCONNECT) { - *pulId = hnode->outputs[index].dev_id; + *chan_id = hnode->outputs[index].dev_id; status = 0; } } @@ -2819,7 +2819,7 @@ static void free_stream(struct node_mgr *hnode_mgr, struct stream_chnl stream) * Purpose: * Retrieves the address for create, execute or delete phase for a node. */ -static int get_fxn_address(struct node_object *hnode, u32 * pulFxnAddr, +static int get_fxn_address(struct node_object *hnode, u32 * fxn_addr, u32 uPhase) { char *pstr_fxn_name = NULL; @@ -2850,7 +2850,7 @@ static int get_fxn_address(struct node_object *hnode, u32 * pulFxnAddr, status = hnode_mgr->nldr_fxns.pfn_get_fxn_addr(hnode->nldr_node_obj, - pstr_fxn_name, pulFxnAddr); + pstr_fxn_name, fxn_addr); return status; } From patchwork Tue Jul 6 15:08:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 110430 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o66F9OcZ003582 for ; Tue, 6 Jul 2010 15:09:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753653Ab0GFPI6 (ORCPT ); Tue, 6 Jul 2010 11:08:58 -0400 Received: from mail-fx0-f46.google.com ([209.85.161.46]:44506 "EHLO mail-fx0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751814Ab0GFPI5 (ORCPT ); Tue, 6 Jul 2010 11:08:57 -0400 Received: by fxm14 with SMTP id 14so4907720fxm.19 for ; Tue, 06 Jul 2010 08:08:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=ohBi6dhNWUzum6UNN+8HkilGjAkUuRTh6hoqb1b9KdY=; b=r/4bMleT4glB7tVa7LhwRF+QqsaYNJI845oeaUVf/6fvMmUImlc2YyLZ9CYn8yDj6L 0qmjpIbpZyzKPNWxeIJgkkhdhfefU1luybMnHR20/3Ub+IzFe91HDnn9qwcXy0r8J9iX hSJbgotnL0lO/SGvfItoHvi3CgLVlwm7lRsEU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=AvZbgieHcixBv+NMYUSk4F0qFeYOUlLjo+pvlF22jgAN+KI3pmyk8K2p3NhcZAY2wL uo0nb6fClkaD4BV7pNudpIVarFacUl8DJXYPnJJekJod1rw6KqWv+m+tcbsnUqS+win5 iAfFUQ59NCfuIIqLJQLdl7geFZ/jlOkTxLbT0= Received: by 10.86.52.20 with SMTP id z20mr1220004fgz.34.1278428935794; Tue, 06 Jul 2010 08:08:55 -0700 (PDT) Received: from localhost.localdomain (79-134-110-189.cust.suomicom.fi [79.134.110.189]) by mx.google.com with ESMTPS id h4sm12089361fai.6.2010.07.06.08.08.54 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 06 Jul 2010 08:08:55 -0700 (PDT) From: Andy Shevchenko To: linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Ohad Ben-Cohen , Greg Kroah-Hartman , linux-omap@vger.kernel.org Subject: [PATCH] staging: tidspbridge: gen: simplify and clean up Date: Tue, 6 Jul 2010 18:08:52 +0300 Message-Id: <1278428932-9145-1-git-send-email-andy.shevchenko@gmail.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: References: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 06 Jul 2010 15:09:27 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/gen/uuidutil.c b/drivers/staging/tidspbridge/gen/uuidutil.c index ce9319d..eb09bc3 100644 --- a/drivers/staging/tidspbridge/gen/uuidutil.c +++ b/drivers/staging/tidspbridge/gen/uuidutil.c @@ -54,61 +54,19 @@ void uuid_uuid_to_string(IN struct dsp_uuid *uuid_obj, OUT char *pszUuid, DBC_ENSURE(i != -1); } -/* - * ======== htoi ======== - * Purpose: - * Converts a hex value to a decimal integer. - */ - -static int htoi(char c) +static s32 uuid_hex_to_bin(char *buf, s32 len) { - switch (c) { - case '0': - return 0; - case '1': - return 1; - case '2': - return 2; - case '3': - return 3; - case '4': - return 4; - case '5': - return 5; - case '6': - return 6; - case '7': - return 7; - case '8': - return 8; - case '9': - return 9; - case 'A': - return 10; - case 'B': - return 11; - case 'C': - return 12; - case 'D': - return 13; - case 'E': - return 14; - case 'F': - return 15; - case 'a': - return 10; - case 'b': - return 11; - case 'c': - return 12; - case 'd': - return 13; - case 'e': - return 14; - case 'f': - return 15; + s32 i; + s32 result = 0; + + for (i = 0; i < len; i++) { + value = hex_to_bin(*buf++); + result *= 16; + if (value > 0) + result += value; } - return 0; + + return result; } /* @@ -118,106 +76,37 @@ static int htoi(char c) */ void uuid_uuid_from_string(IN char *pszUuid, OUT struct dsp_uuid *uuid_obj) { - char c; - s32 i, j; - s32 result; - char *temp = pszUuid; + s32 j; - result = 0; - for (i = 0; i < 8; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->ul_data1 = result; + uuid_obj->ul_data1 = uuid_hex_to_bin(pszUuid, 8); + pszUuid += 8; /* Step over underscore */ - temp++; + pszUuid++; - result = 0; - for (i = 0; i < 4; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->us_data2 = (u16) result; + uuid_obj->us_data2 = (u16) uuid_hex_to_bin(pszUuid, 4); + pszUuid += 4; /* Step over underscore */ - temp++; - - result = 0; - for (i = 0; i < 4; i++) { - /* Get first character in string */ - c = *temp; + pszUuid++; - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->us_data3 = (u16) result; + uuid_obj->us_data3 = (u16) uuid_hex_to_bin(pszUuid, 4); + pszUuid += 4; /* Step over underscore */ - temp++; - - result = 0; - for (i = 0; i < 2; i++) { - /* Get first character in string */ - c = *temp; + pszUuid++; - /* Increase the results by new value */ - result *= 16; - result += htoi(c); + uuid_obj->uc_data4 = (u8) uuid_hex_to_bin(pszUuid, 2); + pszUuid += 2; - /* Go to next character in string */ - temp++; - } - uuid_obj->uc_data4 = (u8) result; - - result = 0; - for (i = 0; i < 2; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->uc_data5 = (u8) result; + uuid_obj->uc_data5 = (u8) uuid_hex_to_bin(pszUuid, 2); + pszUuid += 2; /* Step over underscore */ - temp++; + pszUuid++; for (j = 0; j < 6; j++) { - result = 0; - for (i = 0; i < 2; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->uc_data6[j] = (u8) result; + uuid_obj->uc_data6[j] = (u8) uuid_hex_to_bin(pszUuid, 2); + pszUuid += 2; } } From patchwork Wed May 5 18:45:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jan sebastien X-Patchwork-Id: 97168 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45IjMUJ024708 for ; Wed, 5 May 2010 18:45:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758044Ab0EESpT (ORCPT ); Wed, 5 May 2010 14:45:19 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:33657 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758006Ab0EESpN (ORCPT ); Wed, 5 May 2010 14:45:13 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o45Ij0At023844 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 5 May 2010 13:45:00 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o45IipCO028118; Wed, 5 May 2010 13:44:57 -0500 (CDT) From: Sebastien Jan To: netdev@vger.kernel.org Cc: linux-omap@vger.kernel.org, Abraham Arce , Ben Dooks , Tristram.Ha@micrel.com, Sebastien Jan Subject: [PATCH 3/4 v2] ks8851: companion eeprom access through ethtool Date: Wed, 5 May 2010 20:45:54 +0200 Message-Id: <1273085155-1260-4-git-send-email-s-jan@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1273085155-1260-1-git-send-email-s-jan@ti.com> References: <1273085155-1260-1-git-send-email-s-jan@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 18:45:23 +0000 (UTC) diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c index 787f9df..8e38c36 100644 --- a/drivers/net/ks8851.c +++ b/drivers/net/ks8851.c @@ -1318,6 +1318,117 @@ static int ks8851_nway_reset(struct net_device *dev) return mii_nway_restart(&ks->mii); } +static int ks8851_get_eeprom_len(struct net_device *dev) +{ + struct ks8851_net *ks = netdev_priv(dev); + return ks->eeprom_size; +} + +static int ks8851_get_eeprom(struct net_device *dev, + struct ethtool_eeprom *eeprom, u8 *bytes) +{ + struct ks8851_net *ks = netdev_priv(dev); + u16 *eeprom_buff; + int first_word; + int last_word; + int ret_val = 0; + u16 i; + + if (eeprom->len == 0) + return -EINVAL; + + if (eeprom->len > ks->eeprom_size) + return -EINVAL; + + eeprom->magic = ks8851_rdreg16(ks, KS_CIDER); + + first_word = eeprom->offset >> 1; + last_word = (eeprom->offset + eeprom->len - 1) >> 1; + + eeprom_buff = kmalloc(sizeof(u16) * + (last_word - first_word + 1), GFP_KERNEL); + if (!eeprom_buff) + return -ENOMEM; + + for (i = 0; i < last_word - first_word + 1; i++) + eeprom_buff[i] = ks8851_eeprom_read(dev, first_word + 1); + + /* Device's eeprom is little-endian, word addressable */ + for (i = 0; i < last_word - first_word + 1; i++) + le16_to_cpus(&eeprom_buff[i]); + + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); + kfree(eeprom_buff); + + return ret_val; +} + +static int ks8851_set_eeprom(struct net_device *dev, + struct ethtool_eeprom *eeprom, u8 *bytes) +{ + struct ks8851_net *ks = netdev_priv(dev); + u16 *eeprom_buff; + void *ptr; + int max_len; + int first_word; + int last_word; + int ret_val = 0; + u16 i; + + if (eeprom->len == 0) + return -EOPNOTSUPP; + + if (eeprom->len > ks->eeprom_size) + return -EINVAL; + + if (eeprom->magic != ks8851_rdreg16(ks, KS_CIDER)) + return -EFAULT; + + first_word = eeprom->offset >> 1; + last_word = (eeprom->offset + eeprom->len - 1) >> 1; + max_len = (last_word - first_word + 1) * 2; + eeprom_buff = kmalloc(max_len, GFP_KERNEL); + if (!eeprom_buff) + return -ENOMEM; + + ptr = (void *)eeprom_buff; + + if (eeprom->offset & 1) { + /* need read/modify/write of first changed EEPROM word */ + /* only the second byte of the word is being modified */ + eeprom_buff[0] = ks8851_eeprom_read(dev, first_word); + ptr++; + } + if ((eeprom->offset + eeprom->len) & 1) + /* need read/modify/write of last changed EEPROM word */ + /* only the first byte of the word is being modified */ + eeprom_buff[last_word - first_word] = + ks8851_eeprom_read(dev, last_word); + + + /* Device's eeprom is little-endian, word addressable */ + le16_to_cpus(&eeprom_buff[0]); + le16_to_cpus(&eeprom_buff[last_word - first_word]); + + memcpy(ptr, bytes, eeprom->len); + + for (i = 0; i < last_word - first_word + 1; i++) + eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); + + ks8851_eeprom_write(dev, EEPROM_OP_EWEN, 0, 0); + + for (i = 0; i < last_word - first_word + 1; i++) { + ks8851_eeprom_write(dev, EEPROM_OP_WRITE, first_word + i, + eeprom_buff[i]); + mdelay(EEPROM_WRITE_TIME); + } + + ks8851_eeprom_write(dev, EEPROM_OP_EWDS, 0, 0); + + kfree(eeprom_buff); + return ret_val; +} + static const struct ethtool_ops ks8851_ethtool_ops = { .get_drvinfo = ks8851_get_drvinfo, .get_msglevel = ks8851_get_msglevel, @@ -1326,6 +1437,9 @@ static const struct ethtool_ops ks8851_ethtool_ops = { .set_settings = ks8851_set_settings, .get_link = ks8851_get_link, .nway_reset = ks8851_nway_reset, + .get_eeprom_len = ks8851_get_eeprom_len, + .get_eeprom = ks8851_get_eeprom, + .set_eeprom = ks8851_set_eeprom, }; /* MII interface controls */ From patchwork Tue Jul 6 15:42:34 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zach Pfeffer X-Patchwork-Id: 110435 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o66FhXQ6009943 for ; Tue, 6 Jul 2010 15:43:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754151Ab0GFPmn (ORCPT ); Tue, 6 Jul 2010 11:42:43 -0400 Received: from wolverine02.qualcomm.com ([199.106.114.251]:55829 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751304Ab0GFPmm (ORCPT ); Tue, 6 Jul 2010 11:42:42 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6034"; a="46472225" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 06 Jul 2010 08:42:39 -0700 Received: from localhost.localdomain (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id A1FEE10004C4; Tue, 6 Jul 2010 08:42:41 -0700 (PDT) From: Zach Pfeffer To: mel@csn.ul.ie Cc: linux-arch@vger.kernel.org, dwalker@codeaurora.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, Zach Pfeffer Subject: [RFC 1/3 v3] mm: iommu: An API to unify IOMMU, CPU and device memory management Date: Tue, 6 Jul 2010 08:42:34 -0700 Message-Id: <1278430956-2260-1-git-send-email-zpfeffer@codeaurora.org> X-Mailer: git-send-email 1.7.0.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 06 Jul 2010 15:43:33 +0000 (UTC) diff --git a/Documentation/vcm.txt b/Documentation/vcm.txt new file mode 100644 index 0000000..1c6a8be --- /dev/null +++ b/Documentation/vcm.txt @@ -0,0 +1,587 @@ +What is this document about? +============================ + +This document covers how to use the Virtual Contiguous Memory Manager +(VCMM), how the first implementation works with a specific low-level +Input/Output Memory Management Unit (IOMMU) and the way the VCMM is used +from user-space. It also contains a section that describes why something +like the VCMM is needed in the kernel. + +If anything in this document is wrong, please send patches to the +maintainer of this file, listed at the bottom of the document. + + +The Virtual Contiguous Memory Manager +===================================== + +The VCMM was built to solve the system-wide memory mapping issues that +occur when many bus-masters have IOMMUs. + +An IOMMU maps device addresses to physical addresses. It also insulates +the system from spurious or malicious device bus transactions and allows +fine-grained mapping attribute control. The Linux kernel core does not +contain a generic API to handle IOMMU mapped memory; device driver writers +must implement device specific code to interoperate with the Linux kernel +core. As the number of IOMMUs increases, coordinating the many address +spaces mapped by all discrete IOMMUs becomes difficult without in-kernel +support. + +The VCMM API enables device independent IOMMU control, virtual memory +manager (VMM) interoperation and non-IOMMU enabled device interoperation +by treating devices with or without IOMMUs and all CPUs with or without +MMUs, their mapping contexts and their mappings using common +abstractions. Physical hardware is given a generic device type and mapping +contexts are abstracted into Virtual Contiguous Memory (VCM) +regions. Users "reserve" memory from VCMs and "back" their reservations +with physical memory. + +Why the VCMM is Needed +---------------------- + +Driver writers who control devices with IOMMUs must contend with device +control and memory management. Driver writers have a large device driver +API that they can leverage to control their devices, but they are lacking +a unified API to help them program mappings into IOMMUs and share those +mappings with other devices and CPUs in the system. + +Sharing is complicated by Linux's CPU-centric VMM. The CPU-centric model +generally makes sense because average hardware only contains a MMU for the +CPU and possibly a graphics MMU. If every device in the system has one or +more MMUs the CPU-centric memory management (MM) programming model breaks +down. + +Abstracting IOMMU device programming into a common API has already begun +in the Linux kernel. It was built to abstract the difference between AMD +and Intel IOMMUs to support x86 virtualization on both platforms. The +interface is listed in include/linux/iommu.h. It contains +interfaces for mapping and unmapping as well as domain management. This +interface has not gained widespread use outside the x86; PA-RISC, Alpha +and SPARC architectures and ARM and PowerPC platforms all use their own +mapping modules to control their IOMMUs. The VCMM contains an IOMMU +programming layer, but since its abstraction supports map management +independent of device control, the layer is not used directly. This +higher-level view enables a new kernel service, not just an IOMMU +interoperation layer. + +The General Idea: Map Management using Graphs +--------------------------------------------- + +Looking at mapping from a system-wide perspective reveals a general graph +problem. The VCMM's API is built to manage the general mapping graph. Each +node that talks to memory, either through an MMU or directly (physically +mapped) can be thought of as the device-end of a mapping edge. The other +edge is the physical memory (or intermediate virtual space) that is +mapped. + +In the direct-mapped case the device is assigned a one-to-one MMU. This +scheme allows direct mapped devices to participate in general graph +management. + +The CPU nodes can also be brought under the same mapping abstraction with +the use of a light overlay on the existing VMM. This light overlay allows +VMM-managed mappings to interoperate with the common API. The light +overlay enables this without substantial modifications to the existing +VMM. + +In addition to CPU nodes that are running Linux (and the VMM), remote CPU +nodes that may be running other operating systems can be brought into the +general abstraction. Routing all memory management requests from a remote +node through the central memory management framework enables new features +like system-wide memory migration. This feature may only be feasible for +large buffers that are managed outside of the fast-path, but having remote +allocation in a system enables features that are impossible to build +without it. + +The fundamental objects that support graph-based map management are: + +1) Virtual Contiguous Memory Regions + +2) Reservations + +3) Associated Virtual Contiguous Memory Regions + +4) Memory Targets + +5) Physical Memory Allocations + +Usage Overview +-------------- + +In a nutshell, users allocate Virtual Contiguous Memory Regions and +associate those regions with one or more devices by creating an Associated +Virtual Contiguous Memory Region. Users then create Reservations from the +Virtual Contiguous Memory Region. At this point no physical memory has +been committed to the reservation. To associate physical memory with a +reservation a Physical Memory Allocation is created and the Reservation is +backed with this allocation. + +include/linux/vcm.h includes comments documenting each API. + +Virtual Contiguous Memory Regions +--------------------------------- + +A Virtual Contiguous Memory Region (VCM) abstracts the memory space a +device sees. The addresses of the region are only used by the devices +which are associated with the region. This address space would normally be +implemented as a device page table. + +A VCM is created and destroyed with three functions: + + struct vcm *vcm_create(unsigned long start_addr, unsigned long len); + + struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id); + + int vcm_free(struct vcm *vcm); + +start_addr is an offset into the address space where allocations will +start from. len is the length from start_addr of the VCM. Both functions +generate an instance of a VCM. + +ext_vcm_id is used to pass a request to the VMM to generate a VCM +instance. In the current implementation the call simply makes a note that +the VCM instance is a VMM VCM instance for other interfaces usage. This +muxing is seen throughout the implementation. + +vcm_create() and vcm_create_from_prebuilt() produce VCM instances for +virtually mapped devices (IOMMUs and CPUs). To create a one-to-one mapped +VCM, users pass the start_addr and len of the physical region. The VCMM +matches this and records that the VCM instance is a one-to-one VCM. + +The newly created VCM instance can be passed to any function that needs to +operate on or with a virtual contiguous memory region. Its main attributes +are a start_addr and a len as well as an internal setting that allows the +implementation to mux between true virtual spaces, one-to-one mapped +spaces and VMM managed spaces. + +The current implementation uses the genalloc library to manage the VCM for +IOMMU devices. Return values and more in-depth per-function documentation +for these and the ones listed below are in include/linux/vcm.h. + +Reservations +------------ + +A Reservation is a contiguous region allocated from a VCM. There is no +physical memory associated with it. + +A Reservation is created and destroyed with: + + struct res *vcm_reserve(struct vcm *vcm, size_t len, u32 attr); + + int vcm_unreserve(struct res *res); + +A vcm is a VCM created above. len is the length of the request. It can be +up to the length of the VCM region the reservation is being created +from. attr are mapping attributes: read, write, execute, user, supervisor, +secure, not-cached, write-back/write-allocate, write-back/no +write-allocate, write-through. These attrs are appropriate for ARM but can +be changed to match to any architecture. + +The implementation calls gen_pool_alloc() for IOMMU devices, +alloc_vm_area() for VMM areas and is a pass-through for one-to-one mapped +areas. + +Associated Virtual Contiguous Memory Regions and Activation +----------------------------------------------------------- + +An Associated Virtual Contiguous Memory Region (AVCM) is a mapping of a +VCM to a device. The mapping can be active or inactive. + +An AVCM is managed with: + + struct avcm *vcm_assoc(struct vcm *vcm, struct device *dev, u32 attr); + + int vcm_deassoc(struct avcm *avcm); + + int vcm_activate(struct avcm *avcm); + + int vcm_deactivate(struct avcm *avcm); + +A VCM instance is a VCM created above. A dev is an opaque device handle +thats passed down to the device driver the VCMM muxes in to handle a +request. attr are association attributes: split, use-high or +use-low. split controls which transactions hit a high-address page-table +and which transactions hit a low-address page-table. For instance, all +transactions whose most significant address bit is one would use the +high-address page-table, any other transaction would use the low address +page-table. This scheme is ARM-specific and could be changed in other +architectures. One VCM instance can be associated with many devices and +many VCM instances can be associated with one device. + +An AVCM is only a link. To program and deprogram a device with a VCM the +user calls vcm_activate() and vcm_deactivate(). For IOMMU devices, +activating a mapping programs the base address of a page table into an +IOMMU. For VMM and one-to-one based devices, mappings are active +immediately but the API does require an activation call for them for +internal reference counting. + +Memory Targets +-------------- + +A Memory Target is a platform independent way of specifying a physical +pool; it abstracts a pool of physical memory. The physical memory pool may +be physically discontiguous, need to be allocated from in a unique way or +have other user-defined attributes. + +Physical Memory Allocation and Reservation Backing +-------------------------------------------------- + +Physical memory is allocated as a separate step from reserving +memory. This allows multiple reservations to back the same physical +memory. + +A Physical Memory Allocation is managed using the following functions: + + struct physmem *vcm_phys_alloc(enum memtype_t memtype, + size_t len, u32 attr); + + int vcm_phys_free(struct physmem *physmem); + + int vcm_back(struct res *res, struct physmem *physmem); + + int vcm_unback(struct res *res); + +attr can include an alignment request, a specification to map memory using +various block sizes and/or to use physically contiguous memory. memtype is +one of the memory types listed in Memory Targets. + +The current implementation manages two pools of memory. One pool is a +contiguous block of memory and the other is a set of contiguous block +pools. In the current implementation the block pools contain 4K, 64K and +1M blocks. The physical allocator does not try to split blocks from the +contiguous block pools to satisfy requests. + +The use of 4K, 64K and 1M blocks solves a problem with some IOMMU +hardware. IOMMUs are placed in front of multimedia engines to provide a +contiguous address space to the device. Multimedia devices need large +buffers and large buffers may map to a large number of physical +blocks. IOMMUs tend to have small translation lookaside buffers +(TLBs). Since the TLB is small the number of physical blocks that map a +given range needs to be small or else the IOMMU will continually fetch new +translations during a typical streamed multimedia flow. By using a 1 MB +mapping (or 64K mapping) instead of a 4K mapping the number of misses can +be minimized, allowing the multimedia block to meet its performance goals. + +Low Level Control +----------------- + +It is necessary in some instances to access attributes and provide +higher-level control of the low-level hardware abstraction. The API +contains many members and functions for this task but the two that are +typically used are: + + res->dev_addr; + + int vcm_hook(struct device *dev, vcm_handler handler, void *data); + +res->dev_addr is the device address given a reservation. This device +address is a virtual IOMMU address for reservations on IOMMU VCMs, a +virtual VMM address for reservations on VMM VCMs and a virtual (really +physical since its one-to-one mapped) address for one-to-one devices. + +The function, vcm_hook, allows a caller in the kernel to register a +user_handler. The handler is passed the data member passed to vcm_hook +during a fault. The user can return 1 to indicate that the underlying +driver should handle the fault and retry the transaction or they can +return 0 to halt the transaction. If the user doesn't register a +handler the low-level driver will print a warning and terminate the +transaction. + +A Detailed Walk Through +----------------------- + +The following call sequence walks through a typical allocation +sequence. In the first stage the memory for a device is reserved and +backed. This occurs without mapping the memory into a VMM VCM region. The +second stage maps the first VCM region into a VMM VCM region so the kernel +can read or write it. The second stage is not necessary if the VMM does +not need to read or modify the contents of the original mapping. + + Stage 1: Map and Allocate Memory for a Device + + The call sequence starts by creating a VCM region: + + vcm = vcm_create(start_addr, len); + + The next call associates a VCM region with a device: + + avcm = vcm_assoc(vcm, dev, attr); + + To activate the association, users call vcm_activate() on the avcm from + the associate call. This programs the underlining device with the + mappings. + + ret = vcm_activate(avcm); + + Once a VCM region is created and associated it can be reserved from + with: + + res = vcm_reserve(vcm, res_len, res_attr); + + A user then allocates physical memory with: + + physmem = vcm_phys_alloc(memtype, len, phys_attr); + + To back the reservation with the physical memory allocation the user + calls: + + vcm_back(res, physmem); + + + Stage 2: Map the Device's Memory into the VMM's VCM region + + If the VMM needs to read and/or write the region that was just created, + the following calls are made. + + The first call creates a prebuilt VCM with: + + vcm_vmm = vcm_from_prebuilt(ext_vcm_id); + + The prebuilt VCM is associated with the CPU device and activated with: + + avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr); + vcm_activate(avcm_vmm); + + A reservation is made on the VMM VCM with: + + res_vmm = vcm_reserve(vcm_vmm, res_len, attr); + + Finally, once the topology has been set up a vcm_back() allows the VMM + to read the memory using the physmem generated in stage 1: + + vcm_back(res_vmm, physmem); + +Mapping IOMMU, one-to-one and VMM Reservations +---------------------------------------------- + +The following example demonstrates mapping IOMMU, one-to-one and VMM +reservations to the same physical memory. It shows the use of phys_addr +and phys_size to create a contiguous VCM for one-to-one mapped devices. + + The user allocates physical memory: + + physmem = vcm_phys_alloc(memtype, SZ_2MB + SZ_4K, CONTIGUOUS); + + Creates an IOMMU VCM: + + vcm_iommu = vcm_create(SZ_1K, SZ_16M); + + Creates a one-to-one VCM: + + vcm_onetoone = vcm_create(phys_addr, phys_size); + + Creates a Prebuit VCM: + + vcm_vmm = vcm_from_prebuit(ext_vcm_id); + + Associate and activate all three to their respective devices: + + avcm_iommu = vcm_assoc(vcm_iommu, dev_iommu, attr0); + avcm_onetoone = vcm_assoc(vcm_onetoone, dev_onetoone, attr1); + avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr2); + vcm_activate(avcm_iommu); + vcm_activate(avcm_onetoone); + vcm_activate(avcm_vmm); + + Associations that fail return 0. + + And finally, creates and backs reservations on all 3 such that they + all point to the same memory: + + res_iommu = vcm_reserve(vcm_iommu, SZ_2MB + SZ_4K, attr); + res_onetoone = vcm_reserve(vcm_onetoone, SZ_2MB + SZ_4K, attr); + res_vmm = vcm_reserve(vcm_vmm, SZ_2MB + SZ_4K, attr); + vcm_back(res_iommu, physmem); + vcm_back(res_onetoone, physmem); + vcm_back(res_vmm, physmem); + + Like associations, reservations that fail return 0. + +VCM Summary +----------- + +The VCMM is an attempt to abstract attributes of three distinct classes of +mappings into one API. The VCMM allows users to reason about mappings as +first class objects. It also allows memory mappings to flow from the +traditional 4K mappings prevalent on systems today to more efficient block +sizes. Finally, it allows users to manage mapping interoperation without +becoming VMM experts. These features will allow future systems with many +MMU mapped devices to interoperate simply and therefore correctly. + + +IOMMU Hardware Control +====================== + +The VCM currently supports a single type of IOMMU, a Qualcomm System MMU +(SMMU). The SMMU interface contains functions to map and unmap virtual +addresses, perform address translations and initialize hardware. A +Qualcomm SMMU can contain multiple MMU contexts. Each context can +translate in parallel. All contexts in a SMMU share one global translation +look-aside buffer (TLB). + +To support context muxing the SMMU module creates and manages device +independent virtual contexts. These context abstractions are bound to +actual contexts at run-time. Once bound, a context can be activated. This +activation programs the underlying context with the virtual context +affecting a context switch. + +The following functions are all documented in: + + arch/arm/mach-msm/include/mach/smmu_driver.h. + +Mapping +------- + +To map and unmap a virtual page into physical space the VCM calls: + + int smmu_map(struct smmu_dev *dev, unsigned long pa, + unsigned long va, unsigned long len, unsigned int attr); + + int smmu_unmap(struct smmu_dev *dev, unsigned long va, + unsigned long len); + + int smmu_update_start(struct smmu_dev *dev); + + int smmu_update_done(struct smmu_dev *dev); + +The size given to map must be 4K, 64K, 1M or 16M and the VA and PA must be +aligned to the given size. smmu_update_start() and smmu_update_done() +should be called before and after each map or unmap. + +Translation +----------- + +To request a hardware VA to PA translation on a single address the VCM +calls: + + unsigned long smmu_translate(struct smmu_dev *dev, + unsigned long va); + +Fault Handling +-------------- + +To register an interrupt handler for a context the VCM calls: + + int smmu_hook_interrupt(struct smmu_dev *dev, vcm_handler handler, + void *data); + +The registered interrupt handler should return 1 if it wants the SMMU +driver to retry the transaction again and 0 if it wants the SMMU driver to +terminate the transaction. + +Managing SMMU Initialization and Contexts +----------------------------------------- + +SMMU hardware initialization and management happens in 2 steps. The first +step initializes global SMMU devices and abstract device contexts. The +second step binds contexts and devices. + +An SMMU hardware instance is built with: + + int smmu_drvdata_init(struct smmu_driver *drv, unsigned long base, + int irq); + +An SMMU context is initialized and deinitialized with: + + struct smmu_dev *smmu_ctx_init(int ctx); + int smmu_ctx_deinit(struct smmu_dev *dev); + +An abstract SMMU context is bound to a particular SMMU with: + + int smmu_ctx_bind(struct smmu_dev *ctx, struct smmu_driver *drv); + +Activation +---------- + +Activation affects a context switch. + +Activation, deactivation and activation state testing are done with: + + int smmu_activate(struct smmu_dev *dev); + int smmu_deactivate(struct smmu_dev *dev); + int smmu_is_active(struct smmu_dev *dev); + + +Userspace Access to Devices with IOMMUs +======================================= + +A device that issues transactions through an IOMMU must work with two +APIs. The first API is the VCM. The VCM API is device independent. Users +pass the VCM a dev_id and the VCM makes calls on the hardware device it +has been configured with using this dev_id. The second API is whatever +device topology has been created to organize the particular IOMMUs in a +system. The only constraint on this second API is that it must give the +user a single dev_id that it can pass through the VCM. + +For the Qualcomm SMMUs the second API consists of a tree of platform +devices and two platform drivers as well as a context lookup function that +traverses the device tree and returns a dev_id given a context name. + +Qualcomm SMMU Device Tree +------------------------- + +The current tree organizes the devices into a tree that looks like the +following: + +smmu/ + smmu0/ + ctx0 + ctx1 + ctx2 + smmu1/ + ctx3 + + +Each context, ctx[n] and each smmu, smmu[n] is given a name. Since users +are interested in contexts not smmus, the context name is passed to a +function to find the dev_id associated with that name. The functions to +find, free and get the base address (since the device probe function calls +ioremap to map the SMMUs configuration registers into the kernel) are +listed here: + + struct smmu_dev *smmu_get_ctx_instance(char *ctx_name); + int smmu_free_ctx_instance(struct smmu_dev *dev); + unsigned long smmu_get_base_addr(struct smmu_dev *dev); + +Documentation for these functions is in: + + arch/arm/mach-msm/include/mach/smmu_device.h + +Each context is given a dev node named after the context. For example: + + /dev/vcodec_a_mm1 + /dev/vcodec_b_mm2 + /dev/vcodec_stream + etc... + +Users open, close and mmap these nodes to access VCM buffers from +userspace in the same way that they used to open, close and mmap /dev +nodes that represented large physically contiguous buffers (called PMEM +buffers on Android). + +Example +------- + +An abbreviated example is shown here: + +Users get the dev_id associated with their target context, create a VCM +topology appropriate for their device and finally associate the VCMs of +the topology with the contexts that will take the VCMs: + + dev_id = smmu_get_ctx_instance(vcodec_a_stream); + +create vcm and needed topology + + avcm = vcm_assoc(vcm, dev_id, attr); + +Tying it all Together +--------------------- + +VCMs, IOMMUs and the device tree all work to support system-wide memory +mappings. The use of each API in this system allows users to concentrate +on the relevant details without needing to worry about low-level +details. The API's clear separation of memory spaces and the devices that +support those memory spaces continues the Linux tradition of abstracting the +what from the how. + + +Maintainer: Zach Pfeffer From patchwork Tue Jul 6 15:42:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zach Pfeffer X-Patchwork-Id: 110436 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o66FhXQ7009943 for ; Tue, 6 Jul 2010 15:43:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754540Ab0GFPmw (ORCPT ); Tue, 6 Jul 2010 11:42:52 -0400 Received: from wolverine02.qualcomm.com ([199.106.114.251]:55829 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754338Ab0GFPmp (ORCPT ); Tue, 6 Jul 2010 11:42:45 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6034"; a="46472228" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 06 Jul 2010 08:42:43 -0700 Received: from localhost.localdomain (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 01B5910004C4; Tue, 6 Jul 2010 08:42:45 -0700 (PDT) From: Zach Pfeffer To: mel@csn.ul.ie Cc: linux-arch@vger.kernel.org, dwalker@codeaurora.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, Zach Pfeffer Subject: [RFC 3/3 v3] mm: iommu: The Virtual Contiguous Memory Manager Date: Tue, 6 Jul 2010 08:42:36 -0700 Message-Id: <1278430956-2260-3-git-send-email-zpfeffer@codeaurora.org> X-Mailer: git-send-email 1.7.0.2 In-Reply-To: <1278430956-2260-1-git-send-email-zpfeffer@codeaurora.org> References: <1278430956-2260-1-git-send-email-zpfeffer@codeaurora.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 06 Jul 2010 15:43:34 +0000 (UTC) different pools. This allows fine grained control of block and physical placement, a feature many advanced IOMMU devices need. Once a user has made a reservation on a VCM and allocated physical memory, the two graph end-points are joined in a backing step. This step allows multiple reservations to map the same physical location. Many of the functions in the API take various attributes that provide fine grained control of the objects they create. For instance, reservations can map cachable memory and physical allocations can be constrained to use a particular subset of block sizes. Signed-off-by: Zach Pfeffer --- arch/arm/mm/vcm.c | 1877 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/vcm.h | 661 ++++++++++++++++ include/linux/vcm_types.h | 338 ++++++++ 3 files changed, 2876 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mm/vcm.c create mode 100644 include/linux/vcm.h create mode 100644 include/linux/vcm_types.h diff --git a/arch/arm/mm/vcm.c b/arch/arm/mm/vcm.c new file mode 100644 index 0000000..2c951c3 --- /dev/null +++ b/arch/arm/mm/vcm.c @@ -0,0 +1,1877 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_SMMU +#include +#endif + +/* alloc_vm_area */ +#include +#include +#include + +/* may be temporary */ +#include + +#include +#include + +#define BOOTMEM_SZ SZ_32M +#define BOOTMEM_ALIGN SZ_1M + +#define CONT_SZ SZ_8M +#define CONT_ALIGN SZ_1M + +#define ONE_TO_ONE_CHK 1 + +#define vcm_err(a, ...) \ + pr_err("ERROR %s %i " a, __func__, __LINE__, ##__VA_ARGS__) + +static void *bootmem; +static void *bootmem_cont; +static struct vcm *cont_vcm; +static struct phys_chunk *cont_phys_chunk; + +DEFINE_SPINLOCK(vcmlock); + +static int vcm_no_res(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + return list_empty(&vcm->res_head); +fail: + return -EINVAL; +} + +static int vcm_no_assoc(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + return list_empty(&vcm->assoc_head); +fail: + return -EINVAL; +} + +static int vcm_all_activated(struct vcm *vcm) +{ + struct avcm *avcm; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm) + if (!avcm->is_active) + return 0; + + return 1; +fail: + return -1; +} + +static void vcm_destroy_common(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return; + } + + memset(vcm, 0, sizeof(*vcm)); + kfree(vcm); +} + +static struct vcm *vcm_create_common(void) +{ + struct vcm *vcm = 0; + + vcm = kzalloc(sizeof(*vcm), GFP_KERNEL); + if (!vcm) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret 0\n", + sizeof(*vcm)); + goto fail; + } + + INIT_LIST_HEAD(&vcm->res_head); + INIT_LIST_HEAD(&vcm->assoc_head); + + return vcm; + +fail: + return NULL; +} + + +static int vcm_create_pool(struct vcm *vcm, size_t start_addr, size_t len) +{ + int ret = 0; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + vcm->start_addr = start_addr; + vcm->len = len; + + vcm->pool = gen_pool_create(PAGE_SHIFT, -1); + if (!vcm->pool) { + vcm_err("gen_pool_create(%x, -1) ret 0\n", PAGE_SHIFT); + goto fail; + } + + ret = gen_pool_add(vcm->pool, start_addr, len, -1); + if (ret) { + vcm_err("gen_pool_add(%p, %p, %i, -1) ret %i\n", vcm->pool, + (void *) start_addr, len, ret); + goto fail2; + } + + return 0; + +fail2: + gen_pool_destroy(vcm->pool); +fail: + return -1; +} + + +static struct vcm *vcm_create_flagged(int flag, size_t start_addr, size_t len) +{ + int ret = 0; + struct vcm *vcm = 0; + + vcm = vcm_create_common(); + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + /* special one-to-one mapping case */ + if ((flag & ONE_TO_ONE_CHK) && + bootmem_cont && + __pa(bootmem_cont) && + start_addr == __pa(bootmem_cont) && + len == CONT_SZ) { + vcm->type = VCM_ONE_TO_ONE; + } else { + ret = vcm_create_pool(vcm, start_addr, len); + vcm->type = VCM_DEVICE; + } + + if (ret) { + vcm_err("vcm_create_pool(%p, %p, %i) ret %i\n", vcm, + (void *) start_addr, len, ret); + goto fail2; + } + + return vcm; + +fail2: + vcm_destroy_common(vcm); +fail: + return NULL; +} + +struct vcm *vcm_create(unsigned long start_addr, size_t len) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + vcm = vcm_create_flagged(ONE_TO_ONE_CHK, start_addr, len); + spin_unlock_irqrestore(&vcmlock, flags); + return vcm; +} + + +static int ext_vcm_id_valid(size_t ext_vcm_id) +{ + return ((ext_vcm_id == VCM_PREBUILT_KERNEL) || + (ext_vcm_id == VCM_PREBUILT_USER)); +} + + +struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id) +{ + unsigned long flags; + struct vcm *vcm = 0; + + spin_lock_irqsave(&vcmlock, flags); + + if (!ext_vcm_id_valid(ext_vcm_id)) { + vcm_err("ext_vcm_id_valid(%i) ret 0\n", ext_vcm_id); + goto fail; + } + + vcm = vcm_create_common(); + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (ext_vcm_id == VCM_PREBUILT_KERNEL) + vcm->type = VCM_EXT_KERNEL; + else if (ext_vcm_id == VCM_PREBUILT_USER) + vcm->type = VCM_EXT_USER; + else { + vcm_err("UNREACHABLE ext_vcm_id is illegal\n"); + goto fail_free; + } + + /* TODO: set kernel and userspace start_addr and len, if this + * makes sense */ + + spin_unlock_irqrestore(&vcmlock, flags); + return vcm; + +fail_free: + vcm_destroy_common(vcm); +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return NULL; +} + + +struct vcm *vcm_clone(struct vcm *vcm) +{ + return 0; +} + + +/* No lock needed, vcm->start_addr is never updated after creation */ +size_t vcm_get_start_addr(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return 1; + } + + return vcm->start_addr; +} + + +/* No lock needed, vcm->len is never updated after creation */ +size_t vcm_get_len(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return 0; + } + + return vcm->len; +} + + +static int vcm_free_common_rule(struct vcm *vcm) +{ + int ret; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + ret = vcm_no_res(vcm); + if (!ret) { + vcm_err("vcm_no_res(%p) ret 0\n", vcm); + goto fail_busy; + } + + if (ret == -EINVAL) { + vcm_err("vcm_no_res(%p) ret -EINVAL\n", vcm); + goto fail; + } + + ret = vcm_no_assoc(vcm); + if (!ret) { + vcm_err("vcm_no_assoc(%p) ret 0\n", vcm); + goto fail_busy; + } + + if (ret == -EINVAL) { + vcm_err("vcm_no_assoc(%p) ret -EINVAL\n", vcm); + goto fail; + } + + return 0; + +fail_busy: + return -EBUSY; +fail: + return -EINVAL; +} + + +static int vcm_free_pool_rule(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + /* A vcm always has a valid pool, don't free the vcm because + what we got is probably invalid. + */ + if (!vcm->pool) { + vcm_err("NULL vcm->pool\n"); + goto fail; + } + + return 0; + +fail: + return -EINVAL; +} + + +static void vcm_free_common(struct vcm *vcm) +{ + memset(vcm, 0, sizeof(*vcm)); + + kfree(vcm); +} + + +static int vcm_free_pool(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + gen_pool_destroy(vcm->pool); + + return 0; + +fail: + return -1; +} + + +static int __vcm_free(struct vcm *vcm) +{ + int ret; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + ret = vcm_free_common_rule(vcm); + if (ret != 0) { + vcm_err("vcm_free_common_rule(%p) ret %i\n", vcm, ret); + goto fail; + } + + if (vcm->type == VCM_DEVICE) { + ret = vcm_free_pool_rule(vcm); + if (ret != 0) { + vcm_err("vcm_free_pool_rule(%p) ret %i\n", + (void *) vcm, ret); + goto fail; + } + + ret = vcm_free_pool(vcm); + if (ret != 0) { + vcm_err("vcm_free_pool(%p) ret %i", (void *) vcm, ret); + goto fail; + } + } + + vcm_free_common(vcm); + + return 0; + +fail: + return -EINVAL; +} + +int vcm_free(struct vcm *vcm) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + ret = __vcm_free(vcm); + spin_unlock_irqrestore(&vcmlock, flags); + + return ret; +} + + +static struct res *__vcm_reserve(struct vcm *vcm, size_t len, u32 attr) +{ + struct res *res = NULL; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (len == 0) { + vcm_err("len is 0\n"); + goto fail; + } + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret 0", sizeof(*res)); + goto fail; + } + + INIT_LIST_HEAD(&res->res_elm); + res->vcm = vcm; + res->len = len; + res->attr = attr; + + if (len/SZ_1M) + res->alignment_req = SZ_1M; + else if (len/SZ_64K) + res->alignment_req = SZ_64K; + else + res->alignment_req = SZ_4K; + + res->aligned_len = res->alignment_req + len; + + switch (vcm->type) { + case VCM_DEVICE: + /* should always be not zero */ + if (!vcm->pool) { + vcm_err("NULL vcm->pool\n"); + goto fail2; + } + + res->ptr = gen_pool_alloc(vcm->pool, res->aligned_len); + if (!res->ptr) { + vcm_err("gen_pool_alloc(%p, %i) ret 0\n", + vcm->pool, res->aligned_len); + goto fail2; + } + + /* Calculate alignment... this will all change anyway */ + res->dev_addr = res->ptr + + (res->alignment_req - + (res->ptr & (res->alignment_req - 1))); + + break; + case VCM_EXT_KERNEL: + res->vm_area = alloc_vm_area(res->aligned_len); + res->mapped = 0; /* be explicit */ + if (!res->vm_area) { + vcm_err("NULL res->vm_area\n"); + goto fail2; + } + + res->dev_addr = (size_t) res->vm_area->addr + + (res->alignment_req - + ((size_t) res->vm_area->addr & + (res->alignment_req - 1))); + + break; + case VCM_ONE_TO_ONE: + break; + default: + vcm_err("%i is an invalid vcm->type\n", vcm->type); + goto fail2; + } + + list_add_tail(&res->res_elm, &vcm->res_head); + + return res; + +fail2: + kfree(res); +fail: + return 0; +} + + +struct res *vcm_reserve(struct vcm *vcm, size_t len, u32 attr) +{ + unsigned long flags; + struct res *res; + + spin_lock_irqsave(&vcmlock, flags); + res = __vcm_reserve(vcm, len, attr); + spin_unlock_irqrestore(&vcmlock, flags); + + return res; +} + + +struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm* vcm, + size_t len, u32 attr) +{ + return 0; +} + + +/* No lock needed, res->vcm is never updated after creation */ +struct vcm *vcm_get_vcm_from_res(struct res *res) +{ + if (!res) { + vcm_err("NULL res\n"); + return 0; + } + + return res->vcm; +} + + +static int __vcm_unreserve(struct res *res) +{ + struct vcm *vcm; + + if (!res) { + vcm_err("NULL res\n"); + goto fail; + } + + if (!res->vcm) { + vcm_err("NULL res->vcm\n"); + goto fail; + } + + vcm = res->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + switch (vcm->type) { + case VCM_DEVICE: + if (!res->vcm->pool) { + vcm_err("NULL (res->vcm))->pool\n"); + goto fail; + } + + /* res->ptr could be zero, this isn't an error */ + gen_pool_free(res->vcm->pool, res->ptr, + res->aligned_len); + break; + case VCM_EXT_KERNEL: + if (res->mapped) { + vcm_err("res->mapped is true\n"); + goto fail; + } + + /* This may take a little explaining. + * In the kernel vunmap will free res->vm_area + * so if we've called it then we shouldn't call + * free_vm_area(). If we've called it we set + * res->vm_area to 0. + */ + if (res->vm_area) { + free_vm_area(res->vm_area); + res->vm_area = 0; + } + + break; + case VCM_ONE_TO_ONE: + break; + default: + vcm_err("%i is an invalid vcm->type\n", vcm->type); + goto fail; + } + + list_del(&res->res_elm); + + /* be extra careful by clearing the memory before freeing it */ + memset(res, 0, sizeof(*res)); + + kfree(res); + + return 0; + +fail: + return -EINVAL; +} + + +int vcm_unreserve(struct res *res) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + ret = __vcm_unreserve(res); + spin_unlock_irqrestore(&vcmlock, flags); + + return ret; +} + + +/* No lock needed, res->len is never updated after creation */ +size_t vcm_get_res_len(struct res *res) +{ + if (!res) { + vcm_err("res is 0\n"); + return 0; + } + + return res->len; +} + + +int vcm_set_res_attr(struct res *res, u32 attr) +{ + return 0; +} + + +size_t vcm_get_num_res(struct vcm *vcm) +{ + return 0; +} + + +struct res *vcm_get_next_res(struct vcm *vcm, struct res *res) +{ + return 0; +} + + +size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, + size_t from_off, size_t len) +{ + return 0; +} + + +size_t vcm_get_min_page_size(void) +{ + return PAGE_SIZE; +} + + +static int vcm_to_smmu_attr(u32 attr) +{ + int smmu_attr = 0; + + switch (attr & VCM_CACHE_POLICY) { + case VCM_NOTCACHED: + smmu_attr = VCM_DEV_ATTR_NONCACHED; + break; + case VCM_WB_WA: + smmu_attr = VCM_DEV_ATTR_CACHED_WB_WA; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + case VCM_WB_NWA: + smmu_attr = VCM_DEV_ATTR_CACHED_WB_NWA; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + case VCM_WT: + smmu_attr = VCM_DEV_ATTR_CACHED_WT; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + default: + return -1; + } + + return smmu_attr; +} + + +/* TBD if you vcm_back again what happens? */ +int vcm_back(struct res *res, struct physmem *physmem) +{ + unsigned long flags; + struct vcm *vcm; + struct phys_chunk *chunk; + size_t va = 0; + int ret; + int attr; + + spin_lock_irqsave(&vcmlock, flags); + + if (!res) { + vcm_err("NULL res\n"); + goto fail; + } + + vcm = res->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + switch (vcm->type) { + case VCM_DEVICE: + case VCM_EXT_KERNEL: /* hack part 1 */ + attr = vcm_to_smmu_attr(res->attr); + if (attr == -1) { + vcm_err("Bad SMMU attr\n"); + goto fail; + } + break; + default: + attr = 0; + break; + } + + if (!physmem) { + vcm_err("NULL physmem\n"); + goto fail; + } + + if (res->len == 0) { + vcm_err("res->len is 0\n"); + goto fail; + } + + if (physmem->len == 0) { + vcm_err("physmem->len is 0\n"); + goto fail; + } + + if (res->len != physmem->len) { + vcm_err("res->len (%i) != physmem->len (%i)\n", + res->len, physmem->len); + goto fail; + } + + if (physmem->is_cont) { + if (physmem->res == 0) { + vcm_err("cont physmem->res is 0"); + goto fail; + } + } else { + /* fail if no physmem */ + if (list_empty(&physmem->alloc_head.allocated)) { + vcm_err("no allocated phys memory"); + goto fail; + } + } + + ret = vcm_no_assoc(res->vcm); + if (ret == 1) { + vcm_err("can't back un associated VCM\n"); + goto fail; + } + + if (ret == -1) { + vcm_err("vcm_no_assoc() ret -1\n"); + goto fail; + } + + ret = vcm_all_activated(res->vcm); + if (ret == 0) { + vcm_err("can't back, not all associations are activated\n"); + goto fail_eagain; + } + + if (ret == -1) { + vcm_err("vcm_all_activated() ret -1\n"); + goto fail; + } + + va = res->dev_addr; + + list_for_each_entry(chunk, &physmem->alloc_head.allocated, + allocated) { + struct vcm *vcm = res->vcm; + size_t chunk_size = vcm_alloc_idx_to_size(chunk->size_idx); + + switch (vcm->type) { + case VCM_DEVICE: + { +#ifdef CONFIG_SMMU + struct avcm *avcm; + /* map all */ + list_for_each_entry(avcm, &vcm->assoc_head, + assoc_elm) { + + ret = smmu_map( + (struct smmu_dev *) avcm->dev, + chunk->pa, va, chunk_size, attr); + if (ret != 0) { + vcm_err("smmu_map(%p, %p, %p, 0x%x," + "0x%x)" + " ret %i", + (void *) avcm->dev, + (void *) chunk->pa, + (void *) va, + (int) chunk_size, attr, ret); + goto fail; + /* TODO handle weird inter-map case */ + } + } + break; +#else + vcm_err("No SMMU support - VCM_DEVICE not supported\n"); + goto fail; +#endif + } + + case VCM_EXT_KERNEL: + { + unsigned int pages_in_chunk = chunk_size / PAGE_SIZE; + unsigned long loc_va = va; + unsigned long loc_pa = chunk->pa; + + const struct mem_type *mtype; + + /* TODO: get this based on MEMTYPE */ + mtype = get_mem_type(MT_DEVICE); + if (!mtype) { + vcm_err("mtype is 0\n"); + goto fail; + } + + /* TODO: Map with the same chunk size */ + while (pages_in_chunk--) { + ret = ioremap_page(loc_va, + loc_pa, + mtype); + if (ret != 0) { + vcm_err("ioremap_page(%p, %p, %p) ret" + " %i", (void *) loc_va, + (void *) loc_pa, + (void *) mtype, ret); + goto fail; + /* TODO handle weird + inter-map case */ + } + + /* hack part 2 */ + /* we're changing the PT entry behind + * linux's back + */ + ret = cpu_set_attr(loc_va, PAGE_SIZE, attr); + if (ret != 0) { + vcm_err("cpu_set_attr(%p, %lu, %x)" + "ret %i\n", + (void *) loc_va, PAGE_SIZE, + attr, ret); + goto fail; + /* TODO handle weird + inter-map case */ + } + + res->mapped = 1; + + loc_va += PAGE_SIZE; + loc_pa += PAGE_SIZE; + } + + flush_cache_vmap(va, loc_va); + break; + } + case VCM_ONE_TO_ONE: + va = chunk->pa; + break; + default: + /* this should never happen */ + goto fail; + } + + va += chunk_size; + /* also add res to the allocated chunk list of refs */ + } + + /* note the reservation */ + res->physmem = physmem; + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_eagain: + spin_unlock_irqrestore(&vcmlock, flags); + return -EAGAIN; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_unback(struct res *res) +{ + unsigned long flags; + struct vcm *vcm; + struct physmem *physmem; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + + if (!res) + goto fail; + + vcm = res->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!res->physmem) { + vcm_err("can't unback a non-backed reservation\n"); + goto fail; + } + + physmem = res->physmem; + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + if (list_empty(&physmem->alloc_head.allocated)) { + vcm_err("physmem allocation is empty\n"); + goto fail; + } + + ret = vcm_no_assoc(res->vcm); + if (ret == 1) { + vcm_err("can't unback a unassociated reservation\n"); + goto fail; + } + + if (ret == -1) { + vcm_err("vcm_no_assoc(%p) ret -1\n", (void *) res->vcm); + goto fail; + } + + ret = vcm_all_activated(res->vcm); + if (ret == 0) { + vcm_err("can't unback, not all associations are active\n"); + goto fail_eagain; + } + + if (ret == -1) { + vcm_err("vcm_all_activated(%p) ret -1\n", (void *) res->vcm); + goto fail; + } + + + switch (vcm->type) { + case VCM_EXT_KERNEL: + if (!res->mapped) { + vcm_err("can't unback an unmapped VCM_EXT_KERNEL" + " VCM\n"); + goto fail; + } + + /* vunmap free's vm_area */ + vunmap(res->vm_area->addr); + res->vm_area = 0; + + res->mapped = 0; + break; + + case VCM_DEVICE: + { +#ifdef CONFIG_SMMU + struct phys_chunk *chunk; + size_t va = res->dev_addr; + + list_for_each_entry(chunk, &physmem->alloc_head.allocated, + allocated) { + struct vcm *vcm = res->vcm; + size_t chunk_size = + vcm_alloc_idx_to_size(chunk->size_idx); + struct avcm *avcm; + + /* un map all */ + list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm) { + ret = smmu_unmap( + (struct smmu_dev *) avcm->dev, + va, chunk_size); + if (ret != 0) { + vcm_err("smmu_unmap(%p, %p, 0x%x)" + " ret %i", + (void *) avcm->dev, + (void *) va, + (int) chunk_size, ret); + goto fail; + /* TODO handle weird inter-unmap state*/ + } + } + va += chunk_size; + /* may to a light unback, depending on the requested + * functionality + */ + } +#else + vcm_err("No SMMU support - VCM_DEVICE memory not supported\n"); + goto fail; +#endif + break; + } + + case VCM_ONE_TO_ONE: + break; + default: + /* this should never happen */ + goto fail; + } + + /* clear the reservation */ + res->physmem = 0; + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_eagain: + spin_unlock_irqrestore(&vcmlock, flags); + return -EAGAIN; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +enum memtarget_t vcm_get_memtype_of_res(struct res *res) +{ + return VCM_INVALID; +} + +static int vcm_free_max_munch_cont(struct phys_chunk *head) +{ + struct phys_chunk *chunk, *tmp; + + if (!head) + return -1; + + list_for_each_entry_safe(chunk, tmp, &head->allocated, + allocated) { + list_del_init(&chunk->allocated); + } + + return 0; +} + +static int vcm_alloc_max_munch_cont(size_t start_addr, size_t len, + struct phys_chunk *head) +{ + /* this function should always succeed, since it + parallels a VCM */ + + int i, j; + + if (!head) { + vcm_err("head is NULL in continuous map.\n"); + goto fail; + } + + if (start_addr < __pa(bootmem_cont)) { + vcm_err("phys start addr (%p) < base (%p)\n", + (void *) start_addr, (void *) __pa(bootmem_cont)); + goto fail; + } + + if ((start_addr + len) >= (__pa(bootmem_cont) + CONT_SZ)) { + vcm_err("requested region (%p + %i) > " + " available region (%p + %i)", + (void *) start_addr, (int) len, + (void *) __pa(bootmem_cont), CONT_SZ); + goto fail; + } + + i = (start_addr - __pa(bootmem_cont))/SZ_4K; + + for (j = 0; j < ARRAY_SIZE(chunk_sizes); ++j) { + while (len/chunk_sizes[j]) { + if (!list_empty(&cont_phys_chunk[i].allocated)) { + vcm_err("chunk %i ( addr %p) already mapped\n", + i, (void *) (start_addr + + (i*chunk_sizes[j]))); + goto fail_free; + } + list_add_tail(&cont_phys_chunk[i].allocated, + &head->allocated); + cont_phys_chunk[i].size_idx = j; + + len -= chunk_sizes[j]; + i += chunk_sizes[j]/SZ_4K; + } + } + + if (len % SZ_4K) { + if (!list_empty(&cont_phys_chunk[i].allocated)) { + vcm_err("chunk %i (addr %p) already mapped\n", + i, (void *) (start_addr + (i*SZ_4K))); + goto fail_free; + } + len -= SZ_4K; + list_add_tail(&cont_phys_chunk[i].allocated, + &head->allocated); + + i++; + } + + return i; + +fail_free: + { + struct phys_chunk *chunk, *tmp; + /* just remove from list, if we're double alloc'ing + we don't want to stamp on the other guy */ + list_for_each_entry_safe(chunk, tmp, &head->allocated, + allocated) { + list_del(&chunk->allocated); + } + } +fail: + return 0; +} + +struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len, + u32 attr) +{ + unsigned long flags; + int ret; + struct physmem *physmem = NULL; + int blocks_allocated; + + spin_lock_irqsave(&vcmlock, flags); + + physmem = kzalloc(sizeof(*physmem), GFP_KERNEL); + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + physmem->memtype = memtype; + physmem->len = len; + physmem->attr = attr; + + INIT_LIST_HEAD(&physmem->alloc_head.allocated); + + if (attr & VCM_PHYS_CONT) { + if (!cont_vcm) { + vcm_err("cont_vcm is NULL\n"); + goto fail2; + } + + physmem->is_cont = 1; + + /* TODO: get attributes */ + physmem->res = __vcm_reserve(cont_vcm, len, 0); + if (physmem->res == 0) { + vcm_err("contiguous space allocation failed\n"); + goto fail2; + } + + /* if we're here we know we have memory, create + the shadow physmem links*/ + blocks_allocated = + vcm_alloc_max_munch_cont( + physmem->res->dev_addr, + len, + &physmem->alloc_head); + + if (blocks_allocated == 0) { + vcm_err("shadow physmem allocation failed\n"); + goto fail3; + } + } else { + blocks_allocated = vcm_alloc_max_munch(len, + &physmem->alloc_head); + if (blocks_allocated == 0) { + vcm_err("physical allocation failed:" + " vcm_alloc_max_munch(%i, %p) ret 0\n", + len, &physmem->alloc_head); + goto fail2; + } + } + + spin_unlock_irqrestore(&vcmlock, flags); + return physmem; + +fail3: + ret = __vcm_unreserve(physmem->res); + if (ret != 0) { + vcm_err("vcm_unreserve(%p) ret %i during cleanup", + (void *) physmem->res, ret); + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + } +fail2: + kfree(physmem); +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +} + + +int vcm_phys_free(struct physmem *physmem) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + if (physmem->is_cont) { + if (physmem->res == 0) { + vcm_err("contiguous reservation is NULL\n"); + goto fail; + } + + ret = vcm_free_max_munch_cont(&physmem->alloc_head); + if (ret != 0) { + vcm_err("failed to free physical blocks:" + " vcm_free_max_munch_cont(%p) ret %i\n", + (void *) &physmem->alloc_head, ret); + goto fail; + } + + ret = __vcm_unreserve(physmem->res); + if (ret != 0) { + vcm_err("failed to free virtual blocks:" + " vcm_unreserve(%p) ret %i\n", + (void *) physmem->res, ret); + goto fail; + } + + } else { + + ret = vcm_alloc_free_blocks(&physmem->alloc_head); + if (ret != 0) { + vcm_err("failed to free physical blocks:" + " vcm_alloc_free_blocks(%p) ret %i\n", + (void *) &physmem->alloc_head, ret); + goto fail; + } + } + + memset(physmem, 0, sizeof(*physmem)); + + kfree(physmem); + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +struct avcm *vcm_assoc(struct vcm *vcm, struct device *dev, u32 attr) +{ + unsigned long flags; + struct avcm *avcm = NULL; + + spin_lock_irqsave(&vcmlock, flags); + + if (!vcm) { + vcm_err("vcm is NULL\n"); + goto fail; + } + + if (!dev) { + vcm_err("dev is NULL\n"); + goto fail; + } + + if (vcm->type == VCM_EXT_KERNEL && !list_empty(&vcm->assoc_head)) { + vcm_err("only one device may be assocoated with a" + " VCM_EXT_KERNEL\n"); + goto fail; + } + + avcm = kzalloc(sizeof(*avcm), GFP_KERNEL); + if (!avcm) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret NULL\n", sizeof(*avcm)); + goto fail; + } + + avcm->dev = dev; + + avcm->vcm = vcm; + avcm->attr = attr; + avcm->is_active = 0; + + INIT_LIST_HEAD(&avcm->assoc_elm); + list_add(&avcm->assoc_elm, &vcm->assoc_head); + + spin_unlock_irqrestore(&vcmlock, flags); + return avcm; + +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +} + + +int vcm_deassoc(struct avcm *avcm) +{ + unsigned long flags; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) { + vcm_err("avcm is NULL\n"); + goto fail; + } + + if (list_empty(&avcm->assoc_elm)) { + vcm_err("nothing to deassociate\n"); + goto fail; + } + + if (avcm->is_active) { + vcm_err("association still activated\n"); + goto fail_busy; + } + + list_del(&avcm->assoc_elm); + + memset(avcm, 0, sizeof(*avcm)); + + kfree(avcm); + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_busy: + spin_unlock_irqrestore(&vcmlock, flags); + return -EBUSY; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_set_assoc_attr(struct avcm *avcm, u32 attr) +{ + return 0; +} + + +int vcm_activate(struct avcm *avcm) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) { + vcm_err("avcm is NULL\n"); + goto fail; + } + + vcm = avcm->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!avcm->dev) { + vcm_err("cannot activate without a device\n"); + goto fail_nodev; + } + + if (avcm->is_active) { + vcm_err("double activate\n"); + goto fail_busy; + } + + if (vcm->type == VCM_DEVICE) { +#ifdef CONFIG_SMMU + int ret = smmu_is_active((struct smmu_dev *) avcm->dev); + if (ret == -1) { + vcm_err("smmu_is_active(%p) ret -1\n", + (void *) avcm->dev); + goto fail_dev; + } + + if (ret == 1) { + vcm_err("SMMU is already active\n"); + goto fail_busy; + } + + /* TODO, pmem check */ + ret = smmu_activate((struct smmu_dev *) avcm->dev); + if (ret != 0) { + vcm_err("smmu_activate(%p) ret %i" + " SMMU failed to activate\n", + (void *) avcm->dev, ret); + goto fail_dev; + } +#else + vcm_err("No SMMU support - cannot activate/deactivate\n"); + goto fail_nodev; +#endif + } + + avcm->is_active = 1; + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + +#ifdef CONFIG_SMMU +fail_dev: + spin_unlock_irqrestore(&vcmlock, flags); + return -1; +#endif +fail_busy: + spin_unlock_irqrestore(&vcmlock, flags); + return -EBUSY; +fail_nodev: + spin_unlock_irqrestore(&vcmlock, flags); + return -ENODEV; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_deactivate(struct avcm *avcm) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) + goto fail; + + vcm = avcm->vcm; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!avcm->dev) { + vcm_err("cannot deactivate without a device\n"); + goto fail; + } + + if (!avcm->is_active) { + vcm_err("double deactivate\n"); + goto fail_nobusy; + } + + if (vcm->type == VCM_DEVICE) { +#ifdef CONFIG_SMMU + int ret = smmu_is_active((struct smmu_dev *) avcm->dev); + if (ret == -1) { + vcm_err("smmu_is_active(%p) ret %i\n", + (void *) avcm->dev, ret); + goto fail_dev; + } + + if (ret == 0) { + vcm_err("double SMMU deactivation\n"); + goto fail_nobusy; + } + + /* TODO, pmem check */ + ret = smmu_deactivate((struct smmu_dev *) avcm->dev); + if (ret != 0) { + vcm_err("smmu_deactivate(%p) ret %i\n", + (void *) avcm->dev, ret); + goto fail_dev; + } +#else + vcm_err("No SMMU support - cannot activate/deactivate\n"); + goto fail; +#endif + } + + avcm->is_active = 0; + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +#ifdef CONFIG_SMMU +fail_dev: + spin_unlock_irqrestore(&vcmlock, flags); + return -1; +#endif +fail_nobusy: + spin_unlock_irqrestore(&vcmlock, flags); + return -ENOENT; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + +struct bound *vcm_create_bound(struct vcm *vcm, size_t len) +{ + return 0; +} + + +int vcm_free_bound(struct bound *bound) +{ + return -1; +} + + +struct res *vcm_reserve_from_bound(struct bound *bound, size_t len, + u32 attr) +{ + return 0; +} + + +size_t vcm_get_bound_start_addr(struct bound *bound) +{ + return 0; +} + + +size_t vcm_get_bound_len(struct bound *bound) +{ + return 0; +} + + +struct physmem *vcm_map_phys_addr(size_t phys, size_t len) +{ + return 0; +} + + +size_t vcm_get_next_phys_addr(struct physmem *physmem, size_t phys, size_t *len) +{ + return 0; +} + +struct res *vcm_get_res(unsigned long dev_addr, struct vcm *vcm) +{ + return 0; +} + + +size_t vcm_translate(size_t src_dev, struct vcm *src_vcm, struct vcm *dst_vcm) +{ + return 0; +} + + +size_t vcm_get_phys_num_res(size_t phys) +{ + return 0; +} + + +struct res *vcm_get_next_phys_res(size_t phys, struct res *res, size_t *len) +{ + return 0; +} + + +size_t vcm_get_pgtbl_pa(struct vcm *vcm) +{ + return 0; +} + + +/* No lock needed, smmu_translate has its own lock */ +size_t vcm_dev_addr_to_phys_addr(struct device *dev, unsigned long dev_addr) +{ +#ifdef CONFIG_SMMU + int ret; + ret = smmu_translate((struct smmu_dev *) dev, dev_addr); + if (ret == -1) + vcm_err("smmu_translate(%p, %p) ret %i\n", + (void *) dev, (void *) dev_addr, ret); + + return ret; +#else + vcm_err("No support for SMMU - manual translation not supported\n"); + return -1; +#endif +} + + +/* No lock needed, bootmem_cont never changes after */ +size_t vcm_get_cont_memtype_pa(enum memtype_t memtype) +{ + if (memtype != VCM_MEMTYPE_0) { + vcm_err("memtype != VCM_MEMTYPE_0\n"); + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont 0\n"); + goto fail; + } + + return (size_t) __pa(bootmem_cont); +fail: + return 0; +} + + +/* No lock needed, constant */ +size_t vcm_get_cont_memtype_len(enum memtype_t memtype) +{ + if (memtype != VCM_MEMTYPE_0) { + vcm_err("memtype != VCM_MEMTYPE_0\n"); + return 0; + } + + return CONT_SZ; +} + +int vcm_hook(struct device *dev, vcm_handler handler, void *data) +{ +#ifdef CONFIG_SMMU + int ret; + + ret = smmu_hook_irpt((struct smmu_dev *) dev, handler, data); + if (ret != 0) + vcm_err("smmu_hook_irpt(%p, %p, %p) ret %i\n", (void *) dev, + (void *) handler, (void *) data, ret); + + return ret; +#else + vcm_err("No support for SMMU - interrupts not supported\n"); + return -1; +#endif +} + + +size_t vcm_hw_ver(struct device *dev) +{ + return 0; +} + + +static int vcm_cont_phys_chunk_init(void) +{ + int i; + int cont_pa; + + if (!cont_phys_chunk) { + vcm_err("cont_phys_chunk 0\n"); + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont 0\n"); + goto fail; + } + + cont_pa = (int) __pa(bootmem_cont); + + for (i = 0; i < CONT_SZ/PAGE_SIZE; ++i) { + cont_phys_chunk[i].pa = (int) cont_pa; cont_pa += PAGE_SIZE; + cont_phys_chunk[i].size_idx = IDX_4K; + INIT_LIST_HEAD(&cont_phys_chunk[i].allocated); + } + + return 0; + +fail: + return -1; +} + + +int vcm_sys_init(void) +{ + int ret; + printk(KERN_INFO "VCM Initialization\n"); + if (!bootmem) { + vcm_err("bootmem is 0\n"); + ret = -1; + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont is 0\n"); + ret = -1; + goto fail; + } + + ret = vcm_setup_tex_classes(); + if (ret != 0) { + printk(KERN_INFO "Could not determine TEX attribute mapping\n"); + ret = -1; + goto fail; + } + + + ret = vcm_alloc_init(__pa(bootmem)); + if (ret != 0) { + vcm_err("vcm_alloc_init(%p) ret %i\n", (void *) __pa(bootmem), + ret); + ret = -1; + goto fail; + } + + cont_phys_chunk = kzalloc(sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE), + GFP_KERNEL); + if (!cont_phys_chunk) { + vcm_err("kzalloc(%lu, GFP_KERNEL) ret 0", + sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE)); + goto fail_free; + } + + /* the address and size will hit our special case unless we + pass an override */ + cont_vcm = vcm_create_flagged(0, __pa(bootmem_cont), CONT_SZ); + if (cont_vcm == 0) { + vcm_err("vcm_create_flagged(0, %p, %i) ret 0\n", + (void *) __pa(bootmem_cont), CONT_SZ); + ret = -1; + goto fail_free2; + } + + ret = vcm_cont_phys_chunk_init(); + if (ret != 0) { + vcm_err("vcm_cont_phys_chunk_init() ret %i\n", ret); + goto fail_free3; + } + + printk(KERN_INFO "VCM Initialization OK\n"); + return 0; + +fail_free3: + ret = __vcm_free(cont_vcm); + if (ret != 0) { + vcm_err("vcm_free(%p) ret %i during failure path\n", + (void *) cont_vcm, ret); + return -1; + } + +fail_free2: + kfree(cont_phys_chunk); + cont_phys_chunk = 0; + +fail_free: + ret = vcm_alloc_destroy(); + if (ret != 0) + vcm_err("vcm_alloc_destroy() ret %i during failure path\n", + ret); + + ret = -1; +fail: + return ret; +} + + +int vcm_sys_destroy(void) +{ + int ret = 0; + + if (!cont_phys_chunk) { + vcm_err("cont_phys_chunk is 0\n"); + return -1; + } + + if (!cont_vcm) { + vcm_err("cont_vcm is 0\n"); + return -1; + } + + ret = __vcm_free(cont_vcm); + if (ret != 0) { + vcm_err("vcm_free(%p) ret %i\n", (void *) cont_vcm, ret); + return -1; + } + + cont_vcm = 0; + + kfree(cont_phys_chunk); + cont_phys_chunk = 0; + + ret = vcm_alloc_destroy(); + if (ret != 0) { + vcm_err("vcm_alloc_destroy() ret %i\n", ret); + return -1; + } + + return ret; +} + +int vcm_init(void) +{ + int ret; + + bootmem = __alloc_bootmem(BOOTMEM_SZ, BOOTMEM_ALIGN, 0); + if (!bootmem) { + vcm_err("segregated block pool alloc failed:" + " __alloc_bootmem(%i, %i, 0)\n", + BOOTMEM_SZ, BOOTMEM_ALIGN); + goto fail; + } + + bootmem_cont = __alloc_bootmem(CONT_SZ, CONT_ALIGN, 0); + if (!bootmem_cont) { + vcm_err("contiguous pool alloc failed:" + " __alloc_bootmem(%i, %i, 0)\n", + CONT_SZ, CONT_ALIGN); + goto fail_free; + } + + ret = vcm_sys_init(); + if (ret != 0) { + vcm_err("vcm_sys_init() ret %i\n", ret); + goto fail_free2; + } + + return 0; + +fail_free2: + free_bootmem(__pa(bootmem_cont), CONT_SZ); +fail_free: + free_bootmem(__pa(bootmem), BOOTMEM_SZ); +fail: + return -1; +}; + +/* Useful for testing, and if VCM is ever unloaded */ +void vcm_exit(void) +{ + int ret; + + if (!bootmem_cont) { + vcm_err("bootmem_cont is 0\n"); + goto fail; + } + + if (!bootmem) { + vcm_err("bootmem is 0\n"); + goto fail; + } + + ret = vcm_sys_destroy(); + if (ret != 0) { + vcm_err("vcm_sys_destroy() ret %i\n", ret); + goto fail; + } + + free_bootmem(__pa(bootmem_cont), CONT_SZ); + free_bootmem(__pa(bootmem), BOOTMEM_SZ); +fail: + return; +} +early_initcall(vcm_init); +module_exit(vcm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Zach Pfeffer "); diff --git a/include/linux/vcm.h b/include/linux/vcm.h new file mode 100644 index 0000000..b95dab5 --- /dev/null +++ b/include/linux/vcm.h @@ -0,0 +1,661 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef _VCM_H_ +#define _VCM_H_ + + +/* All undefined types must be defined using platform specific headers */ + +#include + + +/* + * Virtual contiguous memory (VCM) region primitives. + * + * Current memory mapping software uses a CPU centric management + * model. This makes sense in general, average hardware only contains an + * CPU MMU and possibly a graphics MMU. If every device in the system + * has one or more MMUs a CPU centric MM programming model breaks down. + * + * Looking at mapping from a system-wide perspective reveals a general + * graph problem. Each node that talks to memory, either through an MMU + * or directly (via physical memory) can be thought of as the device end + * of a mapping edge. The other edge is the physical memory that is + * mapped. + * + * In the direct mapped case, it is useful to give the device an + * MMU. This one-to-one MMU allows direct mapped devices to + * participate in graph management, they simply see memory through a + * one-to-one mapping. + * + * The CPU nodes can also be brought under the same mapping + * abstraction with the use of a light overlay on the existing + * VMM. This light overlay brings the VMM's page table abstraction for + * each process and the kernel into the graph management API. + * + * Taken together this system wide approach provides a capability that + * is greater than the sum of its parts by allowing users to reason + * about system wide mapping issues without getting bogged down in CPU + * centric device page table management issues. + */ + + +/* + * Creating, freeing and managing VCMs. + * + * A VCM region is a virtual space that can be reserved from and + * associated with one or more devices. At creation the user can + * specify an offset to start addresses and a length of the entire VCM + * region. Reservations out of a VCM region are always contiguous. + */ + + +/** + * vcm_create() - Create a VCM region + * @start_addr: The starting address of the VCM region. + * @len: The len of the VCM region. This must be at least + * vcm_get_min_page_size() bytes. + * + * A VCM typically abstracts a page table. + * + * All functions in this API are passed and return opaque things + * because the underlying implementations will vary. The goal + * is really graph management. vcm_create() creates the "device end" + * of an edge in the mapping graph. + * + * The return value is non-zero if a VCM has successfully been + * created. It will return zero if a VCM region cannot be created or + * len is invalid. + */ +struct vcm *vcm_create(unsigned long start_addr, size_t len); + + +/** + * vcm_create_from_prebuilt() - Create a VCM region from an existing region + * @ext_vcm_id: An external opaque value that allows the + * implementation to reference an already built table. + * + * The ext_vcm_id will probably reference a page table that's been built + * by the VM. + * + * The platform specific implementation will provide this. + * + * The return value is non-zero if a VCM has successfully been created. + */ +struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id); + + +/** + * vcm_clone() - Clone a VCM + * @vcm: A VCM to clone from. + * + * Perform a VCM "deep copy." The resulting VCM will match the original at + * the point of cloning. Subsequent updates to either VCM will only be + * seen by that VCM. + * + * The return value is non-zero if a VCM has been successfully cloned. + */ +struct vcm *vcm_clone(struct vcm *vcm); + + +/** + * vcm_get_start_addr() - Get the starting address of the VCM region. + * @vcm: The VCM we're interested in getting the starting + * address of. + * + * The return value will be 1 if an error has occurred. + */ +size_t vcm_get_start_addr(struct vcm *vcm); + + +/** + * vcm_get_len() - Get the length of the VCM region. + * @vcm: The VCM we're interested in reading the length from. + * + * The return value will be non-zero for a valid VCM. VCM regions + * cannot have 0 len. + */ +size_t vcm_get_len(struct vcm *vcm); + + +/** + * vcm_free() - Free a VCM. + * @vcm: The VCM we're interested in freeing. + * + * The return value is 0 if the VCM has been freed or: + * -EBUSY The VCM region contains reservations or has been + * associated (active or not) and cannot be freed. + * -EINVAL The vcm argument is invalid. + */ +int vcm_free(struct vcm *vcm); + + +/* + * Creating, freeing and managing reservations out of a VCM. + * + */ + +/** + * vcm_reserve() - Create a reservation from a VCM region. + * @vcm: The VCM region to reserve from. + * @len: The length of the reservation. Must be at least + * vcm_get_min_page_size() bytes. + * @attr: See 'Reservation Attributes'. + * + * A reservation, res_t, is a contiguous range from a VCM region. + * + * The return value is non-zero if a reservation has been successfully + * created. It is 0 if any of the parameters are invalid. + */ +struct res *vcm_reserve(struct vcm *vcm, size_t len, u32 attr); + + +/** + * vcm_reserve_at() - Make a reservation at a given logical location. + * @memtarget: A logical location to start the reservation from. + * @vcm: The VCM region to start the reservation from. + * @len: The length of the reservation. + * @attr: See 'Reservation Attributes'. + * + * The return value is non-zero if a reservation has been successfully + * created. + */ +struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm *vcm, + size_t len, u32 attr); + + +/** + * vcm_get_vcm_from_res() - Return the VCM region of a reservation. + * @res: The reservation to return the VCM region of. + * + * Te return value will be non-zero if the reservation is valid. A valid + * reservation is always associated with a VCM region; there is no such + * thing as an orphan reservation. + */ +struct vcm *vcm_get_vcm_from_res(struct res *res); + + +/** + * vcm_unreserve() - Unreserve the reservation. + * @res: The reservation to unreserve. + * + * The return value will be 0 if the reservation was successfully + * unreserved and: + * -EBUSY The reservation is still backed, + * -EINVAL The vcm argument is invalid. + */ +int vcm_unreserve(struct res *res); + + +/** + * vcm_set_res_attr() - Set attributes of an existing reservation. + * @res: An existing reservation of interest. + * @attr: See 'Reservation Attributes'. + * + * This function can only be used on an existing reservation; there + * are no orphan reservations. All attributes can be set on a existing + * reservation. + * + * The return value will be 0 for a success, otherwise it will be: + * -EINVAL res or attr are invalid. + */ +int vcm_set_res_attr(struct res *res, u32 attr); + + +/** + * vcm_get_num_res() - Return the number of reservations in a VCM region. + * @vcm: The VCM region of interest. + */ +size_t vcm_get_num_res(struct vcm *vcm); + + +/** + * vcm_get_next_res() - Read each reservation one at a time. + * @vcm: The VCM region of interest. + * @res: Contains the last reservation. Pass NULL on the + * first call. + * + * This function works like a foreach reservation in a VCM region. + * + * The return value will be non-zero for each reservation in a VCM. A + * zero indicates no further reservations. + */ +struct res *vcm_get_next_res(struct vcm *vcm, struct res *res); + + +/** + * vcm_res_copy() - Copy len bytes from one reservation to another. + * @to: The reservation to copy to. + * @from: The reservation to copy from. + * @len: The length of bytes to copy. + * + * The return value is the number of bytes copied. + */ +size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, size_t + from_off, size_t len); + + +/** + * vcm_get_min_page_size() - Return the minimum page size supported by + * the architecture. + */ +size_t vcm_get_min_page_size(void); + + +/** + * vcm_back() - Physically back a reservation. + * @res: The reservation containing the virtual contiguous + * region to back. + * @physmem: The physical memory that will back the virtual + * contiguous memory region. + * + * One VCM can be associated with multiple devices. When you vcm_back() + * each association must be active. This is not strictly necessary. It may + * be changed in the future. + * + * This function returns 0 on a successful physical backing. Otherwise + * it returns: + * -EINVAL res or physmem is invalid or res's len + * is different from physmem's len. + * -EAGAIN Try again, one of the devices hasn't been activated. + */ +int vcm_back(struct res *res, struct physmem *physmem); + + +/** + * vcm_unback() - Unback a reservation. + * @res: The reservation to unback. + * + * One VCM can be associated with multiple devices. When you vcm_unback() + * each association must be active. + * + * This function returns 0 on a successful unbacking. Otherwise + * it returns: + * -EINVAL res is invalid. + * -EAGAIN Try again, one of the devices hasn't been activated. + */ +int vcm_unback(struct res *res); + + +/** + * vcm_phys_alloc() - Allocate physical memory for the VCM region. + * @memtype: The memory type to allocate. + * @len: The length of the allocation. + * @attr: See 'Physical Allocation Attributes'. + * + * This function will allocate chunks of memory according to the attr + * it is passed. + * + * The return value is non-zero if physical memory has been + * successfully allocated. + */ +struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len, + u32 attr); + + +/** + * vcm_phys_free() - Free a physical allocation. + * @physmem: The physical allocation to free. + * + * The return value is 0 if the physical allocation has been freed or: + * -EBUSY Their are reservation mapping the physical memory. + * -EINVAL The physmem argument is invalid. + */ +int vcm_phys_free(struct physmem *physmem); + + +/** + * vcm_get_physmem_from_res() - Return a reservation's physmem + * @res: An existing reservation of interest. + * + * The return value will be non-zero on success, otherwise it will be: + * -EINVAL res is invalid + * -ENOMEM res is unbacked + */ +struct physmem *vcm_get_physmem_from_res(struct res *res); + + +/** + * vcm_get_memtype_of_physalloc() - Return the memtype of a reservation. + * @physmem: The physical allocation of interest. + * + * This function returns the memtype of a reservation or VCM_INVALID + * if res is invalid. + */ +enum memtype_t vcm_get_memtype_of_physalloc(struct physmem *physmem); + + +/* + * Associate a VCM with a device, activate that association and remove it. + * + */ + +/** + * vcm_assoc() - Associate a VCM with a device. + * @vcm: The VCM region of interest. + * @dev: The device to associate the VCM with. + * @attr: See 'Association Attributes'. + * + * This function returns non-zero if a association is made. It returns 0 + * if any of its parameters are invalid or VCM_ATTR_VALID is not present. + */ +struct avcm *vcm_assoc(struct vcm *vcm, struct device *dev, u32 attr); + + +/** + * vcm_deassoc() - Deassociate a VCM from a device. + * @avcm: The association we want to break. + * + * The function returns 0 on success or: + * -EBUSY The association is currently activated. + * -EINVAL The avcm parameter is invalid. + */ +int vcm_deassoc(struct avcm *avcm); + + +/** + * vcm_set_assoc_attr() - Set an AVCM's attributes. + * @avcm: The AVCM of interest. + * @attr: The new attr. See 'Association Attributes'. + * + * Every attribute can be set at runtime if an association isn't activated. + * + * This function returns 0 on success or: + * -EBUSY The association is currently activated. + * -EINVAL The avcm parameter is invalid. + */ +int vcm_set_assoc_attr(struct avcm *avcm, u32 attr); + + +/** + * vcm_get_assoc_attr() - Return an AVCM's attributes. + * @avcm: The AVCM of interest. + * + * This function returns 0 on error. + */ +u32 vcm_get_assoc_attr(struct avcm *avcm); + + +/** + * vcm_activate() - Activate an AVCM. + * @avcm: The AVCM to activate. + * + * You have to deactivate, before you activate. + * + * This function returns 0 on success or: + * -EINVAL avcm is invalid + * -ENODEV no device + * -EBUSY device is already active + * -1 hardware failure + */ +int vcm_activate(struct avcm *avcm); + + +/** + * vcm_deactivate() - Deactivate an association. + * @avcm: The AVCM to deactivate. + * + * This function returns 0 on success or: + * -ENOENT avcm is not activate + * -EINVAL avcm is invalid + * -1 Hardware failure + */ +int vcm_deactivate(struct avcm *avcm); + + +/** + * vcm_is_active() - Query if an AVCM is active. + * @avcm: The AVCM of interest. + * + * returns 0 for not active, 1 for active or -EINVAL for error. + * + */ +int vcm_is_active(struct avcm *avcm); + + +/* + * Create, manage and remove a boundary in a VCM. + */ + +/** + * vcm_create_bound() - Create a bound in a VCM. + * @vcm: The VCM that needs a bound. + * @len: The len of the bound. + * + * The allocator picks the virtual addresses of the bound. + * + * This function returns non-zero if a bound was created. + */ +struct bound *vcm_create_bound(struct vcm *vcm, size_t len); + + +/** + * vcm_free_bound() - Free a bound. + * @bound: The bound to remove. + * + * This function returns 0 if bound has been removed or: + * -EBUSY The bound contains reservations and cannot be] + * removed. + * -EINVAL The bound is invalid. + */ +int vcm_free_bound(struct bound *bound); + + +/** + * vcm_reserve_from_bound() - Make a reservation from a bounded area. + * @bound: The bound to reserve from. + * @len: The len of the reservation. + * @attr: See 'Reservation Attributes'. + * + * The return value is non-zero on success. It is 0 if any parameter + * is invalid. + */ +struct res *vcm_reserve_from_bound(struct bound *bound, size_t len, + u32 attr); + + +/** + * vcm_get_bound_start_addr() - Return the starting device address of the bound + * @bound: The bound of interest. + * + * On success this function returns the starting addres of the bound. On error + * it returns: + * 1 bound is invalid. + */ +size_t vcm_get_bound_start_addr(struct bound *bound); + + +/* + * Perform low-level control over VCM regions and reservations. + */ + +/** + * vcm_map_phys_addr() - Produce a physmem from a contiguous + * physical address + * + * @phys: The physical address of the contiguous range. + * @len: The len of the contiguous address range. + * + * Returns non-zero on success, 0 on failure. + */ +struct physmem *vcm_map_phys_addr(phys_addr_t phys, size_t len); + + +/** + * vcm_get_next_phys_addr() - Get the next physical addr and len of a + * physmem. + * @res: The physmem of interest. + * @phys: The current physical address. Set this to NULL to + * start the iteration. + * @len: An output: the len of the next physical segment. + * + * physmem's may contain physically discontiguous sections. This + * function returns the next physical address and len. Pass NULL to + * phys to get the first physical address. The len of the physical + * segment is returned in *len. + * + * Returns 0 if there is no next physical address. + */ +size_t vcm_get_next_phys_addr(struct physmem *physmem, phys_addr_t phys, + size_t *len); + + +/** + * vcm_get_res() - Return the reservation from a device address and a VCM + * @dev_addr: The device address of interest. + * @vcm: The VCM that contains the reservation + * + * This function returns 0 if there is no reservation whose device + * address is dev_addr. + */ +struct res *vcm_get_res(unsigned long dev_addr, struct vcm *vcm); + + +/** + * vcm_translate() - Translate from one device address to another. + * @src_dev: The source device address. + * @src_vcm: The source VCM region. + * @dst_vcm: The destination VCM region. + * + * Derive the device address from a VCM region that maps the same physical + * memory as a device address from another VCM region. + * + * On success this function returns the device address of a translation. On + * error it returns: + * 1 res is invalid. + */ +size_t vcm_translate(size_t src_dev, struct vcm *src_vcm, + struct vcm *dst_vcm); + + +/** + * vcm_get_phys_num_res() - Return the number of reservations mapping a + * physical address. + * @phys: The physical address to read. + */ +size_t vcm_get_phys_num_res(size_t phys); + + +/** + * vcm_get_next_phys_res() - Return the next reservation mapped to a physical + * address. + * @phys: The physical address to map. + * @res: The starting reservation. Set this to NULL for the first + * reservation. + * @len: The virtual length of the reservation + * + * This function returns 0 for the last reservation or no reservation. + */ +struct res *vcm_get_next_phys_res(size_t phys, struct res *res, size_t *len); + + +/** + * vcm_get_pgtbl_pa() - Return the physcial address of a VCM's page table. + * @vcm: The VCM region of interest. + * + * This function returns non-zero on success. + */ +size_t vcm_get_pgtbl_pa(struct vcm *vcm); + + +/** + * vcm_get_cont_memtype_pa() - Return the phys base addr of a memtype's + * first contiguous region. + * @memtype: The memtype of interest. + * + * This function returns non-zero on success. A zero return indicates that + * the given memtype does not have a contiguous region or that the memtype + * is invalid. + */ +size_t vcm_get_cont_memtype_pa(enum memtype_t memtype); + + +/** + * vcm_get_cont_memtype_len() - Return the len of a memtype's + * first contiguous region. + * @memtype: The memtype of interest. + * + * This function returns non-zero on success. A zero return indicates that + * the given memtype does not have a contiguous region or that the memtype + * is invalid. + */ +size_t vcm_get_cont_memtype_len(enum memtype_t memtype); + + +/** + * vcm_dev_addr_to_phys_addr() - Perform a device address page-table lookup. + * @dev: The device that has the table. + * @dev_addr: The device address to map. + * + * This function returns the pa of a va from a device's page-table. It will + * fault if the dev_addr is not mapped. + */ +size_t vcm_dev_addr_to_phys_addr(struct device *dev, unsigned long dev_addr); + + +/* + * Fault Hooks + * + * vcm_hook() + */ + +/** + * vcm_hook() - Add a fault handler. + * @dev: The device. + * @handler: The handler. + * @data: A private piece of data that will get passed to the + * handler. + * + * This function returns 0 for a successful registration or: + * -EINVAL The arguments are invalid. + */ +int vcm_hook(struct device *dev, vcm_handler handler, void *data); + + +/* + * Low level, platform agnostic, HW control. + * + * vcm_hw_ver() + */ + +/** + * vcm_hw_ver() - Return the hardware version of a device, if it has one. + * @dev: The device. + */ +size_t vcm_hw_ver(struct device *dev); + + +/* bring-up init, destroy */ +int vcm_sys_init(void); +int vcm_sys_destroy(void); + +#endif /* _VCM_H_ */ + diff --git a/include/linux/vcm_types.h b/include/linux/vcm_types.h new file mode 100644 index 0000000..671e80f --- /dev/null +++ b/include/linux/vcm_types.h @@ -0,0 +1,338 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef VCM_TYPES_H +#define VCM_TYPES_H + +#include +#include +#include +#include +#include +#include +#include + +/* + * Reservation Attributes + * + * Used in vcm_reserve(), vcm_reserve_at(), vcm_set_res_attr() and + * vcm_reserve_bound(). + * + * VCM_READ Specifies that the reservation can be read. + * VCM_WRITE Specifies that the reservation can be written. + * VCM_EXECUTE Specifies that the reservation can be executed. + * VCM_USER Specifies that this reservation is used for + * userspace access. + * VCM_SUPERVISOR Specifies that this reservation is used for + * supervisor access. + * VCM_SECURE Specifies that the target of the reservation is + * secure. The usage of this setting is TBD. + * + * Caching behavior as a 4 bit field: + * VCM_NOTCACHED The VCM region is not cached. + * VCM_INNER_WB_WA The VCM region is inner cached + * and is write-back and write-allocate. + * VCM_INNER_WT_NWA The VCM region is inner cached and is + * write-through and no-write-allocate. + * VCM_INNER_WB_NWA The VCM region is inner cached and is + * write-back and no-write-allocate. + * VCM_OUTER_WB_WA The VCM region is outer cached and is + * write-back and write-allocate. + * VCM_OUTER_WT_NWA The VCM region is outer cached and is + * write-through and no-write-allocate. + * VCM_OUTER_WB_NWA The VCM region is outer cached and is + * write-back and no-write-allocate. + * VCM_WB_WA The VCM region is cached and is write + * -back and write-allocate. + * VCM_WT_NWA The VCM region is cached and is write + * -through and no-write-allocate. + * VCM_WB_NWA The VCM region is cached and is write + * -back and no-write-allocate. + */ + +#define VCM_CACHE_POLICY (0xF << 0) + +#define VCM_READ (1UL << 9) +#define VCM_WRITE (1UL << 8) +#define VCM_EXECUTE (1UL << 7) +#define VCM_USER (1UL << 6) +#define VCM_SUPERVISOR (1UL << 5) +#define VCM_SECURE (1UL << 4) +#define VCM_NOTCACHED (0UL << 0) +#define VCM_WB_WA (1UL << 0) +#define VCM_WB_NWA (2UL << 0) +#define VCM_WT (3UL << 0) + + +/* + * Physical Allocation Attributes + * + * Used in vcm_phys_alloc(). + * + * Alignment as a power of 2 starting at 4 KB. 5 bit field. + * 1 = 4KB, 2 = 8KB, etc. + * + * Specifies that the reservation should have the + * alignment specified. + * + * VCM_4KB Specifies that the reservation should use 4KB pages. + * VCM_64KB Specifies that the reservation should use 64KB pages. + * VCM_1MB specifies that the reservation should use 1MB pages. + * VCM_ALL Specifies that the reservation should use all + * available page sizes. + * VCM_PHYS_CONT Specifies that a reservation should be backed with + * physically contiguous memory. + * VCM_COHERENT Specifies that the reservation must be kept coherent + * because it's shared. + */ + +#define VCM_ALIGNMENT_MASK (0x1FUL << 6) /* 5-bit field */ +#define VCM_4KB (1UL << 5) +#define VCM_64KB (1UL << 4) +#define VCM_1MB (1UL << 3) +#define VCM_ALL (1UL << 2) +#define VCM_PAGE_SEL_MASK (0xFUL << 2) +#define VCM_PHYS_CONT (1UL << 1) +#define VCM_COHERENT (1UL << 0) + + +#define SHIFT_4KB (12) + +#define ALIGN_REQ_BYTES(attr) (1UL << (((attr & VCM_ALIGNMENT_MASK) >> 6) + 12)) +/* set the alignment in pow 2, 0 = 4KB */ +#define SET_ALIGN_REQ_BYTES(attr, align) \ + ((attr & ~VCM_ALIGNMENT_MASK) | ((align << 6) & VCM_ALIGNMENT_MASK)) + +/* + * Association Attributes + * + * Used in vcm_assoc(), vcm_set_assoc_attr(). + * + * VCM_USE_LOW_BASE Use the low base register. + * VCM_USE_HIGH_BASE Use the high base register. + * + * VCM_SPLIT A 5 bit field that defines the + * high/low split. This value defines + * the number of 0's left-filled into the + * split register. Addresses that match + * this will use VCM_USE_LOW_BASE + * otherwise they'll use + * VCM_USE_HIGH_BASE. An all 0's value + * directs all translations to + * VCM_USE_LOW_BASE. + */ + +#define VCM_SPLIT (1UL << 3) +#define VCM_USE_LOW_BASE (1UL << 2) +#define VCM_USE_HIGH_BASE (1UL << 1) + +/* + * External VCMs + * + * Used in vcm_create_from_prebuilt() + * + * Externally created VCM IDs for creating kernel and user space + * mappings to VCMs and kernel and user space buffers out of + * VCM_MEMTYPE_0,1,2, etc. + * + */ +#define VCM_PREBUILT_KERNEL 1 +#define VCM_PREBUILT_USER 2 + +/** + * enum memtarget_t - A logical location in a VCM. + * @vcm_start: Indicates the start of a VCM_REGION. + */ +enum memtarget_t { + VCM_START +}; + + +/** + * enum memtype_t - A logical location in a VCM. + * @vcm_memtype_0: Generic memory type 0 + * @vcm_memtype_1: Generic memory type 1 + * @vcm_memtype_2: Generic memory type 2 + * + * A memtype encapsulates a platform specific memory arrangement. The + * memtype needn't refer to a single type of memory, it can refer to a + * set of memories that can back a reservation. + * + */ +enum memtype_t { + VCM_INVALID, + VCM_MEMTYPE_0, + VCM_MEMTYPE_1, + VCM_MEMTYPE_2, +}; + + +/** + * vcm_handler - The signature of the fault hook. + * @dev: The device id of the faulting device. + * @data: The generic data pointer. + * @fault_data: System specific common fault data. + * + * The handler should return 0 for success. This indicates that the + * fault was handled. A non-zero return value is an error and will be + * propagated up the stack. + */ +typedef int (*vcm_handler)(size_t dev, void *data, void *fault_data); + + +/** + * enum vcm_type - The type of VCM. + * @vcm_memtype_0: Generic memory type 0 + * @vcm_memtype_1: Generic memory type 1 + * @vcm_memtype_2: Generic memory type 2 + * + * A memtype encapsulates a platform specific memory arrangement. The + * memtype needn't refer to a single type of memory, it can refer to a + * set of memories that can back a reservation. + * + */ +enum vcm_type { + VCM_DEVICE, + VCM_EXT_KERNEL, + VCM_EXT_USER, + VCM_ONE_TO_ONE, +}; + +/** + * struct vcm - A Virtually Contiguous Memory region. + * @start_addr: The starting address of the VCM region. + * @len: The len of the VCM region. This must be at least + * vcm_min() bytes. + */ +struct vcm { + /* public */ + unsigned long start_addr; + size_t len; + + + /* private */ + enum vcm_type type; + + struct device *dev; /* opaque device control */ + + /* allocator dependent */ + struct gen_pool *pool; + + struct list_head res_head; + + /* this will be a very short list */ + struct list_head assoc_head; +}; + +/** + * struct avcm - A VCM to device association + * @vcm: The VCM region of interest. + * @dev: The device to associate the VCM with. + * @attr: See 'Association Attributes'. + */ +struct avcm { + /* public */ + struct vcm *vcm; + struct device *dev; + u32 attr; + + /* private */ + struct list_head assoc_elm; + + int is_active; /* is this particular association active */ +}; + + +/** + * struct bound - A boundary to reserve from in a VCM region. + * @vcm: The VCM that needs a bound. + * @len: The len of the bound. + */ +struct bound { + struct vcm *vcm; + size_t len; +}; + + +/** + * struct physmem - A physical memory allocation. + * @memtype: The memory type of the VCM region. + * @len: The len of the physical memory allocation. + * @attr: See 'Physical Allocation Attributes'. + * + */ +struct physmem { + /* public */ + enum memtype_t memtype; + size_t len; +b u32 attr; + + /* private */ + struct phys_chunk alloc_head; + + /* if the physmem is cont then use the built in VCM */ + int is_cont; + struct res *res; +}; + + +/** + * struct res - A reservation in a VCM region. + * @vcm: The VCM region to reserve from. + * @len: The length of the reservation. Must be at least vcm_min() + * bytes. + * @attr: See 'Reservation Attributes'. + * @dev_addr: The device-side address. + */ +struct res { + /* public */ + struct vcm *vcm; + size_t len; + u32 attr; + unsigned long dev_addr; + + + /* private */ + struct physmem *physmem; + + /* allocator dependent */ + size_t alignment_req; + size_t aligned_len; + unsigned long ptr; + + struct list_head res_elm; + + /* type VCM_EXT_KERNEL */ + struct vm_struct *vm_area; + int mapped; +}; + +extern int chunk_sizes[NUM_CHUNK_SIZES]; + +#endif /* VCM_TYPES_H */ From patchwork Tue Jul 6 15:42:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zach Pfeffer X-Patchwork-Id: 110437 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o66FhXQ8009943 for ; Tue, 6 Jul 2010 15:43:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754450Ab0GFPnO (ORCPT ); Tue, 6 Jul 2010 11:43:14 -0400 Received: from wolverine02.qualcomm.com ([199.106.114.251]:55829 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752287Ab0GFPmn (ORCPT ); Tue, 6 Jul 2010 11:42:43 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6034"; a="46472227" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 06 Jul 2010 08:42:41 -0700 Received: from localhost.localdomain (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 67B8A10004C4; Tue, 6 Jul 2010 08:42:43 -0700 (PDT) From: Zach Pfeffer To: mel@csn.ul.ie Cc: linux-arch@vger.kernel.org, dwalker@codeaurora.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, Zach Pfeffer Subject: [RFC 2/3] mm: iommu: A physical allocator for the VCMM Date: Tue, 6 Jul 2010 08:42:35 -0700 Message-Id: <1278430956-2260-2-git-send-email-zpfeffer@codeaurora.org> X-Mailer: git-send-email 1.7.0.2 In-Reply-To: <1278430956-2260-1-git-send-email-zpfeffer@codeaurora.org> References: <1278430956-2260-1-git-send-email-zpfeffer@codeaurora.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 06 Jul 2010 15:43:34 +0000 (UTC) diff --git a/arch/arm/mm/vcm_alloc.c b/arch/arm/mm/vcm_alloc.c new file mode 100644 index 0000000..e592e71 --- /dev/null +++ b/arch/arm/mm/vcm_alloc.c @@ -0,0 +1,425 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include + +/* Amount of memory managed by VCM */ +#define TOTAL_MEM_SIZE SZ_32M + +static unsigned int base_pa = 0x80000000; +int basicalloc_init; + +int chunk_sizes[NUM_CHUNK_SIZES] = {SZ_1M, SZ_64K, SZ_4K}; +int init_num_chunks[] = { + (TOTAL_MEM_SIZE/2) / SZ_1M, + (TOTAL_MEM_SIZE/4) / SZ_64K, + (TOTAL_MEM_SIZE/4) / SZ_4K +}; +#define LAST_SZ() (ARRAY_SIZE(chunk_sizes) - 1) + +#define vcm_alloc_err(a, ...) \ + pr_err("ERROR %s %i " a, __func__, __LINE__, ##__VA_ARGS__) + +struct phys_chunk_head { + struct list_head head; + int num; +}; + +struct phys_mem { + struct phys_chunk_head heads[ARRAY_SIZE(chunk_sizes)]; +} phys_mem; + +static int is_allocated(struct list_head *allocated) +{ + /* This should not happen under normal conditions */ + if (!allocated) { + vcm_alloc_err("no allocated\n"); + return 0; + } + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + return 0; + } + return !list_empty(allocated); +} + +static int count_allocated_size(enum chunk_size_idx idx) +{ + int cnt = 0; + struct phys_chunk *chunk, *tmp; + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + return 0; + } + + list_for_each_entry_safe(chunk, tmp, + &phys_mem.heads[idx].head, list) { + if (is_allocated(&chunk->allocated)) + cnt++; + } + + return cnt; +} + + +int vcm_alloc_get_mem_size(void) +{ + return TOTAL_MEM_SIZE; +} +EXPORT_SYMBOL(vcm_alloc_get_mem_size); + + +int vcm_alloc_blocks_avail(enum chunk_size_idx idx) +{ + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + return 0; + } + + return phys_mem.heads[idx].num; +} +EXPORT_SYMBOL(vcm_alloc_blocks_avail); + + +int vcm_alloc_get_num_chunks(void) +{ + return ARRAY_SIZE(chunk_sizes); +} +EXPORT_SYMBOL(vcm_alloc_get_num_chunks); + + +int vcm_alloc_all_blocks_avail(void) +{ + int i; + int cnt = 0; + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) + cnt += vcm_alloc_blocks_avail(i); + return cnt; +} +EXPORT_SYMBOL(vcm_alloc_all_blocks_avail); + + +int vcm_alloc_count_allocated(void) +{ + int i; + int cnt = 0; + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) + cnt += count_allocated_size(i); + return cnt; +} +EXPORT_SYMBOL(vcm_alloc_count_allocated); + + +void vcm_alloc_print_list(int just_allocated) +{ + int i; + struct phys_chunk *chunk, *tmp; + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + return; + } + + for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) { + if (list_empty(&phys_mem.heads[i].head)) + continue; + list_for_each_entry_safe(chunk, tmp, + &phys_mem.heads[i].head, list) { + if (just_allocated && !is_allocated(&chunk->allocated)) + continue; + + printk(KERN_INFO "pa = %#x, size = %#x\n", + chunk->pa, chunk_sizes[chunk->size_idx]); + } + } +} +EXPORT_SYMBOL(vcm_alloc_print_list); + + +int vcm_alloc_idx_to_size(int idx) +{ + return chunk_sizes[idx]; +} +EXPORT_SYMBOL(vcm_alloc_idx_to_size); + + +int vcm_alloc_destroy(void) +{ + int i; + struct phys_chunk *chunk, *tmp; + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + return -1; + } + + /* can't destroy a space that has allocations */ + if (vcm_alloc_count_allocated()) { + vcm_alloc_err("allocations still present\n"); + return -1; + } + for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) { + + if (list_empty(&phys_mem.heads[i].head)) + continue; + list_for_each_entry_safe(chunk, tmp, + &phys_mem.heads[i].head, list) { + list_del(&chunk->list); + memset(chunk, 0, sizeof(*chunk)); + kfree(chunk); + } + } + + basicalloc_init = 0; + + return 0; +} +EXPORT_SYMBOL(vcm_alloc_destroy); + + +int vcm_alloc_init(unsigned int set_base_pa) +{ + int i = 0, j = 0; + struct phys_chunk *chunk; + int pa; + + if (set_base_pa) + base_pa = set_base_pa; + + pa = base_pa; + + /* no double inits */ + if (basicalloc_init) { + vcm_alloc_err("double basicalloc_init\n"); + BUG(); + return -1; + } + + /* separate out to ensure good cleanup */ + for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) { + INIT_LIST_HEAD(&phys_mem.heads[i].head); + phys_mem.heads[i].num = 0; + } + + for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) { + for (j = 0; j < init_num_chunks[i]; ++j) { + chunk = kzalloc(sizeof(*chunk), GFP_KERNEL); + if (!chunk) { + vcm_alloc_err("null chunk\n"); + goto fail; + } + chunk->pa = pa; pa += chunk_sizes[i]; + chunk->size_idx = i; + INIT_LIST_HEAD(&chunk->allocated); + list_add_tail(&chunk->list, &phys_mem.heads[i].head); + phys_mem.heads[i].num++; + } + } + + basicalloc_init = 1; + return 0; +fail: + vcm_alloc_destroy(); + return -1; +} +EXPORT_SYMBOL(vcm_alloc_init); + + +int vcm_alloc_free_blocks(struct phys_chunk *alloc_head) +{ + struct phys_chunk *chunk, *tmp; + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + goto fail; + } + + if (!alloc_head) { + vcm_alloc_err("no alloc_head\n"); + goto fail; + } + + list_for_each_entry_safe(chunk, tmp, &alloc_head->allocated, + allocated) { + list_del_init(&chunk->allocated); + phys_mem.heads[chunk->size_idx].num++; + } + + return 0; +fail: + return -1; +} +EXPORT_SYMBOL(vcm_alloc_free_blocks); + + +int vcm_alloc_num_blocks(int num, + enum chunk_size_idx idx, /* chunk size */ + struct phys_chunk *alloc_head) +{ + struct phys_chunk *chunk; + int num_allocated = 0; + + if (!basicalloc_init) { + vcm_alloc_err("no basicalloc_init\n"); + goto fail; + } + + if (!alloc_head) { + vcm_alloc_err("no alloc_head\n"); + goto fail; + } + + if (list_empty(&phys_mem.heads[idx].head)) { + vcm_alloc_err("list is empty\n"); + goto fail; + } + + if (vcm_alloc_blocks_avail(idx) < num) { + vcm_alloc_err("not enough blocks? num=%d\n", num); + goto fail; + } + + list_for_each_entry(chunk, &phys_mem.heads[idx].head, list) { + if (num_allocated == num) + break; + if (is_allocated(&chunk->allocated)) + continue; + + list_add_tail(&chunk->allocated, &alloc_head->allocated); + phys_mem.heads[idx].num--; + num_allocated++; + } + return num_allocated; +fail: + return 0; +} +EXPORT_SYMBOL(vcm_alloc_num_blocks); + + +int vcm_alloc_max_munch(int len, + struct phys_chunk *alloc_head) +{ + int i; + + int blocks_req = 0; + int block_residual = 0; + int blocks_allocated = 0; + + int ba = 0; + + if (!basicalloc_init) { + vcm_alloc_err("basicalloc_init is 0\n"); + goto fail; + } + + if (!alloc_head) { + vcm_alloc_err("alloc_head is NULL\n"); + goto fail; + } + + for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) { + blocks_req = len / chunk_sizes[i]; + block_residual = len % chunk_sizes[i]; + + len = block_residual; /* len left */ + if (blocks_req) { + int blocks_available = 0; + int blocks_diff = 0; + int bytes_diff = 0; + + blocks_available = vcm_alloc_blocks_avail(i); + if (blocks_available < blocks_req) { + blocks_diff = + (blocks_req - blocks_available); + bytes_diff = + blocks_diff * chunk_sizes[i]; + + /* add back in the rest */ + len += bytes_diff; + } else { + /* got all the blocks I need */ + blocks_available = + (blocks_available > blocks_req) + ? blocks_req : blocks_available; + } + + ba = vcm_alloc_num_blocks(blocks_available, i, + alloc_head); + + if (ba != blocks_available) { + vcm_alloc_err("blocks allocated (%i) !=" + " blocks_available (%i):" + " chunk size = %#x," + " alloc_head = %p\n", + ba, blocks_available, + i, (void *) alloc_head); + goto fail; + } + blocks_allocated += blocks_available; + } + } + + if (len) { + int blocks_available = 0; + + blocks_available = vcm_alloc_blocks_avail(LAST_SZ()); + + if (blocks_available > 1) { + ba = vcm_alloc_num_blocks(1, LAST_SZ(), alloc_head); + if (ba != 1) { + vcm_alloc_err("blocks allocated (%i) !=" + " blocks_available (%i):" + " chunk size = %#x," + " alloc_head = %p\n", + ba, 1, + LAST_SZ(), + (void *) alloc_head); + goto fail; + } + blocks_allocated += 1; + } else { + vcm_alloc_err("blocks_available (%#x) <= 1\n", + blocks_available); + goto fail; + } + } + + return blocks_allocated; +fail: + vcm_alloc_free_blocks(alloc_head); + return 0; +} +EXPORT_SYMBOL(vcm_alloc_max_munch); diff --git a/include/linux/vcm_alloc.h b/include/linux/vcm_alloc.h new file mode 100644 index 0000000..e3e3b31 --- /dev/null +++ b/include/linux/vcm_alloc.h @@ -0,0 +1,70 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef VCM_ALLOC_H +#define VCM_ALLOC_H + +#include + +#define NUM_CHUNK_SIZES 3 + +enum chunk_size_idx { + IDX_1M = 0, + IDX_64K, + IDX_4K +}; + +struct phys_chunk { + struct list_head list; + struct list_head allocated; /* used to record is allocated */ + + struct list_head refers_to; + + /* TODO: change to unsigned long */ + int pa; + int size_idx; +}; + +int vcm_alloc_get_mem_size(void); +int vcm_alloc_blocks_avail(enum chunk_size_idx idx); +int vcm_alloc_get_num_chunks(void); +int vcm_alloc_all_blocks_avail(void); +int vcm_alloc_count_allocated(void); +void vcm_alloc_print_list(int just_allocated); +int vcm_alloc_idx_to_size(int idx); +int vcm_alloc_destroy(void); +int vcm_alloc_init(unsigned int set_base_pa); +int vcm_alloc_free_blocks(struct phys_chunk *alloc_head); +int vcm_alloc_num_blocks(int num, + enum chunk_size_idx idx, /* chunk size */ + struct phys_chunk *alloc_head); +int vcm_alloc_max_munch(int len, + struct phys_chunk *alloc_head); + +#endif /* VCM_ALLOC_H */ From patchwork Sun Aug 8 10:18:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 118221 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o78AGgno010115 for ; Sun, 8 Aug 2010 10:18:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752795Ab0HHKSf (ORCPT ); Sun, 8 Aug 2010 06:18:35 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:39592 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751645Ab0HHKSe (ORCPT ); Sun, 8 Aug 2010 06:18:34 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o78AISEL011812 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 8 Aug 2010 05:18:30 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o78AINHu016021; Sun, 8 Aug 2010 15:48:23 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o78AINI3027802; Sun, 8 Aug 2010 15:48:23 +0530 Received: (from a0393909@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o78AIMUQ027799; Sun, 8 Aug 2010 15:48:22 +0530 From: Santosh Shilimkar To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Santosh Shilimkar , davinci-linux-open-source@linux.davincidsp.com, Kevin Hilman Subject: [PATCH 3/3] davinci: Map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE Date: Sun, 8 Aug 2010 15:48:22 +0530 Message-Id: <1281262702-27732-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 08 Aug 2010 10:18:36 +0000 (UTC) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3834781..e7bd2ad 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -767,8 +767,7 @@ static struct map_desc dm355_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00010000), .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index a146849..5dee032 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -967,8 +967,7 @@ static struct map_desc dm365_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00010000), .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 7ad1520..5112d51 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -651,8 +651,7 @@ static struct map_desc dm644x_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00008000), .length = SZ_16K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 9404565..97078f4 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -735,8 +735,7 @@ static struct map_desc dm646x_io_desc[] = { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00010000), .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, + .type = MT_MEMORY_NONCACHED, }, }; From patchwork Sun Aug 8 10:18:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 118220 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o78AGgnm010115 for ; Sun, 8 Aug 2010 10:18:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752736Ab0HHKSO (ORCPT ); Sun, 8 Aug 2010 06:18:14 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:54822 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751645Ab0HHKSN (ORCPT ); Sun, 8 Aug 2010 06:18:13 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o78AI5YK029367 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 8 Aug 2010 05:18:07 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o78AI42G016014; Sun, 8 Aug 2010 15:48:04 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o78AI4hs027720; Sun, 8 Aug 2010 15:48:04 +0530 Received: (from a0393909@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o78AI4sJ027718; Sun, 8 Aug 2010 15:48:04 +0530 From: Santosh Shilimkar To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Santosh Shilimkar Subject: [PATCH 2/3] omap1/2/3/4: map only available SRAM Date: Sun, 8 Aug 2010 15:48:04 +0530 Message-Id: <1281262684-27684-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 08 Aug 2010 10:18:15 +0000 (UTC) diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 226b2e8..10b3b4c 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -220,20 +220,7 @@ void __init omap_map_sram(void) if (omap_sram_size == 0) return; - if (cpu_is_omap24xx()) { - omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA; - - base = OMAP2_SRAM_PA; - base = ROUND_DOWN(base, PAGE_SIZE); - omap_sram_io_desc[0].pfn = __phys_to_pfn(base); - } - if (cpu_is_omap34xx()) { - omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA; - base = OMAP3_SRAM_PA; - base = ROUND_DOWN(base, PAGE_SIZE); - omap_sram_io_desc[0].pfn = __phys_to_pfn(base); - /* * SRAM must be marked as non-cached on OMAP3 since the * CORE DPLL M2 divider change code (in SRAM) runs with the @@ -244,13 +231,11 @@ void __init omap_map_sram(void) omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; } - if (cpu_is_omap44xx()) { - omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA; - base = OMAP4_SRAM_PA; - base = ROUND_DOWN(base, PAGE_SIZE); - omap_sram_io_desc[0].pfn = __phys_to_pfn(base); - } - omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ + omap_sram_io_desc[0].virtual = omap_sram_base; + base = omap_sram_start; + base = ROUND_DOWN(base, PAGE_SIZE); + omap_sram_io_desc[0].pfn = __phys_to_pfn(base); + omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE); iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", From patchwork Tue Jun 8 20:41:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aguirre Rodriguez, Sergio Alberto" X-Patchwork-Id: 105027 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o58KfhhO016049 for ; Tue, 8 Jun 2010 20:41:43 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756407Ab0FHUlh (ORCPT ); Tue, 8 Jun 2010 16:41:37 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:40775 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756400Ab0FHUlh (ORCPT ); Tue, 8 Jun 2010 16:41:37 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o58KfUpg013434 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 8 Jun 2010 15:41:30 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o58KfT3m017776; Tue, 8 Jun 2010 15:41:29 -0500 (CDT) Received: from localhost (dtx0091359-ubuntu-1.am.dhcp.ti.com [128.247.75.89]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o58KfTP04705; Tue, 8 Jun 2010 15:41:29 -0500 (CDT) From: Sergio Aguirre To: Tony Lindgren Cc: linux-omap@vger.kernel.org, Matt Fleming , Sergio Aguirre Subject: [PATCH] omap_hsmmc: Remove unused state variable Date: Tue, 8 Jun 2010 15:41:40 -0500 Message-Id: <1276029700-27900-1-git-send-email-saaguirre@ti.com> X-Mailer: git-send-email 1.6.3.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 08 Jun 2010 20:41:43 +0000 (UTC) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b032828..d50e917 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2272,7 +2272,6 @@ static int omap_hsmmc_suspend(struct device *dev) int ret = 0; struct platform_device *pdev = to_platform_device(dev); struct omap_hsmmc_host *host = platform_get_drvdata(pdev); - pm_message_t state = PMSG_SUSPEND; /* unused by MMC core */ if (host && host->suspended) return 0; From patchwork Wed May 5 18:45:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jan sebastien X-Patchwork-Id: 97166 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45IgSxn024057 for ; Wed, 5 May 2010 18:45:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757987Ab0EESpJ (ORCPT ); Wed, 5 May 2010 14:45:09 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:42490 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757809Ab0EESpI (ORCPT ); Wed, 5 May 2010 14:45:08 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o45Iiutv010082 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 5 May 2010 13:44:56 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o45IipCM028118; Wed, 5 May 2010 13:44:54 -0500 (CDT) From: Sebastien Jan To: netdev@vger.kernel.org Cc: linux-omap@vger.kernel.org, Abraham Arce , Ben Dooks , Tristram.Ha@micrel.com, Sebastien Jan Subject: [PATCH 1/4 v2] ks8851: Add caching of CCR register Date: Wed, 5 May 2010 20:45:52 +0200 Message-Id: <1273085155-1260-2-git-send-email-s-jan@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1273085155-1260-1-git-send-email-s-jan@ti.com> References: <1273085155-1260-1-git-send-email-s-jan@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 18:45:11 +0000 (UTC) diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c index 9e9f9b3..a84e500 100644 --- a/drivers/net/ks8851.c +++ b/drivers/net/ks8851.c @@ -76,7 +76,9 @@ union ks8851_tx_hdr { * @msg_enable: The message flags controlling driver output (see ethtool). * @fid: Incrementing frame id tag. * @rc_ier: Cached copy of KS_IER. + * @rc_ccr: Cached copy of KS_CCR. * @rc_rxqcr: Cached copy of KS_RXQCR. + * @eeprom_size: Companion eeprom size in Bytes, 0 if no eeprom * * The @lock ensures that the chip is protected when certain operations are * in progress. When the read or write packet transfer is in progress, most @@ -107,6 +109,8 @@ struct ks8851_net { u16 rc_ier; u16 rc_rxqcr; + u16 rc_ccr; + u16 eeprom_size; struct mii_if_info mii; struct ks8851_rxctrl rxctrl; @@ -1279,6 +1283,14 @@ static int __devinit ks8851_probe(struct spi_device *spi) goto err_id; } + /* cache the contents of the CCR register for EEPROM, etc. */ + ks->rc_ccr = ks8851_rdreg16(ks, KS_CCR); + + if (ks->rc_ccr & CCR_EEPROM) + ks->eeprom_size = 128; + else + ks->eeprom_size = 0; + ks8851_read_selftest(ks); ks8851_init_mac(ks); From patchwork Mon Aug 2 15:49:51 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 116555 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FoK9M018194 for ; Mon, 2 Aug 2010 15:50:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753933Ab0HBPuO (ORCPT ); Mon, 2 Aug 2010 11:50:14 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:48570 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753706Ab0HBPuI (ORCPT ); Mon, 2 Aug 2010 11:50:08 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o72Fo3P4008063 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 2 Aug 2010 10:50:06 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o72FntD4011550; Mon, 2 Aug 2010 21:20:01 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, Sukumar Ghorai , Vimal Singh Subject: [PATCH v4 3/4] omap: nand: ecc layout select from board file Date: Mon, 2 Aug 2010 21:19:51 +0530 Message-Id: <1280764192-15053-4-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> References: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:50:20 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 4871d71..5f74c8f 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -144,7 +144,8 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) { board_nand_data.cs = cs; board_nand_data.parts = nand_parts; - board_nand_data.nr_parts = nr_parts; + board_nand_data.nr_parts = nr_parts; + board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DIFF_LAYOUT; gpmc_nand_init(&board_nand_data); } diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 5e69463..2e026e4 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -23,6 +23,12 @@ struct omap_nand_platform_data { int gpmc_irq; unsigned long phys_base; int devsize; + enum { + OMAP_ECC_HAMMING_CODE_DIFF_LAYOUT = 0, + /* 1-bit s/w ecc and layout different from romcode */ + OMAP_ECC_HAMMING_CODE_HW,/* 1-bit ecc, romcode layout */ + OMAP_ECC_HAMMING_CODE_SW,/* 1-bit ecc, romcode layout */ + } ecc_opt; }; /* minimum size for IO mapping */ diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 20e73bf..63682c0 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -7,7 +7,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#define CONFIG_MTD_NAND_OMAP_HWECC #include #include @@ -658,8 +657,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) return 0; } -#ifdef CONFIG_MTD_NAND_OMAP_HWECC - /** * gen_true_ecc - This function will generate true ECC value * @ecc_buf: buffer to store ecc code @@ -879,8 +876,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); } -#endif - /** * omap_wait - wait until the command is done * @mtd: MTD device structure @@ -1059,17 +1054,19 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } info->nand.verify_buf = omap_verify_buf; -#ifdef CONFIG_MTD_NAND_OMAP_HWECC - info->nand.ecc.bytes = 3; - info->nand.ecc.size = 512; - info->nand.ecc.calculate = omap_calculate_ecc; - info->nand.ecc.hwctl = omap_enable_hwecc; - info->nand.ecc.correct = omap_correct_data; - info->nand.ecc.mode = NAND_ECC_HW; - -#else - info->nand.ecc.mode = NAND_ECC_SOFT; -#endif + /* selsect the ecc type */ + if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DIFF_LAYOUT) || + (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW)) { + info->nand.ecc.bytes = 3; + info->nand.ecc.size = 512; + info->nand.ecc.calculate = omap_calculate_ecc; + info->nand.ecc.hwctl = omap_enable_hwecc; + info->nand.ecc.correct = omap_correct_data; + info->nand.ecc.mode = NAND_ECC_HW; + + } else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_SW) { + info->nand.ecc.mode = NAND_ECC_SOFT; + } /* DIP switches on some boards change between 8 and 16 bit * bus widths for flash. Try the other width if the first try fails. From patchwork Mon Aug 2 15:49:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 116554 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FoBcS018168 for ; Mon, 2 Aug 2010 15:50:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753747Ab0HBPuJ (ORCPT ); Mon, 2 Aug 2010 11:50:09 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:48568 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752682Ab0HBPuH (ORCPT ); Mon, 2 Aug 2010 11:50:07 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o72Fo0EX008020 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 2 Aug 2010 10:50:02 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o72FntD2011550; Mon, 2 Aug 2010 21:19:58 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, Sukumar Ghorai , Vimal Singh Subject: [PATCH v4 1/4] omap3: nand: prefetch in irq mode support Date: Mon, 2 Aug 2010 21:19:49 +0530 Message-Id: <1280764192-15053-2-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> References: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:50:11 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index ac834aa..4871d71 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -133,6 +134,7 @@ static struct omap_nand_platform_data board_nand_data = { .nand_setup = NULL, .gpmc_t = &nand_timings, .dma_channel = -1, /* disable DMA in OMAP NAND driver */ + .gpmc_irq = INT_34XX_GPMC_IRQ, .dev_ready = NULL, .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ }; diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index f46933b..86a6f78 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -487,6 +487,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval) u32 regval = 0; switch (cmd) { + case GPMC_ENABLE_IRQ: + gpmc_write_reg(GPMC_IRQENABLE, wval); + break; + case GPMC_SET_IRQ_STATUS: gpmc_write_reg(GPMC_IRQSTATUS, wval); break; diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 9fd99b9..054e704 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -41,6 +41,8 @@ #define GPMC_NAND_ADDRESS 0x0000000b #define GPMC_NAND_DATA 0x0000000c +#define GPMC_ENABLE_IRQ 0x0000000d + /* ECC commands */ #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ @@ -78,6 +80,8 @@ #define WR_RD_PIN_MONITORING 0x00600000 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) +#define GPMC_IRQ_FIFOEVENTENABLE 0x01 +#define GPMC_IRQ_COUNT_EVENT 0x02 /* * Note that all values in this struct are in nanoseconds, while diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index c01d9f0..fd6d677 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -318,6 +318,7 @@ #define INT_34XX_PRCM_MPU_IRQ 11 #define INT_34XX_MCBSP1_IRQ 16 #define INT_34XX_MCBSP2_IRQ 17 +#define INT_34XX_GPMC_IRQ 20 #define INT_34XX_MCBSP3_IRQ 22 #define INT_34XX_MCBSP4_IRQ 23 #define INT_34XX_CAM_IRQ 24 diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 6562cd0..5e69463 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -20,6 +20,7 @@ struct omap_nand_platform_data { int (*nand_setup)(void); int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; + int gpmc_irq; unsigned long phys_base; int devsize; }; diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index ffc3720..46361ef 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -112,6 +112,9 @@ config MTD_NAND_OMAP_PREFETCH help The NAND device can be accessed for Read/Write using GPMC PREFETCH engine to improve the performance. + GPMC PREFETCH can be configured eigther in MPU interrupt mode or in DMA + interrupt mode. If not selected any of them prefetch will be used in + polling mode. config MTD_NAND_OMAP_PREFETCH_DMA depends on MTD_NAND_OMAP_PREFETCH @@ -120,7 +123,16 @@ config MTD_NAND_OMAP_PREFETCH_DMA help The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode or in DMA interrupt mode. - Say y for DMA mode or MPU mode will be used + Say y for DMA mode + +config MTD_NAND_OMAP_PREFETCH_IRQ + depends on MTD_NAND_OMAP_PREFETCH && !MTD_NAND_OMAP_PREFETCH_DMA + bool "IRQ mode" + default n + help + The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode + or in DMA interrupt mode. + Say y for IRQ mode config MTD_NAND_IDS tristate diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 133d515..9dc5ff9 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -105,17 +106,27 @@ module_param(use_prefetch, bool, 0); MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH"); #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA +const int use_interrupt; static int use_dma = 1; /* "modprobe ... use_dma=0" etc */ module_param(use_dma, bool, 0); -MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); +MODULE_PARM_DESC(use_dma, "enable/disable use of DMA mode"); +#elif defined(CONFIG_MTD_NAND_OMAP_PREFETCH_IRQ) +const int use_dma; +static int use_interrupt = 1; + +/* "modprobe ... use_dma=0" etc */ +module_param(use_interrupt, bool, 0); +MODULE_PARM_DESC(use_interrupt, "enable/disable use of IRQ mode"); #else const int use_dma; +const int use_interrupt; #endif #else const int use_prefetch; const int use_dma; +const int use_interrupt; #endif struct omap_nand_info { @@ -130,6 +141,13 @@ struct omap_nand_info { unsigned long phys_base; struct completion comp; int dma_ch; + int gpmc_irq; + enum { + OMAP_NAND_IO_READ = 0, /* read */ + OMAP_NAND_IO_WRITE, /* write */ + } iomode; + u_char *buf; + int buf_len; }; /** @@ -467,6 +485,152 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd, omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); } +/* + * omap_nand_irq - GMPC irq handler + * @this_irq: gpmc irq number + * @dev: omap_nand_info structure pointer is passed here + */ +static irqreturn_t omap_nand_irq(int this_irq, void *dev) +{ + struct omap_nand_info *info = (struct omap_nand_info *) dev; + u32 bytes; + u32 irq_stat; + + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); + bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); + bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ + if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ + if (irq_stat & 0x2) + goto done; + + if (info->buf_len & (info->buf_len < bytes)) + bytes = info->buf_len; + else if (!info->buf_len) + bytes = 0; + iowrite32_rep(info->nand.IO_ADDR_W, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + info->buf_len -= bytes; + + } else { + ioread32_rep(info->nand.IO_ADDR_R, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + + if (irq_stat & 0x2) + goto done; + } + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); + + return IRQ_HANDLED; + +done: + complete(&info->comp); + /* disable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); + + /* clear status */ + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); + + return IRQ_HANDLED; +} + +/* + * omap_read_buf_irq_pref - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + int ret = 0; + + if (len <= mtd->oobsize) { + omap_read_buf_pref(mtd, buf, len); + return; + } + info->iomode = OMAP_NAND_IO_READ; + info->buf = buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + if (ret) + /* PFPW engine is busy, use cpu copy methode */ + goto out_copy; + + info->buf_len = len; + /* enable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + + /* waiting for read to complete */ + wait_for_completion(&info->comp); + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_read_buf16(mtd, buf, len); + else + omap_read_buf8(mtd, buf, len); +} + +/* + * omap_write_buf_irq_pref - write buffer to NAND controller + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void omap_write_buf_irq_pref(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + int ret = 0; + if (len <= mtd->oobsize) { + omap_write_buf_pref(mtd, buf, len); + return; + } + + info->iomode = OMAP_NAND_IO_WRITE; + info->buf = (u_char *) buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + if (ret) + /* PFPW engine is busy, use cpu copy methode */ + goto out_copy; + + info->buf_len = len; + /* enable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + /* waiting for write to complete */ + wait_for_completion(&info->comp); + /* wait for data to flushed-out before reset the prefetch */ + do { + ret = gpmc_read_status(GPMC_PREFETCH_COUNT); + } while (ret); + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_write_buf16(mtd, buf, len); + else + omap_write_buf8(mtd, buf, len); +} + /** * omap_verify_buf - Verify chip data against buffer * @mtd: MTD device structure @@ -800,6 +964,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->gpmc_cs = pdata->cs; info->phys_base = pdata->phys_base; + info->gpmc_irq = pdata->gpmc_irq; info->mtd.priv = &info->nand; info->mtd.name = dev_name(&pdev->dev); @@ -863,7 +1028,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.read_buf = omap_read_buf_dma_pref; info->nand.write_buf = omap_write_buf_dma_pref; } + } else if (use_interrupt) { + err = request_irq(info->gpmc_irq, omap_nand_irq, + IRQF_SHARED, info->mtd.name, info); + if (err) { + printk(KERN_INFO"failure requesting irq %i." + " Prefetch will work in mpu" + " poling mode.\n", + info->gpmc_irq); + } else { + info->nand.read_buf = omap_read_buf_irq_pref; + info->nand.write_buf = omap_write_buf_irq_pref; + } } + } else { if (info->nand.options & NAND_BUSWIDTH_16) { info->nand.read_buf = omap_read_buf16; @@ -953,11 +1131,19 @@ static int __init omap_nand_init(void) /* This check is required if driver is being * loaded run time as a module */ - if ((1 == use_dma) && (0 == use_prefetch)) { - printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 " - "without use_prefetch'. Prefetch will not be" - " used in either mode (mpu or dma)\n"); + + if ((0 == use_prefetch) && (1 == (use_dma | use_interrupt))) { + printk(KERN_INFO "Wrong parameters: Neither 'dma' nor 'irq' " + "can used without 'use_prefetch' selected.\n"); + printk(KERN_INFO "Prefetch will not be used in any mode: " + "poll, mpu or dma\n"); + } else if ((1 == use_prefetch) && (1 == (use_interrupt & use_dma))) { + printk(KERN_INFO "Wrong parameters: Both DMA and IRQ" + " modes can not be used together.\n"); + printk(KERN_INFO "It has to be selected at compile " + "time and same will be used.\n"); } + return platform_driver_register(&omap_nand_driver); } From patchwork Mon Aug 2 15:49:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 116556 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72Foljk018295 for ; Mon, 2 Aug 2010 15:50:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753911Ab0HBPuN (ORCPT ); Mon, 2 Aug 2010 11:50:13 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59198 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753780Ab0HBPuK (ORCPT ); Mon, 2 Aug 2010 11:50:10 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o72Fo5C1000962 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 2 Aug 2010 10:50:07 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o72FntD5011550; Mon, 2 Aug 2010 21:20:02 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, Sukumar Ghorai , Vimal Singh Subject: [PATCH v4 4/4] omap: nand: making ecc layout as compatible with romcode ecc Date: Mon, 2 Aug 2010 21:19:52 +0530 Message-Id: <1280764192-15053-5-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> References: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:50:47 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 5f74c8f..d71c511 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -145,7 +145,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) board_nand_data.cs = cs; board_nand_data.parts = nand_parts; board_nand_data.nr_parts = nr_parts; - board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DIFF_LAYOUT; + board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_HW; gpmc_nand_init(&board_nand_data); } diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 63682c0..1041783 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -128,6 +128,20 @@ const int use_dma; const int use_interrupt; #endif +/* oob info generated runtime depending on ecc algorithm and layout selected */ +static struct nand_ecclayout omap_oobinfo; +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks + */ +static uint8_t scan_ff_pattern[] = { 0xff }; +static struct nand_bbt_descr bb_descrip_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0, + .len = 1, + .pattern = scan_ff_pattern, +}; + + struct omap_nand_info { struct nand_hw_control controller; struct omap_nand_platform_data *pdata; @@ -945,6 +959,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) struct omap_nand_info *info; struct omap_nand_platform_data *pdata; int err; + int i, offset; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1079,6 +1094,25 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } } + /* rom code layout */ + if (pdata->ecc_opt != OMAP_ECC_HAMMING_CODE_DIFF_LAYOUT) { + offset = (info->nand.options & NAND_BUSWIDTH_16) ? 2 : 1; + if (info->mtd.oobsize == 16) { + info->nand.badblock_pattern = &bb_descrip_flashbased; + omap_oobinfo.eccbytes = 3; + } else + omap_oobinfo.eccbytes = 3 * 4; + + for (i = 0; i < omap_oobinfo.eccbytes; i++) + omap_oobinfo.eccpos[i] = i+offset; + + omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; + omap_oobinfo.oobfree->length = info->mtd.oobsize - + (offset + omap_oobinfo.eccbytes); + + info->nand.ecc.layout = &omap_oobinfo; + } + #ifdef CONFIG_MTD_PARTITIONS err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); if (err > 0) From patchwork Mon Aug 2 15:49:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 116553 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FoBcR018168 for ; Mon, 2 Aug 2010 15:50:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753537Ab0HBPuI (ORCPT ); Mon, 2 Aug 2010 11:50:08 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:54049 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751893Ab0HBPuH (ORCPT ); Mon, 2 Aug 2010 11:50:07 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o72Fo2CK006375 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 2 Aug 2010 10:50:04 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o72FntD3011550; Mon, 2 Aug 2010 21:19:59 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, Sukumar Ghorai , Vimal Singh Subject: [PATCH v4 2/4] omap3: nand: configurable fifo threshold to gain the throughput Date: Mon, 2 Aug 2010 21:19:50 +0530 Message-Id: <1280764192-15053-3-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> References: <1280764192-15053-1-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:50:11 +0000 (UTC) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 86a6f78..8871a91 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -58,7 +58,6 @@ #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ #define GPMC_SECTION_SHIFT 28 /* 128 MB */ -#define PREFETCH_FIFOTHRESHOLD (0x40 << 8) #define CS_NUM_SHIFT 24 #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 @@ -592,15 +591,19 @@ EXPORT_SYMBOL(gpmc_nand_write); /** * gpmc_prefetch_enable - configures and starts prefetch transfer * @cs: cs (chip select) number + * @fifo_th: fifo threshold to be used for read/ write * @dma_mode: dma mode enable (1) or disable (0) * @u32_count: number of bytes to be transferred * @is_write: prefetch read(0) or write post(1) mode */ -int gpmc_prefetch_enable(int cs, int dma_mode, +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, unsigned int u32_count, int is_write) { - if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { + printk(KERN_ERR "PREFETCH Fifo Threshold is not supported\n"); + return -1; + } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { /* Set the amount of bytes to be prefetched */ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); @@ -608,7 +611,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode, * enable the engine. Set which cs is has requested for. */ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | - PREFETCH_FIFOTHRESHOLD | + PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) | (0x1 & is_write))); diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 054e704..fb82335 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -83,6 +83,9 @@ #define GPMC_IRQ_FIFOEVENTENABLE 0x01 #define GPMC_IRQ_COUNT_EVENT 0x02 +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 +#define PREFETCH_FIFOTHRESHOLD(val) (val << 8) + /* * Note that all values in this struct are in nanoseconds, while * the register values are in gpmc_fck cycles. @@ -133,7 +136,7 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); extern int gpmc_cs_set_reserved(int cs, int reserved); extern int gpmc_cs_reserved(int cs); -extern int gpmc_prefetch_enable(int cs, int dma_mode, +extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, unsigned int u32_count, int is_write); extern int gpmc_prefetch_reset(int cs); extern void omap3_gpmc_save_context(void); diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 9dc5ff9..20e73bf 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -275,7 +275,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -319,7 +320,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd, } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -373,10 +375,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, dma_addr_t dma_addr; int ret; - /* The fifo depth is 64 bytes. We have a sync at each frame and frame - * length is 64 bytes. + /* The fifo depth is 64 bytes max. + * But configure the FIFO-threahold to 32 to get a sync at each frame + * and frame length is 32 bytes. */ - int buf_len = len >> 6; + int buf_len = len >> 5; if (addr >= high_memory) { struct page *p1; @@ -415,7 +418,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX/2, 0x1, len, is_write); if (ret) /* PFPW engine is busy, use cpu copy methode */ goto out_copy; @@ -558,7 +562,8 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) init_completion(&info->comp); /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); if (ret) /* PFPW engine is busy, use cpu copy methode */ goto out_copy; @@ -603,8 +608,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd, info->buf = (u_char *) buf; init_completion(&info->comp); - /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + /* configure and start prefetch transfer : size=24 */ + ret = gpmc_prefetch_enable(info->gpmc_cs, + (PREFETCH_FIFOTHRESHOLD_MAX*3)/8, 0x0, len, 0x1); if (ret) /* PFPW engine is busy, use cpu copy methode */ goto out_copy; From patchwork Mon Aug 9 09:19:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 118341 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o799JSDR020662 for ; Mon, 9 Aug 2010 09:19:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755862Ab0HIJT1 (ORCPT ); Mon, 9 Aug 2010 05:19:27 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:53330 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755840Ab0HIJT0 (ORCPT ); Mon, 9 Aug 2010 05:19:26 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o799JBCO025954 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 9 Aug 2010 04:19:14 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o799JAxE003768; Mon, 9 Aug 2010 14:49:10 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Mon, 9 Aug 2010 14:49:11 +0530 From: "Shilimkar, Santosh" To: "linux-omap@vger.kernel.org" CC: Russell King - ARM Linux , "linux-arm-kernel@lists.infradead.org" Date: Mon, 9 Aug 2010 14:49:09 +0530 Subject: RE: [PATCH 1/3] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONACHED L1 entries Thread-Topic: [PATCH 1/3] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONACHED L1 entries Thread-Index: Acs27aHoaqYUumqnRd+EFh6pQj1RGQAAXt4wAC0RybA= Message-ID: References: <1281262672-27626-1-git-send-email-santosh.shilimkar@ti.com> <20100808113403.GA23623@n2100.arm.linux.org.uk> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 09 Aug 2010 09:19:28 +0000 (UTC) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 6e1c4f6..3e986a6 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -246,6 +246,9 @@ static struct mem_type mem_types[] = { .domain = DOMAIN_USER, }, [MT_MEMORY] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_USER | L_PTE_EXEC, + .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, @@ -254,6 +257,9 @@ static struct mem_type mem_types[] = { .domain = DOMAIN_KERNEL, }, [MT_MEMORY_NONCACHED] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE, + .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, @@ -411,9 +417,12 @@ static void __init build_mem_type_table(void) * Enable CPU-specific coherency if supported. * (Only available on XSC3 at the moment.) */ - if (arch_is_coherent() && cpu_is_xsc3()) + if (arch_is_coherent() && cpu_is_xsc3()) { mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; - + mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; + mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; + } /* * ARMv6 and above have extended page tables. */ @@ -438,7 +447,9 @@ static void __init build_mem_type_table(void) mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; #endif } @@ -475,6 +486,8 @@ static void __init build_mem_type_table(void) mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; + mem_types[MT_MEMORY].prot_pte |= kern_pgprot; + mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; mem_types[MT_ROM].prot_sect |= cp->pmd; switch (cp->pmd) { From patchwork Wed Jun 16 16:09:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abraham Arce X-Patchwork-Id: 106524 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5GG9iqJ009750 for ; Wed, 16 Jun 2010 16:09:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759209Ab0FPQJ1 (ORCPT ); Wed, 16 Jun 2010 12:09:27 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:34716 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754987Ab0FPQJ0 (ORCPT ); Wed, 16 Jun 2010 12:09:26 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5GG9P0N008897 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 16 Jun 2010 11:09:25 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o5GG9OPw008852; Wed, 16 Jun 2010 11:09:24 -0500 (CDT) Received: from localhost (x0066660-laptop.am.dhcp.ti.com [128.247.115.249]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o5GG9OP25132; Wed, 16 Jun 2010 11:09:24 -0500 (CDT) From: Abraham Arce To: linux-input@vger.kernel.org, linux-omap@vger.kernel.org Cc: Abraham Arce Subject: [PATCH v4 3/4] OMAP4: Keyboard board support Date: Wed, 16 Jun 2010 11:09:49 -0500 Message-Id: <1276704589-30689-1-git-send-email-x0066660@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: References: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 16 Jun 2010 16:09:46 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index e4a5d66..db30f15 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -34,12 +34,106 @@ #include #include #include +#include #include "hsmmc.h" #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 +static int sdp4430_keymap[] = { + KEY(0, 0, KEY_E), + KEY(0, 1, KEY_R), + KEY(0, 2, KEY_T), + KEY(0, 3, KEY_HOME), + KEY(0, 4, KEY_F5), + KEY(0, 5, KEY_UNKNOWN), + KEY(0, 6, KEY_I), + KEY(0, 7, KEY_LEFTSHIFT), + + KEY(1, 0, KEY_D), + KEY(1, 1, KEY_F), + KEY(1, 2, KEY_G), + KEY(1, 3, KEY_SEND), + KEY(1, 4, KEY_F6), + KEY(1, 5, KEY_UNKNOWN), + KEY(1, 6, KEY_K), + KEY(1, 7, KEY_ENTER), + + KEY(2, 0, KEY_X), + KEY(2, 1, KEY_C), + KEY(2, 2, KEY_V), + KEY(2, 3, KEY_END), + KEY(2, 4, KEY_F7), + KEY(2, 5, KEY_UNKNOWN), + KEY(2, 6, KEY_DOT), + KEY(2, 7, KEY_CAPSLOCK), + + KEY(3, 0, KEY_Z), + KEY(3, 1, KEY_KPPLUS), + KEY(3, 2, KEY_B), + KEY(3, 3, KEY_F1), + KEY(3, 4, KEY_F8), + KEY(3, 5, KEY_UNKNOWN), + KEY(3, 6, KEY_O), + KEY(3, 7, KEY_SPACE), + + KEY(4, 0, KEY_W), + KEY(4, 1, KEY_Y), + KEY(4, 2, KEY_U), + KEY(4, 3, KEY_F2), + KEY(4, 4, KEY_VOLUMEUP), + KEY(4, 5, KEY_UNKNOWN), + KEY(4, 6, KEY_L), + KEY(4, 7, KEY_LEFT), + + KEY(5, 0, KEY_S), + KEY(5, 1, KEY_H), + KEY(5, 2, KEY_J), + KEY(5, 3, KEY_F3), + KEY(5, 4, KEY_F9), + KEY(5, 5, KEY_VOLUMEDOWN), + KEY(5, 6, KEY_M), + KEY(5, 7, KEY_RIGHT), + + KEY(6, 0, KEY_Q), + KEY(6, 1, KEY_A), + KEY(6, 2, KEY_N), + KEY(6, 3, KEY_BACK), + KEY(6, 4, KEY_BACKSPACE), + KEY(6, 5, KEY_UNKNOWN), + KEY(6, 6, KEY_P), + KEY(6, 7, KEY_UP), + + KEY(7, 0, KEY_PROG1), + KEY(7, 1, KEY_PROG2), + KEY(7, 2, KEY_PROG3), + KEY(7, 3, KEY_PROG4), + KEY(7, 4, KEY_F4), + KEY(7, 5, KEY_UNKNOWN), + KEY(7, 6, KEY_OK), + KEY(7, 7, KEY_DOWN), +}; + +static struct matrix_keymap_data sdp4430_keymap_data = { + .keymap = sdp4430_keymap, + .keymap_size = ARRAY_SIZE(sdp4430_keymap), +}; + +static struct omap4_keypad_platform_data sdp4430_keypad_data = { + .keymap_data = &sdp4430_keymap_data, + .rows = 8, + .cols = 8, +}; + +static struct platform_device sdp4430_keypad_device = { + .name = "omap4-keypad", + .id = -1, + .dev = { + .platform_data = &sdp4430_keypad_data, + }, +}; + static struct spi_board_info sdp4430_spi_board_info[] __initdata = { { .modalias = "ks8851", @@ -112,6 +206,7 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, + &sdp4430_keypad_device, }; static struct omap_lcd_config sdp4430_lcd_config __initdata = { @@ -380,6 +475,10 @@ static void __init omap_4430sdp_init(void) if (!cpu_is_omap44xx()) usb_musb_init(&musb_board_data); + status = omap4_init_kp(&sdp4430_keypad_data); + if (status) + pr_err("Keypad initialization failed: %d\n", status); + status = omap_ethernet_init(); if (status) { pr_err("Ethernet initialization failed: %d\n", status); From patchwork Sun Jul 25 11:14:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 114105 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6PBEXpE022654 for ; Sun, 25 Jul 2010 11:14:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752205Ab0GYLOb (ORCPT ); Sun, 25 Jul 2010 07:14:31 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:45762 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751286Ab0GYLOa (ORCPT ); Sun, 25 Jul 2010 07:14:30 -0400 Received: by bwz1 with SMTP id 1so2366943bwz.19 for ; Sun, 25 Jul 2010 04:14:28 -0700 (PDT) Received: by 10.204.112.7 with SMTP id u7mr3083557bkp.70.1280056463055; Sun, 25 Jul 2010 04:14:23 -0700 (PDT) Received: from localhost.localdomain (93-173-247-50.bb.netvision.net.il [93.173.247.50]) by mx.google.com with ESMTPS id bq20sm1898118bkb.4.2010.07.25.04.14.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 25 Jul 2010 04:14:22 -0700 (PDT) From: Ohad Ben-Cohen To: Cc: , , Mark Brown , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH] omap: zoom: add fixed regulator device for wl1271 Date: Sun, 25 Jul 2010 14:14:03 +0300 Message-Id: <1280056443-12589-1-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 25 Jul 2010 11:14:33 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b39849..de88635 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,8 @@ #include "mux.h" #include "hsmmc.h" +#define OMAP_ZOOM_WLAN_PMENA_GPIO (101) + /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { KEY(0, 0, KEY_E), @@ -106,6 +109,11 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = { .supply = "vmmc", }; +static struct regulator_consumer_supply zoom_vmmc3_supply = { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.2", +}; + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data zoom_vmmc1 = { .constraints = { @@ -151,6 +159,32 @@ static struct regulator_init_data zoom_vsim = { .consumer_supplies = &zoom_vsim_supply, }; +static struct regulator_init_data zoom_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom_vmmc3_supply, +}; + +static struct fixed_voltage_config zoom_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.8V */ + .gpio = OMAP_ZOOM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70msec */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &zoom_vmmc3, +}; + +static struct platform_device omap_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &zoom_vwlan, + }, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -280,6 +314,7 @@ static void enable_board_wakeup_source(void) void __init zoom_peripherals_init(void) { omap_i2c_init(); + platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); enable_board_wakeup_source(); } From patchwork Fri Jul 23 19:58:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 113989 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NK2IT2027823 for ; Fri, 23 Jul 2010 20:02:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760636Ab0GWUBE (ORCPT ); Fri, 23 Jul 2010 16:01:04 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:43159 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757342Ab0GWT7L (ORCPT ); Fri, 23 Jul 2010 15:59:11 -0400 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.71) (envelope-from ) id 1OcOOe-00019A-TJ; Fri, 23 Jul 2010 21:59:04 +0200 Received: from ukl by octopus.hi.pengutronix.de with local (Exim 4.69) (envelope-from ) id 1OcOOb-0002T9-QV; Fri, 23 Jul 2010 21:59:01 +0200 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= To: linux-arm-kernel@lists.infradead.org Cc: Tony Lindgren , Russell King , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Tomi Valkeinen , Santosh Shilimkar , Paul Walmsley , janboe , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/11] ARM: omap: move omapfb_reserve_sram() to .init.text Date: Fri, 23 Jul 2010 21:58:30 +0200 Message-Id: <1279915120-4373-7-git-send-email-u.kleine-koenig@pengutronix.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> References: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-omap@vger.kernel.org Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 20:02:19 +0000 (UTC) diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 4df210f..4c0ae4d 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -233,7 +233,7 @@ void __init omapfb_reserve_sdram(void) * this point, since the driver built as a module would have problem with * freeing / reallocating the regions. */ -unsigned long omapfb_reserve_sram(unsigned long sram_pstart, +unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, unsigned long pstart_avail, @@ -360,7 +360,7 @@ static int __init omap_init_fb(void) arch_initcall(omap_init_fb); void __init omapfb_reserve_sdram(void) {} -unsigned long omapfb_reserve_sram(unsigned long sram_pstart, +unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, unsigned long start_avail, @@ -376,7 +376,7 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data) } void __init omapfb_reserve_sdram(void) {} -unsigned long omapfb_reserve_sram(unsigned long sram_pstart, +unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, unsigned long start_avail, diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 226b2e8..ccd6623 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -79,7 +79,7 @@ static unsigned long omap_sram_base; static unsigned long omap_sram_size; static unsigned long omap_sram_ceil; -extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, +extern unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, unsigned long pstart_avail, From patchwork Fri Jul 23 19:58:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 113988 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NK2ISx027823 for ; Fri, 23 Jul 2010 20:02:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757350Ab0GWT7J (ORCPT ); Fri, 23 Jul 2010 15:59:09 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:43125 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756256Ab0GWT7H (ORCPT ); Fri, 23 Jul 2010 15:59:07 -0400 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.71) (envelope-from ) id 1OcOOc-00019E-90; Fri, 23 Jul 2010 21:59:02 +0200 Received: from ukl by octopus.hi.pengutronix.de with local (Exim 4.69) (envelope-from ) id 1OcOOc-0002U4-6n; Fri, 23 Jul 2010 21:59:02 +0200 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= To: linux-arm-kernel@lists.infradead.org Cc: Tony Lindgren , Russell King , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Tomi Valkeinen , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/11] ARM: omap: move get_fbmem_region() to .init.text Date: Fri, 23 Jul 2010 21:58:31 +0200 Message-Id: <1279915120-4373-8-git-send-email-u.kleine-koenig@pengutronix.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> References: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-omap@vger.kernel.org Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 20:02:18 +0000 (UTC) diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 4c0ae4d..e05e320 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -94,7 +94,7 @@ static int fbmem_region_reserved(unsigned long start, size_t size) * Get the region_idx`th region from board config/ATAG and convert it to * our internal format. */ -static int get_fbmem_region(int region_idx, struct omapfb_mem_region *rg) +static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg) { const struct omap_fbmem_config *conf; u32 paddr; From patchwork Sun Jul 4 13:34:33 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110135 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64DYwmd004410 for ; Sun, 4 Jul 2010 13:34:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757765Ab0GDNe5 (ORCPT ); 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Sun, 04 Jul 2010 06:34:56 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id f10sm12807572bkl.17.2010.07.04.06.34.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 04 Jul 2010 06:34:55 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Ohad Ben-Cohen , Omar Ramirez Luna , Greg KH , Felipe Contreras Subject: [PATCH 07/13] staging: ti dspbridge: deh: refactor in mmu_fault_print_stack() Date: Sun, 4 Jul 2010 16:34:33 +0300 Message-Id: <1278250479-16982-8-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> References: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 04 Jul 2010 13:34:58 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/ue_deh.c b/drivers/staging/tidspbridge/core/ue_deh.c index 793e982..1e506d7 100644 --- a/drivers/staging/tidspbridge/core/ue_deh.c +++ b/drivers/staging/tidspbridge/core/ue_deh.c @@ -140,9 +140,8 @@ int bridge_deh_register_notify(struct deh_mgr *deh_mgr, u32 event_mask, return ntfy_unregister(deh_mgr->ntfy_obj, hnotification); } -void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) +static void mmu_fault_print_stack(struct bridge_dev_context *dev_context) { - struct bridge_dev_context *dev_context; struct cfg_hostres *resources; struct hw_mmu_map_attrs_t map_attrs = { .endianism = HW_LITTLE_ENDIAN, @@ -151,12 +150,45 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) }; void *dummy_va_addr; + resources = dev_context->resources; + dummy_va_addr = (void*)__get_free_page(GFP_ATOMIC); + + /* + * Before acking the MMU fault, let's make sure MMU can only + * access entry #0. Then add a new entry so that the DSP OS + * can continue in order to dump the stack. + */ + hw_mmu_twl_disable(resources->dw_dmmu_base); + hw_mmu_tlb_flush_all(resources->dw_dmmu_base); + + hw_mmu_tlb_add(resources->dw_dmmu_base, + virt_to_phys(dummy_va_addr), fault_addr, + HW_PAGE_SIZE4KB, 1, + &map_attrs, HW_SET, HW_SET); + + dsp_clk_enable(DSP_CLK_GPT8); + + dsp_gpt_wait_overflow(DSP_CLK_GPT8, 0xfffffffe); + + /* Clear MMU interrupt */ + hw_mmu_event_ack(resources->dw_dmmu_base, + HW_MMU_TRANSLATION_FAULT); + dump_dsp_stack(dev_context); + dsp_clk_disable(DSP_CLK_GPT8); + + hw_mmu_disable(resources->dw_dmmu_base); + free_page((unsigned long)dummy_va_addr); +} + +void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) +{ + struct bridge_dev_context *dev_context; + if (!deh_mgr) return; dev_info(bridge, "%s: device exception\n", __func__); dev_context = deh_mgr->hbridge_context; - resources = dev_context->resources; switch (ulEventMask) { case DSP_SYSERROR: @@ -181,36 +213,11 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) (unsigned int) deh_mgr->err_info.dw_val1, (unsigned int) deh_mgr->err_info.dw_val2, (unsigned int) fault_addr); - dummy_va_addr = (void*)__get_free_page(GFP_ATOMIC); print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); - /* - * Before acking the MMU fault, let's make sure MMU can only - * access entry #0. Then add a new entry so that the DSP OS - * can continue in order to dump the stack. - */ - hw_mmu_twl_disable(resources->dw_dmmu_base); - hw_mmu_tlb_flush_all(resources->dw_dmmu_base); - - hw_mmu_tlb_add(resources->dw_dmmu_base, - virt_to_phys(dummy_va_addr), fault_addr, - HW_PAGE_SIZE4KB, 1, - &map_attrs, HW_SET, HW_SET); - - dsp_clk_enable(DSP_CLK_GPT8); - - dsp_gpt_wait_overflow(DSP_CLK_GPT8, 0xfffffffe); - - /* Clear MMU interrupt */ - hw_mmu_event_ack(resources->dw_dmmu_base, - HW_MMU_TRANSLATION_FAULT); - dump_dsp_stack(dev_context); - dsp_clk_disable(DSP_CLK_GPT8); - - hw_mmu_disable(resources->dw_dmmu_base); - free_page((unsigned long)dummy_va_addr); + mmu_fault_print_stack(dev_context); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR case DSP_PWRERROR: From patchwork Sun Jul 4 13:34:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110134 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64DYukB004395 for ; Sun, 4 Jul 2010 13:34:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757748Ab0GDNez (ORCPT ); Sun, 4 Jul 2010 09:34:55 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:40955 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757698Ab0GDNez (ORCPT ); Sun, 4 Jul 2010 09:34:55 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so2295322bwz.19 for ; Sun, 04 Jul 2010 06:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=bHWT9ogCUrYPk1xxUExZZ5A+WHe1MErfIInXO4arM9s=; b=spujvMG9hYGvvh9WekgesFkxraLspFDxyhHD3f6TEshORCUjrnplmGXjsw22sAuMCi ctDOLvT5/PtQi+o6RZmv9N3KWwGRsaMEmNKc7jIqnkG6AXSEGApgJ0Df+E5skWMkrMkq T+30Lw3hyr/VViegfXc+MDhsdzkTyAAsvG+6s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=v8yQqNfg0PCi8w4kCiJpQ7UZ2Ah5R0LrGvhsqr41qDV/VzmwPD9flEzMu1PjKpXz8j SCCYxhL/pvy+4IRJfsNd7mukpsjfJJR1EdzxmVzsy5iaV4kh7PWFBFc4wo3kvrVbCo6W pbTuF7mvEz2uLkHLKoh1xiT3f89K3vEh/Ds/o= Received: by 10.204.134.156 with SMTP id j28mr1346075bkt.10.1278250494407; Sun, 04 Jul 2010 06:34:54 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id s17sm9762816bkx.18.2010.07.04.06.34.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 04 Jul 2010 06:34:54 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Ohad Ben-Cohen , Omar Ramirez Luna , Greg KH , Felipe Contreras Subject: [PATCH 06/13] staging: ti dspbridge: deh: ensure only tlb #0 is enabled Date: Sun, 4 Jul 2010 16:34:32 +0300 Message-Id: <1278250479-16982-7-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> References: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 04 Jul 2010 13:34:57 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/ue_deh.c b/drivers/staging/tidspbridge/core/ue_deh.c index 06167ed..793e982 100644 --- a/drivers/staging/tidspbridge/core/ue_deh.c +++ b/drivers/staging/tidspbridge/core/ue_deh.c @@ -186,6 +186,14 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); + /* + * Before acking the MMU fault, let's make sure MMU can only + * access entry #0. Then add a new entry so that the DSP OS + * can continue in order to dump the stack. + */ + hw_mmu_twl_disable(resources->dw_dmmu_base); + hw_mmu_tlb_flush_all(resources->dw_dmmu_base); + hw_mmu_tlb_add(resources->dw_dmmu_base, virt_to_phys(dummy_va_addr), fault_addr, HW_PAGE_SIZE4KB, 1, From patchwork Fri Jul 23 19:58:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 113987 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NK2IT0027823 for ; Fri, 23 Jul 2010 20:02:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758094Ab0GWT7K (ORCPT ); Fri, 23 Jul 2010 15:59:10 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:43136 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757190Ab0GWT7H (ORCPT ); Fri, 23 Jul 2010 15:59:07 -0400 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.71) (envelope-from ) id 1OcOOb-00018w-1m; Fri, 23 Jul 2010 21:59:01 +0200 Received: from ukl by octopus.hi.pengutronix.de with local (Exim 4.69) (envelope-from ) id 1OcOOa-0002RE-Uy; Fri, 23 Jul 2010 21:59:00 +0200 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= To: linux-arm-kernel@lists.infradead.org Cc: Tony Lindgren , Russell King , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Tomi Valkeinen , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/11] ARM: omap: move omapfb_reserve_sdram() to .init.text Date: Fri, 23 Jul 2010 21:58:29 +0200 Message-Id: <1279915120-4373-6-git-send-email-u.kleine-koenig@pengutronix.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> References: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-omap@vger.kernel.org Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 20:02:18 +0000 (UTC) diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index e8a390d..4df210f 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -359,7 +359,7 @@ static int __init omap_init_fb(void) arch_initcall(omap_init_fb); -void omapfb_reserve_sdram(void) {} +void __init omapfb_reserve_sdram(void) {} unsigned long omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, @@ -375,7 +375,7 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data) { } -void omapfb_reserve_sdram(void) {} +void __init omapfb_reserve_sdram(void) {} unsigned long omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, From patchwork Fri Jul 23 19:58:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 113986 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NK2IT1027823 for ; Fri, 23 Jul 2010 20:02:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759959Ab0GWUBA (ORCPT ); Fri, 23 Jul 2010 16:01:00 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:43162 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758337Ab0GWT7L (ORCPT ); Fri, 23 Jul 2010 15:59:11 -0400 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.71) (envelope-from ) id 1OcOOa-00018V-KM; Fri, 23 Jul 2010 21:59:00 +0200 Received: from ukl by octopus.hi.pengutronix.de with local (Exim 4.69) (envelope-from ) id 1OcOOa-0002PJ-4Z; Fri, 23 Jul 2010 21:59:00 +0200 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= To: linux-arm-kernel@lists.infradead.org Cc: Tony Lindgren , Russell King , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Tomi Valkeinen , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/11] ARM: omap: move omap_init_fb to .init.text Date: Fri, 23 Jul 2010 21:58:27 +0200 Message-Id: <1279915120-4373-4-git-send-email-u.kleine-koenig@pengutronix.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> References: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-omap@vger.kernel.org Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 20:02:18 +0000 (UTC) diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index d3eea4f..e8a390d 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -307,7 +307,7 @@ void omapfb_set_ctrl_platform_data(void *data) omapfb_config.ctrl_platform_data = data; } -static inline int omap_init_fb(void) +static int __init omap_init_fb(void) { const struct omap_lcd_config *conf; @@ -352,7 +352,7 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data) omapfb_config = *data; } -static inline int omap_init_fb(void) +static int __init omap_init_fb(void) { return platform_device_register(&omap_fb_device); } From patchwork Fri Jul 23 19:58:34 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 113981 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NK07cF027181 for ; Fri, 23 Jul 2010 20:00:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760215Ab0GWT7g (ORCPT ); Fri, 23 Jul 2010 15:59:36 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:43180 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759246Ab0GWT7f (ORCPT ); Fri, 23 Jul 2010 15:59:35 -0400 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.71) (envelope-from ) id 1OcOOe-00019V-82; Fri, 23 Jul 2010 21:59:04 +0200 Received: from ukl by octopus.hi.pengutronix.de with local (Exim 4.69) (envelope-from ) id 1OcOOd-0002Xf-Qt; Fri, 23 Jul 2010 21:59:03 +0200 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= To: linux-arm-kernel@lists.infradead.org Cc: Tony Lindgren , Russell King , Janusz Krzysztofik , Kalle Valo , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Kevin Hilman , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/11] ARM: omap: ams-delta: move config to .init.data Date: Fri, 23 Jul 2010 21:58:34 +0200 Message-Id: <1279915120-4373-11-git-send-email-u.kleine-koenig@pengutronix.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> References: <1279915120-4373-1-git-send-email-u.kleine-koenig@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-omap@vger.kernel.org Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 20:00:52 +0000 (UTC) diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index fdd1dd5..6b936cc 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -173,7 +173,7 @@ static struct omap_usb_config ams_delta_usb_config __initdata = { .pins[0] = 2, }; -static struct omap_board_config_kernel ams_delta_config[] = { +static struct omap_board_config_kernel ams_delta_config[] __initdata = { { OMAP_TAG_LCD, &ams_delta_lcd_config }, }; From patchwork Sun Jul 4 13:34:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110130 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64DYnw1004359 for ; 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b=USDWP0ccnWoaKtNTkO/Dd+lJw6c6JUkKijOSfHwuzCzp+cYOpluRJJ6YYH7TqncSSN p4aiAhGhf+2sF4qNSgsUlFOD1dTV66+3lgKsNh25UuU7rK7JwexqNc9OdSuyyQqSr9Or sr9LS3VPcI3A2Ss5Q04xYGz6LfPq6D5gIDRUE= Received: by 10.204.81.150 with SMTP id x22mr1329397bkk.101.1278250486681; Sun, 04 Jul 2010 06:34:46 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id v6sm12809345bkx.11.2010.07.04.06.34.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 04 Jul 2010 06:34:46 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Ohad Ben-Cohen , Omar Ramirez Luna , Greg KH , Felipe Contreras Subject: [PATCH 02/13] staging: ti dspbridge: mmufault: trivial cleanups Date: Sun, 4 Jul 2010 16:34:28 +0300 Message-Id: <1278250479-16982-3-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> References: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 04 Jul 2010 13:34:50 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/mmu_fault.c b/drivers/staging/tidspbridge/core/mmu_fault.c index 5c0124f..42fe23f 100644 --- a/drivers/staging/tidspbridge/core/mmu_fault.c +++ b/drivers/staging/tidspbridge/core/mmu_fault.c @@ -40,11 +40,8 @@ #include "_tiomap.h" #include "mmu_fault.h" -static u32 dmmu_event_mask; u32 fault_addr; -static bool mmu_check_if_fault(struct bridge_dev_context *dev_context); - /* * ======== mmu_fault_dpc ======== * Deferred procedure call to handle DSP MMU fault. @@ -53,9 +50,10 @@ void mmu_fault_dpc(IN unsigned long pRefData) { struct deh_mgr *hdeh_mgr = (struct deh_mgr *)pRefData; - if (hdeh_mgr) - bridge_deh_notify(hdeh_mgr, DSP_MMUFAULT, 0L); + if (!hdeh_mgr) + return; + bridge_deh_notify(hdeh_mgr, DSP_MMUFAULT, 0L); } /* @@ -64,76 +62,44 @@ void mmu_fault_dpc(IN unsigned long pRefData) */ irqreturn_t mmu_fault_isr(int irq, IN void *pRefData) { - struct deh_mgr *deh_mgr_obj = (struct deh_mgr *)pRefData; - struct bridge_dev_context *dev_context; + struct deh_mgr *deh_mgr_obj = pRefData; struct cfg_hostres *resources; + u32 dmmu_event_mask; - DBC_REQUIRE(irq == INT_DSP_MMU_IRQ); - DBC_REQUIRE(deh_mgr_obj); - - if (deh_mgr_obj) { - - dev_context = - (struct bridge_dev_context *)deh_mgr_obj->hbridge_context; - - resources = dev_context->resources; + if (!deh_mgr_obj) + return IRQ_HANDLED; - if (!resources) { - dev_dbg(bridge, "%s: Failed to get Host Resources\n", + resources = deh_mgr_obj->hbridge_context->resources; + if (!resources) { + dev_dbg(bridge, "%s: Failed to get Host Resources\n", __func__); - return IRQ_HANDLED; - } - if (mmu_check_if_fault(dev_context)) { - printk(KERN_INFO "***** DSPMMU FAULT ***** IRQStatus " - "0x%x\n", dmmu_event_mask); - printk(KERN_INFO "***** DSPMMU FAULT ***** fault_addr " - "0x%x\n", fault_addr); - /* - * Schedule a DPC directly. In the future, it may be - * necessary to check if DSP MMU fault is intended for - * Bridge. - */ - tasklet_schedule(&deh_mgr_obj->dpc_tasklet); - - /* Reset err_info structure before use. */ - deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT; - deh_mgr_obj->err_info.dw_val1 = fault_addr >> 16; - deh_mgr_obj->err_info.dw_val2 = fault_addr & 0xFFFF; - deh_mgr_obj->err_info.dw_val3 = 0L; - /* Disable the MMU events, else once we clear it will - * start to raise INTs again */ - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_TRANSLATION_FAULT); - } else { - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_ALL_INTERRUPTS); - } + return IRQ_HANDLED; } - return IRQ_HANDLED; -} -/* - * ======== mmu_check_if_fault ======== - * Check to see if MMU Fault is valid TLB miss from DSP - * Note: This function is called from an ISR - */ -static bool mmu_check_if_fault(struct bridge_dev_context *dev_context) -{ - - bool ret = false; - hw_status hw_status_obj; - struct cfg_hostres *resources = dev_context->resources; - - if (!resources) { - dev_dbg(bridge, "%s: Failed to get Host Resources in\n", - __func__); - return ret; - } - hw_status_obj = - hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); + hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); if (dmmu_event_mask == HW_MMU_TRANSLATION_FAULT) { hw_mmu_fault_addr_read(resources->dw_dmmu_base, &fault_addr); - ret = true; + dev_info(bridge, "%s: status=0x%x, fault_addr=0x%x\n", __func__, + dmmu_event_mask, fault_addr); + /* + * Schedule a DPC directly. In the future, it may be + * necessary to check if DSP MMU fault is intended for + * Bridge. + */ + tasklet_schedule(&deh_mgr_obj->dpc_tasklet); + + /* Reset err_info structure before use. */ + deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT; + deh_mgr_obj->err_info.dw_val1 = fault_addr >> 16; + deh_mgr_obj->err_info.dw_val2 = fault_addr & 0xFFFF; + deh_mgr_obj->err_info.dw_val3 = 0L; + /* Disable the MMU events, else once we clear it will + * start to raise INTs again */ + hw_mmu_event_disable(resources->dw_dmmu_base, + HW_MMU_TRANSLATION_FAULT); + } else { + hw_mmu_event_disable(resources->dw_dmmu_base, + HW_MMU_ALL_INTERRUPTS); } - return ret; + return IRQ_HANDLED; } From patchwork Sun Jul 4 13:34:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110133 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64DYtfJ004385 for ; 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b=FMguOLWz27tSYqg0XB8Ljd84MTwSHzwy+L6sGQ35Cau9PwJdK7v/EB26iMqivaQRX0 wIEb5H+b7ZD1bVOI4SHPngQ1TAPmq7Ai4Mn/foZBfeSWcX0VGh6+nsHhA9eRFtQclhDs kJc1rl7a6LUlCE+ceGMiE8hxfc4ZDESypPiEY= Received: by 10.204.46.159 with SMTP id j31mr1344757bkf.5.1278250492450; Sun, 04 Jul 2010 06:34:52 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id s17sm9762678bkx.18.2010.07.04.06.34.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 04 Jul 2010 06:34:52 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Ohad Ben-Cohen , Omar Ramirez Luna , Greg KH , Felipe Contreras Subject: [PATCH 05/13] staging: ti dspbridge: mmu: add hw_mmu_tlb_flush_all() Date: Sun, 4 Jul 2010 16:34:31 +0300 Message-Id: <1278250479-16982-6-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> References: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 04 Jul 2010 13:34:55 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index d1fa560..1000c04 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -73,8 +73,6 @@ #define PAGES_II_LVL_TABLE 512 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT) -#define MMU_GFLUSH 0x60 - /* Forward Declarations: */ static int bridge_brd_monitor(struct bridge_dev_context *dev_context); static int bridge_brd_read(struct bridge_dev_context *dev_context, @@ -218,18 +216,13 @@ static struct bridge_drv_interface drv_interface_fxns = { bridge_msg_set_queue_id, }; -static inline void tlb_flush_all(const void __iomem *base) -{ - __raw_writeb(__raw_readb(base + MMU_GFLUSH) | 1, base + MMU_GFLUSH); -} - static inline void flush_all(struct bridge_dev_context *dev_context) { if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION || dev_context->dw_brd_state == BRD_HIBERNATION) wake_dsp(dev_context, NULL); - tlb_flush_all(dev_context->dw_dsp_mmu_base); + hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base); } static void bad_page_dump(u32 pa, struct page *pg) diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index 965b659..e593358 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -35,6 +35,7 @@ #define MMU_SMALL_PAGE_MASK 0xFFFFF000 #define MMU_LOAD_TLB 0x00000001 +#define MMU_GFLUSH 0x60 /* * hw_mmu_page_size_t: Enumerated Type used to specify the MMU Page Size(SLSS) @@ -585,3 +586,8 @@ static hw_status mmu_set_ram_entry(const void __iomem *baseAddress, return status; } + +void hw_mmu_tlb_flush_all(const void __iomem *base) +{ + __raw_writeb(1, base + MMU_GFLUSH); +} diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h index 9b13468..0436974 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.h +++ b/drivers/staging/tidspbridge/hw/hw_mmu.h @@ -97,6 +97,8 @@ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 page_size, u32 virtualAddr); +void hw_mmu_tlb_flush_all(const void __iomem *base); + static inline u32 hw_mmu_pte_addr_l1(u32 L1_base, u32 va) { u32 pte_addr; From patchwork Sun Jul 4 13:34:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110132 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64DYrBS004376 for ; Sun, 4 Jul 2010 13:34:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757730Ab0GDNew (ORCPT ); Sun, 4 Jul 2010 09:34:52 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:40955 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757698Ab0GDNev (ORCPT ); Sun, 4 Jul 2010 09:34:51 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so2295322bwz.19 for ; Sun, 04 Jul 2010 06:34:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=bNwrPs+23PeP761r0B9maBnINjNrExM6F/P+IJu/quw=; b=CLjWA5ypOYF10b1/SLV39ThQZuLBDg6+jyvxB8l1Ogxncn/UEwbf52kwSUqkcnyUd9 3Xc03usEJoR7+g/gpjuEOOzeni8X150kUL0U4YR9j6JOp4X5W12seD+F35TZ9cSTEw88 uNoIZxSPmksgW2eelHjMrhRe8BuLEnHMfgxUg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=u1N59hOmn+uHKHk71pK2myJ0wmDog9jUnb4cLnUaHacprQaB+4cMMSLei6S3M2c7Ne bNrTn/ibQXvz72HQuXX4SBBbGmPeitIEyrFSES0xNXn0dUhviLjaLwZZwQebKgayoneg wEv8z6cLQuUSb4+ywzMV/QJCjYg+osogNk1uI= Received: by 10.204.81.153 with SMTP id x25mr1342812bkk.36.1278250490802; Sun, 04 Jul 2010 06:34:50 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id g11sm12818111bkw.10.2010.07.04.06.34.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 04 Jul 2010 06:34:50 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Ohad Ben-Cohen , Omar Ramirez Luna , Greg KH , Felipe Contreras Subject: [PATCH 04/13] staging: ti dspbridge: remove unused code Date: Sun, 4 Jul 2010 16:34:30 +0300 Message-Id: <1278250479-16982-5-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> References: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 04 Jul 2010 13:34:53 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h index bf0164e..b754e49 100644 --- a/drivers/staging/tidspbridge/core/_tiomap.h +++ b/drivers/staging/tidspbridge/core/_tiomap.h @@ -339,11 +339,7 @@ struct bridge_dev_context { */ /* DMMU TLB entries */ struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB]; - u32 dw_brd_state; /* Last known board state. */ - u32 ul_int_mask; /* int mask */ - u16 io_base; /* Board I/O base */ - u32 num_tlb_entries; /* DSP MMU TLB entry counter */ - u32 fixed_tlb_entries; /* Fixed DSPMMU TLB entry count */ + u32 dw_brd_state; /* Last known board state. */ /* TC Settings */ bool tc_word_swap_on; /* Traffic Controller Word Swap */ diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index ee9205b..d1fa560 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -837,7 +837,6 @@ static int bridge_dev_create(OUT struct bridge_dev_context dev_context->atlb_entry[entry_ndx].ul_gpp_pa = dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0; } - dev_context->num_tlb_entries = 0; dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *) (pConfig-> dw_mem_base @@ -940,7 +939,6 @@ static int bridge_dev_create(OUT struct bridge_dev_context } if (DSP_SUCCEEDED(status)) { dev_context->hdev_obj = hdev_obj; - dev_context->ul_int_mask = 0; /* Store current board state. */ dev_context->dw_brd_state = BRD_STOPPED; dev_context->resources = resources; diff --git a/drivers/staging/tidspbridge/core/ue_deh.c b/drivers/staging/tidspbridge/core/ue_deh.c index 50868a4..06167ed 100644 --- a/drivers/staging/tidspbridge/core/ue_deh.c +++ b/drivers/staging/tidspbridge/core/ue_deh.c @@ -109,8 +109,6 @@ int bridge_deh_destroy(struct deh_mgr *deh_mgr) if (!deh_mgr) return -EFAULT; - /* Release dummy VA buffer */ - bridge_deh_release_dummy_mem(); /* If notification object exists, delete it */ if (deh_mgr->ntfy_obj) { ntfy_delete(deh_mgr->ntfy_obj); @@ -145,7 +143,6 @@ int bridge_deh_register_notify(struct deh_mgr *deh_mgr, u32 event_mask, void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) { struct bridge_dev_context *dev_context; - u32 hw_mmu_max_tlb_count = 31; struct cfg_hostres *resources; struct hw_mmu_map_attrs_t map_attrs = { .endianism = HW_LITTLE_ENDIAN, @@ -189,16 +186,6 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); - /* - * Reset the dynamic mmu index to fixed count if it exceeds - * 31. So that the dynmmuindex is always between the range of - * standard/fixed entries and 31. - */ - if (dev_context->num_tlb_entries > - hw_mmu_max_tlb_count) { - dev_context->num_tlb_entries = - dev_context->fixed_tlb_entries; - } hw_mmu_tlb_add(resources->dw_dmmu_base, virt_to_phys(dummy_va_addr), fault_addr, HW_PAGE_SIZE4KB, 1, @@ -275,7 +262,3 @@ int bridge_deh_get_info(struct deh_mgr *deh_mgr, return 0; } - -void bridge_deh_release_dummy_mem(void) -{ -} diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdeh.h b/drivers/staging/tidspbridge/include/dspbridge/dspdeh.h index 4394711..af19926 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdeh.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdeh.h @@ -43,5 +43,4 @@ extern int bridge_deh_register_notify(struct deh_mgr *deh_mgr, extern void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo); -extern void bridge_deh_release_dummy_mem(void); #endif /* DSPDEH_ */ diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index c5a8b6b..b1979ce 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -1632,11 +1632,6 @@ int proc_stop(void *hprocessor) status = -EFAULT; goto func_end; } - if (DSP_SUCCEEDED((*p_proc_object->intf_fxns->pfn_brd_status) - (p_proc_object->hbridge_context, &brd_state))) { - if (brd_state == BRD_ERROR) - bridge_deh_release_dummy_mem(); - } /* check if there are any running nodes */ status = dev_get_node_manager(p_proc_object->hdev_obj, &hnode_mgr); if (DSP_SUCCEEDED(status) && hnode_mgr) { From patchwork Tue Jun 22 11:57:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Senthilvadivu Guruswamy X-Patchwork-Id: 107377 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MBvOaB005943 for ; Tue, 22 Jun 2010 11:57:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756416Ab0FVL5V (ORCPT ); Tue, 22 Jun 2010 07:57:21 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:60557 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756174Ab0FVL5U (ORCPT ); Tue, 22 Jun 2010 07:57:20 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MBvCi9004946 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 06:57:14 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MBv9WF013060; Tue, 22 Jun 2010 17:27:09 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o5MBv9tw016022; Tue, 22 Jun 2010 17:27:09 +0530 Received: (from a0876342@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o5MBv93k016020; Tue, 22 Jun 2010 17:27:09 +0530 From: Guruswamy Senthilvadivu To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, tony@atomide.com, tomi.valkeinen@nokia.com, hvaibhav@ti.com Cc: Senthilvadivu Guruswamy Subject: [PATCH v4 3/3] OMAP: DSS2: OMAPFB: Allow usage of def_vrfb only for omap2, 3 Date: Tue, 22 Jun 2010 17:27:07 +0530 Message-Id: <1277207827-15833-4-git-send-email-svadivu@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1277207827-15833-3-git-send-email-svadivu@ti.com> References: <1277207827-15833-1-git-send-email-svadivu@ti.com> <1277207827-15833-2-git-send-email-svadivu@ti.com> <1277207827-15833-3-git-send-email-svadivu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 11:57:24 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 4b4506d..0f79db8 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -2128,6 +2128,16 @@ static int omapfb_probe(struct platform_device *pdev) goto err0; } + /* TODO : Replace cpu check with omap_has_vrfb once HAS_FEATURE + * available for OMAP2 and OMAP3 + */ + if (def_vrfb && (!cpu_is_omap24xx()) && (!cpu_is_omap34xx())) { + def_vrfb = 0; + dev_warn(&pdev->dev, "VRFB is not in this device," + "using DMA for rotation\n"); + } + + mutex_init(&fbdev->mtx); fbdev->dev = &pdev->dev; From patchwork Tue Jun 22 11:57:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Senthilvadivu Guruswamy X-Patchwork-Id: 107376 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MBvMVF005935 for ; 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Tue, 22 Jun 2010 17:27:09 +0530 From: Guruswamy Senthilvadivu To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, tony@atomide.com, tomi.valkeinen@nokia.com, hvaibhav@ti.com Cc: Senthilvadivu Guruswamy Subject: [PATCH v4 1/3] OMAP: DSS2: OMAPFB: Allow FB_OMAP2 to build without VRFB Date: Tue, 22 Jun 2010 17:27:05 +0530 Message-Id: <1277207827-15833-2-git-send-email-svadivu@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1277207827-15833-1-git-send-email-svadivu@ti.com> References: <1277207827-15833-1-git-send-email-svadivu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 11:57:22 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h index d8a03ce..3792bde 100644 --- a/arch/arm/plat-omap/include/plat/vrfb.h +++ b/arch/arm/plat-omap/include/plat/vrfb.h @@ -35,6 +35,7 @@ struct vrfb { bool yuv_mode; }; +#ifdef CONFIG_OMAP2_VRFB extern int omap_vrfb_request_ctx(struct vrfb *vrfb); extern void omap_vrfb_release_ctx(struct vrfb *vrfb); extern void omap_vrfb_adjust_size(u16 *width, u16 *height, @@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot); extern void omap_vrfb_restore_context(void); +#else +static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; } +static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {} +static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, + u8 bytespp) {} +static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) + { return 0; } +static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) + { return 0; } +static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, + u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} +static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot) + { return 0; } +static inline void omap_vrfb_restore_context(void) {} +#endif #endif /* __VRFB_H */ From patchwork Mon Jun 14 22:27:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: omar ramirez X-Patchwork-Id: 106081 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5EMYNFu014484 for ; Mon, 14 Jun 2010 22:34:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757040Ab0FNWeW (ORCPT ); Mon, 14 Jun 2010 18:34:22 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:55616 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752027Ab0FNWeV (ORCPT ); Mon, 14 Jun 2010 18:34:21 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5EMYHB9031439 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 14 Jun 2010 17:34:17 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5EMYFZW028366; Mon, 14 Jun 2010 17:34:15 -0500 (CDT) Received: from localhost (bacab.am.dhcp.ti.com [128.247.77.143]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o5EMYFP01459; Mon, 14 Jun 2010 17:34:15 -0500 (CDT) From: Omar Ramirez Luna To: linux-omap Cc: Ameya Palande , Hiroshi Doyu , Felipe Contreras , Nishanth Menon , Ernesto Ramos Falcon , Shivananda Hebbar , Fernando Guzman Lugo , Ivan Gomez Castellanos , Omar Ramirez Luna Subject: [PATCH] DSPBRIDGE: driver version 0.3 Date: Mon, 14 Jun 2010 17:27:04 -0500 Message-Id: <1276554424-5464-1-git-send-email-omar.ramirez@ti.com> X-Mailer: git-send-email 1.7.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 14 Jun 2010 22:34:23 +0000 (UTC) diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c index cdc7f1b..f0f089b 100644 --- a/drivers/dsp/bridge/rmgr/drv_interface.c +++ b/drivers/dsp/bridge/rmgr/drv_interface.c @@ -69,7 +69,7 @@ #define BRIDGE_NAME "C6410" /* ----------------------------------- Globals */ #define DRIVER_NAME "DspBridge" -#define DSPBRIDGE_VERSION "0.2" +#define DSPBRIDGE_VERSION "0.3" s32 dsp_debug; struct platform_device *omap_dspbridge_dev; From patchwork Tue Jun 22 11:57:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Senthilvadivu Guruswamy X-Patchwork-Id: 107378 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MBvP9P005952 for ; Tue, 22 Jun 2010 11:57:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756853Ab0FVL5X (ORCPT ); Tue, 22 Jun 2010 07:57:23 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:59105 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756595Ab0FVL5W (ORCPT ); Tue, 22 Jun 2010 07:57:22 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MBvCis031734 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 06:57:14 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MBv9B3013058; Tue, 22 Jun 2010 17:27:09 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o5MBv96Y016017; Tue, 22 Jun 2010 17:27:09 +0530 Received: (from a0876342@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o5MBv9cU016015; Tue, 22 Jun 2010 17:27:09 +0530 From: Guruswamy Senthilvadivu To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, tony@atomide.com, tomi.valkeinen@nokia.com, hvaibhav@ti.com Cc: Guruswamy Senthilvadivu Subject: [PATCH v4 2/3] OMAP: DSS2: OMAPFB: make VRFB depends on OMAP2,3 Date: Tue, 22 Jun 2010 17:27:06 +0530 Message-Id: <1277207827-15833-3-git-send-email-svadivu@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1277207827-15833-2-git-send-email-svadivu@ti.com> References: <1277207827-15833-1-git-send-email-svadivu@ti.com> <1277207827-15833-2-git-send-email-svadivu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 11:57:25 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig index 43496d6..65149b2 100644 --- a/drivers/video/omap2/omapfb/Kconfig +++ b/drivers/video/omap2/omapfb/Kconfig @@ -3,7 +3,7 @@ menuconfig FB_OMAP2 depends on FB && OMAP2_DSS select OMAP2_VRAM - select OMAP2_VRFB + select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3 select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT From patchwork Mon May 3 06:18:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 96436 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o436JZWA009969 for ; Mon, 3 May 2010 06:19:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757199Ab0ECGTc (ORCPT ); Mon, 3 May 2010 02:19:32 -0400 Received: from smtp.nokia.com ([192.100.122.233]:30963 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755797Ab0ECGS5 (ORCPT ); Mon, 3 May 2010 02:18:57 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o436IcnY025773; Mon, 3 May 2010 09:18:54 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:18:51 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:18:50 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o436Igop008122; Mon, 3 May 2010 09:18:50 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v2 20/21] OMAP: DSS2: Taal: Add regulator configuration support Date: Mon, 3 May 2010 09:18:40 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: <1ef57e99d69aaf89b8e61074aa8ce2e5f6632d28.1272621452.git.ext-jani.1.nikula@nokia.com> <7a01973540a3afa79701ee08a3d8732db4687d5b.1272621452.git.ext-jani.1.nikula@nokia.com> <1a68710812da041ef583944411a1b7027d216c96.1272621452.git.ext-jani.1.nikula@nokia.com> <85172e14c23339065e319230f9707353409a901e.1272621452.git.ext-jani.1.nikula@nokia.com> <6e9febe4d2179309dcf93b7a8e897890c871f086.1272621452.git.ext-jani.1.nikula@nokia.com> <4004b06a47d3c1d20d6d8a30ddccdf536faeb5a0.1272621452.git.ext-jani.1.nikula@nokia.com> <5a5dc1e253df571477551b8f63560ad9d1a3ab2b.1272621452.git.ext-jani.1.nikula@nokia.com> <261f7b2c8cf1120e05d9664137e22ed237657c60.1272621452.git.ext-jani.1.nikula@nokia.com> <453fa1efec72cc2a4c029b6791c373a4a2e7ad7d.1272621452.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 03 May 2010 06:18:50.0837 (UTC) FILETIME=[7F75F850:01CAEA88] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 06:19:35 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index e209713..07832c4 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -68,6 +69,73 @@ static irqreturn_t taal_te_isr(int irq, void *data); static void taal_te_timeout_work_callback(struct work_struct *work); static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable); +struct panel_regulator { + struct regulator *regulator; + const char *name; + int min_uV; + int max_uV; +}; + +static void free_regulators(struct panel_regulator *regulators, int n) +{ + int i; + + for (i = 0; i < n; i++) { + /* disable/put in reverse order */ + regulator_disable(regulators[n - i - 1].regulator); + regulator_put(regulators[n - i - 1].regulator); + } +} + +static int init_regulators(struct omap_dss_device *dssdev, + struct panel_regulator *regulators, int n) +{ + int r, i, v; + + for (i = 0; i < n; i++) { + struct regulator *reg; + + reg = regulator_get(&dssdev->dev, regulators[i].name); + if (IS_ERR(reg)) { + dev_err(&dssdev->dev, "failed to get regulator %s\n", + regulators[i].name); + r = PTR_ERR(reg); + goto err; + } + + /* FIXME: better handling of fixed vs. variable regulators */ + v = regulator_get_voltage(reg); + if (v < regulators[i].min_uV || v > regulators[i].max_uV) { + r = regulator_set_voltage(reg, regulators[i].min_uV, + regulators[i].max_uV); + if (r) { + dev_err(&dssdev->dev, + "failed to set regulator %s voltage\n", + regulators[i].name); + regulator_put(reg); + goto err; + } + } + + r = regulator_enable(reg); + if (r) { + dev_err(&dssdev->dev, "failed to enable regulator %s\n", + regulators[i].name); + regulator_put(reg); + goto err; + } + + regulators[i].regulator = reg; + } + + return 0; + +err: + free_regulators(regulators, i); + + return r; +} + /** * struct panel_config - panel configuration * @name: panel name @@ -75,6 +143,8 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable); * @timings: panel resolution * @sleep: various panel specific delays, passed to msleep() if non-zero * @reset_sequence: reset sequence timings, passed to udelay() if non-zero + * @regulators: array of panel regulators + * @num_regulators: number of regulators in the array */ struct panel_config { const char *name; @@ -93,6 +163,9 @@ struct panel_config { unsigned int high; unsigned int low; } reset_sequence; + + struct panel_regulator *regulators; + int num_regulators; }; enum { @@ -629,6 +702,11 @@ static int taal_probe(struct omap_dss_device *dssdev) atomic_set(&td->do_update, 0); + r = init_regulators(dssdev, panel_config->regulators, + panel_config->num_regulators); + if (r) + goto err_reg; + td->esd_wq = create_singlethread_workqueue("taal_esd"); if (td->esd_wq == NULL) { dev_err(&dssdev->dev, "can't create ESD workqueue\n"); @@ -715,6 +793,8 @@ err_gpio: err_bl: destroy_workqueue(td->esd_wq); err_wq: + free_regulators(panel_config->regulators, panel_config->num_regulators); +err_reg: kfree(td); err: return r; @@ -747,6 +827,9 @@ static void taal_remove(struct omap_dss_device *dssdev) /* reset, to be sure that the panel is in a valid state */ taal_hw_reset(dssdev); + free_regulators(td->panel_config->regulators, + td->panel_config->num_regulators); + kfree(td); } From patchwork Wed Jun 30 16:00:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Egger X-Patchwork-Id: 108894 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5UG0jxO025007 for ; Wed, 30 Jun 2010 16:00:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932137Ab0F3QAp (ORCPT ); Wed, 30 Jun 2010 12:00:45 -0400 Received: from faui40.informatik.uni-erlangen.de ([131.188.34.40]:39986 "EHLO faui40.informatik.uni-erlangen.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932132Ab0F3QAn (ORCPT ); Wed, 30 Jun 2010 12:00:43 -0400 Received: from faui49p (faui49p.informatik.uni-erlangen.de [131.188.42.67]) by faui40.informatik.uni-erlangen.de (Postfix) with SMTP id A0D5D5F27C; Wed, 30 Jun 2010 18:00:41 +0200 (MEST) Received: by faui49p (sSMTP sendmail emulation); Wed, 30 Jun 2010 18:00:41 +0200 Date: Wed, 30 Jun 2010 18:00:41 +0200 From: Christoph Egger To: Tony Lindgren , Russell King , Jason Lam , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: vamos@i4.informatik.uni-erlangen.de Subject: [PATCH 21/33] Removing dead OMAP2_VENC_OUT_TYPE_SVIDEO, OMAP2_VENC_OUT_TYPE_COMPOSITE Message-ID: <2709d1406900af2436f6f8af00555507baf8dac9.1277911346.git.siccegge@cs.fau.de> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 30 Jun 2010 16:00:46 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index f848ba8..b38afd5 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -181,11 +181,6 @@ static struct omap_dss_device omap3_stalker_tv_device = { .name = "tv", .driver_name = "venc", .type = OMAP_DISPLAY_TYPE_VENC, -#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO) - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) - .u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, -#endif .platform_enable = omap3_stalker_enable_tv, .platform_disable = omap3_stalker_disable_tv, }; From patchwork Mon Mar 22 13:11:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 87421 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2MDBI9j011835 for ; Mon, 22 Mar 2010 13:11:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754584Ab0CVNLS (ORCPT ); Mon, 22 Mar 2010 09:11:18 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:35174 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754335Ab0CVNLR (ORCPT ); Mon, 22 Mar 2010 09:11:17 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2MDBCLv027213 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 22 Mar 2010 08:11:14 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2MDBAG5000529; Mon, 22 Mar 2010 18:41:10 +0530 (IST) From: hvaibhav@ti.com To: linux-omap@vger.kernel.org Cc: tomi.valkeinen@nokia.com, tony@atomide.com, Vaibhav Hiremath Subject: [PATCH 1/2] OMAP3EVM: Made backlight GPIO default state to off Date: Mon, 22 Mar 2010 18:41:09 +0530 Message-Id: <1269263470-13814-1-git-send-email-hvaibhav@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: References: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 22 Mar 2010 13:11:18 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 74bbdcb..f2a52c3 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -420,7 +420,10 @@ static int omap3evm_twl_gpio_setup(struct device *dev, /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); + else + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); /* gpio + 7 == DVI Enable */ gpio_request(gpio + 7, "EN_DVI"); From patchwork Fri May 21 06:52:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 101301 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4L6rvCR004307 for ; Fri, 21 May 2010 06:53:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758155Ab0EUGw7 (ORCPT ); Fri, 21 May 2010 02:52:59 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:33769 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753803Ab0EUGw6 (ORCPT ); Fri, 21 May 2010 02:52:58 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4L6qwtI029601 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 21 May 2010 01:52:58 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4L6qsE4007543; Fri, 21 May 2010 01:52:56 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Fri, 21 May 2010 12:22:57 +0530 (IST) Message-ID: <15445.10.24.255.17.1274424777.squirrel@dbdmail.itg.ti.com> Date: Fri, 21 May 2010 12:22:57 +0530 (IST) Subject: [RFC] [PATCH V2 1/2] input: CMA3000 Accelerometer driver From: "Hemanth V" To: linux-input@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 21 May 2010 06:53:58 +0000 (UTC) diff --git a/Documentation/input/cma3000_d0x.txt b/Documentation/input/cma3000_d0x.txt new file mode 100644 index 0000000..29ab6b7 --- /dev/null +++ b/Documentation/input/cma3000_d0x.txt @@ -0,0 +1,112 @@ +Kernel driver for CMA3000-D0x +============================ + +Supported chips: +* VTI CMA3000-D0x +Datasheet: + CMA3000-D0X Product Family Specification 8281000A.02.pdf + +Author: Hemanth V + + +Description +----------- +CMA3000 Tri-axis accelerometer supports Motion detect, Measurement and +Free fall modes. + +Motion Detect Mode: Its the low power mode where interrupts are generated only +when motion exceeds the defined thresholds. + +Measurement Mode: This mode is used to read the acceleration data on X,Y,Z +axis and supports 400, 100, 40 Hz sample frequency. + +Free fall Mode: This mode is intented to save system resources. + +Threshold values: Chip supports defining threshold values for above modes +which includes time and g value. Refer product specifications for more details. + +CMA3000 supports both I2C/SPI bus for communication, currently the driver +supports I2C based communication. + +Driver reports acceleration data through input subsystem and supports sysfs +for configuration changes. It generates ABS_MISC event with value 1 when +free fall is detected. + +Platform data need to be configured for initial default values. + +Platform Data +------------- +fuzz_x: Noise on X Axis + +fuzz_y: Noise on Y Axis + +fuzz_z: Noise on Z Axis + +g_range: G range in milli g i.e 2000 or 8000 + +mode: Default Operating mode + +mdthr: Motion detect threshold value + +mdfftmr: Motion detect and free fall time value + +ffthr: Free fall threshold value + +Input Interface +-------------- +Input driver version is 1.0.0 +Input device ID: bus 0x18 vendor 0x0 product 0x0 version 0x0 +Input device name: "cma3000-acclerometer" +Supported events: + Event type 0 (Sync) + Event type 3 (Absolute) + Event code 0 (X) + Value 47 + Min -8000 + Max 8000 + Fuzz 200 + Event code 1 (Y) + Value -28 + Min -8000 + Max 8000 + Fuzz 200 + Event code 2 (Z) + Value 905 + Min -8000 + Max 8000 + Fuzz 200 + Event code 40 (Misc) + Value 0 + Min 0 + Max 1 + Event type 4 (Misc) + +Sysfs entries +------------- + +mode: + 0: power down mode + 1: 100 Hz Measurement mode + 2: 400 Hz Measurement mode + 3: 40 Hz Measurement mode + 4: Motion Detect mode (default) + 5: 100 Hz Free fall mode + 6: 40 Hz Free fall mode + 7: Power off mode + +grange: + 2000: 2000 mg or 2G Range + 8000: 8000 mg or 8G Range + +mdthr: + X: X * 71mg (8G Range) + X: X * 18mg (2G Range) + +mdfftmr: + X: (X & 0x70) * 100 ms (MDTMR) + (X & 0x0F) * 2.5 ms (FFTMR 400 Hz) + (X & 0x0F) * 10 ms (FFTMR 100 Hz) + +ffthr: + X: (X >> 2) * 18mg (2G Range) + X: (X & 0x0F) * 71 mg (8G Range) diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 1cf25ee..043ee8d 100755 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -340,4 +340,11 @@ To compile this driver as a module, choose M here: the module will be called pcap_keys. +config INPUT_CMA3000_I2C + bool "VTI CMA3000 Tri-axis accelerometer" + depends on I2C && SYSFS + help + Say Y here if you want to use VTI CMA3000 Accelerometer + through I2C interface. + endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 07ee237..011161d 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o +obj-$(CONFIG_INPUT_CMA3000_I2C) += cma3000_d0x.o cma3000_d0x_i2c.o diff --git a/drivers/input/misc/cma3000_d0x.c b/drivers/input/misc/cma3000_d0x.c new file mode 100644 index 0000000..812c464 --- /dev/null +++ b/drivers/input/misc/cma3000_d0x.c @@ -0,0 +1,633 @@ +/* + * cma3000_d0x.c + * VTI CMA3000_D0x Accelerometer driver + * Supports I2C/SPI interfaces + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#include "cma3000_d0x.h" + +#define CMA3000_WHOAMI 0x00 +#define CMA3000_REVID 0x01 +#define CMA3000_CTRL 0x02 +#define CMA3000_STATUS 0x03 +#define CMA3000_RSTR 0x04 +#define CMA3000_INTSTATUS 0x05 +#define CMA3000_DOUTX 0x06 +#define CMA3000_DOUTY 0x07 +#define CMA3000_DOUTZ 0x08 +#define CMA3000_MDTHR 0x09 +#define CMA3000_MDFFTMR 0x0A +#define CMA3000_FFTHR 0x0B + +#define CMA3000_RANGE2G (1 << 7) +#define CMA3000_RANGE8G (0 << 7) +#define CMA3000_BUSI2C (0 << 4) +#define CMA3000_MODEMASK (7 << 1) +#define CMA3000_GRANGEMASK (1 << 7) + +#define CMA3000_STATUS_PERR 1 +#define CMA3000_INTSTATUS_FFDET (1 << 2) + +/* Settling time delay in ms */ +#define CMA3000_SETDELAY 30 + +/* Delay for clearing interrupt in us */ +#define CMA3000_INTDELAY 44 + + +/* + * Bit weights in mg for bit 0, other bits need + * multipy factor 2^n. Eight bit is the sign bit. + */ +#define BIT_TO_2G 18 +#define BIT_TO_8G 71 + +/* + * Conversion for each of the eight modes to g, depending + * on G range i.e 2G or 8G. Some modes always operate in + * 8G. + */ + +static int mode_to_mg[8][2] = { + {0, 0}, + {BIT_TO_8G, BIT_TO_2G}, + {BIT_TO_8G, BIT_TO_2G}, + {BIT_TO_8G, BIT_TO_8G}, + {BIT_TO_8G, BIT_TO_8G}, + {BIT_TO_8G, BIT_TO_2G}, + {BIT_TO_8G, BIT_TO_2G}, + {0, 0}, +}; + +static ssize_t cma3000_show_attr_mode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + uint8_t mode; + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_CTRL, "ctrl"); + if (mode < 0) + return mode; + + return sprintf(buf, "%d\n", (mode & CMA3000_MODEMASK) >> 1); +} + +static ssize_t cma3000_store_attr_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + uint8_t ctrl; + + error = strict_strtoul(buf, 0, &val); + if (error) + goto err_op3_failed; + + if (val < CMAMODE_DEFAULT || val > CMAMODE_POFF) { + error = -EINVAL; + goto err_op3_failed; + } + + mutex_lock(&data->mutex); + val &= (CMA3000_MODEMASK >> 1); + ctrl = cma3000_read(data, CMA3000_CTRL, "ctrl"); + if (ctrl < 0) { + error = ctrl; + goto err_op2_failed; + } + + ctrl &= ~CMA3000_MODEMASK; + ctrl |= (val << 1); + data->pdata.mode = val; + disable_irq(data->client->irq); + + error = cma3000_set(data, CMA3000_CTRL, ctrl, "ctrl"); + if (error < 0) + goto err_op1_failed; + + /* Settling time delay required after mode change */ + msleep(CMA3000_SETDELAY); + + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + return count; + +err_op1_failed: + enable_irq(data->client->irq); +err_op2_failed: + mutex_unlock(&data->mutex); +err_op3_failed: + return error; +} + +static ssize_t cma3000_show_attr_grange(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + uint8_t mode; + int g_range; + + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_CTRL, "ctrl"); + if (mode < 0) + return mode; + + g_range = (mode & CMA3000_GRANGEMASK) ? CMARANGE_2G : CMARANGE_8G; + return sprintf(buf, "%d\n", g_range); +} + +static ssize_t cma3000_store_attr_grange(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error, g_range, fuzz_x, fuzz_y, fuzz_z; + uint8_t ctrl; + + error = strict_strtoul(buf, 0, &val); + if (error) + goto err_op3_failed; + + mutex_lock(&data->mutex); + ctrl = cma3000_read(data, CMA3000_CTRL, "ctrl"); + if (ctrl < 0) { + error = ctrl; + goto err_op2_failed; + } + + ctrl &= ~CMA3000_GRANGEMASK; + + if (val == CMARANGE_2G) { + ctrl |= CMA3000_RANGE2G; + data->pdata.g_range = CMARANGE_2G; + } else if (val == CMARANGE_8G) { + ctrl |= CMA3000_RANGE8G; + data->pdata.g_range = CMARANGE_8G; + } else { + error = -EINVAL; + goto err_op2_failed; + } + + g_range = data->pdata.g_range; + fuzz_x = data->pdata.fuzz_x; + fuzz_y = data->pdata.fuzz_y; + fuzz_z = data->pdata.fuzz_z; + + disable_irq(data->client->irq); + error = cma3000_set(data, CMA3000_CTRL, ctrl, "ctrl"); + if (error < 0) + goto err_op1_failed; + + input_set_abs_params(data->input_dev, ABS_X, -g_range, + g_range, fuzz_x, 0); + input_set_abs_params(data->input_dev, ABS_Y, -g_range, + g_range, fuzz_y, 0); + input_set_abs_params(data->input_dev, ABS_Z, -g_range, + g_range, fuzz_z, 0); + + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + return count; + +err_op1_failed: + enable_irq(data->client->irq); +err_op2_failed: + mutex_unlock(&data->mutex); +err_op3_failed: + return error; +} + +static ssize_t cma3000_show_attr_mdthr(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + uint8_t mode; + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_MDTHR, "mdthr"); + if (mode < 0) + return mode; + + return sprintf(buf, "%d\n", mode); +} + +static ssize_t cma3000_store_attr_mdthr(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + mutex_lock(&data->mutex); + data->pdata.mdthr = val; + disable_irq(data->client->irq); + error = cma3000_set(data, CMA3000_MDTHR, val, "mdthr"); + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + /* If there was error during write, return error */ + if (error < 0) + return error; + else + return count; +} + +static ssize_t cma3000_show_attr_mdfftmr(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + uint8_t mode; + + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_MDFFTMR, "mdfftmr"); + if (mode < 0) + return mode; + + return sprintf(buf, "%d\n", mode); +} + +static ssize_t cma3000_store_attr_mdfftmr(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + mutex_lock(&data->mutex); + data->pdata.mdfftmr = val; + disable_irq(data->client->irq); + error = cma3000_set(data, CMA3000_MDFFTMR, val, "mdthr"); + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + /* If there was error during write, return error */ + if (error < 0) + return error; + else + return count; +} + +static ssize_t cma3000_show_attr_ffthr(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + uint8_t mode; + + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_FFTHR, "ffthr"); + if (mode < 0) + return mode; + + return sprintf(buf, "%d\n", mode); +} + +static ssize_t cma3000_store_attr_ffthr(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + mutex_lock(&data->mutex); + data->pdata.ffthr = val; + disable_irq(data->client->irq); + error = cma3000_set(data, CMA3000_FFTHR, val, "mdthr"); + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + /* If there was error during write, return error */ + if (error < 0) + return error; + else + return count; +} + +static DEVICE_ATTR(mode, S_IWUSR | S_IRUGO, + cma3000_show_attr_mode, cma3000_store_attr_mode); + +static DEVICE_ATTR(grange, S_IWUSR | S_IRUGO, + cma3000_show_attr_grange, cma3000_store_attr_grange); + +static DEVICE_ATTR(mdthr, S_IWUSR | S_IRUGO, + cma3000_show_attr_mdthr, cma3000_store_attr_mdthr); + +static DEVICE_ATTR(mdfftmr, S_IWUSR | S_IRUGO, + cma3000_show_attr_mdfftmr, cma3000_store_attr_mdfftmr); + +static DEVICE_ATTR(ffthr, S_IWUSR | S_IRUGO, + cma3000_show_attr_ffthr, cma3000_store_attr_ffthr); + + +static struct attribute *cma_attrs[] = { + &dev_attr_mode.attr, + &dev_attr_grange.attr, + &dev_attr_mdthr.attr, + &dev_attr_mdfftmr.attr, + &dev_attr_ffthr.attr, + NULL, +}; + +static struct attribute_group cma3000_attr_group = { + .attrs = cma_attrs, +}; + +static void decode_mg(struct cma3000_accl_data *data, int *datax, + int *datay, int *dataz) +{ + /* Data in 2's complement, convert to mg */ + *datax = (((s8)(*datax)) * (data->bit_to_mg)); + *datay = (((s8)(*datay)) * (data->bit_to_mg)); + *dataz = (((s8)(*dataz)) * (data->bit_to_mg)); +} + +static irqreturn_t cma3000_thread_irq(int irq, void *dev_id) +{ + struct cma3000_accl_data *data = dev_id; + int datax, datay, dataz; + u8 ctrl, mode, range, intr_status; + + intr_status = cma3000_read(data, CMA3000_INTSTATUS, "interrupt status"); + if (intr_status < 0) + return IRQ_NONE; + + /* Check if free fall is detected, report immediately */ + if (intr_status & CMA3000_INTSTATUS_FFDET) { + input_report_abs(data->input_dev, ABS_MISC, 1); + input_sync(data->input_dev); + } else { + input_report_abs(data->input_dev, ABS_MISC, 0); + } + + datax = cma3000_read(data, CMA3000_DOUTX, "X"); + datay = cma3000_read(data, CMA3000_DOUTY, "Y"); + dataz = cma3000_read(data, CMA3000_DOUTZ, "Z"); + + ctrl = cma3000_read(data, CMA3000_CTRL, "ctrl"); + mode = (ctrl & CMA3000_MODEMASK) >> 1; + range = (ctrl & CMA3000_GRANGEMASK) >> 7; + + data->bit_to_mg = mode_to_mg[mode][range]; + + /* Interrupt not for this device */ + if (data->bit_to_mg == 0) + return IRQ_NONE; + + /* Decode register values to milli g */ + decode_mg(data, &datax, &datay, &dataz); + + input_report_abs(data->input_dev, ABS_X, datax); + input_report_abs(data->input_dev, ABS_Y, datay); + input_report_abs(data->input_dev, ABS_Z, dataz); + input_sync(data->input_dev); + + return IRQ_HANDLED; +} + +static int cma3000_reset(struct cma3000_accl_data *data) +{ + int ret; + + /* Reset sequence */ + cma3000_set(data, CMA3000_RSTR, 0x02, "Reset"); + cma3000_set(data, CMA3000_RSTR, 0x0A, "Reset"); + cma3000_set(data, CMA3000_RSTR, 0x04, "Reset"); + + /* Settling time delay */ + mdelay(10); + + ret = cma3000_read(data, CMA3000_STATUS, "Status"); + if (ret < 0) { + dev_err(&data->client->dev, "Reset failed\n"); + return ret; + } else if (ret & CMA3000_STATUS_PERR) { + dev_err(&data->client->dev, "Parity Error\n"); + return -EIO; + } else { + return 0; + } +} + +int cma3000_poweron(struct cma3000_accl_data *data) +{ + uint8_t ctrl = 0, mdthr, mdfftmr, ffthr, mode; + int g_range, ret; + + g_range = data->pdata.g_range; + mode = data->pdata.mode; + mdthr = data->pdata.mdthr; + mdfftmr = data->pdata.mdfftmr; + ffthr = data->pdata.ffthr; + + if (mode < CMAMODE_DEFAULT || mode > CMAMODE_POFF) { + data->pdata.mode = CMAMODE_MOTDET; + mode = data->pdata.mode; + dev_info(&data->client->dev, + "Invalid mode specified, assuming Motion Detect\n"); + } + + if (g_range == CMARANGE_2G) { + ctrl = (mode << 1) | CMA3000_RANGE2G; + } else if (g_range == CMARANGE_8G) { + ctrl = (mode << 1) | CMA3000_RANGE8G; + } else { + dev_info(&data->client->dev, + "Invalid G range specified, assuming 8G\n"); + ctrl = (mode << 1) | CMA3000_RANGE8G; + data->pdata.g_range = CMARANGE_8G; + } +#ifdef CONFIG_INPUT_CMA3000_I2C + ctrl |= CMA3000_BUSI2C; +#endif + + cma3000_set(data, CMA3000_MDTHR, mdthr, "Motion Detect Threshold"); + cma3000_set(data, CMA3000_MDFFTMR, mdfftmr, "Time register"); + cma3000_set(data, CMA3000_FFTHR, ffthr, "Free fall threshold"); + ret = cma3000_set(data, CMA3000_CTRL, ctrl, "Mode setting"); + if (ret < 0) + return -EIO; + + mdelay(CMA3000_SETDELAY); + + return 0; +} + +int cma3000_poweroff(struct cma3000_accl_data *data) +{ + int ret; + + ret = cma3000_set(data, CMA3000_CTRL, CMAMODE_POFF, "Mode setting"); + mdelay(CMA3000_SETDELAY); + + return ret; +} + +int cma3000_init(struct cma3000_accl_data *data) +{ + int ret = 0, fuzz_x, fuzz_y, fuzz_z, g_range; + uint32_t irqflags; + + if (data->client->dev.platform_data == NULL) { + dev_err(&data->client->dev, "platform data not found\n"); + goto err_op2_failed; + } + + memcpy(&(data->pdata), data->client->dev.platform_data, + sizeof(struct cma3000_platform_data)); + + ret = cma3000_reset(data); + if (ret) + goto err_op2_failed; + + ret = cma3000_read(data, CMA3000_REVID, "Revid"); + if (ret < 0) + goto err_op2_failed; + + pr_info("CMA3000 Acclerometer : Revision %x\n", ret); + + /* Bring it out of default power down state */ + ret = cma3000_poweron(data); + if (ret < 0) + goto err_op2_failed; + + fuzz_x = data->pdata.fuzz_x; + fuzz_y = data->pdata.fuzz_y; + fuzz_z = data->pdata.fuzz_z; + g_range = data->pdata.g_range; + irqflags = data->pdata.irqflags; + + data->input_dev = input_allocate_device(); + if (data->input_dev == NULL) { + ret = -ENOMEM; + dev_err(&data->client->dev, + "Failed to allocate input device\n"); + goto err_op2_failed; + } + + data->input_dev->name = "cma3000-acclerometer"; + +#ifdef CONFIG_INPUT_CMA3000_I2C + data->input_dev->id.bustype = BUS_I2C; +#endif + + __set_bit(EV_ABS, data->input_dev->evbit); + __set_bit(EV_MSC, data->input_dev->evbit); + + input_set_abs_params(data->input_dev, ABS_X, -g_range, + g_range, fuzz_x, 0); + input_set_abs_params(data->input_dev, ABS_Y, -g_range, + g_range, fuzz_y, 0); + input_set_abs_params(data->input_dev, ABS_Z, -g_range, + g_range, fuzz_z, 0); + input_set_abs_params(data->input_dev, ABS_MISC, 0, + 1, 0, 0); + + ret = input_register_device(data->input_dev); + if (ret) { + dev_err(&data->client->dev, + "Unable to register input device\n"); + goto err_op2_failed; + } + + mutex_init(&data->mutex); + + if (data->client->irq) { + ret = request_threaded_irq(data->client->irq, NULL, + cma3000_thread_irq, + irqflags | IRQF_ONESHOT, + data->client->name, data); + + if (ret < 0) { + dev_err(&data->client->dev, + "request_threaded_irq failed\n"); + goto err_op1_failed; + } + } + + ret = sysfs_create_group(&data->client->dev.kobj, &cma3000_attr_group); + if (ret) { + dev_err(&data->client->dev, + "failed to create sysfs entries\n"); + goto err_op1_failed; + } + return 0; + +err_op1_failed: + mutex_destroy(&data->mutex); + input_unregister_device(data->input_dev); +err_op2_failed: + if (data != NULL) { + if (data->input_dev != NULL) + input_free_device(data->input_dev); + } + + return ret; +} + +int cma3000_exit(struct cma3000_accl_data *data) +{ + int ret; + + ret = cma3000_poweroff(data); + + if (data->client->irq) + free_irq(data->client->irq, data); + + mutex_destroy(&data->mutex); + input_unregister_device(data->input_dev); + input_free_device(data->input_dev); + sysfs_remove_group(&data->client->dev.kobj, &cma3000_attr_group); + return ret; +} diff --git a/drivers/input/misc/cma3000_d0x.h b/drivers/input/misc/cma3000_d0x.h new file mode 100644 index 0000000..12a8faf --- /dev/null +++ b/drivers/input/misc/cma3000_d0x.h @@ -0,0 +1,46 @@ +/* + * cma3000_d0x.h + * VTI CMA3000_D0x Accelerometer driver + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef INPUT_CMA3000_H +#define INPUT_CMA3000_H + +#include +#include + +struct cma3000_accl_data { +#ifdef CONFIG_INPUT_CMA3000_I2C + struct i2c_client *client; +#endif + struct input_dev *input_dev; + struct cma3000_platform_data pdata; + + /* mutex for sysfs operations */ + struct mutex mutex; + int bit_to_mg; +}; + +int cma3000_set(struct cma3000_accl_data *, u8, u8, char *); +int cma3000_read(struct cma3000_accl_data *, u8, char *); +int cma3000_init(struct cma3000_accl_data *); +int cma3000_exit(struct cma3000_accl_data *); +int cma3000_poweron(struct cma3000_accl_data *); +int cma3000_poweroff(struct cma3000_accl_data *); + +#endif diff --git a/drivers/input/misc/cma3000_d0x_i2c.c b/drivers/input/misc/cma3000_d0x_i2c.c new file mode 100644 index 0000000..41f845c --- /dev/null +++ b/drivers/input/misc/cma3000_d0x_i2c.c @@ -0,0 +1,136 @@ +/* + * cma3000_d0x_i2c.c + * + * Implements I2C interface for VTI CMA300_D0x Accelerometer driver + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include "cma3000_d0x.h" + +int cma3000_set(struct cma3000_accl_data *accl, u8 reg, u8 val, char *msg) +{ + int ret = i2c_smbus_write_byte_data(accl->client, reg, val); + if (ret < 0) + dev_err(&accl->client->dev, + "i2c_smbus_write_byte_data failed (%s)\n", msg); + return ret; +} + +int cma3000_read(struct cma3000_accl_data *accl, u8 reg, char *msg) +{ + int ret = i2c_smbus_read_byte_data(accl->client, reg); + if (ret < 0) + dev_err(&accl->client->dev, + "i2c_smbus_read_byte_data failed (%s)\n", msg); + return ret; +} + +static int __devinit cma3000_accl_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + struct cma3000_accl_data *data = NULL; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (data == NULL) { + ret = -ENOMEM; + goto err_op_failed; + } + + data->client = client; + i2c_set_clientdata(client, data); + + ret = cma3000_init(data); + if (ret) + goto err_op_failed; + + return 0; + +err_op_failed: + + if (data != NULL) + kfree(data); + + return ret; +} + +static int __devexit cma3000_accl_remove(struct i2c_client *client) +{ + struct cma3000_accl_data *data = i2c_get_clientdata(client); + int ret; + + ret = cma3000_exit(data); + i2c_set_clientdata(client, NULL); + kfree(data); + + return ret; +} + +#ifdef CONFIG_PM +static int cma3000_accl_suspend(struct i2c_client *client, pm_message_t mesg) +{ + struct cma3000_accl_data *data = i2c_get_clientdata(client); + + return cma3000_poweroff(data); +} + +static int cma3000_accl_resume(struct i2c_client *client) +{ + struct cma3000_accl_data *data = i2c_get_clientdata(client); + + return cma3000_poweron(data); +} +#endif + +static const struct i2c_device_id cma3000_id[] = { + { "cma3000_accl", 0 }, + { }, +}; + +static struct i2c_driver cma3000_accl_driver = { + .probe = cma3000_accl_probe, + .remove = cma3000_accl_remove, + .id_table = cma3000_id, +#ifdef CONFIG_PM + .suspend = cma3000_accl_suspend, + .resume = cma3000_accl_resume, +#endif + .driver = { + .name = "cma3000_accl" + }, +}; + +static int __init cma3000_accl_init(void) +{ + return i2c_add_driver(&cma3000_accl_driver); +} + +static void __exit cma3000_accl_exit(void) +{ + i2c_del_driver(&cma3000_accl_driver); +} + +module_init(cma3000_accl_init); +module_exit(cma3000_accl_exit); + +MODULE_DESCRIPTION("CMA3000-D0x Accelerometer Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Hemanth V "); diff --git a/include/linux/i2c/cma3000.h b/include/linux/i2c/cma3000.h new file mode 100644 index 0000000..50aa3fc --- /dev/null +++ b/include/linux/i2c/cma3000.h @@ -0,0 +1,60 @@ +/* + * cma3000.h + * VTI CMA300_Dxx Accelerometer driver + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef _LINUX_CMA3000_I2C_H +#define _LINUX_CMA3000_I2C_H + +#define CMAMODE_DEFAULT 0 +#define CMAMODE_MEAS100 1 +#define CMAMODE_MEAS400 2 +#define CMAMODE_MEAS40 3 +#define CMAMODE_MOTDET 4 +#define CMAMODE_FF100 5 +#define CMAMODE_FF400 6 +#define CMAMODE_POFF 7 + +#define CMARANGE_2G 2000 +#define CMARANGE_8G 8000 + +/** + * struct cma3000_i2c_platform_data - CMA3000 Platform data + * @fuzz_x: Noise on X Axis + * @fuzz_y: Noise on Y Axis + * @fuzz_z: Noise on Z Axis + * @g_range: G range in milli g i.e 2000 or 8000 + * @mode: Operating mode + * @mdthr: Motion detect threshold value + * @mdfftmr: Motion detect and free fall time value + * @ffthr: Free fall threshold value + */ + +struct cma3000_platform_data { + int fuzz_x; + int fuzz_y; + int fuzz_z; + int g_range; + uint8_t mode; + uint8_t mdthr; + uint8_t mdfftmr; + uint8_t ffthr; + uint32_t irqflags; +}; + +#endif From patchwork Wed Jul 7 14:12:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 110649 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o67ECW7T010675 for ; Wed, 7 Jul 2010 14:12:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755940Ab0GGOMa (ORCPT ); Wed, 7 Jul 2010 10:12:30 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59972 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755234Ab0GGOM3 (ORCPT ); Wed, 7 Jul 2010 10:12:29 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o67ECRDd012159 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 7 Jul 2010 09:12:27 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o67ECLJe000014; Wed, 7 Jul 2010 09:12:22 -0500 (CDT) Received: from 10.24.255.18 (SquirrelMail authenticated user x0099945); by dbdmail.itg.ti.com with HTTP; Wed, 7 Jul 2010 19:42:24 +0530 (IST) Message-ID: <20809.10.24.255.18.1278511944.squirrel@dbdmail.itg.ti.com> Date: Wed, 7 Jul 2010 19:42:24 +0530 (IST) Subject: [PATCH v6] OMAP4 HSMMC: Adding Card detect support for MMC1 on OMAP4 From: "kishore kadiyala" To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: tony@atomide.com, madhu.cr@ti.com, adrian.hunter@nokia.com User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 14:12:32 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index f287461..388b96d 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -227,9 +227,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) struct omap_mmc_platform_data *pdata = dev->platform_data; /* Setting MMC1 Card detect Irq */ - if (pdev->id == 0) + if (pdev->id == 0) { + ret = twl6030_mmc_card_detect_config(); + if (ret) + pr_err("Failed configuring MMC1 card detect\n"); pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET; + pdata->slots[0].card_detect = twl6030_mmc_card_detect; + } return ret; } diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c index 10bf228..c027692 100644 --- a/drivers/mfd/twl6030-irq.c +++ b/drivers/mfd/twl6030-irq.c @@ -36,6 +36,7 @@ #include #include #include +#include /* * TWL6030 (unlike its predecessors, which had two level interrupt handling) @@ -223,6 +224,81 @@ int twl6030_interrupt_mask(u8 bit_mask, u8 offset) } EXPORT_SYMBOL(twl6030_interrupt_mask); +int twl6030_mmc_card_detect_config(void) +{ + int ret; + u8 reg_val = 0; + + /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */ + if (twl_class_is_6030()) { + twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, + REG_INT_MSK_LINE_B); + twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, + REG_INT_MSK_STS_B); + } + + /* + * Intially Configuring MMC_CTRL for receving interrupts & + * Card status on TWL6030 for MMC1 + */ + ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL); + if (ret < 0) { + pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret); + return ret; + } + reg_val &= ~VMMC_AUTO_OFF; + reg_val |= SW_FC; + ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL); + if (ret < 0) { + return ret; + pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret); + } + + /* Configuring PullUp-PullDown register */ + ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, + TWL6030_CFG_INPUT_PUPD3); + if (ret < 0) { + return ret; + pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n", + ret); + } + reg_val &= ~(MMC_PU | MMC_PD); + ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, + TWL6030_CFG_INPUT_PUPD3); + if (ret < 0) { + pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n", + ret); + return ret; + } + return 0; +} +EXPORT_SYMBOL(twl6030_mmc_card_detect_config); + +int twl6030_mmc_card_detect(struct device *dev, int slot) +{ + int ret = -EIO; + u8 read_reg; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + + switch (pdev->id) { + case 0: + /* + * BIT0 of REG_MMC_CTRL + * 0 - Card not present ,1 - Card present + */ + ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg, + TWL6030_MMCCTRL); + if (ret >= 0) + ret = read_reg & STS_MMC; + break; + default: + pr_err("Unkown MMC controller %d in %s\n", pdev->id, __func__); + } + return ret; +} +EXPORT_SYMBOL(twl6030_mmc_card_detect); + int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) { diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b032828..c047b13 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -464,8 +464,6 @@ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) int ret; if (gpio_is_valid(pdata->slots[0].switch_pin)) { - pdata->suspend = omap_hsmmc_suspend_cdirq; - pdata->resume = omap_hsmmc_resume_cdirq; if (pdata->slots[0].cover) pdata->slots[0].get_cover_state = omap_hsmmc_get_cover_state; @@ -2170,6 +2168,8 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) "Unable to grab MMC CD IRQ\n"); goto err_irq_cd; } + pdata->suspend = omap_hsmmc_suspend_cdirq; + pdata->resume = omap_hsmmc_resume_cdirq; } omap_hsmmc_disable_irq(host); diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 6de90bf..9493292 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -141,6 +141,16 @@ #define TWL6030_CHARGER_CTRL_INT_MASK 0x10 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60 +#define TWL6030_MMCCTRL 0xEE +#define VMMC_AUTO_OFF (0x1 << 3) +#define SW_FC (0x1 << 2) +#define STS_MMC 0x1 + +#define TWL6030_CFG_INPUT_PUPD3 0xF2 +#define MMC_PU (0x1 << 3) +#define MMC_PD (0x1 << 2) + + #define TWL4030_CLASS_ID 0x4030 #define TWL6030_CLASS_ID 0x6030 @@ -173,6 +183,12 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); int twl6030_interrupt_mask(u8 bit_mask, u8 offset); +/* Card detect Configuration for MMC1 Controller on OMAP4 */ +int twl6030_mmc_card_detect_config(void); + +/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ +int twl6030_mmc_card_detect(struct device *dev, int slot); + /*----------------------------------------------------------------------*/ /* From patchwork Fri May 21 06:53:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 101303 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4L6rvCT004307 for ; Fri, 21 May 2010 06:53:59 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932145Ab0EUGxI (ORCPT ); Fri, 21 May 2010 02:53:08 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:33772 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758173Ab0EUGxF (ORCPT ); Fri, 21 May 2010 02:53:05 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4L6r5Th029607 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 21 May 2010 01:53:05 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4L6r2pF028910; Fri, 21 May 2010 01:53:03 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Fri, 21 May 2010 12:23:04 +0530 (IST) Message-ID: <15504.10.24.255.17.1274424784.squirrel@dbdmail.itg.ti.com> Date: Fri, 21 May 2010 12:23:04 +0530 (IST) Subject: [RFC ] [PATCH V2 2/2] Platform changes for CMA3000 From: "Hemanth V" To: linux-input@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 21 May 2010 06:53:59 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 3005558..b5b3d0b 100755 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -19,9 +19,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -66,6 +68,8 @@ static struct platform_device sdp4430_proximity_device = { }, }; +#define OMAP4_CMA3000ACCL_GPIO 186 + static int sdp4430_keymap[] = { KEY(0, 0, KEY_E), KEY(0, 1, KEY_R), @@ -575,6 +579,18 @@ static struct twl4030_platform_data sdp4430_twldata = { .vaux3 = &sdp4430_vaux3, }; +static struct cma3000_platform_data cma3000_platform_data = { + .fuzz_x = 25, + .fuzz_y = 25, + .fuzz_z = 25, + .g_range = CMARANGE_8G, + .mode = CMAMODE_MOTDET, + .mdthr = 0x8, + .mdfftmr = 0x33, + .ffthr = 0x8, + .irqflags = IRQF_TRIGGER_HIGH, +}; + static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { { I2C_BOARD_INFO("twl6030", 0x48), @@ -598,6 +614,14 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { }, }; +static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { + { + I2C_BOARD_INFO("cma3000_accl", 0x1c), + .platform_data = &cma3000_platform_data, + .irq = OMAP_GPIO_IRQ(OMAP4_CMA3000ACCL_GPIO), + }, +}; + static int __init omap4_i2c_init(void) { /* Phoenix Audio IC needs I2C1 to start with 400 KHz and less */ @@ -607,7 +631,8 @@ static int __init omap4_i2c_init(void) ARRAY_SIZE(sdp4430_i2c_2_boardinfo)); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); - omap_register_i2c_bus(4, 400, NULL, 0); + omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo, + ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); return 0; } @@ -661,6 +686,15 @@ fail1: gpio_free(OMAP4_SFH7741_SENSOR_OUTPUT_GPIO); } +static void omap_cma3000accl_init(void) +{ + if (gpio_request(OMAP4_CMA3000ACCL_GPIO, "Accelerometer") < 0) { + pr_err("Accelerometer GPIO request failed\n"); + return; + } + gpio_direction_input(OMAP4_CMA3000ACCL_GPIO); +} + static void __init omap_4430sdp_init(void) { int status; @@ -686,6 +720,7 @@ static void __init omap_4430sdp_init(void) ARRAY_SIZE(sdp4430_spi_board_info)); } omap_sfh7741prox_init(); + omap_cma3000accl_init(); } static void __init omap_4430sdp_map_io(void) From patchwork Wed May 5 08:42:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 97015 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o458fPBA026907 for ; Wed, 5 May 2010 08:42:43 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933851Ab0EEIld (ORCPT ); Wed, 5 May 2010 04:41:33 -0400 Received: from smtp.nokia.com ([192.100.122.233]:37648 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933838Ab0EEIl3 (ORCPT ); Wed, 5 May 2010 04:41:29 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458fHxb028291; Wed, 5 May 2010 11:41:21 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:17 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:16 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458f1LG016327; Wed, 5 May 2010 11:41:10 +0300 From: Eduardo Valentin To: linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: ext Tony Lindgren , ext Kevin Hilman , "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , santosh.shilimkar@ti.com, felipe.balbi@nokia.com, Eduardo Valentin Subject: [RESEND PATCHv3 3/4] mach-omap1: Add SoC info data for OMAP1 into /proc/cpuinfo Date: Wed, 5 May 2010 11:42:07 +0300 Message-Id: <1273048928-6105-4-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> References: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 05 May 2010 08:41:16.0860 (UTC) FILETIME=[BA1D17C0:01CAEC2E] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 08:42:44 +0000 (UTC) diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index a0e3560..9a84347 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -120,7 +120,7 @@ static u8 __init omap_get_die_rev(void) void __init omap_check_revision(void) { - int i; + int i, sz; u16 jtag_id; u8 die_rev; u32 omap_id; @@ -194,11 +194,14 @@ void __init omap_check_revision(void) printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type); } - printk(KERN_INFO "OMAP%04x", omap_revision >> 16); + sz = snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "OMAP%04x", + omap_revision >> 16); if ((omap_revision >> 8) & 0xff) - printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff); - printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n", - die_rev, omap_revision & 0xff, system_serial_low, - system_serial_high); + snprintf(system_soc_info + sz, SYSTEM_SOC_INFO_SIZE - sz, + "%x", (omap_revision >> 8) & 0xff); + pr_info("%s revision %i handled as %02xxx id: %08x%08x\n", + system_soc_info, die_rev, omap_revision & 0xff, + system_serial_low, system_serial_high); + } From patchwork Wed May 5 08:42:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 97014 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o458fPB9026907 for ; Wed, 5 May 2010 08:42:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933821Ab0EEIlc (ORCPT ); Wed, 5 May 2010 04:41:32 -0400 Received: from smtp.nokia.com ([192.100.122.233]:37647 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933833Ab0EEIl3 (ORCPT ); Wed, 5 May 2010 04:41:29 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458fCAb028253; Wed, 5 May 2010 11:41:20 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:10 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:10 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458f1LE016327; Wed, 5 May 2010 11:41:05 +0300 From: Eduardo Valentin To: linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: ext Tony Lindgren , ext Kevin Hilman , "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , santosh.shilimkar@ti.com, felipe.balbi@nokia.com, Eduardo Valentin Subject: [RESEND PATCHv3 1/4] ARM: Introduce SoC Info into /proc/cpuinfo Date: Wed, 5 May 2010 11:42:05 +0300 Message-Id: <1273048928-6105-2-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> References: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 05 May 2010 08:41:10.0945 (UTC) FILETIME=[B6968910:01CAEC2E] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 08:42:38 +0000 (UTC) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4ace45e..53a9645 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -71,6 +71,8 @@ struct task_struct; extern unsigned int system_rev; extern unsigned int system_serial_low; extern unsigned int system_serial_high; +#define SYSTEM_SOC_INFO_SIZE 128 +extern char system_soc_info[SYSTEM_SOC_INFO_SIZE]; extern unsigned int mem_fclk_21285; struct pt_regs; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c91c77b..025d795 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -85,6 +85,9 @@ EXPORT_SYMBOL(system_serial_low); unsigned int system_serial_high; EXPORT_SYMBOL(system_serial_high); +char system_soc_info[SYSTEM_SOC_INFO_SIZE]; +EXPORT_SYMBOL(system_soc_info); + unsigned int elf_hwcap; EXPORT_SYMBOL(elf_hwcap); @@ -847,6 +850,8 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "Revision\t: %04x\n", system_rev); seq_printf(m, "Serial\t\t: %08x%08x\n", system_serial_high, system_serial_low); + if (strlen(system_soc_info)) + seq_printf(m, "SoC Info\t: %s\n", system_soc_info); return 0; } From patchwork Tue May 4 16:01:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 96818 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o44G1kkm014128 for ; Tue, 4 May 2010 16:01:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932134Ab0EDQBo (ORCPT ); Tue, 4 May 2010 12:01:44 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:58134 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932084Ab0EDQBn (ORCPT ); Tue, 4 May 2010 12:01:43 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o44G1XpE020816 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 4 May 2010 11:01:33 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o44G1Rh6018373; Tue, 4 May 2010 11:01:28 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099945); by dbdmail.itg.ti.com with HTTP; Tue, 4 May 2010 21:31:30 +0530 (IST) Message-ID: <35156.10.24.255.17.1272988890.squirrel@dbdmail.itg.ti.com> Date: Tue, 4 May 2010 21:31:30 +0530 (IST) Subject: [PATCH v2 2/5] OMAP4-HSMMC: Adding Card detect support From: "kishore kadiyala" To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: tony@atomide.com, madhu.cr@ti.com, jarkko.lavinen@nokia.com, rmk@arm.linux.org.uk, paul@pwsan.com User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 04 May 2010 16:01:49 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index c4e61d5..41fbffe 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -102,6 +102,7 @@ static struct omap2_hsmmc_info mmc[] = { * but is a phoenix interrupt */ .gpio_cd = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET, + .cd_type = true, .gpio_wp = -EINVAL, }, { diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 9ad2295..f5ca16c 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -189,6 +190,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info mmc->get_context_loss_count = hsmmc_get_context_loss; mmc->slots[0].switch_pin = c->gpio_cd; + mmc->slots[0].nongpio_cd = c->cd_type; mmc->slots[0].gpio_wp = c->gpio_wp; mmc->slots[0].remux = c->remux; diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8..3dfc43a 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -17,6 +17,7 @@ struct omap2_hsmmc_info { bool no_off; /* power_saving and power is not to go off */ bool vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */ int gpio_cd; /* or -EINVAL */ + bool cd_type; /* Card detect Type:NON-GPIO=true,GPIO=flase */ int gpio_wp; /* or -EINVAL */ char *name; /* or NULL for default */ struct device *dev; /* returned: pointer to mmc adapter */ diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index a1bac07..8458a8b 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -14,6 +14,7 @@ #include #include #include +#include #include @@ -103,6 +104,7 @@ struct omap_mmc_platform_data { unsigned vcc_aux_disable_is_sleep:1; int switch_pin; /* gpio (card detect) */ + unsigned nongpio_cd:1; /* NON-GPIO=true , GPIO=false */ int gpio_wp; /* gpio (write protect) */ int (*set_bus_mode)(struct device *dev, int slot, int bus_mode); diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c index 10bf228..da3d4ec 100644 --- a/drivers/mfd/twl6030-irq.c +++ b/drivers/mfd/twl6030-irq.c @@ -36,6 +36,7 @@ #include #include #include +#include /* * TWL6030 (unlike its predecessors, which had two level interrupt handling) @@ -223,6 +224,32 @@ int twl6030_interrupt_mask(u8 bit_mask, u8 offset) } EXPORT_SYMBOL(twl6030_interrupt_mask); +int twl6030_mmc_card_detect(struct device *dev, int slot) +{ + int ret = -ENOSYS; + int res = 0; + u8 read_reg; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + + switch (pdev->id) { + case 0: + /* + * BIT0 of REG_MMC_CTRL + * 0 - Card not present ,1 - Card present + */ + res = twl_i2c_read_u8(TWL6030_MODULE_ID0, + &read_reg, TWL6030_MMCCTRL); + if (res >= 0) + ret = read_reg & 0x1; + break; + default: + pr_err("Unkown MMC controller %d in %s\n", pdev->id, __func__); + } + return ret; +} +EXPORT_SYMBOL(twl6030_mmc_card_detect); + int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) { diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index e9caf69..ac903b0 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -505,6 +505,18 @@ err_free_sp: return ret; } +static int omap_hsmmc_non_gpio_init(struct omap_mmc_platform_data *pdata) +{ + if (pdata->slots[0].switch_pin) { + pdata->suspend = omap_hsmmc_suspend_cdirq; + pdata->resume = omap_hsmmc_resume_cdirq; + pdata->slots[0].card_detect = twl6030_mmc_card_detect; + pdata->slots[0].card_detect_irq = pdata->slots[0].switch_pin; + return 0; + } + return -1; +} + static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) { if (gpio_is_valid(pdata->slots[0].gpio_wp)) @@ -1977,7 +1989,11 @@ static int __init omap_hsmmc_probe(struct platform_device if (res == NULL) return -EBUSY; - ret = omap_hsmmc_gpio_init(pdata); + if (!pdata->slots[0].nongpio_cd) + ret = omap_hsmmc_gpio_init(pdata); + else + ret = omap_hsmmc_non_gpio_init(pdata); + if (ret) goto err; diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index fb6784e..eb198db 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -141,6 +141,7 @@ #define TWL6030_CHARGER_CTRL_INT_MASK 0x10 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60 +#define TWL6030_MMCCTRL 0xEE #define TWL4030_CLASS_ID 0x4030 #define TWL6030_CLASS_ID 0x6030 @@ -173,6 +174,11 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); int twl6030_interrupt_mask(u8 bit_mask, u8 offset); +/* + * MMC1 Controller on OMAP4 uses Phoenix Irq for Card detect. + */ +int twl6030_mmc_card_detect(struct device *dev, int slot); + /*----------------------------------------------------------------------*/ /* From patchwork Wed May 5 08:42:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 97013 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o458fPB8026907 for ; Wed, 5 May 2010 08:42:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933850Ab0EEIla (ORCPT ); Wed, 5 May 2010 04:41:30 -0400 Received: from smtp.nokia.com ([192.100.122.233]:37642 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933821Ab0EEIl2 (ORCPT ); Wed, 5 May 2010 04:41:28 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458eoxd027876; Wed, 5 May 2010 11:41:19 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:13 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:12 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458f1LF016327; Wed, 5 May 2010 11:41:07 +0300 From: Eduardo Valentin To: linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: ext Tony Lindgren , ext Kevin Hilman , "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , santosh.shilimkar@ti.com, felipe.balbi@nokia.com, Eduardo Valentin Subject: [RESEND PATCHv3 2/4] mach-omap2: Add SoC info data for OMAP2, 3, 4 into /proc/cpuinfo Date: Wed, 5 May 2010 11:42:06 +0300 Message-Id: <1273048928-6105-3-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> References: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 05 May 2010 08:41:13.0492 (UTC) FILETIME=[B81B2D40:01CAEC2E] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 08:42:24 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a..4702ffe 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -104,7 +104,7 @@ static u16 tap_prod_id; void __init omap24xx_check_revision(void) { - int i, j; + int i, j, sz; u32 idcode, prod_id; u16 hawkeye; u8 dev_type, rev; @@ -152,10 +152,12 @@ void __init omap24xx_check_revision(void) j = i; } - pr_info("OMAP%04x", omap_rev() >> 16); + sz = snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "OMAP%04x", + omap_rev() >> 16); if ((omap_rev() >> 8) & 0x0f) - pr_info("ES%x", (omap_rev() >> 12) & 0xf); - pr_info("\n"); + snprintf(system_soc_info + sz, SYSTEM_SOC_INFO_SIZE - sz, + "ES%x", (omap_rev() >> 12) & 0xf); + pr_info("%s\n", system_soc_info); } #define OMAP3_CHECK_FEATURE(status,feat) \ @@ -286,7 +288,9 @@ void __init omap4_check_revision(void) if ((hawkeye == 0xb852) && (rev == 0x0)) { omap_revision = OMAP4430_REV_ES1_0; omap_chip.oc |= CHIP_IS_OMAP4430ES1; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); + snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "OMAP%04x %s\n", + omap_rev() >> 16, rev_name); + pr_info("%s\n", system_soc_info); return; } @@ -356,7 +360,9 @@ void __init omap3_cpuinfo(void) } /* Print verbose information */ - pr_info("%s ES%s (", cpu_name, cpu_rev); + snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "%s ES%s", cpu_name, + cpu_rev); + pr_info("%s (", system_soc_info); OMAP3_SHOW_FEATURE(l2cache); OMAP3_SHOW_FEATURE(iva); From patchwork Wed May 5 08:42:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 97012 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o458fPB6026907 for ; Wed, 5 May 2010 08:41:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933844Ab0EEIl3 (ORCPT ); Wed, 5 May 2010 04:41:29 -0400 Received: from smtp.nokia.com ([192.100.105.134]:48929 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932189Ab0EEIl1 (ORCPT ); Wed, 5 May 2010 04:41:27 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458f3hH026208; Wed, 5 May 2010 03:41:20 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:19 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 11:41:18 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o458f1LH016327; Wed, 5 May 2010 11:41:13 +0300 From: Eduardo Valentin To: linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: ext Tony Lindgren , ext Kevin Hilman , "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , santosh.shilimkar@ti.com, felipe.balbi@nokia.com, Eduardo Valentin Subject: [RESEND PATCHv3 4/4] OMAP3: export chip IDCODE, Production ID and Die ID Date: Wed, 5 May 2010 11:42:08 +0300 Message-Id: <1273048928-6105-5-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> References: <1273048928-6105-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 05 May 2010 08:41:19.0258 (UTC) FILETIME=[BB8AFFA0:01CAEC2E] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 08:41:59 +0000 (UTC) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 839b21b..6a84e6c 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1809,6 +1809,8 @@ and is between 256 and 4096 characters. It is defined in the file waiting for the ACK, so if this is set too high interrupts *may* be lost! + omap3_die_id [OMAP] Append DIE ID info under /proc/cpuinfo + omap_mux= [OMAP] Override bootloader pin multiplexing. Format: ... For example, to override I2C bus2: diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2455dcc..462c23a 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -169,3 +169,13 @@ config OMAP3_SDRC_AC_TIMING wish to say no. Selecting yes without understanding what is going on could result in system crashes; +config OMAP3_EXPORT_DIE_ID + bool "Export DIE ID code under /proc/cpuinfo" + depends on ARCH_OMAP3 + default n + help + Say Y here if you need DIE ID code to be exported via /proc/cpuinfo + in production systems. You will need also to explicitly flag it by + appending the "omap3_die_id" parameter to your boot command line. + + diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 4702ffe..6fe554b 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -76,6 +76,10 @@ EXPORT_SYMBOL(omap_type); /*----------------------------------------------------------------------------*/ #define OMAP_TAP_IDCODE 0x0204 +#define OMAP_TAP_PROD_ID_0 0x0208 +#define OMAP_TAP_PROD_ID_1 0x020c +#define OMAP_TAP_PROD_ID_2 0x0210 +#define OMAP_TAP_PROD_ID_3 0x0214 #define OMAP_TAP_DIE_ID_0 0x0218 #define OMAP_TAP_DIE_ID_1 0x021C #define OMAP_TAP_DIE_ID_2 0x0220 @@ -303,6 +307,7 @@ void __init omap4_check_revision(void) void __init omap3_cpuinfo(void) { + int sz; u8 rev = GET_OMAP_REVISION(); char cpu_name[16], cpu_rev[16]; @@ -360,8 +365,8 @@ void __init omap3_cpuinfo(void) } /* Print verbose information */ - snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "%s ES%s", cpu_name, - cpu_rev); + sz = snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "%s ES%s", + cpu_name, cpu_rev); pr_info("%s (", system_soc_info); OMAP3_SHOW_FEATURE(l2cache); @@ -372,7 +377,35 @@ void __init omap3_cpuinfo(void) OMAP3_SHOW_FEATURE(192mhz_clk); printk(")\n"); + + /* Append OMAP3 IDCODE and Production ID to system_soc_info */ + snprintf(system_soc_info + sz, SYSTEM_SOC_INFO_SIZE - sz, + "\n\tIDCODE\t: %08x\n\tPr. ID\t: %08x %08x %08x %08x", + read_tap_reg(OMAP_TAP_IDCODE), + read_tap_reg(OMAP_TAP_PROD_ID_0), + read_tap_reg(OMAP_TAP_PROD_ID_1), + read_tap_reg(OMAP_TAP_PROD_ID_2), + read_tap_reg(OMAP_TAP_PROD_ID_3)); + +} + +#ifdef CONFIG_OMAP3_EXPORT_DIE_ID +static int __init omap3_die_id_setup(char *s) +{ + int sz; + + sz = strlen(system_soc_info); + snprintf(system_soc_info + sz, SYSTEM_SOC_INFO_SIZE - sz, + "\n\tDie ID\t: %08x %08x %08x %08x", + read_tap_reg(OMAP_TAP_DIE_ID_0), + read_tap_reg(OMAP_TAP_DIE_ID_1), + read_tap_reg(OMAP_TAP_DIE_ID_2), + read_tap_reg(OMAP_TAP_DIE_ID_3)); + + return 1; } +__setup("omap3_die_id", omap3_die_id_setup); +#endif /* * Try to detect the exact revision of the omap we're running on From patchwork Fri Jun 4 07:40:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 104228 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o547eU4Y018793 for ; Fri, 4 Jun 2010 07:40:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752925Ab0FDHka (ORCPT ); Fri, 4 Jun 2010 03:40:30 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:37630 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752815Ab0FDHk3 (ORCPT ); Fri, 4 Jun 2010 03:40:29 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o547eAi9029044 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 4 Jun 2010 02:40:12 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o547e582021210; Fri, 4 Jun 2010 13:10:09 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: linux-mtd@lists.infradead.org, tony@atomide.com, mike@compulab.co.il, Sukumar Ghorai Subject: [PATCH v5 3/3] omap3 nand: fix issue in board file to detect nand Date: Fri, 4 Jun 2010 13:10:05 +0530 Message-Id: <1275637205-489-4-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1275637205-489-3-git-send-email-s-ghorai@ti.com> References: <1275637205-489-1-git-send-email-s-ghorai@ti.com> <1275637205-489-2-git-send-email-s-ghorai@ti.com> <1275637205-489-3-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 04 Jun 2010 07:40:31 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index bc4c3f8..4870da2 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -61,8 +61,6 @@ #define SB_T35_SMSC911X_GPIO 65 #define NAND_BLOCK_SIZE SZ_128K -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS0_BASE_ADDR (OMAP34XX_GPMC_VIRT + GPMC_CS0_BASE) #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include @@ -223,28 +221,12 @@ static struct omap_nand_platform_data cm_t35_nand_data = { .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), .dma_channel = -1, /* disable DMA in OMAP NAND driver */ .cs = 0, - .gpmc_cs_baseaddr = (void __iomem *)GPMC_CS0_BASE_ADDR, - .gpmc_baseaddr = (void __iomem *)OMAP34XX_GPMC_VIRT, }; -static struct resource cm_t35_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device cm_t35_nand_device = { - .name = "omap2-nand", - .id = -1, - .num_resources = 1, - .resource = &cm_t35_nand_resource, - .dev = { - .platform_data = &cm_t35_nand_data, - }, -}; - static void __init cm_t35_init_nand(void) { - if (platform_device_register(&cm_t35_nand_device) < 0) + if (gpmc_nand_init(&cm_t35_nand_data) < 0) pr_err("CM-T35: Unable to register NAND device\n"); } #else diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 922b746..364511a --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -58,9 +58,6 @@ #include "mux.h" #include "hsmmc.h" -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K #define OMAP_DM9000_GPIO_IRQ 25 @@ -104,20 +101,6 @@ static struct omap_nand_platform_data devkit8000_nand_data = { .dma_channel = -1, /* disable DMA in OMAP NAND driver */ }; -static struct resource devkit8000_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device devkit8000_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &devkit8000_nand_data, - }, - .num_resources = 1, - .resource = &devkit8000_nand_resource, -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -581,8 +564,6 @@ static void __init devkit8000_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -604,13 +585,9 @@ static void __init devkit8000_flash_init(void) if (nandcs < GPMC_CS_NUM) { devkit8000_nand_data.cs = nandcs; - devkit8000_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - devkit8000_nand_data.gpmc_baseaddr = (void *) - (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&devkit8000_nand_device) < 0) + if (gpmc_nand_init(&devkit8000_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 0ab0c26..befb5e3 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -48,9 +48,6 @@ #include "mux.h" #include "hsmmc.h" -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K static struct mtd_partition omap3beagle_nand_partitions[] = { @@ -93,20 +90,6 @@ static struct omap_nand_platform_data omap3beagle_nand_data = { .dev_ready = NULL, }; -static struct resource omap3beagle_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device omap3beagle_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &omap3beagle_nand_data, - }, - .num_resources = 1, - .resource = &omap3beagle_nand_resource, -}; - /* DSS */ static int beagle_enable_dvi(struct omap_dss_device *dssdev) @@ -424,8 +407,6 @@ static void __init omap3beagle_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -447,12 +428,9 @@ static void __init omap3beagle_flash_init(void) if (nandcs < GPMC_CS_NUM) { omap3beagle_nand_data.cs = nandcs; - omap3beagle_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&omap3beagle_nand_device) < 0) + if (gpmc_nand_init(&omap3beagle_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index f05b867..bf8089f --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -54,9 +54,6 @@ #include -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K #define OMAP3_AC_GPIO 136 @@ -106,20 +103,6 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { .dev_ready = NULL, }; -static struct resource omap3touchbook_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device omap3touchbook_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &omap3touchbook_nand_data, - }, - .num_resources = 1, - .resource = &omap3touchbook_nand_resource, -}; - #include "sdram-micron-mt46h32m32lf-6.h" static struct omap2_hsmmc_info mmc[] = { @@ -458,8 +441,6 @@ static void __init omap3touchbook_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -481,13 +462,9 @@ static void __init omap3touchbook_flash_init(void) if (nandcs < GPMC_CS_NUM) { omap3touchbook_nand_data.cs = nandcs; - omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - omap3touchbook_nand_data.gpmc_baseaddr = - (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&omap3touchbook_nand_device) < 0) + if (gpmc_nand_init(&omap3touchbook_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index d05ced5..9c51936 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -58,8 +58,6 @@ #define OVERO_GPIO_USBH_NRESET 183 #define NAND_BLOCK_SIZE SZ_128K -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 #define OVERO_SMSC911X_CS 5 #define OVERO_SMSC911X_GPIO 176 @@ -269,28 +267,11 @@ static struct omap_nand_platform_data overo_nand_data = { .dma_channel = -1, /* disable DMA in OMAP NAND driver */ }; -static struct resource overo_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device overo_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &overo_nand_data, - }, - .num_resources = 1, - .resource = &overo_nand_resource, -}; - - static void __init overo_flash_init(void) { u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -312,12 +293,9 @@ static void __init overo_flash_init(void) if (nandcs < GPMC_CS_NUM) { overo_nand_data.cs = nandcs; - overo_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&overo_nand_device) < 0) + if (gpmc_nand_init(&overo_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-sdp-flash.c old mode 100644 new mode 100755 index 2d02632..2638c83 --- a/arch/arm/mach-omap2/board-sdp-flash.c +++ b/arch/arm/mach-omap2/board-sdp-flash.c @@ -162,11 +162,6 @@ __init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) sdp_nand_data.parts = sdp_nand_parts.parts; sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts; - sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT + - GPMC_CS0_BASE + - cs * GPMC_CS_SIZE); - sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT); - gpmc_nand_init(&sdp_nand_data); } #else From patchwork Mon May 10 13:49:34 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkatraman S X-Patchwork-Id: 98172 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4ADnbN7018436 for ; Mon, 10 May 2010 13:49:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754248Ab0EJNtg (ORCPT ); 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Mon, 10 May 2010 06:49:34 -0700 (PDT) Received: by 10.231.146.20 with HTTP; Mon, 10 May 2010 06:49:34 -0700 (PDT) Date: Mon, 10 May 2010 19:19:34 +0530 X-Google-Sender-Auth: 9df697eb85ddc43d Message-ID: Subject: [PATCH] update omap3 features bitmap and API to generic names From: Venkatraman S To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon , Tony Lindgren Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 10 May 2010 13:49:38 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 9cba556..afa481d 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3510,7 +3510,7 @@ int __init omap3xxx_clk_init(void) cpu_clkflg |= CK_3430ES2; } } - if (omap3_has_192mhz_clk()) + if (omap_has_192mhz_clk()) omap_96m_alwon_fck = omap_96m_alwon_fck_3630; if (cpu_is_omap3630()) { diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a..a095b87 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -28,7 +28,7 @@ static struct omap_chip_id omap_chip; static unsigned int omap_revision; -u32 omap3_features; +u32 omap_features; unsigned int omap_rev(void) { @@ -161,14 +161,14 @@ void __init omap24xx_check_revision(void) #define OMAP3_CHECK_FEATURE(status,feat) \ if (((status & OMAP3_ ##feat## _MASK) \ >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ - omap3_features |= OMAP3_HAS_ ##feat; \ + omap_features |= OMAP_HAS_ ##feat; \ } void __init omap3_check_features(void) { u32 status; - omap3_features = 0; + omap_features = 0; status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); @@ -178,7 +178,7 @@ void __init omap3_check_features(void) OMAP3_CHECK_FEATURE(status, NEON); OMAP3_CHECK_FEATURE(status, ISP); if (cpu_is_omap3630()) - omap3_features |= OMAP3_HAS_192MHZ_CLK; + omap_features |= OMAP_HAS_192MHZ_CLK; /* * TODO: Get additional info (where applicable) @@ -294,7 +294,7 @@ void __init omap4_check_revision(void) } #define OMAP3_SHOW_FEATURE(feat) \ - if (omap3_has_ ##feat()) \ + if (omap_has_ ##feat()) \ printk(#feat" "); void __init omap3_cpuinfo(void) @@ -314,20 +314,20 @@ void __init omap3_cpuinfo(void) /* * AM35xx devices */ - if (omap3_has_sgx()) { + if (omap_has_sgx()) { omap_revision = OMAP3517_REV(rev); strcpy(cpu_name, "AM3517"); } else { /* Already set in omap3_check_revision() */ strcpy(cpu_name, "AM3505"); } - } else if (omap3_has_iva() && omap3_has_sgx()) { + } else if (omap_has_iva() && omap_has_sgx()) { /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ strcpy(cpu_name, "OMAP3430/3530"); - } else if (omap3_has_iva()) { + } else if (omap_has_iva()) { omap_revision = OMAP3525_REV(rev); strcpy(cpu_name, "OMAP3525"); - } else if (omap3_has_sgx()) { + } else if (omap_has_sgx()) { omap_revision = OMAP3515_REV(rev); strcpy(cpu_name, "OMAP3515"); } else { diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 7514174..80dc8e0 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -434,28 +434,28 @@ int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); /* - * Runtime detection of OMAP3 features + * Runtime detection of OMAP features */ -extern u32 omap3_features; +extern u32 omap_features; -#define OMAP3_HAS_L2CACHE BIT(0) -#define OMAP3_HAS_IVA BIT(1) -#define OMAP3_HAS_SGX BIT(2) -#define OMAP3_HAS_NEON BIT(3) -#define OMAP3_HAS_ISP BIT(4) -#define OMAP3_HAS_192MHZ_CLK BIT(5) +#define OMAP_HAS_L2CACHE BIT(0) +#define OMAP_HAS_IVA BIT(1) +#define OMAP_HAS_SGX BIT(2) +#define OMAP_HAS_NEON BIT(3) +#define OMAP_HAS_ISP BIT(4) +#define OMAP_HAS_192MHZ_CLK BIT(5) -#define OMAP3_HAS_FEATURE(feat,flag) \ -static inline unsigned int omap3_has_ ##feat(void) \ +#define OMAP_HAS_FEATURE(feat, flag) \ +static inline unsigned int omap_has_ ##feat(void) \ { \ - return (omap3_features & OMAP3_HAS_ ##flag); \ + return (omap_features & OMAP_HAS_ ##flag); \ } \ -OMAP3_HAS_FEATURE(l2cache, L2CACHE) -OMAP3_HAS_FEATURE(sgx, SGX) -OMAP3_HAS_FEATURE(iva, IVA) -OMAP3_HAS_FEATURE(neon, NEON) -OMAP3_HAS_FEATURE(isp, ISP) -OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) +OMAP_HAS_FEATURE(l2cache, L2CACHE) +OMAP_HAS_FEATURE(sgx, SGX) +OMAP_HAS_FEATURE(iva, IVA) +OMAP_HAS_FEATURE(neon, NEON) +OMAP_HAS_FEATURE(isp, ISP) +OMAP_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) #endif From patchwork Mon May 3 06:18:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 96437 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o436JbgC009976 for ; Mon, 3 May 2010 06:19:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757216Ab0ECGTe (ORCPT ); Mon, 3 May 2010 02:19:34 -0400 Received: from smtp.nokia.com ([192.100.122.233]:30960 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751851Ab0ECGS4 (ORCPT ); Mon, 3 May 2010 02:18:56 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o436IqUd026061; Mon, 3 May 2010 09:18:52 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:18:49 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:18:49 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o436Igol008122; Mon, 3 May 2010 09:18:48 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v2 16/21] OMAP: DSS2: Taal: Use Nokia DSI panel data Date: Mon, 3 May 2010 09:18:36 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: <1ef57e99d69aaf89b8e61074aa8ce2e5f6632d28.1272621452.git.ext-jani.1.nikula@nokia.com> <7a01973540a3afa79701ee08a3d8732db4687d5b.1272621452.git.ext-jani.1.nikula@nokia.com> <1a68710812da041ef583944411a1b7027d216c96.1272621452.git.ext-jani.1.nikula@nokia.com> <85172e14c23339065e319230f9707353409a901e.1272621452.git.ext-jani.1.nikula@nokia.com> <6e9febe4d2179309dcf93b7a8e897890c871f086.1272621452.git.ext-jani.1.nikula@nokia.com> <4004b06a47d3c1d20d6d8a30ddccdf536faeb5a0.1272621452.git.ext-jani.1.nikula@nokia.com> <5a5dc1e253df571477551b8f63560ad9d1a3ab2b.1272621452.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 03 May 2010 06:18:49.0305 (UTC) FILETIME=[7E8C3490:01CAEA88] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 06:19:37 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index c326e51..b68976b 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -33,6 +33,7 @@ #include #include +#include /* DSI Virtual channel. Hardcoded for now. */ #define TCH 0 @@ -85,7 +86,6 @@ struct taal_data { bool mirror; bool te_enabled; - bool use_ext_te; atomic_t do_update; struct { @@ -107,6 +107,12 @@ struct taal_data { struct delayed_work esd_work; }; +static inline struct nokia_dsi_panel_data +*get_panel_data(const struct omap_dss_device *dssdev) +{ + return (struct nokia_dsi_panel_data *) dssdev->data; +} + static void taal_esd_work(struct work_struct *work); static void hw_guard_start(struct taal_data *td, int guard_msec) @@ -288,6 +294,7 @@ static int taal_bl_update_status(struct backlight_device *dev) { struct omap_dss_device *dssdev = dev_get_drvdata(&dev->dev); struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; int level; @@ -310,10 +317,10 @@ static int taal_bl_update_status(struct backlight_device *dev) r = 0; } } else { - if (!dssdev->set_backlight) + if (!panel_data->set_backlight) r = -EINVAL; else - r = dssdev->set_backlight(dssdev, level); + r = panel_data->set_backlight(dssdev, level); } mutex_unlock(&td->lock); @@ -503,16 +510,18 @@ static struct attribute_group taal_attr_group = { static void taal_hw_reset(struct omap_dss_device *dssdev) { - if (dssdev->reset_gpio == -1) + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); + + if (panel_data->reset_gpio == -1) return; - gpio_set_value(dssdev->reset_gpio, 1); + gpio_set_value(panel_data->reset_gpio, 1); udelay(10); /* reset the panel */ - gpio_set_value(dssdev->reset_gpio, 0); + gpio_set_value(panel_data->reset_gpio, 0); /* assert reset for at least 10us */ udelay(10); - gpio_set_value(dssdev->reset_gpio, 1); + gpio_set_value(panel_data->reset_gpio, 1); /* wait 5ms after releasing reset */ msleep(5); } @@ -522,6 +531,7 @@ static int taal_probe(struct omap_dss_device *dssdev) struct backlight_properties props; struct taal_data *td; struct backlight_device *bldev; + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; const struct omap_video_timings taal_panel_timings = { @@ -531,6 +541,11 @@ static int taal_probe(struct omap_dss_device *dssdev) dev_dbg(&dssdev->dev, "probe\n"); + if (!panel_data || !panel_data->name) { + r = -EINVAL; + goto err; + } + dssdev->panel.config = OMAP_DSS_LCD_TFT; dssdev->panel.timings = taal_panel_timings; dssdev->ctrl.pixel_size = 24; @@ -559,7 +574,7 @@ static int taal_probe(struct omap_dss_device *dssdev) /* if no platform set_backlight() defined, presume DSI backlight * control */ memset(&props, 0, sizeof(props)); - if (!dssdev->set_backlight) + if (!panel_data->set_backlight) td->use_dsi_bl = true; if (td->use_dsi_bl) @@ -584,8 +599,8 @@ static int taal_probe(struct omap_dss_device *dssdev) taal_bl_update_status(bldev); - if (dssdev->phy.dsi.ext_te) { - int gpio = dssdev->phy.dsi.ext_te_gpio; + if (panel_data->use_ext_te) { + int gpio = panel_data->ext_te_gpio; r = gpio_request(gpio, "taal irq"); if (r) { @@ -608,8 +623,6 @@ static int taal_probe(struct omap_dss_device *dssdev) INIT_DELAYED_WORK_DEFERRABLE(&td->te_timeout_work, taal_te_timeout_work_callback); - td->use_ext_te = true; - dev_dbg(&dssdev->dev, "Using GPIO TE\n"); } @@ -624,11 +637,11 @@ static int taal_probe(struct omap_dss_device *dssdev) return 0; err_sysfs: - if (td->use_ext_te) - free_irq(gpio_to_irq(dssdev->phy.dsi.ext_te_gpio), dssdev); + if (panel_data->use_ext_te) + free_irq(gpio_to_irq(panel_data->ext_te_gpio), dssdev); err_irq: - if (td->use_ext_te) - gpio_free(dssdev->phy.dsi.ext_te_gpio); + if (panel_data->use_ext_te) + gpio_free(panel_data->ext_te_gpio); err_gpio: backlight_device_unregister(bldev); err_bl: @@ -642,14 +655,15 @@ err: static void taal_remove(struct omap_dss_device *dssdev) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); struct backlight_device *bldev; dev_dbg(&dssdev->dev, "remove\n"); sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group); - if (td->use_ext_te) { - int gpio = dssdev->phy.dsi.ext_te_gpio; + if (panel_data->use_ext_te) { + int gpio = panel_data->ext_te_gpio; free_irq(gpio_to_irq(gpio), dssdev); gpio_free(gpio); } @@ -959,6 +973,7 @@ static int taal_update(struct omap_dss_device *dssdev, u16 x, u16 y, u16 w, u16 h) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; dev_dbg(&dssdev->dev, "update %d, %d, %d x %d\n", x, y, w, h); @@ -979,7 +994,7 @@ static int taal_update(struct omap_dss_device *dssdev, if (r) goto err; - if (td->te_enabled && td->use_ext_te) { + if (td->te_enabled && panel_data->use_ext_te) { td->update_region.x = x; td->update_region.y = y; td->update_region.w = w; @@ -1023,6 +1038,7 @@ static int taal_sync(struct omap_dss_device *dssdev) static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; td->te_enabled = enable; @@ -1032,7 +1048,7 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) else r = taal_dcs_write_0(DCS_TEAR_OFF); - if (!td->use_ext_te) + if (!panel_data->use_ext_te) omapdss_dsi_enable_te(dssdev, enable); /* XXX for some reason, DSI TE breaks if we don't wait here. @@ -1265,6 +1281,7 @@ static void taal_esd_work(struct work_struct *work) struct taal_data *td = container_of(work, struct taal_data, esd_work.work); struct omap_dss_device *dssdev = td->dssdev; + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); u8 state1, state2; int r; @@ -1305,7 +1322,7 @@ static void taal_esd_work(struct work_struct *work) } /* Self-diagnostics result is also shown on TE GPIO line. We need * to re-enable TE after self diagnostics */ - if (td->use_ext_te && td->te_enabled) { + if (td->te_enabled && panel_data->use_ext_te) { r = taal_dcs_write_1(DCS_TEAR_ON, 0); if (r) goto err; From patchwork Mon May 17 11:12:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ameya Palande X-Patchwork-Id: 100093 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4HBCpwY026827 for ; Mon, 17 May 2010 11:12:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752730Ab0EQLMt (ORCPT ); Mon, 17 May 2010 07:12:49 -0400 Received: from smtp.nokia.com ([192.100.122.233]:57479 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751522Ab0EQLMt (ORCPT ); Mon, 17 May 2010 07:12:49 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4HBCJdM012661; Mon, 17 May 2010 14:12:45 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 17 May 2010 14:12:41 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 17 May 2010 14:12:41 +0300 Received: from localhost.localdomain (esdhcp040115.research.nokia.com [172.21.40.115]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4HBCZIZ030870; Mon, 17 May 2010 14:12:36 +0300 From: Ameya Palande To: linux-omap@vger.kernel.org Cc: timo.t.kokkonen@nokia.com, wim@iguana.be Subject: [PATCH] twl4030_wdt: Disable watchdog while probing Date: Mon, 17 May 2010 14:12:15 +0300 Message-Id: <7fcfe2bbdbad2e7c330c219fa1e27497a5fd0f89.1274094577.git.ameya.palande@nokia.com> X-Mailer: git-send-email 1.6.3.3 X-OriginalArrivalTime: 17 May 2010 11:12:41.0434 (UTC) FILETIME=[DDE613A0:01CAF5B1] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 17 May 2010 11:12:51 +0000 (UTC) diff --git a/drivers/watchdog/twl4030_wdt.c b/drivers/watchdog/twl4030_wdt.c index dcabe77..b5045ca 100644 --- a/drivers/watchdog/twl4030_wdt.c +++ b/drivers/watchdog/twl4030_wdt.c @@ -190,6 +190,8 @@ static int __devinit twl4030_wdt_probe(struct platform_device *pdev) twl4030_wdt_dev = pdev; + twl4030_wdt_disable(wdt); + ret = misc_register(&wdt->miscdev); if (ret) { dev_err(wdt->miscdev.parent, From patchwork Mon May 17 11:08:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 100092 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4HB8aox025594 for ; Mon, 17 May 2010 11:08:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753312Ab0EQLIT (ORCPT ); Mon, 17 May 2010 07:08:19 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:39661 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751321Ab0EQLIS (ORCPT ); Mon, 17 May 2010 07:08:18 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4HB8BLc032479 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 17 May 2010 06:08:14 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4HB8AfS026215; Mon, 17 May 2010 16:38:10 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o4HB89jm016002; Mon, 17 May 2010 16:38:09 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o4HB89qT015999; Mon, 17 May 2010 16:38:09 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, Ajay Kumar Gupta Subject: [PATCH 5/6] musb: gadget: fix tx transfer path for mode0 operation Date: Mon, 17 May 2010 16:38:07 +0530 Message-Id: <1274094488-15925-5-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1274094488-15925-4-git-send-email-ajay.gupta@ti.com> References: <1274094488-15925-1-git-send-email-ajay.gupta@ti.com> <1274094488-15925-2-git-send-email-ajay.gupta@ti.com> <1274094488-15925-3-git-send-email-ajay.gupta@ti.com> <1274094488-15925-4-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 17 May 2010 11:08:37 +0000 (UTC) diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c index 6fca870..9ac45e4 100644 --- a/drivers/usb/musb/musb_gadget.c +++ b/drivers/usb/musb/musb_gadget.c @@ -317,6 +317,22 @@ static void txstate(struct musb *musb, struct musb_request *req) else musb_ep->dma->desired_mode = 1; + /* + * Use system dma for unaligned buffers on RTL >= 1.8 + * for Inventra DMA. As system DMA can work only in + * mode-0 so update the desired_mode and request_size. + */ + if (is_inventra_dma_enabled() && + ((request->dma + request->actual) & 0x3) && + (musb->hwvers >= MUSB_HWVERS_1800)) { + + request_size = min_t(size_t, + musb_ep->hw_ep->max_packet_sz_tx, + request->length - request->actual); + + musb_ep->dma->desired_mode = 0; + } + use_dma = use_dma && c->channel_program( musb_ep->dma, musb_ep->packet_sz, musb_ep->dma->desired_mode, @@ -463,7 +479,6 @@ void musb_g_tx(struct musb *musb, u8 epnum) u8 is_dma = 0; if (dma && (csr & MUSB_TXCSR_DMAENAB)) { - is_dma = 1; csr |= MUSB_TXCSR_P_WZC_BITS; csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); @@ -471,6 +486,10 @@ void musb_g_tx(struct musb *musb, u8 epnum) /* Ensure writebuffer is empty. */ csr = musb_readw(epio, MUSB_TXCSR); request->actual += musb_ep->dma->actual_len; + + if (request->actual == request->length) + is_dma = 1; + DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n", epnum, csr, musb_ep->dma->actual_len, request); } From patchwork Mon May 17 11:08:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 100091 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4HB8aow025594 for ; Mon, 17 May 2010 11:08:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752094Ab0EQLIR (ORCPT ); Mon, 17 May 2010 07:08:17 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:39010 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751321Ab0EQLIR (ORCPT ); Mon, 17 May 2010 07:08:17 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4HB8Bwx007994 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 17 May 2010 06:08:14 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4HB8AkM026218; Mon, 17 May 2010 16:38:10 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o4HB89k0016008; Mon, 17 May 2010 16:38:09 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o4HB89TM016005; Mon, 17 May 2010 16:38:09 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, Ajay Kumar Gupta Subject: [PATCH 6/6] musb: dma: use optimal transfer element for sdma Date: Mon, 17 May 2010 16:38:08 +0530 Message-Id: <1274094488-15925-6-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1274094488-15925-5-git-send-email-ajay.gupta@ti.com> References: <1274094488-15925-1-git-send-email-ajay.gupta@ti.com> <1274094488-15925-2-git-send-email-ajay.gupta@ti.com> <1274094488-15925-3-git-send-email-ajay.gupta@ti.com> <1274094488-15925-4-git-send-email-ajay.gupta@ti.com> <1274094488-15925-5-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 17 May 2010 11:08:36 +0000 (UTC) diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index d29e487..39c1801 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c @@ -52,11 +52,34 @@ static void musb_sdma_channel_program(struct musb *musb, struct musb_dma_channel *musb_channel, dma_addr_t dma_addr, u32 len) { + u16 frame = len; + int data_type = OMAP_DMA_DATA_TYPE_S8; + + switch (dma_addr & 0x3) { + case 0: + if ((len % 4) == 0) { + data_type = OMAP_DMA_DATA_TYPE_S32; + frame = len / 4; + break; + } + case 2: + if ((len % 2) == 0) { + data_type = OMAP_DMA_DATA_TYPE_S16; + frame = len / 2; + break; + } + case 1: + case 3: + default: + data_type = OMAP_DMA_DATA_TYPE_S8; + frame = len; + break; + } /* set transfer parameters */ omap_set_dma_transfer_params(musb_channel->sysdma_channel, - OMAP_DMA_DATA_TYPE_S8, - len ? len : 1, 1, /* One frame */ - OMAP_DMA_SYNC_ELEMENT, + data_type, + len ? frame : 1, 1, /* One frame */ + OMAP_DMA_SYNC_FRAME, OMAP24XX_DMA_NO_DEVICE, 0); /* Src Sync */ From patchwork Mon May 17 11:08:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 100090 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4HB8VM1025491 for ; Mon, 17 May 2010 11:08:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755000Ab0EQLIX (ORCPT ); Mon, 17 May 2010 07:08:23 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:39011 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752565Ab0EQLIT (ORCPT ); Mon, 17 May 2010 07:08:19 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4HB8BoR007993 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 17 May 2010 06:08:14 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4HB89QP026213; Mon, 17 May 2010 16:38:09 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o4HB89vW015996; Mon, 17 May 2010 16:38:09 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o4HB89fe015993; Mon, 17 May 2010 16:38:09 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, Ajay Kumar Gupta Subject: [PATCH 4/6] musb: use system DMA for unaligned buffers on RTL >= 1.8 Date: Mon, 17 May 2010 16:38:06 +0530 Message-Id: <1274094488-15925-4-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1274094488-15925-3-git-send-email-ajay.gupta@ti.com> References: <1274094488-15925-1-git-send-email-ajay.gupta@ti.com> <1274094488-15925-2-git-send-email-ajay.gupta@ti.com> <1274094488-15925-3-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 17 May 2010 11:08:31 +0000 (UTC) diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig index be5bea6..f518339 100644 --- a/drivers/usb/musb/Kconfig +++ b/drivers/usb/musb/Kconfig @@ -166,6 +166,12 @@ config MUSB_USE_SYSTEM_DMA_WORKAROUND DMA channels are simultaneously enabled. To work around this issue, you can choose to use System DMA for RX channels. + Also on Mentor DMA in MUSB RTL version 1.8 (OMAP3630, AM/DM37x) + requires buffers to be aligned on a four byte boundary. This affects + USB CDC/RNDIS class application where buffers are always unaligned. + To work around this issue, you can choose to use System DMA for + unaligned buffers. + config USB_TI_CPPI_DMA bool depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index d2dab57..d29e487 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c @@ -52,8 +52,7 @@ static void musb_sdma_channel_program(struct musb *musb, struct musb_dma_channel *musb_channel, dma_addr_t dma_addr, u32 len) { - /* System DMA */ - /* RX: set src = FIFO */ + /* set transfer parameters */ omap_set_dma_transfer_params(musb_channel->sysdma_channel, OMAP_DMA_DATA_TYPE_S8, len ? len : 1, 1, /* One frame */ @@ -61,20 +60,39 @@ static void musb_sdma_channel_program(struct musb *musb, OMAP24XX_DMA_NO_DEVICE, 0); /* Src Sync */ - omap_set_dma_src_params(musb_channel->sysdma_channel, 0, - OMAP_DMA_AMODE_CONSTANT, - MUSB_FIFO_ADDRESS(musb->ctrl_phys_base, - musb_channel->epnum), - 0, 0); - - omap_set_dma_dest_params(musb_channel->sysdma_channel, 0, - OMAP_DMA_AMODE_POST_INC, dma_addr, - 0, 0); - - omap_set_dma_dest_data_pack(musb_channel->sysdma_channel, 1); - omap_set_dma_dest_burst_mode(musb_channel->sysdma_channel, - OMAP_DMA_DATA_BURST_16); - + if (!musb_channel->transmit) { + /* RX: set src = FIFO */ + omap_set_dma_src_params(musb_channel->sysdma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + MUSB_FIFO_ADDRESS(musb->ctrl_phys_base, + musb_channel->epnum), + 0, 0); + + omap_set_dma_dest_params(musb_channel->sysdma_channel, 0, + OMAP_DMA_AMODE_POST_INC, dma_addr, + 0, 0); + + omap_set_dma_dest_data_pack(musb_channel->sysdma_channel, 1); + omap_set_dma_dest_burst_mode(musb_channel->sysdma_channel, + OMAP_DMA_DATA_BURST_16); + + } else if (musb_channel->transmit) { + /* TX: set dst = FIFO */ + omap_set_dma_src_params(musb_channel->sysdma_channel, 0, + OMAP_DMA_AMODE_POST_INC, dma_addr, + 0, 0); + + omap_set_dma_dest_params(musb_channel->sysdma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + MUSB_FIFO_ADDRESS(musb->ctrl_phys_base, + musb_channel->epnum), + 0, 0); + + omap_set_dma_dest_data_pack(musb_channel->sysdma_channel, 0); + omap_set_dma_dest_burst_mode(musb_channel->sysdma_channel, + OMAP_DMA_DATA_BURST_DIS); + } + /* start the system dma */ omap_start_dma(musb_channel->sysdma_channel); } static void musb_sysdma_completion(int lch, u16 ch_status, void *data) @@ -88,12 +106,18 @@ static void musb_sysdma_completion(int lch, u16 ch_status, void *data) (struct musb_dma_channel *) data; struct musb_dma_controller *controller = musb_channel->controller; struct musb *musb = controller->private_data; + void __iomem *mbase = controller->base; + channel = &musb_channel->channel; DBG(2, "lch = 0x%d, ch_status = 0x%x\n", lch, ch_status); spin_lock_irqsave(&musb->lock, flags); - addr = (u32) omap_get_dma_dst_pos(musb_channel->sysdma_channel); + if (musb_channel->transmit) + addr = (u32) omap_get_dma_src_pos(musb_channel->sysdma_channel); + else + addr = (u32) omap_get_dma_dst_pos(musb_channel->sysdma_channel); + if (musb_channel->len == 0) channel->actual_len = 0; else @@ -106,6 +130,26 @@ static void musb_sysdma_completion(int lch, u16 ch_status, void *data) "=> reconfig 0 " : " => complete"); channel->status = MUSB_DMA_STATUS_FREE; + + /* completed */ + if ((musb_channel->transmit) && (channel->desired_mode == 0) + && (channel->actual_len == musb_channel->max_packet_sz)) { + + u8 epnum = musb_channel->epnum; + int offset = MUSB_EP_OFFSET(epnum, + MUSB_TXCSR); + u16 txcsr; + + /* + * The programming guide says that we + * must clear DMAENAB before DMAMODE. + */ + musb_ep_select(mbase, epnum); + txcsr = musb_readw(mbase, offset); + txcsr |= MUSB_TXCSR_TXPKTRDY; + musb_writew(mbase, offset, txcsr); + } + musb_dma_completion(musb, musb_channel->epnum, musb_channel->transmit); spin_unlock_irqrestore(&musb->lock, flags); @@ -194,8 +238,15 @@ static struct dma_channel *dma_channel_allocate(struct dma_controller *c, * issue when TX and RX DMA channels are simultaneously * enabled. To work around this issue, use system DMA * for all RX channels. + * Also on MUSB RTL version 1.8 onward (OMAP3630, OMAP4 + * and AM/DM37x) DMA requires buffers to be aligned on + * a four byte boundary. This affects USB CDC/RNDIS + * class application where buffers are always unaligned. + * Using system DMA for unaligned buffers as a + * workaround for this issue. */ - if (((musb->hwvers == MUSB_HWVERS_1400) && !transmit) + if ((((musb->hwvers == MUSB_HWVERS_1400) && !transmit) + || (musb->hwvers >= MUSB_HWVERS_1800)) && use_sdma_workaround()) { int ret; ret = musb_sdma_channel_request( @@ -248,11 +299,18 @@ static void configure_channel(struct dma_channel *channel, struct musb *musb = controller->private_data; void __iomem *mbase = controller->base; u8 bchannel = musb_channel->idx; + u8 buffer_is_aligned = (dma_addr & 0x3) ? 0 : 1; + u8 use_sdma = (musb_channel->sysdma_channel == -1) ? 0 : 1; u16 csr = 0; DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", channel, packet_sz, dma_addr, len, mode); - if (musb_channel->sysdma_channel != -1) { + + if (buffer_is_aligned && (packet_sz >= 512) && + (musb->hwvers >= MUSB_HWVERS_1800)) + use_sdma = 0; + + if (use_sdma) { musb_sdma_channel_program(musb, musb_channel, dma_addr, len); } else { /* Mentor DMA */ @@ -328,6 +386,9 @@ static int dma_channel_abort(struct dma_channel *channel) u16 csr; if (channel->status == MUSB_DMA_STATUS_BUSY) { + if (musb_channel->sysdma_channel != -1) + musb_sdma_channel_abort(musb_channel->sysdma_channel); + if (musb_channel->transmit) { offset = MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR); @@ -342,10 +403,6 @@ static int dma_channel_abort(struct dma_channel *channel) csr &= ~MUSB_TXCSR_DMAMODE; musb_writew(mbase, offset, csr); } else { - if (musb_channel->sysdma_channel != -1) - musb_sdma_channel_abort( - musb_channel->sysdma_channel); - offset = MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR); From patchwork Fri Mar 12 15:39:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 85273 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2CDshL5000493 for ; Fri, 12 Mar 2010 13:54:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758157Ab0CLNyz (ORCPT ); Fri, 12 Mar 2010 08:54:55 -0500 Received: from smtp.nokia.com ([192.100.105.134]:53995 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758131Ab0CLNyx (ORCPT ); Fri, 12 Mar 2010 08:54:53 -0500 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CDrj2h007397 for ; Fri, 12 Mar 2010 07:54:52 -0600 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 15:54:39 +0200 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 15:54:39 +0200 Received: from localhost.localdomain (sokoban.nmp.nokia.com [172.22.215.13]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CDsV8m003701 for ; Fri, 12 Mar 2010 15:54:36 +0200 From: Tero Kristo To: linux-omap@vger.kernel.org Subject: [PATCHv7 5/7] OMAP: Powerdomains: Add support for checking if pwrdm/clkdm can idle Date: Fri, 12 Mar 2010 17:39:15 +0200 Message-Id: <1268408357-15621-5-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1268408357-15621-4-git-send-email-tero.kristo@nokia.com> References: <> <1268408357-15621-1-git-send-email-tero.kristo@nokia.com> <1268408357-15621-2-git-send-email-tero.kristo@nokia.com> <1268408357-15621-3-git-send-email-tero.kristo@nokia.com> <1268408357-15621-4-git-send-email-tero.kristo@nokia.com> X-OriginalArrivalTime: 12 Mar 2010 13:54:39.0573 (UTC) FILETIME=[8F18E850:01CAC1EB] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 12 Mar 2010 13:54:56 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index a38a615..9ebff51 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -867,6 +867,38 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) return 0; } + +/** + * omap2_clkdm_can_idle - check if clockdomain has any active clocks or not + * @clkdm: struct clockdomain * + * + * Checks if the clockdomain has any active clock or not, i.e. whether it + * can enter idle. Returns -EINVAL if clkdm is NULL; 0 if unable to idle; + * 1 if can idle. + */ +int omap2_clkdm_can_idle(struct clockdomain *clkdm) +{ + int i; + + if (!clkdm) + return -EINVAL; + + for (i = 0; i < clkdm->clk_reg_num; i++) { + u32 idlest, fclk; + + fclk = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, + CM_FCLKEN + 4 * i); + if (fclk & ~clkdm->idle_def[i].fclk_ignore) + return 0; + + idlest = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, + CM_IDLEST + 4 * i); + if (~idlest & clkdm->idle_def[i].idlest_mask) + return 0; + } + return 1; +} + /** * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm * @clkdm: struct clockdomain * diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index 8fc19ff..5e29de8 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h @@ -663,6 +663,12 @@ static struct clockdomain iva2_clkdm = { .wkdep_srcs = iva2_wkdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .clk_reg_num = 1, + .idle_def = { + [0] = { + .idlest_mask = OMAP3430_ST_IVA2, + }, + }, }; static struct clockdomain gfx_3430es1_clkdm = { @@ -686,6 +692,12 @@ static struct clockdomain sgx_clkdm = { .sleepdep_srcs = gfx_sgx_sleepdeps, .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), + .clk_reg_num = 1, + .idle_def = { + [0] = { + .idlest_mask = OMAP3430ES2_ST_SGX_SHIFT, + }, + }, }; /* @@ -717,6 +729,57 @@ static struct clockdomain core_l3_3xxx_clkdm = { .dep_bit = OMAP3430_EN_CORE_SHIFT, .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .clk_reg_num = 3, + .idle_def = { + [0] = { + /* UARTs are controlled by idle loop so ignore */ + .fclk_ignore = OMAP3430_EN_UART2 | + OMAP3430_EN_UART1, + /* + * Reason for IDLEST ignores: + * - SDRC and OMAPCTRL controlled by HW + * - HSOTGUSB_IDLE bit is autoidled by HW + * - MAILBOX is controlled by HW + */ + .idlest_mask = + OMAP3430ES2_ST_MMC3_MASK | + OMAP3430_ST_ICR_MASK | + OMAP3430_ST_AES2_MASK | + OMAP3430_ST_SHA12_MASK | + OMAP3430_ST_DES2_MASK | + OMAP3430_ST_MMC2_MASK | + OMAP3430_ST_MMC1_MASK | + OMAP3430_ST_MSPRO_MASK | + OMAP3430_ST_HDQ_MASK | + OMAP3430_ST_MCSPI4_MASK | + OMAP3430_ST_MCSPI3_MASK | + OMAP3430_ST_MCSPI2_MASK | + OMAP3430_ST_MCSPI1_MASK | + OMAP3430_ST_I2C3_MASK | + OMAP3430_ST_I2C2_MASK | + OMAP3430_ST_I2C1_MASK | + OMAP3430_ST_GPT11_MASK | + OMAP3430_ST_GPT10_MASK | + OMAP3430_ST_MCBSP5_MASK | + OMAP3430_ST_MCBSP1_MASK | + OMAP3430ES2_ST_SSI_IDLE_MASK | + OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK | + OMAP3430_ST_D2D_MASK | + OMAP3430_ST_SDMA_MASK | + OMAP3430_ST_SSI_STDBY_MASK, + }, + [1] = { + .idlest_mask = OMAP3430_ST_PKA_MASK | + OMAP3430_ST_AES1_MASK | + OMAP3430_ST_RNG_MASK | + OMAP3430_ST_SHA11_MASK | + OMAP3430_ST_DES1_MASK, + }, + [2] = { + .idlest_mask = OMAP3430ES2_ST_USBTLL_MASK | + OMAP3430ES2_ST_CPEFUSE_MASK, + }, + }, }; /* @@ -746,6 +809,13 @@ static struct clockdomain dss_3xxx_clkdm = { .sleepdep_srcs = dss_sleepdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .clk_reg_num = 1, + .idle_def = { + [0] = { + .idlest_mask = OMAP3430ES2_ST_DSS_IDLE_MASK | + OMAP3430ES2_ST_DSS_STDBY_MASK, + }, + }, }; static struct clockdomain cam_clkdm = { @@ -758,6 +828,12 @@ static struct clockdomain cam_clkdm = { .sleepdep_srcs = cam_sleepdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .clk_reg_num = 1, + .idle_def = { + [0] = { + .idlest_mask = OMAP3430_ST_CAM, + }, + }, }; static struct clockdomain usbhost_clkdm = { @@ -770,6 +846,13 @@ static struct clockdomain usbhost_clkdm = { .sleepdep_srcs = usbhost_sleepdeps, .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), + .clk_reg_num = 1, + .idle_def = { + [0] = { + .idlest_mask = OMAP3430ES2_ST_USBHOST_IDLE_MASK | + OMAP3430ES2_ST_USBHOST_STDBY_MASK, + }, + }, }; static struct clockdomain per_clkdm = { @@ -783,6 +866,29 @@ static struct clockdomain per_clkdm = { .sleepdep_srcs = per_sleepdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .clk_reg_num = 1, + .idle_def = { + [0] = { + .fclk_ignore = OMAP3430_ST_UART3_MASK, + /* + * GPIO2...6 are dropped out from this mask + * as they are always non-idle, UART3 is also + * out as it is handled by idle loop + * */ + .idlest_mask = OMAP3430_ST_WDT3_MASK | + OMAP3430_ST_GPT9_MASK | + OMAP3430_ST_GPT8_MASK | + OMAP3430_ST_GPT7_MASK | + OMAP3430_ST_GPT6_MASK | + OMAP3430_ST_GPT5_MASK | + OMAP3430_ST_GPT4_MASK | + OMAP3430_ST_GPT3_MASK | + OMAP3430_ST_GPT2_MASK | + OMAP3430_ST_MCBSP4_MASK | + OMAP3430_ST_MCBSP3_MASK | + OMAP3430_ST_MCBSP2_MASK, + }, + }, }; /* diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index dc03289..a9ca884 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -919,6 +919,26 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) return 0; } +/** + * pwrdm_can_idle - check if the powerdomain can enter idle + * @pwrdm: struct powerdomain * the powerdomain to check status of + * + * Checks all associated clockdomains if they can idle or not. + * Returns 1 if the powerdomain can idle, 0 if not. + */ +int pwrdm_can_idle(struct powerdomain *pwrdm) +{ + int i; + int ret = 1; + + for (i = 0; i < PWRDM_MAX_CLKDMS; i++) + if (pwrdm->pwrdm_clkdms[i] && + !omap2_clkdm_can_idle(pwrdm->pwrdm_clkdms[i])) + ret = 0; + + return ret; +} + int pwrdm_state_switch(struct powerdomain *pwrdm) { return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h index ba0a6c0..ecf7f88 100644 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ b/arch/arm/plat-omap/include/plat/clockdomain.h @@ -30,6 +30,12 @@ #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) #define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) +/* + * Maximum number of FCLK register masks that can be associated with a + * clockdomain. CORE powerdomain on OMAP3 is the worst case + */ +#define CLKDM_MAX_CLK_REGS 3 + /* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 @@ -82,6 +88,11 @@ struct clkdm_dep { const struct omap_chip_id omap_chip; }; +struct clkdm_idle_def { + u32 fclk_ignore; + u32 idlest_mask; +}; + /** * struct clockdomain - OMAP clockdomain * @name: clockdomain name @@ -95,6 +106,8 @@ struct clkdm_dep { * @omap_chip: OMAP chip types that this clockdomain is valid on * @usecount: Usecount tracking * @node: list_head to link all clockdomains together + * @clk_reg_num: Number of idle definitions for clockdomain idle status checks + * @idle_def: Declarations for idle checks for clockdomain */ struct clockdomain { const char *name; @@ -111,6 +124,8 @@ struct clockdomain { const struct omap_chip_id omap_chip; atomic_t usecount; struct list_head node; + u8 clk_reg_num; + struct clkdm_idle_def idle_def[CLKDM_MAX_CLK_REGS]; }; void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); @@ -138,4 +153,6 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm); int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); +int omap2_clkdm_can_idle(struct clockdomain *clkdm); + #endif diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index e15c7e9..a1ecd47 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -145,6 +145,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); int pwrdm_wait_transition(struct powerdomain *pwrdm); +int pwrdm_can_idle(struct powerdomain *pwrdm); int pwrdm_state_switch(struct powerdomain *pwrdm); int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); From patchwork Mon May 24 17:02:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Nelson X-Patchwork-Id: 101907 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4OH2VX0030386 for ; Mon, 24 May 2010 17:02:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757991Ab0EXRCL (ORCPT ); Mon, 24 May 2010 13:02:11 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:41818 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757828Ab0EXRCD (ORCPT ); Mon, 24 May 2010 13:02:03 -0400 Received: by bwz7 with SMTP id 7so1112101bwz.19 for ; Mon, 24 May 2010 10:02:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=wx2TGiAKoZ4e2R7I79TAGyBGZLZ2Bux6NVqLgIvEMkQ=; b=IjMGc8r/lYYfVXDQtd5gbGevfLqZvzIIzmMv8kiv+j39S/jvqdel4wmeMOz2JL4Mts 04MA0FDZlAmhirCANiF3QG9dHVNkhnyun4i3hup4131bnqepzXgsdoCLgNkQ8ApIxlZQ hNSKkj4F0144+LnGolPUyJ4vs5X29cDQ9gexE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=ez/8ek3ja2+EAJshUCUcONN4bM5ihwo1tBKjjomiqsaNcLtRQDXMKI3m21uBe3GU6U lOGvDUknoeHtNGCraGizQvkt4UvDvYXFGcj4f7nT17VzWOZMnMy/RrjRa6PPV5jZwibA iSJ4x3IGDR0oWoug5ZgQwZz3HQgsWpEfHHQRA= MIME-Version: 1.0 Received: by 10.204.161.211 with SMTP id s19mr2346983bkx.129.1274720520776; Mon, 24 May 2010 10:02:00 -0700 (PDT) Received: by 10.204.113.67 with HTTP; Mon, 24 May 2010 10:02:00 -0700 (PDT) In-Reply-To: References: <1274169334.2307.74.camel@tubuntu.research.nokia.com> Date: Mon, 24 May 2010 12:02:00 -0500 Message-ID: Subject: Re: dss2 for-next BUG at drivers/video/omap2/dss/core.c:323! From: Robert Nelson To: "linux-omap@vger.kernel.org" Cc: Tomi Valkeinen , Felipe Contreras , Ville Syrjala Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 24 May 2010 17:02:32 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c index 300eff5..b4b1970 100644 --- a/drivers/video/omap2/displays/panel-generic.c +++ b/drivers/video/omap2/displays/panel-generic.c @@ -91,6 +91,18 @@ static int generic_panel_enable(struct omap_dss_device *dssdev) static void generic_panel_disable(struct omap_dss_device *dssdev) { + + if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) + { + int r = 0; + + r = generic_panel_power_on(dssdev); + if (r) + return r; + + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; + } + generic_panel_power_off(dssdev); dssdev->state = OMAP_DSS_DISPLAY_DISABLED; From patchwork Thu Aug 5 07:22:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 117226 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o757MACC027934 for ; Thu, 5 Aug 2010 07:22:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759830Ab0HEHWJ (ORCPT ); Thu, 5 Aug 2010 03:22:09 -0400 Received: from smtp.nokia.com ([192.100.105.134]:17485 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758296Ab0HEHWI (ORCPT ); Thu, 5 Aug 2010 03:22:08 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o757LZgC002374; Thu, 5 Aug 2010 02:22:03 -0500 Received: from vaepf101.NOE.Nokia.com ([10.160.244.86]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 Aug 2010 10:21:55 +0300 Received: from [172.21.40.78] ([172.21.40.78]) by vaepf101.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 Aug 2010 10:21:55 +0300 Message-ID: <4C5A669D.9070202@nokia.com> Date: Thu, 05 Aug 2010 10:22:05 +0300 From: Adrian Hunter User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: Tony Lindgren CC: linux-omap Mailing List , "Lavinen Jarkko (Nokia-M/Helsinki)" Subject: [PATCH] omap: hsmmc: Do not mux the slot if non default muxing is already done X-OriginalArrivalTime: 05 Aug 2010 07:21:55.0640 (UTC) FILETIME=[E2359380:01CB346E] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 07:22:11 +0000 (UTC) diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2dbb265..c6329eb 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -608,6 +608,9 @@ static inline void omap_hsmmc_reset(void) {} static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, int controller_nr) { + if (mmc_controller->slots[0].nomux) + return; + if ((mmc_controller->slots[0].switch_pin > 0) && \ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 1ef54b0..e1ec467 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -267,6 +267,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) mmc->slots[0].switch_pin = c->gpio_cd; mmc->slots[0].gpio_wp = c->gpio_wp; + mmc->slots[0].nomux = c->nomux; mmc->slots[0].remux = c->remux; if (c->cover_only) diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8..56d65cc 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -16,6 +16,7 @@ struct omap2_hsmmc_info { bool power_saving; /* Try to sleep or power off when possible */ bool no_off; /* power_saving and power is not to go off */ bool vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */ + bool nomux; /* No default muxing for this slot */ int gpio_cd; /* or -EINVAL */ int gpio_wp; /* or -EINVAL */ char *name; /* or NULL for default */ From patchwork Thu Aug 5 00:16:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 117181 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o750GjG9029268 for ; Thu, 5 Aug 2010 00:16:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933080Ab0HEAQL (ORCPT ); Wed, 4 Aug 2010 20:16:11 -0400 Received: from mail-yx0-f174.google.com ([209.85.213.174]:63189 "EHLO mail-yx0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758230Ab0HEAQJ (ORCPT ); Wed, 4 Aug 2010 20:16:09 -0400 Received: by yxg6 with SMTP id 6so2241189yxg.19 for ; Wed, 04 Aug 2010 17:16:08 -0700 (PDT) Received: by 10.231.157.11 with SMTP id z11mr11202049ibw.147.1280967368636; Wed, 04 Aug 2010 17:16:08 -0700 (PDT) Received: from localhost (c-24-18-179-55.hsd1.wa.comcast.net [24.18.179.55]) by mx.google.com with ESMTPS id h8sm8434006ibk.3.2010.08.04.17.16.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Aug 2010 17:16:07 -0700 (PDT) From: Kevin Hilman To: Patrick Pannuto Cc: "linux-kernel\@vger.kernel.org" , "linux-arm-msm\@vger.kernel.org" , "linux-omap\@vger.kernel.org" , "damm\@opensource.se" , "lethal\@linux-sh.org" , "rjw\@sisk.pl" , "eric.y.miao\@gmail.com" , "netdev\@vger.kernel.org" , Greg Kroah-Hartman , alan@lxorguk.ukuu.org.uk, zt.tmzt@gmail.com, grant.likely@secretlab.ca, magnus.damm@gmail.com Subject: Re: [PATCH] platform: Facilitate the creation of pseduo-platform busses Organization: Deep Root Systems, LLC References: <4C59E654.1090403@codeaurora.org> Date: Wed, 04 Aug 2010 17:16:05 -0700 In-Reply-To: <4C59E654.1090403@codeaurora.org> (Patrick Pannuto's message of "Wed, 04 Aug 2010 15:14:44 -0700") Message-ID: <877hk56hiy.fsf@deeprootsystems.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (gnu/linux) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 00:16:45 +0000 (UTC) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 4d99c8b..2cf55e2 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -241,7 +241,8 @@ int platform_device_add(struct platform_device *pdev) if (!pdev->dev.parent) pdev->dev.parent = &platform_bus; - pdev->dev.bus = &platform_bus_type; + if (!pdev->dev.bus) + pdev->dev.bus = &platform_bus_type; if (pdev->id != -1) dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); @@ -482,7 +483,8 @@ static void platform_drv_shutdown(struct device *_dev) */ int platform_driver_register(struct platform_driver *drv) { - drv->driver.bus = &platform_bus_type; + if (!drv->driver.bus) + drv->driver.bus = &platform_bus_type; if (drv->probe) drv->driver.probe = platform_drv_probe; if (drv->remove) @@ -539,12 +541,12 @@ int __init_or_module platform_driver_probe(struct platform_driver *drv, * if the probe was successful, and make sure any forced probes of * new devices fail. */ - spin_lock(&platform_bus_type.p->klist_drivers.k_lock); + spin_lock(&drv->driver.bus->p->klist_drivers.k_lock); drv->probe = NULL; if (code == 0 && list_empty(&drv->driver.p->klist_devices.k_list)) retval = -ENODEV; drv->driver.probe = platform_drv_probe_fail; - spin_unlock(&platform_bus_type.p->klist_drivers.k_lock); + spin_unlock(&drv->driver.bus->p->klist_drivers.k_lock); if (code != retval) platform_driver_unregister(drv); From patchwork Thu May 27 07:04:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 102573 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4R75JxJ012829 for ; Thu, 27 May 2010 07:05:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755400Ab0E0HFF (ORCPT ); Thu, 27 May 2010 03:05:05 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:55132 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753118Ab0E0HFD (ORCPT ); Thu, 27 May 2010 03:05:03 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4R74sVd006864 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 27 May 2010 02:04:56 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4R74oKC024768; Thu, 27 May 2010 12:34:51 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o4R74oEE017660; Thu, 27 May 2010 12:34:50 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o4R74ojW017657; Thu, 27 May 2010 12:34:50 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, amit.kucheria@verdurent.com, khilman@deeprootsystems.com, Ajay Kumar Gupta Subject: [PATCH 2/3] musb: populate board_data within musb structure Date: Thu, 27 May 2010 12:34:47 +0530 Message-Id: <1274943888-17615-2-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1274943888-17615-1-git-send-email-ajay.gupta@ti.com> References: <1274943888-17615-1-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 27 May 2010 07:05:19 +0000 (UTC) diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c index b611420..0bef011 100644 --- a/drivers/usb/musb/blackfin.c +++ b/drivers/usb/musb/blackfin.c @@ -323,7 +323,7 @@ int musb_platform_set_mode(struct musb *musb, u8 musb_mode) return -EIO; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { /* diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c index 5762436..ce2e16f 100644 --- a/drivers/usb/musb/davinci.c +++ b/drivers/usb/musb/davinci.c @@ -376,7 +376,7 @@ int musb_platform_set_mode(struct musb *musb, u8 mode) return -EIO; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { void __iomem *tibase = musb->ctrl_base; u32 revision; diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index d3911ab..1ccc4d7 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -1961,6 +1961,7 @@ bad_config: } spin_lock_init(&musb->lock); + musb->board_data = plat->board_data; musb->board_mode = plat->mode; musb->board_set_power = plat->set_power; musb->set_clock = plat->set_clock; @@ -1995,7 +1996,7 @@ bad_config: * isp1504, non-OTG, etc) mostly hooking up through ULPI. */ musb->isr = generic_interrupt; - status = musb_platform_init(musb, plat->board_data); + status = musb_platform_init(musb); if (status < 0) goto fail2; diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index 7cef2b7..9dddaa4 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -393,6 +393,7 @@ struct musb { int (*board_set_power)(int state); int (*set_clock)(struct clk *clk, int is_active); + void *board_data; /* board specific data */ u8 min_power; /* vbus for periph, in mA/2 */ @@ -604,7 +605,7 @@ extern int musb_platform_get_vbus_status(struct musb *musb); #define musb_platform_get_vbus_status(x) 0 #endif -extern int __init musb_platform_init(struct musb *musb, void *board_data); +extern int __init musb_platform_init(struct musb *musb); extern int musb_platform_exit(struct musb *musb); #endif /* __MUSB_CORE_H__ */ diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index e06d65e..50591e7 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -189,10 +189,10 @@ int musb_platform_set_mode(struct musb *musb, u8 musb_mode) return 0; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { u32 l; - struct omap_musb_board_data *data = board_data; + struct omap_musb_board_data *data = musb->board_data; #if defined(CONFIG_ARCH_OMAP2430) omap_cfg_reg(AE5_2430_USB0HS_STP); diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c index 05c077f..60d3938 100644 --- a/drivers/usb/musb/tusb6010.c +++ b/drivers/usb/musb/tusb6010.c @@ -1104,7 +1104,7 @@ err: return -ENODEV; } -int __init musb_platform_init(struct musb *musb, void *board_data) +int __init musb_platform_init(struct musb *musb) { struct platform_device *pdev; struct resource *mem; From patchwork Thu Jul 8 14:05:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathias Nyman X-Patchwork-Id: 110855 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68E5PGf017535 for ; Thu, 8 Jul 2010 14:05:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751851Ab0GHOFY (ORCPT ); Thu, 8 Jul 2010 10:05:24 -0400 Received: from smtp.nokia.com ([192.100.122.233]:37363 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751544Ab0GHOFY (ORCPT ); Thu, 8 Jul 2010 10:05:24 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o68E4gSl010940 for ; Thu, 8 Jul 2010 17:05:21 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 17:05:13 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 17:05:11 +0300 Received: from localhost.localdomain (esdhcp038119.research.nokia.com [172.21.38.119]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o68E5Bca026182 for ; Thu, 8 Jul 2010 17:05:11 +0300 From: Mathias Nyman To: linux-omap@vger.kernel.org Subject: [PATCH] omap: rx51: Platform support for tsl2563 ALS Date: Thu, 8 Jul 2010 17:05:11 +0300 Message-Id: <1278597911-11839-1-git-send-email-mathias.nyman@nokia.com> X-Mailer: git-send-email 1.5.6.5 X-OriginalArrivalTime: 08 Jul 2010 14:05:11.0883 (UTC) FILETIME=[94BA41B0:01CB1EA6] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 14:05:25 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 3c3f975..a3a396c 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -35,6 +35,8 @@ #include #include +#include <../drivers/staging/iio/light/tsl2563.h> + #include "mux.h" #include "hsmmc.h" @@ -53,6 +55,12 @@ enum { static struct wl12xx_platform_data wl1251_pdata; +#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) +static struct tsl2563_platform_data rx51_tsl2563_platform_data = { + .cover_comp_gain = 16, +}; +#endif + static struct omap2_mcspi_device_config wl1251_mcspi_config = { .turbo_mode = 0, .single_channel = 1, @@ -714,6 +722,12 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { I2C_BOARD_INFO("tlv320aic3x", 0x18), .platform_data = &rx51_aic3x_data, }, +#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) + { + I2C_BOARD_INFO("tsl2563", 0x29), + .platform_data = &rx51_tsl2563_platform_data, + }, +#endif { I2C_BOARD_INFO("tpa6130a2", 0x60), .platform_data = &rx51_tpa6130a2_data, From patchwork Mon May 10 06:48:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Senthilvadivu Guruswamy X-Patchwork-Id: 98078 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4A6mqkF015611 for ; Mon, 10 May 2010 06:48:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753129Ab0EJGsw (ORCPT ); Mon, 10 May 2010 02:48:52 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:48604 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751101Ab0EJGsv (ORCPT ); Mon, 10 May 2010 02:48:51 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4A6mbQH008560 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 May 2010 01:48:39 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4A6mV9Z009096; Mon, 10 May 2010 12:18:32 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o4A6mVPe027888; Mon, 10 May 2010 12:18:31 +0530 Received: (from a0876342@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o4A6mUO1027833; Mon, 10 May 2010 12:18:30 +0530 From: Senthilvadivu Guruswamy To: linux-omap@vger.kernel.org, linux-fbdev-devel@lists.sourceforge.net, tony@atomide.com, tomi.valkeinen@nokia.com, v-hiremath@ti.com Cc: Senthilvadivu Guruswamy Subject: [PATCH] DSS2 Include VRFB into omap2-3build only Date: Mon, 10 May 2010 12:18:30 +0530 Message-Id: <1273474110-22451-1-git-send-email-svadivu@ti.com> X-Mailer: git-send-email 1.5.5 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 10 May 2010 06:48:53 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h index d8a03ce..3792bde 100644 --- a/arch/arm/plat-omap/include/plat/vrfb.h +++ b/arch/arm/plat-omap/include/plat/vrfb.h @@ -35,6 +35,7 @@ struct vrfb { bool yuv_mode; }; +#ifdef CONFIG_OMAP2_VRFB extern int omap_vrfb_request_ctx(struct vrfb *vrfb); extern void omap_vrfb_release_ctx(struct vrfb *vrfb); extern void omap_vrfb_adjust_size(u16 *width, u16 *height, @@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot); extern void omap_vrfb_restore_context(void); +#else +static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; } +static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {} +static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, + u8 bytespp) {} +static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) + { return 0; } +static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) + { return 0; } +static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, + u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} +static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot) + { return 0; } +static inline void omap_vrfb_restore_context(void) {} +#endif #endif /* __VRFB_H */ diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig index d877c36..253376a 100644 --- a/drivers/video/omap2/Kconfig +++ b/drivers/video/omap2/Kconfig @@ -3,6 +3,10 @@ config OMAP2_VRAM config OMAP2_VRFB bool + depends on FB_OMAP2 && (!ARCH_OMAP4) + default y if (ARCH_OMAP2 || ARCH_OMAP3) + help + OMAP VRFB buffer support is efficient for rotation source "drivers/video/omap2/dss/Kconfig" source "drivers/video/omap2/omapfb/Kconfig" diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig index 43496d6..fee537e 100644 --- a/drivers/video/omap2/omapfb/Kconfig +++ b/drivers/video/omap2/omapfb/Kconfig @@ -3,7 +3,6 @@ menuconfig FB_OMAP2 depends on FB && OMAP2_DSS select OMAP2_VRAM - select OMAP2_VRFB select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT From patchwork Thu Jul 8 22:51:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110949 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsMqF011250 for ; Thu, 8 Jul 2010 22:54:22 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932094Ab0GHWyT (ORCPT ); Thu, 8 Jul 2010 18:54:19 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:37480 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932086Ab0GHWyS (ORCPT ); Thu, 8 Jul 2010 18:54:18 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms5iX026350 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:11 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaF022017; Fri, 9 Jul 2010 04:23:59 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 05/10] OMAP1: DMA: Introduce DMA driver as platform driver Date: Fri, 9 Jul 2010 04:21:17 +0530 Message-Id: <1278629482-32501-6-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:22 +0000 (UTC) This patch introduces OMAP1 DMA driver as platform device and adds support for registering through platform device layer. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap1/dma.c | 271 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap1/include/mach/dma.h | 80 ++++++++++ arch/arm/plat-omap/include/plat/dma.h | 118 ++++++++++++++ 3 files changed, 469 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-omap1/dma.c create mode 100644 arch/arm/mach-omap1/include/mach/dma.h diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c new file mode 100644 index 0000000..57be4f5 --- /dev/null +++ b/arch/arm/mach-omap1/dma.c @@ -0,0 +1,271 @@ +/* + * dma.c - OMAP1/OMAP7xx-specific DMA code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Author: + * Manjunatha GK + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) + +#define omap1_dma_read(reg) __raw_readw(dma_base + reg) +#define omap1_dma_write(val, reg) __raw_writew(val, dma_base + reg) + +static struct resource res[] __initdata = { + [0] = { + .start = OMAP1_DMA_BASE, + .end = OMAP1_DMA_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "system_dma_0", + .start = INT_DMA_CH0_6, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "system_dma_1", + .start = INT_DMA_CH1_7, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .name = "system_dma_2", + .start = INT_DMA_CH2_8, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .name = "system_dma_3", + .start = INT_DMA_CH3, + .flags = IORESOURCE_IRQ, + }, + [5] = { + .name = "system_dma_4", + .start = INT_DMA_CH4, + .flags = IORESOURCE_IRQ, + }, + [6] = { + .name = "system_dma_5", + .start = INT_DMA_CH5, + .flags = IORESOURCE_IRQ, + }, + [7] = { + .name = "system_dma_6", + .start = INT_DMA_LCD, + .flags = IORESOURCE_IRQ, + }, + /* irq's for omap16xx and omap7xx */ + [8] = { + .name = "system_dma_7", + .start = 53 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [9] = { + .name = "system_dma_8", + .start = 54 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [10] = { + .name = "system_dma_9", + .start = 55 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [11] = { + .name = "system_dma_10", + .start = 56 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [12] = { + .name = "system_dma_11", + .start = 57 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [13] = { + .name = "system_dma_12", + .start = 58 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [14] = { + .name = "system_dma_13", + .start = 59 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [15] = { + .name = "system_dma_14", + .start = 60 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [16] = { + .name = "system_dma_15", + .start = 61 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [17] = { + .name = "system_dma_16", + .start = 62 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct omap_dma_reg_offset dma_reg_offset[] = { + { + .lch_base = OMAP1_DMA_CH_BASE, + .gcr = OMAP1_DMA_GCR, + .gscr = OMAP1_DMA_GSCR, + .grst = OMAP1_DMA_GRST, + .hw_id = OMAP1_DMA_HW_ID, + .ch_specific = { + .cssa_l = OMAP1_DMA_CSSA_L, + .cssa_u = OMAP1_DMA_CSSA_U, + .cdsa_l = OMAP1_DMA_CDSA_L, + .cdsa_u = OMAP1_DMA_CDSA_U, + .lch_ctrl = OMAP1_DMA_LCH_CTRL, + .color_l = OMAP1_DMA_COLOR_L, + .color_u = OMAP1_DMA_COLOR_U, + .ccr2 = OMAP1_DMA_CCR2, + }, + .common_ch = { + .csdp = OMAP1_DMA_CSDP, + .ccr = OMAP1_DMA_CCR, + .csei = OMAP1_DMA_CSEI, + .csfi = OMAP1_DMA_CSFI, + .cdei = OMAP1_DMA_CDEI, + .cdfi = OMAP1_DMA_CDFI, + .clnk_ctrl = OMAP1_DMA_CLNK_CTRL, + .cpc = OMAP1_DMA_CPC, + .cdac = OMAP1_DMA_CDAC, + .cicr = OMAP1_DMA_CICR, + }, + .reg_caps = { + .caps_0u = OMAP1_DMA_CAPS_0_U, + .caps_0l = OMAP1_DMA_CAPS_0_L, + .caps_1u = OMAP1_DMA_CAPS_1_U, + .caps_1l = OMAP1_DMA_CAPS_1_L, + .caps_2 = OMAP1_DMA_CAPS_2, + .caps_3 = OMAP1_DMA_CAPS_3, + .caps_4 = OMAP1_DMA_CAPS_4, + }, + }, +}; +struct omap_dma_reg_offset *r = (struct omap_dma_reg_offset *)&dma_reg_offset; + + +static struct omap_dma_lch *omap1_dma_chan; +static void __iomem *dma_base; +static int enable_1510_mode; + +static int __init omap1_system_dma_init(void) +{ + struct platform_device *pdev; + struct omap_system_dma_plat_info *pdata; + struct omap_dma_dev_attr *d; + int ret; + + pdev = platform_device_alloc("system_dma", 0); + if (!pdev) { + pr_err("%s: Unable to device alloc for dma\n", + __func__); + return -ENOMEM; + } + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret) { + pr_err("%s: Unable to add resources for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_device_put; + } + + pdata = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); + if (!pdata) { + pr_err("%s: Unable to allocate pdata for %s\n", + __func__, pdev->name); + ret = -ENOMEM; + goto exit_device_put; + } + + d = pdata->dma_attr; + + /* Valid attributes for omap1 plus processors */ + d->dma_dev_attr = 0; + + if (cpu_is_omap15xx()) + d->dma_dev_attr = enable_1510_mode = ENABLE_1510_MODE; + + d->dma_dev_attr |= SRC_PORT; + d->dma_dev_attr |= DST_PORT; + d->dma_dev_attr |= SRC_INDEX; + d->dma_dev_attr |= DST_INDEX; + d->dma_dev_attr |= IS_BURST_ONLY4; + d->dma_dev_attr |= CLEAR_CSR_ON_READ; + d->dma_dev_attr |= IS_WORD_16; + + d->dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; + + pdata->omap_dma_base = (void __iomem *)res[0].start; + pdata->dma_reg_offset = r; + + pdata->dma_handle_ch = omap1_dma_handle_ch; + pdata->clear_lch_regs = clear_lch_regs; + pdata->clear_ccr_csr = clear_ccr_csr; + pdata->sync_device_set = sync_device_set; + pdata->dma_running = dma_running; + pdata->dma_irq_register = dma_irq_register; + pdata->set_prio_lch = set_prio_lch; + pdata->enable_lnk = enable_lnk; + pdata->disable_lnk = disable_lnk; + pdata->enable_channel_irq = omap_enable_channel_irq; + pdata->disable_channel_irq = NULL; + pdata->set_dma_write_mode = NULL; + pdata->disable_irq_lch = NULL; + pdata->enable_irq_lch = NULL; + + dma_base = pdata->omap_dma_base; + + /* Errata handling for all omap1 plus processors */ + pdata->errata = 0; + + if (cpu_class_is_omap1() && !cpu_is_omap15xx()) + pdata->errata |= OMAP3_3_ERRATUM; + + ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (ret) { + pr_err("%s: Unable to add resources for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_release_pdata; + } + ret = platform_device_add(pdev); + if (ret) { + pr_err("%s: Unable to add resources for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_release_pdata; + } + +exit_release_pdata: + kfree(pdata); +exit_device_put: + platform_device_put(pdev); + + return ret; +} +arch_initcall(omap1_system_dma_init); diff --git a/arch/arm/mach-omap1/include/mach/dma.h b/arch/arm/mach-omap1/include/mach/dma.h new file mode 100644 index 0000000..7c23330 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/dma.h @@ -0,0 +1,80 @@ +/* + * arch/arm/mach-omap1/include/mach/dma.h + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Author: Manjunatha GK + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP1_DMA_H +#define __ASM_ARCH_OMAP1_DMA_H +/* Hardware registers for omap1 */ +#define OMAP1_DMA_BASE (0xfffed800) + +#define OMAP1_DMA_GCR 0x400 +#define OMAP1_DMA_GSCR 0x404 +#define OMAP1_DMA_GRST 0x408 +#define OMAP1_DMA_HW_ID 0x442 +#define OMAP1_DMA_PCH2_ID 0x444 +#define OMAP1_DMA_PCH0_ID 0x446 +#define OMAP1_DMA_PCH1_ID 0x448 +#define OMAP1_DMA_PCHG_ID 0x44a +#define OMAP1_DMA_PCHD_ID 0x44c +#define OMAP1_DMA_CAPS_0_U 0x44e +#define OMAP1_DMA_CAPS_0_L 0x450 +#define OMAP1_DMA_CAPS_1_U 0x452 +#define OMAP1_DMA_CAPS_1_L 0x454 +#define OMAP1_DMA_CAPS_2 0x456 +#define OMAP1_DMA_CAPS_3 0x458 +#define OMAP1_DMA_CAPS_4 0x45a +#define OMAP1_DMA_PCH2_SR 0x460 +#define OMAP1_DMA_PCH0_SR 0x480 +#define OMAP1_DMA_PCH1_SR 0x482 +#define OMAP1_DMA_PCHD_SR 0x4c0 + +#define OMAP1_LOGICAL_DMA_CH_COUNT 17 + +/* Common channel specific registers for omap1 */ +#define OMAP1_DMA_CH_BASE (0x40) + +#define OMAP1_DMA_CSDP (0x00) +#define OMAP1_DMA_CCR (0x02) +#define OMAP1_DMA_CICR (0x04) +#define OMAP1_DMA_CSR (0x06) +#define OMAP1_DMA_CEN (0x10) +#define OMAP1_DMA_CFN (0x12) +#define OMAP1_DMA_CSFI (0x14) +#define OMAP1_DMA_CSEI (0x16) +#define OMAP1_DMA_CPC (0x18) /* 15xx only */ +#define OMAP1_DMA_CSAC (0x18) +#define OMAP1_DMA_CDAC (0x1a) +#define OMAP1_DMA_CDEI (0x1c) +#define OMAP1_DMA_CDFI (0x1e) +#define OMAP1_DMA_CLNK_CTRL (0x28) + +/* Channel specific registers only on omap1 */ +#define OMAP1_DMA_CSSA_L (0x08) +#define OMAP1_DMA_CSSA_U (0x0a) +#define OMAP1_DMA_CDSA_L (0x0c) +#define OMAP1_DMA_CDSA_U (0x0e) +#define OMAP1_DMA_COLOR_L (0x20) +#define OMAP1_DMA_COLOR_U (0x22) +#define OMAP1_DMA_CCR2 (0x24) +#define OMAP1_DMA_LCH_CTRL (0x2a) /* not on 15xx */ +#define OMAP1_DMA_CCEN 0 +#define OMAP1_DMA_CCFN 0 + +#endif /* __ASM_ARCH_OMAP1_DMA_H */ diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 02232ca..fcc7d6e 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -21,6 +21,8 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H +#include + /* Move omap4 specific defines to dma-44xx.h */ #include "dma-44xx.h" @@ -429,6 +431,76 @@ enum omap_dma_channel_mode { OMAP_DMA_LCH_PD }; +/* Register offset's structures */ +struct dma_irq_offset { + int irq_status_l0; + int irq_enable_l0; +}; + +struct dma_common_ch { + /* common channel specific register offsets */ + int csdp; + int ccr; + int cicr; + int csr; + int cen; + int cfn; + int csfi; + int csei; + int cpc; + int csac; + int cdac; + int cdei; + int cdfi; + int clnk_ctrl; +}; + +struct dma_ch_specific { + /* channel specific registers */ + int cssa; + int cssa_l; + int cssa_u; + int cdsa; + int cdsa_l; + int cdsa_u; + int color; + int color_l; + int color_u; + int ccr2; + int lch_ctrl; + int ccen; + int ccfn; +}; + +struct dma_reg_caps { + int caps_0; + int caps_0u; + int caps_0l; + int caps_1u; + int caps_1l; + int caps_2; + int caps_3; + int caps_4; +}; + +struct omap_dma_reg_offset { + int lch_base; + + /* Hardware registers */ + int gcr; + int gscr; + int grst; + int hw_id; + int rev; + int sysstatus; + int ocp_sysconfig; + + struct dma_ch_specific ch_specific; + struct dma_reg_caps reg_caps; + struct dma_common_ch common_ch; + struct dma_irq_offset irqreg; +}; + struct omap_dma_channel_params { int data_type; /* data type 8,16,32 */ int elem_count; /* number of elements in a frame */ @@ -463,6 +535,52 @@ struct omap_dma_channel_params { #endif }; +struct omap_dma_lch { + int next_lch; + int dev_id; + u16 saved_csr; + u16 enabled_irqs; + const char *dev_name; + void (*callback)(int lch, u16 ch_status, void *data); + void *data; + /* required for Dynamic chaining */ + int prev_linked_ch; + int next_linked_ch; + int state; + int chain_id; + + int status; + long flags; +}; + +struct omap_dma_dev_attr { + u32 dma_dev_attr; + u16 dma_lch_count; +}; + +/* System DMA platform data structure */ +struct omap_system_dma_plat_info { + struct omap_dma_dev_attr *dma_attr; + u32 errata; + struct omap_dma_reg_offset *dma_reg_offset; + void __iomem *omap_dma_base; + void (*clear_lch_regs)(int lch); + void (*clear_ccr_csr)(int lch); + void (*set_dma_write_mode)(int lch, int mode); + void (*enable_irq_lch)(int lch); + void (*disable_irq_lch)(int lch); + int (*dma_running) (int dma_chan_count); + int (*dma_handle_ch) (int ch); + void (*sync_device_set)(int dev_id, int free_ch); + int (*set_prio_lch)(int l, unsigned char read_prio, + unsigned char write_prio); + int (*dma_irq_register)(int dma_irq, int irq_count, + struct omap_dma_lch *dma_chan); + void (*enable_lnk)(int lch); + void (*disable_lnk)(int lch); + void (*enable_channel_irq)(int lch); + void (*disable_channel_irq)(int lch); +}; extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, From patchwork Fri Jul 23 23:22:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Sin X-Patchwork-Id: 114030 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NN7Gnv030447 for ; Fri, 23 Jul 2010 23:07:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759508Ab0GWXHR (ORCPT ); Fri, 23 Jul 2010 19:07:17 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:43191 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759491Ab0GWXHP (ORCPT ); Fri, 23 Jul 2010 19:07:15 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6NN6r2N004903 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 23 Jul 2010 18:06:53 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6NN6pMd014645; Fri, 23 Jul 2010 18:06:51 -0500 (CDT) Received: from localhost.localdomain (neo.am.dhcp.ti.com [128.247.75.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBDHgPP19222; Mon, 13 Dec 1915 12:42:26 -0500 (CDT) From: David Sin To: , , Tony Lindgren , Russell King Cc: Hari Kanigeri , Ohad Ben-Cohen , Vaibhav Hiremath , Santosh Shilimkar , Lajos Molnar , David Sin Subject: [RFC 5/8] TILER-DMM: TILER interface file and documentation Date: Fri, 23 Jul 2010 18:22:25 -0500 Message-Id: <1279927348-21750-6-git-send-email-davidsin@ti.com> X-Mailer: git-send-email 1.6.6.2 In-Reply-To: <1279927348-21750-5-git-send-email-davidsin@ti.com> References: <1279927348-21750-1-git-send-email-davidsin@ti.com> <1279927348-21750-2-git-send-email-davidsin@ti.com> <1279927348-21750-3-git-send-email-davidsin@ti.com> <1279927348-21750-4-git-send-email-davidsin@ti.com> <1279927348-21750-5-git-send-email-davidsin@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 23:07:20 +0000 (UTC) diff --git a/Documentation/arm/TILER b/Documentation/arm/TILER new file mode 100644 index 0000000..9c54037 --- /dev/null +++ b/Documentation/arm/TILER @@ -0,0 +1,144 @@ +TILER driver + +TILER is a hardware block made by Texas Instruments. Its purpose is to +organize video/image memory in a 2-dimensional fashion to limit memory +bandwidth and facilitate 0 effort rotation and mirroring. The TILER driver +facilitates allocating, freeing, as well as mapping 2D blocks (areas) in the +TILER container(s). It also facilitates rotating and mirroring the allocated +blocks or its rectangular subsections. + +TERMINOLOGY + +"slot" + +The basic TILER driver operates on blocks of slots. A slot is the granularity +of the TILER hardware device. For all current uses it is 4K, but could also be +16 or 64K. The DMM-TILER TRM refers to this as "page" but we want to separate +this concept from the MMU pages. + +"page" + +The granularity of the MMU, used by the kernel. This is 4K. + +"block" + +The TILER hardware block supports 1D and 2D blocks. A 2D block is a rectangular +arrangement of slots with arbitrary width and height in a 2D container. A +1D block is a linear arrangement of slots with arbitrary length in a 1D +container. This TILER driver only supports 2D blocks. + +"container" + +The TILER driver supports an arbitrary TILER container size. However, for +all current implementations it is 256 by 128 slots. The container currently can +only be used as a 2D container. + +"reserved area" + +Each block resides within a reserved area in the container. This area may +be larger than the actual set of slots that a block occupies. The reason for +this is to protect access from one block into another. Since TILER container is +mmap-ped into user space as individual pages, all slots that are spanned by +that page become visible to the user. The tiler driver allows restricting the +granularity of the reserved area (default alignment) as well as the mapped +area (granularity). + +KERNEL API to the TILER driver. + +1. Allocating and freeing a 1080p YUV422 block + + struct tiler_block_t blk = {0}; + int res; + + blk.width = 1920; + blk.height = 1080; + res = tiler_alloc(&blk, TILFMT_16BIT, 0, 0); + + tiler_free(&blk); + +2. Allocating and freeing a 1080p YUV420p block + + struct tiler_block_t blk_Y = {0}, blk_UV = {0}; + int res; + + blk_Y.width = 1920; + blk_Y.height = 1080; + blk_UV.widht = 960; + blk_UV.height = 540; + res = tiler_alloc(&blk_Y, TILFMT_8BIT, 0, 0) ? : + tiler_alloc(&blk_UV, TILFMT_16BIT, PAGE_SIZE, + blk_y->phys & ~PAGE_MASK); + + tiler_free(&blk_Y); + tiler_free(&blk_UV); + +Note how we allocated the UV block at the same in-page offset as the Y buffer. +This facilitates mmap-ping both Y and UV blocks into userspace as one +contiguous buffer. + +3. Mmap-ing YUV420p block into user space + + static int my_mmap(struct file *file, struct vm_area_struct *vma) + { + unsigned long size = (vma->vm_end - vma->vm_start); + unsigned long start = vma->vm_start; + + if (size != tiler_size(&blk_Y) + tiler_size(&blk_UV)) + return -EINVAL; + + return tiler_mmap_blk(&blk_Y, 0, tiler_size(&blk_Y), vma, 0) ? + : tiler_mmap_blk(&blk_UV, 0, tiler_size(&blk_UV), vma, + tiler_size(&blk_Y)); + } + +4. Ioremap-ing YUV422 block into kernel space + + void *my_ioremap(tiler_block_t *blk) { + struct vm_struct *area; + int res; + + area = get_vm_area(tiler_size(&blk), VM_IOREMAP); + if (!area) + return NULL; + + int res = tiler_ioremap_blk(&blk, 0, tiler_size(&block), + (u32) area->addr, MT_DEVICE_WC); + if (res) { + vunmap(area->addr); + return NULL; + } + return area->addr; + } + +CONFIGURATIONS + +The TILER driver allows specifying a container manager (tcm) for each +pixel format. The same container manager can be specified for more than +one pixel formats. + +Each container manager also operates on a PAT instance. One can also +specify a "virtual" PAT (with a linear preassigned memory space no actual +PAT programming), but it is not implemented. + +PARAMETERS + +The TILER driver allows specifying: + + granularity (tiler.grain, CONFIG_TILER_GRANULARITY): + + Each block is mapped in width-chunks of granularity. + + default alignment (tiler.align, CONFIG_TILER_ALIGNMENT): + + Default alignment if aligment is not specified (0). Otherwise, + blocks are allocated at an address aligned to the value given plus an + offset within the alignment. + + cache limit (tiler.cache, CONFIG_TILER_CACHE_LIMIT): + + TILER driver keeps a cache of allocated pages to speed up allocation of + TILER blocks. You can set a limit of how much memory the TILER driver + should keep if there are no actual TILER allocations. This also means + that if there is less memory used than this limit, the pages of freed + tiler blocks will not actually be freed, but instead are put into this + cache. diff --git a/arch/arm/mach-omap2/include/mach/tiler.h b/arch/arm/mach-omap2/include/mach/tiler.h new file mode 100644 index 0000000..8509678 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/tiler.h @@ -0,0 +1,201 @@ +/* + * tiler.h + * + * TILER driver support functions for TI TILER hardware block. + * + * Authors: Lajos Molnar + * David Sin + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef TILER_H +#define TILER_H + +#include + +/* + * ----------------------------- API Definitions ----------------------------- + */ + +/* return true if physical address is in the tiler container */ +bool is_tiler_addr(u32 phys); + +enum tiler_fmt { + TILFMT_MIN = -2, + TILFMT_INVALID = -2, + TILFMT_NONE = -1, + TILFMT_8BIT = 0, + TILFMT_16BIT = 1, + TILFMT_32BIT = 2, + TILFMT_MAX = 2, + TILFMT_PAGE = 3, /* for completeness */ +}; + +/* tiler block info */ +struct tiler_block_t { + u32 phys; /* system space (L3) tiler addr */ + u32 width; /* width */ + u32 height; /* height */ +}; + +/* tiler (image/video frame) view */ +struct tiler_view_t { + u32 tsptr; /* tiler space addr */ + u32 width; /* width */ + u32 height; /* height */ + u32 bpp; /* bytes per pixel */ + s32 h_inc; /* horizontal increment */ + s32 v_inc; /* vertical increment */ +}; + +/* get tiler format for a physical address */ +enum tiler_fmt tiler_fmt(u32 phys); + +/* get tiler block bytes-per-pixel */ +u32 tiler_bpp(const struct tiler_block_t *b); + +/* get tiler block physical stride */ +u32 tiler_pstride(const struct tiler_block_t *b); + +/* get tiler block virtual stride */ +static inline u32 tiler_vstride(const struct tiler_block_t *b) +{ + return PAGE_ALIGN((b->phys & ~PAGE_MASK) + tiler_bpp(b) * b->width); +} + +/* returns the virtual size of the block (for mmap) */ +static inline u32 tiler_size(const struct tiler_block_t *b) +{ + return b->height * tiler_vstride(b); +} + +/** + * Reserves a 2D TILER block area and memory. + * + * @param blk pointer to tiler block data. This must be set up ('phys' member + * must be 0) with the tiler block information. + * @param fmt TILER block format + * @param align block alignment (default: normally PAGE_SIZE) + * @param offs block offset + * + * @return error status + */ +s32 tiler_alloc(struct tiler_block_t *blk, enum tiler_fmt fmt, u32 align, + u32 offs); + +/** + * Mmaps a portion of a tiler block to a virtual address. Use this method in + * your driver's mmap function to potentially combine multiple tiler blocks as + * one virtual buffer. + * + * @param blk pointer to tiler block data + * @param offs offset from where to map (must be page aligned) + * @param size size of area to map (must be page aligned) + * @param vma VMM memory area to map to + * @param voffs offset (from vm_start) in the VMM memory area to start + * mapping at + * + * @return error status + */ +s32 tiler_mmap_blk(struct tiler_block_t *blk, u32 offs, u32 size, + struct vm_area_struct *vma, u32 voffs); + +/** + * Ioremaps a portion of a tiler block. Use this method in your driver instead + * of ioremap to potentially combine multiple tiler blocks as one virtual + * buffer. + * + * @param blk pointer to tiler block data + * @param offs offset from where to map (must be page aligned) + * @param size size of area to map (must be page aligned) + * @param addr virtual address + * @param mtype ioremap memory type (e.g. MT_DEVICE) + * + * @return error status + */ +s32 tiler_ioremap_blk(struct tiler_block_t *blk, u32 offs, u32 size, u32 addr, + u32 mtype); + +/** + * Frees TILER memory. Since there may be multiple references for the same area + * if duplicated by tiler_dup, the area is only actually freed if all references + * have been freed. + * + * @param blk pointer to a tiler block data as filled by tiler_alloc, + * tiler_map or tiler_dup. 'phys' member will be set to 0 on + * success. + */ +void tiler_free(struct tiler_block_t *blk); + +/** + * Create a view based on a tiler address and width and height + * + * This method should only be used as a last resort, e.g. if tilview object + * cannot be passed because of incoherence with other view 2D objects that must + * be supported. + * + * @param view Pointer to a view where the information will be stored + * @param ssptr MUST BE a tiler address + * @param width view width + * @param height view height + */ +void tilview_create(struct tiler_view_t *view, u32 phys, u32 width, u32 height); + +/** + * Obtains the view information for a tiler block + * + * @param view Pointer to a view where the information will be stored + * @param blk Pointer to an existing allocated tiler block + */ +void tilview_get(struct tiler_view_t *view, struct tiler_block_t *blk); + +/** + * Crops a tiler view to a rectangular portion. Crop area must be fully within + * the orginal tiler view: 0 <= left <= left + width <= view->width, also: + * 0 <= top <= top + height <= view->height. + * + * @param view Pointer to tiler view to be cropped + * @param left x of top-left corner + * @param top y of top-left corner + * @param width crop width + * @param height crop height + * + * @return error status. The view will be reduced to the crop region if the + * crop region is correct. Otherwise, no modifications are made. + */ +s32 tilview_crop(struct tiler_view_t *view, u32 left, u32 top, u32 width, + u32 height); + +/** + * Rotates a tiler view clockwise by a specified degree. + * + * @param view Pointer to tiler view to be cropped + * @param rotate Degree of rotation (clockwise). Must be a multiple of + * 90. + * @return error status. View is not modified on error; otherwise, it is + * updated in place. + */ +s32 tilview_rotate(struct tiler_view_t *view, s32 rotation); + +/** + * Mirrors a tiler view horizontally and/or vertically. + * + * @param view Pointer to tiler view to be cropped + * @param flip_x Mirror horizontally (left-to-right) + * @param flip_y Mirror vertically (top-to-bottom) + * + * @return error status. View is not modified on error; otherwise, it is + * updated in place. + */ +s32 tilview_flip(struct tiler_view_t *view, bool flip_x, bool flip_y); + +#endif From patchwork Fri May 14 12:06:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gadiyar X-Patchwork-Id: 99590 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4EC6FI4007238 for ; Fri, 14 May 2010 12:06:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758781Ab0ENMGO (ORCPT ); Fri, 14 May 2010 08:06:14 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59157 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756791Ab0ENMGM (ORCPT ); Fri, 14 May 2010 08:06:12 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4EC68lU032420 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 14 May 2010 07:06:11 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4EC67o1014863; Fri, 14 May 2010 17:36:07 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4EC67Vk016698; Fri, 14 May 2010 17:36:07 +0530 Received: (from a0393673@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4EC67od016696; Fri, 14 May 2010 17:36:07 +0530 From: Anand Gadiyar To: linux-omap@vger.kernel.org Cc: Anand Gadiyar Subject: [PATCH 1/2] omap: 3630: introduce CHIP_GE_3630ES1_1 Date: Fri, 14 May 2010 17:36:06 +0530 Message-Id: <1273838767-16638-1-git-send-email-gadiyar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 14 May 2010 12:06:15 +0000 (UTC) Index: linux-omap-2.6/arch/arm/plat-omap/include/plat/cpu.h =================================================================== --- linux-omap-2.6.orig/arch/arm/plat-omap/include/plat/cpu.h +++ linux-omap-2.6/arch/arm/plat-omap/include/plat/cpu.h @@ -431,6 +431,7 @@ IS_OMAP_TYPE(3517, 0x3517) CHIP_IS_OMAP3630ES1) #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ CHIP_IS_OMAP3630ES1) +#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1) int omap_chip_is(struct omap_chip_id oci); From patchwork Fri Aug 6 12:34:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 117794 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CW6W7016517 for ; Fri, 6 Aug 2010 12:32:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934646Ab0HFMcB (ORCPT ); Fri, 6 Aug 2010 08:32:01 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:52298 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932824Ab0HFMbp (ORCPT ); Fri, 6 Aug 2010 08:31:45 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76CVe0Z004166 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 07:31:43 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76CVaja022391; Fri, 6 Aug 2010 18:01:38 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, b-cousson@ti.com, rnayak@ti.com, Charulatha V , "Basak, Partha" Subject: [PATCH 07/13 v5] OMAP: GPIO: add GPIO hwmods structures for OMAP243X Date: Fri, 6 Aug 2010 18:04:19 +0530 Message-Id: <1281098065-24177-8-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281098065-24177-7-git-send-email-charu@ti.com> References: <1281098065-24177-1-git-send-email-charu@ti.com> <1281098065-24177-2-git-send-email-charu@ti.com> <1281098065-24177-3-git-send-email-charu@ti.com> <1281098065-24177-4-git-send-email-charu@ti.com> <1281098065-24177-5-git-send-email-charu@ti.com> <1281098065-24177-6-git-send-email-charu@ti.com> <1281098065-24177-7-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:32:10 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4526628..d3582e1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -33,6 +34,11 @@ static struct omap_hwmod omap2430_mpu_hwmod; static struct omap_hwmod omap2430_iva_hwmod; static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; +static struct omap_hwmod omap2430_gpio1_hwmod; +static struct omap_hwmod omap2430_gpio2_hwmod; +static struct omap_hwmod omap2430_gpio3_hwmod; +static struct omap_hwmod omap2430_gpio4_hwmod; +static struct omap_hwmod omap2430_gpio5_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -165,12 +171,296 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* L4 WKUP -> GPIO1 interface */ + +static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { + { + .pa_start = 0x4900C000, + .pa_end = 0x4900C1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> GPIO2 interface */ + +static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { + { + .pa_start = 0x4900E000, + .pa_end = 0x4900E1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> GPIO3 interface */ + +static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { + { + .pa_start = 0x49010000, + .pa_end = 0x490101ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> GPIO4 interface */ + +static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { + { + .pa_start = 0x49012000, + .pa_end = 0x490121ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio4_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> GPIO5 interface */ + +static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { + { + .pa_start = 0x480B6000, + .pa_end = 0x480B61ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap2430_gpio5_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* GPIO common */ + +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, + /* + * off_mode is supported by GPIO, but it is not + * supported by software due to leakage current problem. + * Hence making off_mode_support flag as false + */ + .off_mode_support = false, +}; + +static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap243x_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap243x_gpio_sysc, + .rev = 0, +}; + +/* GPIO1 */ + +static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK1 }, +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { + &omap2430_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap2430_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap243x_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* GPIO2 */ + +static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK2 }, +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { + &omap2430_l4_wkup__gpio2, +}; + +static struct omap_hwmod omap2430_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap243x_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* GPIO3 */ + +static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK3 }, +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { + &omap2430_l4_wkup__gpio3, +}; + +static struct omap_hwmod omap2430_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap243x_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* GPIO4 */ + +static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK4 }, +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { + &omap2430_l4_wkup__gpio4, +}; + +static struct omap_hwmod omap2430_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap243x_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* GPIO5 */ + +static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK5 }, +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { + &omap2430_l4_core__gpio5, +}; + +static struct omap_hwmod omap2430_gpio5_hwmod = { + .name = "gpio5", + .mpu_irqs = omap243x_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), + .main_clk = "gpio5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_ST_GPIO5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, + }, + }, + .slaves = omap2430_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, &omap2430_iva_hwmod, + &omap2430_gpio1_hwmod, + &omap2430_gpio2_hwmod, + &omap2430_gpio3_hwmod, + &omap2430_gpio4_hwmod, + &omap2430_gpio5_hwmod, NULL, }; From patchwork Fri Aug 6 12:34:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 117795 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CW6W8016517 for ; Fri, 6 Aug 2010 12:32:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934680Ab0HFMcF (ORCPT ); Fri, 6 Aug 2010 08:32:05 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:52297 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934299Ab0HFMbp (ORCPT ); Fri, 6 Aug 2010 08:31:45 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76CVeQv004165 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 07:31:42 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76CVajZ022391; Fri, 6 Aug 2010 18:01:38 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, b-cousson@ti.com, rnayak@ti.com, Charulatha V , "Basak, Partha" Subject: [PATCH 06/13 v5] OMAP: GPIO: add GPIO hwmods structures for OMAP242X Date: Fri, 6 Aug 2010 18:04:18 +0530 Message-Id: <1281098065-24177-7-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281098065-24177-6-git-send-email-charu@ti.com> References: <1281098065-24177-1-git-send-email-charu@ti.com> <1281098065-24177-2-git-send-email-charu@ti.com> <1281098065-24177-3-git-send-email-charu@ti.com> <1281098065-24177-4-git-send-email-charu@ti.com> <1281098065-24177-5-git-send-email-charu@ti.com> <1281098065-24177-6-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:32:10 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 3cc768e..228ffe4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -33,6 +34,10 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_iva_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_gpio1_hwmod; +static struct omap_hwmod omap2420_gpio2_hwmod; +static struct omap_hwmod omap2420_gpio3_hwmod; +static struct omap_hwmod omap2420_gpio4_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -165,12 +170,241 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* L4 WKUP -> GPIO1 interface */ +static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { + { + .pa_start = 0x48018000, + .pa_end = 0x480181ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> GPIO2 interface */ +static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { + { + .pa_start = 0x4801a000, + .pa_end = 0x4801a1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> GPIO3 interface */ +static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { + { + .pa_start = 0x4801c000, + .pa_end = 0x4801c1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> GPIO4 interface */ +static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { + { + .pa_start = 0x4801e000, + .pa_end = 0x4801e1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio4_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* GPIO common */ + +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, + /* + * off_mode is supported by GPIO, but it is not + * supported by software due to leakage current problem. + * Hence making off_mode_support flag as false + */ + .off_mode_support = false, +}; + +static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap242x_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap242x_gpio_sysc, + .rev = 0, +}; + +/* GPIO1 */ + +static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK1 }, +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { + &omap2420_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap2420_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap242x_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* GPIO2 */ + +static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK2 }, +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { + &omap2420_l4_wkup__gpio2, +}; + +static struct omap_hwmod omap2420_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap242x_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* GPIO3 */ + +static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK3 }, +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { + &omap2420_l4_wkup__gpio3, +}; + +static struct omap_hwmod omap2420_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap242x_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* GPIO4 */ + +static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_24XX_GPIO_BANK4 }, +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { + &omap2420_l4_wkup__gpio4, +}; + +static struct omap_hwmod omap2420_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap242x_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, + &omap2420_gpio1_hwmod, + &omap2420_gpio2_hwmod, + &omap2420_gpio3_hwmod, + &omap2420_gpio4_hwmod, NULL, }; From patchwork Fri Aug 6 12:34:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 117796 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CW6W9016517 for ; Fri, 6 Aug 2010 12:32:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933664Ab0HFMcH (ORCPT ); Fri, 6 Aug 2010 08:32:07 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:52294 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934262Ab0HFMbo (ORCPT ); Fri, 6 Aug 2010 08:31:44 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76CVeBJ004163 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 07:31:42 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76CVajW022391; Fri, 6 Aug 2010 18:01:37 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, b-cousson@ti.com, rnayak@ti.com, Charulatha V , "Basak, Partha" Subject: [PATCH 03/13 v5] OMAP: GPIO: Introduce support for OMAP16xx chip GPIO init Date: Fri, 6 Aug 2010 18:04:15 +0530 Message-Id: <1281098065-24177-4-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281098065-24177-3-git-send-email-charu@ti.com> References: <1281098065-24177-1-git-send-email-charu@ti.com> <1281098065-24177-2-git-send-email-charu@ti.com> <1281098065-24177-3-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:32:11 +0000 (UTC) diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c new file mode 100644 index 0000000..727c52b --- /dev/null +++ b/arch/arm/mach-omap1/gpio16xx.c @@ -0,0 +1,208 @@ +/* + * OMAP16XX-specific gpio code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Author: + * Charulatha V + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#define OMAP1610_GPIO1_BASE 0xfffbe400 +#define OMAP1610_GPIO2_BASE 0xfffbec00 +#define OMAP1610_GPIO3_BASE 0xfffbb400 +#define OMAP1610_GPIO4_BASE 0xfffbbc00 +#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE + +static struct omap_gpio_dev_attr omap16xx_gpio_attr = { + .bank_width = 16, +}; + +/* + * OMAP16XX MPU GPIO interface data + */ +static struct __initdata resource omap16xx_mpu_gpio_resources[] = { + { + .start = OMAP1_MPUIO_VBASE, + .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MPUIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { + .virtual_irq_start = IH_MPUIO_BASE, + .bank_type = METHOD_MPUIO, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_mpu_gpio = { + .name = "omap-gpio", + .id = 0, + .dev = { + .platform_data = &omap16xx_mpu_gpio_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_mpu_gpio_resources), + .resource = omap16xx_mpu_gpio_resources, +}; + +/* + * OMAP16XX GPIO1 interface data + */ +static struct __initdata resource omap16xx_gpio1_resources[] = { + { + .start = OMAP1610_GPIO1_BASE, + .end = OMAP1610_GPIO1_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_GPIO_BANK1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { + .virtual_irq_start = IH_GPIO_BASE, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio1 = { + .name = "omap-gpio", + .id = 1, + .dev = { + .platform_data = &omap16xx_gpio1_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio1_resources), + .resource = omap16xx_gpio1_resources, +}; + +/* + * OMAP16XX GPIO2 interface data + */ +static struct __initdata resource omap16xx_gpio2_resources[] = { + { + .start = OMAP1610_GPIO2_BASE, + .end = OMAP1610_GPIO2_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_1610_GPIO_BANK2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { + .virtual_irq_start = IH_GPIO_BASE + 16, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio2 = { + .name = "omap-gpio", + .id = 2, + .dev = { + .platform_data = &omap16xx_gpio2_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio2_resources), + .resource = omap16xx_gpio2_resources, +}; + +/* + * OMAP16XX GPIO3 interface data + */ +static struct __initdata resource omap16xx_gpio3_resources[] = { + { + .start = OMAP1610_GPIO3_BASE, + .end = OMAP1610_GPIO3_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_1610_GPIO_BANK3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { + .virtual_irq_start = IH_GPIO_BASE + 32, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio3 = { + .name = "omap-gpio", + .id = 3, + .dev = { + .platform_data = &omap16xx_gpio3_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio3_resources), + .resource = omap16xx_gpio3_resources, +}; + +/* + * OMAP16XX GPIO4 interface data + */ +static struct __initdata resource omap16xx_gpio4_resources[] = { + { + .start = OMAP1610_GPIO4_BASE, + .end = OMAP1610_GPIO4_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_1610_GPIO_BANK4, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { + .virtual_irq_start = IH_GPIO_BASE + 48, + .bank_type = METHOD_GPIO_1610, + .gpio_attr = &omap16xx_gpio_attr, +}; + +static struct __initdata platform_device omap16xx_gpio4 = { + .name = "omap-gpio", + .id = 4, + .dev = { + .platform_data = &omap16xx_gpio4_config, + }, + .num_resources = ARRAY_SIZE(omap16xx_gpio4_resources), + .resource = omap16xx_gpio4_resources, +}; + +static struct __initdata platform_device * omap16xx_gpio_dev[] = { + &omap16xx_mpu_gpio, + &omap16xx_gpio1, + &omap16xx_gpio2, + &omap16xx_gpio3, + &omap16xx_gpio4, +}; + +/* + * omap16xx_gpio_init needs to be done before + * machine_init functions access gpio APIs. + * Hence omap16xx_gpio_init is a postcore_initcall. + */ +static int __init omap16xx_gpio_init(void) +{ + int i; + + if (!cpu_is_omap16xx()) + return -EINVAL; + + for (i = 0; i < sizeof(omap16xx_gpio_dev); i++) + platform_device_register(omap16xx_gpio_dev[i]); + + gpio_bank_count = sizeof(omap16xx_gpio_dev); + + return 0; +} +postcore_initcall(omap16xx_gpio_init); From patchwork Fri Aug 6 12:39:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Nikula X-Patchwork-Id: 117797 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CcNPj017817 for ; Fri, 6 Aug 2010 12:38:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934883Ab0HFMiK (ORCPT ); Fri, 6 Aug 2010 08:38:10 -0400 Received: from mail-ew0-f46.google.com ([209.85.215.46]:46416 "EHLO mail-ew0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934066Ab0HFMh6 (ORCPT ); Fri, 6 Aug 2010 08:37:58 -0400 Received: by ewy23 with SMTP id 23so2746944ewy.19 for ; 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Fri, 06 Aug 2010 05:37:55 -0700 (PDT) From: Jarkko Nikula To: linux-omap@vger.kernel.org Cc: Tony Lindgren , Jarkko Nikula Subject: [PATCH] omap2: McBSP: Remove mux code for OMAP2420 McBSP2 and do cleanups Date: Fri, 6 Aug 2010 15:39:02 +0300 Message-Id: <1281098342-5161-1-git-send-email-jhnikula@gmail.com> X-Mailer: git-send-email 1.7.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:38:23 +0000 (UTC) diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 87aa4c9..fa8da0a 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -23,29 +23,6 @@ #include #include -#include "mux.h" - -static void omap2_mcbsp2_mux_setup(void) -{ - omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); - omap_mux_init_gpio(117, OMAP_PULL_ENA); - /* - * TODO: Need to add MUX settings for OMAP 2430 SDP - */ -} - -static void omap2_mcbsp_request(unsigned int id) -{ - if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) - omap2_mcbsp2_mux_setup(); -} - -static struct omap_mcbsp_ops omap2_mcbsp_ops = { - .request = omap2_mcbsp_request, -}; #ifdef CONFIG_ARCH_OMAP2420 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { @@ -55,7 +32,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -63,7 +39,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) @@ -82,7 +57,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -90,7 +64,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP3_BASE, @@ -98,7 +71,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP4_BASE, @@ -106,7 +78,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP5_BASE, @@ -114,7 +85,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) @@ -133,7 +103,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x6F, }, { @@ -143,7 +112,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x3FF, }, { @@ -153,7 +121,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x6F, }, { @@ -162,7 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x6F, }, { @@ -171,7 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x6F, }, }; @@ -189,28 +154,24 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, .tx_irq = OMAP44XX_IRQ_MCBSP1, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, .tx_irq = OMAP44XX_IRQ_MCBSP2, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, .tx_irq = OMAP44XX_IRQ_MCBSP3, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, .tx_irq = OMAP44XX_IRQ_MCBSP4, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) From patchwork Fri Aug 6 12:34:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 117790 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CW6W3016517 for ; Fri, 6 Aug 2010 12:32:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934601Ab0HFMbz (ORCPT ); Fri, 6 Aug 2010 08:31:55 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:48638 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934519Ab0HFMbr (ORCPT ); Fri, 6 Aug 2010 08:31:47 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76CVgue025306 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 07:31:44 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76CVajf022391; Fri, 6 Aug 2010 18:01:39 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, b-cousson@ti.com, rnayak@ti.com, Charulatha V , "Basak, Partha" Subject: [PATCH 12/13 v5] OMAP: GPIO: Use dev_pm_ops instead of sys_dev_class Date: Fri, 6 Aug 2010 18:04:24 +0530 Message-Id: <1281098065-24177-13-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281098065-24177-12-git-send-email-charu@ti.com> References: <1281098065-24177-1-git-send-email-charu@ti.com> <1281098065-24177-2-git-send-email-charu@ti.com> <1281098065-24177-3-git-send-email-charu@ti.com> <1281098065-24177-4-git-send-email-charu@ti.com> <1281098065-24177-5-git-send-email-charu@ti.com> <1281098065-24177-6-git-send-email-charu@ti.com> <1281098065-24177-7-git-send-email-charu@ti.com> <1281098065-24177-8-git-send-email-charu@ti.com> <1281098065-24177-9-git-send-email-charu@ti.com> <1281098065-24177-10-git-send-email-charu@ti.com> <1281098065-24177-11-git-send-email-charu@ti.com> <1281098065-24177-12-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:32:09 +0000 (UTC) diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 6aeedea..c01e156 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -106,7 +106,7 @@ static void omap2_enter_full_retention(void) l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - omap2_gpio_prepare_for_idle(PWRDM_POWER_RET); + omap2_gpio_prepare_for_idle(false); if (omap2_pm_debug) { omap2_pm_dump(0, 0, 0); @@ -140,7 +140,7 @@ no_sleep: tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; omap2_pm_dump(0, 1, tmp); } - omap2_gpio_resume_after_idle(); + omap2_gpio_resume_after_idle(false); clk_enable(osc_ck); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index fb4994a..66c7e11 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -79,16 +79,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm; static struct powerdomain *core_pwrdm, *per_pwrdm; static struct powerdomain *cam_pwrdm; -static inline void omap3_per_save_context(void) -{ - omap_gpio_save_context(); -} - -static inline void omap3_per_restore_context(void) -{ - omap_gpio_restore_context(); -} - static void omap3_enable_io_chain(void) { int timeout = 0; @@ -395,15 +385,17 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); - omap2_gpio_prepare_for_idle(per_next_state); if (per_next_state == PWRDM_POWER_OFF) { if (core_next_state == PWRDM_POWER_ON) { per_next_state = PWRDM_POWER_RET; pwrdm_set_next_pwrst(per_pwrdm, per_next_state); per_state_modified = 1; - } else - omap3_per_save_context(); + } } + if (per_next_state == PWRDM_POWER_OFF) + omap2_gpio_prepare_for_idle(true); + else + omap2_gpio_prepare_for_idle(false); } if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) @@ -471,9 +463,10 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); - omap2_gpio_resume_after_idle(); if (per_prev_state == PWRDM_POWER_OFF) - omap3_per_restore_context(); + omap2_gpio_resume_after_idle(true); + else + omap2_gpio_resume_after_idle(false); omap_uart_resume_idle(2); if (per_state_modified) pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 6a5cf43..6686f9f 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -25,12 +25,12 @@ #include #include +#include #include #include #include #include #include -#include /* * OMAP1510 GPIO registers @@ -179,7 +179,6 @@ struct gpio_bank { * related to all instances of the device */ static struct gpio_bank *gpio_bank; - static int bank_width; /* TODO: Analyze removing gpio_bank_count usage from driver code */ @@ -1045,6 +1044,9 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); unsigned long flags; + if (!bank->mod_usage) + pm_runtime_get_sync(bank->dev); + spin_lock_irqsave(&bank->lock, flags); /* Set trigger to none. You need to enable the desired trigger with @@ -1061,22 +1063,19 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) __raw_writel(__raw_readl(reg) | (1 << offset), reg); } #endif - if (!cpu_class_is_omap1()) { - if (!bank->mod_usage) { - void __iomem *reg = bank->base; - u32 ctrl; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - reg += OMAP24XX_GPIO_CTRL; - else if (cpu_is_omap44xx()) - reg += OMAP4_GPIO_CTRL; - ctrl = __raw_readl(reg); - /* Module is enabled, clocks are not gated */ - ctrl &= 0xFFFFFFFE; - __raw_writel(ctrl, reg); - } - bank->mod_usage |= 1 << offset; + if ((!bank->mod_usage) && (!cpu_class_is_omap1())) { + void __iomem *reg = bank->base; + u32 ctrl; + if (bank->method == METHOD_GPIO_24XX) + reg += OMAP24XX_GPIO_CTRL; + else if (bank->method == METHOD_GPIO_44XX) + reg += OMAP4_GPIO_CTRL; + ctrl = __raw_readl(reg); + /* Module is enabled, clocks are not gated */ + ctrl &= 0xFFFFFFFE; + __raw_writel(ctrl, reg); } + bank->mod_usage |= 1 << offset; spin_unlock_irqrestore(&bank->lock, flags); return 0; @@ -1109,24 +1108,26 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) __raw_writel(1 << offset, reg); } #endif - if (!cpu_class_is_omap1()) { - bank->mod_usage &= ~(1 << offset); - if (!bank->mod_usage) { - void __iomem *reg = bank->base; - u32 ctrl; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - reg += OMAP24XX_GPIO_CTRL; - else if (cpu_is_omap44xx()) - reg += OMAP4_GPIO_CTRL; - ctrl = __raw_readl(reg); - /* Module is disabled, clocks are gated */ - ctrl |= 1; - __raw_writel(ctrl, reg); - } + bank->mod_usage &= ~(1 << offset); + if ((!bank->mod_usage) && (!cpu_class_is_omap1())) { + void __iomem *reg = bank->base; + u32 ctrl; + + if (bank->method == METHOD_GPIO_24XX) + reg += OMAP24XX_GPIO_CTRL; + else if (bank->method == METHOD_GPIO_44XX) + reg += OMAP4_GPIO_CTRL; + ctrl = __raw_readl(reg); + /* Module is disabled, clocks are gated */ + ctrl |= 1; + __raw_writel(ctrl, reg); } + _reset_gpio(bank, bank->chip.base + offset); spin_unlock_irqrestore(&bank->lock, flags); + + if (!bank->mod_usage) + pm_runtime_put_sync(bank->dev); } /* @@ -1728,7 +1729,6 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) } pm_runtime_enable(bank->dev); - pm_runtime_get_sync(bank->dev); omap_gpio_mod_init(bank, id); omap_gpio_chip_init(bank); @@ -1741,294 +1741,222 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) return 0; } -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) -static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) -{ - int i; - - if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) - return 0; +static void omap_gpio_save_context(struct device *dev); +static void omap_gpio_restore_context(struct device *dev); - for (i = 0; i < gpio_bank_count; i++) { - struct gpio_bank *bank = &gpio_bank[i]; - void __iomem *wake_status; - void __iomem *wake_clear; - void __iomem *wake_set; - unsigned long flags; +static int omap_gpio_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + void __iomem *wake_status; + void __iomem *wake_clear; + void __iomem *wake_set; + unsigned long flags; + struct gpio_bank *bank = &gpio_bank[pdev->id]; - switch (bank->method) { -#ifdef CONFIG_ARCH_OMAP16XX - case METHOD_GPIO_1610: - wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; - wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; - wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; - break; -#endif -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - case METHOD_GPIO_24XX: - wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; - wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; - wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; - break; -#endif -#ifdef CONFIG_ARCH_OMAP4 - case METHOD_GPIO_44XX: - wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; - wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; - wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; - break; -#endif - default: - continue; - } + omap_gpio_save_context(dev); - spin_lock_irqsave(&bank->lock, flags); - bank->saved_wakeup = __raw_readl(wake_status); - __raw_writel(0xffffffff, wake_clear); - __raw_writel(bank->suspend_wakeup, wake_set); - spin_unlock_irqrestore(&bank->lock, flags); + switch (bank->method) { + case METHOD_GPIO_1610: + wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; + wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; + wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; + break; + case METHOD_GPIO_24XX: + wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; + wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; + wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; + break; + case METHOD_GPIO_44XX: + wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; + wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; + wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; + break; + default: + return 0; } + spin_lock_irqsave(&bank->lock, flags); + bank->saved_wakeup = __raw_readl(wake_status); + __raw_writel(0xffffffff, wake_clear); + __raw_writel(bank->suspend_wakeup, wake_set); + spin_unlock_irqrestore(&bank->lock, flags); + return 0; } -static int omap_gpio_resume(struct sys_device *dev) +static int omap_gpio_resume(struct device *dev) { - int i; + struct platform_device *pdev = to_platform_device(dev); + struct gpio_bank *bank = &gpio_bank[pdev->id]; + void __iomem *wake_clear; + void __iomem *wake_set; + unsigned long flags; - if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) + switch (bank->method) { + case METHOD_GPIO_1610: + wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; + wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; + break; + case METHOD_GPIO_24XX: + wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; + wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; + break; + case METHOD_GPIO_44XX: + wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; + wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; + break; + default: return 0; + } - for (i = 0; i < gpio_bank_count; i++) { - struct gpio_bank *bank = &gpio_bank[i]; - void __iomem *wake_clear; - void __iomem *wake_set; - unsigned long flags; - - switch (bank->method) { -#ifdef CONFIG_ARCH_OMAP16XX - case METHOD_GPIO_1610: - wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; - wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; - break; -#endif -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - case METHOD_GPIO_24XX: - wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; - wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; - break; -#endif -#ifdef CONFIG_ARCH_OMAP4 - case METHOD_GPIO_44XX: - wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; - wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; - break; -#endif - default: - continue; - } + spin_lock_irqsave(&bank->lock, flags); + __raw_writel(0xffffffff, wake_clear); + __raw_writel(bank->saved_wakeup, wake_set); + spin_unlock_irqrestore(&bank->lock, flags); - spin_lock_irqsave(&bank->lock, flags); - __raw_writel(0xffffffff, wake_clear); - __raw_writel(bank->saved_wakeup, wake_set); - spin_unlock_irqrestore(&bank->lock, flags); - } + omap_gpio_restore_context(dev); return 0; } -static struct sysdev_class omap_gpio_sysclass = { - .name = "gpio", - .suspend = omap_gpio_suspend, - .resume = omap_gpio_resume, -}; - -static struct sys_device omap_gpio_device = { - .id = 0, - .cls = &omap_gpio_sysclass, -}; - -#endif - -#ifdef CONFIG_ARCH_OMAP2PLUS - static int workaround_enabled; -void omap2_gpio_prepare_for_idle(int power_state) +static int gpio_bank_runtime_suspend(struct device *dev) { - int i, c = 0; - int min = 0; - - if (cpu_is_omap34xx()) - min = 1; - - for (i = min; i < gpio_bank_count; i++) { - struct gpio_bank *bank = &gpio_bank[i]; - u32 l1, l2; - - if (bank->dbck_enable_mask) - clk_disable(bank->dbck); + u32 l1, l2; + struct platform_device *pdev = to_platform_device(dev); + struct gpio_bank *bank = &gpio_bank[pdev->id]; - if (power_state > PWRDM_POWER_OFF) - continue; + if (bank->dbck_enable_mask) + clk_disable(bank->dbck); - /* If going to OFF, remove triggering for all - * non-wakeup GPIOs. Otherwise spurious IRQs will be - * generated. See OMAP2420 Errata item 1.101. */ - if (!(bank->enabled_non_wakeup_gpios)) - continue; + /* If going to OFF, remove triggering for all + * non-wakeup GPIOs. Otherwise spurious IRQs will be + * generated. See OMAP2420 Errata item 1.101. */ + if (!(bank->enabled_non_wakeup_gpios)) + return 0; - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - bank->saved_datain = __raw_readl(bank->base + + if (bank->method == METHOD_GPIO_24XX) { + bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); - l1 = __raw_readl(bank->base + - OMAP24XX_GPIO_FALLINGDETECT); - l2 = __raw_readl(bank->base + - OMAP24XX_GPIO_RISINGDETECT); - } - - if (cpu_is_omap44xx()) { - bank->saved_datain = __raw_readl(bank->base + - OMAP4_GPIO_DATAIN); - l1 = __raw_readl(bank->base + - OMAP4_GPIO_FALLINGDETECT); - l2 = __raw_readl(bank->base + - OMAP4_GPIO_RISINGDETECT); - } - - bank->saved_fallingdetect = l1; - bank->saved_risingdetect = l2; - l1 &= ~bank->enabled_non_wakeup_gpios; - l2 &= ~bank->enabled_non_wakeup_gpios; - - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - __raw_writel(l1, bank->base + + l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); - __raw_writel(l2, bank->base + - OMAP24XX_GPIO_RISINGDETECT); - } + l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); + } else if (bank->method == METHOD_GPIO_44XX) { + bank->saved_datain = __raw_readl(bank->base + + OMAP4_GPIO_DATAIN); + l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT); + l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT); + } - if (cpu_is_omap44xx()) { - __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); - __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); - } + bank->saved_fallingdetect = l1; + bank->saved_risingdetect = l2; + l1 &= ~bank->enabled_non_wakeup_gpios; + l2 &= ~bank->enabled_non_wakeup_gpios; - c++; - } - if (!c) { - workaround_enabled = 0; - return; + if (bank->method == METHOD_GPIO_24XX) { + __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); + __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); + } else if (bank->method == METHOD_GPIO_44XX) { + __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); + __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); } + workaround_enabled = 1; + + return 0; } -void omap2_gpio_resume_after_idle(void) +static int gpio_bank_runtime_resume(struct device *dev) { - int i; - int min = 0; - - if (cpu_is_omap34xx()) - min = 1; - for (i = min; i < gpio_bank_count; i++) { - struct gpio_bank *bank = &gpio_bank[i]; - u32 l, gen, gen0, gen1; - - if (bank->dbck_enable_mask) - clk_enable(bank->dbck); + u32 l, gen, gen0, gen1; + struct platform_device *pdev = to_platform_device(dev); + struct gpio_bank *bank = &gpio_bank[pdev->id]; - if (!workaround_enabled) - continue; + if (bank->dbck_enable_mask) + clk_enable(bank->dbck); - if (!(bank->enabled_non_wakeup_gpios)) - continue; + if ((!workaround_enabled) || (!(bank->enabled_non_wakeup_gpios))) + return 0; - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - __raw_writel(bank->saved_fallingdetect, + if (bank->method == METHOD_GPIO_24XX) { + __raw_writel(bank->saved_fallingdetect, bank->base + OMAP24XX_GPIO_FALLINGDETECT); - __raw_writel(bank->saved_risingdetect, + __raw_writel(bank->saved_risingdetect, bank->base + OMAP24XX_GPIO_RISINGDETECT); - l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); - } - - if (cpu_is_omap44xx()) { - __raw_writel(bank->saved_fallingdetect, + l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); + } else if (bank->method == METHOD_GPIO_44XX) { + __raw_writel(bank->saved_fallingdetect, bank->base + OMAP4_GPIO_FALLINGDETECT); - __raw_writel(bank->saved_risingdetect, + __raw_writel(bank->saved_risingdetect, bank->base + OMAP4_GPIO_RISINGDETECT); - l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); - } + l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); + } - /* Check if any of the non-wakeup interrupt GPIOs have changed - * state. If so, generate an IRQ by software. This is - * horribly racy, but it's the best we can do to work around - * this silicon bug. */ - l ^= bank->saved_datain; - l &= bank->enabled_non_wakeup_gpios; + /* Check if any of the non-wakeup interrupt GPIOs have changed + * state. If so, generate an IRQ by software. This is + * horribly racy, but it's the best we can do to work around + * this silicon bug. */ + l ^= bank->saved_datain; + l &= bank->enabled_non_wakeup_gpios; - /* - * No need to generate IRQs for the rising edge for gpio IRQs - * configured with falling edge only; and vice versa. - */ - gen0 = l & bank->saved_fallingdetect; - gen0 &= bank->saved_datain; + /* + * No need to generate IRQs for the rising edge for gpio IRQs + * configured with falling edge only; and vice versa. + */ + gen0 = l & bank->saved_fallingdetect; + gen0 &= bank->saved_datain; - gen1 = l & bank->saved_risingdetect; - gen1 &= ~(bank->saved_datain); + gen1 = l & bank->saved_risingdetect; + gen1 &= ~(bank->saved_datain); - /* FIXME: Consider GPIO IRQs with level detections properly! */ - gen = l & (~(bank->saved_fallingdetect) & - ~(bank->saved_risingdetect)); - /* Consider all GPIO IRQs needed to be updated */ - gen |= gen0 | gen1; + /* FIXME: Consider GPIO IRQs with level detections properly! */ + gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect)); + /* Consider all GPIO IRQs needed to be updated */ + gen |= gen0 | gen1; - if (gen) { - u32 old0, old1; + if (gen) { + u32 old0, old1; - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - old0 = __raw_readl(bank->base + + if (bank->method == METHOD_GPIO_24XX) { + old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); - old1 = __raw_readl(bank->base + + old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); - __raw_writel(old0 | gen, bank->base + + __raw_writel(old0 | gen, bank->base + OMAP24XX_GPIO_LEVELDETECT0); - __raw_writel(old1 | gen, bank->base + + __raw_writel(old1 | gen, bank->base + OMAP24XX_GPIO_LEVELDETECT1); - __raw_writel(old0, bank->base + + __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); - __raw_writel(old1, bank->base + + __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); - } - - if (cpu_is_omap44xx()) { - old0 = __raw_readl(bank->base + + } else if (bank->method == METHOD_GPIO_44XX) { + old0 = __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0); - old1 = __raw_readl(bank->base + + old1 = __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); - __raw_writel(old0 | l, bank->base + + __raw_writel(old0 | l, bank->base + OMAP4_GPIO_LEVELDETECT0); - __raw_writel(old1 | l, bank->base + + __raw_writel(old1 | l, bank->base + OMAP4_GPIO_LEVELDETECT1); - __raw_writel(old0, bank->base + + __raw_writel(old0, bank->base + OMAP4_GPIO_LEVELDETECT0); - __raw_writel(old1, bank->base + + __raw_writel(old1, bank->base + OMAP4_GPIO_LEVELDETECT1); - } } } + return 0; } -#endif - -#ifdef CONFIG_ARCH_OMAP3 -/* save the registers of bank 2-6 */ -void omap_gpio_save_context(void) +/* save the registers of bank */ +static void omap_gpio_save_context(struct device *dev) { - int i; + struct platform_device *pdev = to_platform_device(dev); + struct gpio_bank *bank = &gpio_bank[pdev->id]; - /* saving banks from 2-6 only since GPIO1 is in WKUP */ - for (i = 1; i < gpio_bank_count; i++) { - struct gpio_bank *bank = &gpio_bank[i]; + if (bank->method == METHOD_GPIO_24XX) { bank->gpio_context.irqenable1 = __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); bank->gpio_context.irqenable2 = @@ -2049,17 +1977,37 @@ void omap_gpio_save_context(void) __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); bank->gpio_context.dataout = __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); + } else if (bank->method == METHOD_GPIO_44XX) { + bank->gpio_context.irqenable1 = + __raw_readl(bank->base + OMAP4_GPIO_IRQENABLE1); + bank->gpio_context.irqenable2 = + __raw_readl(bank->base + OMAP4_GPIO_IRQENABLE2); + bank->gpio_context.wake_en = + __raw_readl(bank->base + OMAP4_GPIO_WAKE_EN); + bank->gpio_context.ctrl = + __raw_readl(bank->base + OMAP4_GPIO_CTRL); + bank->gpio_context.oe = + __raw_readl(bank->base + OMAP4_GPIO_OE); + bank->gpio_context.leveldetect0 = + __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0); + bank->gpio_context.leveldetect1 = + __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); + bank->gpio_context.risingdetect = + __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT); + bank->gpio_context.fallingdetect = + __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT); + bank->gpio_context.dataout = + __raw_readl(bank->base + OMAP4_GPIO_DATAOUT); } } /* restore the required registers of bank 2-6 */ -void omap_gpio_restore_context(void) +static void omap_gpio_restore_context(struct device *dev) { - int i; + struct platform_device *pdev = to_platform_device(dev); + struct gpio_bank *bank = &gpio_bank[pdev->id]; - for (i = 1; i < gpio_bank_count; i++) { - struct gpio_bank *bank = &gpio_bank[i]; - __raw_writel(gpio_context[i].irqenable1, + if (bank->method == METHOD_GPIO_24XX) { __raw_writel(bank->gpio_context.irqenable1, bank->base + OMAP24XX_GPIO_IRQENABLE1); __raw_writel(bank->gpio_context.irqenable2, @@ -2080,14 +2028,88 @@ void omap_gpio_restore_context(void) bank->base + OMAP24XX_GPIO_FALLINGDETECT); __raw_writel(bank->gpio_context.dataout, bank->base + OMAP24XX_GPIO_DATAOUT); + } else if (bank->method == METHOD_GPIO_44XX) { + __raw_writel(bank->gpio_context.irqenable1, + bank->base + OMAP4_GPIO_IRQENABLE1); + __raw_writel(bank->gpio_context.irqenable2, + bank->base + OMAP4_GPIO_IRQENABLE2); + __raw_writel(bank->gpio_context.wake_en, + bank->base + OMAP4_GPIO_WAKE_EN); + __raw_writel(bank->gpio_context.ctrl, + bank->base + OMAP4_GPIO_CTRL); + __raw_writel(bank->gpio_context.oe, + bank->base + OMAP4_GPIO_OE); + __raw_writel(bank->gpio_context.leveldetect0, + bank->base + OMAP4_GPIO_LEVELDETECT0); + __raw_writel(bank->gpio_context.leveldetect1, + bank->base + OMAP4_GPIO_LEVELDETECT1); + __raw_writel(bank->gpio_context.risingdetect, + bank->base + OMAP4_GPIO_RISINGDETECT); + __raw_writel(bank->gpio_context.fallingdetect, + bank->base + OMAP4_GPIO_FALLINGDETECT); + __raw_writel(bank->gpio_context.dataout, + bank->base + OMAP4_GPIO_DATAOUT); } } + +void omap2_gpio_prepare_for_idle(bool save_context) +{ +#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ARCH_OMAP2PLUS) + int i; + + for (i = 0; i < gpio_bank_count; i++) { + struct gpio_bank *bank = &gpio_bank[i]; + struct platform_device *pdev = to_platform_device(bank->dev); + + /* + * Only if the device is used & if it supports off-mode, + * prepare for idle. + */ + if ((!bank->off_mode_support) || (!bank->mod_usage)) + continue; + + gpio_bank_runtime_suspend(bank->dev); + if (save_context) + omap_gpio_save_context(bank->dev); + omap_device_idle(pdev); + } +#endif +} + +void omap2_gpio_resume_after_idle(bool restore_context) +{ +#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ARCH_OMAP2PLUS) + int i; + + for (i = 0; i < gpio_bank_count; i++) { + struct gpio_bank *bank = &gpio_bank[i]; + if ((bank->off_mode_support) && (bank->mod_usage)) { + struct platform_device *pdev = + to_platform_device(bank->dev); + + omap_device_enable(pdev); + if (restore_context) + omap_gpio_restore_context(bank->dev); + gpio_bank_runtime_resume(bank->dev); + } + } + + workaround_enabled = 0; #endif +} + +static const struct dev_pm_ops gpio_pm_ops = { + .suspend = omap_gpio_suspend, + .resume = omap_gpio_resume, + .runtime_suspend = gpio_bank_runtime_suspend, + .runtime_resume = gpio_bank_runtime_resume, +}; static struct platform_driver omap_gpio_driver = { .probe = omap_gpio_probe, .driver = { .name = "omap-gpio", + .pm = &gpio_pm_ops, }, }; @@ -2110,21 +2132,8 @@ int __init omap_gpio_init(void) static int __init omap_gpio_sysinit(void) { - int ret = 0; - mpuio_init(); - -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) - if (cpu_is_omap16xx() || cpu_class_is_omap2()) { - if (ret == 0) { - ret = sysdev_class_register(&omap_gpio_sysclass); - if (ret == 0) - ret = sysdev_register(&omap_gpio_device); - } - } -#endif - - return ret; + return 0; } arch_initcall(omap_gpio_sysinit); diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 6d95eb2..b84b179 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -95,12 +95,10 @@ struct omap_gpio_platform_data { extern int gpio_bank_count; extern int omap_gpio_init(void); /* Call from board init only */ -extern void omap2_gpio_prepare_for_idle(int power_state); -extern void omap2_gpio_resume_after_idle(void); +extern void omap2_gpio_prepare_for_idle(bool save_context); +extern void omap2_gpio_resume_after_idle(bool restore_context); extern void omap_set_gpio_debounce(int gpio, int enable); extern void omap_set_gpio_debounce_time(int gpio, int enable); -extern void omap_gpio_save_context(void); -extern void omap_gpio_restore_context(void); /*-------------------------------------------------------------------------*/ /* Wrappers for "new style" GPIO calls, using the new infrastructure From patchwork Fri Aug 6 12:34:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 117791 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CW6W4016517 for ; Fri, 6 Aug 2010 12:32:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934611Ab0HFMb5 (ORCPT ); Fri, 6 Aug 2010 08:31:57 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:48639 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934526Ab0HFMbs (ORCPT ); Fri, 6 Aug 2010 08:31:48 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76CVgcH025307 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 07:31:44 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76CVajg022391; Fri, 6 Aug 2010 18:01:40 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, b-cousson@ti.com, rnayak@ti.com, Charulatha V , "Basak, Partha" Subject: [PATCH 13/13 v5] OMAP: GPIO: Remove omap_gpio_init() Date: Fri, 6 Aug 2010 18:04:25 +0530 Message-Id: <1281098065-24177-14-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281098065-24177-13-git-send-email-charu@ti.com> References: <1281098065-24177-1-git-send-email-charu@ti.com> <1281098065-24177-2-git-send-email-charu@ti.com> <1281098065-24177-3-git-send-email-charu@ti.com> <1281098065-24177-4-git-send-email-charu@ti.com> <1281098065-24177-5-git-send-email-charu@ti.com> <1281098065-24177-6-git-send-email-charu@ti.com> <1281098065-24177-7-git-send-email-charu@ti.com> <1281098065-24177-8-git-send-email-charu@ti.com> <1281098065-24177-9-git-send-email-charu@ti.com> <1281098065-24177-10-git-send-email-charu@ti.com> <1281098065-24177-11-git-send-email-charu@ti.com> <1281098065-24177-12-git-send-email-charu@ti.com> <1281098065-24177-13-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:32:09 +0000 (UTC) diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 41992ab..774867f 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -136,7 +136,6 @@ static void __init ams_delta_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static struct map_desc ams_delta_io_desc[] __initdata = { diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 180ce79..09b6165 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -325,7 +325,6 @@ static void __init omap_fsample_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); fsample_init_smc91x(); } diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index d2cda58..cf9aaff 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -374,7 +374,6 @@ static void __init h2_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); h2_init_smc91x(); } diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index c2ef4ff..423b45e 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -435,7 +435,6 @@ static void __init h3_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); h3_init_smc91x(); } diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 311899f..bc8f56f 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -278,7 +278,6 @@ static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); - omap_gpio_init(); omap_board_config = htcherald_config; omap_board_config_size = ARRAY_SIZE(htcherald_config); diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 3daf87a..27c283d 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -290,7 +290,6 @@ static void __init innovator_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { omap1510_fpga_init_irq(); diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 51a4539..397febe 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -246,7 +246,6 @@ static void __init omap_nokia770_init(void) platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); spi_register_board_info(nokia770_spi_board_info, ARRAY_SIZE(nokia770_spi_board_info)); - omap_gpio_init(); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); hwa742_dev_init(); diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 679740c..fcd67d0 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -283,7 +283,6 @@ static void __init osk_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); osk_init_smc91x(); osk_init_cf(); } diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 782bb25..69708ac 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -63,7 +63,6 @@ static void __init omap_palmte_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static const int palmte_keymap[] = { diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 6636290..644d217 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -62,7 +62,6 @@ omap_palmz71_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static int palmz71_keymap[] = { diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 34ab354..d8dbb4a 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -293,7 +293,6 @@ static void __init omap_perseus2_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); perseus2_init_smc91x(); } /* Only FPGA needs to be mapped here. All others are done with ioremap */ diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 2eb148b..18093a5 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -409,7 +409,6 @@ static void __init omap_sx1_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } /*----------------------------------------*/ diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 6b3cf14..794c497 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -158,7 +158,6 @@ static void __init voiceblue_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static void __init voiceblue_init(void) diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 8538e41..b86824e 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -144,7 +144,6 @@ static void __init omap_2430sdp_init_irq(void) omap_board_config_size = ARRAY_SIZE(sdp2430_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static struct twl4030_gpio_platform_data sdp2430_gpio_data = { diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 67b95b5..9f38f5f 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -328,7 +328,6 @@ static void __init omap_3430sdp_init_irq(void) omap3_pm_init_cpuidle(omap3_cpuidle_params_table); omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); omap_init_irq(); - omap_gpio_init(); } static int sdp3430_batt_table[] = { diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index b359c3f..78973f5 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -76,7 +76,6 @@ static void __init omap_sdp_init_irq(void) omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 9447644..b7f6369 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -181,7 +181,6 @@ static void __init omap_4430sdp_init_irq(void) omap2_gp_clockevent_set_gptimer(1); #endif gic_init_irq(); - omap_gpio_init(); } static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 4d0f585..dd7aa66 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -372,7 +372,6 @@ static void __init am3517_evm_init_irq(void) omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index c6421a7..cd70971 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -280,7 +280,6 @@ static void __init omap_apollon_init_irq(void) omap_board_config_size = ARRAY_SIZE(apollon_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); apollon_init_smc91x(); } diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index e10bc10..000c7d4 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -687,7 +687,6 @@ static void __init cm_t35_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct omap_board_mux board_mux[] __initdata = { diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index a07086d..82b73e5 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -452,7 +452,6 @@ static void __init devkit8000_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static void __init devkit8000_ads7846_init(void) diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index e09bd68..4eb7c24 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -293,7 +293,6 @@ static void __init omap_h4_init_irq(void) omap_board_config_size = ARRAY_SIZE(h4_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); h4_init_flash(); } diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 175f043..63a68ef 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -406,7 +406,6 @@ static void __init igep2_init_irq(void) omap_board_config_size = ARRAY_SIZE(igep2_config); omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct twl4030_codec_audio_data igep2_audio_data = { diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 00d9b13..097c8b9 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -292,7 +292,6 @@ static void __init omap_ldp_init_irq(void) omap_board_config_size = ARRAY_SIZE(ldp_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); ldp_init_smsc911x(); } diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index a3e2b49..afa0ce5 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -648,7 +648,6 @@ static void __init n8x0_init_irq(void) { omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 87969c7..fda730b 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -393,7 +393,6 @@ static void __init omap3_beagle_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_beagle_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 6494dbd..cbb7614 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -627,7 +627,6 @@ static void __init omap3_evm_init_irq(void) omap_board_config_size = ARRAY_SIZE(omap3_evm_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); omap_init_irq(); - omap_gpio_init(); } static struct platform_device *omap3_evm_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 55836fa..ad9cd5f 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -588,7 +588,6 @@ static void __init omap3pandora_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static void pandora_wl1251_set_power(bool enable) diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index bcd01d2..1fbce09 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -588,7 +588,6 @@ static void __init omap3_stalker_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_stalker_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 663c62d..6118042 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -427,7 +427,6 @@ static void __init omap3_touchbook_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_touchbook_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index c03d1d5..09b0da1 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -44,7 +44,6 @@ static void __init omap4_panda_init_irq(void) { omap2_init_common_hw(NULL, NULL); gic_init_irq(); - omap_gpio_init(); } static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 4c48436..099f4f7 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -415,7 +415,6 @@ static void __init overo_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct platform_device *overo_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index a58e8cb..04b0259 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -108,7 +108,6 @@ static void __init rx51_init_irq(void) sdrc_params = rx51_get_sdram_timings(); omap2_init_common_hw(sdrc_params, sdrc_params); omap_init_irq(); - omap_gpio_init(); } extern void __init rx51_peripherals_init(void); diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 3ad9ecf..634b05b 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -31,7 +31,6 @@ static void __init omap_zoom2_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } /* REVISIT: These audio entries can be removed once MFD code is merged */ diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 6ca0b83..a048981 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -76,7 +76,6 @@ static void __init omap_zoom_init_irq(void) omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX From patchwork Fri Aug 6 12:34:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 117792 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CW6W5016517 for ; Fri, 6 Aug 2010 12:32:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934642Ab0HFMb7 (ORCPT ); Fri, 6 Aug 2010 08:31:59 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:52300 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934244Ab0HFMbr (ORCPT ); Fri, 6 Aug 2010 08:31:47 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76CVehQ004162 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 07:31:42 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76CVajX022391; Fri, 6 Aug 2010 18:01:37 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, b-cousson@ti.com, rnayak@ti.com, Charulatha V , "Basak, Partha" Subject: [PATCH 04/13 v5] OMAP: GPIO: Introduce support for OMAP7xx chip GPIO init Date: Fri, 6 Aug 2010 18:04:16 +0530 Message-Id: <1281098065-24177-5-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281098065-24177-4-git-send-email-charu@ti.com> References: <1281098065-24177-1-git-send-email-charu@ti.com> <1281098065-24177-2-git-send-email-charu@ti.com> <1281098065-24177-3-git-send-email-charu@ti.com> <1281098065-24177-4-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:32:09 +0000 (UTC) diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c new file mode 100644 index 0000000..c8cebc4 --- /dev/null +++ b/arch/arm/mach-omap1/gpio7xx.c @@ -0,0 +1,274 @@ +/* + * OMAP7XX-specific gpio code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Author: + * Charulatha V + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#define OMAP7XX_GPIO1_BASE 0xfffbc000 +#define OMAP7XX_GPIO2_BASE 0xfffbc800 +#define OMAP7XX_GPIO3_BASE 0xfffbd000 +#define OMAP7XX_GPIO4_BASE 0xfffbd800 +#define OMAP7XX_GPIO5_BASE 0xfffbe000 +#define OMAP7XX_GPIO6_BASE 0xfffbe800 +#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE + +static struct omap_gpio_dev_attr omap7xx_gpio_attr = { + .bank_width = 32, +}; + +/* + * OMAP7XX MPU GPIO interface data + */ +static struct __initdata resource omap7xx_mpu_gpio_resources[] = { + { + .start = OMAP1_MPUIO_VBASE, + .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_7XX_MPUIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { + .virtual_irq_start = IH_MPUIO_BASE, + .bank_type = METHOD_MPUIO, + .gpio_attr = &omap7xx_gpio_attr, +}; + +static struct __initdata platform_device omap7xx_mpu_gpio = { + .name = "omap-gpio", + .id = 0, + .dev = { + .platform_data = &omap7xx_mpu_gpio_config, + }, + .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources), + .resource = omap7xx_mpu_gpio_resources, +}; + +/* + * OMAP7XX GPIO1 interface data + */ +static struct __initdata resource omap7xx_gpio1_resources[] = { + { + .start = OMAP7XX_GPIO1_BASE, + .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_7XX_GPIO_BANK1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { + .virtual_irq_start = IH_GPIO_BASE, + .bank_type = METHOD_GPIO_7XX, + .gpio_attr = &omap7xx_gpio_attr, +}; + +static struct __initdata platform_device omap7xx_gpio1 = { + .name = "omap-gpio", + .id = 1, + .dev = { + .platform_data = &omap7xx_gpio1_config, + }, + .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources), + .resource = omap7xx_gpio1_resources, +}; + +/* + * OMAP7XX GPIO2 interface data + */ +static struct __initdata resource omap7xx_gpio2_resources[] = { + { + .start = OMAP7XX_GPIO2_BASE, + .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_7XX_GPIO_BANK2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { + .virtual_irq_start = IH_GPIO_BASE + 32, + .bank_type = METHOD_GPIO_7XX, + .gpio_attr = &omap7xx_gpio_attr, +}; + +static struct __initdata platform_device omap7xx_gpio2 = { + .name = "omap-gpio", + .id = 2, + .dev = { + .platform_data = &omap7xx_gpio2_config, + }, + .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources), + .resource = omap7xx_gpio2_resources, +}; + +/* + * OMAP7XX GPIO3 interface data + */ +static struct __initdata resource omap7xx_gpio3_resources[] = { + { + .start = OMAP7XX_GPIO3_BASE, + .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_7XX_GPIO_BANK3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { + .virtual_irq_start = IH_GPIO_BASE + 64, + .bank_type = METHOD_GPIO_7XX, + .gpio_attr = &omap7xx_gpio_attr, +}; + +static struct __initdata platform_device omap7xx_gpio3 = { + .name = "omap-gpio", + .id = 3, + .dev = { + .platform_data = &omap7xx_gpio3_config, + }, + .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources), + .resource = omap7xx_gpio3_resources, +}; + +/* + * OMAP7XX GPIO4 interface data + */ +static struct __initdata resource omap7xx_gpio4_resources[] = { + { + .start = OMAP7XX_GPIO4_BASE, + .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_7XX_GPIO_BANK4, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { + .virtual_irq_start = IH_GPIO_BASE + 96, + .bank_type = METHOD_GPIO_7XX, + .gpio_attr = &omap7xx_gpio_attr, +}; + +static struct __initdata platform_device omap7xx_gpio4 = { + .name = "omap-gpio", + .id = 4, + .dev = { + .platform_data = &omap7xx_gpio4_config, + }, + .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources), + .resource = omap7xx_gpio4_resources, +}; + +/* + * OMAP7XX GPIO5 interface data + */ +static struct __initdata resource omap7xx_gpio5_resources[] = { + { + .start = OMAP7XX_GPIO5_BASE, + .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_7XX_GPIO_BANK5, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { + .virtual_irq_start = IH_GPIO_BASE + 128, + .bank_type = METHOD_GPIO_7XX, + .gpio_attr = &omap7xx_gpio_attr, +}; + +static struct __initdata platform_device omap7xx_gpio5 = { + .name = "omap-gpio", + .id = 5, + .dev = { + .platform_data = &omap7xx_gpio5_config, + }, + .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources), + .resource = omap7xx_gpio5_resources, +}; + +/* + * OMAP7XX GPIO6 interface data + */ +static struct __initdata resource omap7xx_gpio6_resources[] = { + { + .start = OMAP7XX_GPIO6_BASE, + .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_7XX_GPIO_BANK6, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { + .virtual_irq_start = IH_GPIO_BASE + 160, + .bank_type = METHOD_GPIO_7XX, + .gpio_attr = &omap7xx_gpio_attr, +}; + +static struct __initdata platform_device omap7xx_gpio6 = { + .name = "omap-gpio", + .id = 6, + .dev = { + .platform_data = &omap7xx_gpio6_config, + }, + .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources), + .resource = omap7xx_gpio6_resources, +}; + +static struct __initdata platform_device * omap7xx_gpio_dev[] = { + &omap7xx_mpu_gpio, + &omap7xx_gpio1, + &omap7xx_gpio2, + &omap7xx_gpio3, + &omap7xx_gpio4, + &omap7xx_gpio5, + &omap7xx_gpio6, +}; + +/* + * omap7xx_gpio_init needs to be done before + * machine_init functions access gpio APIs. + * Hence omap7xx_gpio_init is a postcore_initcall. + */ +static int __init omap7xx_gpio_init(void) +{ + int i; + + if (!cpu_is_omap7xx()) + return -EINVAL; + + for (i = 0; i < sizeof(omap7xx_gpio_dev); i++) + platform_device_register(omap7xx_gpio_dev[i]); + + gpio_bank_count = sizeof(omap7xx_gpio_dev); + + return 0; +} +postcore_initcall(omap7xx_gpio_init); From patchwork Fri Aug 6 12:34:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 117793 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76CW6W6016517 for ; Fri, 6 Aug 2010 12:32:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934244Ab0HFMcA (ORCPT ); Fri, 6 Aug 2010 08:32:00 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:52299 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934411Ab0HFMbp (ORCPT ); Fri, 6 Aug 2010 08:31:45 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76CVeXL004164 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 07:31:42 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76CVajY022391; Fri, 6 Aug 2010 18:01:38 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, b-cousson@ti.com, rnayak@ti.com, Charulatha V , "Basak, Partha" Subject: [PATCH 05/13 v5] OMAP: GPIO: add GPIO hwmods structures for OMAP3 Date: Fri, 6 Aug 2010 18:04:17 +0530 Message-Id: <1281098065-24177-6-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281098065-24177-5-git-send-email-charu@ti.com> References: <1281098065-24177-1-git-send-email-charu@ti.com> <1281098065-24177-2-git-send-email-charu@ti.com> <1281098065-24177-3-git-send-email-charu@ti.com> <1281098065-24177-4-git-send-email-charu@ti.com> <1281098065-24177-5-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 12:32:10 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 5d8eb58..90fb907 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -36,6 +37,12 @@ static struct omap_hwmod omap3xxx_iva_hwmod; static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; +static struct omap_hwmod omap3xxx_gpio1_hwmod; +static struct omap_hwmod omap3xxx_gpio2_hwmod; +static struct omap_hwmod omap3xxx_gpio3_hwmod; +static struct omap_hwmod omap3xxx_gpio4_hwmod; +static struct omap_hwmod omap3xxx_gpio5_hwmod; +static struct omap_hwmod omap3xxx_gpio6_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -197,6 +204,375 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* L4 WKUP -> GPIO1 interface */ + +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = 0x48310000, + .pa_end = 0x483101ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .clk = "gpio1_ick", + .addr = omap3xxx_gpio1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO2 interface */ + +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = 0x49050000, + .pa_end = 0x490501ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .clk = "gpio2_ick", + .addr = omap3xxx_gpio2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO3 interface */ + +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = 0x49052000, + .pa_end = 0x490521ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .clk = "gpio3_ick", + .addr = omap3xxx_gpio3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO4 interface */ + +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = 0x49054000, + .pa_end = 0x490541ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .clk = "gpio4_ick", + .addr = omap3xxx_gpio4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO5 interface */ + +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = 0x49056000, + .pa_end = 0x490561ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap3xxx_gpio5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO6 interface */ + +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = 0x49058000, + .pa_end = 0x490581ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .clk = "gpio6_ick", + .addr = omap3xxx_gpio6_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* GPIO common*/ + +static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap3xxx_gpio_sysc, + .rev = 1, +}; + +/* GPIO dev_attr common for gpio2-6*/ + +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, + .off_mode_support = true, +}; + +/* GPIO1 */ + +static struct omap_gpio_dev_attr gpio1_dev_attr = { + .bank_width = 32, + .dbck_flag = true, + .off_mode_support = false, +}; + +static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK1 }, +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { + &omap3xxx_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap3xxx_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap3xxx_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), + .main_clk = NULL, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPIO1_SHIFT, + }, + }, + .slaves = omap3xxx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO2 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK2 }, +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { + &omap3xxx_l4_per__gpio2, +}; + +static struct omap_hwmod omap3xxx_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap3xxx_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), + .main_clk = NULL, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPIO2_SHIFT, + }, + }, + .slaves = omap3xxx_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO3 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK3 }, +}; + +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { + &omap3xxx_l4_per__gpio3, +}; + +static struct omap_hwmod omap3xxx_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap3xxx_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), + .main_clk = NULL, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPIO3_SHIFT, + }, + }, + .slaves = omap3xxx_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO4 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK4 }, +}; + +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { + &omap3xxx_l4_per__gpio4, +}; + +static struct omap_hwmod omap3xxx_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap3xxx_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), + .main_clk = NULL, + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPIO4_SHIFT, + }, + }, + .slaves = omap3xxx_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + + +/* GPIO5 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK5 }, +}; + +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { + &omap3xxx_l4_per__gpio5, +}; + +static struct omap_hwmod omap3xxx_gpio5_hwmod = { + .name = "gpio5", + .mpu_irqs = omap3xxx_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), + .main_clk = NULL, + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO5_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPIO5_SHIFT, + }, + }, + .slaves = omap3xxx_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO6 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK6 }, +}; + +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { + &omap3xxx_l4_per__gpio6, +}; + +static struct omap_hwmod omap3xxx_gpio6_hwmod = { + .name = "gpio6", + .mpu_irqs = omap3xxx_gpio6_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), + .main_clk = NULL, + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPIO6_SHIFT, + }, + }, + .slaves = omap3xxx_gpio6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +580,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_gpio1_hwmod, + &omap3xxx_gpio2_hwmod, + &omap3xxx_gpio3_hwmod, + &omap3xxx_gpio4_hwmod, + &omap3xxx_gpio5_hwmod, + &omap3xxx_gpio6_hwmod, NULL, }; From patchwork Thu Apr 1 10:32:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripathy, Vishwanath" X-Patchwork-Id: 90065 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o314t5ni025612 for ; Thu, 1 Apr 2010 04:56:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752689Ab0DAEzB (ORCPT ); Thu, 1 Apr 2010 00:55:01 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:40189 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752648Ab0DAEy7 (ORCPT ); Thu, 1 Apr 2010 00:54:59 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o314stjW005409 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 31 Mar 2010 23:54:58 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o314srCA018187; Thu, 1 Apr 2010 10:24:55 +0530 (IST) From: Vishwanath BS To: linux-omap@vger.kernel.org Cc: Vishwanath BS Subject: [PATCHV3 2/2] Set MPU and IVA bypass clock dividers in DVFS Date: Thu, 1 Apr 2010 18:32:19 +0800 Message-Id: <1270117939-10730-3-git-send-email-vishwanath.bs@ti.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1270117939-10730-2-git-send-email-vishwanath.bs@ti.com> References: <> <1270117939-10730-1-git-send-email-vishwanath.bs@ti.com> <1270117939-10730-2-git-send-email-vishwanath.bs@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Apr 2010 04:56:05 +0000 (UTC) diff --git a/arch/arm/mach-omap2/resource34xx.c b/arch/arm/mach-omap2/resource34xx.c index c6cce8b..068021c --- a/arch/arm/mach-omap2/resource34xx.c +++ b/arch/arm/mach-omap2/resource34xx.c @@ -154,6 +154,7 @@ static struct device vdd2_dev; static int vdd1_lock; static int vdd2_lock; static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk; +static struct clk *dpll1_fck, *dpll2_fck; static int curr_vdd1_opp; static int curr_vdd2_opp; static DEFINE_MUTEX(dvfs_mutex); @@ -228,6 +229,8 @@ void init_opp(struct shared_resource *resp) ret = freq_to_opp(&opp_id, OPP_MPU, dpll1_clk->rate); BUG_ON(ret); /* TBD Cleanup handling */ curr_vdd1_opp = opp_id; + dpll1_fck = clk_get(NULL, "dpll1_fck"); + dpll2_fck = clk_get(NULL, "dpll2_fck"); } else if (strcmp(resp->name, "vdd2_opp") == 0) { vdd2_resp = resp; dpll3_clk = clk_get(NULL, "dpll3_m2_ck"); @@ -276,9 +279,9 @@ static unsigned long compute_lpj(unsigned long ref, u_int div, u_int mult) static int program_opp_freq(int res, int target_level, int current_level) { - int ret = 0, l3_div; + int ret = 0, l3_div, mpu_div, iva2_div; int *curr_opp; - unsigned long mpu_freq, dsp_freq, l3_freq; + unsigned long mpu_freq, dsp_freq, l3_freq, max_core_clk; #ifndef CONFIG_CPU_FREQ unsigned long mpu_cur_freq; #endif @@ -299,6 +302,17 @@ static int program_opp_freq(int res, int target_level, int current_level) lock_scratchpad_sem(); if (res == VDD1_OPP) { + /* adjust bypass clock diviers */ + max_core_clk = ULONG_MAX; + opp_find_freq_floor(OPP_L3, &max_core_clk); + l3_div = cm_read_mod_reg(CORE_MOD, CM_CLKSEL) & + OMAP3430_CLKSEL_L3_MASK; + max_core_clk *= l3_div; + mpu_div = 1 << (max_core_clk / mpu_freq); + iva2_div = 1 << (max_core_clk / dsp_freq); + clk_set_rate(dpll1_fck, max_core_clk/mpu_div); + clk_set_rate(dpll2_fck, max_core_clk/iva2_div); + curr_opp = &curr_vdd1_opp; clk_set_rate(dpll1_clk, mpu_freq); clk_set_rate(dpll2_clk, dsp_freq); From patchwork Mon May 24 14:20:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Ellis X-Patchwork-Id: 101889 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4OFnnFn013433 for ; Mon, 24 May 2010 15:49:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753537Ab0EXPtr (ORCPT ); Mon, 24 May 2010 11:49:47 -0400 Received: from pan.gwi.net ([207.5.128.165]:4286 "EHLO pan.gwi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752208Ab0EXPtq (ORCPT ); Mon, 24 May 2010 11:49:46 -0400 Received: from [192.168.10.4] (66-63-88-74.static.suscom-maine.net [66.63.88.74]) by pan.gwi.net (8.13.1/8.13.1) with ESMTP id o4OEKStr068728; Mon, 24 May 2010 10:20:28 -0400 (EDT) (envelope-from scott@jumpnowtek.com) Subject: Re: [PATCHv3 1/6] SPI omap2_mcspi.c: Check params before dereference or use From: Scott Ellis To: spi-devel-general@lists.sourceforge.net Cc: Grant Likely , David Brownell , Andrew Morton , Tony Lindgren , Kevin Hilman , Aaro Koskinen , Roman Tereshonkov , linux-omap@vger.kernel.org In-Reply-To: References: <1268406713.14445.50.camel@quad> Date: Mon, 24 May 2010 10:20:27 -0400 Message-ID: <1274710827.2888.9.camel@quad> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 24 May 2010 15:49:50 +0000 (UTC) diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index e0de0d0..0b35468 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -755,7 +755,6 @@ static void omap2_mcspi_cleanup(struct spi_device *spi) struct omap2_mcspi_cs *cs; mcspi = spi_master_get_devdata(spi->master); - mcspi_dma = &mcspi->dma_channels[spi->chip_select]; if (spi->controller_state) { From patchwork Wed Jul 21 17:33:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113414 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONX007938 for ; Wed, 21 Jul 2010 17:35:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758581Ab0GURfE (ORCPT ); Wed, 21 Jul 2010 13:35:04 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758499Ab0GURe7 (ORCPT ); Wed, 21 Jul 2010 13:34:59 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:58 -0700 (PDT) Received: by 10.204.163.77 with SMTP id z13mr334913bkx.169.1279733697969; Wed, 21 Jul 2010 10:34:57 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.54 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:57 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 10/20] omap: zoom: add fixed regulator device for wlan Date: Wed, 21 Jul 2010 20:33:44 +0300 Message-Id: <1279733634-21974-11-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:14 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b39849..2fc0f4a 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,8 @@ #include "mux.h" #include "hsmmc.h" +#define OMAP_ZOOM_WLAN_PMENA_GPIO (101) + /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { KEY(0, 0, KEY_E), @@ -106,6 +109,10 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = { .supply = "vmmc", }; +static struct regulator_consumer_supply zoom_vmmc3_supply = { + .supply = "vmmc", +}; + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data zoom_vmmc1 = { .constraints = { @@ -151,6 +158,32 @@ static struct regulator_init_data zoom_vsim = { .consumer_supplies = &zoom_vsim_supply, }; +static struct regulator_init_data zoom_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom_vmmc3_supply, +}; + +static struct fixed_voltage_config zoom_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.8V */ + .gpio = OMAP_ZOOM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70msec */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &zoom_vmmc3, +}; + +static struct platform_device omap_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &zoom_vwlan, + }, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -280,6 +313,7 @@ static void enable_board_wakeup_source(void) void __init zoom_peripherals_init(void) { omap_i2c_init(); + platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); enable_board_wakeup_source(); } From patchwork Wed May 5 14:27:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97114 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESTjf002812 for ; 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Wed, 5 May 2010 17:28:11 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 20/21] OMAP: DSS2: Taal: Add regulator configuration support Date: Wed, 5 May 2010 17:27:40 +0300 Message-Id: <1b93af2daf403f2fe822469b71c12ea7eb1cc68a.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <5e7384699d72bad3865dc9604b18ad05775bfb27.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> <690ef5c45aee3fb87a40fa03039356f8238925dc.1273067195.git.ext-jani.1.nikula@nokia.com> <025c12267d4bd88e1f59d9e13aafec247fe3c730.1273067195.git.ext-jani.1.nikula@nokia.com> <5e7384699d72bad3865dc9604b18ad05775bfb27.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:12.0240 (UTC) FILETIME=[310C0500:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:33 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index b73cd12..617723b 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -68,6 +69,73 @@ static irqreturn_t taal_te_isr(int irq, void *data); static void taal_te_timeout_work_callback(struct work_struct *work); static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable); +struct panel_regulator { + struct regulator *regulator; + const char *name; + int min_uV; + int max_uV; +}; + +static void free_regulators(struct panel_regulator *regulators, int n) +{ + int i; + + for (i = 0; i < n; i++) { + /* disable/put in reverse order */ + regulator_disable(regulators[n - i - 1].regulator); + regulator_put(regulators[n - i - 1].regulator); + } +} + +static int init_regulators(struct omap_dss_device *dssdev, + struct panel_regulator *regulators, int n) +{ + int r, i, v; + + for (i = 0; i < n; i++) { + struct regulator *reg; + + reg = regulator_get(&dssdev->dev, regulators[i].name); + if (IS_ERR(reg)) { + dev_err(&dssdev->dev, "failed to get regulator %s\n", + regulators[i].name); + r = PTR_ERR(reg); + goto err; + } + + /* FIXME: better handling of fixed vs. variable regulators */ + v = regulator_get_voltage(reg); + if (v < regulators[i].min_uV || v > regulators[i].max_uV) { + r = regulator_set_voltage(reg, regulators[i].min_uV, + regulators[i].max_uV); + if (r) { + dev_err(&dssdev->dev, + "failed to set regulator %s voltage\n", + regulators[i].name); + regulator_put(reg); + goto err; + } + } + + r = regulator_enable(reg); + if (r) { + dev_err(&dssdev->dev, "failed to enable regulator %s\n", + regulators[i].name); + regulator_put(reg); + goto err; + } + + regulators[i].regulator = reg; + } + + return 0; + +err: + free_regulators(regulators, i); + + return r; +} + /** * struct panel_config - panel configuration * @name: panel name @@ -75,6 +143,8 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable); * @timings: panel resolution * @sleep: various panel specific delays, passed to msleep() if non-zero * @reset_sequence: reset sequence timings, passed to udelay() if non-zero + * @regulators: array of panel regulators + * @num_regulators: number of regulators in the array */ struct panel_config { const char *name; @@ -93,6 +163,9 @@ struct panel_config { unsigned int high; unsigned int low; } reset_sequence; + + struct panel_regulator *regulators; + int num_regulators; }; enum { @@ -629,6 +702,11 @@ static int taal_probe(struct omap_dss_device *dssdev) atomic_set(&td->do_update, 0); + r = init_regulators(dssdev, panel_config->regulators, + panel_config->num_regulators); + if (r) + goto err_reg; + td->esd_wq = create_singlethread_workqueue("taal_esd"); if (td->esd_wq == NULL) { dev_err(&dssdev->dev, "can't create ESD workqueue\n"); @@ -714,6 +792,8 @@ err_gpio: err_bl: destroy_workqueue(td->esd_wq); err_wq: + free_regulators(panel_config->regulators, panel_config->num_regulators); +err_reg: kfree(td); err: return r; @@ -746,6 +826,9 @@ static void taal_remove(struct omap_dss_device *dssdev) /* reset, to be sure that the panel is in a valid state */ taal_hw_reset(dssdev); + free_regulators(td->panel_config->regulators, + td->panel_config->num_regulators); + kfree(td); } From patchwork Wed Jun 23 13:01:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 107627 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5ND3Wx5003514 for ; Wed, 23 Jun 2010 13:03:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752502Ab0FWNC6 (ORCPT ); Wed, 23 Jun 2010 09:02:58 -0400 Received: from mail-ww0-f46.google.com ([74.125.82.46]:58323 "EHLO mail-ww0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751494Ab0FWNCz (ORCPT ); Wed, 23 Jun 2010 09:02:55 -0400 Received: by mail-ww0-f46.google.com with SMTP id 33so980721wwc.19 for ; Wed, 23 Jun 2010 06:02:54 -0700 (PDT) Received: by 10.227.143.212 with SMTP id w20mr7390796wbu.107.1277298174417; Wed, 23 Jun 2010 06:02:54 -0700 (PDT) Received: from localhost.localdomain (89-139-43-41.bb.netvision.net.il [89.139.43.41]) by mx.google.com with ESMTPS id n31sm60551089wba.15.2010.06.23.06.02.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 23 Jun 2010 06:02:53 -0700 (PDT) From: Ohad Ben-Cohen To: Greg KH Cc: , , Hebbar Shivananda , Ramos Falcon Ernesto , Anna Suman , Kanigeri Hari , Felipe Contreras , Felipe Balbi , Hiroshi DOYU , Gupta Ramesh , Guzman Lugo Fernando , Tony Lindgren , Ameya Palande , Gomez Castellanos Ivan , Andy Shevchenko , Armando Uribe De Leon , Deepak Chitriki , Menon Nishanth , Phil Carmody , Pitney Gilbert , Bhavin Shah , Omar Ramirez Luna , Ohad Ben-Cohen Subject: [PATCH 01/11] staging: ti dspbridge: add driver documentation Date: Wed, 23 Jun 2010 16:01:55 +0300 Message-Id: <1277298125-17991-2-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1277298125-17991-1-git-send-email-ohad@wizery.com> References: <1277298125-17991-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 23 Jun 2010 13:03:33 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/Documentation/CONTRIBUTORS b/drivers/staging/tidspbridge/Documentation/CONTRIBUTORS new file mode 100644 index 0000000..b40e7a6 --- /dev/null +++ b/drivers/staging/tidspbridge/Documentation/CONTRIBUTORS @@ -0,0 +1,82 @@ +TI DSP/Bridge Driver - Contributors File + +The DSP/Bridge project wish to thank all of its contributors, current bridge +driver is the result of the work of all of them. If any name is accidentally +omitted, let us know by sending a mail to omar.ramirez@ti.com or +x095840@ti.com. + +Please keep the following list in alphabetical order. + + Suman Anna + Sripal Bagadia + Felipe Balbi + Ohad Ben-Cohen + Phil Carmody + Deepak Chitriki + Felipe Contreras + Hiroshi Doyu + Seth Forshee + Ivan Gomez Castellanos + Mark Grosen + Ramesh Gupta G + Fernando Guzman Lugo + Axel Haslam + Janet Head + Shivananda Hebbar + Hari Kanigeri + Tony Lindgren + Antonio Luna + Hari Nagalla + Nishanth Menon + Ameya Palande + Vijay Pasam + Gilbert Pitney + Omar Ramirez Luna + Ernesto Ramos + Chris Ring + Larry Schiefer + Rebecca Schultz Zavin + Bhavin Shah + Andy Shevchenko + Jeff Taylor + Roman Tereshonkov + Armando Uribe de Leon + Nischal Varide + Wenbiao Wang + + + +The following list was taken from file Revision History, if you recognize your +alias or did any contribution to the project please let us now, so we can +proper credit your work. + + ag + ap + cc + db + dh4 + dr + hp + jg + kc + kln + kw + ge + gv + map + mf + mk + mr + nn + rajesh + rg + rr + rt + sb + sg + sh + sp + srid + swa + vp + ww diff --git a/drivers/staging/tidspbridge/Documentation/README b/drivers/staging/tidspbridge/Documentation/README new file mode 100644 index 0000000..df6d371 --- /dev/null +++ b/drivers/staging/tidspbridge/Documentation/README @@ -0,0 +1,70 @@ + Linux DSP/BIOS Bridge release + +DSP/BIOS Bridge overview +======================== + +DSP/BIOS Bridge is designed for platforms that contain a GPP and one or more +attached DSPs. The GPP is considered the master or "host" processor, and the +attached DSPs are processing resources that can be utilized by applications +and drivers running on the GPP. + +The abstraction that DSP/BIOS Bridge supplies, is a direct link between a GPP +program and a DSP task. This communication link is partitioned into two +types of sub-links: messaging (short, fixed-length packets) and data +streaming (multiple, large buffers). Each sub-link operates independently, +and features in-order delivery of data, meaning that messages are delivered +in the order they were submitted to the message link, and stream buffers are +delivered in the order they were submitted to the stream link. + +In addition, a GPP client can specify what inputs and outputs a DSP task +uses. DSP tasks typically use message objects for passing control and status +information and stream objects for efficient streaming of real-time data. + +GPP Software Architecture +========================= + +A GPP application communicates with its associated DSP task running on the +DSP subsystem using the DSP/BIOS Bridge API. For example, a GPP audio +application can use the API to pass messages to a DSP task that is managing +data flowing from analog-to-digital converters (ADCs) to digital-to-analog +converters (DACs). + +From the perspective of the GPP OS, the DSP is treated as just another +peripheral device. Most high level GPP OS typically support a device driver +model, whereby applications can safely access and share a hardware peripheral +through standard driver interfaces. Therefore, to allow multiple GPP +applications to share access to the DSP, the GPP side of DSP/BIOS Bridge +implements a device driver for the DSP. + +Since driver interfaces are not always standard across GPP OS, and to provide +some level of interoperability of application code using DSP/BIOS Bridge +between GPP OS, DSP/BIOS Bridge provides a standard library of APIs which +wrap calls into the device driver. So, rather than calling GPP OS specific +driver interfaces, applications (and even other device drivers) can use the +standard API library directly. + +DSP Software Architecture +========================= + +For DSP/BIOS, DSP/BIOS Bridge adds a device-independent streaming I/O (STRM) +interface, a messaging interface (NODE), and a Resource Manager (RM) Server. +The RM Server runs as a task of DSP/BIOS and is subservient to commands +and queries from the GPP. It executes commands to start and stop DSP signal +processing nodes in response to GPP programs making requests through the +(GPP-side) API. + +DSP tasks started by the RM Server are similar to any other DSP task with two +important differences: they must follow a specific task model consisting of +three C-callable functions (node create, execute, and delete), with specific +sets of arguments, and they have a pre-defined task environment established +by the RM Server. + +Tasks started by the RM Server communicate using the STRM and NODE interfaces +and act as servers for their corresponding GPP clients, performing signal +processing functions as requested by messages sent by their GPP client. +Typically, a DSP task moves data from source devices to sink devices using +device independent I/O streams, performing application-specific processing +and transformations on the data while it is moved. For example, an audio +task might perform audio decompression (ADPCM, MPEG, CELP) on data received +from a GPP audio driver and then send the decompressed linear samples to a +digital-to-analog converter. diff --git a/drivers/staging/tidspbridge/Documentation/error-codes b/drivers/staging/tidspbridge/Documentation/error-codes new file mode 100644 index 0000000..12826e2 --- /dev/null +++ b/drivers/staging/tidspbridge/Documentation/error-codes @@ -0,0 +1,157 @@ + DSP/Bridge Error Code Guide + + +Success code is always taken as 0, except for one case where a success status +different than 0 can be possible, this is when enumerating a series of dsp +objects, if the enumeration doesn't have any more objects it is considered as a +successful case. In this case a positive ENODATA is returned (TODO: Change to +avoid this case). + +Error codes are returned as a negative 1, if an specific code is expected, it +can be propagated to user space by reading errno symbol defined in errno.h, for +specific details on the implementation a copy of the standard used should be +read first. + +The error codes used by this driver are: + +[EPERM] + General driver failure. + + According to the use case the following might apply: + - Device is in 'sleep/suspend' mode due to DPM. + - User cannot mark end of stream on an input channel. + - Requested operation is invalid for the node type. + - Invalid alignment for the node messaging buffer. + - The specified direction is invalid for the stream. + - Invalid stream mode. + +[ENOENT] + The specified object or file was not found. + +[ESRCH] + A shared memory buffer contained in a message or stream could not be mapped + to the GPP client process's virtual space. + +[EIO] + Driver interface I/O error. + + or: + - Unable to plug channel ISR for configured IRQ. + - No free I/O request packets are available. + +[ENXIO] + Unable to find a named section in DSP executable or a non-existent memory + segment identifier was specified. + +[EBADF] + General error for file handling: + + - Unable to open file. + - Unable to read file. + - An error occurred while parsing the DSP executable file. + +[ENOMEM] + A memory allocation failure occurred. + +[EACCES] + - Unable to read content of DCD data section; this is typically caused by + improperly configured nodes. + - Unable to decode DCD data section content; this is typically caused by + changes to DSP/BIOS Bridge data structures. + - Unable to get pointer to DCD data section; this is typically caused by + improperly configured UUIDs. + - Unable to load file containing DCD data section; this is typically + caused by a missing COFF file. + - The specified COFF file does not contain a valid node registration + section. + +[EFAULT] + Invalid pointer or handler. + +[EEXIST] + Attempted to create a channel manager when one already exists. + +[EINVAL] + Invalid argument. + +[ESPIPE] + Symbol not found in the COFF file. DSPNode_Create will return this if + the iAlg function table for an xDAIS socket is not found in the COFF file. + In this case, force the symbol to be linked into the COFF file. + DSPNode_Create, DSPNode_Execute, and DSPNode_Delete will return this if + the create, execute, or delete phase function, respectively, could not be + found in the COFF file. + + - No symbol table is loaded/found for this board. + - Unable to initialize the ZL COFF parsing module. + +[EPIPE] + I/O is currently pending. + + - End of stream was already requested on this output channel. + +[EDOM] + A parameter is specified outside its valid range. + +[ENOSYS] + The indicated operation is not supported. + +[EIDRM] + During enumeration a change in the number or properties of the objects + has occurred. + +[ECHRNG] + Attempt to created channel manager with too many channels or channel ID out + of range. + +[EBADR] + The state of the specified object is incorrect for the requested operation. + + - Invalid segment ID. + +[ENODATA] + Unable to retrieve resource information from the registry. + + - No more registry values. + +[ETIME] + A timeout occurred before the requested operation could complete. + +[ENOSR] + A stream has been issued the maximum number of buffers allowed in the + stream at once; buffers must be reclaimed from the stream before any more + can be issued. + + - No free channels are available. + +[EILSEQ] + Error occurred in a dynamic loader library function. + +[EISCONN] + The Specified Connection already exists. + +[ENOTCONN] + Nodes not connected. + +[ETIMEDOUT] + Timeout occurred waiting for a response from the hardware. + + - Wait for flush operation on an output channel timed out. + +[ECONNREFUSED] + No more connections can be made for this node. + +[EALREADY] + Channel is already in use. + +[EREMOTEIO] + dwTimeOut parameter was CHNL_IOCNOWAIT, yet no I/O completions were + queued. + +[ECANCELED] + I/O has been cancelled on this channel. + +[ENOKEY] + Invalid subkey parameter. + + - UUID not found in registry. From patchwork Thu May 6 11:59:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97338 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o46BxQAw013750 for ; Thu, 6 May 2010 11:59:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757558Ab0EFL7c (ORCPT ); Thu, 6 May 2010 07:59:32 -0400 Received: from smtp.nokia.com ([192.100.122.230]:47186 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752139Ab0EFL7b (ORCPT ); Thu, 6 May 2010 07:59:31 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o46BxE62023463; Thu, 6 May 2010 14:59:14 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 6 May 2010 14:59:06 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 6 May 2010 14:59:05 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o46Bx3sk015300; Thu, 6 May 2010 14:59:04 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, khilman@deeprootsystems.com Cc: linux-fbdev-devel@lists.sourceforge.net, linux-omap@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH 1/2] OMAP: DSS2: omap_dss_probe() conditional compilation cleanup Date: Thu, 6 May 2010 14:59:02 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: In-Reply-To: References: X-OriginalArrivalTime: 06 May 2010 11:59:05.0362 (UTC) FILETIME=[86B48720:01CAED13] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 06 May 2010 11:59:32 +0000 (UTC) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 7ebe50b..92ee067 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -482,6 +482,14 @@ static void dss_uninitialize_debugfs(void) if (dss_debugfs_dir) debugfs_remove_recursive(dss_debugfs_dir); } +#else /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ +static inline int dss_initialize_debugfs(void) +{ + return 0; +} +static inline void dss_uninitialize_debugfs(void) +{ +} #endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ /* PLATFORM DEVICE */ @@ -518,13 +526,11 @@ static int omap_dss_probe(struct platform_device *pdev) goto fail0; } -#ifdef CONFIG_OMAP2_DSS_RFBI r = rfbi_init(); if (r) { DSSERR("Failed to initialize rfbi\n"); goto fail0; } -#endif r = dpi_init(pdev); if (r) { @@ -537,35 +543,30 @@ static int omap_dss_probe(struct platform_device *pdev) DSSERR("Failed to initialize dispc\n"); goto fail0; } -#ifdef CONFIG_OMAP2_DSS_VENC + r = venc_init(pdev); if (r) { DSSERR("Failed to initialize venc\n"); goto fail0; } -#endif + if (cpu_is_omap34xx()) { -#ifdef CONFIG_OMAP2_DSS_SDI r = sdi_init(skip_init); if (r) { DSSERR("Failed to initialize SDI\n"); goto fail0; } -#endif -#ifdef CONFIG_OMAP2_DSS_DSI + r = dsi_init(pdev); if (r) { DSSERR("Failed to initialize DSI\n"); goto fail0; } -#endif } -#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) r = dss_initialize_debugfs(); if (r) goto fail0; -#endif for (i = 0; i < pdata->num_devices; ++i) { struct omap_dss_device *dssdev = pdata->devices[i]; @@ -593,25 +594,15 @@ static int omap_dss_remove(struct platform_device *pdev) int i; int c; -#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) dss_uninitialize_debugfs(); -#endif -#ifdef CONFIG_OMAP2_DSS_VENC venc_exit(); -#endif dispc_exit(); dpi_exit(); -#ifdef CONFIG_OMAP2_DSS_RFBI rfbi_exit(); -#endif if (cpu_is_omap34xx()) { -#ifdef CONFIG_OMAP2_DSS_DSI dsi_exit(); -#endif -#ifdef CONFIG_OMAP2_DSS_SDI sdi_exit(); -#endif } dss_exit(); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 24326a5..65f95ee 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -242,11 +242,22 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, struct dispc_clock_info *dispc_cinfo); /* SDI */ +#ifdef CONFIG_OMAP2_DSS_SDI int sdi_init(bool skip_init); void sdi_exit(void); int sdi_init_display(struct omap_dss_device *display); +#else +static inline int sdi_init(bool skip_init) +{ + return 0; +} +static inline void sdi_exit(void) +{ +} +#endif /* DSI */ +#ifdef CONFIG_OMAP2_DSS_DSI int dsi_init(struct platform_device *pdev); void dsi_exit(void); @@ -270,6 +281,15 @@ void dsi_pll_uninit(void); void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, u32 fifo_size, enum omap_burst_size *burst_size, u32 *fifo_low, u32 *fifo_high); +#else +static inline int dsi_init(struct platform_device *pdev) +{ + return 0; +} +static inline void dsi_exit(void) +{ +} +#endif /* DPI */ int dpi_init(struct platform_device *pdev); @@ -362,12 +382,23 @@ int dispc_get_clock_div(struct dispc_clock_info *cinfo); /* VENC */ +#ifdef CONFIG_OMAP2_DSS_VENC int venc_init(struct platform_device *pdev); void venc_exit(void); void venc_dump_regs(struct seq_file *s); int venc_init_display(struct omap_dss_device *display); +#else +static inline int venc_init(struct platform_device *pdev) +{ + return 0; +} +static inline void venc_exit(void) +{ +} +#endif /* RFBI */ +#ifdef CONFIG_OMAP2_DSS_RFBI int rfbi_init(void); void rfbi_exit(void); void rfbi_dump_regs(struct seq_file *s); @@ -379,6 +410,15 @@ void rfbi_transfer_area(u16 width, u16 height, void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t); unsigned long rfbi_get_max_tx_rate(void); int rfbi_init_display(struct omap_dss_device *display); +#else +static inline int rfbi_init(void) +{ + return 0; +} +static inline void rfbi_exit(void) +{ +} +#endif #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS From patchwork Wed Jul 7 15:47:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Que, Simon" X-Patchwork-Id: 110672 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o67FlqTh027876 for ; Wed, 7 Jul 2010 15:47:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757239Ab0GGPrv (ORCPT ); Wed, 7 Jul 2010 11:47:51 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:57116 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757065Ab0GGPrv (ORCPT ); Wed, 7 Jul 2010 11:47:51 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o67Flnje016321 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 7 Jul 2010 10:47:49 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o67FlnVe006489; Wed, 7 Jul 2010 10:47:49 -0500 (CDT) Received: from dlee75.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o67FlnOe023791; Wed, 7 Jul 2010 10:47:49 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dlee75.ent.ti.com ([157.170.170.72]) with mapi; Wed, 7 Jul 2010 10:47:48 -0500 From: "Que, Simon" To: Tony Lindgren , "linux-omap@vger.kernel.org" CC: "Kanigeri, Hari" , Ohad Ben-Cohen , "Shilimkar, Santosh" , "Cousson, Benoit" Date: Wed, 7 Jul 2010 10:47:46 -0500 Subject: [PATCH] omap: hwspinlock: Added hwspinlock driver Thread-Topic: [PATCH] omap: hwspinlock: Added hwspinlock driver Thread-Index: Acsd678IVv/M6Ik9RcmC7qopYTPHWg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 15:47:53 +0000 (UTC) ========================================================================== From 509bd1a2e7e5c1a6af3248742e0d53ca5f9fd066 Mon Sep 17 00:00:00 2001 From: Simon Que Date: Wed, 23 Jun 2010 18:40:30 -0500 Subject: [PATCH] omap: hwspinlock: Added hwspinlock driver Created driver for OMAP hardware spinlock. This driver supports: - Reserved spinlocks for internal use - Dynamic allocation of unreserved locks - Lock, unlock, and trylock functions, with or without disabling irqs/preempt - Registered as a platform device driver The device initialization uses hwmod to configure the devices. One device will be created for each IP. It will pass spinlock register offset info to the driver. The device initialization file is: arch/arm/mach-omap2/hwspinlocks.c The driver takes in register offset info passed in device initialization. It uses hwmod to obtain the base address of the hardware spinlock module. Then it reads info from the registers. The function hwspinlock_probe() initializes the array of spinlock structures, each containing a spinlock register address calculated from the base address and lock offsets. The device driver file is: arch/arm/plat-omap/hwspinlock.c Here's an API summary: int hwspinlock_lock(struct hwspinlock *); Attempt to lock a hardware spinlock. If it is busy, the function will keep trying until it succeeds. This is a blocking function. int hwspinlock_trylock(struct hwspinlock *); Attempt to lock a hardware spinlock. If it is busy, the function will return BUSY. If it succeeds in locking, the function will return ACQUIRED. This is a non-blocking function. int hwspinlock_unlock(struct hwspinlock *); Unlock a hardware spinlock. struct hwspinlock *hwspinlock_request(void); Provides for "dynamic allocation" of a hardware spinlock. It returns the handle to the next available (unallocated) spinlock. If no more locks are available, it returns NULL. struct hwspinlock *hwspinlock_request_specific(unsigned int); Provides for "static allocation" of a specific hardware spinlock. This allows the system to use a specific spinlock, identified by an ID. If the ID is invalid or if the desired lock is already allocated, this will return NULL. Otherwise it returns a spinlock handle. int hwspinlock_free(struct hwspinlock *); Frees an allocated hardware spinlock (either reserved or unreserved). Signed-off-by: Simon Que --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/hwspinlocks.c | 71 ++++++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +- arch/arm/plat-omap/Makefile | 3 +- arch/arm/plat-omap/hwspinlock.c | 335 ++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/hwspinlock.h | 29 +++ arch/arm/plat-omap/include/plat/omap44xx.h | 2 + 7 files changed, 442 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/hwspinlocks.c create mode 100644 arch/arm/plat-omap/hwspinlock.c create mode 100644 arch/arm/plat-omap/include/plat/hwspinlock.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 6725b3a..5f5c87b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -170,3 +170,5 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) + +obj-$(CONFIG_ARCH_OMAP4) += hwspinlocks.o \ No newline at end of file diff --git a/arch/arm/mach-omap2/hwspinlocks.c b/arch/arm/mach-omap2/hwspinlocks.c new file mode 100644 index 0000000..58a6483 --- /dev/null +++ b/arch/arm/mach-omap2/hwspinlocks.c @@ -0,0 +1,71 @@ +/* + * OMAP hardware spinlock device initialization + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Spinlock register offsets */ +#define REVISION_OFFSET 0x0000 +#define SYSCONFIG_OFFSET 0x0010 +#define SYSSTATUS_OFFSET 0x0014 +#define LOCK_BASE_OFFSET 0x0800 +#define LOCK_OFFSET(i) (LOCK_BASE_OFFSET + 0x4 * (i)) + +/* Initialization function */ +int __init hwspinlocks_init(void) +{ + int retval = 0; + + struct hwspinlock_plat_info *pdata; + struct omap_hwmod *oh; + char *oh_name, *pdev_name; + + oh_name = "spinlock"; + oh = omap_hwmod_lookup(oh_name); + if (WARN_ON(oh == NULL)) + return -EINVAL; + + pdev_name = "hwspinlock"; + + /* Pass data to device initialization */ + pdata = kzalloc(sizeof(struct hwspinlock_plat_info), GFP_KERNEL); + if (WARN_ON(pdata == NULL)) + return -ENOMEM; + pdata->sysstatus_offset = SYSSTATUS_OFFSET; + pdata->lock_base_offset = LOCK_BASE_OFFSET; + + omap_device_build(pdev_name, 0, oh, pdata, + sizeof(struct hwspinlock_plat_info), NULL, 0, false); + + return retval; +} +module_init(hwspinlocks_init); + diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index d8d6d58..ce6c5ff 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -4875,7 +4875,7 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* &omap44xx_smartreflex_iva_hwmod, */ /* &omap44xx_smartreflex_mpu_hwmod, */ /* spinlock class */ -/* &omap44xx_spinlock_hwmod, */ + &omap44xx_spinlock_hwmod, /* timer class */ &omap44xx_timer1_hwmod, &omap44xx_timer2_hwmod, diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index a37abf5..f725afc 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -32,4 +32,5 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o obj-$(CONFIG_OMAP_REMOTE_PROC) += remoteproc.o -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o \ No newline at end of file diff --git a/arch/arm/plat-omap/hwspinlock.c b/arch/arm/plat-omap/hwspinlock.c new file mode 100644 index 0000000..1883add --- /dev/null +++ b/arch/arm/plat-omap/hwspinlock.c @@ -0,0 +1,335 @@ +/* + * OMAP hardware spinlock driver + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * This driver supports: + * - Reserved spinlocks for internal use + * - Dynamic allocation of unreserved locks + * - Lock, unlock, and trylock functions, with or without disabling irqs/preempt + * - Registered as a platform device driver + * + * The device initialization uses hwmod to configure the devices. One device + * will be created for each IP. It will pass spinlock register offset info to + * the driver. The device initialization file is: + * arch/arm/mach-omap2/hwspinlocks.c + * + * The driver takes in register offset info passed in device initialization. + * It uses hwmod to obtain the base address of the hardware spinlock module. + * Then it reads info from the registers. The function hwspinlock_probe() + * initializes the array of spinlock structures, each containing a spinlock + * register address calculated from the base address and lock offsets. + * + * Here's an API summary: + * + * int hwspinlock_lock(struct hwspinlock *); + * Attempt to lock a hardware spinlock. If it is busy, the function will + * keep trying until it succeeds. This is a blocking function. + * int hwspinlock_trylock(struct hwspinlock *); + * Attempt to lock a hardware spinlock. If it is busy, the function will + * return BUSY. If it succeeds in locking, the function will return + * ACQUIRED. This is a non-blocking function + * int hwspinlock_unlock(struct hwspinlock *); + * Unlock a hardware spinlock. + * + * struct hwspinlock *hwspinlock_request(void); + * Provides for "dynamic allocation" of a hardware spinlock. It returns + * the handle to the next available (unallocated) spinlock. If no more + * locks are available, it returns NULL. + * struct hwspinlock *hwspinlock_request_specific(unsigned int); + * Provides for "static allocation" of a specific hardware spinlock. This + * allows the system to use a specific spinlock, identified by an ID. If + * the ID is invalid or if the desired lock is already allocated, this + * will return NULL. Otherwise it returns a spinlock handle. + * int hwspinlock_free(struct hwspinlock *); + * Frees an allocated hardware spinlock (either reserved or unreserved). + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Spinlock count code */ +#define SPINLOCK_32_REGS 1 +#define SPINLOCK_64_REGS 2 +#define SPINLOCK_128_REGS 4 +#define SPINLOCK_256_REGS 8 +#define SPINLOCK_NUMLOCKS_OFFSET 24 + +/* for managing a hardware spinlock module */ +struct hwspinlock_state { + bool is_init; /* For first-time initialization */ + int num_locks; /* Total number of locks in system */ + spinlock_t local_lock; /* Local protection */ + void __iomem *io_base; /* Mapped base address */ +}; + +/* Points to the hardware spinlock module */ +static struct hwspinlock_state hwspinlock_state; +static struct hwspinlock_state *hwspinlock_module = &hwspinlock_state; + +/* Spinlock object */ +struct hwspinlock { + bool is_init; + int id; + void __iomem *lock_reg; + bool is_allocated; + struct platform_device *pdev; +}; + +/* Array of spinlocks */ +static struct hwspinlock *hwspinlocks; + +/* API functions */ + +/* Busy loop to acquire a spinlock */ +int hwspinlock_lock(struct hwspinlock *handle) +{ + int retval; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_irq())) + return -EPERM; + + if (pm_runtime_get(&handle->pdev->dev) < 0) + return -ENODEV; + + /* Attempt to acquire the lock by reading from it */ + do { + retval = readl(handle->lock_reg); + } while (retval == HWSPINLOCK_BUSY); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_lock); + +/* Attempt to acquire a spinlock once */ +int hwspinlock_trylock(struct hwspinlock *handle) +{ + int retval = 0; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_irq())) + return -EPERM; + + if (pm_runtime_get(&handle->pdev->dev) < 0) + return -ENODEV; + + /* Attempt to acquire the lock by reading from it */ + retval = readl(handle->lock_reg); + + if (retval == HWSPINLOCK_BUSY) + pm_runtime_put(&handle->pdev->dev); + + return retval; +} +EXPORT_SYMBOL(hwspinlock_trylock); + +/* Release a spinlock */ +int hwspinlock_unlock(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + /* Release it by writing 0 to it */ + writel(0, handle->lock_reg); + + pm_runtime_put(&handle->pdev->dev); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_unlock); + +/* Request an unclaimed spinlock */ +struct hwspinlock *hwspinlock_request(void) +{ + int i; + bool found = false; + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + /* Search for an unclaimed, unreserved lock */ + for (i = 0; i < hwspinlock_module->num_locks && !found; i++) { + if (!hwspinlocks[i].is_allocated) { + found = true; + handle = &hwspinlocks[i]; + } + } + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + + /* Return error if no more locks available */ + if (!found) + return NULL; + + handle->is_allocated = true; + + return handle; +} +EXPORT_SYMBOL(hwspinlock_request); + +/* Request an unclaimed spinlock by ID */ +struct hwspinlock *hwspinlock_request_specific(unsigned int id) +{ + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + + if (WARN_ON(hwspinlocks[id].is_allocated)) + goto exit; + + handle = &hwspinlocks[id]; + handle->is_allocated = true; + +exit: + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + return handle; +} +EXPORT_SYMBOL(hwspinlock_request_specific); + +/* Release a claimed spinlock */ +int hwspinlock_free(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(!handle->is_allocated)) + return -ENOMEM; + + handle->is_allocated = false; + + return 0; +} +EXPORT_SYMBOL(hwspinlock_free); + +/* Probe function */ +static int __devinit hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_plat_info *pdata = pdev->dev.platform_data; + struct resource *res; + void __iomem *io_base; + int id; + + void __iomem *sysstatus_reg; + + /* Determine number of locks */ + sysstatus_reg = ioremap(OMAP44XX_SPINLOCK_BASE + + pdata->sysstatus_offset, sizeof(u32)); + switch (readl(sysstatus_reg) >> SPINLOCK_NUMLOCKS_OFFSET) { + case SPINLOCK_32_REGS: + hwspinlock_module->num_locks = 32; + break; + case SPINLOCK_64_REGS: + hwspinlock_module->num_locks = 64; + break; + case SPINLOCK_128_REGS: + hwspinlock_module->num_locks = 128; + break; + case SPINLOCK_256_REGS: + hwspinlock_module->num_locks = 256; + break; + default: + return -EINVAL; /* Invalid spinlock count code */ + } + iounmap(sysstatus_reg); + + /* Allocate spinlock device objects */ + hwspinlocks = kmalloc(sizeof(struct hwspinlock) * + hwspinlock_module->num_locks, GFP_KERNEL); + if (WARN_ON(hwspinlocks == NULL)) + return -ENOMEM; + + /* Initialize local lock */ + spin_lock_init(&hwspinlock_module->local_lock); + + /* Get address info */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + /* Map spinlock module address space */ + io_base = ioremap(res->start, resource_size(res)); + hwspinlock_module->io_base = io_base; + + /* Set up each individual lock handle */ + for (id = 0; id < hwspinlock_module->num_locks; id++) { + hwspinlocks[id].id = id; + hwspinlocks[id].pdev = pdev; + + hwspinlocks[id].is_init = true; + hwspinlocks[id].is_allocated = false; + + hwspinlocks[id].lock_reg = io_base + pdata-> + lock_base_offset + sizeof(u32) * id; + } + + return 0; +} + +static struct platform_driver hwspinlock_driver = { + .probe = hwspinlock_probe, + .driver = { + .name = "hwspinlock", + }, +}; + +/* Initialization function */ +static int __init hwspinlock_init(void) +{ + int retval = 0; + + /* Register spinlock driver */ + retval = platform_driver_register(&hwspinlock_driver); + + return retval; +} + +/* Cleanup function */ +static void __exit hwspinlock_exit(void) +{ + int id; + + platform_driver_unregister(&hwspinlock_driver); + + for (id = 0; id < hwspinlock_module->num_locks; id++) + hwspinlocks[id].is_init = false; + iounmap(hwspinlock_module->io_base); + + /* Free spinlock device objects */ + if (hwspinlock_module->is_init) + kfree(hwspinlocks); +} + +module_init(hwspinlock_init); +module_exit(hwspinlock_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver"); +MODULE_AUTHOR("Simon Que"); +MODULE_AUTHOR("Hari Kanigeri"); diff --git a/arch/arm/plat-omap/include/plat/hwspinlock.h b/arch/arm/plat-omap/include/plat/hwspinlock.h new file mode 100644 index 0000000..8c69ca5 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/hwspinlock.h @@ -0,0 +1,29 @@ +/* hwspinlock.h */ + +#ifndef HWSPINLOCK_H +#define HWSPINLOCK_H + +#include +#include + +/* Read values from the spinlock register */ +#define HWSPINLOCK_ACQUIRED 0 +#define HWSPINLOCK_BUSY 1 + +/* Device data */ +struct hwspinlock_plat_info { + u32 sysstatus_offset; /* System status register offset */ + u32 lock_base_offset; /* Offset of spinlock registers */ +}; + +struct hwspinlock; + +int hwspinlock_lock(struct hwspinlock *handle); +int hwspinlock_trylock(struct hwspinlock *handle); +int hwspinlock_unlock(struct hwspinlock *handle); + +struct hwspinlock *hwspinlock_request(void); +struct hwspinlock *hwspinlock_request_specific(unsigned int id); +int hwspinlock_free(struct hwspinlock *hwspinlock_ptr); + +#endif /* HWSPINLOCK_H */ diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index 8b3f12f..8016508 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -52,5 +52,7 @@ #define OMAP4_MMU1_BASE 0x55082000 #define OMAP4_MMU2_BASE 0x4A066000 +#define OMAP44XX_SPINLOCK_BASE (L4_44XX_BASE + 0xF6000) + #endif /* __ASM_ARCH_OMAP44XX_H */ From patchwork Thu Jul 29 09:59:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 115039 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6TABn5C006472 for ; Thu, 29 Jul 2010 10:12:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756098Ab0G2KBV (ORCPT ); Thu, 29 Jul 2010 06:01:21 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59302 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756422Ab0G2KBE (ORCPT ); Thu, 29 Jul 2010 06:01:04 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6TA0vKg008954 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Jul 2010 05:00:59 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6TA0qYm006167; Thu, 29 Jul 2010 15:30:54 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Benoit Cousson , Kevin Hilman , Paul Walmsley , Tony Lindgren , Anand Sawant , Santosh Shilimkar , Rajendra Nayak , Basak Partha , Charulatha V Subject: [PATCH 07/11] OMAP2/3/4: DMA: HWMOD: Device registration Date: Thu, 29 Jul 2010 15:29:01 +0530 Message-Id: <1280397545-27323-8-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280397545-27323-1-git-send-email-manjugk@ti.com> References: <1280397545-27323-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 29 Jul 2010 10:13:13 +0000 (UTC) diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c new file mode 100644 index 0000000..da76c34 --- /dev/null +++ b/arch/arm/mach-omap2/dma.c @@ -0,0 +1,134 @@ +/* + * dma.c - OMAP2 specific DMA code + * + * Copyright (C) 2003 - 2008 Nokia Corporation + * Author: Juha Yrjölä + * DMA channel linking for 1610 by Samuel Ortiz + * Graphics DMA and LCD DMA graphics tranformations + * by Imre Deak + * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. + * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Converted DMA library into platform driver by Manjunatha GK + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define dma_read(reg) \ +({ \ + u32 __val; \ + __val = __raw_readl(dma_base + OMAP_DMA4_##reg); \ + __val; \ +}) + +#define dma_write(val, reg) \ +({ \ + __raw_writel((val), dma_base + OMAP_DMA4_##reg); \ +}) + +static struct omap_dma_dev_attr *d; +static void __iomem *dma_base; +static struct omap_system_dma_plat_info *omap2_pdata; +static int dma_caps0_status; + +static struct omap_device_pm_latency omap2_dma_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +/* One time initializations */ +static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) +{ + struct omap_device *od; + struct omap_system_dma_plat_info *pdata; + struct resource *mem; + char *name = "dma"; + + pdata = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); + if (!pdata) { + pr_err("%s: Unable to allocate pdata for %s:%s\n", + __func__, name, oh->name); + return -ENOMEM; + } + + pdata->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; + + od = omap_device_build(name, 0, oh, pdata, sizeof(*pdata), + omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); + + if (IS_ERR(od)) { + pr_err("%s: Cant build omap_device for %s:%s.\n", + __func__, name, oh->name); + kfree(pdata); + return 0; + } + + mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__); + return -EINVAL; + } + + dma_base = ioremap(mem->start, resource_size(mem)); + if (!dma_base) { + dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__); + return -ENOMEM; + } + + /* Get DMA device attributes from hwmod data base */ + d = (struct omap_dma_dev_attr *)oh->dev_attr; + + /* OMAP2 Plus: physical and logical channel count is same */ + d->dma_chan_count = d->dma_lch_count; + + d->dma_chan = kzalloc(sizeof(struct omap_dma_lch) * + (d->dma_lch_count), GFP_KERNEL); + + if (!d->dma_chan) { + dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__); + return -ENOMEM; + } + + omap2_pdata = pdata; + dma_caps0_status = dma_read(CAPS_0); + + return 0; +} + +static int __init omap2_system_dma_init(void) +{ + int ret; + + ret = omap_hwmod_for_each_by_class("dma", + omap2_system_dma_init_dev, NULL); + + return ret; +} +arch_initcall(omap2_system_dma_init); diff --git a/arch/arm/mach-omap2/include/mach/dma.h b/arch/arm/mach-omap2/include/mach/dma.h new file mode 100644 index 0000000..3eca7d8 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/dma.h @@ -0,0 +1,80 @@ +/* + * OMAP DMA controller register offsets. + * + * Copyright (C) 2003 Nokia Corporation + * Author: Juha Yrjölä + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar + * + * Copyright (C) 2010 Texas Instruments + * Converted DMA library into platform driver by Manjunatha GK + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP2_DMA_H +#define __ASM_ARCH_OMAP2_DMA_H + +/* OMAP2 Plus register offset's */ +#define OMAP_DMA4_REVISION 0x00 +#define OMAP_DMA4_GCR 0x78 +#define OMAP_DMA4_IRQSTATUS_L0 0x08 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c +#define OMAP_DMA4_IRQSTATUS_L2 0x10 +#define OMAP_DMA4_IRQSTATUS_L3 0x14 +#define OMAP_DMA4_IRQENABLE_L0 0x18 +#define OMAP_DMA4_IRQENABLE_L1 0x1c +#define OMAP_DMA4_IRQENABLE_L2 0x20 +#define OMAP_DMA4_IRQENABLE_L3 0x24 +#define OMAP_DMA4_SYSSTATUS 0x28 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c +#define OMAP_DMA4_CAPS_0 0x64 +#define OMAP_DMA4_CAPS_2 0x6c +#define OMAP_DMA4_CAPS_3 0x70 +#define OMAP_DMA4_CAPS_4 0x74 + +/* Should be part of hwmod data base ? */ +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ + +/* Common channel specific registers for omap2 */ +#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) +#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) +#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) +#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) +#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) +#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) +#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) +#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) +#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) +#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) +#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) +#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) +#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) +#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) + +/* Channel specific registers only on omap2 */ +#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) +#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) +#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) +#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) +#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) + +/* Additional registers available on OMAP4 */ +#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0) +#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4) +#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8) + +#endif /* __ASM_ARCH_OMAP2_DMA_H */ From patchwork Thu Jul 29 09:59:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 115038 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6TABn5E006472 for ; Thu, 29 Jul 2010 10:13:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756391Ab0G2KBY (ORCPT ); Thu, 29 Jul 2010 06:01:24 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59301 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756412Ab0G2KBE (ORCPT ); Thu, 29 Jul 2010 06:01:04 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6TA0vn0008957 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Jul 2010 05:00:59 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6TA0qYn006167; Thu, 29 Jul 2010 15:30:55 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Benoit Cousson , Kevin Hilman , Paul Walmsley , Tony Lindgren , Anand Sawant , Santosh Shilimkar , Rajendra Nayak , Basak Partha , Charulatha V Subject: [PATCH 08/11] OMAP: DMA: Convert DMA library into DMA platform Driver Date: Thu, 29 Jul 2010 15:29:02 +0530 Message-Id: <1280397545-27323-9-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280397545-27323-1-git-send-email-manjugk@ti.com> References: <1280397545-27323-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 29 Jul 2010 10:13:22 +0000 (UTC) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index fd4df71..a159af4 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o +obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o obj-y += clock.o clock_data.o opp_data.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap1/include/mach/dma.h b/arch/arm/mach-omap1/include/mach/dma.h index d446cdd..1eb0d31 100644 --- a/arch/arm/mach-omap1/include/mach/dma.h +++ b/arch/arm/mach-omap1/include/mach/dma.h @@ -77,4 +77,70 @@ #define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) #define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) +/* Dummy defines to support multi omap code */ +/* Channel specific registers */ +#define OMAP_DMA4_CCR(n) 0 +#define OMAP_DMA4_CSDP(n) 0 +#define OMAP_DMA4_CEN(n) 0 +#define OMAP_DMA4_CFN(n) 0 +#define OMAP_DMA4_COLOR(n) 0 +#define OMAP_DMA4_CSSA(n) 0 +#define OMAP_DMA4_CSEI(n) 0 +#define OMAP_DMA4_CSFI(n) 0 +#define OMAP_DMA4_CDSA(n) 0 +#define OMAP_DMA4_CDEI(n) 0 +#define OMAP_DMA4_CDFI(n) 0 +#define OMAP_DMA4_CSR(n) 0 +#define OMAP_DMA4_CICR(n) 0 +#define OMAP_DMA4_CLNK_CTRL(n) 0 +#define OMAP_DMA4_CH_BASE(n) 0 +#define OMAP_DMA4_CDAC(n) 0 +#define OMAP_DMA4_CSAC(n) 0 + +/* Common registers */ +#define OMAP_DMA4_IRQENABLE_L0 0 +#define OMAP_DMA4_OCP_SYSCONFIG 0 +#define OMAP_DMA4_GCR 0 +#define OMAP_DMA4_IRQSTATUS_L0 0 +#define OMAP_DMA4_CAPS_2 0 +#define OMAP_DMA4_CAPS_3 0 +#define OMAP_DMA4_CAPS_4 0 +#define OMAP_DMA4_REVISION 0 + +#define OMAP_DMA4_CCR2(n) 0 +#define OMAP_DMA4_LCH_CTRL(n) 0 +#define OMAP_DMA4_COLOR_L(n) 0 +#define OMAP_DMA4_COLOR_U(n) 0 +#define OMAP1_DMA_COLOR(n) 0 +#define OMAP_DMA4_CSSA_U(n) 0 +#define OMAP_DMA4_CSSA_L(n) 0 +#define OMAP1_DMA_CSSA(n) 0 +#define OMAP_DMA4_CDSA_U(n) 0 +#define OMAP_DMA4_CDSA_L(n) 0 +#define OMAP1_DMA_CDSA(n) 0 +#define OMAP_DMA4_CPC(n) 0 + +#define OMAP1_DMA_IRQENABLE_L0 0 +#define OMAP1_DMA_IRQENABLE_L0 0 +#define OMAP1_DMA_IRQSTATUS_L0 0 +#define OMAP1_DMA_OCP_SYSCONFIG 0 +#define OMAP_DMA4_HW_ID 0 +#define OMAP_DMA4_CAPS_0_U 0 +#define OMAP_DMA4_CAPS_0_L 0 +#define OMAP_DMA4_CAPS_1_U 0 +#define OMAP_DMA4_CAPS_1_L 0 +#define OMAP_DMA4_GSCR 0 +#define OMAP1_DMA_REVISION 0 + +struct omap_dma_lch { + int next_lch; + int dev_id; + u16 saved_csr; + u16 enabled_irqs; + const char *dev_name; + void (*callback)(int lch, u16 ch_status, void *data); + void *data; + long flags; +}; + #endif /* __ASM_ARCH_OMAP1_DMA_H */ diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ae5f36f..3c5557a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o dma.o omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ diff --git a/arch/arm/mach-omap2/include/mach/dma.h b/arch/arm/mach-omap2/include/mach/dma.h index 3eca7d8..22f4b41 100644 --- a/arch/arm/mach-omap2/include/mach/dma.h +++ b/arch/arm/mach-omap2/include/mach/dma.h @@ -77,4 +77,87 @@ #define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4) #define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8) + +/* Dummy defines for support multi omap code */ +/* Common registers */ +#define OMAP1_DMA_GCR 0 +#define OMAP1_DMA_HW_ID 0 +#define OMAP1_DMA_CAPS_0_U 0 +#define OMAP1_DMA_CAPS_0_L 0 +#define OMAP1_DMA_CAPS_1_U 0 +#define OMAP1_DMA_CAPS_1_L 0 +#define OMAP1_DMA_CAPS_2 0 +#define OMAP1_DMA_CAPS_3 0 +#define OMAP1_DMA_CAPS_4 0 +#define OMAP1_DMA_GSCR 0 + +/* Channel specific registers */ +#define OMAP1_DMA_CH_BASE(n) 0 +#define OMAP1_DMA_CCR(n) 0 +#define OMAP1_DMA_CSDP(n) 0 +#define OMAP1_DMA_CCR2(n) 0 +#define OMAP1_DMA_CEN(n) 0 +#define OMAP1_DMA_CFN(n) 0 +#define OMAP1_DMA_LCH_CTRL(n) 0 +#define OMAP1_DMA_COLOR_L(n) 0 +#define OMAP1_DMA_COLOR_U(n) 0 +#define OMAP1_DMA_CSSA_U(n) 0 +#define OMAP1_DMA_CSSA_L(n) 0 +#define OMAP1_DMA_CSEI(n) 0 +#define OMAP1_DMA_CSFI(n) 0 +#define OMAP1_DMA_CDSA_U(n) 0 +#define OMAP1_DMA_CDSA_L(n) 0 +#define OMAP1_DMA_CDEI(n) 0 +#define OMAP1_DMA_CDFI(n) 0 +#define OMAP1_DMA_CSR(n) 0 +#define OMAP1_DMA_CICR(n) 0 +#define OMAP1_DMA_CLNK_CTRL(n) 0 +#define OMAP1_DMA_CPC(n) 0 +#define OMAP1_DMA_CDAC(n) 0 +#define OMAP1_DMA_CSAC(n) 0 +#define OMAP1_DMA_CCEN(n) 0 +#define OMAP1_DMA_CCFN(n) 0 + +#define OMAP_DMA4_CCR2(n) 0 +#define OMAP_DMA4_LCH_CTRL(n) 0 +#define OMAP_DMA4_COLOR_L(n) 0 +#define OMAP_DMA4_COLOR_U(n) 0 +#define OMAP1_DMA_COLOR(n) 0 +#define OMAP_DMA4_CSSA_U(n) 0 +#define OMAP_DMA4_CSSA_L(n) 0 +#define OMAP1_DMA_CSSA(n) 0 +#define OMAP_DMA4_CDSA_U(n) 0 +#define OMAP_DMA4_CDSA_L(n) 0 +#define OMAP1_DMA_CDSA(n) 0 +#define OMAP_DMA4_CPC(n) 0 + +#define OMAP1_DMA_IRQENABLE_L0 0 +#define OMAP1_DMA_IRQSTATUS_L0 0 +#define OMAP1_DMA_OCP_SYSCONFIG 0 +#define OMAP1_DMA_OCP_SYSCONFIG 0 +#define OMAP_DMA4_HW_ID 0 +#define OMAP_DMA4_CAPS_0_U 0 +#define OMAP_DMA4_CAPS_0_L 0 +#define OMAP_DMA4_CAPS_1_U 0 +#define OMAP_DMA4_CAPS_1_L 0 +#define OMAP_DMA4_GSCR 0 +#define OMAP1_DMA_REVISION 0 + +struct omap_dma_lch { + int next_lch; + int dev_id; + u16 saved_csr; + u16 enabled_irqs; + const char *dev_name; + void (*callback)(int lch, u16 ch_status, void *data); + void *data; + long flags; + /* required for Dynamic chaining */ + int prev_linked_ch; + int next_linked_ch; + int state; + int chain_id; + int status; +}; + #endif /* __ASM_ARCH_OMAP2_DMA_H */ diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index f7f571e..4627e84 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -15,6 +15,9 @@ * * Support functions for the OMAP internal DMA channels. * + * Copyright (C) 2010 Texas Instruments + * Converted DMA library into DMA platform driver. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -60,27 +63,6 @@ static struct omap_dma_global_context_registers { u32 dma_gcr; } omap_dma_global_context; -struct omap_dma_lch { - int next_lch; - int dev_id; - u16 saved_csr; - u16 enabled_irqs; - const char *dev_name; - void (*callback)(int lch, u16 ch_status, void *data); - void *data; - -#ifndef CONFIG_ARCH_OMAP1 - /* required for Dynamic chaining */ - int prev_linked_ch; - int next_linked_ch; - int state; - int chain_id; - - int status; -#endif - long flags; -}; - struct dma_link_info { int *linked_dmach_q; int no_of_lchs_linked; @@ -136,15 +118,10 @@ static int omap_dma_reserve_channels; static spinlock_t dma_chan_lock; static struct omap_dma_lch *dma_chan; -static void __iomem *omap_dma_base; -static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = { - INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, - INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, - INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, - INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13, - INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD -}; +static void __iomem *omap_dma_base; +static struct omap_system_dma_plat_info *p; +static struct omap_dma_dev_attr *d; static inline void disable_lnk(int lch); static void omap_disable_channel_irq(int lch); @@ -959,7 +936,7 @@ void omap_start_dma(int lch) if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; - char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[dma_chan_count]; dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ @@ -1020,7 +997,7 @@ void omap_stop_dma(int lch) if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; - char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[dma_chan_count]; memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); do { @@ -2036,57 +2013,56 @@ void omap_dma_global_context_restore(void) omap_clear_dma(ch); } -/*----------------------------------------------------------------------------*/ - -static int __init omap_init_dma(void) +static int __devinit omap_system_dma_probe(struct platform_device *pdev) { - unsigned long base; - int ch, r; + struct omap_system_dma_plat_info *pdata = pdev->dev.platform_data; + struct resource *mem; + int ch, ret = 0; + int dma_irq; + char irq_name[14]; + + if (!pdata) { + dev_err(&pdev->dev, "%s: System DMA initialized without" + "platform data\n", __func__); + return -EINVAL; + } - if (cpu_class_is_omap1()) { - base = OMAP1_DMA_BASE; - dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap24xx()) { - base = OMAP24XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap34xx()) { - base = OMAP34XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap44xx()) { - base = OMAP44XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else { - pr_err("DMA init failed for unsupported omap\n"); - return -ENODEV; + p = pdata; + d = p->dma_attr; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "%s: no mem resource\n", __func__); + return -EINVAL; } - omap_dma_base = ioremap(base, SZ_4K); - BUG_ON(!omap_dma_base); + omap_dma_base = ioremap(mem->start, resource_size(mem)); + if (!omap_dma_base) { + dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); + ret = -ENOMEM; + goto exit_release_region; + } if (cpu_class_is_omap2() && omap_dma_reserve_channels && (omap_dma_reserve_channels <= dma_lch_count)) - dma_lch_count = omap_dma_reserve_channels; + d->dma_lch_count = omap_dma_reserve_channels; - dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, - GFP_KERNEL); - if (!dma_chan) { - r = -ENOMEM; - goto out_unmap; - } + dma_lch_count = d->dma_lch_count; + dma_chan_count = d->dma_chan_count; + dma_chan = d->dma_chan; if (cpu_class_is_omap2()) { dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * dma_lch_count, GFP_KERNEL); if (!dma_linked_lch) { - r = -ENOMEM; - goto out_free; + ret = -ENOMEM; + goto exit_dma_chan; } } + enable_1510_mode = d->dma_dev_attr & ENABLE_1510_MODE; if (cpu_is_omap15xx()) { printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); - dma_chan_count = 9; - enable_1510_mode = 1; } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { printk(KERN_INFO "OMAP DMA hardware version %d\n", dma_read(HW_ID)); @@ -2104,21 +2080,14 @@ static int __init omap_init_dma(void) w = dma_read(GSCR); w |= 1 << 3; dma_write(w, GSCR); - dma_chan_count = 16; - } else - dma_chan_count = 9; + } } else if (cpu_class_is_omap2()) { u8 revision = dma_read(REVISION) & 0xff; printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", revision >> 4, revision & 0xf); - dma_chan_count = dma_lch_count; - } else { - dma_chan_count = 0; - return 0; } spin_lock_init(&dma_chan_lock); - for (ch = 0; ch < dma_chan_count; ch++) { omap_clear_dma(ch); if (cpu_class_is_omap2()) @@ -2135,19 +2104,29 @@ static int __init omap_init_dma(void) * request_irq() doesn't like dev_id (ie. ch) being * zero, so we have to kludge around this. */ - r = request_irq(omap1_dma_irq[ch], + dma_irq = platform_get_irq_byname(pdev, irq_name); + + if (dma_irq < 0) { + dev_err(&pdev->dev, "%s:unable to get irq\n", + __func__); + ret = dma_irq; + goto exit_unmap; + } + ret = request_irq(dma_irq, omap1_dma_irq_handler, 0, "DMA", (void *) (ch + 1)); - if (r != 0) { - int i; - - printk(KERN_ERR "unable to request IRQ %d " - "for DMA (error %d)\n", - omap1_dma_irq[ch], r); - for (i = 0; i < ch; i++) - free_irq(omap1_dma_irq[i], - (void *) (i + 1)); - goto out_free; + if (ret != 0) { + int irq_rel; + printk(KERN_ERR "unable to request IRQ %d" + "for DMA (error %d)\n", dma_irq, ret); + for (irq_rel = 0; irq_rel < ch; + irq_rel++) { + dma_irq = platform_get_irq(pdev, + irq_rel); + free_irq(dma_irq, (void *) + (irq_rel + 1)); + goto exit_dma_chan; + } } } } @@ -2157,46 +2136,65 @@ static int __init omap_init_dma(void) DMA_DEFAULT_FIFO_DEPTH, 0); if (cpu_class_is_omap2()) { - int irq; - if (cpu_is_omap44xx()) - irq = OMAP44XX_IRQ_SDMA_0; - else - irq = INT_24XX_SDMA_IRQ0; - setup_irq(irq, &omap24xx_dma_irq); - } - - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - /* Enable smartidle idlemodes and autoidle */ - u32 v = dma_read(OCP_SYSCONFIG); - v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | - DMA_SYSCONFIG_SIDLEMODE_MASK | - DMA_SYSCONFIG_AUTOIDLE); - v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | - DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | - DMA_SYSCONFIG_AUTOIDLE); - dma_write(v , OCP_SYSCONFIG); - /* reserve dma channels 0 and 1 in high security devices */ - if (cpu_is_omap34xx() && - (omap_type() != OMAP2_DEVICE_TYPE_GP)) { - printk(KERN_INFO "Reserving DMA channels 0 and 1 for " - "HS ROM code\n"); - dma_chan[0].dev_id = 0; - dma_chan[1].dev_id = 1; - } + strcpy(irq_name, "dma_0"); + dma_irq = platform_get_irq_byname(pdev, irq_name); + setup_irq(dma_irq, &omap24xx_dma_irq); } + /* reserve dma channels 0 and 1 in high security devices */ + if (cpu_is_omap34xx() && + (omap_type() != OMAP2_DEVICE_TYPE_GP)) { + printk(KERN_INFO "Reserving DMA channels 0 and 1 for " + "HS ROM code\n"); + dma_chan[0].dev_id = 0; + dma_chan[1].dev_id = 1; + } + + dev_info(&pdev->dev, "System DMA registered\n"); return 0; -out_free: +exit_dma_chan: kfree(dma_chan); +exit_unmap: + iounmap(omap_dma_base); +exit_release_region: + release_mem_region(mem->start, resource_size(mem)); + return ret; +} -out_unmap: +static int __devexit omap_system_dma_remove(struct platform_device *pdev) +{ + struct resource *mem; iounmap(omap_dma_base); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(mem->start, resource_size(mem)); + return 0; +} + +static struct platform_driver omap_system_dma_driver = { + .probe = omap_system_dma_probe, + .remove = omap_system_dma_remove, + .driver = { + .name = "dma" + }, +}; - return r; +static int __init omap_system_dma_init(void) +{ + return platform_driver_register(&omap_system_dma_driver); +} + +arch_initcall(omap_system_dma_init); + +static void __exit omap_system_dma_exit(void) +{ + platform_driver_unregister(&omap_system_dma_driver); } -arch_initcall(omap_init_dma); +MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_AUTHOR("Texas Instruments Inc"); /* * Reserve the omap SDMA channels using cmdline bootarg diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index ff60f11..92c348f 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -21,142 +21,11 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H +#include + /* Move omap4 specific defines to dma-44xx.h */ #include "dma-44xx.h" -/* Hardware registers for omap1 */ -#define OMAP1_DMA_BASE (0xfffed800) - -#define OMAP1_DMA_GCR 0x400 -#define OMAP1_DMA_GSCR 0x404 -#define OMAP1_DMA_GRST 0x408 -#define OMAP1_DMA_HW_ID 0x442 -#define OMAP1_DMA_PCH2_ID 0x444 -#define OMAP1_DMA_PCH0_ID 0x446 -#define OMAP1_DMA_PCH1_ID 0x448 -#define OMAP1_DMA_PCHG_ID 0x44a -#define OMAP1_DMA_PCHD_ID 0x44c -#define OMAP1_DMA_CAPS_0_U 0x44e -#define OMAP1_DMA_CAPS_0_L 0x450 -#define OMAP1_DMA_CAPS_1_U 0x452 -#define OMAP1_DMA_CAPS_1_L 0x454 -#define OMAP1_DMA_CAPS_2 0x456 -#define OMAP1_DMA_CAPS_3 0x458 -#define OMAP1_DMA_CAPS_4 0x45a -#define OMAP1_DMA_PCH2_SR 0x460 -#define OMAP1_DMA_PCH0_SR 0x480 -#define OMAP1_DMA_PCH1_SR 0x482 -#define OMAP1_DMA_PCHD_SR 0x4c0 - -/* Hardware registers for omap2 and omap3 */ -#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) -#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) -#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000) - -#define OMAP_DMA4_REVISION 0x00 -#define OMAP_DMA4_GCR 0x78 -#define OMAP_DMA4_IRQSTATUS_L0 0x08 -#define OMAP_DMA4_IRQSTATUS_L1 0x0c -#define OMAP_DMA4_IRQSTATUS_L2 0x10 -#define OMAP_DMA4_IRQSTATUS_L3 0x14 -#define OMAP_DMA4_IRQENABLE_L0 0x18 -#define OMAP_DMA4_IRQENABLE_L1 0x1c -#define OMAP_DMA4_IRQENABLE_L2 0x20 -#define OMAP_DMA4_IRQENABLE_L3 0x24 -#define OMAP_DMA4_SYSSTATUS 0x28 -#define OMAP_DMA4_OCP_SYSCONFIG 0x2c -#define OMAP_DMA4_CAPS_0 0x64 -#define OMAP_DMA4_CAPS_2 0x6c -#define OMAP_DMA4_CAPS_3 0x70 -#define OMAP_DMA4_CAPS_4 0x74 - -#define OMAP1_LOGICAL_DMA_CH_COUNT 17 -#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ - -/* Common channel specific registers for omap1 */ -#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) -#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) -#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) -#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) -#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) -#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) -#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) -#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) -#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) -#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ -#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) -#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) -#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) -#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) -#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) - -/* Common channel specific registers for omap2 */ -#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) -#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) -#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) -#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) -#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) -#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) -#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) -#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) -#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) -#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) -#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) -#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) -#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) -#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) - -/* Channel specific registers only on omap1 */ -#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) -#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) -#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) -#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) -#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) -#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) -#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) -#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ -#define OMAP1_DMA_CCEN(n) 0 -#define OMAP1_DMA_CCFN(n) 0 - -/* Channel specific registers only on omap2 */ -#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) -#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) -#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) -#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) -#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) - -/* Additional registers available on OMAP4 */ -#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0) -#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4) -#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8) - -/* Dummy defines to keep multi-omap compiles happy */ -#define OMAP1_DMA_REVISION 0 -#define OMAP1_DMA_IRQSTATUS_L0 0 -#define OMAP1_DMA_IRQENABLE_L0 0 -#define OMAP1_DMA_OCP_SYSCONFIG 0 -#define OMAP_DMA4_HW_ID 0 -#define OMAP_DMA4_CAPS_0_L 0 -#define OMAP_DMA4_CAPS_0_U 0 -#define OMAP_DMA4_CAPS_1_L 0 -#define OMAP_DMA4_CAPS_1_U 0 -#define OMAP_DMA4_GSCR 0 -#define OMAP_DMA4_CPC(n) 0 - -#define OMAP_DMA4_LCH_CTRL(n) 0 -#define OMAP_DMA4_COLOR_L(n) 0 -#define OMAP_DMA4_COLOR_U(n) 0 -#define OMAP_DMA4_CCR2(n) 0 -#define OMAP1_DMA_CSSA(n) 0 -#define OMAP1_DMA_CDSA(n) 0 -#define OMAP_DMA4_CSSA_L(n) 0 -#define OMAP_DMA4_CSSA_U(n) 0 -#define OMAP_DMA4_CDSA_L(n) 0 -#define OMAP_DMA4_CDSA_U(n) 0 -#define OMAP1_DMA_COLOR(n) 0 - -/*----------------------------------------------------------------------------*/ - /* DMA channels for omap1 */ #define OMAP_DMA_NO_DEVICE 0 #define OMAP_DMA_MCSI1_TX 1 @@ -372,21 +241,6 @@ #define DMA_THREAD_FIFO_25 (0x02 << 14) #define DMA_THREAD_FIFO_50 (0x03 << 14) -/* DMA4_OCP_SYSCONFIG bits */ -#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) -#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) -#define DMA_SYSCONFIG_EMUFREE (1 << 5) -#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) -#define DMA_SYSCONFIG_SOFTRESET (1 << 2) -#define DMA_SYSCONFIG_AUTOIDLE (1 << 0) - -#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) -#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) - -#define DMA_IDLEMODE_SMARTIDLE 0x2 -#define DMA_IDLEMODE_NO_IDLE 0x1 -#define DMA_IDLEMODE_FORCE_IDLE 0x0 - /* Chaining modes*/ #ifndef CONFIG_ARCH_OMAP1 #define OMAP_DMA_STATIC_CHAIN 0x1 @@ -479,6 +333,7 @@ struct omap_dma_channel_params { #endif }; +#include struct omap_dma_dev_attr { u32 dma_dev_attr; u16 dma_lch_count; @@ -486,6 +341,12 @@ struct omap_dma_dev_attr { struct omap_dma_lch *dma_chan; }; +/* System DMA platform data structure */ +struct omap_system_dma_plat_info { + struct omap_dma_dev_attr *dma_attr; + void __iomem *omap_dma_base; +}; + extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), From patchwork Fri May 14 12:06:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gadiyar X-Patchwork-Id: 99591 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4EC6GgZ007252 for ; Fri, 14 May 2010 12:06:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758786Ab0ENMGP (ORCPT ); Fri, 14 May 2010 08:06:15 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:54574 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758766Ab0ENMGM (ORCPT ); Fri, 14 May 2010 08:06:12 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4EC69gI007586 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 14 May 2010 07:06:11 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4EC6764014864; Fri, 14 May 2010 17:36:07 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4EC67K3016703; Fri, 14 May 2010 17:36:07 +0530 Received: (from a0393673@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4EC67Xj016701; Fri, 14 May 2010 17:36:07 +0530 From: Anand Gadiyar To: linux-omap@vger.kernel.org Cc: Anand Gadiyar Subject: [PATCH 2/2] omap: 3630: disable TLL SAR on 3630 ES1 Date: Fri, 14 May 2010 17:36:07 +0530 Message-Id: <1273838767-16638-2-git-send-email-gadiyar@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1273838767-16638-1-git-send-email-gadiyar@ti.com> References: <1273838767-16638-1-git-send-email-gadiyar@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 14 May 2010 12:06:17 +0000 (UTC) Index: linux-omap-2.6/arch/arm/mach-omap2/powerdomains34xx.h =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/powerdomains34xx.h +++ linux-omap-2.6/arch/arm/mach-omap2/powerdomains34xx.h @@ -80,7 +80,8 @@ static struct powerdomain core_3xxx_pre_ .prcm_offs = CORE_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0), + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3630ES1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 2, @@ -97,7 +98,8 @@ static struct powerdomain core_3xxx_pre_ static struct powerdomain core_3xxx_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | + CHIP_GE_OMAP3630ES1_1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ From patchwork Tue Jun 22 15:01:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107404 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF1XKj017599 for ; Tue, 22 Jun 2010 15:01:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758421Ab0FVPBd (ORCPT ); Tue, 22 Jun 2010 11:01:33 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41820 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758499Ab0FVPB3 (ORCPT ); Tue, 22 Jun 2010 11:01:29 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1MCe024609 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:25 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZh026711; Tue, 22 Jun 2010 20:31:20 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 01/13] OMAP: GPIO: Modify init() in preparation for platform device implementation Date: Tue, 22 Jun 2010 20:31:44 +0530 Message-Id: <1277218916-15213-2-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-1-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:35 +0000 (UTC) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 9b7e354..3ea616a 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -190,14 +190,12 @@ struct gpio_bank { u32 suspend_wakeup; u32 saved_wakeup; #endif -#ifdef CONFIG_ARCH_OMAP2PLUS u32 non_wakeup_gpios; u32 enabled_non_wakeup_gpios; u32 saved_datain; u32 saved_fallingdetect; u32 saved_risingdetect; -#endif u32 level_mask; u32 toggle_mask; spinlock_t lock; @@ -1711,6 +1709,124 @@ static void __init omap_gpio_show_rev(void) */ static struct lock_class_key gpio_lock_class; +static void omap_gpio_mod_init(struct gpio_bank *bank, int id) +{ + if (cpu_class_is_omap2()) { + if (cpu_is_omap44xx()) { + __raw_writel(0xffffffff, bank->base + + OMAP4_GPIO_IRQSTATUSCLR0); + __raw_writel(0x00000000, bank->base + + OMAP4_GPIO_DEBOUNCENABLE); + /* Initialize interface clk ungated, module enabled */ + __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); + } else if (cpu_is_omap34xx()) { + __raw_writel(0x00000000, bank->base + + OMAP24XX_GPIO_IRQENABLE1); + __raw_writel(0xffffffff, bank->base + + OMAP24XX_GPIO_IRQSTATUS1); + __raw_writel(0x00000000, bank->base + + OMAP24XX_GPIO_DEBOUNCE_EN); + + /* Initialize interface clk ungated, module enabled */ + __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); + /* Enable autoidle for the OCP interface */ + omap_writel(1 << 0, 0x48306814); + } else if (cpu_is_omap24xx()) { + static const u32 non_wakeup_gpios[] = { + 0xe203ffc0, 0x08700040 + }; + if (id < ARRAY_SIZE(non_wakeup_gpios)) + bank->non_wakeup_gpios = non_wakeup_gpios[id]; + + /* Enable autoidle for the OCP interface */ + omap_writel(1 << 0, 0x48019010); + } + } else if (cpu_class_is_omap1()) { + if (bank_is_mpuio(bank)) + __raw_writew(0xffff, bank->base + + OMAP_MPUIO_GPIO_MASKIT); + if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { + __raw_writew(0xffff, bank->base + + OMAP1510_GPIO_INT_MASK); + __raw_writew(0x0000, bank->base + + OMAP1510_GPIO_INT_STATUS); + } + if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { + __raw_writew(0x0000, bank->base + + OMAP1610_GPIO_IRQENABLE1); + __raw_writew(0xffff, bank->base + + OMAP1610_GPIO_IRQSTATUS1); + __raw_writew(0x0014, bank->base + + OMAP1610_GPIO_SYSCONFIG); + + /* Enable system clock for GPIO module. + * The CAM_CLK_CTRL *is* really the right place. */ + omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, + ULPD_CAM_CLK_CTRL); + } + if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { + __raw_writel(0xffffffff, bank->base + + OMAP7XX_GPIO_INT_MASK); + __raw_writel(0x00000000, bank->base + + OMAP7XX_GPIO_INT_STATUS); + } + } +} + +static void __init omap_gpio_chip_init(struct gpio_bank *bank) +{ + int j, gpio_bank_bits = 16; + static int gpio; + + if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) + gpio_bank_bits = 32; /* 7xx has 32-bit GPIOs */ + + if ((bank->method == METHOD_GPIO_24XX) || + (bank->method == METHOD_GPIO_44XX)) + gpio_bank_bits = 32; + + bank->mod_usage = 0; + /* REVISIT eventually switch from OMAP-specific gpio structs + * over to the generic ones + */ + bank->chip.request = omap_gpio_request; + bank->chip.free = omap_gpio_free; + bank->chip.direction_input = gpio_input; + bank->chip.get = gpio_get; + bank->chip.direction_output = gpio_output; + bank->chip.set_debounce = gpio_debounce; + bank->chip.set = gpio_set; + bank->chip.to_irq = gpio_2irq; + if (bank_is_mpuio(bank)) { + bank->chip.label = "mpuio"; +#ifdef CONFIG_ARCH_OMAP16XX + bank->chip.dev = &omap_mpuio_device.dev; +#endif + bank->chip.base = OMAP_MPUIO(0); + } else { + bank->chip.label = "gpio"; + bank->chip.base = gpio; + gpio += gpio_bank_bits; + } + bank->chip.ngpio = gpio_bank_bits; + + gpiochip_add(&bank->chip); + + for (j = bank->virtual_irq_start; + j < bank->virtual_irq_start + gpio_bank_bits; j++) { + lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); + set_irq_chip_data(j, bank); + if (bank_is_mpuio(bank)) + set_irq_chip(j, &mpuio_irq_chip); + else + set_irq_chip(j, &gpio_irq_chip); + set_irq_handler(j, handle_simple_irq); + set_irq_flags(j, IRQF_VALID); + } + set_irq_chained_handler(bank->irq, gpio_irq_handler); + set_irq_data(bank->irq, bank); +} + static int __init _omap_gpio_init(void) { int i; @@ -1821,7 +1937,6 @@ static int __init _omap_gpio_init(void) } #endif for (i = 0; i < gpio_bank_count; i++) { - int j, gpio_count = 16; bank = &gpio_bank[i]; spin_lock_init(&bank->lock); @@ -1833,107 +1948,8 @@ static int __init _omap_gpio_init(void) continue; } - if (bank_is_mpuio(bank)) - __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); - if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { - __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); - __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); - } - if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { - __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); - __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); - __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); - } - if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { - __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); - __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); - - gpio_count = 32; /* 7xx has 32-bit GPIOs */ - } - -#ifdef CONFIG_ARCH_OMAP2PLUS - if ((bank->method == METHOD_GPIO_24XX) || - (bank->method == METHOD_GPIO_44XX)) { - static const u32 non_wakeup_gpios[] = { - 0xe203ffc0, 0x08700040 - }; - - if (cpu_is_omap44xx()) { - __raw_writel(0xffffffff, bank->base + - OMAP4_GPIO_IRQSTATUSCLR0); - __raw_writew(0x0015, bank->base + - OMAP4_GPIO_SYSCONFIG); - __raw_writel(0x00000000, bank->base + - OMAP4_GPIO_DEBOUNCENABLE); - /* - * Initialize interface clock ungated, - * module enabled - */ - __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); - } else { - __raw_writel(0x00000000, bank->base + - OMAP24XX_GPIO_IRQENABLE1); - __raw_writel(0xffffffff, bank->base + - OMAP24XX_GPIO_IRQSTATUS1); - __raw_writew(0x0015, bank->base + - OMAP24XX_GPIO_SYSCONFIG); - __raw_writel(0x00000000, bank->base + - OMAP24XX_GPIO_DEBOUNCE_EN); - - /* - * Initialize interface clock ungated, - * module enabled - */ - __raw_writel(0, bank->base + - OMAP24XX_GPIO_CTRL); - } - if (cpu_is_omap24xx() && - i < ARRAY_SIZE(non_wakeup_gpios)) - bank->non_wakeup_gpios = non_wakeup_gpios[i]; - gpio_count = 32; - } -#endif - - bank->mod_usage = 0; - /* REVISIT eventually switch from OMAP-specific gpio structs - * over to the generic ones - */ - bank->chip.request = omap_gpio_request; - bank->chip.free = omap_gpio_free; - bank->chip.direction_input = gpio_input; - bank->chip.get = gpio_get; - bank->chip.direction_output = gpio_output; - bank->chip.set_debounce = gpio_debounce; - bank->chip.set = gpio_set; - bank->chip.to_irq = gpio_2irq; - if (bank_is_mpuio(bank)) { - bank->chip.label = "mpuio"; -#ifdef CONFIG_ARCH_OMAP16XX - bank->chip.dev = &omap_mpuio_device.dev; -#endif - bank->chip.base = OMAP_MPUIO(0); - } else { - bank->chip.label = "gpio"; - bank->chip.base = gpio; - gpio += gpio_count; - } - bank->chip.ngpio = gpio_count; - - gpiochip_add(&bank->chip); - - for (j = bank->virtual_irq_start; - j < bank->virtual_irq_start + gpio_count; j++) { - lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); - set_irq_chip_data(j, bank); - if (bank_is_mpuio(bank)) - set_irq_chip(j, &mpuio_irq_chip); - else - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_simple_irq); - set_irq_flags(j, IRQF_VALID); - } - set_irq_chained_handler(bank->irq, gpio_irq_handler); - set_irq_data(bank->irq, bank); + omap_gpio_mod_init(bank, i); + omap_gpio_chip_init(bank); if (cpu_is_omap34xx() || cpu_is_omap44xx()) { sprintf(clk_name, "gpio%d_dbck", i + 1); @@ -1943,17 +1959,6 @@ static int __init _omap_gpio_init(void) } } - /* Enable system clock for GPIO module. - * The CAM_CLK_CTRL *is* really the right place. */ - if (cpu_is_omap16xx()) - omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); - - /* Enable autoidle for the OCP interface */ - if (cpu_is_omap24xx()) - omap_writel(1 << 0, 0x48019010); - if (cpu_is_omap34xx()) - omap_writel(1 << 0, 0x48306814); - omap_gpio_show_rev(); return 0; From patchwork Thu Jul 29 09:58:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 115033 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6TA56aS005543 for ; Thu, 29 Jul 2010 10:07:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756496Ab0G2KBK (ORCPT ); Thu, 29 Jul 2010 06:01:10 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59290 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756400Ab0G2KBC (ORCPT ); Thu, 29 Jul 2010 06:01:02 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6TA0tF5008949 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Jul 2010 05:00:58 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6TA0qYg006167; Thu, 29 Jul 2010 15:30:53 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Benoit Cousson , Kevin Hilman , Paul Walmsley , Tony Lindgren , Anand Sawant , Santosh Shilimkar , Rajendra Nayak , Basak Partha , Charulatha V Subject: [PATCH 01/11] OMAP: DMA: Introduce DMA device attributes Date: Thu, 29 Jul 2010 15:28:55 +0530 Message-Id: <1280397545-27323-2-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280397545-27323-1-git-send-email-manjugk@ti.com> References: <1280397545-27323-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 29 Jul 2010 10:07:42 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 02232ca..ff60f11 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -398,6 +398,22 @@ #define DMA_CH_PRIO_HIGH 0x1 #define DMA_CH_PRIO_LOW 0x0 /* Def */ +/* Attributes for OMAP DMA Contrllers */ +#define ENABLE_1510_MODE (1 << 0) +#define DMA_LINKED_LCH (1 << 1) +#define GLOBAL_PRIORITY (1 << 2) +#define RESERVE_CHANNEL (1 << 3) +#define SRC_PORT (2 << 3) +#define DST_PORT (2 << 4) +#define IS_CSSA_32 (2 << 5) +#define IS_CDSA_32 (2 << 6) +#define SRC_INDEX (4 << 6) +#define DST_INDEX (4 << 7) +#define IS_BURST_ONLY4 (4 << 8) +#define CLEAR_CSR_ON_READ (4 << 9) +#define IS_WORD_16 (8 << 9) +#define IS_RW_PRIORIY (8 << 0xA) + enum omap_dma_burst_mode { OMAP_DMA_DATA_BURST_DIS = 0, OMAP_DMA_DATA_BURST_4, @@ -463,6 +479,12 @@ struct omap_dma_channel_params { #endif }; +struct omap_dma_dev_attr { + u32 dma_dev_attr; + u16 dma_lch_count; + u16 dma_chan_count; + struct omap_dma_lch *dma_chan; +}; extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, From patchwork Thu Jul 29 09:59:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 115032 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6TA56aQ005543 for ; Thu, 29 Jul 2010 10:06:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756544Ab0G2KBM (ORCPT ); Thu, 29 Jul 2010 06:01:12 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59300 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756418Ab0G2KBE (ORCPT ); Thu, 29 Jul 2010 06:01:04 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6TA0vkI008958 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Jul 2010 05:00:59 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6TA0qYo006167; Thu, 29 Jul 2010 15:30:55 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Benoit Cousson , Kevin Hilman , Paul Walmsley , Tony Lindgren , Anand Sawant , Santosh Shilimkar , Rajendra Nayak , Basak Partha , Charulatha V Subject: [PATCH 09/11] OMAP: DMA: Implement generic errata handling Date: Thu, 29 Jul 2010 15:29:03 +0530 Message-Id: <1280397545-27323-10-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1280397545-27323-1-git-send-email-manjugk@ti.com> References: <1280397545-27323-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 29 Jul 2010 10:06:34 +0000 (UTC) diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 0df2b82..00ef40f 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -170,6 +170,12 @@ static int __init omap1_system_dma_init(void) goto exit_device_put; } + /* Errata handling for all omap1 plus processors */ + pdata->errata = 0; + + if (cpu_class_is_omap1() && !cpu_is_omap15xx()) + pdata->errata |= OMAP3_3_ERRATUM; + d = pdata->dma_attr; /* Valid attributes for omap1 plus processors */ diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index da76c34..72abfec 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -80,6 +80,40 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) pdata->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; + /* Handling Errata's for all OMAP2PLUS processors */ + pdata->errata = 0; + + if (cpu_is_omap242x() || + (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) + pdata->errata = DMA_CHAINING_ERRATA; + + /* + * Errata: On ES2.0 BUFFERING disable must be set. + * This will always fail on ES1.0 + */ + if (cpu_is_omap24xx()) + pdata->errata |= DMA_BUFF_DISABLE_ERRATA; + + /* + * Errata: OMAP2: sDMA Channel is not disabled + * after a transaction error. So we explicitely + * disable the channel + */ + if (cpu_class_is_omap2()) + pdata->errata |= DMA_CH_DISABLE_ERRATA; + + /* Errata: OMAP3 : + * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared + * after secure sram context save and restore. Hence we need to + * manually clear those IRQs to avoid spurious interrupts. This + * affects only secure devices. + */ + if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + pdata->errata |= DMA_IRQ_STATUS_ERRATA; + + /* Errata3.3: Applicable for all omap2 plus */ + pdata->errata |= OMAP3_3_ERRATUM; + od = omap_device_build(name, 0, oh, pdata, sizeof(*pdata), omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 4627e84..b31c88f 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -182,6 +182,25 @@ static inline void set_gdma_dev(int req, int dev) #define set_gdma_dev(req, dev) do {} while (0) #endif +static void dma_ocpsysconfig_errata(u32 *sys_cf, bool flag) +{ + u32 l; + + /* + * DMA Errata: + * Special programming model needed to disable DMA before end of block + */ + if (!flag) { + *sys_cf = dma_read(OCP_SYSCONFIG); + l = *sys_cf; + /* Middle mode reg set no Standby */ + l &= ~((1 << 12)|(1 << 13)); + dma_write(l, OCP_SYSCONFIG); + } else + /* put back old value */ + dma_write(*sys_cf, OCP_SYSCONFIG); +} + /* Omap1 only */ static void clear_lch_regs(int lch) { @@ -958,22 +977,16 @@ void omap_start_dma(int lch) cur_lch = next_lch; } while (next_lch != -1); - } else if (cpu_is_omap242x() || - (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) { + } - /* Errata: Need to write lch even if not using chaining */ + if (p->errata & DMA_CHAINING_ERRATA) dma_write(lch, CLNK_CTRL(lch)); - } omap_enable_channel_irq(lch); l = dma_read(CCR(lch)); - /* - * Errata: On ES2.0 BUFFERING disable must be set. - * This will always fail on ES1.0 - */ - if (cpu_is_omap24xx()) + if (p->errata & DMA_BUFF_DISABLE_ERRATA) l |= OMAP_DMA_CCR_EN; l |= OMAP_DMA_CCR_EN; @@ -1647,7 +1660,7 @@ int omap_stop_dma_chain_transfers(int chain_id) { int *channels; u32 l, i; - u32 sys_cf; + u32 get_sysconfig; /* Check for input params */ if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { @@ -1662,15 +1675,8 @@ int omap_stop_dma_chain_transfers(int chain_id) } channels = dma_linked_lch[chain_id].linked_dmach_q; - /* - * DMA Errata: - * Special programming model needed to disable DMA before end of block - */ - sys_cf = dma_read(OCP_SYSCONFIG); - l = sys_cf; - /* Middle mode reg set no Standby */ - l &= ~((1 << 12)|(1 << 13)); - dma_write(l, OCP_SYSCONFIG); + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, false); for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { @@ -1689,8 +1695,8 @@ int omap_stop_dma_chain_transfers(int chain_id) /* Reset the Queue pointers */ OMAP_DMA_CHAIN_QINIT(chain_id); - /* Errata - put in the old value */ - dma_write(sys_cf, OCP_SYSCONFIG); + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, true); return 0; } diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 92c348f..6d1fee0 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -268,6 +268,14 @@ #define IS_WORD_16 (8 << 9) #define IS_RW_PRIORIY (8 << 0xA) +/* Errata Definitions */ +#define DMA_CHAINING_ERRATA (1 << 0) +#define DMA_BUFF_DISABLE_ERRATA (1 << 1) +#define OMAP3_3_ERRATUM (1 << 2) +#define DMA_SYSCONFIG_ERRATA (1 << 3) +#define DMA_CH_DISABLE_ERRATA (1 << 4) +#define DMA_IRQ_STATUS_ERRATA (1 << 5) + enum omap_dma_burst_mode { OMAP_DMA_DATA_BURST_DIS = 0, OMAP_DMA_DATA_BURST_4, @@ -345,6 +353,7 @@ struct omap_dma_dev_attr { struct omap_system_dma_plat_info { struct omap_dma_dev_attr *dma_attr; void __iomem *omap_dma_base; + u32 errata; }; extern void omap_set_dma_priority(int lch, int dst_port, int priority); From patchwork Fri Jul 9 22:48:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111141 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o69MoQZR001926 for ; Fri, 9 Jul 2010 22:50:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754662Ab0GIWuE (ORCPT ); Fri, 9 Jul 2010 18:50:04 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:48653 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753636Ab0GIWuC (ORCPT ); Fri, 9 Jul 2010 18:50:02 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o69MntF3027742 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 17:49:56 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o69Mnsbp012832; Fri, 9 Jul 2010 17:49:55 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o69MnmLv027224; Fri, 9 Jul 2010 17:49:49 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, andy.shevchenko@gmail.com, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH] staging: ti dspbridge: fix compilation error Date: Fri, 9 Jul 2010 17:48:52 -0500 Message-Id: <1278715732-21167-1-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 09 Jul 2010 22:50:26 +0000 (UTC) This patch fix a compilation error in uuid_hex_to_bin due to the patch "simplify and clean up" Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/gen/uuidutil.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) mode change 100644 => 100755 drivers/staging/tidspbridge/gen/uuidutil.c diff --git a/drivers/staging/tidspbridge/gen/uuidutil.c b/drivers/staging/tidspbridge/gen/uuidutil.c index eb09bc3..070761b --- a/drivers/staging/tidspbridge/gen/uuidutil.c +++ b/drivers/staging/tidspbridge/gen/uuidutil.c @@ -58,6 +58,7 @@ static s32 uuid_hex_to_bin(char *buf, s32 len) { s32 i; s32 result = 0; + int value; for (i = 0; i < len; i++) { value = hex_to_bin(*buf++); From patchwork Fri Jul 9 23:17:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gadiyar X-Patchwork-Id: 111147 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o69NHrsp006752 for ; Fri, 9 Jul 2010 23:17:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755118Ab0GIXRw (ORCPT ); Fri, 9 Jul 2010 19:17:52 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:49516 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754745Ab0GIXRw (ORCPT ); Fri, 9 Jul 2010 19:17:52 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o69NHmuP029228 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 18:17:50 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o69NHgm2005389; Sat, 10 Jul 2010 04:47:43 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o69NHgKA005639; Sat, 10 Jul 2010 04:47:42 +0530 Received: (from a0393673@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o69NHf3u005634; Sat, 10 Jul 2010 04:47:41 +0530 From: Anand Gadiyar To: linux-omap@vger.kernel.org Cc: Anand Gadiyar , Nishanth Menon , Manjunatha GK , Tony Lindgren Subject: [PATCH] OMAP3630: Add ES1.1 and ES1.2 detection Date: Sat, 10 Jul 2010 04:47:41 +0530 Message-Id: <1278717461-5329-1-git-send-email-gadiyar@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <20100709072941.GG24913@atomide.com> References: <20100709072941.GG24913@atomide.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 09 Jul 2010 23:18:34 +0000 (UTC) Add revision detection for ES1.1 and ES1.2. Set default revision as ES1.2. Add CHIP_GE_OMAP3630ES1_1 to detect revisions 1.1 and later. This is needed for at least one feature that is broken in 3630ES1.0 but exists on older (3430 ES3.1) and newer revisions. Additionally, update some of the CHIP_GE_* macros to use other macros for ease of maintenance. Signed-off-by: Anand Gadiyar Cc: Nishanth Menon Cc: Manjunatha GK Cc: Tony Lindgren --- This is based on Manju's original patch at [1] and my update [2]. The original patch failed to properly update the CHIP_GE_OMAP3630ES1 macro. Would be nice to get this queued for the next merge window [1] https://patchwork.kernel.org/patch/95684/ [2] https://patchwork.kernel.org/patch/99590/ arch/arm/mach-omap2/id.c | 27 +++++++++++++++++++++++---- arch/arm/plat-omap/include/plat/cpu.h | 15 +++++++++++---- 2 files changed, 34 insertions(+), 8 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-omap-2.6/arch/arm/mach-omap2/id.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/id.c +++ linux-omap-2.6/arch/arm/mach-omap2/id.c @@ -269,11 +269,24 @@ void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; break; case 0xb891: - /* FALLTHROUGH */ - default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; + /* Handle 36xx devices */ omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + break; + case 2: + /* Fall through */ + default: + /* Use the latest known revision as default */ + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + } } } @@ -349,6 +362,12 @@ void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; Index: linux-omap-2.6/arch/arm/plat-omap/include/plat/cpu.h =================================================================== --- linux-omap-2.6.orig/arch/arm/plat-omap/include/plat/cpu.h +++ linux-omap-2.6/arch/arm/plat-omap/include/plat/cpu.h @@ -66,6 +66,8 @@ unsigned int omap_rev(void); * family. This difference can be handled separately. */ #define OMAP_REVBITS_00 0x00 +#define OMAP_REVBITS_01 0x01 +#define OMAP_REVBITS_02 0x02 #define OMAP_REVBITS_10 0x10 #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 @@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3430_REV_ES3_1_2 0x34305034 #define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 +#define OMAP3630_REV_ES1_2 0x36300234 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) #define CHIP_IS_OMAP4430ES1 (1 << 8) +#define CHIP_IS_OMAP3630ES1_1 (1 << 9) +#define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517) */ #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ CHIP_IS_OMAP3430ES3_0 | \ - CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) + CHIP_GE_OMAP3430ES3_1) #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) - + CHIP_IS_OMAP3630ES1 | \ + CHIP_GE_OMAP3630ES1_1) +#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ + CHIP_IS_OMAP3630ES1_2) int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); From patchwork Wed Jul 21 17:33:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113419 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHZI5h008223 for ; Wed, 21 Jul 2010 17:35:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758684Ab0GURfP (ORCPT ); Wed, 21 Jul 2010 13:35:15 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758499Ab0GURfG (ORCPT ); Wed, 21 Jul 2010 13:35:06 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:35:05 -0700 (PDT) Received: by 10.204.34.133 with SMTP id l5mr293679bkd.180.1279733704858; Wed, 21 Jul 2010 10:35:04 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.35.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:35:04 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 12/20] omap: hsmmc: allow board-specific settings of private mmc data Date: Wed, 21 Jul 2010 20:33:46 +0300 Message-Id: <1279733634-21974-13-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:18 +0000 (UTC) diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 5d3d789..f06ddd2 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -284,6 +284,8 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) if (c->vcc_aux_disable_is_sleep) mmc->slots[0].vcc_aux_disable_is_sleep = 1; + mmc->slots[0].priv_data = c->priv_data; + /* NOTE: MMC slots should have a Vcc regulator set up. * This may be from a TWL4030-family chip, another * controllable regulator, or a fixed supply. diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8..434a3ed 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -23,6 +23,7 @@ struct omap2_hsmmc_info { int ocr_mask; /* temporary HACK */ /* Remux (pad configuation) when powering on/off */ void (*remux)(struct device *dev, int slot, int power_on); + void *priv_data; /* private data to SDIO function driver */ }; #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index c835f1e..9db1617 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -140,6 +140,8 @@ struct omap_mmc_platform_data { unsigned int ban_openended:1; + /* card private data that should be used by function driver */ + void *priv_data; } slots[OMAP_MMC_MAX_SLOTS]; }; diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 4c5a669..4ac548e 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2157,6 +2157,8 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) if (mmc_slot(host).nonremovable) mmc->caps |= MMC_CAP_NONREMOVABLE; + mmc_set_embedded_data(mmc, mmc_slot(host).priv_data); + omap_hsmmc_conf_bus_power(host); /* Select DMA lines */ From patchwork Mon May 10 19:55:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkatraman S X-Patchwork-Id: 98268 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4AJuJe8015780 for ; Mon, 10 May 2010 19:57:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756273Ab0EJTzI (ORCPT ); Mon, 10 May 2010 15:55:08 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:59349 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755717Ab0EJTzH (ORCPT ); Mon, 10 May 2010 15:55:07 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4AJt0nw007356 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 May 2010 14:55:00 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4AJsune022538; Mon, 10 May 2010 14:54:56 -0500 (CDT) Received: from localhost (a0393540pc.apr.dhcp.ti.com [172.24.137.124]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o4AJsrP13528; Mon, 10 May 2010 14:54:53 -0500 (CDT) From: Venkatraman S To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Venkatraman S , Nishant Menon , Tony Lindgren , Madhusudhan Chikkature Subject: [PATCH RESEND] update omap3 features bitmap and API to generic names Date: Tue, 11 May 2010 01:25:38 +0530 Message-Id: <1273521338-2896-1-git-send-email-svenkatr@ti.com> X-Mailer: git-send-email 1.6.3.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 10 May 2010 19:58:37 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 9cba556..afa481d 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3510,7 +3510,7 @@ int __init omap3xxx_clk_init(void) cpu_clkflg |= CK_3430ES2; } } - if (omap3_has_192mhz_clk()) + if (omap_has_192mhz_clk()) omap_96m_alwon_fck = omap_96m_alwon_fck_3630; if (cpu_is_omap3630()) { diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a..a095b87 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -28,7 +28,7 @@ static struct omap_chip_id omap_chip; static unsigned int omap_revision; -u32 omap3_features; +u32 omap_features; unsigned int omap_rev(void) { @@ -161,14 +161,14 @@ void __init omap24xx_check_revision(void) #define OMAP3_CHECK_FEATURE(status,feat) \ if (((status & OMAP3_ ##feat## _MASK) \ >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ - omap3_features |= OMAP3_HAS_ ##feat; \ + omap_features |= OMAP_HAS_ ##feat; \ } void __init omap3_check_features(void) { u32 status; - omap3_features = 0; + omap_features = 0; status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); @@ -178,7 +178,7 @@ void __init omap3_check_features(void) OMAP3_CHECK_FEATURE(status, NEON); OMAP3_CHECK_FEATURE(status, ISP); if (cpu_is_omap3630()) - omap3_features |= OMAP3_HAS_192MHZ_CLK; + omap_features |= OMAP_HAS_192MHZ_CLK; /* * TODO: Get additional info (where applicable) @@ -294,7 +294,7 @@ void __init omap4_check_revision(void) } #define OMAP3_SHOW_FEATURE(feat) \ - if (omap3_has_ ##feat()) \ + if (omap_has_ ##feat()) \ printk(#feat" "); void __init omap3_cpuinfo(void) @@ -314,20 +314,20 @@ void __init omap3_cpuinfo(void) /* * AM35xx devices */ - if (omap3_has_sgx()) { + if (omap_has_sgx()) { omap_revision = OMAP3517_REV(rev); strcpy(cpu_name, "AM3517"); } else { /* Already set in omap3_check_revision() */ strcpy(cpu_name, "AM3505"); } - } else if (omap3_has_iva() && omap3_has_sgx()) { + } else if (omap_has_iva() && omap_has_sgx()) { /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ strcpy(cpu_name, "OMAP3430/3530"); - } else if (omap3_has_iva()) { + } else if (omap_has_iva()) { omap_revision = OMAP3525_REV(rev); strcpy(cpu_name, "OMAP3525"); - } else if (omap3_has_sgx()) { + } else if (omap_has_sgx()) { omap_revision = OMAP3515_REV(rev); strcpy(cpu_name, "OMAP3515"); } else { diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 7514174..80dc8e0 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -434,28 +434,28 @@ int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); /* - * Runtime detection of OMAP3 features + * Runtime detection of OMAP features */ -extern u32 omap3_features; +extern u32 omap_features; -#define OMAP3_HAS_L2CACHE BIT(0) -#define OMAP3_HAS_IVA BIT(1) -#define OMAP3_HAS_SGX BIT(2) -#define OMAP3_HAS_NEON BIT(3) -#define OMAP3_HAS_ISP BIT(4) -#define OMAP3_HAS_192MHZ_CLK BIT(5) +#define OMAP_HAS_L2CACHE BIT(0) +#define OMAP_HAS_IVA BIT(1) +#define OMAP_HAS_SGX BIT(2) +#define OMAP_HAS_NEON BIT(3) +#define OMAP_HAS_ISP BIT(4) +#define OMAP_HAS_192MHZ_CLK BIT(5) -#define OMAP3_HAS_FEATURE(feat,flag) \ -static inline unsigned int omap3_has_ ##feat(void) \ +#define OMAP_HAS_FEATURE(feat, flag) \ +static inline unsigned int omap_has_ ##feat(void) \ { \ - return (omap3_features & OMAP3_HAS_ ##flag); \ + return (omap_features & OMAP_HAS_ ##flag); \ } \ -OMAP3_HAS_FEATURE(l2cache, L2CACHE) -OMAP3_HAS_FEATURE(sgx, SGX) -OMAP3_HAS_FEATURE(iva, IVA) -OMAP3_HAS_FEATURE(neon, NEON) -OMAP3_HAS_FEATURE(isp, ISP) -OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) +OMAP_HAS_FEATURE(l2cache, L2CACHE) +OMAP_HAS_FEATURE(sgx, SGX) +OMAP_HAS_FEATURE(iva, IVA) +OMAP_HAS_FEATURE(neon, NEON) +OMAP_HAS_FEATURE(isp, ISP) +OMAP_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) #endif From patchwork Wed Jul 21 17:33:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113418 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHZI5g008223 for ; Wed, 21 Jul 2010 17:35:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758653Ab0GURfM (ORCPT ); Wed, 21 Jul 2010 13:35:12 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758554Ab0GURfJ (ORCPT ); Wed, 21 Jul 2010 13:35:09 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:35:08 -0700 (PDT) Received: by 10.204.163.84 with SMTP id z20mr319352bkx.184.1279733708463; Wed, 21 Jul 2010 10:35:08 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.35.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:35:07 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 13/20] omap: zoom: add mmc3/wl1271 device support Date: Wed, 21 Jul 2010 20:33:47 +0300 Message-Id: <1279733634-21974-14-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:18 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 2fc0f4a..3230801 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include @@ -29,6 +31,7 @@ #include "hsmmc.h" #define OMAP_ZOOM_WLAN_PMENA_GPIO (101) +#define OMAP_ZOOM_WLAN_IRQ_GPIO (162) /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { @@ -184,6 +187,12 @@ static struct platform_device omap_vwlan_device = { }, }; +struct wl12xx_platform_data omap_zoom_wlan_data = { + .irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO), + /* ZOOM ref clock is 26 MHz */ + .board_ref_clock = 1, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -201,6 +210,15 @@ static struct omap2_hsmmc_info mmc[] __initdata = { .nonremovable = true, .power_saving = true, }, + { + .name = "wl1271", + .mmc = 3, + .wires = 4, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .ocr_mask = MMC_VDD_165_195, + .priv_data = &omap_zoom_wlan_data, + }, {} /* Terminator */ }; @@ -217,6 +235,7 @@ static int zoom_twl_gpio_setup(struct device *dev, zoom_vmmc1_supply.dev = mmc[0].dev; zoom_vsim_supply.dev = mmc[0].dev; zoom_vmmc2_supply.dev = mmc[1].dev; + zoom_vmmc3_supply.dev = mmc[2].dev; return 0; } From patchwork Wed May 26 06:53:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 102338 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4Q6sWjs002713 for ; Wed, 26 May 2010 06:54:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934212Ab0EZGyb (ORCPT ); Wed, 26 May 2010 02:54:31 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50147 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934200Ab0EZGya convert rfc822-to-8bit (ORCPT ); Wed, 26 May 2010 02:54:30 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4Q6rtuZ016633 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 26 May 2010 01:53:57 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4Q6rpjg008858; Wed, 26 May 2010 12:23:52 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Wed, 26 May 2010 12:23:51 +0530 From: "Gupta, Ajay Kumar" To: "felipe.balbi@nokia.com" CC: Amit Kucheria , Kevin Hilman , "me@felipebalbi.com" , "linux-omap@vger.kernel.org" , "tony@atomide.com" Date: Wed, 26 May 2010 12:23:50 +0530 Subject: RE: usb_nop_xceiv_register() missing when OTG built as modules Thread-Topic: usb_nop_xceiv_register() missing when OTG built as modules Thread-Index: Acr8mTOFsLzTuDYeQQeiQ/5YXgktKwABqg4A Message-ID: <19F8576C6E063C45BE387C64729E7394044E616B60@dbde02.ent.ti.com> References: <87635d54nn.fsf@deeprootsystems.com> <19F8576C6E063C45BE387C64729E7394044DB7B6BD@dbde02.ent.ti.com> <87eik03scn.fsf@deeprootsystems.com> <20100305090426.GG12757@nokia.com> <871vfy3azr.fsf@deeprootsystems.com> <558f5bffd42210a777154737d6730232@secure211.sgcpanel.com> <87y6i6zatj.fsf@deeprootsystems.com> <20100522235310.GA15859@matterhorn.lan> <19F8576C6E063C45BE387C64729E7394044E61643A@dbde02.ent.ti.com> <20100526060321.GE3069@nokia.com> In-Reply-To: <20100526060321.GE3069@nokia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 26 May 2010 06:54:32 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 77af4c9..fb29837 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -137,6 +137,7 @@ static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, .mode = MUSB_PERIPHERAL, .power = 100, + .neednop = 1, }; static struct omap2_hsmmc_info mmc[] = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 83d3aa5..609f021 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -665,6 +665,7 @@ static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_ULPI, .mode = MUSB_OTG, .power = 100, + .neednop = 1, }; static void __init omap3_evm_init(void) diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index a32d3af..b53489a 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -69,6 +69,7 @@ struct omap_musb_board_data { u8 mode; u16 power; unsigned extvbus:1; + unsigned neednop:1; /* NOP transceiver */ }; enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index e71049c..b774312 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -1964,6 +1964,7 @@ bad_config: musb->board_set_power = plat->set_power; musb->set_clock = plat->set_clock; musb->min_power = plat->min_power; + musb->board_data = plat->board_data; /* Clock usage is chip-specific ... functional clock (DaVinci, * OMAP2430), or PHY ref (some TUSB6010 boards). All this core diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index eaabf98..b72e2e5 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -392,6 +392,7 @@ struct musb { int (*board_set_power)(int state); int (*set_clock)(struct clk *clk, int is_active); + void *board_data; u8 min_power; /* vbus for periph, in mA/2 */ diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index 58acd0c..8488a23 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -198,12 +198,11 @@ int __init musb_platform_init(struct musb *musb, void *board_data) omap_cfg_reg(AE5_2430_USB0HS_STP); #endif -#if defined(CONFIG_MACH_OMAP3EVM) || defined(CONFIG_MACH_OMAP_4430SDP) /* OMAP3EVM used ISP150x and OMAP4 SDP uses internal transceiver * so register nop transceiver */ - usb_nop_xceiv_register(); -#endif + if (data->neednop) + usb_nop_xceiv_register(); /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, @@ -330,10 +329,10 @@ static int musb_platform_resume(struct musb *musb) int musb_platform_exit(struct musb *musb) { + struct omap_musb_board_data *data = musb->board_data; musb_platform_suspend(musb); -#if defined(CONFIG_MACH_OMAP3EVM) || defined(CONFIG_MACH_OMAP_4430SDP) - usb_nop_xceiv_unregister(); -#endif + if (data->neednop) + usb_nop_xceiv_unregister(); return 0; } From patchwork Fri Aug 6 15:55:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 117853 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o76FteIM020143 for ; Fri, 6 Aug 2010 15:55:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761544Ab0HFPzg (ORCPT ); Fri, 6 Aug 2010 11:55:36 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:36337 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754948Ab0HFPzf (ORCPT ); Fri, 6 Aug 2010 11:55:35 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o76FtSxS029554 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Aug 2010 10:55:30 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o76FtOpm005315; Fri, 6 Aug 2010 21:25:25 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o76FtOcp003776; Fri, 6 Aug 2010 21:25:24 +0530 Received: (from a0876481@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o76FtOij003774; Fri, 6 Aug 2010 21:25:24 +0530 From: Hema HK To: linux-omap@vger.kernel.org, linux-usb@vger.kernel.org Cc: Hema HK , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH 1/8] usb: musb: Adding names for IRQs in resource structure Date: Fri, 6 Aug 2010 21:25:24 +0530 Message-Id: <1281110124-3186-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 15:55:41 +0000 (UTC) Index: linux-omap-pm/arch/arm/mach-davinci/usb.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-davinci/usb.c 2010-08-06 09:01:23.605862579 -0400 +++ linux-omap-pm/arch/arm/mach-davinci/usb.c 2010-08-06 09:01:25.526112352 -0400 @@ -64,10 +64,12 @@ { .start = IRQ_USBINT, .flags = IORESOURCE_IRQ, + .name = "mc" }, { /* placeholder for the dedicated CPPI IRQ */ .flags = IORESOURCE_IRQ, + .name = "dma" }, }; Index: linux-omap-pm/arch/arm/mach-omap2/usb-musb.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/usb-musb.c 2010-08-06 09:01:23.613862415 -0400 +++ linux-omap-pm/arch/arm/mach-omap2/usb-musb.c 2010-08-06 09:01:25.526112352 -0400 @@ -39,10 +39,12 @@ [1] = { /* general IRQ */ .start = INT_243X_HS_USB_MC, .flags = IORESOURCE_IRQ, + .name = "mc", }, [2] = { /* DMA IRQ */ .start = INT_243X_HS_USB_DMA, .flags = IORESOURCE_IRQ, + .name = "dma", }, }; Index: linux-omap-pm/arch/blackfin/mach-bf527/boards/cm_bf527.c =================================================================== --- linux-omap-pm.orig/arch/blackfin/mach-bf527/boards/cm_bf527.c 2010-08-06 09:01:23.645862783 -0400 +++ linux-omap-pm/arch/blackfin/mach-bf527/boards/cm_bf527.c 2010-08-06 09:01:25.526112352 -0400 @@ -82,11 +82,13 @@ .start = IRQ_USB_INT0, .end = IRQ_USB_INT0, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "mc" }, [2] = { /* DMA IRQ */ .start = IRQ_USB_DMA, .end = IRQ_USB_DMA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "dma" }, }; Index: linux-omap-pm/arch/blackfin/mach-bf527/boards/ezbrd.c =================================================================== --- linux-omap-pm.orig/arch/blackfin/mach-bf527/boards/ezbrd.c 2010-08-06 09:01:23.637862922 -0400 +++ linux-omap-pm/arch/blackfin/mach-bf527/boards/ezbrd.c 2010-08-06 09:01:25.526112352 -0400 @@ -46,11 +46,13 @@ .start = IRQ_USB_INT0, .end = IRQ_USB_INT0, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "mc" }, [2] = { /* DMA IRQ */ .start = IRQ_USB_DMA, .end = IRQ_USB_DMA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "dma" }, }; Index: linux-omap-pm/arch/blackfin/mach-bf527/boards/ezkit.c =================================================================== --- linux-omap-pm.orig/arch/blackfin/mach-bf527/boards/ezkit.c 2010-08-06 09:01:23.653862977 -0400 +++ linux-omap-pm/arch/blackfin/mach-bf527/boards/ezkit.c 2010-08-06 09:01:25.526112352 -0400 @@ -86,11 +86,13 @@ .start = IRQ_USB_INT0, .end = IRQ_USB_INT0, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "mc" }, [2] = { /* DMA IRQ */ .start = IRQ_USB_DMA, .end = IRQ_USB_DMA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "dma" }, }; Index: linux-omap-pm/arch/blackfin/mach-bf548/boards/cm_bf548.c =================================================================== --- linux-omap-pm.orig/arch/blackfin/mach-bf548/boards/cm_bf548.c 2010-08-06 09:01:23.625864028 -0400 +++ linux-omap-pm/arch/blackfin/mach-bf548/boards/cm_bf548.c 2010-08-06 09:01:25.526112352 -0400 @@ -482,11 +482,13 @@ .start = IRQ_USB_INT0, .end = IRQ_USB_INT0, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "mc" }, [2] = { /* DMA IRQ */ .start = IRQ_USB_DMA, .end = IRQ_USB_DMA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "dma" }, }; Index: linux-omap-pm/arch/blackfin/mach-bf548/boards/ezkit.c =================================================================== --- linux-omap-pm.orig/arch/blackfin/mach-bf548/boards/ezkit.c 2010-08-06 09:01:23.629863856 -0400 +++ linux-omap-pm/arch/blackfin/mach-bf548/boards/ezkit.c 2010-08-06 09:01:25.530112841 -0400 @@ -587,11 +587,13 @@ .start = IRQ_USB_INT0, .end = IRQ_USB_INT0, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "mc" }, [2] = { /* DMA IRQ */ .start = IRQ_USB_DMA, .end = IRQ_USB_DMA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "dma" }, }; Index: linux-omap-pm/drivers/usb/musb/cppi_dma.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/cppi_dma.c 2010-08-06 09:01:23.589863406 -0400 +++ linux-omap-pm/drivers/usb/musb/cppi_dma.c 2010-08-06 09:01:25.530112841 -0400 @@ -1307,7 +1307,7 @@ struct cppi *controller; struct device *dev = musb->controller; struct platform_device *pdev = to_platform_device(dev); - int irq = platform_get_irq(pdev, 1); + int irq = platform_get_irq_byname(pdev, "dma"); controller = kzalloc(sizeof *controller, GFP_KERNEL); if (!controller) Index: linux-omap-pm/drivers/usb/musb/musb_core.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/musb_core.c 2010-08-06 09:01:23.585862534 -0400 +++ linux-omap-pm/drivers/usb/musb/musb_core.c 2010-08-06 09:01:25.530112841 -0400 @@ -2204,7 +2204,7 @@ static int __init musb_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - int irq = platform_get_irq(pdev, 0); + int irq = platform_get_irq_byname(pdev, "mc"); int status; struct resource *iomem; void __iomem *base; Index: linux-omap-pm/drivers/usb/musb/musbhsdma.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/musbhsdma.c 2010-08-06 09:01:23.597862505 -0400 +++ linux-omap-pm/drivers/usb/musb/musbhsdma.c 2010-08-06 09:01:25.530112841 -0400 @@ -366,7 +366,7 @@ struct musb_dma_controller *controller; struct device *dev = musb->controller; struct platform_device *pdev = to_platform_device(dev); - int irq = platform_get_irq(pdev, 1); + int irq = platform_get_irq_byname(pdev, "dma"); if (irq == 0) { dev_err(dev, "No DMA interrupt line!\n"); From patchwork Mon May 24 13:43:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindraj.R" X-Patchwork-Id: 101874 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4ODhJBU015222 for ; Mon, 24 May 2010 13:43:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757058Ab0EXNnQ (ORCPT ); Mon, 24 May 2010 09:43:16 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:60753 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757041Ab0EXNnO (ORCPT ); Mon, 24 May 2010 09:43:14 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4ODhCgi000675 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 24 May 2010 08:43:12 -0500 Received: from webmail.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4ODh7w9002238; Mon, 24 May 2010 08:43:09 -0500 (CDT) Received: from 192.168.10.88 (proxying for 10.24.255.18) (SquirrelMail authenticated user x0100947); by dbdmail.itg.ti.com with HTTP; Mon, 24 May 2010 19:13:10 +0530 (IST) Message-ID: <58269.192.168.10.88.1274708590.squirrel@dbdmail.itg.ti.com> Date: Mon, 24 May 2010 19:13:10 +0530 (IST) Subject: [PATCH v2] serial: Add OMAP high-speed UART driver From: "Govindraj.R" To: linux-omap@vger.kernel.org, linux-serial@vger.kernel.org Cc: "Kevin Hilman" , "Tony Lindgren" User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 24 May 2010 13:43:20 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h new file mode 100644 index 0000000..0d6f076 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -0,0 +1,129 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __OMAP_SERIAL_H__ +#define __OMAP_SERIAL_H__ + +#include +#include + +#include +#include + +#define DRIVER_NAME "omap-hsuart" + +/* + * Use tty device name as ttyO, [O -> OMAP] + * in bootargs we specify as console=ttyO0 if uart1 + * is used as console uart. + */ +#define OMAP_SERIAL_NAME "ttyO" + +#define OMAP_MDR1_DISABLE 0x07 +#define OMAP_MDR1_MODE13X 0x03 +#define OMAP_MDR1_MODE16X 0x00 +#define OMAP_MODE13X_SPEED 230400 + +/* + * LCR = 0XBF: Switch to Configuration Mode B. + * In configuration mode b allow access + * to EFR,DLL,DLH. + * Reference OMAP TRM Chapter 17 + * Section: 1.4.3 Mode Selection + */ +#define OMAP_UART_LCR_CONF_MDB 0XBF + +/* WER = 0x7F + * Enable module level wakeup in WER reg + */ +#define OMAP_UART_WER_MOD_WKUP 0X7F + +/* Enable XON/XOFF flow control on output */ +#define OMAP_UART_SW_TX 0x04 + +/* Enable XON/XOFF flow control on input */ +#define OMAP_UART_SW_RX 0x04 + +#define OMAP_UART_SYSC_RESET 0X07 +#define OMAP_UART_TCR_TRIG 0X0F +#define OMAP_UART_SW_CLR 0XF0 +#define OMAP_UART_FIFO_CLR 0X06 + +#define OMAP_UART_DMA_CH_FREE -1 + +#define RX_TIMEOUT (3 * HZ) +#define OMAP_MAX_HSUART_PORTS 4 + +#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA + +struct omap_uart_port_info { + bool dma_enabled; /* To specify DMA Mode */ + unsigned int uartclk; /* UART clock rate */ + void __iomem *membase; /* ioremap cookie or NULL */ + resource_size_t mapbase; /* resource base */ + unsigned long irqflags; /* request_irq flags */ + upf_t flags; /* UPF_* flags */ +}; + +struct uart_omap_dma { + u8 uart_dma_tx; + u8 uart_dma_rx; + int rx_dma_channel; + int tx_dma_channel; + dma_addr_t rx_buf_dma_phys; + dma_addr_t tx_buf_dma_phys; + unsigned int uart_base; + /* + * Buffer for rx dma.It is not required for tx because the buffer + * comes from port structure. + */ + unsigned char *rx_buf; + unsigned int prev_rx_dma_pos; + int tx_buf_size; + int tx_dma_used; + int rx_dma_used; + spinlock_t tx_lock; + spinlock_t rx_lock; + /* timer to poll activity on rx dma */ + struct timer_list rx_timer; + int rx_buf_size; + int rx_timeout; +}; + +struct uart_omap_port { + struct uart_port port; + struct uart_omap_dma uart_dma; + struct platform_device *pdev; + + unsigned char ier; + unsigned char lcr; + unsigned char mcr; + unsigned char fcr; + unsigned char efr; + + int use_dma; + /* + * Some bits in registers are cleared on a read, so they must + * be saved whenever the register is read but the bits will not + * be immediately processed. + */ + unsigned int lsr_break_flag; + unsigned char msr_saved_flags; + char name[20]; + unsigned long port_activity; +}; + +#endif /* __OMAP_SERIAL_H__ */ diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index f55c494..4346bfa 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1387,6 +1387,33 @@ config SERIAL_OF_PLATFORM Currently, only 8250 compatible ports are supported, but others can easily be added. +config SERIAL_OMAP + tristate "OMAP serial port support" + depends on ARCH_OMAP3 || ARCH_OMAP4 + select SERIAL_CORE + help + If you have a machine based on an Texas Instruments OMAP CPU you + can enable its onboard serial ports by enabling this option. + + By enabling this option you take advantage of dma feature available + with the omap-serial driver. DMA support can be enabled from platform + data. + +config SERIAL_OMAP_CONSOLE + bool "Console on OMAP serial port" + depends on SERIAL_OMAP + select SERIAL_CORE_CONSOLE + help + Select this option if you would like to use omap serial port as + console. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyOx". (Try "man bootparam" or see the documentation of + your boot loader about how to pass options to the kernel at + boot time.) + config SERIAL_OF_PLATFORM_NWPSERIAL tristate "NWP serial port driver" depends on PPC_OF && PPC_DCR diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6aa4723..87e4d7a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -83,3 +83,4 @@ obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o obj-$(CONFIG_SERIAL_QE) += ucc_uart.o obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o +obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o diff --git a/drivers/serial/omap-serial.c b/drivers/serial/omap-serial.c new file mode 100644 index 0000000..b40a911 --- /dev/null +++ b/drivers/serial/omap-serial.c @@ -0,0 +1,1318 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Note: This driver is made seperate from 8250 driver as we cannot + * over load 8250 driver with omap platform specific configuration for + * features like DMA, it makes easier to implement features like DMA and + * hardware flow control and software flow control configuration with + * this driver as required for the omap-platform. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; + +/* Forward declaration of functions */ +static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); +static void serial_omap_rx_timeout(unsigned long uart_no); +static int serial_omap_start_rxdma(struct uart_omap_port *up); + +static inline unsigned int serial_in(struct uart_omap_port *up, int offset) +{ + offset <<= up->port.regshift; + return readw(up->port.membase + offset); +} + +static inline void serial_out(struct uart_omap_port *up, int offset, int value) +{ + offset <<= up->port.regshift; + writew(value, up->port.membase + offset); +} + +static inline void serial_omap_clear_fifos(struct uart_omap_port *up) +{ + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + serial_out(up, UART_FCR, 0); +} + +/** + * serial_omap_get_divisor() - calculate divisor value + * @port: uart port info + * @baud: baudrate for which divisor needs to be calculated. + * + * We have written our own function to get the divisor so as to support + * 13x mode. 3Mbps Baudrate as an different divisor. + * Reference OMAP TRM Chapter 17: + * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates + * referring to oversampling - divisor value + * baudrate 460,800 to 3,686,400 all have divisor 13 + * except 3,000,000 which has divisor value 16 + */ +static unsigned int +serial_omap_get_divisor(struct uart_port *port, unsigned int baud) +{ + unsigned int divisor; + + if (baud > OMAP_MODE13X_SPEED && baud != 3000000) + divisor = 13; + else + divisor = 16; + return port->uartclk/(baud * divisor); +} + +static void serial_omap_stop_rxdma(struct uart_omap_port *up) +{ + if (up->uart_dma.rx_dma_used) { + del_timer(&up->uart_dma.rx_timer); + omap_stop_dma(up->uart_dma.rx_dma_channel); + omap_free_dma(up->uart_dma.rx_dma_channel); + up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; + up->uart_dma.rx_dma_used = false; + } +} + +static void serial_omap_enable_ms(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); + up->ier |= UART_IER_MSI; + serial_out(up, UART_IER, up->ier); +} + +static void serial_omap_stop_tx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + if (up->use_dma && + up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { + /* + * Check if dma is still active. If yes do nothing, + * return. Else stop dma + */ + if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) + return; + omap_stop_dma(up->uart_dma.tx_dma_channel); + omap_free_dma(up->uart_dma.tx_dma_channel); + up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; + } + + if (up->ier & UART_IER_THRI) { + up->ier &= ~UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serial_omap_stop_rx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + if (up->use_dma) + serial_omap_stop_rxdma(up); + up->ier &= ~UART_IER_RLSI; + up->port.read_status_mask &= ~UART_LSR_DR; + serial_out(up, UART_IER, up->ier); +} + +static inline void receive_chars(struct uart_omap_port *up, int *status) +{ + struct tty_struct *tty = up->port.state->port.tty; + unsigned int flag; + unsigned char ch, lsr = *status; + int max_count = 256; + + do { + if (likely(lsr & UART_LSR_DR)) + ch = serial_in(up, UART_RX); + flag = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { + /* + * For statistics only + */ + if (lsr & UART_LSR_BI) { + lsr &= ~(UART_LSR_FE | UART_LSR_PE); + up->port.icount.brk++; + /* + * We do the SysRQ and SAK checking + * here because otherwise the break + * may get masked by ignore_status_mask + * or read_status_mask. + */ + if (uart_handle_break(&up->port)) + goto ignore_char; + } else if (lsr & UART_LSR_PE) + up->port.icount.parity++; + else if (lsr & UART_LSR_FE) + up->port.icount.frame++; + if (lsr & UART_LSR_OE) + up->port.icount.overrun++; + + /* + * Mask off conditions which should be ignored. + */ + lsr &= up->port.read_status_mask; + +#ifdef CONFIG_SERIAL_OMAP_CONSOLE + if (up->port.line == up->port.cons->index) { + /* Recover the break flag from console xmit */ + lsr |= up->lsr_break_flag; + up->lsr_break_flag = 0; + } +#endif + if (lsr & UART_LSR_BI) + flag = TTY_BREAK; + else if (lsr & UART_LSR_PE) + flag = TTY_PARITY; + else if (lsr & UART_LSR_FE) + flag = TTY_FRAME; + } + + if (uart_handle_sysrq_char(&up->port, ch)) + goto ignore_char; + uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); +ignore_char: + lsr = serial_in(up, UART_LSR); + } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); + spin_unlock(&up->port.lock); + tty_flip_buffer_push(tty); + spin_lock(&up->port.lock); +} + +static void transmit_chars(struct uart_omap_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count; + + if (up->port.x_char) { + serial_out(up, UART_TX, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { + serial_omap_stop_tx(&up->port); + return; + } + count = up->port.fifosize / 4; + do { + serial_out(up, UART_TX, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (uart_circ_empty(xmit)) + serial_omap_stop_tx(&up->port); +} + +static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) +{ + if (!(up->ier & UART_IER_THRI)) { + up->ier |= UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serial_omap_start_tx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + struct circ_buf *xmit; + unsigned int start; + int ret = 0; + + if (!up->use_dma) { + serial_omap_enable_ier_thri(up); + return; + } + + xmit = &up->port.state->xmit; + if (uart_circ_empty(xmit) || up->uart_dma.tx_dma_used) + return; + + if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) + ret = omap_request_dma(up->uart_dma.uart_dma_tx, + "UART Tx DMA", + (void *)uart_tx_dma_callback, up, + &(up->uart_dma.tx_dma_channel)); + + if (ret < 0) { + serial_omap_enable_ier_thri(up); + return; + } + + start = up->uart_dma.tx_buf_dma_phys + + (xmit->tail & (UART_XMIT_SIZE - 1)); + spin_lock(&(up->uart_dma.tx_lock)); + up->uart_dma.tx_dma_used = true; + spin_unlock(&(up->uart_dma.tx_lock)); + + up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); + /* + * It is a circular buffer. See if the buffer has wounded back. + * If yes it will have to be transferred in two separate dma + * transfers + */ + if (start + up->uart_dma.tx_buf_size >= + up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) + up->uart_dma.tx_buf_size = + (up->uart_dma.tx_buf_dma_phys + + UART_XMIT_SIZE) - start; + + omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, start, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.tx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_tx, 0); + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.tx_dma_channel); +} + +static unsigned int check_modem_status(struct uart_omap_port *up) +{ + int status; + status = serial_in(up, UART_MSR); + + status |= up->msr_saved_flags; + up->msr_saved_flags = 0; + + if ((status & UART_MSR_ANY_DELTA) == 0) + return status; + if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && + up->port.state != NULL) { + if (status & UART_MSR_TERI) + up->port.icount.rng++; + if (status & UART_MSR_DDSR) + up->port.icount.dsr++; + if (status & UART_MSR_DDCD) + uart_handle_dcd_change + (&up->port, status & UART_MSR_DCD); + if (status & UART_MSR_DCTS) + uart_handle_cts_change + (&up->port, status & UART_MSR_CTS); + wake_up_interruptible(&up->port.state->port.delta_msr_wait); + } + + return status; +} + +/** + * serial_omap_irq() - This handles the interrupt from one port + * @irq: uart port irq number + * @dev_id: uart port info + */ +static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) +{ + struct uart_omap_port *up = dev_id; + unsigned int iir, lsr; + unsigned long flags; + + iir = serial_in(up, UART_IIR); + if (iir & UART_IIR_NO_INT) + return IRQ_NONE; + + spin_lock_irqsave(&up->port.lock, flags); + lsr = serial_in(up, UART_LSR); + if (iir & UART_IER_RLSI) { + if (!up->use_dma) { + if (lsr & UART_LSR_DR) + receive_chars(up, &lsr); + } else { + up->ier &= ~UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + if (serial_omap_start_rxdma(up) != 0) + if (lsr & UART_LSR_DR) + receive_chars(up, &lsr); + } + } + + check_modem_status(up); + if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) + transmit_chars(up); + + spin_unlock_irqrestore(&up->port.lock, flags); + up->port_activity = jiffies; + return IRQ_HANDLED; +} + +static unsigned int serial_omap_tx_empty(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + unsigned int ret = 0; + + dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); + spin_lock_irqsave(&up->port.lock, flags); + ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; + spin_unlock_irqrestore(&up->port.lock, flags); + + return ret; +} + +static unsigned int serial_omap_get_mctrl(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char status; + unsigned int ret = 0; + + status = check_modem_status(up); + dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); + + if (status & UART_MSR_DCD) + ret |= TIOCM_CAR; + if (status & UART_MSR_RI) + ret |= TIOCM_RNG; + if (status & UART_MSR_DSR) + ret |= TIOCM_DSR; + if (status & UART_MSR_CTS) + ret |= TIOCM_CTS; + return ret; +} + +static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char mcr = 0; + + dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); + if (mctrl & TIOCM_RTS) + mcr |= UART_MCR_RTS; + if (mctrl & TIOCM_DTR) + mcr |= UART_MCR_DTR; + if (mctrl & TIOCM_OUT1) + mcr |= UART_MCR_OUT1; + if (mctrl & TIOCM_OUT2) + mcr |= UART_MCR_OUT2; + if (mctrl & TIOCM_LOOP) + mcr |= UART_MCR_LOOP; + + mcr |= up->mcr; + serial_out(up, UART_MCR, mcr); +} + +static void serial_omap_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + + dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); + spin_lock_irqsave(&up->port.lock, flags); + if (break_state == -1) + up->lcr |= UART_LCR_SBC; + else + up->lcr &= ~UART_LCR_SBC; + serial_out(up, UART_LCR, up->lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int serial_omap_startup(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + int retval; + + /* + * Allocate the IRQ + */ + retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, + up->name, up); + if (retval) + return retval; + + dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); + + /* + * Clear the FIFO buffers and disable them. + * (they will be reenabled in set_termios()) + */ + serial_omap_clear_fifos(up); + /* For Hardware flow control */ + serial_out(up, UART_MCR, UART_MCR_RTS); + + /* + * Clear the interrupt registers. + */ + (void) serial_in(up, UART_LSR); + if (serial_in(up, UART_LSR) & UART_LSR_DR) + (void) serial_in(up, UART_RX); + (void) serial_in(up, UART_IIR); + (void) serial_in(up, UART_MSR); + + /* + * Now, initialize the UART + */ + serial_out(up, UART_LCR, UART_LCR_WLEN8); + spin_lock_irqsave(&up->port.lock, flags); + /* + * Most PC uarts need OUT2 raised to enable interrupts. + */ + up->port.mctrl |= TIOCM_OUT2; + serial_omap_set_mctrl(&up->port, up->port.mctrl); + spin_unlock_irqrestore(&up->port.lock, flags); + + up->msr_saved_flags = 0; + if (up->use_dma) { + free_page((unsigned long)up->port.state->xmit.buf); + up->port.state->xmit.buf = dma_alloc_coherent(NULL, + UART_XMIT_SIZE, + (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), + 0); + init_timer(&(up->uart_dma.rx_timer)); + up->uart_dma.rx_timer.function = serial_omap_rx_timeout; + up->uart_dma.rx_timer.data = up->pdev->id; + /* Currently the buffer size is 4KB. Can increase it */ + up->uart_dma.rx_buf = dma_alloc_coherent(NULL, + up->uart_dma.rx_buf_size, + (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); + } + /* + * Finally, enable interrupts. Note: Modem status interrupts + * are set via set_termios(), which will be occurring imminently + * anyway, so we don't enable them here. + */ + up->ier = UART_IER_RLSI | UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + + up->port_activity = jiffies; + return 0; +} + +static void serial_omap_shutdown(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + + dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); + /* + * Disable interrupts from this port + */ + up->ier = 0; + serial_out(up, UART_IER, 0); + + spin_lock_irqsave(&up->port.lock, flags); + up->port.mctrl &= ~TIOCM_OUT2; + serial_omap_set_mctrl(&up->port, up->port.mctrl); + spin_unlock_irqrestore(&up->port.lock, flags); + + /* + * Disable break condition and FIFOs + */ + serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); + serial_omap_clear_fifos(up); + + /* + * Read data port to reset things, and then free the irq + */ + if (serial_in(up, UART_LSR) & UART_LSR_DR) + (void) serial_in(up, UART_RX); + if (up->use_dma) { + int tmp; + dma_free_coherent(up->port.dev, + UART_XMIT_SIZE, up->port.state->xmit.buf, + up->uart_dma.tx_buf_dma_phys); + up->port.state->xmit.buf = NULL; + serial_omap_stop_rx(port); + dma_free_coherent(up->port.dev, + up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, + up->uart_dma.rx_buf_dma_phys); + up->uart_dma.rx_buf = NULL; + tmp = serial_in(up, UART_OMAP_SYSC) & OMAP_UART_SYSC_RESET; + serial_out(up, UART_OMAP_SYSC, tmp); /* force-idle */ + } + free_irq(up->port.irq, up); +} + +static inline void +serial_omap_configure_xonxoff + (struct uart_omap_port *up, struct ktermios *termios) +{ + unsigned char efr = 0; + + up->lcr = serial_in(up, UART_LCR); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); + + serial_out(up, UART_XON1, termios->c_cc[VSTART]); + serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); + + /* clear SW control mode bits */ + efr = up->efr; + efr &= OMAP_UART_SW_CLR; + + /* + * IXON Flag: + * Enable XON/XOFF flow control on output. + * Transmit XON1, XOFF1 + */ + if (termios->c_iflag & IXON) + efr |= OMAP_UART_SW_TX; + + /* + * IXOFF Flag: + * Enable XON/XOFF flow control on input. + * Receiver compares XON1, XOFF1. + */ + if (termios->c_iflag & IXOFF) + efr |= OMAP_UART_SW_RX; + + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + up->mcr = serial_in(up, UART_MCR); + + /* + * IXANY Flag: + * Enable any character to restart output. + * Operation resumes after receiving any + * character after recognition of the XOFF character + */ + if (termios->c_iflag & IXANY) + up->mcr |= UART_MCR_XONANY; + + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); + /* Enable special char function UARTi.EFR_REG[5] and + * load the new software flow control mode IXON or IXOFF + * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. + */ + serial_out(up, UART_EFR, efr | UART_EFR_SCD); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); + serial_out(up, UART_LCR, up->lcr); +} + +static void +serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char cval = 0; + unsigned char efr = 0; + unsigned long flags = 0; + unsigned int baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + cval = UART_LCR_WLEN5; + break; + case CS6: + cval = UART_LCR_WLEN6; + break; + case CS7: + cval = UART_LCR_WLEN7; + break; + default: + case CS8: + cval = UART_LCR_WLEN8; + break; + } + + if (termios->c_cflag & CSTOPB) + cval |= UART_LCR_STOP; + if (termios->c_cflag & PARENB) + cval |= UART_LCR_PARITY; + if (!(termios->c_cflag & PARODD)) + cval |= UART_LCR_EPAR; + + /* + * Ask the core to calculate the divisor for us. + */ + + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); + quot = serial_omap_get_divisor(port, baud); + + up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | + UART_FCR_ENABLE_FIFO; + if (up->use_dma) + up->fcr |= UART_FCR_DMA_SELECT; + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= UART_LSR_BI; + + /* + * Characters to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= UART_LSR_BI; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_OE; + } + + /* + * ignore all characters if CREAD is not set + */ + if ((termios->c_cflag & CREAD) == 0) + up->port.ignore_status_mask |= UART_LSR_DR; + + /* + * Modem status interrupts + */ + up->ier &= ~UART_IER_MSI; + if (UART_ENABLE_MS(&up->port, termios->c_cflag)) + up->ier |= UART_IER_MSI; + serial_out(up, UART_IER, up->ier); + serial_out(up, UART_LCR, cval); /* reset DLAB */ + + /* FIFOs and DMA Settings */ + + /* FCR can be changed only when the + * baud clock is not running + * DLL_REG and DLH_REG set to 0. + */ + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_DLL, 0); + serial_out(up, UART_DLM, 0); + serial_out(up, UART_LCR, 0); + + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_LCR, 0); + up->mcr = serial_in(up, UART_MCR); + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + /* FIFO ENABLE, DMA MODE */ + serial_out(up, UART_FCR, up->fcr); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + if (up->use_dma) { + serial_out(up, UART_TI752_TLR, 0); + serial_out(up, UART_OMAP_SCR, + (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8)); + } + + serial_out(up, UART_EFR, up->efr); + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_MCR, up->mcr); + + /* Protocol, Baud Rate, and Interrupt Settings */ + + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_DISABLE); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_LCR, 0); + serial_out(up, UART_IER, 0); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ + serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ + + serial_out(up, UART_LCR, 0); + serial_out(up, UART_IER, up->ier); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + serial_out(up, UART_EFR, up->efr); + serial_out(up, UART_LCR, cval); + + if (baud > 230400 && baud != 3000000) + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE13X); + else + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE16X); + + /* Hardware Flow Control Configuration */ + + if (termios->c_cflag & CRTSCTS) { + efr |= (UART_EFR_CTS | UART_EFR_RTS); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + up->mcr = serial_in(up, UART_MCR); + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); + serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); + serial_out(up, UART_LCR, cval); + } + + serial_omap_set_mctrl(&up->port, up->port.mctrl); + /* Software Flow Control Configuration */ + if (termios->c_iflag & (IXON | IXOFF)) + serial_omap_configure_xonxoff(up, termios); + + spin_unlock_irqrestore(&up->port.lock, flags); + dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); +} + +static void +serial_omap_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char efr; + + dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, efr | UART_EFR_ECB); + serial_out(up, UART_LCR, 0); + + serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_EFR, efr); + serial_out(up, UART_LCR, 0); + /* Enable module level wake up */ + serial_out(up, UART_OMAP_WER, + (state != 0) ? OMAP_UART_WER_MOD_WKUP : 0); +} + +static void serial_omap_release_port(struct uart_port *port) +{ + dev_dbg(port->dev, "serial_omap_release_port+\n"); +} + +static int serial_omap_request_port(struct uart_port *port) +{ + dev_dbg(port->dev, "serial_omap_request_port+\n"); + return 0; +} + +static void serial_omap_config_port(struct uart_port *port, int flags) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", + up->pdev->id); + up->port.type = PORT_OMAP; +} + +static int +serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + /* we don't want the core code to modify any port params */ + dev_dbg(port->dev, "serial_omap_verify_port+\n"); + return -EINVAL; +} + +static const char * +serial_omap_type(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); + return up->name; +} + +#ifdef CONFIG_SERIAL_OMAP_CONSOLE + +static struct uart_omap_port *serial_omap_console_ports[4]; + +static struct uart_driver serial_omap_reg; + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void wait_for_xmitr(struct uart_omap_port *up) +{ + unsigned int status, tmout = 10000; + + /* Wait up to 10ms for the character(s) to be sent. */ + do { + status = serial_in(up, UART_LSR); + + if (status & UART_LSR_BI) + up->lsr_break_flag = UART_LSR_BI; + + if (--tmout == 0) + break; + udelay(1); + } while ((status & BOTH_EMPTY) != BOTH_EMPTY); + + /* Wait up to 1s for flow control if necessary */ + if (up->port.flags & UPF_CONS_FLOW) { + tmout = 1000000; + for (tmout = 1000000; tmout; tmout--) { + unsigned int msr = serial_in(up, UART_MSR); + up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; + if (msr & UART_MSR_CTS) + break; + udelay(1); + } + } +} + +static void serial_omap_console_putchar(struct uart_port *port, int ch) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + wait_for_xmitr(up); + serial_out(up, UART_TX, ch); +} + +static void +serial_omap_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_omap_port *up = serial_omap_console_ports[co->index]; + unsigned int ier; + + /* + * First save the IER then disable the interrupts + */ + ier = serial_in(up, UART_IER); + serial_out(up, UART_IER, 0); + + uart_console_write(&up->port, s, count, serial_omap_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + wait_for_xmitr(up); + serial_out(up, UART_IER, ier); + /* + * The receive handling will happen properly because the + * receive ready bit will still be set; it is not cleared + * on read. However, modem control will not, we must + * call it if we have saved something in the saved flags + * while processing with interrupts off. + */ + if (up->msr_saved_flags) + check_modem_status(up); +} + +static int __init +serial_omap_console_setup(struct console *co, char *options) +{ + struct uart_omap_port *up; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + int r; + + if (serial_omap_console_ports[co->index] == NULL) + return -ENODEV; + up = serial_omap_console_ports[co->index]; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + r = uart_set_options(&up->port, co, baud, parity, bits, flow); + + return r; +} + +static struct console serial_omap_console = { + .name = OMAP_SERIAL_NAME, + .write = serial_omap_console_write, + .device = uart_console_device, + .setup = serial_omap_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &serial_omap_reg, +}; + +static void serial_omap_add_console_port(struct uart_omap_port *up) +{ + serial_omap_console_ports[up->pdev->id] = up; +} + +#define OMAP_CONSOLE (&serial_omap_console) + +#else + +#define OMAP_CONSOLE NULL + +static inline void serial_omap_add_console_port(struct uart_omap_port *up) +{} + +#endif + +struct uart_ops serial_omap_pops = { + .tx_empty = serial_omap_tx_empty, + .set_mctrl = serial_omap_set_mctrl, + .get_mctrl = serial_omap_get_mctrl, + .stop_tx = serial_omap_stop_tx, + .start_tx = serial_omap_start_tx, + .stop_rx = serial_omap_stop_rx, + .enable_ms = serial_omap_enable_ms, + .break_ctl = serial_omap_break_ctl, + .startup = serial_omap_startup, + .shutdown = serial_omap_shutdown, + .set_termios = serial_omap_set_termios, + .pm = serial_omap_pm, + .type = serial_omap_type, + .release_port = serial_omap_release_port, + .request_port = serial_omap_request_port, + .config_port = serial_omap_config_port, + .verify_port = serial_omap_verify_port, +}; + +static struct uart_driver serial_omap_reg = { + .owner = THIS_MODULE, + .driver_name = "OMAP-SERIAL", + .dev_name = OMAP_SERIAL_NAME, + .nr = OMAP_MAX_HSUART_PORTS, + .cons = OMAP_CONSOLE, +}; + +static int +serial_omap_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct uart_omap_port *up = platform_get_drvdata(pdev); + + if (up) + uart_suspend_port(&serial_omap_reg, &up->port); + return 0; +} + +static int serial_omap_resume(struct platform_device *dev) +{ + struct uart_omap_port *up = platform_get_drvdata(dev); + + if (up) + uart_resume_port(&serial_omap_reg, &up->port); + return 0; +} + +static void serial_omap_rx_timeout(unsigned long uart_no) +{ + struct uart_omap_port *up = ui[uart_no]; + unsigned int curr_dma_pos, curr_transmitted_size; + unsigned int ret = 0; + + curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); + if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || + (curr_dma_pos == 0)) { + if (jiffies_to_msecs(jiffies - up->port_activity) < + RX_TIMEOUT) { + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + } else { + serial_omap_stop_rxdma(up); + up->ier |= UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + } + return; + } + + curr_transmitted_size = curr_dma_pos - + up->uart_dma.prev_rx_dma_pos; + up->port.icount.rx += curr_transmitted_size; + tty_insert_flip_string(up->port.state->port.tty, + up->uart_dma.rx_buf + + (up->uart_dma.prev_rx_dma_pos - + up->uart_dma.rx_buf_dma_phys), + curr_transmitted_size); + tty_flip_buffer_push(up->port.state->port.tty); + up->uart_dma.prev_rx_dma_pos = curr_dma_pos; + if (up->uart_dma.rx_buf_size + + up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { + ret = serial_omap_start_rxdma(up); + if (ret < 0) { + serial_omap_stop_rxdma(up); + up->ier |= UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + } + } else { + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + } + up->port_activity = jiffies; +} + +static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) +{ + return; +} + +static int serial_omap_start_rxdma(struct uart_omap_port *up) +{ + int ret = 0; + + if (up->uart_dma.rx_dma_channel == -1) { + ret = omap_request_dma(up->uart_dma.uart_dma_rx, + "UART Rx DMA", + (void *)uart_rx_dma_callback, up, + &(up->uart_dma.rx_dma_channel)); + if (ret < 0) + return ret; + + omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, + up->uart_dma.rx_buf_dma_phys, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.rx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_rx, 0); + } + up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.rx_dma_channel); + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + up->uart_dma.rx_dma_used = true; + return ret; +} + +static void serial_omap_continue_tx(struct uart_omap_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int start = up->uart_dma.tx_buf_dma_phys + + (xmit->tail & (UART_XMIT_SIZE - 1)); + + if (uart_circ_empty(xmit)) + return; + + up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); + /* + * It is a circular buffer. See if the buffer has wounded back. + * If yes it will have to be transferred in two separate dma + * transfers + */ + if (start + up->uart_dma.tx_buf_size >= + up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) + up->uart_dma.tx_buf_size = + (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; + omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, start, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.tx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_tx, 0); + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.tx_dma_channel); +} + +static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) +{ + struct uart_omap_port *up = (struct uart_omap_port *)data; + struct circ_buf *xmit = &up->port.state->xmit; + + xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ + (UART_XMIT_SIZE - 1); + up->port.icount.tx += up->uart_dma.tx_buf_size; + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (uart_circ_empty(xmit)) { + spin_lock(&(up->uart_dma.tx_lock)); + serial_omap_stop_tx(&up->port); + up->uart_dma.tx_dma_used = false; + spin_unlock(&(up->uart_dma.tx_lock)); + } else { + omap_stop_dma(up->uart_dma.tx_dma_channel); + serial_omap_continue_tx(up); + } + up->port_activity = jiffies; + return; +} + +static int serial_omap_probe(struct platform_device *pdev) +{ + struct uart_omap_port *up; + struct resource *mem, *irq, *dma_tx, *dma_rx; + struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; + int ret = -ENOSPC; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "no mem resource?\n"); + return -ENODEV; + } + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!irq) { + dev_err(&pdev->dev, "no irq resource?\n"); + return -ENODEV; + } + + if (!request_mem_region(mem->start, (mem->end - mem->start) + 1, + pdev->dev.driver->name)) { + dev_err(&pdev->dev, "memory region already claimed\n"); + return -EBUSY; + } + + dma_rx = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!dma_rx) { + ret = -EINVAL; + goto err; + } + + dma_tx = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (!dma_tx) { + ret = -EINVAL; + goto err; + } + + up = kzalloc(sizeof(*up), GFP_KERNEL); + if (up == NULL) { + ret = -ENOMEM; + goto do_release_region; + } + sprintf(up->name, "OMAP UART%d", pdev->id); + up->pdev = pdev; + up->port.dev = &pdev->dev; + up->port.type = PORT_OMAP; + up->port.iotype = UPIO_MEM; + up->port.irq = irq->start; + + up->port.regshift = 2; + up->port.fifosize = 64; + up->port.ops = &serial_omap_pops; + up->port.line = pdev->id; + + up->port.membase = omap_up_info->membase; + up->port.mapbase = omap_up_info->mapbase; + up->port.flags = omap_up_info->flags; + up->port.irqflags = omap_up_info->irqflags; + up->port.uartclk = omap_up_info->uartclk; + up->uart_dma.uart_base = mem->start; + + if (omap_up_info->dma_enabled) { + up->uart_dma.uart_dma_tx = dma_tx->start; + up->uart_dma.uart_dma_rx = dma_rx->start; + up->use_dma = 1; + up->uart_dma.rx_buf_size = 4096; + up->uart_dma.rx_timeout = 1; + spin_lock_init(&(up->uart_dma.tx_lock)); + spin_lock_init(&(up->uart_dma.rx_lock)); + up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; + up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; + } + + ui[pdev->id] = up; + serial_omap_add_console_port(up); + + ret = uart_add_one_port(&serial_omap_reg, &up->port); + if (ret != 0) + goto do_release_region; + + platform_set_drvdata(pdev, up); + return 0; +err: + dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", + pdev->id, __func__, ret); +do_release_region: + release_mem_region(mem->start, (mem->end - mem->start) + 1); + return ret; +} + +static int serial_omap_remove(struct platform_device *dev) +{ + struct uart_omap_port *up = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + if (up) { + uart_remove_one_port(&serial_omap_reg, &up->port); + kfree(up); + } + return 0; +} + +static struct platform_driver serial_omap_driver = { + .probe = serial_omap_probe, + .remove = serial_omap_remove, + + .suspend = serial_omap_suspend, + .resume = serial_omap_resume, + .driver = { + .name = DRIVER_NAME, + }, +}; + +int __init serial_omap_init(void) +{ + int ret; + + ret = uart_register_driver(&serial_omap_reg); + if (ret != 0) + return ret; + ret = platform_driver_register(&serial_omap_driver); + if (ret != 0) + uart_unregister_driver(&serial_omap_reg); + return ret; +} + +void __exit serial_omap_exit(void) +{ + platform_driver_unregister(&serial_omap_driver); + uart_unregister_driver(&serial_omap_reg); +} + +module_init(serial_omap_init); +module_exit(serial_omap_exit); + +MODULE_DESCRIPTION("OMAP High Speed UART driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 78dd1e7..caaa311 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -182,6 +182,9 @@ /* Aeroflex Gaisler GRLIB APBUART */ #define PORT_APBUART 90 +/* TI OMAP-UART */ +#define PORT_OMAP 91 + #ifdef __KERNEL__ #include From patchwork Sat May 8 04:31:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Weber X-Patchwork-Id: 97870 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o484VoZX020150 for ; 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Sat, 8 May 2010 06:31:47 +0200 (CEST) From: Thomas Weber To: linux-omap@vger.kernel.org Cc: Thomas Weber Subject: [PATCH 4/6] Devkit8000: Using the REGULATOR_SUPPLY macro Date: Sat, 8 May 2010 06:31:21 +0200 Message-Id: <1273293083-24063-5-git-send-email-weber@corscience.de> X-Mailer: git-send-email 1.6.4.4 In-Reply-To: <1273293083-24063-1-git-send-email-weber@corscience.de> References: <1273293083-24063-1-git-send-email-weber@corscience.de> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 08 May 2010 04:31:50 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 85adf54..c0905b0 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -165,9 +165,8 @@ static struct regulator_consumer_supply devkit8000_vmmc1_supply = { }; /* ads7846 on SPI */ -static struct regulator_consumer_supply devkit8000_vio_supplies[] = { - REGULATOR_SUPPLY("vcc", "spi2.0") -}; +static struct regulator_consumer_supply devkit8000_vio_supply = + REGULATOR_SUPPLY("vcc", "spi2.0"); static struct omap_dss_device devkit8000_lcd_device = { .name = "lcd", @@ -216,10 +215,8 @@ static struct platform_device devkit8000_dss_device = { }, }; -static struct regulator_consumer_supply devkit8000_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &devkit8000_dss_device.dev, -}; +static struct regulator_consumer_supply devkit8000_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); static int board_keymap[] = { KEY(0, 0, KEY_1), @@ -281,12 +278,8 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { .setup = devkit8000_twl_gpio_setup, }; -static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { - { - .supply = "vdds_dsi", - .dev = &devkit8000_dss_device.dev, - } -}; +static struct regulator_consumer_supply devkit8000_vpll1_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data devkit8000_vmmc1 = { @@ -327,8 +320,8 @@ static struct regulator_init_data devkit8000_vpll1 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll1_supplies), - .consumer_supplies = devkit8000_vpll1_supplies, + .num_consumer_supplies = 1, + .consumer_supplies = &devkit8000_vpll1_supply, }; /* VAUX4 for ads7846 and nubs */ @@ -342,8 +335,8 @@ static struct regulator_init_data devkit8000_vio = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = ARRAY_SIZE(devkit8000_vio_supplies), - .consumer_supplies = devkit8000_vio_supplies, + .num_consumer_supplies = 1, + .consumer_supplies = &devkit8000_vio_supply, }; static struct twl4030_usb_data devkit8000_usb_data = { From patchwork Thu Aug 5 15:47:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 117350 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75FmGLA022948 for ; Thu, 5 Aug 2010 15:48:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933353Ab0HEPsP (ORCPT ); Thu, 5 Aug 2010 11:48:15 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:39257 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933260Ab0HEPsO (ORCPT ); Thu, 5 Aug 2010 11:48:14 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75FmBnO002980 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 10:48:11 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o75FluBS007306; Thu, 5 Aug 2010 10:48:06 -0500 (CDT) From: Benoit Cousson To: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, paul@pwsan.com Cc: rnayak@ti.com, santosh.shilimkar@ti.com, Benoit Cousson Subject: [PATCH v3 4/7] OMAP4: hwmod: Add TIMER data for OMAP4430 ES1 & ES2 Date: Thu, 5 Aug 2010 17:47:53 +0200 Message-Id: <1281023276-15679-5-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <1281023276-15679-1-git-send-email-b-cousson@ti.com> References: <1281023276-15679-1-git-send-email-b-cousson@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 15:48:17 +0000 (UTC) different depending of the instance. - timer 1 is inside the wakeup domain - timers 5, 6, 7 & 8 are inside in the ABE (audio backend) - timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain The timer was previously named gptimerX or dmtimerX, it is now simply named timerX. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Kevin Hilman Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 619 ++++++++++++++++++++++++++++ 1 files changed, 619 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index e20b0ee..e6aeb57 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -452,6 +452,613 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'timer' class + * general purpose timer module with accurate 1ms tick + * This class contains several variants: ['timer_1ms', 'timer'] + */ + +static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | + SYSS_MISSING), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { + .name = "timer_1ms", + .sysc = &omap44xx_timer_1ms_sysc, +}; + +static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_SOFTRESET | SYSS_MISSING), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap44xx_timer_sysc, +}; + +/* timer1 */ +static struct omap_hwmod omap44xx_timer1_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { + { .irq = 37 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { + { + .pa_start = 0x4a318000, + .pa_end = 0x4a31807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_timer1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_timer1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { + &omap44xx_l4_wkup__timer1, +}; + +static struct omap_hwmod omap44xx_timer1_hwmod = { + .name = "timer1", + .class = &omap44xx_timer_1ms_hwmod_class, + .mpu_irqs = omap44xx_timer1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), + .main_clk = "timer1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + }, + }, + .slaves = omap44xx_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer2 */ +static struct omap_hwmod omap44xx_timer2_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { + { .irq = 38 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { + { + .pa_start = 0x48032000, + .pa_end = 0x4803207f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { + &omap44xx_l4_per__timer2, +}; + +static struct omap_hwmod omap44xx_timer2_hwmod = { + .name = "timer2", + .class = &omap44xx_timer_1ms_hwmod_class, + .mpu_irqs = omap44xx_timer2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs), + .main_clk = "timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + }, + }, + .slaves = omap44xx_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer3 */ +static struct omap_hwmod omap44xx_timer3_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { + { .irq = 39 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { + { + .pa_start = 0x48034000, + .pa_end = 0x4803407f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { + &omap44xx_l4_per__timer3, +}; + +static struct omap_hwmod omap44xx_timer3_hwmod = { + .name = "timer3", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs), + .main_clk = "timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + }, + }, + .slaves = omap44xx_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer4 */ +static struct omap_hwmod omap44xx_timer4_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { + { .irq = 40 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { + { + .pa_start = 0x48036000, + .pa_end = 0x4803607f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { + &omap44xx_l4_per__timer4, +}; + +static struct omap_hwmod omap44xx_timer4_hwmod = { + .name = "timer4", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs), + .main_clk = "timer4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + }, + }, + .slaves = omap44xx_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer5 */ +static struct omap_hwmod omap44xx_timer5_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { + { .irq = 41 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { + { + .pa_start = 0x40138000, + .pa_end = 0x4013807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x4903807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer5 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer5 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { + &omap44xx_l4_abe__timer5, + &omap44xx_l4_abe__timer5_dma, +}; + +static struct omap_hwmod omap44xx_timer5_hwmod = { + .name = "timer5", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs), + .main_clk = "timer5_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + }, + }, + .slaves = omap44xx_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer6 */ +static struct omap_hwmod omap44xx_timer6_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { + { .irq = 42 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { + { + .pa_start = 0x4013a000, + .pa_end = 0x4013a07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { + { + .pa_start = 0x4903a000, + .pa_end = 0x4903a07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer6 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer6 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { + &omap44xx_l4_abe__timer6, + &omap44xx_l4_abe__timer6_dma, +}; + +static struct omap_hwmod omap44xx_timer6_hwmod = { + .name = "timer6", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer6_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), + .main_clk = "timer6_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + }, + }, + .slaves = omap44xx_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer7 */ +static struct omap_hwmod omap44xx_timer7_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { + { .irq = 43 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { + { + .pa_start = 0x4013c000, + .pa_end = 0x4013c07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { + { + .pa_start = 0x4903c000, + .pa_end = 0x4903c07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer7 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer7 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { + &omap44xx_l4_abe__timer7, + &omap44xx_l4_abe__timer7_dma, +}; + +static struct omap_hwmod omap44xx_timer7_hwmod = { + .name = "timer7", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer7_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs), + .main_clk = "timer7_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + }, + }, + .slaves = omap44xx_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer8 */ +static struct omap_hwmod omap44xx_timer8_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { + { .irq = 44 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { + { + .pa_start = 0x4013e000, + .pa_end = 0x4013e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { + { + .pa_start = 0x4903e000, + .pa_end = 0x4903e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer8 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer8 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { + &omap44xx_l4_abe__timer8, + &omap44xx_l4_abe__timer8_dma, +}; + +static struct omap_hwmod omap44xx_timer8_hwmod = { + .name = "timer8", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer8_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs), + .main_clk = "timer8_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + }, + }, + .slaves = omap44xx_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer9 */ +static struct omap_hwmod omap44xx_timer9_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { + { .irq = 45 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { + { + .pa_start = 0x4803e000, + .pa_end = 0x4803e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer9_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer9_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { + &omap44xx_l4_per__timer9, +}; + +static struct omap_hwmod omap44xx_timer9_hwmod = { + .name = "timer9", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer9_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs), + .main_clk = "timer9_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + }, + }, + .slaves = omap44xx_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer10 */ +static struct omap_hwmod omap44xx_timer10_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { + { .irq = 46 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x4808607f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer10_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer10_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer10 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { + &omap44xx_l4_per__timer10, +}; + +static struct omap_hwmod omap44xx_timer10_hwmod = { + .name = "timer10", + .class = &omap44xx_timer_1ms_hwmod_class, + .mpu_irqs = omap44xx_timer10_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs), + .main_clk = "timer10_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + }, + }, + .slaves = omap44xx_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer11 */ +static struct omap_hwmod omap44xx_timer11_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { + { .irq = 47 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x4808807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer11_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer11_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer11 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { + &omap44xx_l4_per__timer11, +}; + +static struct omap_hwmod omap44xx_timer11_hwmod = { + .name = "timer11", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer11_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs), + .main_clk = "timer11_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + }, + }, + .slaves = omap44xx_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* dmm class */ &omap44xx_dmm_hwmod, @@ -472,6 +1079,18 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* mpu class */ &omap44xx_mpu_hwmod, + /* timer class */ + &omap44xx_timer1_hwmod, + &omap44xx_timer2_hwmod, + &omap44xx_timer3_hwmod, + &omap44xx_timer4_hwmod, + &omap44xx_timer5_hwmod, + &omap44xx_timer6_hwmod, + &omap44xx_timer7_hwmod, + &omap44xx_timer8_hwmod, + &omap44xx_timer9_hwmod, + &omap44xx_timer10_hwmod, + &omap44xx_timer11_hwmod, NULL, }; From patchwork Thu Aug 5 15:47:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 117351 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75FmLbL022987 for ; Thu, 5 Aug 2010 15:48:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933434Ab0HEPsU (ORCPT ); Thu, 5 Aug 2010 11:48:20 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39663 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933260Ab0HEPsS (ORCPT ); Thu, 5 Aug 2010 11:48:18 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75FmG6L026400 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 10:48:16 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o75FluBU007306; Thu, 5 Aug 2010 10:48:11 -0500 (CDT) From: Benoit Cousson To: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, paul@pwsan.com Cc: rnayak@ti.com, santosh.shilimkar@ti.com, Benoit Cousson Subject: [PATCH v3 6/7] OMAP: hwmod: Temporary prevent reset during _setup for GPIOs Date: Thu, 5 Aug 2010 17:47:55 +0200 Message-Id: <1281023276-15679-7-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <1281023276-15679-1-git-send-email-b-cousson@ti.com> References: <1281023276-15679-1-git-send-email-b-cousson@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 15:48:21 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 83a208d..5d440d5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1704,6 +1704,7 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { static struct omap_hwmod omap44xx_gpio2_hwmod = { .name = "gpio2", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), .main_clk = "gpio2_ick", @@ -1755,6 +1756,7 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { static struct omap_hwmod omap44xx_gpio3_hwmod = { .name = "gpio3", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), .main_clk = "gpio3_ick", @@ -1806,6 +1808,7 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { static struct omap_hwmod omap44xx_gpio4_hwmod = { .name = "gpio4", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), .main_clk = "gpio4_ick", @@ -1857,6 +1860,7 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { static struct omap_hwmod omap44xx_gpio5_hwmod = { .name = "gpio5", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_gpio5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), .main_clk = "gpio5_ick", @@ -1908,6 +1912,7 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { static struct omap_hwmod omap44xx_gpio6_hwmod = { .name = "gpio6", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_gpio6_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), .main_clk = "gpio6_ick", From patchwork Thu Aug 5 15:47:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 117352 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75FmNap022996 for ; Thu, 5 Aug 2010 15:48:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933260Ab0HEPsW (ORCPT ); Thu, 5 Aug 2010 11:48:22 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:35486 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933438Ab0HEPsU (ORCPT ); Thu, 5 Aug 2010 11:48:20 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75FmIr1020356 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 10:48:18 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o75FluBV007306; Thu, 5 Aug 2010 10:48:13 -0500 (CDT) From: Benoit Cousson To: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, paul@pwsan.com Cc: rnayak@ti.com, santosh.shilimkar@ti.com, Benoit Cousson Subject: [PATCH v3 7/7] OMAP: hwmod: Temporary prevent reset during _setup for I2Cs Date: Thu, 5 Aug 2010 17:47:56 +0200 Message-Id: <1281023276-15679-8-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <1281023276-15679-1-git-send-email-b-cousson@ti.com> References: <1281023276-15679-1-git-send-email-b-cousson@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 15:48:23 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 5d440d5..9736a49 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2268,6 +2268,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_i2c1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), .sdma_reqs = omap44xx_i2c1_sdma_reqs, @@ -2320,6 +2321,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { static struct omap_hwmod omap44xx_i2c2_hwmod = { .name = "i2c2", .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_i2c2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), .sdma_reqs = omap44xx_i2c2_sdma_reqs, @@ -2372,6 +2374,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_i2c3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), .sdma_reqs = omap44xx_i2c3_sdma_reqs, @@ -2424,6 +2427,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_i2c4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), .sdma_reqs = omap44xx_i2c4_sdma_reqs, From patchwork Thu Apr 29 08:48:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Rapoport X-Patchwork-Id: 96065 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3UL3bJS031256 for ; Fri, 30 Apr 2010 21:03:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759264Ab0D3VDM (ORCPT ); Fri, 30 Apr 2010 17:03:12 -0400 Received: from compulab.co.il ([67.18.134.219]:38483 "EHLO compulab.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757260Ab0D3VDA (ORCPT ); Fri, 30 Apr 2010 17:03:00 -0400 Received: from [62.90.235.247] (helo=zimbra-mta.compulab.co.il) by compulab.site5.com with esmtp (Exim 4.69) (envelope-from ) id 1O7PR9-0008JF-60; Thu, 29 Apr 2010 03:49:35 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by zimbra-mta.compulab.co.il (Postfix) with ESMTP id 4C41B9A002A; Thu, 29 Apr 2010 11:49:33 +0300 (IDT) X-Virus-Scanned: amavisd-new at compulab.co.il Received: from zimbra-mta.compulab.co.il ([127.0.0.1]) by localhost (zimbra-mta.compulab.co.il [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X+xAHTYxX-Fn; Thu, 29 Apr 2010 11:49:33 +0300 (IDT) Received: from droid.compulab.local (droid.compulab.local [10.1.1.77]) by zimbra-mta.compulab.co.il (Postfix) with ESMTP id 0E3F69A0026; Thu, 29 Apr 2010 11:49:33 +0300 (IDT) Received: from droid.compulab.local (localhost [127.0.0.1]) by droid.compulab.local (8.14.0/8.14.0) with ESMTP id o3T8mJ71015328; Thu, 29 Apr 2010 11:48:19 +0300 Received: (from mike@localhost) by droid.compulab.local (8.14.4/8.14.0/Submit) id o3T8mJSt015327; Thu, 29 Apr 2010 11:48:19 +0300 X-Authentication-Warning: droid.compulab.local: mike set sender to mike@compulab.co.il using -f From: Mike Rapoport To: linux-omap@vger.kernel.org Cc: tony@atomide.com, vimal.newwork@gmail.com, s-ghorai@ti.com, Mike Rapoport Subject: [PATCH v2 3/3] omap: gpmc-nand: add ability to keep timings defined by the bootloader Date: Thu, 29 Apr 2010 11:48:12 +0300 Message-Id: X-Mailer: git-send-email 1.6.6.2 In-Reply-To: References: X-ACL-Warn: { X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - compulab.site5.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - compulab.co.il X-Source: X-Source-Args: X-Source-Dir: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 30 Apr 2010 21:03:48 +0000 (UTC) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 9434c80..96f0c7f 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -22,6 +22,7 @@ #define WR_RD_PIN_MONITORING 0x00600000 static struct omap_nand_platform_data *gpmc_nand_data; +static struct gpmc_timings gpmc_default_timings; static struct resource gpmc_nand_resource = { .flags = IORESOURCE_MEM, @@ -65,21 +66,28 @@ static void omap2_nand_gpmc_round_timings(struct gpmc_timings *src, static int omap2_nand_gpmc_retime(void) { + struct device *dev = &gpmc_nand_device.dev; + struct gpmc_timings *gpmc_t = gpmc_nand_data->gpmc_t; struct gpmc_timings t; int err; - if (!gpmc_nand_data->gpmc_t) + if (!gpmc_t) { + dev_warn(dev, "No timings provided, skipping retime\n"); return 0; + } - memset(&t, 0, sizeof(t)); - omap2_nand_gpmc_round_timings(gpmc_nand_data->gpmc_t, &t); + if (!gpmc_nand_data->keep_timings) { + memset(&t, 0, sizeof(t)); + omap2_nand_gpmc_round_timings(gpmc_nand_data->gpmc_t, &t); + gpmc_t = &t; + } /* Configure GPMC */ gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | GPMC_CONFIG1_DEVICETYPE_NAND); - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); if (err) return err; @@ -116,6 +124,11 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) return err; } + if (gpmc_nand_data->keep_timings) { + gpmc_cs_get_timings(gpmc_nand_data->cs, &gpmc_default_timings); + gpmc_nand_data->gpmc_t = &gpmc_default_timings; + } + err = gpmc_nand_setup(); if (err < 0) { dev_err(dev, "NAND platform setup failed: %d\n", err); diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index f8efd54..0f727ea 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -24,6 +24,7 @@ struct omap_nand_platform_data { void __iomem *gpmc_cs_baseaddr; void __iomem *gpmc_baseaddr; int devsize; + bool keep_timings; }; /* size (4 KiB) for IO mapping */ From patchwork Tue May 18 20:13:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liam Girdwood X-Patchwork-Id: 100596 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4IKDtxu020832 for ; Tue, 18 May 2010 20:13:55 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757465Ab0ERUNy (ORCPT ); Tue, 18 May 2010 16:13:54 -0400 Received: from mail-wy0-f174.google.com ([74.125.82.174]:48480 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754806Ab0ERUNx (ORCPT ); Tue, 18 May 2010 16:13:53 -0400 Received: by mail-wy0-f174.google.com with SMTP id 39so1699320wyb.19 for ; Tue, 18 May 2010 13:13:52 -0700 (PDT) Received: by 10.227.143.211 with SMTP id w19mr6715739wbu.182.1274213632612; Tue, 18 May 2010 13:13:52 -0700 (PDT) Received: from localhost.localdomain (host81-136-218-57.in-addr.btopenworld.com [81.136.218.57]) by mx.google.com with ESMTPS id l23sm50762912wbb.8.2010.05.18.13.13.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 18 May 2010 13:13:51 -0700 (PDT) From: Liam Girdwood To: , Cc: Liam Girdwood , Mark Brown , Peter Ujfalusi , Jarkko Nikula , Tony Lindgren Subject: [PATCH 3/4] ASoC: mcbsp - add machine threshold callback Date: Tue, 18 May 2010 21:13:13 +0100 Message-Id: <1274213594-26554-4-git-send-email-lrg@slimlogic.co.uk> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1274213594-26554-1-git-send-email-lrg@slimlogic.co.uk> References: <1274213594-26554-1-git-send-email-lrg@slimlogic.co.uk> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 18 May 2010 20:13:55 +0000 (UTC) diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index 6f44cb4..9a1583d 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -51,6 +51,9 @@ struct omap_mcbsp_data { unsigned int bus_id; struct omap_mcbsp_reg_cfg regs; unsigned int fmt; + + /* optional machine set_threshold() sample value */ + void (*mach_set_threshold)(struct snd_pcm_substream *substream); /* * Flags indicating is the bus already activated and configured by * another substream @@ -306,7 +309,11 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, } else if (cpu_is_omap343x()) { dma = omap24xx_dma_reqs[bus_id][substream->stream]; port = omap34xx_mcbsp_port[bus_id][substream->stream]; - omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold = + if (mcbsp_data->mach_set_threshold) + omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold = + mcbsp_data->mach_set_threshold; + else + omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold = omap_mcbsp_set_threshold; /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ if (omap_mcbsp_get_dma_op_mode(bus_id) == @@ -835,6 +842,19 @@ int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id) } EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls); +int omap_bcbsp_set_threshold_func(struct snd_soc_dai *cpu_dai, + void (*mach_set_threshold)(struct snd_pcm_substream *substream)) +{ + struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); + + if (!cpu_is_omap34xx()) + return -ENODEV; + + mcbsp_data->mach_set_threshold = mach_set_threshold; + return 0; +} +EXPORT_SYMBOL_GPL(omap_bcbsp_set_threshold_func); + static int __init snd_omap_mcbsp_init(void) { return snd_soc_register_dais(omap_mcbsp_dai, diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h index 6c363e5..f8d8044 100644 --- a/sound/soc/omap/omap-mcbsp.h +++ b/sound/soc/omap/omap-mcbsp.h @@ -58,5 +58,7 @@ enum omap_mcbsp_div { extern struct snd_soc_dai omap_mcbsp_dai[NUM_LINKS]; int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id); +int omap_bcbsp_set_threshold_func(struct snd_soc_dai *cpu_dai, + void (*mach_set_threshold)(struct snd_pcm_substream *substream)); #endif From patchwork Thu Jul 1 00:00:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 108971 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5UNrwa4014167 for ; Wed, 30 Jun 2010 23:53:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757505Ab0F3XwF (ORCPT ); Wed, 30 Jun 2010 19:52:05 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:52312 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756056Ab0F3Xue (ORCPT ); Wed, 30 Jun 2010 19:50:34 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5UNoXWZ010945 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 30 Jun 2010 18:50:33 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o5UNoWLe014586; Wed, 30 Jun 2010 18:50:33 -0500 (CDT) Received: from localhost (x0095840-desktop.am.dhcp.ti.com [128.247.77.44]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o5UNoWP07709; Wed, 30 Jun 2010 18:50:32 -0500 (CDT) From: Fernando Guzman Lugo To: , Cc: , , , , Fernando Guzman Lugo Subject: [PATCHv3 9/9] dspbridge: cleanup bridge_dev_context and cfg_hostres structures Date: Wed, 30 Jun 2010 19:00:01 -0500 Message-Id: <1277942401-3566-10-git-send-email-x0095840@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277942401-3566-9-git-send-email-x0095840@ti.com> References: <1277942401-3566-1-git-send-email-x0095840@ti.com> <1277942401-3566-2-git-send-email-x0095840@ti.com> <1277942401-3566-3-git-send-email-x0095840@ti.com> <1277942401-3566-4-git-send-email-x0095840@ti.com> <1277942401-3566-5-git-send-email-x0095840@ti.com> <1277942401-3566-6-git-send-email-x0095840@ti.com> <1277942401-3566-7-git-send-email-x0095840@ti.com> <1277942401-3566-8-git-send-email-x0095840@ti.com> <1277942401-3566-9-git-send-email-x0095840@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 30 Jun 2010 23:53:58 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h index 38122db..dfb55cc 100644 --- a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h +++ b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h @@ -68,7 +68,6 @@ struct cfg_hostres { void __iomem *dw_per_base; u32 dw_per_pm_base; u32 dw_core_pm_base; - void __iomem *dw_dmmu_base; void __iomem *dw_sys_ctrl_base; }; diff --git a/drivers/dsp/bridge/core/_tiomap.h b/drivers/dsp/bridge/core/_tiomap.h index 8a9a822..82bce7d 100644 --- a/drivers/dsp/bridge/core/_tiomap.h +++ b/drivers/dsp/bridge/core/_tiomap.h @@ -323,7 +323,6 @@ struct bridge_dev_context { */ u32 dw_dsp_ext_base_addr; /* See the comment above */ u32 dw_api_reg_base; /* API mem map'd registers */ - void __iomem *dw_dsp_mmu_base; /* DSP MMU Mapped registers */ u32 dw_api_clk_base; /* CLK Registers */ u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */ u32 dw_public_rhea; /* Pub Rhea */ @@ -347,10 +346,6 @@ struct bridge_dev_context { /* DMMU TLB entries */ struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB]; u32 dw_brd_state; /* Last known board state. */ - u32 ul_int_mask; /* int mask */ - u16 io_base; /* Board I/O base */ - u32 num_tlb_entries; /* DSP MMU TLB entry counter */ - u32 fixed_tlb_entries; /* Fixed DSPMMU TLB entry count */ /* TC Settings */ bool tc_word_swap_on; /* Traffic Controller Word Swap */ diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index aa6e999..83a9561 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -753,7 +753,6 @@ static int bridge_dev_create(OUT struct bridge_dev_context dev_context->atlb_entry[entry_ndx].ul_gpp_pa = dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0; } - dev_context->num_tlb_entries = 0; dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *) (pConfig-> dw_mem_base @@ -766,11 +765,7 @@ static int bridge_dev_create(OUT struct bridge_dev_context if (DSP_SUCCEEDED(status)) { dev_context->tc_word_swap_on = drv_datap->tc_wordswapon; - /* MMU address is obtained from the host - * resources struct */ - dev_context->dw_dsp_mmu_base = resources->dw_dmmu_base; dev_context->hdev_obj = hdev_obj; - dev_context->ul_int_mask = 0; /* Store current board state. */ dev_context->dw_brd_state = BRD_STOPPED; dev_context->resources = resources; @@ -887,8 +882,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) iounmap((void *)host_res->dw_mem_base[3]); if (host_res->dw_mem_base[4]) iounmap((void *)host_res->dw_mem_base[4]); - if (host_res->dw_dmmu_base) - iounmap(host_res->dw_dmmu_base); if (host_res->dw_per_base) iounmap(host_res->dw_per_base); if (host_res->dw_per_pm_base) @@ -902,7 +895,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) host_res->dw_mem_base[2] = (u32) NULL; host_res->dw_mem_base[3] = (u32) NULL; host_res->dw_mem_base[4] = (u32) NULL; - host_res->dw_dmmu_base = NULL; host_res->dw_sys_ctrl_base = NULL; kfree(host_res); diff --git a/drivers/dsp/bridge/core/tiomap_io.c b/drivers/dsp/bridge/core/tiomap_io.c index 3c0d3a3..2f2f8c2 100644 --- a/drivers/dsp/bridge/core/tiomap_io.c +++ b/drivers/dsp/bridge/core/tiomap_io.c @@ -437,7 +437,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) omap_mbox_restore_ctx(dev_context->mbox); /* Access MMU SYS CONFIG register to generate a short wakeup */ - __raw_readl(resources->dw_dmmu_base + 0x10); + iommu_read_reg(dev_context->dsp_mmu, MMU_SYSCONFIG); dev_context->dw_brd_state = BRD_RUNNING; } else if (dev_context->dw_brd_state == BRD_RETENTION) { diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c index c6e38e5..7804479 100644 --- a/drivers/dsp/bridge/rmgr/drv.c +++ b/drivers/dsp/bridge/rmgr/drv.c @@ -829,7 +829,6 @@ static int request_bridge_resources(struct cfg_hostres *res) host_res->dw_sys_ctrl_base = ioremap(OMAP_SYSC_BASE, OMAP_SYSC_SIZE); dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", host_res->dw_mem_base[0]); dev_dbg(bridge, "dw_mem_base[3] 0x%x\n", host_res->dw_mem_base[3]); - dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base); /* for 24xx base port is not mapping the mamory for DSP * internal memory TODO Do a ioremap here */ @@ -883,8 +882,6 @@ int drv_request_bridge_res_dsp(void **phost_resources) OMAP_PER_PRM_SIZE); host_res->dw_core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE, OMAP_CORE_PRM_SIZE); - host_res->dw_dmmu_base = ioremap(OMAP_DMMU_BASE, - OMAP_DMMU_SIZE); dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", host_res->dw_mem_base[0]); @@ -896,7 +893,6 @@ int drv_request_bridge_res_dsp(void **phost_resources) host_res->dw_mem_base[3]); dev_dbg(bridge, "dw_mem_base[4] 0x%x\n", host_res->dw_mem_base[4]); - dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base); shm_size = drv_datap->shm_size; if (shm_size >= 0x10000) { From patchwork Wed May 26 20:48:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Dumazet X-Patchwork-Id: 102506 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4QKnZhD027233 for ; Wed, 26 May 2010 20:49:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932892Ab0EZUtD (ORCPT ); Wed, 26 May 2010 16:49:03 -0400 Received: from mail-fx0-f46.google.com ([209.85.161.46]:58839 "EHLO mail-fx0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753981Ab0EZUtA (ORCPT ); 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Wed, 26 May 2010 13:48:57 -0700 (PDT) Received: from [127.0.0.1] ([85.17.35.125]) by mx.google.com with ESMTPS id 2sm2128596faf.15.2010.05.26.13.48.54 (version=SSLv3 cipher=RC4-MD5); Wed, 26 May 2010 13:48:56 -0700 (PDT) Subject: RE: NULL Pointer Deference: NFS & Telnet From: Eric Dumazet To: "Arce, Abraham" Cc: David Miller , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-nfs@vger.kernel.org" , "linux-omap@vger.kernel.org" , "tony@atomide.com" , "Shilimkar, Santosh" , "Ha, Tristram" In-Reply-To: <27F9C60D11D683428E133F85D2BB4A53043E3EE6A3@dlee03.ent.ti.com> References: <27F9C60D11D683428E133F85D2BB4A53043E33A997@dlee03.ent.ti.com> <27F9C60D11D683428E133F85D2BB4A53043E3EDFE6@dlee03.ent.ti.com> <20100525.185236.193707791.davem@davemloft.net> <27F9C60D11D683428E133F85D2BB4A53043E3EDFF1@dlee03.ent.ti.com> <1274851741.25136.16.camel@edumazet-laptop> <27F9C60D11D683428E133F85D2BB4A53043E3EE6A3@dlee03.ent.ti.com> Date: Wed, 26 May 2010 22:48:53 +0200 Message-ID: <1274906933.2542.17.camel@edumazet-laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 26 May 2010 20:49:35 +0000 (UTC) diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c index b4fb07a..05bd312 100644 --- a/drivers/net/ks8851.c +++ b/drivers/net/ks8851.c @@ -503,8 +503,9 @@ static void ks8851_rx_pkts(struct ks8851_net *ks) ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr | RXQCR_SDA | RXQCR_ADRFE); - if (rxlen > 0) { - skb = netdev_alloc_skb(ks->netdev, rxlen + 2 + 8); + if (rxlen > 4) { + rxlen -= 4; + skb = netdev_alloc_skb(ks->netdev, 2 + 8 + ALIGN(rxlen, 4)); if (!skb) { /* todo - dump frame and move on */ } @@ -513,7 +514,7 @@ static void ks8851_rx_pkts(struct ks8851_net *ks) * for the status header and 4 bytes of garbage */ skb_reserve(skb, 2 + 4 + 4); - rxpkt = skb_put(skb, rxlen - 4) - 8; + rxpkt = skb_put(skb, rxlen) - 8; /* align the packet length to 4 bytes, and add 4 bytes * as we're getting the rx status header as well */ @@ -526,7 +527,7 @@ static void ks8851_rx_pkts(struct ks8851_net *ks) netif_rx(skb); ks->netdev->stats.rx_packets++; - ks->netdev->stats.rx_bytes += rxlen - 4; + ks->netdev->stats.rx_bytes += rxlen; } ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr); From patchwork Tue Jun 22 15:01:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107402 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF00MV017121 for ; Tue, 22 Jun 2010 15:01:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758604Ab0FVPB3 (ORCPT ); Tue, 22 Jun 2010 11:01:29 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41816 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756413Ab0FVPB2 (ORCPT ); Tue, 22 Jun 2010 11:01:28 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1Nlm024611 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:25 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZj026711; Tue, 22 Jun 2010 20:31:20 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 03/13] OMAP: GPIO: Include platform_data structure for GPIO Date: Tue, 22 Jun 2010 20:31:46 +0530 Message-Id: <1277218916-15213-4-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-3-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> <1277218916-15213-3-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:30 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index de1c604..212ce22 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -28,6 +28,7 @@ #include #include +#include #define OMAP1_MPUIO_BASE 0xfffb5000 @@ -71,6 +72,25 @@ IH_MPUIO_BASE + ((nr) & 0x0f) : \ IH_GPIO_BASE + (nr)) +#define METHOD_MPUIO 0 +#define METHOD_GPIO_1510 1 +#define METHOD_GPIO_1610 2 +#define METHOD_GPIO_7XX 3 +#define METHOD_GPIO_24XX 5 +#define METHOD_GPIO_44XX 6 + +struct omap_gpio_dev_attr { + int gpio_bank_width; /* GPIO bank width */ + bool dbck_flag; /* dbck validity - True only for OMAP3&4 */ + bool omap1_ick_flag; /* OMAP1 ick - True only for OMAP15xx */ +}; + +struct omap_gpio_platform_data { + u16 virtual_irq_start; + int bank_type; + struct omap_gpio_dev_attr *gpio_attr; +}; + extern int omap_gpio_init(void); /* Call from board init only */ extern void omap2_gpio_prepare_for_idle(int power_state); extern void omap2_gpio_resume_after_idle(void); From patchwork Sun Jul 18 04:23:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 112586 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6I4NetR026117 for ; Sun, 18 Jul 2010 04:23:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751286Ab0GREXi (ORCPT ); Sun, 18 Jul 2010 00:23:38 -0400 Received: from d1.icnet.pl ([212.160.220.21]:56088 "EHLO d1.icnet.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750717Ab0GREXh (ORCPT ); Sun, 18 Jul 2010 00:23:37 -0400 Received: from 87-205-12-81.ip.netia.com.pl ([87.205.12.81] helo=vclass.intranet) by d1.icnet.pl with asmtp (TLS-1.0:DHE_RSA_AES_128_CBC_SHA:16) (Exim 4.34) id 1OaLPc-0007I9-JM; Sun, 18 Jul 2010 06:23:36 +0200 From: Janusz Krzysztofik Organization: Tele-Info-System, Poznan, PL To: "linux-omap@vger.kernel.org" Subject: [RFC] [PATCH 2/6] OMAP1: Add support for SoC camera interface Date: Sun, 18 Jul 2010 06:23:09 +0200 User-Agent: KMail/1.9.10 Cc: linux-media@vger.kernel.org, Guennadi Liakhovetski , Tony Lindgren , "Discussion of the Amstrad E3 emailer hardware/software" References: <201007180618.08266.jkrzyszt@tis.icnet.pl> In-Reply-To: <201007180618.08266.jkrzyszt@tis.icnet.pl> MIME-Version: 1.0 Content-Disposition: inline Message-Id: <201007180623.10663.jkrzyszt@tis.icnet.pl> X-SA-Exim-Scanned: No (on d1.icnet); SAEximRunCond expanded to false Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 18 Jul 2010 04:23:40 +0000 (UTC) --- linux-2.6.35-rc3.orig/arch/arm/mach-omap1/devices.c 2010-06-26 15:54:47.000000000 +0200 +++ linux-2.6.35-rc3/arch/arm/mach-omap1/devices.c 2010-07-18 01:54:39.000000000 +0200 @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include /*-------------------------------------------------------------------------*/ @@ -267,6 +269,47 @@ static inline void omap_init_sti(void) static inline void omap_init_sti(void) {} #endif + +#define OMAP1_CAMERA_BASE 0xfffb6800 + +static struct resource omap1_camera_resources[] = { + [0] = { + .start = OMAP1_CAMERA_BASE, + .end = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_CAMERA, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device omap1_camera_device = { + .name = "omap1-camera", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &omap1_camera_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(omap1_camera_resources), + .resource = omap1_camera_resources, +}; + +void __init omap1_set_camera_info(struct omap1_cam_platform_data *info) +{ + struct platform_device *dev = &omap1_camera_device; + int ret; + + dev->dev.platform_data = info; + + ret = platform_device_register(dev); + if (ret) + dev_err(&dev->dev, "unable to register device: %d\n", ret); +} + + /*-------------------------------------------------------------------------*/ /* --- linux-2.6.35-rc3.orig/arch/arm/mach-omap1/include/mach/camera.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.35-rc3/arch/arm/mach-omap1/include/mach/camera.h 2010-07-18 01:57:18.000000000 +0200 @@ -0,0 +1,8 @@ +#ifndef __ASM_ARCH_CAMERA_H_ +#define __ASM_ARCH_CAMERA_H_ + +#include + +extern void omap1_set_camera_info(struct omap1_cam_platform_data *); + +#endif /* __ASM_ARCH_CAMERA_H_ */ From patchwork Sun Jul 18 04:21:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 112584 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6I4LjO4025898 for ; Sun, 18 Jul 2010 04:21:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751122Ab0GREVn (ORCPT ); Sun, 18 Jul 2010 00:21:43 -0400 Received: from d1.icnet.pl ([212.160.220.21]:55747 "EHLO d1.icnet.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750717Ab0GREVl (ORCPT ); Sun, 18 Jul 2010 00:21:41 -0400 Received: from 87-205-12-81.ip.netia.com.pl ([87.205.12.81] helo=vclass.intranet) by d1.icnet.pl with asmtp (TLS-1.0:DHE_RSA_AES_128_CBC_SHA:16) (Exim 4.34) id 1OaLNj-000787-9W; Sun, 18 Jul 2010 06:21:40 +0200 From: Janusz Krzysztofik Organization: Tele-Info-System, Poznan, PL To: linux-media@vger.kernel.org Subject: [RFC] [PATCH 1/6] SoC Camera: add driver for OMAP1 camera interface Date: Sun, 18 Jul 2010 06:21:11 +0200 User-Agent: KMail/1.9.10 Cc: Guennadi Liakhovetski , "linux-omap@vger.kernel.org" , Tony Lindgren , "Discussion of the Amstrad E3 emailer hardware/software" References: <201007180618.08266.jkrzyszt@tis.icnet.pl> In-Reply-To: <201007180618.08266.jkrzyszt@tis.icnet.pl> MIME-Version: 1.0 Content-Disposition: inline Message-Id: <201007180621.13347.jkrzyszt@tis.icnet.pl> X-SA-Exim-Scanned: No (on d1.icnet); SAEximRunCond expanded to false Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 18 Jul 2010 04:21:46 +0000 (UTC) --- linux-2.6.35-rc3.orig/include/media/omap1_camera.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.35-rc3/include/media/omap1_camera.h 2010-07-18 01:31:57.000000000 +0200 @@ -0,0 +1,16 @@ +#ifndef __MEDIA_OMAP1_CAMERA_H_ +#define __MEDIA_OMAP1_CAMERA_H_ + +#define OMAP1_CAMERA_IOSIZE 0x1c + +struct omap1_cam_platform_data { + unsigned long camexclk_khz; + unsigned long lclk_khz_max; + unsigned long flags; +}; + +#define OMAP1_CAMERA_LCLK_RISING BIT(0) +#define OMAP1_CAMERA_RST_LOW BIT(1) +#define OMAP1_CAMERA_RST_HIGH BIT(2) + +#endif /* __MEDIA_OMAP1_CAMERA_H_ */ --- linux-2.6.35-rc3.orig/drivers/media/video/Kconfig 2010-06-26 15:55:29.000000000 +0200 +++ linux-2.6.35-rc3/drivers/media/video/Kconfig 2010-07-02 04:12:02.000000000 +0200 @@ -962,6 +962,20 @@ config VIDEO_SH_MOBILE_CEU ---help--- This is a v4l2 driver for the SuperH Mobile CEU Interface +config VIDEO_OMAP1 + tristate "OMAP1 Camera Interface driver" + depends on VIDEO_DEV && ARCH_OMAP1 && SOC_CAMERA + select VIDEOBUF_DMA_CONTIG if !VIDEO_OMAP1_SG + ---help--- + This is a v4l2 driver for the TI OMAP1 camera interface + +if VIDEO_OMAP1 +config VIDEO_OMAP1_SG + bool "Scatter-gather mode" + depends on VIDEO_OMAP1 && EXPERIMENTAL + select VIDEOBUF_DMA_SG +endif + config VIDEO_OMAP2 tristate "OMAP2 Camera Capture Interface driver" depends on VIDEO_DEV && ARCH_OMAP2 --- linux-2.6.35-rc3.orig/drivers/media/video/Makefile 2010-06-26 15:55:29.000000000 +0200 +++ linux-2.6.35-rc3/drivers/media/video/Makefile 2010-06-26 17:28:09.000000000 +0200 @@ -165,6 +165,7 @@ obj-$(CONFIG_VIDEO_MX1) += mx1_camera. obj-$(CONFIG_VIDEO_MX3) += mx3_camera.o obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o +obj-$(CONFIG_VIDEO_OMAP1) += omap1_camera.o obj-$(CONFIG_ARCH_DAVINCI) += davinci/ --- linux-2.6.35-rc3.orig/drivers/media/video/omap1_camera.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.35-rc3/drivers/media/video/omap1_camera.c 2010-07-18 01:32:48.000000000 +0200 @@ -0,0 +1,1656 @@ +/* + * V4L2 SoC Camera driver for OMAP1 Camera Interface + * + * Copyright (C) 2010, Janusz Krzysztofik + * + * Based on V4L2 Driver for i.MXL/i.MXL camera (CSI) host + * Copyright (C) 2008, Paulius Zaleckas + * Copyright (C) 2009, Darius Augulis + * + * Based on PXA SoC camera driver + * Copyright (C) 2006, Sascha Hauer, Pengutronix + * Copyright (C) 2008, Guennadi Liakhovetski + * + * Hardware specific bits initialy based on former work by Matt Callow + * drivers/media/video/omap/omap1510cam.c + * Copyright (C) 2006 Matt Callow + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#ifndef CONFIG_VIDEO_OMAP1_SG +#include +#else +#include +#endif + +#include + + +#define DRIVER_NAME "omap1-camera" +#define VERSION_CODE KERNEL_VERSION(0, 0, 1) + + +/* + * --------------------------------------------------------------------------- + * OMAP1 Camera Interface registers + * --------------------------------------------------------------------------- + */ + +#define REG_CTRLCLOCK 0x00 +#define REG_IT_STATUS 0x04 +#define REG_MODE 0x08 +#define REG_STATUS 0x0C +#define REG_CAMDATA 0x10 +#define REG_GPIO 0x14 +#define REG_PEAK_COUNTER 0x18 + +/* CTRLCLOCK bit shifts */ +#define LCLK_EN BIT(7) +#define DPLL_EN BIT(6) +#define MCLK_EN BIT(5) +#define CAMEXCLK_EN BIT(4) +#define POLCLK BIT(3) +#define FOSCMOD_SHIFT 0 +#define FOSCMOD_MASK (0x7 << FOSCMOD_SHIFT) +#define FOSCMOD_12MHz 0x0 +#define FOSCMOD_6MHz 0x2 +#define FOSCMOD_9_6MHz 0x4 +#define FOSCMOD_24MHz 0x5 +#define FOSCMOD_8MHz 0x6 + +/* IT_STATUS bit shifts */ +#define DATA_TRANSFER BIT(5) +#define FIFO_FULL BIT(4) +#define H_DOWN BIT(3) +#define H_UP BIT(2) +#define V_DOWN BIT(1) +#define V_UP BIT(0) + +/* MODE bit shifts */ +#define RAZ_FIFO BIT(18) +#define EN_FIFO_FULL BIT(17) +#define EN_NIRQ BIT(16) +#define THRESHOLD_SHIFT 9 +#define THRESHOLD_MASK (0x7f << THRESHOLD_SHIFT) +#define DMA BIT(8) +#define EN_H_DOWN BIT(7) +#define EN_H_UP BIT(6) +#define EN_V_DOWN BIT(5) +#define EN_V_UP BIT(4) +#define ORDERCAMD BIT(3) + +#define IRQ_MASK (EN_V_UP | EN_V_DOWN | EN_H_UP | EN_H_DOWN | \ + EN_NIRQ | EN_FIFO_FULL) + +/* STATUS bit shifts */ +#define HSTATUS BIT(1) +#define VSTATUS BIT(0) + +/* GPIO bit shifts */ +#define CAM_RST BIT(0) + +/* end of OMAP1 Camera Interface registers */ + + +#define SOCAM_BUS_FLAGS (SOCAM_MASTER | \ + SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH | \ + SOCAM_PCLK_SAMPLE_RISING | SOCAM_PCLK_SAMPLE_FALLING | \ + SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8) + + +#define CAM_EXCLK_6MHz 6000000 +#define CAM_EXCLK_8MHz 8000000 +#define CAM_EXCLK_9_6MHz 9600000 +#define CAM_EXCLK_12MHz 12000000 +#define CAM_EXCLK_24MHz 24000000 + + +#define FIFO_SIZE ((THRESHOLD_MASK >> THRESHOLD_SHIFT) + 1) +#define FIFO_SHIFT __fls(FIFO_SIZE) + +#define DMA_BURST_SHIFT (1 + OMAP_DMA_DATA_BURST_4) +#define DMA_BURST_SIZE (1 << DMA_BURST_SHIFT) + +#define DMA_ELEMENT_SHIFT OMAP_DMA_DATA_TYPE_S32 +#define DMA_ELEMENT_SIZE (1 << DMA_ELEMENT_SHIFT) + +#ifndef CONFIG_VIDEO_OMAP1_SG +#define DMA_FRAME_SHIFT (FIFO_SHIFT - 1) +#define MIN_BUF_COUNT 3 +#else +#define DMA_FRAME_SHIFT DMA_BURST_SHIFT +#define MIN_BUF_COUNT 2 +#endif + +#define DMA_FRAME_SIZE (1 << DMA_FRAME_SHIFT) +#define DMA_SYNC OMAP_DMA_SYNC_FRAME +#define THRESHOLD_LEVEL DMA_FRAME_SIZE + + +#define MAX_VIDEO_MEM 4 /* arbitrary video memory limit in MB */ + + +/* + * Structures + */ + +/* buffer for one video frame */ +struct omap1_cam_buf { + struct videobuf_buffer vb; + enum v4l2_mbus_pixelcode code; + int inwork; +#ifdef CONFIG_VIDEO_OMAP1_SG + struct scatterlist *sgbuf; + int sgcount; + int bytes_left; + enum videobuf_state result; +#endif +}; + +struct omap1_cam_dev { + struct soc_camera_host soc_host; + struct soc_camera_device *icd; + struct clk *clk; + + unsigned int irq; + void __iomem *base; + + int dma_ch; + + struct omap1_cam_platform_data *pdata; + struct resource *res; + unsigned long pflags; + unsigned long camexclk; + + struct list_head capture; + + spinlock_t lock; + + /* Pointers to DMA buffers */ + struct omap1_cam_buf *active; + struct omap1_cam_buf *ready; + + u32 reg_cache[OMAP1_CAMERA_IOSIZE / sizeof(u32)]; +}; + + +void cam_write(struct omap1_cam_dev *pcdev, u16 reg, u32 val) +{ + pcdev->reg_cache[reg / sizeof(u32)] = val; + __raw_writel(val, pcdev->base + reg); +} + +int cam_read(struct omap1_cam_dev *pcdev, u16 reg, bool from_cache) +{ + return !from_cache ? __raw_readl(pcdev->base + reg) : + pcdev->reg_cache[reg / sizeof(u32)]; +} + +#define CAM_READ(pcdev, reg) \ + cam_read(pcdev, REG_##reg, 0) +#define CAM_WRITE(pcdev, reg, val) \ + cam_write(pcdev, REG_##reg, val) +#define CAM_READ_CACHE(pcdev, reg) \ + cam_read(pcdev, REG_##reg, 1) + +/* + * Videobuf operations + */ +static int omap1_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, + unsigned int *size) +{ + struct soc_camera_device *icd = vq->priv_data; + int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + + if (bytes_per_line < 0) + return bytes_per_line; + + *size = bytes_per_line * icd->user_height; + + if (!*count || *count < MIN_BUF_COUNT) + *count = MIN_BUF_COUNT; + + if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) + *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; + + dev_dbg(icd->dev.parent, + "%s: count=%d, size=%d\n", __func__, *count, *size); + + return 0; +} + +static void free_buffer(struct videobuf_queue *vq, struct omap1_cam_buf *buf) +{ + struct videobuf_buffer *vb = &buf->vb; +#ifdef CONFIG_VIDEO_OMAP1_SG + struct videobuf_dmabuf *dma = videobuf_to_dma(vb); +#endif + + BUG_ON(in_interrupt()); + + videobuf_waiton(vb, 0, 0); +#ifndef CONFIG_VIDEO_OMAP1_SG + videobuf_dma_contig_free(vq, vb); +#else + videobuf_dma_unmap(vq, dma); + videobuf_dma_free(dma); +#endif + + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static int omap1_videobuf_prepare(struct videobuf_queue *vq, + struct videobuf_buffer *vb, enum v4l2_field field) +{ + struct soc_camera_device *icd = vq->priv_data; + struct omap1_cam_buf *buf = container_of(vb, struct omap1_cam_buf, vb); + int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + int ret; + + if (bytes_per_line < 0) + return bytes_per_line; + + WARN_ON(!list_empty(&vb->queue)); + + BUG_ON(NULL == icd->current_fmt); + + buf->inwork = 1; + + if (buf->code != icd->current_fmt->code || + vb->width != icd->user_width || + vb->height != icd->user_height || + vb->field != field) { + buf->code = icd->current_fmt->code; + vb->width = icd->user_width; + vb->height = icd->user_height; + vb->field = field; + vb->state = VIDEOBUF_NEEDS_INIT; + } + + vb->size = bytes_per_line * vb->height; + + if (vb->baddr && vb->bsize < vb->size) { + ret = -EINVAL; + goto out; + } + + if (vb->state == VIDEOBUF_NEEDS_INIT) { + ret = videobuf_iolock(vq, vb, NULL); + if (ret) + goto fail; + + vb->state = VIDEOBUF_PREPARED; + } + buf->inwork = 0; + + return 0; +fail: + free_buffer(vq, buf); +out: + buf->inwork = 0; + return ret; +} + +static void set_dma_dest_params(int dma_ch, struct omap1_cam_buf *buf) +{ +#ifndef CONFIG_VIDEO_OMAP1_SG + dma_addr_t dma_addr = videobuf_to_dma_contig(&buf->vb); + unsigned int block_size = buf->vb.size; +#else + dma_addr_t dma_addr; + unsigned int block_size; + + if (WARN_ON(!buf->sgbuf)) { + buf->result = VIDEOBUF_ERROR; + return; + } + dma_addr = sg_dma_address(buf->sgbuf); + if (WARN_ON(!dma_addr)) { + buf->sgbuf = NULL; + buf->result = VIDEOBUF_ERROR; + return; + } + block_size = sg_dma_len(buf->sgbuf); + if (WARN_ON(!block_size)) { + buf->sgbuf = NULL; + buf->result = VIDEOBUF_ERROR; + return; + } + if (unlikely(buf->bytes_left < block_size)) + block_size = buf->bytes_left; + if (WARN_ON(dma_addr & (DMA_FRAME_SIZE * DMA_ELEMENT_SIZE - 1))) { + dma_addr = ALIGN(dma_addr, DMA_FRAME_SIZE * DMA_ELEMENT_SIZE); + block_size &= ~(DMA_FRAME_SIZE * DMA_ELEMENT_SIZE - 1); + } + buf->bytes_left -= block_size; + buf->sgcount++; +#endif + omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_EMIFF, + OMAP_DMA_AMODE_POST_INC, dma_addr, 0, 0); + omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, + DMA_FRAME_SIZE, block_size >> (DMA_FRAME_SHIFT + + DMA_ELEMENT_SHIFT), DMA_SYNC, 0, 0); +} + +#ifdef CONFIG_VIDEO_OMAP1_SG +static struct scatterlist *try_next_sgbuf(int dma_ch, struct omap1_cam_buf *buf) +{ + struct scatterlist *sgbuf; + + if (likely(buf->sgbuf)) { + + if (unlikely(!buf->bytes_left)) { + /* indicate sglist complete */ + sgbuf = NULL; + } else { + sgbuf = sg_next(buf->sgbuf); + if (WARN_ON(!sgbuf)) { + buf->result = VIDEOBUF_ERROR; + } else if (WARN_ON(!sg_dma_len(sgbuf))) { + sgbuf = NULL; + buf->result = VIDEOBUF_ERROR; + } + } + buf->sgbuf = sgbuf; + } else { + struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); + + buf->sgbuf = sgbuf = dma->sglist; + if (sgbuf) { + buf->sgcount = 0; + buf->bytes_left = buf->vb.size; + buf->result = VIDEOBUF_DONE; + } + } + if (sgbuf) + set_dma_dest_params(dma_ch, buf); + + return sgbuf; +} +#endif + +static struct omap1_cam_buf *prepare_next_vb(struct omap1_cam_dev *pcdev) +{ + struct omap1_cam_buf *buf; + + buf = pcdev->ready; + if (!buf) { + if (list_empty(&pcdev->capture)) + return buf; + buf = list_entry(pcdev->capture.next, + struct omap1_cam_buf, vb.queue); + buf->vb.state = VIDEOBUF_ACTIVE; + pcdev->ready = buf; + list_del_init(&buf->vb.queue); + } +#ifndef CONFIG_VIDEO_OMAP1_SG + set_dma_dest_params(pcdev->dma_ch, buf); +#else + buf->sgbuf = NULL; +#endif + return buf; +} + +static void start_capture(struct omap1_cam_dev *pcdev) +{ + struct omap1_cam_buf *buf = pcdev->active; + unsigned long ctrlclock = CAM_READ_CACHE(pcdev, CTRLCLOCK); + unsigned long mode = CAM_READ_CACHE(pcdev, MODE); + + if (WARN_ON(!buf)) + return; + +#ifndef CONFIG_VIDEO_OMAP1_SG + /* don't enable end of frame interrupts before capture autostart */ + mode &= ~EN_V_DOWN; +#endif + if (WARN_ON(mode & RAZ_FIFO)) + /* clean up possibly insane reset condition */ + CAM_WRITE(pcdev, MODE, mode &= ~RAZ_FIFO); + + if (unlikely(ctrlclock & LCLK_EN)) + /* stop pixel clock before FIFO reset */ + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN); + /* reset FIFO */ + CAM_WRITE(pcdev, MODE, mode | RAZ_FIFO); + + omap_start_dma(pcdev->dma_ch); + + /* (re)enable pixel clock */ + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock | LCLK_EN); + /* release FIFO reset */ + CAM_WRITE(pcdev, MODE, mode); + +#ifdef CONFIG_VIDEO_OMAP1_SG + try_next_sgbuf(pcdev->dma_ch, buf); +#endif +} + +static void suspend_capture(struct omap1_cam_dev *pcdev) +{ + unsigned long ctrlclock = CAM_READ_CACHE(pcdev, CTRLCLOCK); + + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN); + omap_stop_dma(pcdev->dma_ch); +} + +static void disable_capture(struct omap1_cam_dev *pcdev) +{ + unsigned long mode = CAM_READ_CACHE(pcdev, MODE); + + CAM_WRITE(pcdev, MODE, mode & ~(IRQ_MASK | DMA)); +} + +static void omap1_videobuf_queue(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct soc_camera_device *icd = vq->priv_data; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct omap1_cam_dev *pcdev = ici->priv; + struct omap1_cam_buf *buf; + unsigned long mode; + + list_add_tail(&vb->queue, &pcdev->capture); + vb->state = VIDEOBUF_QUEUED; + + if (pcdev->active) + return; + + WARN_ON(pcdev->ready); + + buf = prepare_next_vb(pcdev); + if (WARN_ON(!buf)) + return; + + pcdev->active = buf; + pcdev->ready = NULL; + + dev_dbg(icd->dev.parent, "%s: capture not active, setup FIFO, start DMA" + "\n", __func__); + mode = CAM_READ_CACHE(pcdev, MODE) & (THRESHOLD_MASK | ORDERCAMD); + mode |= EN_FIFO_FULL | DMA; +#ifndef CONFIG_VIDEO_OMAP1_SG + CAM_WRITE(pcdev, MODE, mode | EN_V_UP); +#else + CAM_WRITE(pcdev, MODE, mode | EN_V_DOWN); + + try_next_sgbuf(pcdev->dma_ch, buf); +#endif + start_capture(pcdev); +} + +static void omap1_videobuf_release(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct omap1_cam_buf *buf = + container_of(vb, struct omap1_cam_buf, vb); + struct soc_camera_device *icd = vq->priv_data; + struct device *dev = icd->dev.parent; + + switch (vb->state) { + case VIDEOBUF_DONE: + dev_dbg(dev, "%s (done)\n", __func__); + break; + case VIDEOBUF_ACTIVE: + dev_dbg(dev, "%s (active)\n", __func__); + break; + case VIDEOBUF_QUEUED: + dev_dbg(dev, "%s (queued)\n", __func__); + break; + case VIDEOBUF_PREPARED: + dev_dbg(dev, "%s (prepared)\n", __func__); + break; + default: + dev_dbg(dev, "%s (unknown)\n", __func__); + break; + } + + free_buffer(vq, buf); +} + +static void videobuf_done(struct omap1_cam_dev *pcdev, + enum videobuf_state result) +{ + struct omap1_cam_buf *buf = pcdev->active; + struct videobuf_buffer *vb; + struct device *dev = pcdev->icd->dev.parent; + + if (WARN_ON(!buf)) { + suspend_capture(pcdev); + disable_capture(pcdev); + return; + } + + if (result == VIDEOBUF_ERROR) + suspend_capture(pcdev); + + vb = &buf->vb; + if (waitqueue_active(&vb->done)) { + if (!pcdev->ready && result != VIDEOBUF_ERROR) + suspend_capture(pcdev); + vb->state = result; + do_gettimeofday(&vb->ts); + vb->field_count++; + wake_up(&vb->done); + + pcdev->active = buf = pcdev->ready; + pcdev->ready = NULL; + + if (!buf) { + result = VIDEOBUF_ERROR; + prepare_next_vb(pcdev); + + pcdev->active = buf = pcdev->ready; + pcdev->ready = NULL; + } + } else if (pcdev->ready) { + dev_dbg(dev, "%s: nobody waiting on videobuf, swap with next\n", + __func__); + pcdev->active = pcdev->ready; +#ifdef CONFIG_VIDEO_OMAP1_SG + buf->sgbuf = NULL; +#endif + pcdev->ready = buf; + + buf = pcdev->active; + } else { +#ifndef CONFIG_VIDEO_OMAP1_SG + dev_dbg(dev, "%s: nobody waiting on videobuf, reuse it\n", + __func__); +#else + if (result != VIDEOBUF_ERROR) { + suspend_capture(pcdev); + result = VIDEOBUF_ERROR; + } + prepare_next_vb(pcdev); +#endif + } + + if (!buf) { + dev_dbg(dev, "%s: no more videobufs, stop capture\n", __func__); + disable_capture(pcdev); + return; + } + +#ifdef CONFIG_VIDEO_OMAP1_SG + if (result == VIDEOBUF_ERROR) + buf->sgbuf = NULL; + + try_next_sgbuf(pcdev->dma_ch, buf); +#endif + + if (result == VIDEOBUF_ERROR) { + dev_dbg(dev, "%s: videobuf error; reset FIFO, restart DMA\n", + __func__); + start_capture(pcdev); + } + + prepare_next_vb(pcdev); +} + +static void dma_isr(int channel, unsigned short status, void *data) +{ + struct omap1_cam_dev *pcdev = data; + struct omap1_cam_buf *buf = pcdev->active; + enum videobuf_state result; + unsigned long flags; + + spin_lock_irqsave(&pcdev->lock, flags); + + if (WARN_ON(!buf)) { + suspend_capture(pcdev); + disable_capture(pcdev); + goto out; + } + +#ifndef CONFIG_VIDEO_OMAP1_SG + /* videobuf complete, disable end of frame interrupt for this frame */ + CAM_WRITE(pcdev, MODE, CAM_READ_CACHE(pcdev, MODE) & ~EN_V_DOWN); + result = VIDEOBUF_DONE; +#else + if (buf->sgbuf) { + /* current sglist not complete yet */ + try_next_sgbuf(pcdev->dma_ch, buf); + if (buf->sgbuf) + goto out; + + if (buf->result != VIDEOBUF_ERROR) { + buf = prepare_next_vb(pcdev); + if (!buf) + goto out; + + try_next_sgbuf(pcdev->dma_ch, buf); + goto out; + } + } + /* end of videobuf */ + result = buf->result; +#endif + videobuf_done(pcdev, result); +out: + spin_unlock_irqrestore(&pcdev->lock, flags); +} + +static irqreturn_t cam_isr(int irq, void *data) +{ + struct omap1_cam_dev *pcdev = data; + struct device *dev = pcdev->icd->dev.parent; + struct omap1_cam_buf *buf = pcdev->active; + unsigned long it_status; + unsigned long flags; + + it_status = CAM_READ(pcdev, IT_STATUS); + if (!it_status) + return IRQ_NONE; + + spin_lock_irqsave(&pcdev->lock, flags); + + if (WARN_ON(!buf)) { + suspend_capture(pcdev); + disable_capture(pcdev); + goto out; + } + + if (unlikely(it_status & FIFO_FULL)) { + dev_warn(dev, "%s: FIFO overflow\n", __func__); + + } else if (it_status & V_DOWN) { +#ifdef CONFIG_VIDEO_OMAP1_SG + /* + * if exactly 2 sgbufs of the next sglist has be used, + * then we are in sync + */ + if (buf && buf->sgcount == 2) + goto out; +#endif + dev_notice(dev, "%s: unexpected end of video frame\n", + __func__); + +#ifndef CONFIG_VIDEO_OMAP1_SG + } else if (it_status & V_UP) { + unsigned long mode = CAM_READ_CACHE(pcdev, MODE); + + if (!(mode & EN_V_DOWN)) { + /* enable end of frame interrupt for current videobuf */ + CAM_WRITE(pcdev, MODE, mode | EN_V_DOWN); + } + goto out; +#endif + + } else { + dev_warn(pcdev->soc_host.v4l2_dev.dev, "%s: " + "unhandled camera interrupt, status == 0x%lx\n", + __func__, it_status); + goto out; + } + + videobuf_done(pcdev, VIDEOBUF_ERROR); +out: + spin_unlock_irqrestore(&pcdev->lock, flags); + return IRQ_HANDLED; +} + +static struct videobuf_queue_ops omap1_videobuf_ops = { + .buf_setup = omap1_videobuf_setup, + .buf_prepare = omap1_videobuf_prepare, + .buf_queue = omap1_videobuf_queue, + .buf_release = omap1_videobuf_release, +}; + + +/* + * SOC Camera host operations + */ + +static void sensor_reset(struct omap1_cam_dev *pcdev, bool reset) +{ + /* apply/release camera sensor reset if requested by platform data */ + if (pcdev->pflags & OMAP1_CAMERA_RST_HIGH) + CAM_WRITE(pcdev, GPIO, reset); + else if (pcdev->pflags & OMAP1_CAMERA_RST_LOW) + CAM_WRITE(pcdev, GPIO, !reset); +} + +/* + * The following two functions absolutely depend on the fact, that + * there can be only one camera on OMAP1 camera sensor interface + */ +static int omap1_cam_add_device(struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct omap1_cam_dev *pcdev = ici->priv; + unsigned int ctrlclock; + int ret = 0; + + if (pcdev->icd) { + ret = -EBUSY; + goto ebusy; + } + + clk_enable(pcdev->clk); + + /* setup sensor clock */ + ctrlclock = CAM_READ(pcdev, CTRLCLOCK); + ctrlclock &= ~(CAMEXCLK_EN | MCLK_EN | DPLL_EN); + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock); + + ctrlclock &= ~FOSCMOD_MASK; + switch (pcdev->camexclk) { + case CAM_EXCLK_6MHz: + ctrlclock |= CAMEXCLK_EN | FOSCMOD_6MHz; + break; + case CAM_EXCLK_8MHz: + ctrlclock |= CAMEXCLK_EN | FOSCMOD_8MHz | DPLL_EN; + break; + case CAM_EXCLK_9_6MHz: + ctrlclock |= CAMEXCLK_EN | FOSCMOD_9_6MHz | DPLL_EN; + break; + case CAM_EXCLK_12MHz: + ctrlclock |= CAMEXCLK_EN | FOSCMOD_12MHz; + break; + case CAM_EXCLK_24MHz: + ctrlclock |= CAMEXCLK_EN | FOSCMOD_24MHz | DPLL_EN; + default: + break; + } + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~DPLL_EN); + + /* enable clock */ + ctrlclock |= MCLK_EN; + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock); + + sensor_reset(pcdev, 0); + + pcdev->icd = icd; + + dev_info(icd->dev.parent, "OMAP1 Camera driver attached to camera %d\n", + icd->devnum); +ebusy: + return ret; +} + +static void omap1_cam_remove_device(struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct omap1_cam_dev *pcdev = ici->priv; + unsigned long ctrlclock; + + BUG_ON(icd != pcdev->icd); + + suspend_capture(pcdev); + disable_capture(pcdev); + + sensor_reset(pcdev, 1); + + /* disable and release system clocks */ + ctrlclock = CAM_READ(pcdev, CTRLCLOCK); + ctrlclock &= ~(MCLK_EN | DPLL_EN | CAMEXCLK_EN); + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock); + + ctrlclock = (ctrlclock & ~FOSCMOD_MASK) | FOSCMOD_12MHz; + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock); + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock | MCLK_EN); + + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~MCLK_EN); + + clk_disable(pcdev->clk); + + pcdev->icd = NULL; + + dev_info(icd->dev.parent, "OMAP1 Camera driver detached from camera %d" + "\n", icd->devnum); +} + +/* Duplicate standard formats based on host capability of byte swapping */ +static const struct soc_mbus_pixelfmt omap1_cam_formats[] = { + [V4L2_MBUS_FMT_YUYV8_2X8_BE] = { + .fourcc = V4L2_PIX_FMT_YUYV, + .name = "YUYV", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, + [V4L2_MBUS_FMT_YVYU8_2X8_BE] = { + .fourcc = V4L2_PIX_FMT_YVYU, + .name = "YVYU", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, + [V4L2_MBUS_FMT_YUYV8_2X8_LE] = { + .fourcc = V4L2_PIX_FMT_UYVY, + .name = "UYVY", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, + [V4L2_MBUS_FMT_YVYU8_2X8_LE] = { + .fourcc = V4L2_PIX_FMT_VYUY, + .name = "VYUY", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, + [V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE] = { + .fourcc = V4L2_PIX_FMT_RGB555, + .name = "RGB555", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, + [V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE] = { + .fourcc = V4L2_PIX_FMT_RGB555X, + .name = "RGB555X", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, + [V4L2_MBUS_FMT_RGB565_2X8_BE] = { + .fourcc = V4L2_PIX_FMT_RGB565, + .name = "RGB565", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, + [V4L2_MBUS_FMT_RGB565_2X8_LE] = { + .fourcc = V4L2_PIX_FMT_RGB565X, + .name = "RGB565X", + .bits_per_sample = 8, + .packing = SOC_MBUS_PACKING_2X8_PADHI, + .order = SOC_MBUS_ORDER_BE, + }, +}; + +static int omap1_cam_get_formats(struct soc_camera_device *icd, + unsigned int idx, struct soc_camera_format_xlate *xlate) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->dev.parent; + int formats = 0, ret; + enum v4l2_mbus_pixelcode code; + const struct soc_mbus_pixelfmt *fmt; + + ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); + if (ret < 0) + /* No more formats */ + return 0; + + fmt = soc_mbus_get_fmtdesc(code); + if (!fmt) { + dev_err(dev, "%s: invalid format code #%d: %d\n", __func__, + idx, code); + return 0; + } + + /* Check support for the requested bits-per-sample */ + if (fmt->bits_per_sample != 8) + return 0; + + switch (code) { + case V4L2_MBUS_FMT_YUYV8_2X8_BE: + case V4L2_MBUS_FMT_YVYU8_2X8_BE: + case V4L2_MBUS_FMT_YUYV8_2X8_LE: + case V4L2_MBUS_FMT_YVYU8_2X8_LE: + case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE: + case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE: + case V4L2_MBUS_FMT_RGB565_2X8_BE: + case V4L2_MBUS_FMT_RGB565_2X8_LE: + formats++; + if (xlate) { + xlate->host_fmt = &omap1_cam_formats[code]; + xlate->code = code; + xlate++; + dev_dbg(dev, "%s: providing format %s " + "as byte swapped code #%d\n", __func__, + omap1_cam_formats[code].name, code); + } + default: + if (xlate) + dev_dbg(dev, "%s: providing format %s " + "in pass-through mode\n", __func__, + fmt->name); + } + formats++; + if (xlate) { + xlate->host_fmt = fmt; + xlate->code = code; + xlate++; + } + + return formats; +} + +static int is_dma_aligned(s32 bytes_per_line, unsigned int height) +{ + int size = bytes_per_line * height; + + return IS_ALIGNED(bytes_per_line, DMA_ELEMENT_SIZE) && + IS_ALIGNED(size, DMA_FRAME_SIZE * DMA_ELEMENT_SIZE); +} + +static int dma_align(int *width, int *height, + const struct soc_mbus_pixelfmt *fmt, bool enlarge) +{ + s32 bytes_per_line = soc_mbus_bytes_per_line(*width, fmt); + + if (bytes_per_line < 0) + return bytes_per_line; + + if (!is_dma_aligned(bytes_per_line, *height)) { + unsigned int pxalign = __fls(bytes_per_line / *width); + unsigned int salign = + DMA_FRAME_SHIFT + DMA_ELEMENT_SHIFT - pxalign; + unsigned int incr = enlarge << salign; + + v4l_bound_align_image(width, DMA_ELEMENT_SIZE >> pxalign, + *width + incr, DMA_ELEMENT_SHIFT - pxalign, + height, 1, *height + incr, 0, salign); + return 0; + } + return 1; +} + +/* returns 1 on g_crop() success, 0 on cropcap() success, <0 on error */ +static int get_crop(struct soc_camera_device *icd, struct v4l2_rect *rect) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->dev.parent; + struct v4l2_crop crop; + int ret; + + crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + ret = v4l2_subdev_call(sd, video, g_crop, &crop); + if (ret == -ENOIOCTLCMD) { + struct v4l2_cropcap cc; + + dev_dbg(dev, "%s: g_crop() missing, trying cropcap() instead" + "\n", __func__); + cc.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + ret = v4l2_subdev_call(sd, video, cropcap, &cc); + if (ret < 0) + return ret; + *rect = cc.defrect; + return 0; + } else if (ret < 0) { + return ret; + } + *rect = crop.c; + return 1; +} + +/* + * returns 1 on g_mbus_fmt() or g_crop() success, 0 on cropcap() success, + * <0 on error + */ +static int get_geometry(struct soc_camera_device *icd, struct v4l2_rect *rect, + enum v4l2_mbus_pixelcode code) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct device *dev = icd->dev.parent; + struct v4l2_mbus_framefmt mf; + int ret; + + ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); + if (ret == -ENOIOCTLCMD) { + struct v4l2_rect c; + + dev_dbg(dev, "%s: g_mbus_fmt() missing, trying g_crop() instead" + "\n", __func__); + ret = get_crop(icd, &c); + if (ret < 0) + return ret; + /* REVISIT: + * Should cropcap() obtained defrect reflect last s_crop()? + * Can we use it here for s_crop() result verification? + */ + if (ret) { + *rect = c; /* use g_crop() result */ + } else { + dev_warn(dev, "%s: current geometry not available\n", + __func__); + return 0; + } + } else if (ret < 0) { + return ret; + } else if (mf.code != code) { + return -EINVAL; + } else { + rect->width = mf.width; + rect->height = mf.height; + } + return 1; +} + +#define subdev_call_with_sense(ret, function, args...) \ +{ \ + struct soc_camera_sense sense = { \ + .master_clock = pcdev->camexclk, \ + .pixel_clock_max = 0, \ + }; \ +\ + if (pcdev->pdata) \ + sense.pixel_clock_max = pcdev->pdata->lclk_khz_max * 1000; \ + icd->sense = &sense; \ + *(ret) = v4l2_subdev_call(sd, video, function, ##args); \ + icd->sense = NULL; \ +\ + if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { \ + if (sense.pixel_clock > sense.pixel_clock_max) { \ + dev_err(dev, "%s: " \ + "pixel clock %lu set by the camera too high!" \ + "\n", __func__, sense.pixel_clock); \ + return -EIO; \ + } \ + } \ +} + +static int omap1_cam_set_crop(struct soc_camera_device *icd, + struct v4l2_crop *crop) +{ + struct v4l2_rect *rect = &crop->c; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct omap1_cam_dev *pcdev = ici->priv; + struct device *dev = icd->dev.parent; + s32 bytes_per_line; + int ret; + + ret = dma_align(&rect->width, &rect->height, icd->current_fmt->host_fmt, + false); + if (ret < 0) { + dev_err(dev, "%s: failed to align %ux%u %s with DMA\n", + __func__, rect->width, rect->height, + icd->current_fmt->host_fmt->name); + return ret; + } + + subdev_call_with_sense(&ret, s_crop, crop); + if (ret < 0) { + dev_warn(dev, "%s: failed to crop to %ux%u@%u:%u\n", __func__, + rect->width, rect->height, rect->left, rect->top); + return ret; + } + + ret = get_geometry(icd, rect, icd->current_fmt->code); + if (ret < 0) { + dev_err(dev, "%s: get_geometry() failed\n", __func__); + return ret; + } + if (!ret) { + dev_warn(dev, "%s: unable to verify s_crop() results\n", + __func__); + } + + bytes_per_line = soc_mbus_bytes_per_line(rect->width, + icd->current_fmt->host_fmt); + if (bytes_per_line < 0) { + dev_err(dev, "%s: soc_mbus_bytes_per_line() failed\n", + __func__); + return bytes_per_line; + } + + ret = is_dma_aligned(bytes_per_line, rect->height); + if (ret < 0) { + dev_err(dev, "%s: is_dma_aligned() failed\n", __func__); + return ret; + } + if (!ret) { + dev_err(dev, "%s: resulting geometry %dx%d not DMA aligned\n", + __func__, rect->width, rect->height); + return -EINVAL; + } + + icd->user_width = rect->width; + icd->user_height = rect->height; + + return ret; +} + +static int omap1_cam_set_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + const struct soc_camera_format_xlate *xlate; + struct device *dev = icd->dev.parent; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct omap1_cam_dev *pcdev = ici->priv; + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_mbus_framefmt mf; + struct v4l2_crop crop; + struct v4l2_rect *rect = &crop.c; + int bytes_per_line; + int ret; + + xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); + if (!xlate) { + dev_warn(dev, "%s: format %x not found\n", __func__, + pix->pixelformat); + return -EINVAL; + } + + bytes_per_line = soc_mbus_bytes_per_line(pix->width, xlate->host_fmt); + if (bytes_per_line < 0) { + dev_err(dev, "%s: soc_mbus_bytes_per_line() failed\n", + __func__); + return bytes_per_line; + } + if (pix->bytesperline && pix->bytesperline != bytes_per_line) { + dev_err(dev, "%s: bytes per line mismatch\n", __func__); + return -EINVAL; + } + ret = is_dma_aligned(bytes_per_line, pix->height); + if (ret < 0) { + dev_err(dev, "%s: is_dma_aligned() failed\n", __func__); + return ret; + } + if (!ret) { + dev_err(dev, "%s: image size %dx%d not DMA aligned\n", + __func__, pix->width, pix->height); + return -EINVAL; + } + + mf.width = pix->width; + mf.height = pix->height; + mf.field = pix->field; + mf.colorspace = pix->colorspace; + mf.code = xlate->code; + + subdev_call_with_sense(&ret, s_mbus_fmt, &mf); + if (ret < 0) { + dev_err(dev, "%s: failed to set format\n", __func__); + return ret; + } + + if (mf.code != xlate->code) { + dev_err(dev, "%s: unexpected pixel code change\n", __func__); + return -EINVAL; + } + icd->current_fmt = xlate; + + pix->field = mf.field; + pix->colorspace = mf.colorspace; + + if (mf.width == pix->width && mf.height == pix->height) + return 0; + + dev_notice(dev, "%s: sensor geometry differs, trying to crop to %dx%d" + "\n", __func__, pix->width, pix->height); + crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + ret = get_crop(icd, rect); + if (ret < 0) { + dev_err(dev, "%s: get_crop() failed\n", __func__); + return ret; + } + + rect->width = pix->width; + rect->height = pix->height; + + subdev_call_with_sense(&ret, s_crop, &crop); + if (ret < 0) { + dev_warn(dev, "%s: failed to crop to %ux%u@%u:%u\n", __func__, + rect->width, rect->height, rect->left, rect->top); + return ret; + } + + ret = get_geometry(icd, rect, xlate->code); + if (ret < 0) { + dev_err(dev, "%s: get_geometry() failed\n", __func__); + return ret; + } + + if (!ret) { + dev_warn(dev, "%s: s_crop() results not verified\n", __func__); + return 0; + } + + if (pix->width != rect->width || pix->height != rect->height) { + dev_err(dev, "%s: tried to set %dx%d, got %dx%d\n", __func__, + pix->width, pix->height, + rect->width, rect->height); + return -EINVAL; + } + return 0; +} + +static int omap1_cam_try_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +{ + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + const struct soc_camera_format_xlate *xlate; + struct device *dev = icd->dev.parent; + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_mbus_framefmt mf, testmf; + const struct soc_mbus_pixelfmt *fmt; + int ret; + + xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); + if (!xlate) { + dev_warn(dev, "%s: format %x not found\n", __func__, + pix->pixelformat); + return -EINVAL; + } + + fmt = xlate->host_fmt; + ret = dma_align(&pix->width, &pix->height, fmt, true); + if (ret < 0) { + dev_err(dev, "%s: failed to align %ux%u %s with DMA\n", + __func__, pix->width, pix->height, fmt->name); + return ret; + } + + mf.width = pix->width; + mf.height = pix->height; + mf.field = pix->field; + mf.colorspace = pix->colorspace; + mf.code = xlate->code; + + /* limit to sensor capabilities */ + ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); + if (ret < 0) { + dev_err(dev, "%s: try_mbus_fmt() failed\n", __func__); + return ret; + } + + pix->field = mf.field; + pix->colorspace = mf.colorspace; + + if (mf.width == pix->width && mf.height == pix->height && + mf.code == xlate->code) + return 0; + + dev_dbg(dev, "%s: geometry changed, recheck alignment\n", __func__); + pix->width = mf.width; + pix->height = mf.height; + + fmt = soc_mbus_get_fmtdesc(mf.code); + ret = dma_align(&pix->width, &pix->height, fmt, false); + if (ret < 0) { + dev_err(dev, "%s: failed to align %ux%u %s with DMA\n", + __func__, pix->width, pix->height, fmt->name); + return ret; + } + if (ret) + return 0; + + testmf.width = pix->width; + testmf.height = pix->height; + testmf.field = mf.field; + testmf.colorspace = mf.colorspace; + testmf.code = mf.code; + + ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &testmf); + if (ret < 0) { + dev_err(dev, "%s: try_mbus_fmt() failed\n", __func__); + return ret; + } + + if (testmf.code != mf.code || testmf.width != mf.width || + testmf.height != mf.height) { + dev_err(dev, "%s: sensor format inconsistency, giving up\n", + __func__); + return -EINVAL; + } + dev_notice(dev, "%s: " + "sensor frame not DMA aligned, will try to crop from set_fmt()" + "\n", __func__); + + return 0; +} + +static void omap1_cam_init_videobuf(struct videobuf_queue *q, + struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct omap1_cam_dev *pcdev = ici->priv; + +#ifndef CONFIG_VIDEO_OMAP1_SG + videobuf_queue_dma_contig_init(q, &omap1_videobuf_ops, icd->dev.parent, + &pcdev->lock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_NONE, + sizeof(struct omap1_cam_buf), + icd); +#else + videobuf_queue_sg_init(q, &omap1_videobuf_ops, icd->dev.parent, + &pcdev->lock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_NONE, + sizeof(struct omap1_cam_buf), + icd); +#endif +} + +static int omap1_cam_reqbufs(struct soc_camera_file *icf, + struct v4l2_requestbuffers *p) +{ + int i; + + /* + * This is for locking debugging only. I removed spinlocks and now I + * check whether .prepare is ever called on a linked buffer, or whether + * a dma IRQ can occur for an in-work or unlinked buffer. Until now + * it hadn't triggered + */ + for (i = 0; i < p->count; i++) { + struct omap1_cam_buf *buf = container_of(icf->vb_vidq.bufs[i], + struct omap1_cam_buf, vb); + buf->inwork = 0; + INIT_LIST_HEAD(&buf->vb.queue); + } + + return 0; +} + +static int omap1_cam_querycap(struct soc_camera_host *ici, + struct v4l2_capability *cap) +{ + /* cap->name is set by the friendly caller:-> */ + strlcpy(cap->card, "OMAP1 Camera", sizeof(cap->card)); + cap->version = VERSION_CODE; + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + + return 0; +} + +static int omap1_cam_set_bus_param(struct soc_camera_device *icd, + __u32 pixfmt) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct omap1_cam_dev *pcdev = ici->priv; + struct device *dev = icd->dev.parent; + const struct soc_camera_format_xlate *xlate; + const struct soc_mbus_pixelfmt *fmt; + unsigned long camera_flags, common_flags; + unsigned int ctrlclock, mode; + int ret; + + camera_flags = icd->ops->query_bus_param(icd); + + common_flags = soc_camera_bus_param_compatible(camera_flags, + SOCAM_BUS_FLAGS); + if (!common_flags) + return -EINVAL; + + /* Make choices, possibly based on platform configuration */ + if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && + (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { + if (!pcdev->pdata || + pcdev->pdata->flags & OMAP1_CAMERA_LCLK_RISING) + common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; + else + common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; + } + + ret = icd->ops->set_bus_param(icd, common_flags); + if (ret < 0) + return ret; + + ctrlclock = CAM_READ_CACHE(pcdev, CTRLCLOCK); + if (ctrlclock & LCLK_EN) + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN); + + if (common_flags & SOCAM_PCLK_SAMPLE_RISING) { + dev_dbg(dev, "CTRLCLOCK_REG |= POLCLK\n"); + ctrlclock |= POLCLK; + } else { + dev_dbg(dev, "CTRLCLOCK_REG &= ~POLCLK\n"); + ctrlclock &= ~POLCLK; + } + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN); + + if (ctrlclock & LCLK_EN) + CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock); + + /* select bus endianess */ + xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); + fmt = xlate->host_fmt; + + if (fmt->order == SOC_MBUS_ORDER_LE) { + dev_dbg(dev, "MODE_REG &= ~ORDERCAMD\n"); + mode = CAM_READ(pcdev, MODE) & ~ORDERCAMD; + } else { + dev_dbg(dev, "MODE_REG |= ORDERCAMD\n"); + mode = CAM_READ(pcdev, MODE) | ORDERCAMD; + } + CAM_WRITE(pcdev, MODE, mode); + + return 0; +} + +static unsigned int omap1_cam_poll(struct file *file, poll_table *pt) +{ + struct soc_camera_file *icf = file->private_data; + struct omap1_cam_buf *buf; + + buf = list_entry(icf->vb_vidq.stream.next, struct omap1_cam_buf, + vb.stream); + + poll_wait(file, &buf->vb.done, pt); + + if (buf->vb.state == VIDEOBUF_DONE || + buf->vb.state == VIDEOBUF_ERROR) + return POLLIN | POLLRDNORM; + + return 0; +} + +static struct soc_camera_host_ops omap1_host_ops = { + .owner = THIS_MODULE, + .add = omap1_cam_add_device, + .remove = omap1_cam_remove_device, + .get_formats = omap1_cam_get_formats, + .set_crop = omap1_cam_set_crop, + .set_fmt = omap1_cam_set_fmt, + .try_fmt = omap1_cam_try_fmt, + .init_videobuf = omap1_cam_init_videobuf, + .reqbufs = omap1_cam_reqbufs, + .querycap = omap1_cam_querycap, + .set_bus_param = omap1_cam_set_bus_param, + .poll = omap1_cam_poll, +}; + +static int __init omap1_cam_probe(struct platform_device *pdev) +{ + struct omap1_cam_dev *pcdev; + struct resource *res; + struct clk *clk; + void __iomem *base; + unsigned int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || (int)irq <= 0) { + err = -ENODEV; + goto exit; + } + + clk = clk_get(&pdev->dev, "armper_ck"); + if (IS_ERR(clk)) { + err = PTR_ERR(clk); + goto exit; + } + + pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); + if (!pcdev) { + dev_err(&pdev->dev, "Could not allocate pcdev\n"); + err = -ENOMEM; + goto exit_put_clk; + } + + pcdev->res = res; + pcdev->clk = clk; + + pcdev->pdata = pdev->dev.platform_data; + pcdev->pflags = pcdev->pdata->flags; + + if (pcdev->pdata) + pcdev->camexclk = pcdev->pdata->camexclk_khz * 1000; + + switch (pcdev->camexclk) { + case CAM_EXCLK_6MHz: + case CAM_EXCLK_8MHz: + case CAM_EXCLK_9_6MHz: + case CAM_EXCLK_12MHz: + case CAM_EXCLK_24MHz: + break; + default: + dev_warn(&pdev->dev, + "Incorrect sensor clock frequency %ld kHz, " + "should be one of 0, 6, 8, 9.6, 12 or 24 MHz, " + "please correct your platform data\n", + pcdev->pdata->camexclk_khz); + pcdev->camexclk = 0; + case 0: + dev_info(&pdev->dev, + "Not providing sensor clock\n"); + } + + INIT_LIST_HEAD(&pcdev->capture); + spin_lock_init(&pcdev->lock); + + /* + * Request the region. + */ + if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) { + err = -EBUSY; + goto exit_kfree; + } + + base = ioremap(res->start, resource_size(res)); + if (!base) { + err = -ENOMEM; + goto exit_release; + } + pcdev->irq = irq; + pcdev->base = base; + + /* apply reset to camera sensor if requested by platform data */ + if (pcdev->pflags & OMAP1_CAMERA_RST_HIGH) + CAM_WRITE(pcdev, GPIO, 0x1); + else if (pcdev->pflags & OMAP1_CAMERA_RST_LOW) + CAM_WRITE(pcdev, GPIO, 0x0); + + err = omap_request_dma(OMAP_DMA_CAMERA_IF_RX, DRIVER_NAME, + dma_isr, (void *)pcdev, &pcdev->dma_ch); + if (err < 0) { + dev_err(&pdev->dev, "Can't request DMA for OMAP1 Camera\n"); + err = -EBUSY; + goto exit_iounmap; + } + dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_ch); + + /* preconfigure DMA */ + omap_set_dma_src_params(pcdev->dma_ch, OMAP_DMA_PORT_TIPB, + OMAP_DMA_AMODE_CONSTANT, res->start + REG_CAMDATA, + 0, 0); + omap_set_dma_dest_burst_mode(pcdev->dma_ch, OMAP_DMA_DATA_BURST_4); + /* setup DMA autoinitialization */ + omap_dma_link_lch(pcdev->dma_ch, pcdev->dma_ch); + + CAM_WRITE(pcdev, MODE, THRESHOLD_LEVEL << THRESHOLD_SHIFT); + + err = request_irq(pcdev->irq, cam_isr, 0, DRIVER_NAME, pcdev); + if (err) { + dev_err(&pdev->dev, "Camera interrupt register failed\n"); + goto exit_free_dma; + } + + pcdev->soc_host.drv_name = DRIVER_NAME; + pcdev->soc_host.ops = &omap1_host_ops; + pcdev->soc_host.priv = pcdev; + pcdev->soc_host.v4l2_dev.dev = &pdev->dev; + pcdev->soc_host.nr = pdev->id; + + err = soc_camera_host_register(&pcdev->soc_host); + if (err) + goto exit_free_irq; + + dev_info(&pdev->dev, "OMAP1 Camera Interface driver loaded\n"); + + return 0; + +exit_free_irq: + free_irq(pcdev->irq, pcdev); +exit_free_dma: + omap_free_dma(pcdev->dma_ch); +exit_iounmap: + iounmap(base); +exit_release: + release_mem_region(res->start, resource_size(res)); +exit_kfree: + kfree(pcdev); +exit_put_clk: + clk_put(clk); +exit: + return err; +} + +static int __exit omap1_cam_remove(struct platform_device *pdev) +{ + struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); + struct omap1_cam_dev *pcdev = container_of(soc_host, + struct omap1_cam_dev, soc_host); + struct resource *res; + + soc_camera_host_unregister(soc_host); + + free_irq(pcdev->irq, pcdev); + + omap_free_dma(pcdev->dma_ch); + + iounmap(pcdev->base); + + res = pcdev->res; + release_mem_region(res->start, resource_size(res)); + + kfree(pcdev); + + clk_put(pcdev->clk); + + dev_info(&pdev->dev, "OMAP1 Camera Interface driver unloaded\n"); + + return 0; +} + +static struct platform_driver omap1_cam_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = omap1_cam_probe, + .remove = __exit_p(omap1_cam_remove), +}; + +static int __init omap1_cam_init(void) +{ + return platform_driver_register(&omap1_cam_driver); +} + +static void __exit omap1_cam_exit(void) +{ + platform_driver_unregister(&omap1_cam_driver); +} + +module_init(omap1_cam_init); +module_exit(omap1_cam_exit); + +MODULE_DESCRIPTION("OMAP1 Camera Interface driver"); +MODULE_AUTHOR("Janusz Krzysztofik "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); From patchwork Thu Jul 8 13:55:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110852 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68DtJcS015742 for ; Thu, 8 Jul 2010 13:55:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757947Ab0GHNzS (ORCPT ); Thu, 8 Jul 2010 09:55:18 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:60814 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757915Ab0GHNzR (ORCPT ); Thu, 8 Jul 2010 09:55:17 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWrZM-00044m-LI; Thu, 08 Jul 2010 13:55:16 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1+qVFSczxltAQ/aZ8cv+Iod Subject: [PATCH 13/13] omap: Devkit8000: Use DIE id to initialize dm9000 MAC address To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: linux-omap@vger.kernel.org, Kan-Ru Chen Date: Thu, 08 Jul 2010 16:55:14 +0300 Message-ID: <20100708135514.26276.25014.stgit@baageli.muru.com> In-Reply-To: <20100708135342.26276.80936.stgit@baageli.muru.com> References: <20100708135342.26276.80936.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 13:55:20 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 19da458..4b7103a 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -556,6 +557,9 @@ static struct platform_device omap_dm9000_dev = { static void __init omap_dm9000_init(void) { + unsigned char *eth_addr = omap_dm9000_platdata.dev_addr; + struct omap_die_id odi; + if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n", OMAP_DM9000_GPIO_IRQ); @@ -563,6 +567,16 @@ static void __init omap_dm9000_init(void) } gpio_direction_input(OMAP_DM9000_GPIO_IRQ); + + /* init the mac address using DIE id */ + omap_get_die_id(&odi); + + eth_addr[0] = 0x02; /* locally administered */ + eth_addr[1] = odi.id_1 & 0xff; + eth_addr[2] = (odi.id_0 & 0xff000000) >> 24; + eth_addr[3] = (odi.id_0 & 0x00ff0000) >> 16; + eth_addr[4] = (odi.id_0 & 0x0000ff00) >> 8; + eth_addr[5] = (odi.id_0 & 0x000000ff); } static struct platform_device *devkit8000_devices[] __initdata = { From patchwork Thu Jul 8 13:55:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110850 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68DtDGv015721 for ; Thu, 8 Jul 2010 13:55:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757919Ab0GHNzL (ORCPT ); Thu, 8 Jul 2010 09:55:11 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:60624 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757915Ab0GHNzK (ORCPT ); Thu, 8 Jul 2010 09:55:10 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWrZF-000416-F7; Thu, 08 Jul 2010 13:55:09 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1+YewV1CyXZUksKYPPqKJft Subject: [PATCH 11/13] omap: Add new interface omap_get_die_id To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: linux-omap@vger.kernel.org, Kan-Ru Chen Date: Thu, 08 Jul 2010 16:55:06 +0300 Message-ID: <20100708135506.26276.73243.stgit@baageli.muru.com> In-Reply-To: <20100708135342.26276.80936.stgit@baageli.muru.com> References: <20100708135342.26276.80936.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 13:55:13 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index ccaa1ed..d079ccf 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -25,6 +25,8 @@ #include #include +#include + static struct omap_chip_id omap_chip; static unsigned int omap_revision; @@ -102,6 +104,14 @@ static struct omap_id omap_ids[] __initdata = { static void __iomem *tap_base; static u16 tap_prod_id; +void omap_get_die_id(struct omap_die_id *odi) +{ + odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); + odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); + odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); + odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); +} + static void __init omap24xx_check_revision(void) { int i, j; diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h new file mode 100644 index 0000000..02ed3aa --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/id.h @@ -0,0 +1,22 @@ +/* + * OMAP2 CPU identification code + * + * Copyright (C) 2010 Kan-Ru Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP2_ARCH_ID_H +#define OMAP2_ARCH_ID_H + +struct omap_die_id { + u32 id_0; + u32 id_1; + u32 id_2; + u32 id_3; +}; + +void omap_get_die_id(struct omap_die_id *odi); + +#endif From patchwork Thu Jul 8 13:55:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110851 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68DtGUq015730 for ; Thu, 8 Jul 2010 13:55:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757932Ab0GHNzP (ORCPT ); Thu, 8 Jul 2010 09:55:15 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:56330 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757915Ab0GHNzO (ORCPT ); Thu, 8 Jul 2010 09:55:14 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWrZJ-0007yl-5G; Thu, 08 Jul 2010 13:55:13 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1+zdw4G8yfT1S/g04KGEwVz Subject: [PATCH 12/13] omap: Use omap_get_die_id() to get the DIE ids To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: linux-omap@vger.kernel.org, Kan-Ru Chen Date: Thu, 08 Jul 2010 16:55:11 +0300 Message-ID: <20100708135511.26276.34207.stgit@baageli.muru.com> In-Reply-To: <20100708135342.26276.80936.stgit@baageli.muru.com> References: <20100708135342.26276.80936.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 13:55:16 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index d079ccf..fd1904b 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -118,24 +118,22 @@ static void __init omap24xx_check_revision(void) u32 idcode, prod_id; u16 hawkeye; u8 dev_type, rev; + struct omap_die_id odi; idcode = read_tap_reg(OMAP_TAP_IDCODE); prod_id = read_tap_reg(tap_prod_id); hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0x0f; dev_type = (prod_id >> 16) & 0x0f; + omap_get_die_id(&odi); pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); - pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_0)); + pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", - read_tap_reg(OMAP_TAP_DIE_ID_1), - (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); - pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_2)); - pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_3)); + odi.id_1, (odi.id_1 >> 28) & 0xf); + pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); + pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", prod_id, dev_type); From patchwork Mon Aug 9 14:36:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 118401 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o79EauCJ010026 for ; Mon, 9 Aug 2010 14:36:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756805Ab0HIOgi (ORCPT ); Mon, 9 Aug 2010 10:36:38 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:57216 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756725Ab0HIOgf (ORCPT ); Mon, 9 Aug 2010 10:36:35 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o79EaTpk032121 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 9 Aug 2010 09:36:32 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o79EaRv9001867; Mon, 9 Aug 2010 20:06:27 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o79EaQ5A026403; Mon, 9 Aug 2010 20:06:26 +0530 Received: (from x0016154@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o79EaQj9026399; Mon, 9 Aug 2010 20:06:26 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak , Kevin Hilman Subject: [PATCH 1/5] OMAP4: runtime: Enable PM runtime core for OMAP4 Date: Mon, 9 Aug 2010 20:06:22 +0530 Message-Id: <1281364586-26323-1-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 09 Aug 2010 14:36:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 800b430..18db759 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -50,7 +50,7 @@ ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 From patchwork Mon Aug 9 14:36:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 118400 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o79EauCI010026 for ; Mon, 9 Aug 2010 14:36:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756798Ab0HIOgh (ORCPT ); Mon, 9 Aug 2010 10:36:37 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41369 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756654Ab0HIOge (ORCPT ); Mon, 9 Aug 2010 10:36:34 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o79EaTmd023130 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 9 Aug 2010 09:36:32 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o79EaRk2001869; Mon, 9 Aug 2010 20:06:28 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o79EaRjm026415; Mon, 9 Aug 2010 20:06:27 +0530 Received: (from x0016154@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o79EaRBT026413; Mon, 9 Aug 2010 20:06:27 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak , Paul Walmsley , Kevin Hilman Subject: [PATCH 3/5] OMAP3: hwmod: add I2C hwmods for OMAP3430 Date: Mon, 9 Aug 2010 20:06:24 +0530 Message-Id: <1281364586-26323-3-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1281364586-26323-2-git-send-email-rnayak@ti.com> References: <1281364586-26323-1-git-send-email-rnayak@ti.com> <1281364586-26323-2-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 09 Aug 2010 14:36:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 5d8eb58..7ef093f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,6 +17,9 @@ #include #include #include +#include +#include +#include #include "omap_hwmod_common_data.h" @@ -36,6 +39,9 @@ static struct omap_hwmod omap3xxx_iva_hwmod; static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; +static struct omap_hwmod omap3xxx_i2c1_hwmod; +static struct omap_hwmod omap3xxx_i2c2_hwmod; +static struct omap_hwmod omap3xxx_i2c3_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -90,6 +96,85 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; + +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap3xxx_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap3xxx_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C3 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c3_hwmod, + .clk = "i2c3_ick", + .addr = omap3xxx_i2c3_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -98,6 +183,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3xxx_l4_core__l4_wkup, + &omap3_l4_core__i2c1, + &omap3_l4_core__i2c2, + &omap3_l4_core__i2c3, }; /* L4 CORE */ @@ -197,6 +285,147 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; + +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +/* I2C1 */ + +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { + &omap3_l4_core__i2c1, +}; + +static struct omap_hwmod omap3xxx_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_chs = i2c1_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(i2c1_sdma_chs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_GRPSEL_I2C1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_GRPSEL_I2C1_SHIFT, + }, + }, + .slaves = omap3xxx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C2 */ + +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { + &omap3_l4_core__i2c2, +}; + +static struct omap_hwmod omap3xxx_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_chs = i2c2_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(i2c2_sdma_chs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_GRPSEL_I2C2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_GRPSEL_I2C2_SHIFT, + }, + }, + .slaves = omap3xxx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C3 */ + +static struct omap_i2c_dev_attr i2c3_dev_attr = { + .fifo_depth = 64, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = INT_34XX_I2C3_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c3_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP34XX_DMA_I2C3_TX }, + { .name = "rx", .dma_ch = OMAP34XX_DMA_I2C3_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { + &omap3_l4_core__i2c3, +}; + +static struct omap_hwmod omap3xxx_i2c3_hwmod = { + .name = "i2c3", + .mpu_irqs = i2c3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), + .sdma_chs = i2c3_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(i2c3_sdma_chs), + .main_clk = "i2c3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_GRPSEL_I2C3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_GRPSEL_I2C3_SHIFT, + }, + }, + .slaves = omap3xxx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), + .class = &i2c_class, + .dev_attr = &i2c3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +433,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_i2c1_hwmod, + &omap3xxx_i2c2_hwmod, + &omap3xxx_i2c3_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 7fd6023..51c354e 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -101,8 +101,11 @@ #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) +#define OMAP3430_GRPSEL_I2C3_SHIFT 17 #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) +#define OMAP3430_GRPSEL_I2C2_SHIFT 16 #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) +#define OMAP3430_GRPSEL_I2C1_SHIFT 15 #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h index 87f6bf2..255c756 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/plat-omap/include/plat/i2c.h @@ -34,5 +34,18 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, } #endif +/** + * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod + * @fifo_depth: total controller FIFO size (in bytes) + * @flags: differences in hardware support capability + * + * @fifo_depth represents what exists on the hardware, not what is + * actually configured at runtime by the device driver. + */ +struct omap_i2c_dev_attr { + u8 fifo_depth; + u8 flags; +}; + void __init omap1_i2c_mux_pins(int bus_id); void __init omap2_i2c_mux_pins(int bus_id); diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h new file mode 100644 index 0000000..5e19493 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h @@ -0,0 +1,24 @@ +/* + * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H + +/* L4 CORE */ +#define OMAP3_L4_CORE_FW_I2C1_REGION 21 +#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22 +#define OMAP3_L4_CORE_FW_I2C2_REGION 23 +#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24 +#define OMAP3_L4_CORE_FW_I2C3_REGION 73 +#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 + +#endif From patchwork Mon Aug 9 14:36:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 118403 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o79EauCL010026 for ; Mon, 9 Aug 2010 14:36:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756836Ab0HIOgj (ORCPT ); Mon, 9 Aug 2010 10:36:39 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:57217 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756746Ab0HIOgf (ORCPT ); Mon, 9 Aug 2010 10:36:35 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o79EaU3b032122 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 9 Aug 2010 09:36:32 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o79EaSvn001871; Mon, 9 Aug 2010 20:06:28 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o79EaSUB026425; Mon, 9 Aug 2010 20:06:28 +0530 Received: (from x0016154@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o79EaSIG026423; Mon, 9 Aug 2010 20:06:28 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak , Kevin Hilman , Paul Walmsley Subject: [PATCH 5/5] OMAP: I2C: Convert i2c driver to use PM runtime api's Date: Mon, 9 Aug 2010 20:06:26 +0530 Message-Id: <1281364586-26323-5-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1281364586-26323-4-git-send-email-rnayak@ti.com> References: <1281364586-26323-1-git-send-email-rnayak@ti.com> <1281364586-26323-2-git-send-email-rnayak@ti.com> <1281364586-26323-3-git-send-email-rnayak@ti.com> <1281364586-26323-4-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 09 Aug 2010 14:36:58 +0000 (UTC) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 7674efb..387f9c6 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -39,6 +39,7 @@ #include #include #include +#include /* I2C controller revisions */ #define OMAP_I2C_REV_2 0x20 @@ -175,8 +176,6 @@ struct omap_i2c_dev { void __iomem *base; /* virtual */ int irq; int reg_shift; /* bit shift for I2C register addresses */ - struct clk *iclk; /* Interface clock */ - struct clk *fclk; /* Functional clock */ struct completion cmd_complete; struct resource *ioarea; u32 latency; /* maximum mpu wkup latency */ @@ -265,45 +264,25 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) (i2c_dev->regs[reg] << i2c_dev->reg_shift)); } -static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) +static void omap_i2c_unidle(struct omap_i2c_dev *dev) { - int ret; - - dev->iclk = clk_get(dev->dev, "ick"); - if (IS_ERR(dev->iclk)) { - ret = PTR_ERR(dev->iclk); - dev->iclk = NULL; - return ret; - } - - dev->fclk = clk_get(dev->dev, "fck"); - if (IS_ERR(dev->fclk)) { - ret = PTR_ERR(dev->fclk); - if (dev->iclk != NULL) { - clk_put(dev->iclk); - dev->iclk = NULL; - } - dev->fclk = NULL; - return ret; - } + struct platform_device *pdev; + struct omap_i2c_bus_platform_data *pdata; - return 0; -} + WARN_ON(!dev->idle); -static void omap_i2c_put_clocks(struct omap_i2c_dev *dev) -{ - clk_put(dev->fclk); - dev->fclk = NULL; - clk_put(dev->iclk); - dev->iclk = NULL; -} + pdev = container_of(dev->dev, struct platform_device, dev); + pdata = pdev->dev.platform_data; -static void omap_i2c_unidle(struct omap_i2c_dev *dev) -{ - WARN_ON(!dev->idle); + pm_runtime_get_sync(&pdev->dev); + /* + * This is needed for now to have OMAP1 + * working as PM runtime is not yet + * supported on OMAP1 + */ + if (pdata->device_enable) + pdata->device_enable(pdev); - clk_enable(dev->iclk); - clk_enable(dev->fclk); if (cpu_is_omap34xx()) { omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); @@ -326,10 +305,15 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev) static void omap_i2c_idle(struct omap_i2c_dev *dev) { + struct platform_device *pdev; + struct omap_i2c_bus_platform_data *pdata; u16 iv; WARN_ON(dev->idle); + pdev = container_of(dev->dev, struct platform_device, dev); + pdata = pdev->dev.platform_data; + dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); if (dev->rev >= OMAP_I2C_REV_ON_4430) omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1); @@ -345,8 +329,15 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev) omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); } dev->idle = 1; - clk_disable(dev->fclk); - clk_disable(dev->iclk); + + pm_runtime_put_sync(&pdev->dev); + /* + * This is needed for now to have OMAP1 + * working as PM runtime is not yet + * supported on OMAP1 + */ + if (pdata->device_idle) + pdata->device_idle(pdev); } static int omap_i2c_init(struct omap_i2c_dev *dev) @@ -356,6 +347,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) unsigned long fclk_rate = 12000000; unsigned long timeout; unsigned long internal_clk = 0; + struct clk *fclk; if (dev->rev >= OMAP_I2C_REV_2) { /* Disable I2C controller before soft reset */ @@ -414,7 +406,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) * always returns 12MHz for the functional clock, we can * do this bit unconditionally. */ - fclk_rate = clk_get_rate(dev->fclk); + fclk = clk_get(dev->dev, "fck"); + fclk_rate = clk_get_rate(fclk); /* TRM for 5912 says the I2C clock must be prescaled to be * between 7 - 12 MHz. The XOR input clock is typically @@ -443,7 +436,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) internal_clk = 9600; else internal_clk = 4000; - fclk_rate = clk_get_rate(dev->fclk) / 1000; + fclk = clk_get(dev->dev, "fck"); + fclk_rate = clk_get_rate(fclk) / 1000; /* Compute prescaler divisor */ psc = fclk_rate / internal_clk; @@ -1046,14 +1040,12 @@ omap_i2c_probe(struct platform_device *pdev) else dev->reg_shift = 2; - if ((r = omap_i2c_get_clocks(dev)) != 0) - goto err_iounmap; - if (cpu_is_omap44xx()) dev->regs = (u8 *) omap4_reg_map; else dev->regs = (u8 *) reg_map; + pm_runtime_enable(&pdev->dev); omap_i2c_unidle(dev); dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; @@ -1125,8 +1117,6 @@ err_free_irq: err_unuse_clocks: omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); omap_i2c_idle(dev); - omap_i2c_put_clocks(dev); -err_iounmap: iounmap(dev->base); err_free_mem: platform_set_drvdata(pdev, NULL); @@ -1148,7 +1138,6 @@ omap_i2c_remove(struct platform_device *pdev) free_irq(dev->irq, dev); i2c_del_adapter(&dev->adapter); omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); - omap_i2c_put_clocks(dev); iounmap(dev->base); kfree(dev); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); From patchwork Mon Aug 9 14:36:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 118402 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o79EauCK010026 for ; Mon, 9 Aug 2010 14:36:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756809Ab0HIOgi (ORCPT ); Mon, 9 Aug 2010 10:36:38 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:41475 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756714Ab0HIOge (ORCPT ); Mon, 9 Aug 2010 10:36:34 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o79EaUYQ025184 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 9 Aug 2010 09:36:32 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o79EaS8R001870; Mon, 9 Aug 2010 20:06:28 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o79EaRKR026420; Mon, 9 Aug 2010 20:06:27 +0530 Received: (from x0016154@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o79EaR9w026418; Mon, 9 Aug 2010 20:06:27 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Paul Walmsley , Rajendra Nayak , Kevin Hilman Subject: [PATCH 4/5] OMAP: I2C: split device registration; convert OMAP2+ to omap_device Date: Mon, 9 Aug 2010 20:06:25 +0530 Message-Id: <1281364586-26323-4-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1281364586-26323-3-git-send-email-rnayak@ti.com> References: <1281364586-26323-1-git-send-email-rnayak@ti.com> <1281364586-26323-2-git-send-email-rnayak@ti.com> <1281364586-26323-3-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 09 Aug 2010 14:36:57 +0000 (UTC) diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index a5ce4f0..f58b425 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -27,18 +27,18 @@ #include #include #include +#include +#include +#include #include #include #include #include +#include #define OMAP_I2C_SIZE 0x3f #define OMAP1_I2C_BASE 0xfffb3800 -#define OMAP2_I2C_BASE1 0x48070000 -#define OMAP2_I2C_BASE2 0x48072000 -#define OMAP2_I2C_BASE3 0x48060000 -#define OMAP4_I2C_BASE4 0x48350000 static const char name[] = "i2c_omap"; @@ -55,15 +55,6 @@ static const char name[] = "i2c_omap"; static struct resource i2c_resources[][2] = { { I2C_RESOURCE_BUILDER(0, 0) }, -#if defined(CONFIG_ARCH_OMAP2PLUS) - { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) }, -#endif -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) }, -#endif -#if defined(CONFIG_ARCH_OMAP4) - { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) }, -#endif }; #define I2C_DEV_BUILDER(bus_id, res, data) \ @@ -77,22 +68,19 @@ static struct resource i2c_resources[][2] = { }, \ } -static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)]; +#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 +#define OMAP_I2C_MAX_CONTROLLERS 4 +static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS]; static struct platform_device omap_i2c_devices[] = { I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), -#if defined(CONFIG_ARCH_OMAP2PLUS) - I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]), -#endif -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]), -#endif -#if defined(CONFIG_ARCH_OMAP4) - I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]), -#endif }; #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) +#define I2C_ICLK 0 +#define I2C_FCLK 1 +static struct clk *omap_i2c_clks[ARRAY_SIZE(omap_i2c_devices)][2]; + static int __init omap_i2c_nr_ports(void) { int ports = 0; @@ -109,35 +97,57 @@ static int __init omap_i2c_nr_ports(void) return ports; } -/* Shared between omap2 and 3 */ -static resource_size_t omap2_i2c_irq[3] __initdata = { - INT_24XX_I2C1_IRQ, - INT_24XX_I2C2_IRQ, - INT_34XX_I2C3_IRQ, -}; +static int omap1_i2c_device_enable(struct platform_device *pdev) +{ + struct clk *c; + c = omap_i2c_clks[pdev->id - 1][I2C_ICLK]; + if (c && !IS_ERR(c)) + clk_enable(c); -static resource_size_t omap4_i2c_irq[4] __initdata = { - OMAP44XX_IRQ_I2C1, - OMAP44XX_IRQ_I2C2, - OMAP44XX_IRQ_I2C3, - OMAP44XX_IRQ_I2C4, -}; + c = omap_i2c_clks[pdev->id - 1][I2C_FCLK]; + if (c && !IS_ERR(c)) + clk_enable(c); + + return 0; +} + +static int omap1_i2c_device_idle(struct platform_device *pdev) +{ + struct clk *c; + + c = omap_i2c_clks[pdev->id - 1][I2C_FCLK]; + if (c && !IS_ERR(c)) + clk_disable(c); -static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id) + c = omap_i2c_clks[pdev->id - 1][I2C_ICLK]; + if (c && !IS_ERR(c)) + clk_disable(c); + + return 0; +} + +static inline int omap1_i2c_add_bus(int bus_id) { - struct omap_i2c_bus_platform_data *pd; - struct resource *res; - - pd = pdev->dev.platform_data; - res = pdev->resource; - res[0].start = OMAP1_I2C_BASE; - res[0].end = res[0].start + OMAP_I2C_SIZE; - res[1].start = INT_I2C; + struct platform_device *pdev; + struct omap_i2c_bus_platform_data *pdata; + omap1_i2c_mux_pins(bus_id); + pdev = &omap_i2c_devices[bus_id - 1]; + pdata = &i2c_pdata[bus_id - 1]; + + /* idle and shutdown share the same code */ + pdata->device_enable = omap1_i2c_device_enable; + pdata->device_idle = omap1_i2c_device_idle; + pdata->device_shutdown = omap1_i2c_device_idle; + + omap_i2c_clks[bus_id - 1][I2C_ICLK] = clk_get(&pdev->dev, "ick"); + omap_i2c_clks[bus_id - 1][I2C_FCLK] = clk_get(&pdev->dev, "fck"); + return platform_device_register(pdev); } + /* * XXX This function is a temporary compatibility wrapper - only * needed until the I2C driver can be converted to call @@ -148,52 +158,57 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) omap_pm_set_max_mpu_wakeup_lat(dev, t); } -static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) -{ - struct resource *res; - resource_size_t *irq; +static struct omap_device_pm_latency omap_i2c_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; - res = pdev->resource; +static inline int omap2_i2c_add_bus(int bus_id) +{ + int l; + struct omap_hwmod *oh; + struct omap_device *od; + char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; + struct omap_i2c_bus_platform_data *pdata; - if (!cpu_is_omap44xx()) - irq = omap2_i2c_irq; - else - irq = omap4_i2c_irq; + omap2_i2c_mux_pins(bus_id); - if (bus_id == 1) { - res[0].start = OMAP2_I2C_BASE1; - res[0].end = res[0].start + OMAP_I2C_SIZE; + l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id); + WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN, + "String buffer overflow in I2C%d device setup\n", bus_id); + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return -EEXIST; } - res[1].start = irq[bus_id - 1]; - omap2_i2c_mux_pins(bus_id); - + pdata = &i2c_pdata[bus_id - 1]; /* * When waiting for completion of a i2c transfer, we need to * set a wake up latency constraint for the MPU. This is to * ensure quick enough wakeup from idle, when transfer * completes. + * Only omap3 has support for constraints */ - if (cpu_is_omap34xx()) { - struct omap_i2c_bus_platform_data *pd; - - pd = pdev->dev.platform_data; - pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; - } - - return platform_device_register(pdev); + if (cpu_is_omap34xx()) + pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; + od = omap_device_build(name, bus_id, oh, pdata, + sizeof(struct omap_i2c_bus_platform_data), + omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0); + WARN(IS_ERR(od), "Could not build omap_device for %s\n", name); + + return PTR_ERR(od); } static int __init omap_i2c_add_bus(int bus_id) { - struct platform_device *pdev; - - pdev = &omap_i2c_devices[bus_id - 1]; - if (cpu_class_is_omap1()) - return omap1_i2c_add_bus(pdev, bus_id); + return omap1_i2c_add_bus(bus_id); else - return omap2_i2c_add_bus(pdev, bus_id); + return omap2_i2c_add_bus(bus_id); } /** diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h index 78ebf50..7472449 100644 --- a/include/linux/i2c-omap.h +++ b/include/linux/i2c-omap.h @@ -1,9 +1,14 @@ #ifndef __I2C_OMAP_H__ #define __I2C_OMAP_H__ +#include + struct omap_i2c_bus_platform_data { u32 clkrate; void (*set_mpu_wkup_lat)(struct device *dev, long set); + int (*device_enable) (struct platform_device *pdev); + int (*device_shutdown) (struct platform_device *pdev); + int (*device_idle) (struct platform_device *pdev); }; #endif From patchwork Fri Mar 19 10:23:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjeev Premi X-Patchwork-Id: 86910 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2JANQYJ031633 for ; Fri, 19 Mar 2010 10:23:27 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751581Ab0CSKX0 (ORCPT ); Fri, 19 Mar 2010 06:23:26 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:40182 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751171Ab0CSKXZ (ORCPT ); Fri, 19 Mar 2010 06:23:25 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2JANMsr002877 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 19 Mar 2010 05:23:24 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2JANK9X029601; Fri, 19 Mar 2010 15:53:21 +0530 (IST) From: Sanjeev Premi To: linux-omap@vger.kernel.org Cc: Sanjeev Premi Subject: [RFC] omap3: Fix incorrect restore pointer Date: Fri, 19 Mar 2010 15:53:00 +0530 Message-Id: <1268994180-25170-1-git-send-email-premi@ti.com> X-Mailer: git-send-email 1.6.6.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 19 Mar 2010 10:23:27 +0000 (UTC) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 43f8a33..575593b 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -213,13 +213,16 @@ void omap3_save_scratchpad_contents(void) /* Populate the Scratchpad contents */ scratchpad_contents.boot_config_ptr = 0x0; - if (omap_rev() != OMAP3430_REV_ES3_0 && - omap_rev() != OMAP3430_REV_ES3_1) + + if (!cpu_is_omap3630() && + (cpu_is_34xx() && + (omap_rev() < OMAP3430_REV_ES3_0))) scratchpad_contents.public_restore_ptr = virt_to_phys(get_restore_pointer()); else scratchpad_contents.public_restore_ptr = virt_to_phys(get_es3_restore_pointer()); + if (omap_type() == OMAP2_DEVICE_TYPE_GP) scratchpad_contents.secure_ram_restore_ptr = 0x0; else From patchwork Fri Jun 4 07:40:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 104227 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o547eU4X018793 for ; Fri, 4 Jun 2010 07:40:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752902Ab0FDHk3 (ORCPT ); Fri, 4 Jun 2010 03:40:29 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:37628 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752767Ab0FDHk2 (ORCPT ); Fri, 4 Jun 2010 03:40:28 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o547e915029043 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 4 Jun 2010 02:40:12 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o547e581021210; Fri, 4 Jun 2010 13:10:09 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: linux-mtd@lists.infradead.org, tony@atomide.com, mike@compulab.co.il, Sukumar Ghorai Subject: [PATCH v5 2/3] omap3 nand: cleanup virtual address usages Date: Fri, 4 Jun 2010 13:10:04 +0530 Message-Id: <1275637205-489-3-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1275637205-489-2-git-send-email-s-ghorai@ti.com> References: <1275637205-489-1-git-send-email-s-ghorai@ti.com> <1275637205-489-2-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 04 Jun 2010 07:40:31 +0000 (UTC) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index e57fb29..80f5d94 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -19,8 +19,6 @@ #include #include -#define WR_RD_PIN_MONITORING 0x00600000 - static struct omap_nand_platform_data *gpmc_nand_data; static struct resource gpmc_nand_resource = { @@ -71,10 +69,10 @@ static int omap2_nand_gpmc_retime(void) t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); /* Configure GPMC */ - gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, - GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | - GPMC_CONFIG1_DEVICETYPE_NAND); - + gpmc_hwcontrol(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_SIZE, 1, gpmc_nand_data->devsize, NULL); + gpmc_hwcontrol(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_TYPE, 1, GPMC_DEVICETYPE_NAND, NULL); err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); if (err) return err; @@ -82,27 +80,13 @@ static int omap2_nand_gpmc_retime(void) return 0; } -static int gpmc_nand_setup(void) -{ - struct device *dev = &gpmc_nand_device.dev; - - /* Set timings in GPMC */ - if (omap2_nand_gpmc_retime() < 0) { - dev_err(dev, "Unable to set gpmc timings\n"); - return -EINVAL; - } - - return 0; -} - int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) { - unsigned int val; int err = 0; struct device *dev = &gpmc_nand_device.dev; gpmc_nand_data = _nand_data; - gpmc_nand_data->nand_setup = gpmc_nand_setup; + gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime; gpmc_nand_device.dev.platform_data = gpmc_nand_data; err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, @@ -112,19 +96,17 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) return err; } - err = gpmc_nand_setup(); + /* Set timings in GPMC */ + err = omap2_nand_gpmc_retime(); if (err < 0) { - dev_err(dev, "NAND platform setup failed: %d\n", err); + dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; } /* Enable RD PIN Monitoring Reg */ if (gpmc_nand_data->dev_ready) { - val = gpmc_cs_read_reg(gpmc_nand_data->cs, - GPMC_CS_CONFIG1); - val |= WR_RD_PIN_MONITORING; - gpmc_cs_write_reg(gpmc_nand_data->cs, - GPMC_CS_CONFIG1, val); + gpmc_hwcontrol(gpmc_nand_data->cs, + GPMC_CONFIG_RDY_BSY, 1, 1, NULL); } err = platform_device_register(&gpmc_nand_device); @@ -140,3 +122,4 @@ out_free_cs: return err; } + diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 48b5af0..91e1526 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -584,15 +584,6 @@ int gpmc_prefetch_reset(int cs) } EXPORT_SYMBOL(gpmc_prefetch_reset); -/** - * gpmc_prefetch_status - reads prefetch status of engine - */ -int gpmc_prefetch_status(void) -{ - return gpmc_read_reg(GPMC_PREFETCH_STATUS); -} -EXPORT_SYMBOL(gpmc_prefetch_status); - static void __init gpmc_mem_init(void) { int cs; diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 8a1e9d9..ccbc530 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -25,9 +25,6 @@ #define GPMC_CS_NAND_ADDRESS 0x20 #define GPMC_CS_NAND_DATA 0x24 -#define GPMC_CONFIG 0x50 -#define GPMC_STATUS 0x54 - /* Control Commands */ #define GPMC_CONFIG_WP 0x00000001 #define GPMC_CONFIG_RDY_BSY 0x00000002 @@ -63,7 +60,6 @@ #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) -#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2) #define GPMC_CONFIG1_MUXADDDATA (1 << 9) #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) @@ -133,7 +129,6 @@ extern int gpmc_cs_reserved(int cs); extern int gpmc_prefetch_enable(int cs, int dma_mode, unsigned int u32_count, int is_write); extern int gpmc_prefetch_reset(int cs); -extern int gpmc_prefetch_status(void); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); extern void gpmc_init(void); diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index f8efd54..6562cd0 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -21,13 +21,11 @@ struct omap_nand_platform_data { int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; unsigned long phys_base; - void __iomem *gpmc_cs_baseaddr; - void __iomem *gpmc_baseaddr; int devsize; }; -/* size (4 KiB) for IO mapping */ -#define NAND_IO_SIZE SZ_4K +/* minimum size for IO mapping */ +#define NAND_IO_SIZE 4 #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) extern int gpmc_nand_init(struct omap_nand_platform_data *d); diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index ec8eb31..f9fa3cb --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -7,6 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#define CONFIG_MTD_NAND_OMAP_HWECC #include #include @@ -23,20 +24,8 @@ #include #include -#define GPMC_IRQ_STATUS 0x18 -#define GPMC_ECC_CONFIG 0x1F4 -#define GPMC_ECC_CONTROL 0x1F8 -#define GPMC_ECC_SIZE_CONFIG 0x1FC -#define GPMC_ECC1_RESULT 0x200 - #define DRIVER_NAME "omap2-nand" -#define NAND_WP_OFF 0 -#define NAND_WP_BIT 0x00000010 - -#define GPMC_BUF_FULL 0x00000001 -#define GPMC_BUF_EMPTY 0x00000000 - #define NAND_Ecc_P1e (1 << 0) #define NAND_Ecc_P2e (1 << 1) #define NAND_Ecc_P4e (1 << 2) @@ -139,34 +128,11 @@ struct omap_nand_info { int gpmc_cs; unsigned long phys_base; - void __iomem *gpmc_cs_baseaddr; - void __iomem *gpmc_baseaddr; - void __iomem *nand_pref_fifo_add; struct completion comp; int dma_ch; }; /** - * omap_nand_wp - This function enable or disable the Write Protect feature - * @mtd: MTD device structure - * @mode: WP ON/OFF - */ -static void omap_nand_wp(struct mtd_info *mtd, int mode) -{ - struct omap_nand_info *info = container_of(mtd, - struct omap_nand_info, mtd); - - unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG); - - if (mode) - config &= ~(NAND_WP_BIT); /* WP is ON */ - else - config |= (NAND_WP_BIT); /* WP is OFF */ - - __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG)); -} - -/** * omap_hwcontrol - hardware specific access to control-lines * @mtd: MTD device structure * @cmd: command to device @@ -181,31 +147,20 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - switch (ctrl) { - case NAND_CTRL_CHANGE | NAND_CTRL_CLE: - info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + - GPMC_CS_NAND_COMMAND; - info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + - GPMC_CS_NAND_DATA; - break; - - case NAND_CTRL_CHANGE | NAND_CTRL_ALE: - info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + - GPMC_CS_NAND_ADDRESS; - info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + - GPMC_CS_NAND_DATA; - break; - - case NAND_CTRL_CHANGE | NAND_NCE: - info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + - GPMC_CS_NAND_DATA; - info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + - GPMC_CS_NAND_DATA; - break; - } - if (cmd != NAND_CMD_NONE) - __raw_writeb(cmd, info->nand.IO_ADDR_W); + if (cmd != NAND_CMD_NONE) { + if (ctrl & NAND_CLE) + gpmc_hwcontrol(info->gpmc_cs, + GPMC_NAND_COMMAND, 1, cmd, NULL); + + else if (ctrl & NAND_ALE) + gpmc_hwcontrol(info->gpmc_cs, + GPMC_NAND_ADDRESS, 1, cmd, NULL); + + else /* NAND_NCE */ + gpmc_hwcontrol(info->gpmc_cs, + GPMC_NAND_DATA, 1, cmd, NULL); + } } /** @@ -232,11 +187,15 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); u_char *p = (u_char *)buf; + u32 status = 0; while (len--) { iowrite8(*p++, info->nand.IO_ADDR_W); - while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr + - GPMC_STATUS) & GPMC_BUF_FULL)); + /* wait until buffer is available for write */ + do { + gpmc_hwcontrol(info->gpmc_cs, + GPMC_STATUS_BUFFER, 0, 0, &status); + } while (!status); } } @@ -264,16 +223,17 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); u16 *p = (u16 *) buf; - + u32 status = 0; /* FIXME try bursts of writesw() or DMA ... */ len >>= 1; while (len--) { iowrite16(*p++, info->nand.IO_ADDR_W); - - while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr + - GPMC_STATUS) & GPMC_BUF_FULL)) - ; + /* wait until buffer is available for write */ + do { + gpmc_hwcontrol(info->gpmc_cs, + GPMC_STATUS_BUFFER, 0, 0, &status); + } while (!status); } } @@ -287,7 +247,7 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - uint32_t pfpw_status = 0, r_count = 0; + uint32_t r_count = 0; int ret = 0; u32 *p = (u32 *)buf; @@ -310,14 +270,15 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) else omap_read_buf8(mtd, buf, len); } else { + p = (u32 *) buf; do { - pfpw_status = gpmc_prefetch_status(); - r_count = ((pfpw_status >> 24) & 0x7F) >> 2; - ioread32_rep(info->nand_pref_fifo_add, p, r_count); + gpmc_hwcontrol(info->gpmc_cs, + GPMC_PREFETCH_FIFO_CNT, 0, 0, &r_count); + r_count = r_count >> 2; + ioread32_rep(info->nand.IO_ADDR_R, p, r_count); p += r_count; len -= r_count << 2; } while (len); - /* disable and stop the PFPW engine */ gpmc_prefetch_reset(info->gpmc_cs); } @@ -334,13 +295,13 @@ static void omap_write_buf_pref(struct mtd_info *mtd, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - uint32_t pfpw_status = 0, w_count = 0; + uint32_t pref_count = 0, w_count = 0; int i = 0, ret = 0; - u16 *p = (u16 *) buf; + u16 *p; /* take care of subpage writes */ if (len % 2 != 0) { - writeb(*buf, info->nand.IO_ADDR_R); + writeb(*buf, info->nand.IO_ADDR_W); p = (u16 *)(buf + 1); len--; } @@ -354,14 +315,19 @@ static void omap_write_buf_pref(struct mtd_info *mtd, else omap_write_buf8(mtd, buf, len); } else { - pfpw_status = gpmc_prefetch_status(); - while (pfpw_status & 0x3FFF) { - w_count = ((pfpw_status >> 24) & 0x7F) >> 1; + p = (u16 *) buf; + while (len) { + gpmc_hwcontrol(info->gpmc_cs, + GPMC_PREFETCH_FIFO_CNT, 0, 0, &w_count); + w_count = w_count >> 1; for (i = 0; (i < w_count) && len; i++, len -= 2) - iowrite16(*p++, info->nand_pref_fifo_add); - pfpw_status = gpmc_prefetch_status(); + iowrite16(*p++, info->nand.IO_ADDR_W); } - + /* wait for data to flushed-out before reset the prefetch */ + do { + gpmc_hwcontrol(info->gpmc_cs, + GPMC_PREFETCH_COUNT, 0, 0, &pref_count); + } while (pref_count); /* disable and stop the PFPW engine */ gpmc_prefetch_reset(info->gpmc_cs); } @@ -451,8 +417,10 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, /* setup and start DMA using dma_addr */ wait_for_completion(&info->comp); - while (0x3fff & (prefetch_status = gpmc_prefetch_status())) - ; + do { + gpmc_hwcontrol(info->gpmc_cs, + GPMC_PREFETCH_COUNT, 0, 0, &prefetch_status); + } while (prefetch_status); /* disable and stop the PFPW engine */ gpmc_prefetch_reset(); @@ -530,29 +498,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) } #ifdef CONFIG_MTD_NAND_OMAP_HWECC -/** - * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller - * @mtd: MTD device structure - */ -static void omap_hwecc_init(struct mtd_info *mtd) -{ - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, - mtd); - struct nand_chip *chip = mtd->priv; - unsigned long val = 0x0; - - /* Read from ECC Control Register */ - val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL); - /* Clear all ECC | Enable Reg1 */ - val = ((0x00000001<<8) | 0x00000001); - __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL); - - /* Read from ECC Size Config Register */ - val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); - /* ECCSIZE1=512 | Select eccResultsize[0-3] */ - val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F)); - __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); -} /** * gen_true_ecc - This function will generate true ECC value @@ -755,19 +700,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - unsigned long val = 0x0; - unsigned long reg; - - /* Start Reading from HW ECC1_Result = 0x200 */ - reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT); - val = __raw_readl(reg); - *ecc_code++ = val; /* P128e, ..., P1e */ - *ecc_code++ = val >> 16; /* P128o, ..., P1o */ - /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ - *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); - reg += 4; - - return 0; + return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code); } /** @@ -781,32 +714,10 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) mtd); struct nand_chip *chip = mtd->priv; unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; - unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG); - - switch (mode) { - case NAND_ECC_READ: - __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); - /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ - val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); - break; - case NAND_ECC_READSYN: - __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL); - /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ - val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); - break; - case NAND_ECC_WRITE: - __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); - /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ - val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); - break; - default: - DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n", - mode); - break; - } - __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG); + gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); } + #endif /** @@ -834,14 +745,10 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) else timeo += (HZ * 20) / 1000; - this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr + - GPMC_CS_NAND_COMMAND; - this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA; - - __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W); - + gpmc_hwcontrol(info->gpmc_cs, + GPMC_NAND_COMMAND, 1, (NAND_CMD_STATUS & 0xFF), NULL); while (time_before(jiffies, timeo)) { - status = __raw_readb(this->IO_ADDR_R); + gpmc_hwcontrol(info->gpmc_cs, GPMC_NAND_DATA, 0, 0, &status); if (status & NAND_STATUS_READY) break; cond_resched(); @@ -855,22 +762,24 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) */ static int omap_dev_ready(struct mtd_info *mtd) { + unsigned int val = 0; struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS); + gpmc_hwcontrol(info->gpmc_cs, GPMC_GET_SET_IRQ_STATUS, 0, 0, &val); if ((val & 0x100) == 0x100) { /* Clear IRQ Interrupt */ val |= 0x100; val &= ~(0x0); - __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS); + gpmc_hwcontrol(info->gpmc_cs, + GPMC_GET_SET_IRQ_STATUS, 1, val, NULL); } else { unsigned int cnt = 0; while (cnt++ < 0x1FF) { if ((val & 0x100) == 0x100) return 0; - val = __raw_readl(info->gpmc_baseaddr + - GPMC_IRQ_STATUS); + gpmc_hwcontrol(info->gpmc_cs, + GPMC_GET_SET_IRQ_STATUS, 0, 0, &val); } } @@ -901,8 +810,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->pdev = pdev; info->gpmc_cs = pdata->cs; - info->gpmc_baseaddr = pdata->gpmc_baseaddr; - info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr; info->phys_base = pdata->phys_base; info->mtd.priv = &info->nand; @@ -913,7 +820,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.options |= NAND_SKIP_BBTSCAN; /* NAND write protect off */ - omap_nand_wp(&info->mtd, NAND_WP_OFF); + gpmc_hwcontrol(info->gpmc_cs, GPMC_CONFIG_WP, 1, 0, NULL); if (!request_mem_region(info->phys_base, NAND_IO_SIZE, pdev->dev.driver->name)) { @@ -948,8 +855,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } if (use_prefetch) { - /* copy the virtual address of nand base for fifo access */ - info->nand_pref_fifo_add = info->nand.IO_ADDR_R; info->nand.read_buf = omap_read_buf_pref; info->nand.write_buf = omap_write_buf_pref; @@ -989,8 +894,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.ecc.correct = omap_correct_data; info->nand.ecc.mode = NAND_ECC_HW; - /* init HW ECC */ - omap_hwecc_init(&info->mtd); #else info->nand.ecc.mode = NAND_ECC_SOFT; #endif @@ -1040,7 +943,7 @@ static int omap_nand_remove(struct platform_device *pdev) /* Release NAND device, its internal structures and partitions */ nand_release(&info->mtd); - iounmap(info->nand_pref_fifo_add); + iounmap(info->nand.IO_ADDR_R); kfree(&info->mtd); return 0; } From patchwork Wed Jun 16 14:15:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nagarajan, Rajkumar" X-Patchwork-Id: 106498 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5GEFlPY021496 for ; Wed, 16 Jun 2010 14:15:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758922Ab0FPOPq (ORCPT ); Wed, 16 Jun 2010 10:15:46 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:55388 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752189Ab0FPOPp convert rfc822-to-8bit (ORCPT ); Wed, 16 Jun 2010 10:15:45 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5GEFgNq014081 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 16 Jun 2010 09:15:45 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5GEFgnq012463 for ; Wed, 16 Jun 2010 19:45:42 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Wed, 16 Jun 2010 19:45:42 +0530 From: "Nagarajan, Rajkumar" To: "linux-omap@vger.kernel.org" Date: Wed, 16 Jun 2010 19:45:42 +0530 Subject: [PATCH] OMAP: DSS2: Switching GFX from LCD to TV Thread-Topic: [PATCH] OMAP: DSS2: Switching GFX from LCD to TV Thread-Index: AcsNX2BucTCJuGnKRyGk2Thj5VkGQQ== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 16 Jun 2010 14:15:49 +0000 (UTC) diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 8233658..4e9966f 100644 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -117,6 +117,36 @@ static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf) ovl->info.width, ovl->info.height); } +static ssize_t overlay_input_size_store(struct omap_overlay *ovl, + const char *buf, size_t size) +{ + int r; + char *last; + struct omap_overlay_info info; + + ovl->get_overlay_info(ovl, &info); + + info.width = simple_strtoul(buf, &last, 10); + ++last; + if (last - buf >= size) + return -EINVAL; + + info.height = simple_strtoul(last, &last, 10); + + r = ovl->set_overlay_info(ovl, &info); + if (r) + return r; + + if (ovl->manager) { + r = ovl->manager->apply(ovl->manager); + if (r) + return r; + } + + return size; +} + + static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf) { return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width); @@ -268,7 +298,8 @@ struct overlay_attribute { static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL); static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR, overlay_manager_show, overlay_manager_store); -static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL); +static OVERLAY_ATTR(input_size, S_IRUGO|S_IWUSR, + overlay_input_size_show, overlay_input_size_store); static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL); static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR, overlay_position_show, overlay_position_store); diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 4b4506d..73ecc9f 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -46,6 +46,8 @@ static char *def_vram; static int def_vrfb; static int def_rotate; static int def_mirror; +unsigned int omapfb_size; +module_param_named(fb_size, omapfb_size, int, 0644); #ifdef DEBUG unsigned int omapfb_debug; @@ -1444,6 +1446,11 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size, } } + if (omapfb_size) { + if (omapfb_size > size) + size = omapfb_size; + } + if (!size) return 0; From patchwork Thu Jun 17 10:40:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106657 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAf67r010533 for ; Thu, 17 Jun 2010 10:41:06 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759833Ab0FQKlD (ORCPT ); Thu, 17 Jun 2010 06:41:03 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:53707 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759815Ab0FQKk7 (ORCPT ); Thu, 17 Jun 2010 06:40:59 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAelG3007927 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:50 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAejOq015342; Thu, 17 Jun 2010 16:10:45 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAejTn005304; Thu, 17 Jun 2010 16:10:45 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAeiSo005301; Thu, 17 Jun 2010 16:10:44 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Maulik Mankad , David Brownell , Ajay Kumar Gupta Subject: [PATCH 8/8] usb: musb: Fix suspend interrupt issue in device mode Date: Thu, 17 Jun 2010 16:10:41 +0530 Message-Id: <1276771242-5201-9-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-8-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> <1276771242-5201-5-git-send-email-ajay.gupta@ti.com> <1276771242-5201-6-git-send-email-ajay.gupta@ti.com> <1276771242-5201-7-git-send-email-ajay.gupta@ti.com> <1276771242-5201-8-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:07 +0000 (UTC) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 4f43db7..64b08f9 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -635,7 +635,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, handled = IRQ_HANDLED; } - +#endif if (int_usb & MUSB_INTR_SUSPEND) { DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", otg_state_string(musb), devctl, power); @@ -698,6 +698,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, } } +#ifdef CONFIG_USB_MUSB_HDRC_HCD if (int_usb & MUSB_INTR_CONNECT) { struct usb_hcd *hcd = musb_to_hcd(musb); From patchwork Thu Jun 17 10:40:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106656 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAf21v010521 for ; Thu, 17 Jun 2010 10:41:02 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759805Ab0FQKk6 (ORCPT ); Thu, 17 Jun 2010 06:40:58 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:44622 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759573Ab0FQKk4 (ORCPT ); Thu, 17 Jun 2010 06:40:56 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAek2m031880 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:49 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAeigK015341; Thu, 17 Jun 2010 16:10:44 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAeiix005298; Thu, 17 Jun 2010 16:10:44 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAeiqn005295; Thu, 17 Jun 2010 16:10:44 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Anand Gadiyar , Ajay Kumar Gupta Subject: [PATCH 7/8] musb: Kill board specific pinmux from driver file Date: Thu, 17 Jun 2010 16:10:40 +0530 Message-Id: <1276771242-5201-8-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-7-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> <1276771242-5201-5-git-send-email-ajay.gupta@ti.com> <1276771242-5201-6-git-send-email-ajay.gupta@ti.com> <1276771242-5201-7-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:02 +0000 (UTC) diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index e06d65e..2111a24 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -32,8 +32,6 @@ #include #include -#include - #include "musb_core.h" #include "omap2430.h" @@ -194,10 +192,6 @@ int __init musb_platform_init(struct musb *musb, void *board_data) u32 l; struct omap_musb_board_data *data = board_data; -#if defined(CONFIG_ARCH_OMAP2430) - omap_cfg_reg(AE5_2430_USB0HS_STP); -#endif - /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. From patchwork Wed Apr 28 05:51:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 95617 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3S5pXBB005088 for ; Wed, 28 Apr 2010 05:51:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753588Ab0D1Fvc (ORCPT ); Wed, 28 Apr 2010 01:51:32 -0400 Received: from smtp.nokia.com ([192.100.122.230]:59743 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753451Ab0D1Fvc (ORCPT ); Wed, 28 Apr 2010 01:51:32 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3S5pMPw025538; Wed, 28 Apr 2010 08:51:23 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 08:51:22 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 08:51:21 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3S5pKkX001721; Wed, 28 Apr 2010 08:51:21 +0300 From: Eduardo Valentin To: linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: ext Tony Lindgren , ext Kevin Hilman , "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , santosh.shilimkar@ti.com, felipe.balbi@nokia.com, Eduardo Valentin Subject: [PATCHv3 1/4] ARM: Introduce SoC Info into /proc/cpuinfo Date: Wed, 28 Apr 2010 08:51:40 +0300 Message-Id: <1272433903-24003-2-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1272433903-24003-1-git-send-email-eduardo.valentin@nokia.com> References: <1272433903-24003-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 28 Apr 2010 05:51:21.0836 (UTC) FILETIME=[D483A2C0:01CAE696] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Apr 2010 05:51:34 +0000 (UTC) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4ace45e..53a9645 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -71,6 +71,8 @@ struct task_struct; extern unsigned int system_rev; extern unsigned int system_serial_low; extern unsigned int system_serial_high; +#define SYSTEM_SOC_INFO_SIZE 128 +extern char system_soc_info[SYSTEM_SOC_INFO_SIZE]; extern unsigned int mem_fclk_21285; struct pt_regs; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c91c77b..025d795 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -85,6 +85,9 @@ EXPORT_SYMBOL(system_serial_low); unsigned int system_serial_high; EXPORT_SYMBOL(system_serial_high); +char system_soc_info[SYSTEM_SOC_INFO_SIZE]; +EXPORT_SYMBOL(system_soc_info); + unsigned int elf_hwcap; EXPORT_SYMBOL(elf_hwcap); @@ -847,6 +850,8 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "Revision\t: %04x\n", system_rev); seq_printf(m, "Serial\t\t: %08x%08x\n", system_serial_high, system_serial_low); + if (strlen(system_soc_info)) + seq_printf(m, "SoC Info\t: %s\n", system_soc_info); return 0; } From patchwork Wed Jul 28 09:41:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Rapeli X-Patchwork-Id: 114719 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6S9fprP021577 for ; Wed, 28 Jul 2010 09:41:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754397Ab0G1Jlv (ORCPT ); Wed, 28 Jul 2010 05:41:51 -0400 Received: from smtp.nokia.com ([192.100.105.134]:29061 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752934Ab0G1Jlu (ORCPT ); Wed, 28 Jul 2010 05:41:50 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o6S9fEs6011590; Wed, 28 Jul 2010 04:41:43 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 28 Jul 2010 12:41:36 +0300 Received: from mgw-da02.ext.nokia.com ([147.243.128.26]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 28 Jul 2010 12:41:35 +0300 Received: from localhost.localdomain (ouped11834.nmp.nokia.com [172.23.118.34]) by mgw-da02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o6S9fWr8020344; Wed, 28 Jul 2010 12:41:33 +0300 From: Mikko Rapeli To: linux-omap@vger.kernel.org Cc: mturquette@ti.com, sameo@linux.intel.com Subject: [PATCH] twl4030 reboot workaround Date: Wed, 28 Jul 2010 12:41:32 +0300 Message-Id: <1280310092-27260-1-git-send-email-ext-mikko.rapeli@nokia.com> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1265226207-22971-3-git-send-email-mturquette@ti.com> References: <1265226207-22971-3-git-send-email-mturquette@ti.com> X-OriginalArrivalTime: 28 Jul 2010 09:41:36.0362 (UTC) FILETIME=[123444A0:01CB2E39] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 09:41:52 +0000 (UTC) diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c index 7efa878..5d46768 100644 --- a/drivers/mfd/twl4030-power.c +++ b/drivers/mfd/twl4030-power.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -127,6 +128,29 @@ static u8 res_config_addrs[] = { [RES_Main_Ref] = 0x94, }; +/* + * PRCM on OMAP3 will drive SYS_OFFMODE low during DPLL3 warm reset. + * This causes Gaia sleep script to execute, usually killing VDD1 and + * VDD2 while code is running. WA is to disable the sleep script + * before warm reset. + */ +static int twl4030_prepare_for_reboot(struct notifier_block *this, + unsigned long cmd, void *p) +{ + int err; + err = twl4030_remove_script(TWL4030_SLEEP_SCRIPT); + if (err) + pr_err("TWL4030: error trying to disable sleep script!\n"); + + return NOTIFY_DONE; +} + +static struct notifier_block twl4030_reboot_notifier = { + .notifier_call = twl4030_prepare_for_reboot, + .next = NULL, + .priority = 0 +}; + static int __init twl4030_write_script_byte(u8 address, u8 byte) { int err; @@ -549,6 +573,11 @@ void __init twl4030_power_init(struct twl4030_power_data *twl4030_scripts) err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY); if (err) pr_err("TWL4030 Unable to relock registers\n"); + + err = register_reboot_notifier(&twl4030_reboot_notifier); + if (err) + pr_err("TWL4030 Failed to register reboot notifier\n"); + return; unlock: From patchwork Wed Apr 28 05:51:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 95618 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3S5pbGo005121 for ; Wed, 28 Apr 2010 05:51:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753630Ab0D1Fvh (ORCPT ); Wed, 28 Apr 2010 01:51:37 -0400 Received: from smtp.nokia.com ([192.100.105.134]:40907 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753589Ab0D1Fvg (ORCPT ); Wed, 28 Apr 2010 01:51:36 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3S5pOjG014683; Wed, 28 Apr 2010 00:51:30 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 08:51:22 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 08:51:22 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3S5pKkY001721; Wed, 28 Apr 2010 08:51:21 +0300 From: Eduardo Valentin To: linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: ext Tony Lindgren , ext Kevin Hilman , "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , santosh.shilimkar@ti.com, felipe.balbi@nokia.com, Eduardo Valentin Subject: [PATCHv3 2/4] mach-omap2: Add SoC info data for OMAP2, 3, 4 into /proc/cpuinfo Date: Wed, 28 Apr 2010 08:51:41 +0300 Message-Id: <1272433903-24003-3-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1272433903-24003-1-git-send-email-eduardo.valentin@nokia.com> References: <1272433903-24003-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 28 Apr 2010 05:51:22.0492 (UTC) FILETIME=[D4E7BBC0:01CAE696] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Apr 2010 05:51:41 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a..4702ffe 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -104,7 +104,7 @@ static u16 tap_prod_id; void __init omap24xx_check_revision(void) { - int i, j; + int i, j, sz; u32 idcode, prod_id; u16 hawkeye; u8 dev_type, rev; @@ -152,10 +152,12 @@ void __init omap24xx_check_revision(void) j = i; } - pr_info("OMAP%04x", omap_rev() >> 16); + sz = snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "OMAP%04x", + omap_rev() >> 16); if ((omap_rev() >> 8) & 0x0f) - pr_info("ES%x", (omap_rev() >> 12) & 0xf); - pr_info("\n"); + snprintf(system_soc_info + sz, SYSTEM_SOC_INFO_SIZE - sz, + "ES%x", (omap_rev() >> 12) & 0xf); + pr_info("%s\n", system_soc_info); } #define OMAP3_CHECK_FEATURE(status,feat) \ @@ -286,7 +288,9 @@ void __init omap4_check_revision(void) if ((hawkeye == 0xb852) && (rev == 0x0)) { omap_revision = OMAP4430_REV_ES1_0; omap_chip.oc |= CHIP_IS_OMAP4430ES1; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); + snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "OMAP%04x %s\n", + omap_rev() >> 16, rev_name); + pr_info("%s\n", system_soc_info); return; } @@ -356,7 +360,9 @@ void __init omap3_cpuinfo(void) } /* Print verbose information */ - pr_info("%s ES%s (", cpu_name, cpu_rev); + snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "%s ES%s", cpu_name, + cpu_rev); + pr_info("%s (", system_soc_info); OMAP3_SHOW_FEATURE(l2cache); OMAP3_SHOW_FEATURE(iva); From patchwork Thu Jun 17 10:40:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106659 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAfDgB010572 for ; Thu, 17 Jun 2010 10:41:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759822Ab0FQKlA (ORCPT ); Thu, 17 Jun 2010 06:41:00 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:53706 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759810Ab0FQKk7 (ORCPT ); Thu, 17 Jun 2010 06:40:59 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAelpu007928 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:50 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAei1G015339; Thu, 17 Jun 2010 16:10:44 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAeivp005286; Thu, 17 Jun 2010 16:10:44 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAeirE005283; Thu, 17 Jun 2010 16:10:44 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Mike Frysinger , Ajay Kumar Gupta Subject: [PATCH 5/8] usb: musb: fix Blackfin ulpi stubs Date: Thu, 17 Jun 2010 16:10:38 +0530 Message-Id: <1276771242-5201-6-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-5-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> <1276771242-5201-5-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:14 +0000 (UTC) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 7cc8398..4f43db7 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -219,8 +219,8 @@ static int musb_ulpi_write(struct otg_transceiver *otg, return 0; } #else -#define musb_ulpi_read(a, b) NULL -#define musb_ulpi_write(a, b, c) NULL +#define musb_ulpi_read NULL +#define musb_ulpi_write NULL #endif static struct otg_io_access_ops musb_ulpi_access = { From patchwork Tue Aug 3 13:49:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Basak, Partha" X-Patchwork-Id: 116772 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o73DnpQm031083 for ; Tue, 3 Aug 2010 13:49:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756725Ab0HCNtu (ORCPT ); Tue, 3 Aug 2010 09:49:50 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:34888 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755867Ab0HCNts convert rfc822-to-8bit (ORCPT ); Tue, 3 Aug 2010 09:49:48 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o73DniE5030930 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 3 Aug 2010 08:49:46 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o73DngMp015970; Tue, 3 Aug 2010 19:19:42 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Tue, 3 Aug 2010 19:19:42 +0530 From: "Basak, Partha" To: "Basak, Partha" , Kevin Hilman CC: Paul Walmsley , "linux-omap@vger.kernel.org" , "Kalliguddi, Hema" , "Raja, Govindraj" , "Varadarajan, Charulatha" , "Nayak, Rajendra" , "Cousson, Benoit" Date: Tue, 3 Aug 2010 19:19:40 +0530 Subject: Issues with calling pm_runtime functions in platform_pm_suspend_noirq/IRQ disabled context. Thread-Topic: Issues with calling pm_runtime functions in platform_pm_suspend_noirq/IRQ disabled context. Thread-Index: AcszBKFQdmIr2IusRju0mNvXcq/jCgADa1NA Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 03 Aug 2010 13:49:52 +0000 (UTC) diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c index 9719a9f..5e453dc 100644 (file) --- a/arch/arm/mach-omap2/pm_bus.c +++ b/arch/arm/mach-omap2/pm_bus.c @@ -68,3 +68,51 @@ int platform_pm_runtime_idle(struct device *dev) }; #endif /* CONFIG_PM_RUNTIME */ +#ifdef CONFIG_SUSPEND +int platform_pm_suspend_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->suspend_noirq) + ret = drv->pm->suspend_noirq(dev); + } + + /* + * The DPM core has done a 'get' to prevent runtime PM + * transitions during system PM. This put is to balance + * out that get so that this device can now be runtime + * suspended. + */ + pm_runtime_put_sync(dev); + + return ret; +} + +int platform_pm_resume_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + /* + * This 'get' is to balance the 'put' in the above suspend_noirq + * method so that the runtime PM usage counting is in the same + * state it was when suspend was called. + */ + pm_runtime_get_sync(dev); + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->resume_noirq) + ret = drv->pm->resume_noirq(dev); + } + + return ret; +} +#endif /* CONFIG_SUSPEND */ From patchwork Tue May 18 12:08:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 100439 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4IC8peV021616 for ; Tue, 18 May 2010 12:08:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757162Ab0ERMIq (ORCPT ); Tue, 18 May 2010 08:08:46 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:34230 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756176Ab0ERMIq (ORCPT ); Tue, 18 May 2010 08:08:46 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4IC8gJ0022575 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 18 May 2010 07:08:45 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4IC8fxY008233; Tue, 18 May 2010 17:38:41 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o4IC8f1F028815; Tue, 18 May 2010 17:38:41 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o4IC8eWG028812; Tue, 18 May 2010 17:38:40 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, Ajay Kumar Gupta Subject: [PATCH 6/6 v2] musb: dma: use optimal transfer element for sdma Date: Tue, 18 May 2010 17:38:40 +0530 Message-Id: <1274184520-28783-1-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 18 May 2010 12:08:51 +0000 (UTC) diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index d29e487..22a2978 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c @@ -52,11 +52,34 @@ static void musb_sdma_channel_program(struct musb *musb, struct musb_dma_channel *musb_channel, dma_addr_t dma_addr, u32 len) { + u16 frame = len; + int data_type = OMAP_DMA_DATA_TYPE_S8; + + switch (dma_addr & 0x3) { + case 0: + if ((len % 4) == 0) { + data_type = OMAP_DMA_DATA_TYPE_S32; + frame = len / 4; + break; + } + case 2: + if ((len % 2) == 0) { + data_type = OMAP_DMA_DATA_TYPE_S16; + frame = len / 2; + break; + } + case 1: + case 3: + default: + data_type = OMAP_DMA_DATA_TYPE_S8; + frame = len; + break; + } /* set transfer parameters */ omap_set_dma_transfer_params(musb_channel->sysdma_channel, - OMAP_DMA_DATA_TYPE_S8, - len ? len : 1, 1, /* One frame */ - OMAP_DMA_SYNC_ELEMENT, + data_type, + len ? frame : 1, 1, /* One frame */ + OMAP_DMA_SYNC_FRAME, OMAP24XX_DMA_NO_DEVICE, 0); /* Src Sync */ From patchwork Tue Apr 13 10:41:51 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roman Tereshonkov X-Patchwork-Id: 92154 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3DAgLRa009465 for ; Tue, 13 Apr 2010 10:42:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752694Ab0DMKmS (ORCPT ); Tue, 13 Apr 2010 06:42:18 -0400 Received: from smtp.nokia.com ([192.100.122.230]:60773 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752520Ab0DMKmR (ORCPT ); Tue, 13 Apr 2010 06:42:17 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3DAfk5a027711; Tue, 13 Apr 2010 13:42:02 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Apr 2010 13:41:53 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Apr 2010 13:41:52 +0300 Received: from localhost.localdomain (ramses.research.nokia.com [172.21.51.130]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3DAfpQY006890; Tue, 13 Apr 2010 13:41:51 +0300 From: Roman Tereshonkov To: spi-devel-general@lists.sourceforge.net, glikely@secretlab.ca Cc: linux-omap@vger.kernel.org, juuso.oikarinen@nokia.com, Roman Tereshonkov Subject: [PATCH] omap2_mcspi: add turbo mode support Date: Tue, 13 Apr 2010 13:41:51 +0300 Message-Id: <1271155311-24809-1-git-send-email-roman.tereshonkov@nokia.com> X-Mailer: git-send-email 1.6.2.rc1.3.g81d3f X-OriginalArrivalTime: 13 Apr 2010 10:41:52.0901 (UTC) FILETIME=[EE0AD350:01CADAF5] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 13 Apr 2010 10:42:21 +0000 (UTC) diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index d87ca43..ac1fef1 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -38,7 +38,7 @@ #include #include - +#include #define OMAP2_MCSPI_MAX_FREQ 48000000 @@ -228,6 +228,8 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); + /* Flash post-writes */ + mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); } static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) @@ -302,11 +304,14 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) unsigned int count, c; unsigned long base, tx_reg, rx_reg; int word_len, data_type, element_count; + int elements; + u32 l; u8 * rx; const u8 * tx; mcspi = spi_master_get_devdata(spi->master); mcspi_dma = &mcspi->dma_channels[spi->chip_select]; + l = mcspi_cached_chconf0(spi); count = xfer->len; c = count; @@ -345,8 +350,12 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) } if (rx != NULL) { + elements = element_count - 1; + if (l & OMAP2_MCSPI_CHCONF_TURBO) + elements--; + omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, - data_type, element_count - 1, 1, + data_type, elements, 1, OMAP_DMA_SYNC_ELEMENT, mcspi_dma->dma_rx_sync_dev, 1); @@ -378,17 +387,42 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) wait_for_completion(&mcspi_dma->dma_rx_completion); dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE); omap2_mcspi_set_enable(spi, 0); + + if (l & OMAP2_MCSPI_CHCONF_TURBO) { + + if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) + & OMAP2_MCSPI_CHSTAT_RXS)) { + u32 w; + + w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); + if (word_len <= 8) + ((u8 *)xfer->rx_buf)[elements++] = w; + else if (word_len <= 16) + ((u16 *)xfer->rx_buf)[elements++] = w; + else /* word_len <= 32 */ + ((u32 *)xfer->rx_buf)[elements++] = w; + } else { + dev_err(&spi->dev, + "DMA RX penultimate word empty"); + count -= (word_len <= 8) ? 2 : + (word_len <= 16) ? 4 : + /* word_len <= 32 */ 8; + omap2_mcspi_set_enable(spi, 1); + return count; + } + } + if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) & OMAP2_MCSPI_CHSTAT_RXS)) { u32 w; w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); if (word_len <= 8) - ((u8 *)xfer->rx_buf)[element_count - 1] = w; + ((u8 *)xfer->rx_buf)[elements] = w; else if (word_len <= 16) - ((u16 *)xfer->rx_buf)[element_count - 1] = w; + ((u16 *)xfer->rx_buf)[elements] = w; else /* word_len <= 32 */ - ((u32 *)xfer->rx_buf)[element_count - 1] = w; + ((u32 *)xfer->rx_buf)[elements] = w; } else { dev_err(&spi->dev, "DMA RX last word empty"); count -= (word_len <= 8) ? 1 : @@ -432,7 +466,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) word_len = cs->word_len; l = mcspi_cached_chconf0(spi); - l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; /* We store the pre-calculated register addresses on stack to speed * up the transfer loop. */ @@ -467,11 +500,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) dev_err(&spi->dev, "RXS timed out\n"); goto out; } - /* prevent last RX_ONLY read from triggering - * more word i/o: switch to rx+tx - */ - if (c == 0 && tx == NULL) - mcspi_write_chconf0(spi, l); + + if (c == 1 && tx == NULL && + (l & OMAP2_MCSPI_CHCONF_TURBO)) { + omap2_mcspi_set_enable(spi, 0); + *rx++ = __raw_readl(rx_reg); +#ifdef VERBOSE + dev_dbg(&spi->dev, "read-%d %02x\n", + word_len, *(rx - 1)); +#endif + if (mcspi_wait_for_reg_bit(chstat_reg, + OMAP2_MCSPI_CHSTAT_RXS) < 0) { + dev_err(&spi->dev, + "RXS timed out\n"); + goto out; + } + c = 0; + } else if (c == 0 && tx == NULL) { + omap2_mcspi_set_enable(spi, 0); + } + *rx++ = __raw_readl(rx_reg); #ifdef VERBOSE dev_dbg(&spi->dev, "read-%d %02x\n", @@ -505,11 +553,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) dev_err(&spi->dev, "RXS timed out\n"); goto out; } - /* prevent last RX_ONLY read from triggering - * more word i/o: switch to rx+tx - */ - if (c == 0 && tx == NULL) - mcspi_write_chconf0(spi, l); + + if (c == 2 && tx == NULL && + (l & OMAP2_MCSPI_CHCONF_TURBO)) { + omap2_mcspi_set_enable(spi, 0); + *rx++ = __raw_readl(rx_reg); +#ifdef VERBOSE + dev_dbg(&spi->dev, "read-%d %04x\n", + word_len, *(rx - 1)); +#endif + if (mcspi_wait_for_reg_bit(chstat_reg, + OMAP2_MCSPI_CHSTAT_RXS) < 0) { + dev_err(&spi->dev, + "RXS timed out\n"); + goto out; + } + c = 0; + } else if (c == 0 && tx == NULL) { + omap2_mcspi_set_enable(spi, 0); + } + *rx++ = __raw_readl(rx_reg); #ifdef VERBOSE dev_dbg(&spi->dev, "read-%d %04x\n", @@ -543,11 +606,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) dev_err(&spi->dev, "RXS timed out\n"); goto out; } - /* prevent last RX_ONLY read from triggering - * more word i/o: switch to rx+tx - */ - if (c == 0 && tx == NULL) - mcspi_write_chconf0(spi, l); + + if (c == 4 && tx == NULL && + (l & OMAP2_MCSPI_CHCONF_TURBO)) { + omap2_mcspi_set_enable(spi, 0); + *rx++ = __raw_readl(rx_reg); +#ifdef VERBOSE + dev_dbg(&spi->dev, "read-%d %08x\n", + word_len, *(rx - 1)); +#endif + if (mcspi_wait_for_reg_bit(chstat_reg, + OMAP2_MCSPI_CHSTAT_RXS) < 0) { + dev_err(&spi->dev, + "RXS timed out\n"); + goto out; + } + c = 0; + } else if (c == 0 && tx == NULL) { + omap2_mcspi_set_enable(spi, 0); + } + *rx++ = __raw_readl(rx_reg); #ifdef VERBOSE dev_dbg(&spi->dev, "read-%d %04x\n", @@ -567,6 +645,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) dev_err(&spi->dev, "EOT timed out\n"); } out: + omap2_mcspi_set_enable(spi, 1); return count - c; } @@ -796,6 +875,7 @@ static void omap2_mcspi_work(struct work_struct *work) struct spi_transfer *t = NULL; int cs_active = 0; struct omap2_mcspi_cs *cs; + struct omap2_mcspi_device_config *cd; int par_override = 0; int status = 0; u32 chconf; @@ -808,6 +888,7 @@ static void omap2_mcspi_work(struct work_struct *work) spi = m->spi; cs = spi->controller_state; + cd = spi->controller_data; omap2_mcspi_set_enable(spi, 1); list_for_each_entry(t, &m->transfers, transfer_list) { @@ -831,10 +912,19 @@ static void omap2_mcspi_work(struct work_struct *work) chconf = mcspi_cached_chconf0(spi); chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; + chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; + if (t->tx_buf == NULL) chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; else if (t->rx_buf == NULL) chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; + + if (cd && cd->turbo_mode && t->tx_buf == NULL) { + /* Turbo mode is for more than one word */ + if (t->len > ((cs->word_len + 7) >> 3)) + chconf |= OMAP2_MCSPI_CHCONF_TURBO; + } + mcspi_write_chconf0(spi, chconf); if (t->len) { From patchwork Tue Apr 27 11:56:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ranjith Lohithakshan X-Patchwork-Id: 95379 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3RBuCuw006499 for ; Tue, 27 Apr 2010 11:56:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753077Ab0D0L4L (ORCPT ); Tue, 27 Apr 2010 07:56:11 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:59382 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751396Ab0D0L4K (ORCPT ); Tue, 27 Apr 2010 07:56:10 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3RBu5ZE027322 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 27 Apr 2010 06:56:08 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3RBu1dc000680; Tue, 27 Apr 2010 17:26:03 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o3RBu1Di025181; Tue, 27 Apr 2010 17:26:01 +0530 Received: (from a0876318@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o3RBu1Ku025178; Tue, 27 Apr 2010 17:26:01 +0530 From: Ranjith Lohithakshan To: linux-omap@vger.kernel.org Cc: tony@atomide.com, ranjithl@ti.com Subject: [PATCH] OMAP3EVM: Update pad configuration for wakeup enabled pads Date: Tue, 27 Apr 2010 17:26:01 +0530 Message-Id: <1272369361-25147-1-git-send-email-ranjithl@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 27 Apr 2010 11:56:13 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 017bb2f..ce66ef0 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -650,12 +650,16 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { +#ifdef CONFIG_KEYBOARD_TWL4030 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | OMAP_PIN_OFF_WAKEUPENABLE), +#endif +#ifdef CONFIG_TOUCHSCREEN_ADS7846 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | OMAP_PIN_OFF_WAKEUPENABLE), +#endif { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else From patchwork Mon Jul 19 11:55:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 112649 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6JBttc8026289 for ; Mon, 19 Jul 2010 11:56:07 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760632Ab0GSL4G (ORCPT ); Mon, 19 Jul 2010 07:56:06 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:47593 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760621Ab0GSL4F (ORCPT ); Mon, 19 Jul 2010 07:56:05 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6JBtwxY001683 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 19 Jul 2010 06:55:58 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6JBtuSC023201; Mon, 19 Jul 2010 06:55:56 -0500 (CDT) Received: from localhost (omaplbp.india.ti.com [172.24.190.217]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6JBtrP02506; Mon, 19 Jul 2010 06:55:53 -0500 (CDT) From: Archit Taneja To: tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Sumit Semwal , Mukund Mittal , Archit Taneja Subject: [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC Date: Mon, 19 Jul 2010 17:25:41 +0530 Message-Id: <1279540544-12682-3-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1279540544-12682-2-git-send-email-archit@ti.com> References: <1279540544-12682-1-git-send-email-archit@ti.com> <1279540544-12682-2-git-send-email-archit@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 19 Jul 2010 11:56:07 +0000 (UTC) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 48167a2..00aad04 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -138,6 +138,33 @@ struct dispc_reg { u16 idx; }; #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) +/* DISPC Video plane, n = 0 for VID3, n = 1 for WB */ +#define DISPC_VID3_WB_REG(n, idx) DISPC_REG(0x0300 + (n)*0x200 + idx) + +#define DISPC_VID3_WB_ACCU0(n) DISPC_VID3_WB_REG(n, 0x0000) +#define DISPC_VID3_WB_ACCU1(n) DISPC_VID3_WB_REG(n, 0x0004) +#define DISPC_VID3_WB_BA0(n) DISPC_VID3_WB_REG(n, 0x0008) +#define DISPC_VID3_WB_BA1(n) DISPC_VID3_WB_REG(n, 0x000C) +#define DISPC_VID3_WB_ATTRIBUTES(n) DISPC_VID3_WB_REG(n, 0x0070) +#define DISPC_VID3_WB_BUF_SIZE_STATUS(n) DISPC_VID3_WB_REG(n, 0x0088) +#define DISPC_VID3_WB_BUF_THRESHOLD(n) DISPC_VID3_WB_REG(n, 0x008C) +#define DISPC_VID3_WB_FIR(n) DISPC_VID3_WB_REG(n, 0x0090) +#define DISPC_VID3_WB_PICTURE_SIZE(n) DISPC_VID3_WB_REG(n, 0x0094) +#define DISPC_VID3_WB_PIXEL_INC(n) DISPC_VID3_WB_REG(n, 0x0098) +#define DISPC_VID3_WB_ROW_INC(n) DISPC_VID3_WB_REG(n, 0x00A4) +#define DISPC_VID3_WB_SIZE(n) DISPC_VID3_WB_REG(n, 0x00A8) + +/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ +#define DISPC_VID3_WB_FIR_COEF_H(n, i) DISPC_REG(0x0310 + (n)*0x200 + (i)*0x8) +/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ +#define DISPC_VID3_WB_FIR_COEF_HV(n, i) DISPC_REG(0x0314 + (n)*0x200 + (i)*0x8) +/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ +#define DISPC_VID3_WB_FIR_COEF_V(n, i) DISPC_REG(0x0350 + (n)*0x200 + (i)*0x4) +/* coef index i = {0, 1, 2, 3, 4} */ +#define DISPC_VID3_WB_CONV_COEF(n, i) DISPC_REG(0x0374 + (n)*0x200 + (i)*0x4) + +#define DISPC_VID3_POSITION DISPC_REG(0x039C) +#define DISPC_VID3_PRELOAD DISPC_REG(0x03A0) #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ DISPC_IRQ_OCP_ERR | \ @@ -164,7 +191,8 @@ struct omap_dispc_isr_data { static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES, DISPC_VID_ATTRIBUTES(0), - DISPC_VID_ATTRIBUTES(1) }; + DISPC_VID_ATTRIBUTES(1), + DISPC_VID3_WB_ATTRIBUTES(0) }; /* VID 3 pipeline */ struct dispc_irq_stats { unsigned long last_reset; @@ -603,21 +631,30 @@ static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value) { BUG_ON(plane == OMAP_DSS_GFX); - dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value); + if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane)) + dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value); + else if (OMAP_DSS_VIDEO3 == plane) + dispc_write_reg(DISPC_VID3_WB_FIR_COEF_H(0, reg), value); } static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value) { BUG_ON(plane == OMAP_DSS_GFX); - dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value); + if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane)) + dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value); + else if (OMAP_DSS_VIDEO3 == plane) + dispc_write_reg(DISPC_VID3_WB_FIR_COEF_HV(0, reg), value); } static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value) { BUG_ON(plane == OMAP_DSS_GFX); - dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value); + if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane)) + dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value); + else if (OMAP_DSS_VIDEO3 == plane) + dispc_write_reg(DISPC_VID3_WB_FIR_COEF_V(0, reg), value); } static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, @@ -801,11 +838,25 @@ static void _dispc_setup_color_conv_coef(void) dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr)); dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by)); dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb)); - + if (cpu_is_omap44xx()) { + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 0), + CVAL(ct->rcr, ct->ry)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 1), + CVAL(ct->gy, ct->rcb)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 2), + CVAL(ct->gcb, ct->gcr)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 3), + CVAL(ct->bcr, ct->by)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 4), + CVAL(0, ct->bcb)); + } #undef CVAL REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); + if (cpu_is_omap44xx()) + REG_FLD_MOD(DISPC_VID3_WB_ATTRIBUTES(0), + ct->full_range, 11, 11); } @@ -813,7 +864,8 @@ static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) { const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0, DISPC_VID_BA0(0), - DISPC_VID_BA0(1) }; + DISPC_VID_BA0(1), + DISPC_VID3_WB_BA0(0) }; dispc_write_reg(ba0_reg[plane], paddr); } @@ -821,8 +873,9 @@ static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr) { const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1, - DISPC_VID_BA1(0), - DISPC_VID_BA1(1) }; + DISPC_VID_BA1(0), + DISPC_VID_BA1(1), + DISPC_VID3_WB_BA1(0) }; dispc_write_reg(ba1_reg[plane], paddr); } @@ -831,7 +884,8 @@ static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y) { const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION, DISPC_VID_POSITION(0), - DISPC_VID_POSITION(1) }; + DISPC_VID_POSITION(1), + DISPC_VID3_POSITION }; u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); dispc_write_reg(pos_reg[plane], val); @@ -841,7 +895,9 @@ static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) { const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE, DISPC_VID_PICTURE_SIZE(0), - DISPC_VID_PICTURE_SIZE(1) }; + DISPC_VID_PICTURE_SIZE(1), + DISPC_VID3_WB_PICTURE_SIZE(0) }; + u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); dispc_write_reg(siz_reg[plane], val); } @@ -849,9 +905,9 @@ static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) { u32 val; - const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0), - DISPC_VID_SIZE(1) }; - + struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0), + DISPC_VID_SIZE(1), + DISPC_VID3_WB_SIZE(0) }; BUG_ON(plane == OMAP_DSS_GFX); val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); @@ -870,13 +926,16 @@ static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha) REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0); else if (plane == OMAP_DSS_VIDEO2) REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16); + else if (plane == OMAP_DSS_VIDEO3) + REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 31, 24); } static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc) { const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC, DISPC_VID_PIXEL_INC(0), - DISPC_VID_PIXEL_INC(1) }; + DISPC_VID_PIXEL_INC(1), + DISPC_VID3_WB_PIXEL_INC(0) }; dispc_write_reg(ri_reg[plane], inc); } @@ -885,7 +944,8 @@ static void _dispc_set_row_inc(enum omap_plane plane, s32 inc) { const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC, DISPC_VID_ROW_INC(0), - DISPC_VID_ROW_INC(1) }; + DISPC_VID_ROW_INC(1), + DISPC_VID3_WB_ROW_INC(0) }; dispc_write_reg(ri_reg[plane], inc); } @@ -944,6 +1004,7 @@ static void _dispc_set_channel_out(enum omap_plane plane, break; case OMAP_DSS_VIDEO1: case OMAP_DSS_VIDEO2: + case OMAP_DSS_VIDEO3: shift = 16; break; default: @@ -993,6 +1054,7 @@ void dispc_set_burst_size(enum omap_plane plane, break; case OMAP_DSS_VIDEO1: case OMAP_DSS_VIDEO2: + case OMAP_DSS_VIDEO3: shift = 14; break; default: @@ -1056,7 +1118,8 @@ static void dispc_read_plane_fifo_sizes(void) { const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS, DISPC_VID_FIFO_SIZE_STATUS(0), - DISPC_VID_FIFO_SIZE_STATUS(1) }; + DISPC_VID_FIFO_SIZE_STATUS(1), + DISPC_VID3_WB_BUF_SIZE_STATUS(0) }; u32 size; int plane; @@ -1067,6 +1130,8 @@ static void dispc_read_plane_fifo_sizes(void) size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0); else if (cpu_is_omap34xx()) size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0); + else if (cpu_is_omap44xx()) + size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 15, 0); else BUG(); @@ -1085,7 +1150,8 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) { const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD, DISPC_VID_FIFO_THRESHOLD(0), - DISPC_VID_FIFO_THRESHOLD(1) }; + DISPC_VID_FIFO_THRESHOLD(1), + DISPC_VID3_WB_BUF_THRESHOLD(0) }; enable_clocks(1); DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", @@ -1097,9 +1163,12 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) if (cpu_is_omap24xx()) dispc_write_reg(ftrs_reg[plane], FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0)); - else + else if (cpu_is_omap34xx()) dispc_write_reg(ftrs_reg[plane], FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0)); + else if (cpu_is_omap44xx()) + dispc_write_reg(ftrs_reg[plane], + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); enable_clocks(0); } @@ -1118,7 +1187,8 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc) { u32 val; const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0), - DISPC_VID_FIR(1) }; + DISPC_VID_FIR(1), + DISPC_VID3_WB_FIR(0) }; BUG_ON(plane == OMAP_DSS_GFX); @@ -1133,11 +1203,15 @@ static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) { u32 val; const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), - DISPC_VID_ACCU0(1) }; + DISPC_VID_ACCU0(1), + DISPC_VID3_WB_ACCU0(0) }; BUG_ON(plane == OMAP_DSS_GFX); - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); + if (cpu_is_omap44xx()) + val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); + else + val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); dispc_write_reg(ac0_reg[plane-1], val); } @@ -1145,11 +1219,15 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) { u32 val; const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), - DISPC_VID_ACCU1(1) }; + DISPC_VID_ACCU1(1), + DISPC_VID3_WB_ACCU1(0) }; BUG_ON(plane == OMAP_DSS_GFX); - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); + if (cpu_is_omap44xx()) + val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); + else + val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); dispc_write_reg(ac1_reg[plane-1], val); } @@ -2563,6 +2641,21 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_VID_ACCU0(1)); DUMPREG(DISPC_VID_ACCU1(1)); + if (cpu_is_omap44xx()) { + DUMPREG(DISPC_VID3_WB_BA0(0)); + DUMPREG(DISPC_VID3_WB_BA1(0)); + DUMPREG(DISPC_VID3_POSITION); + DUMPREG(DISPC_VID3_WB_SIZE(0)); + DUMPREG(DISPC_VID3_WB_ATTRIBUTES(0)); + DUMPREG(DISPC_VID3_WB_BUF_THRESHOLD(0)); + DUMPREG(DISPC_VID3_WB_BUF_SIZE_STATUS(0)); + DUMPREG(DISPC_VID3_WB_ROW_INC(0)); + DUMPREG(DISPC_VID3_WB_PIXEL_INC(0)); + DUMPREG(DISPC_VID3_WB_FIR(0)); + DUMPREG(DISPC_VID3_WB_PICTURE_SIZE(0)); + DUMPREG(DISPC_VID3_WB_ACCU0(0)); + DUMPREG(DISPC_VID3_WB_ACCU1(0)); + } DUMPREG(DISPC_VID_FIR_COEF_H(0, 0)); DUMPREG(DISPC_VID_FIR_COEF_H(0, 1)); DUMPREG(DISPC_VID_FIR_COEF_H(0, 2)); @@ -2623,8 +2716,41 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_VID_FIR_COEF_V(1, 6)); DUMPREG(DISPC_VID_FIR_COEF_V(1, 7)); + if (cpu_is_omap44xx()) { + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 0)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 1)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 2)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 3)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 5)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 6)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 7)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 0)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 1)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 2)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 3)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 5)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 6)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 7)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 0)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 1)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 2)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 3)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 0)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 1)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 2)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 3)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 5)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 6)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 7)); + } DUMPREG(DISPC_VID_PRELOAD(0)); DUMPREG(DISPC_VID_PRELOAD(1)); + if (cpu_is_omap44xx()) + DUMPREG(DISPC_VID3_PRELOAD); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); #undef DUMPREG From patchwork Mon Jul 19 11:55:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 112648 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6JBttc7026289 for ; Mon, 19 Jul 2010 11:55:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760625Ab0GSLz5 (ORCPT ); Mon, 19 Jul 2010 07:55:57 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:35625 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760621Ab0GSLz4 (ORCPT ); Mon, 19 Jul 2010 07:55:56 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6JBtsHh003131 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 19 Jul 2010 06:55:54 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6JBtpaY023180; Mon, 19 Jul 2010 06:55:51 -0500 (CDT) Received: from localhost (omaplbp.india.ti.com [172.24.190.217]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6JBtnP02500; Mon, 19 Jul 2010 06:55:49 -0500 (CDT) From: Archit Taneja To: tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Sumit Semwal , Mukund Mittal , Archit Taneja Subject: [PATCH 1/5] OMAP: DSS2: Add Video3 pipeline in display.h Date: Mon, 19 Jul 2010 17:25:40 +0530 Message-Id: <1279540544-12682-2-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1279540544-12682-1-git-send-email-archit@ti.com> References: <1279540544-12682-1-git-send-email-archit@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 19 Jul 2010 11:55:58 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 56e7045..d1da317 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -62,7 +62,8 @@ enum omap_display_type { enum omap_plane { OMAP_DSS_GFX = 0, OMAP_DSS_VIDEO1 = 1, - OMAP_DSS_VIDEO2 = 2 + OMAP_DSS_VIDEO2 = 2, + OMAP_DSS_VIDEO3 = 3, }; enum omap_channel { @@ -117,6 +118,8 @@ enum omap_color_mode { OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, + + OMAP_DSS_COLOR_VID3_OMAP3 = OMAP_DSS_COLOR_VID2_OMAP3, }; enum omap_lcd_display_type { From patchwork Wed Apr 28 05:51:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 95619 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3S5pbGq005121 for ; Wed, 28 Apr 2010 05:51:55 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753712Ab0D1Fvj (ORCPT ); Wed, 28 Apr 2010 01:51:39 -0400 Received: from smtp.nokia.com ([192.100.122.233]:20106 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753623Ab0D1Fvh (ORCPT ); Wed, 28 Apr 2010 01:51:37 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3S5oxDb006915; Wed, 28 Apr 2010 08:51:27 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 08:51:26 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 08:51:22 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3S5pKkZ001721; Wed, 28 Apr 2010 08:51:22 +0300 From: Eduardo Valentin To: linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: ext Tony Lindgren , ext Kevin Hilman , "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , santosh.shilimkar@ti.com, felipe.balbi@nokia.com, Eduardo Valentin Subject: [PATCHv3 3/4] mach-omap1: Add SoC info data for OMAP1 into /proc/cpuinfo Date: Wed, 28 Apr 2010 08:51:42 +0300 Message-Id: <1272433903-24003-4-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1272433903-24003-1-git-send-email-eduardo.valentin@nokia.com> References: <1272433903-24003-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 28 Apr 2010 05:51:22.0960 (UTC) FILETIME=[D52F2500:01CAE696] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Apr 2010 05:51:56 +0000 (UTC) diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index a0e3560..9a84347 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -120,7 +120,7 @@ static u8 __init omap_get_die_rev(void) void __init omap_check_revision(void) { - int i; + int i, sz; u16 jtag_id; u8 die_rev; u32 omap_id; @@ -194,11 +194,14 @@ void __init omap_check_revision(void) printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type); } - printk(KERN_INFO "OMAP%04x", omap_revision >> 16); + sz = snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "OMAP%04x", + omap_revision >> 16); if ((omap_revision >> 8) & 0xff) - printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff); - printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n", - die_rev, omap_revision & 0xff, system_serial_low, - system_serial_high); + snprintf(system_soc_info + sz, SYSTEM_SOC_INFO_SIZE - sz, + "%x", (omap_revision >> 8) & 0xff); + pr_info("%s revision %i handled as %02xxx id: %08x%08x\n", + system_soc_info, die_rev, omap_revision & 0xff, + system_serial_low, system_serial_high); + } From patchwork Wed May 5 14:27:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97108 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5PC002693 for ; Wed, 5 May 2010 14:28:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934826Ab0EEO2N (ORCPT ); Wed, 5 May 2010 10:28:13 -0400 Received: from smtp.nokia.com ([192.100.122.230]:65022 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932540Ab0EEO2I (ORCPT ); Wed, 5 May 2010 10:28:08 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERrll008227; Wed, 5 May 2010 17:28:05 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:53 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:52 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfR8016232; Wed, 5 May 2010 17:27:51 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 06/21] OMAP: DSS2: Taal: Fix request_irq() error handling Date: Wed, 5 May 2010 17:27:26 +0300 Message-Id: <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:52.0225 (UTC) FILETIME=[251DF910:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:19 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index b7d1275..788aa91 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -603,7 +603,7 @@ static int taal_probe(struct omap_dss_device *dssdev) if (r) { dev_err(&dssdev->dev, "IRQ request failed\n"); gpio_free(gpio); - goto err3; + goto err4; } init_completion(&td->te_completion); @@ -614,16 +614,16 @@ static int taal_probe(struct omap_dss_device *dssdev) r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group); if (r) { dev_err(&dssdev->dev, "failed to create sysfs files\n"); - goto err4; + goto err5; } return 0; +err5: + if (td->use_ext_te) + free_irq(gpio_to_irq(dssdev->phy.dsi.ext_te_gpio), dssdev); err4: - if (td->use_ext_te) { - int gpio = dssdev->phy.dsi.ext_te_gpio; - free_irq(gpio_to_irq(gpio), dssdev); - gpio_free(gpio); - } + if (td->use_ext_te) + gpio_free(dssdev->phy.dsi.ext_te_gpio); err3: backlight_device_unregister(bldev); err2: From patchwork Wed Jul 7 09:44:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110597 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679iW1B027868 for ; Wed, 7 Jul 2010 09:44:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754591Ab0GGJob (ORCPT ); Wed, 7 Jul 2010 05:44:31 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:59081 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754518Ab0GGJob (ORCPT ); Wed, 7 Jul 2010 05:44:31 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRB8-000IIk-H1; Wed, 07 Jul 2010 09:44:30 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1/e+shoTxi5bfp2aWXxcRn6 Subject: [PATCH 08/13] omap: rx51: Add supply and data for the tpa6130a2 headphoneamplifier To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Jarkko Nikula , linux-omap@vger.kernel.org Date: Wed, 07 Jul 2010 12:44:29 +0300 Message-ID: <20100707094429.2562.1171.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:33 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index b4c3dd7..3c3f975 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -33,6 +33,7 @@ #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -314,6 +315,8 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { /* tlv320aic3x analog supplies */ REGULATOR_SUPPLY("AVDD", "2-0018"), REGULATOR_SUPPLY("DRVDD", "2-0018"), + /* tpa6130a2 */ + REGULATOR_SUPPLY("Vdd", "2-0060"), /* Keep vmmc as last item. It is not iterated for newer boards */ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), }; @@ -692,6 +695,11 @@ static struct aic3x_pdata rx51_aic3x_data __initdata = { .gpio_reset = 60, }; +static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { + .id = TPA6130A2, + .power_gpio = 98, +}; + static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { { I2C_BOARD_INFO("twl5030", 0x48), @@ -706,6 +714,10 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { I2C_BOARD_INFO("tlv320aic3x", 0x18), .platform_data = &rx51_aic3x_data, }, + { + I2C_BOARD_INFO("tpa6130a2", 0x60), + .platform_data = &rx51_tpa6130a2_data, + } }; static int __init rx51_i2c_init(void) From patchwork Wed Jul 7 09:44:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110596 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679iTgK027847 for ; Wed, 7 Jul 2010 09:44:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754584Ab0GGJo2 (ORCPT ); Wed, 7 Jul 2010 05:44:28 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:59759 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754518Ab0GGJo2 (ORCPT ); Wed, 7 Jul 2010 05:44:28 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRB3-000Jkr-Cj; Wed, 07 Jul 2010 09:44:27 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1+xXIiHiiBrSK+3HJqg8Hjz Subject: [PATCH 07/13] omap: rx51: Use REGULATOR_SUPPLY macro when initializingregulator consumers To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Jarkko Nikula , linux-omap@vger.kernel.org, Eduardo Valentin Date: Wed, 07 Jul 2010 12:44:23 +0300 Message-ID: <20100707094423.2562.78977.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:30 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index e350f0b..b4c3dd7 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -301,48 +301,27 @@ static struct omap2_hsmmc_info mmc[] __initdata = { {} /* Terminator */ }; -static struct regulator_consumer_supply rx51_vmmc1_supply = { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.0", -}; +static struct regulator_consumer_supply rx51_vmmc1_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -static struct regulator_consumer_supply rx51_vaux3_supply = { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", -}; +static struct regulator_consumer_supply rx51_vaux3_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -static struct regulator_consumer_supply rx51_vsim_supply = { - .supply = "vmmc_aux", - .dev_name = "mmci-omap-hs.1", -}; +static struct regulator_consumer_supply rx51_vsim_supply = + REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { /* tlv320aic3x analog supplies */ - { - .supply = "AVDD", - .dev_name = "2-0018", - }, - { - .supply = "DRVDD", - .dev_name = "2-0018", - }, + REGULATOR_SUPPLY("AVDD", "2-0018"), + REGULATOR_SUPPLY("DRVDD", "2-0018"), /* Keep vmmc as last item. It is not iterated for newer boards */ - { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", - }, + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), }; static struct regulator_consumer_supply rx51_vio_supplies[] = { /* tlv320aic3x digital supplies */ - { - .supply = "IOVDD", - .dev_name = "2-0018" - }, - { - .supply = "DVDD", - .dev_name = "2-0018" - }, + REGULATOR_SUPPLY("IOVDD", "2-0018"), + REGULATOR_SUPPLY("DVDD", "2-0018"), }; #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) From patchwork Sun Apr 25 10:53:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Y, Kishore" X-Patchwork-Id: 94937 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3PAqX13016444 for ; Sun, 25 Apr 2010 10:52:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753408Ab0DYKwW (ORCPT ); Sun, 25 Apr 2010 06:52:22 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:54495 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753398Ab0DYKwV convert rfc822-to-8bit (ORCPT ); Sun, 25 Apr 2010 06:52:21 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3PAqDPd012851 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 25 Apr 2010 05:52:16 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3PAqDpQ027735; Sun, 25 Apr 2010 16:22:13 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Sun, 25 Apr 2010 16:22:13 +0530 From: "Y, Kishore" To: Tomi Valkeinen CC: "linux-omap@vger.kernel.org" Date: Sun, 25 Apr 2010 16:23:35 +0530 Subject: [PATCH] OMAP:DSS: Add missing line for update bg color Thread-Topic: [PATCH] OMAP:DSS: Add missing line for update bg color Thread-Index: AcrkZY3AMbM5fmbQQImS5SSQLQiFeQ== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 25 Apr 2010 10:52:34 +0000 (UTC) diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index c12fa14..72d53eb 100644 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -845,6 +845,7 @@ static void configure_manager(enum omap_channel channel) c = &dss_cache.manager_cache[channel]; + dispc_set_default_color(channel, c->default_color); dispc_set_trans_key(channel, c->trans_key_type, c->trans_key); dispc_enable_trans_key(channel, c->trans_enabled); dispc_enable_alpha_blending(channel, c->alpha_enabled); From patchwork Thu Jun 17 10:40:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106658 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HAf67s010533 for ; Thu, 17 Jun 2010 10:41:07 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756989Ab0FQKlE (ORCPT ); Thu, 17 Jun 2010 06:41:04 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:53705 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759814Ab0FQKk7 (ORCPT ); Thu, 17 Jun 2010 06:40:59 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HAelMW007924 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 05:40:49 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HAehMc015336; Thu, 17 Jun 2010 16:10:44 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o5HAehha005266; Thu, 17 Jun 2010 16:10:43 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o5HAehBE005263; Thu, 17 Jun 2010 16:10:43 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Sergei Shtylyov , Ajay Kumar Gupta Subject: [PATCH 2/8] MUSB: make non-OMAP platforms build with CONFIG_PM=y Date: Thu, 17 Jun 2010 16:10:35 +0530 Message-Id: <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 10:41:07 +0000 (UTC) diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index b22d02d..91d6779 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -470,7 +470,8 @@ struct musb_csr_regs { struct musb_context_registers { -#ifdef CONFIG_PM +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) u32 otg_sysconfig, otg_forcestandby; #endif u8 power; @@ -484,7 +485,8 @@ struct musb_context_registers { struct musb_csr_regs index_regs[MUSB_C_NUM_EPS]; }; -#ifdef CONFIG_PM +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) extern void musb_platform_save_context(struct musb *musb, struct musb_context_registers *musb_context); extern void musb_platform_restore_context(struct musb *musb, From patchwork Wed Jul 7 09:44:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110595 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679iOm3027834 for ; Wed, 7 Jul 2010 09:44:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754573Ab0GGJoX (ORCPT ); Wed, 7 Jul 2010 05:44:23 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:58942 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754518Ab0GGJoW (ORCPT ); Wed, 7 Jul 2010 05:44:22 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRAz-000IGe-PF; Wed, 07 Jul 2010 09:44:22 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19DC0SvvNVO/qCqBAzVzpsB Subject: [PATCH 06/13] omap: rx51: Add platform_data for tlv320aic3x with reset gpionumber To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: Jarkko Nikula , linux-omap@vger.kernel.org Date: Wed, 07 Jul 2010 12:44:20 +0300 Message-ID: <20100707094420.2562.76871.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:24 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 3d95534..e350f0b 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -32,6 +32,8 @@ #include #include +#include + #include "mux.h" #include "hsmmc.h" @@ -707,6 +709,10 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .vio = &rx51_vio, }; +static struct aic3x_pdata rx51_aic3x_data __initdata = { + .gpio_reset = 60, +}; + static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { { I2C_BOARD_INFO("twl5030", 0x48), @@ -719,6 +725,7 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { { I2C_BOARD_INFO("tlv320aic3x", 0x18), + .platform_data = &rx51_aic3x_data, }, }; From patchwork Tue Jul 13 14:59:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ye janboe X-Patchwork-Id: 111807 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6DFCr1e012130 for ; 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b=MVvAB2NgiKnmA2PtIfd3oJLVOb5I4EzKLfkcN7jDxB8LI3YqElpbz5qDEegMEvN8yY a2y1bq6G4Z71BdaQPxrKfB3PhUaQFEovRMiPk7t5PdDoe7op3hx9rrZu5/xX8zD891lt KT4DCkDkGXCvJf06lnBSHUaJnXGyuLOI0cq9M= Received: by 10.142.215.7 with SMTP id n7mr19514887wfg.63.1279033207411; Tue, 13 Jul 2010 08:00:07 -0700 (PDT) Received: from localhost.localdomain ([222.130.218.212]) by mx.google.com with ESMTPS id n2sm6246980wfl.13.2010.07.13.08.00.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 13 Jul 2010 08:00:06 -0700 (PDT) Date: Tue, 13 Jul 2010 22:59:53 +0800 From: janboe To: khilman@deeprootsystems.com Cc: linux-omap@vger.kernel.org Subject: [PATCH] omap: gpio: omap3_gpio_pads_init current only works for omap3 Message-ID: <20100713145953.GA17852@localhost.localdomain> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 13 Jul 2010 15:12:53 +0000 (UTC) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 0838c72..bae2649 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -379,6 +379,62 @@ struct gpio_pad { static struct gpio_pad *gpio_pads; static u16 gpio_pad_map[OMAP34XX_GPIO_AMT]; + +/* + * Following pad init code in addition to the context / restore hooks are + * needed to fix glitches in GPIO outputs during off-mode. See OMAP3 + * errate section 1.158 + */ +static int __init omap3_gpio_pads_init(void) +{ + int i, j, min, max, gpio_amt; + u16 offset; + + gpio_amt = 0; + + for (i = 0; i < ARRAY_SIZE(gpio_pads_config); i++) { + min = gpio_pads_config[i].min; + max = gpio_pads_config[i].max; + offset = gpio_pads_config[i].offset; + + for (j = min; j <= max; j++) { + /* + * Check if pad has been configured as GPIO + * (mux mode 4.) + */ + if ((omap_ctrl_readw(offset) & 0x7) == 4) { + gpio_pad_map[j] = offset; + if (j > 31) + gpio_amt++; + } + offset += 2; + } + } + gpio_pads = kmalloc(sizeof(struct gpio_pad) * (gpio_amt + 1), + GFP_KERNEL); + + if (gpio_pads == NULL) { + printk(KERN_ERR "FATAL: Failed to allocate gpio_pads\n"); + return -ENOMEM; + } + + gpio_amt = 0; + for (i = 0; i < OMAP34XX_GPIO_AMT; i++) { + /* + * First module (gpio 0...31) is ignored as it is + * in wakeup domain and does not need special + * handling during off mode. + */ + if (gpio_pad_map[i] && i > 31) { + gpio_pads[gpio_amt].gpio = i; + gpio_pads[gpio_amt].offset = gpio_pad_map[i]; + gpio_amt++; + } + } + gpio_pads[gpio_amt].gpio = -1; + return 0; +} +late_initcall(omap3_gpio_pads_init); #endif #ifdef CONFIG_ARCH_OMAP4 @@ -1750,62 +1806,6 @@ static struct clk * gpio5_fck; #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; - -/* - * Following pad init code in addition to the context / restore hooks are - * needed to fix glitches in GPIO outputs during off-mode. See OMAP3 - * errate section 1.158 - */ -static int __init omap3_gpio_pads_init(void) -{ - int i, j, min, max, gpio_amt; - u16 offset; - - gpio_amt = 0; - - for (i = 0; i < ARRAY_SIZE(gpio_pads_config); i++) { - min = gpio_pads_config[i].min; - max = gpio_pads_config[i].max; - offset = gpio_pads_config[i].offset; - - for (j = min; j <= max; j++) { - /* - * Check if pad has been configured as GPIO - * (mux mode 4.) - */ - if ((omap_ctrl_readw(offset) & 0x7) == 4) { - gpio_pad_map[j] = offset; - if (j > 31) - gpio_amt++; - } - offset += 2; - } - } - gpio_pads = kmalloc(sizeof(struct gpio_pad) * (gpio_amt + 1), - GFP_KERNEL); - - if (gpio_pads == NULL) { - printk(KERN_ERR "FATAL: Failed to allocate gpio_pads\n"); - return -ENOMEM; - } - - gpio_amt = 0; - for (i = 0; i < OMAP34XX_GPIO_AMT; i++) { - /* - * First module (gpio 0...31) is ignored as it is - * in wakeup domain and does not need special - * handling during off mode. - */ - if (gpio_pad_map[i] && i > 31) { - gpio_pads[gpio_amt].gpio = i; - gpio_pads[gpio_amt].offset = gpio_pad_map[i]; - gpio_amt++; - } - } - gpio_pads[gpio_amt].gpio = -1; - return 0; -} -late_initcall(omap3_gpio_pads_init); #endif static void __init omap_gpio_show_rev(void) From patchwork Tue Jul 13 15:06:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjeev Premi X-Patchwork-Id: 111805 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6DF6qhQ011091 for ; Tue, 13 Jul 2010 15:06:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755931Ab0GMPGv (ORCPT ); Tue, 13 Jul 2010 11:06:51 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:42199 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754713Ab0GMPGu convert rfc822-to-8bit (ORCPT ); Tue, 13 Jul 2010 11:06:50 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6DF6aes030763 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 13 Jul 2010 10:06:39 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6DF6WrK013898; Tue, 13 Jul 2010 20:36:33 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Tue, 13 Jul 2010 20:36:32 +0530 From: "Premi, Sanjeev" To: "Menon, Nishanth" , Tony Lindgren CC: "felipe.balbi@nokia.com" , linux-omap , Angelo Arrifano , "Zebediah C. McClure" , Alistair Buxton , Grazvydas Ignotas , Paul Walmsley , "Shilimkar, Santosh" , "Guruswamy, Senthilvadivu" , Kevin Hilman , "DebBarma, Tarun Kanti" , "ValkeinenTomi (Nokia-MS/Helsinki)" , "Koskinen Aaro (Nokia-MS/Helsinki)" , "Pandita, Vikram" , "S, Vishwanath" Date: Tue, 13 Jul 2010 20:36:31 +0530 Subject: RE: [PATCH 3/9 v3] omap: generic: introduce a single check_revision Thread-Topic: [PATCH 3/9 v3] omap: generic: introduce a single check_revision Thread-Index: AcseqcLZj5QRn6otR7qzMBRhpSMbbwD8jlbA Message-ID: References: <1278590256.3787.14.camel@Nokia-N900> <20100708122157.GI1920@atomide.com> <4C35E04B.1090102@ti.com> In-Reply-To: <4C35E04B.1090102@ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 13 Jul 2010 15:06:53 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/ index 7514174..7cc5611 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -70,6 +70,12 @@ unsigned int omap_rev(void); #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 #define OMAP_REVBITS_40 0x40 +#define OMAP_REVBITS_50 0x50 + +/* + * Get the CPU Id for OMAP devices + */ +#define GET_OMAP_ID() ((omap_rev() >> 16) & 0xffff) /* * Get the CPU revision for OMAP devices @@ -385,6 +391,12 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << +#define AM37XX_CLASS 0x37000034 +#define AM3703_REV(v) (AM37XX_CLASS | (0x3503 << 16) | (v << 8)) +#define AM3715_REV(v) (AM37XX_CLASS | (0x3515 << 16) | (v << 8)) +#define AM3725_REV(v) (AM37XX_CLASS | (0x3525 << 16) | (v << 8)) +#define AM3730_REV(v) (AM37XX_CLASS | (0x3530 << 16) | (v << 8)) + #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 0x44300044 @@ -458,4 +470,36 @@ OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) +/* + * Map revision bits to silicon specific revisions + */ +#define OMAP34XX_ES_1_0 OMAP_REVBITS_00 +#define OMAP34XX_ES_2_0 OMAP_REVBITS_10 +#define OMAP34XX_ES_2_1 OMAP_REVBITS_20 +#define OMAP34XX_ES_3_0 OMAP_REVBITS_30 +#define OMAP34XX_ES_3_1 OMAP_REVBITS_40 +#define OMAP34XX_ES_3_1_2 OMAP_REVBITS_50 + +#define AM3517_ES_1_0 OMAP_REVBITS_00 + +#define OMAP36XX_ES_1_0 OMAP_REVBITS_00 + +/* + * Macros to evaluate CPU revision + */ +#define cpu_rev_lt(cpu,rev) \ + ((cpu_is_omap ##cpu() && (GET_OMAP_REVISION() < (rev))) ? 1 : 0) + +#define cpu_rev_le(cpu,rev) \ + ((cpu_is_omap ##cpu() && (GET_OMAP_REVISION() <= (rev))) ? 1 : 0) + +#define cpu_rev_eq(cpu,rev) \ + ((cpu_is_omap ##cpu() && (GET_OMAP_REVISION() == (rev))) ? 1 : 0) + +#define cpu_rev_ge(cpu,rev) \ + ((cpu_is_omap ##cpu() && (GET_OMAP_REVISION() >= (rev))) ? 1 : 0) + +#define cpu_rev_gt(cpu,rev) \ + ((cpu_is_omap ##cpu() && (GET_OMAP_REVISION() > (rev))) ? 1 : 0) + #endif From patchwork Sun May 16 15:46:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99978 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkdbv025348 for ; Sun, 16 May 2010 15:46:39 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753862Ab0EPPqi (ORCPT ); Sun, 16 May 2010 11:46:38 -0400 Received: from fg-out-1718.google.com ([72.14.220.159]:5081 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753628Ab0EPPqh (ORCPT ); Sun, 16 May 2010 11:46:37 -0400 Received: by fg-out-1718.google.com with SMTP id d23so2359940fga.1 for ; Sun, 16 May 2010 08:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=86I+iU/r/OJhs3YNKD3o1KGOu+SE8fQgS0knzU8veoQ=; b=si04w+FZ0vasDTRNgaZhS8yqZxosWa3IWuoxTJ/ZMEf+Wt2qSgIjfmHvS7++hCMBFF QC9eOBg+DV9fXzRlNJmEW61SmJ7UjgFPjt44JX3nhsVZKEP7+xeeZbajO/SFe9Ki+mvn ssiGuq3UCi48sAYryHUzsUP02PlQQoUscvYeo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Zg6fVS/CQ6p8ExV7pyFoVHlwHi9EiHs42u+3O3fQKXiF8qVX+oBIhoub2AI+dNIc// IbLq7f8MlacMai2u/fMrFpxRPdWH2wSZwjaXcgz2hxxsWxEJOJhRteuKZMvVQUKpmQUh yeo66JxEopUsG/WEsH28gjh6Sa+YjMF2f/kz8= Received: by 10.87.9.11 with SMTP id m11mr6723951fgi.73.1274024796701; Sun, 16 May 2010 08:46:36 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id 12sm3766365fgg.14.2010.05.16.08.46.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:36 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 14/14] dspbridge: deh: update copyright notice Date: Sun, 16 May 2010 18:46:05 +0300 Message-Id: <1274024765-21076-15-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:39 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/dspdeh.h b/arch/arm/plat-omap/include/dspbridge/dspdeh.h index e5e83b4..28734f2 100644 --- a/arch/arm/plat-omap/include/dspbridge/dspdeh.h +++ b/arch/arm/plat-omap/include/dspbridge/dspdeh.h @@ -10,6 +10,7 @@ * Function comment headers reside with the function typedefs in dspdefs.h. * * Copyright (C) 2005-2006 Texas Instruments, Inc. + * Copyright (C) 2010 Felipe Contreras * * This package is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/drivers/dsp/bridge/core/_deh.h b/drivers/dsp/bridge/core/_deh.h index 9fb727b..16723cd 100644 --- a/drivers/dsp/bridge/core/_deh.h +++ b/drivers/dsp/bridge/core/_deh.h @@ -6,6 +6,7 @@ * Private header for DEH module. * * Copyright (C) 2005-2006 Texas Instruments, Inc. + * Copyright (C) 2010 Felipe Contreras * * This package is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 6ff73a2..315672b 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -6,6 +6,7 @@ * Implements upper edge DSP exception handling (DEH) functions. * * Copyright (C) 2005-2006 Texas Instruments, Inc. + * Copyright (C) 2010 Felipe Contreras * * This package is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as From patchwork Fri Jul 23 23:22:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Sin X-Patchwork-Id: 114025 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NN74MW030334 for ; Fri, 23 Jul 2010 23:07:07 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759077Ab0GWXHF (ORCPT ); Fri, 23 Jul 2010 19:07:05 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:43178 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757523Ab0GWXHE (ORCPT ); Fri, 23 Jul 2010 19:07:04 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6NN6vZC004909 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 23 Jul 2010 18:06:57 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6NN6s4c017702; Fri, 23 Jul 2010 18:06:54 -0500 (CDT) Received: from localhost.localdomain (neo.am.dhcp.ti.com [128.247.75.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBDHgTP19231; Mon, 13 Dec 1915 12:42:29 -0500 (CDT) From: David Sin To: , , Tony Lindgren , Russell King Cc: Hari Kanigeri , Ohad Ben-Cohen , Vaibhav Hiremath , Santosh Shilimkar , Lajos Molnar , David Sin Subject: [RFC 8/8] TILER-DMM: Linking TILER driver into the Linux kernel build Date: Fri, 23 Jul 2010 18:22:28 -0500 Message-Id: <1279927348-21750-9-git-send-email-davidsin@ti.com> X-Mailer: git-send-email 1.6.6.2 In-Reply-To: <1279927348-21750-8-git-send-email-davidsin@ti.com> References: <1279927348-21750-1-git-send-email-davidsin@ti.com> <1279927348-21750-2-git-send-email-davidsin@ti.com> <1279927348-21750-3-git-send-email-davidsin@ti.com> <1279927348-21750-4-git-send-email-davidsin@ti.com> <1279927348-21750-5-git-send-email-davidsin@ti.com> <1279927348-21750-6-git-send-email-davidsin@ti.com> <1279927348-21750-7-git-send-email-davidsin@ti.com> <1279927348-21750-8-git-send-email-davidsin@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 23:07:07 +0000 (UTC) diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig index a28541b..96ebc1d 100644 --- a/drivers/media/Kconfig +++ b/drivers/media/Kconfig @@ -98,6 +98,12 @@ config VIDEO_MEDIA comment "Multimedia drivers" +# +# TI TILER driver support +# + +source "drivers/media/video/tiler/Kconfig" + source "drivers/media/common/Kconfig" source "drivers/media/IR/Kconfig" diff --git a/drivers/media/Makefile b/drivers/media/Makefile index 499b081..922d71c 100644 --- a/drivers/media/Makefile +++ b/drivers/media/Makefile @@ -4,5 +4,7 @@ obj-y += common/ IR/ video/ +obj-${CONFIG_TI_TILER} += video/tiler/ + obj-$(CONFIG_VIDEO_DEV) += radio/ obj-$(CONFIG_DVB_CORE) += dvb/ From patchwork Thu Jul 1 10:42:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 109052 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o61AgS6f024349 for ; Thu, 1 Jul 2010 10:42:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755270Ab0GAKm1 (ORCPT ); Thu, 1 Jul 2010 06:42:27 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:60346 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755183Ab0GAKmZ (ORCPT ); Thu, 1 Jul 2010 06:42:25 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o61AgImC004516 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 1 Jul 2010 05:42:20 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o61AgFDC001253; Thu, 1 Jul 2010 16:12:17 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: linux-mtd@lists.infradead.org, Sukumar Ghorai , Vimal Singh Subject: [PATCH v2 1/4] omap3: nand: prefetch in irq mode support Date: Thu, 1 Jul 2010 16:12:12 +0530 Message-Id: <1277980935-24070-2-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1277980935-24070-1-git-send-email-s-ghorai@ti.com> References: <1277980935-24070-1-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Jul 2010 10:42:29 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index ac834aa..c6a07dd 100755 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -133,6 +133,7 @@ static struct omap_nand_platform_data board_nand_data = { .nand_setup = NULL, .gpmc_t = &nand_timings, .dma_channel = -1, /* disable DMA in OMAP NAND driver */ + .gpmc_irq = GPMC_IRQ_NUMBER, .dev_ready = NULL, .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ }; diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index b8077c6..4e12a9f 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -465,6 +465,13 @@ int gpmc_hwcontrol(int cs, int cmd, int write, int wval, int *rval) *rval = gpmc_read_reg(GPMC_IRQSTATUS); break; + case GPMC_ENABLE_IRQ: + if (write) + gpmc_write_reg(GPMC_IRQENABLE, wval); + else + *rval = gpmc_read_reg(GPMC_IRQENABLE); + break; + case GPMC_PREFETCH_FIFO_CNT: regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); *rval = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); diff --git a/arch/arm/mach-omap2/include/mach/board-flash.h b/arch/arm/mach-omap2/include/mach/board-flash.h index b2242ae..37567a7 100644 --- a/arch/arm/mach-omap2/include/mach/board-flash.h +++ b/arch/arm/mach-omap2/include/mach/board-flash.h @@ -19,6 +19,9 @@ #define PDC_ONENAND 3 #define DBG_MPDB 4 +/* Interrupt number to the MPU Subsystem for GPMC */ +#define GPMC_IRQ_NUMBER 20 + struct flash_partitions { struct mtd_partition *parts; int nr_parts; diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index ccbc530..4bdd851 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -37,6 +37,7 @@ #define GPMC_PREFETCH_FIFO_CNT 0x00000009 /* bytes available in FIFO for r/w */ #define GPMC_PREFETCH_COUNT 0x0000000A /* remaining bytes to be read/write*/ #define GPMC_GET_SET_IRQ_STATUS 0x0000000B +#define GPMC_ENABLE_IRQ 0x0000000C /* ECC commands */ #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ @@ -75,6 +76,8 @@ #define WR_RD_PIN_MONITORING 0x00600000 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) +#define GPMC_IRQ_FIFOEVENTENABLE 0x01 +#define GPMC_IRQ_COUNT_EVENT 0x02 /* * Note that all values in this struct are in nanoseconds, while diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 6562cd0..5e69463 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -20,6 +20,7 @@ struct omap_nand_platform_data { int (*nand_setup)(void); int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; + int gpmc_irq; unsigned long phys_base; int devsize; }; diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 98a04b3..d0e934b 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -111,6 +111,9 @@ config MTD_NAND_OMAP_PREFETCH help The NAND device can be accessed for Read/Write using GPMC PREFETCH engine to improve the performance. + GPMC PREFETCH can be configured eigther in MPU interrupt mode or in DMA + interrupt mode. If not selected any of them prefetch will be used in + polling mode. config MTD_NAND_OMAP_PREFETCH_DMA depends on MTD_NAND_OMAP_PREFETCH @@ -119,7 +122,16 @@ config MTD_NAND_OMAP_PREFETCH_DMA help The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode or in DMA interrupt mode. - Say y for DMA mode or MPU mode will be used + Say y for DMA mode + +config MTD_NAND_OMAP_PREFETCH_IRQ + depends on MTD_NAND_OMAP_PREFETCH && !MTD_NAND_OMAP_PREFETCH_DMA + bool "IRQ mode" + default n + help + The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode + or in DMA interrupt mode. + Say y for IRQ mode config MTD_NAND_IDS tristate diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index f9fa3cb..2ce2410 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -105,17 +106,27 @@ module_param(use_prefetch, bool, 0); MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH"); #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA +const int use_interrupt; static int use_dma = 1; /* "modprobe ... use_dma=0" etc */ module_param(use_dma, bool, 0); -MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); +MODULE_PARM_DESC(use_dma, "enable/disable use of DMA mode"); +#elif defined(CONFIG_MTD_NAND_OMAP_PREFETCH_IRQ) +const int use_dma; +static int use_interrupt = 1; + +/* "modprobe ... use_dma=0" etc */ +module_param(use_interrupt, bool, 0); +MODULE_PARM_DESC(use_interrupt, "enable/disable use of IRQ mode"); #else const int use_dma; +const int use_interrupt; #endif #else const int use_prefetch; const int use_dma; +const int use_interrupt; #endif struct omap_nand_info { @@ -130,6 +141,13 @@ struct omap_nand_info { unsigned long phys_base; struct completion comp; int dma_ch; + int gpmc_irq; + enum { + NAND_IO_READ = 0, /* read */ + NAND_IO_WRITE, /* write */ + } iomode; + u_char *buf; + int buf_len; }; /** @@ -476,6 +494,155 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd, omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); } +/* + * omap_nand_irq - GMPC irq handler + * @this_irq: gpmc irq number + * @dev: omap_nand_info structure pointer is passed here + */ +static irqreturn_t omap_nand_irq(int this_irq, void *dev) +{ + struct omap_nand_info *info = (struct omap_nand_info *) dev; + u32 irq_enb, bytes; + u32 irq_stat; + + gpmc_hwcontrol(info->gpmc_cs, GPMC_GET_SET_IRQ_STATUS, 0, 0, &irq_stat); + gpmc_hwcontrol(info->gpmc_cs, GPMC_PREFETCH_FIFO_CNT, 0, 0, &bytes); + bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ + if (info->iomode == NAND_IO_WRITE) { /* checks for write operaiton */ + if (irq_stat & 0x2) + goto done; + + if (info->buf_len & (info->buf_len < bytes)) + bytes = info->buf_len; + else if (!info->buf_len) + bytes = 0; + iowrite32_rep(info->nand.IO_ADDR_W, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + info->buf_len -= bytes; + + } else { + ioread32_rep(info->nand.IO_ADDR_R, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + + if (irq_stat & 0x2) + goto done; + } + gpmc_hwcontrol(info->gpmc_cs, GPMC_GET_SET_IRQ_STATUS, 1, irq_stat, 0); + gpmc_hwcontrol(info->gpmc_cs, GPMC_GET_SET_IRQ_STATUS, 0, 0, &irq_stat); + + return IRQ_HANDLED; + +done: + complete(&info->comp); + /* disable irq */ + gpmc_hwcontrol(info->gpmc_cs, GPMC_ENABLE_IRQ, 0, 0, &irq_enb); + irq_enb &= ~(GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT); + gpmc_hwcontrol(info->gpmc_cs, GPMC_ENABLE_IRQ, 1, irq_enb, 0); + + /* clear status */ + gpmc_hwcontrol(info->gpmc_cs, GPMC_GET_SET_IRQ_STATUS, 1, irq_stat, 0); + gpmc_hwcontrol(info->gpmc_cs, GPMC_GET_SET_IRQ_STATUS, 0, 0, &irq_stat); + + return IRQ_HANDLED; +} + +/* + * omap_read_buf_irq_pref - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + u32 irq_enb; + int ret = 0; + + if (len <= mtd->oobsize) { + omap_read_buf_pref(mtd, buf, len); + return; + } + info->iomode = NAND_IO_READ; + info->buf = buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + if (ret) + /* PFPW engine is busy, use cpu copy methode */ + goto out_copy; + + info->buf_len = len; + gpmc_hwcontrol(info->gpmc_cs, GPMC_ENABLE_IRQ, 0, 0, &irq_enb); + irq_enb |= (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT); + gpmc_hwcontrol(info->gpmc_cs, GPMC_ENABLE_IRQ, 1, irq_enb, 0); + + /* waiting for read to complete */ + wait_for_completion(&info->comp); + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_read_buf16(mtd, buf, len); + else + omap_read_buf8(mtd, buf, len); +} + +/* + * omap_write_buf_irq_pref - write buffer to NAND controller + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void omap_write_buf_irq_pref(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + u32 irq_enb; + int ret = 0; + if (len <= mtd->oobsize) { + omap_write_buf_pref(mtd, buf, len); + return; + } + + info->iomode = NAND_IO_WRITE; + info->buf = (u_char *) buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + if (ret) + /* PFPW engine is busy, use cpu copy methode */ + goto out_copy; + + info->buf_len = len; + gpmc_hwcontrol(info->gpmc_cs, GPMC_ENABLE_IRQ, 0, 0, &irq_enb); + irq_enb |= (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT); + gpmc_hwcontrol(info->gpmc_cs, GPMC_ENABLE_IRQ, 1, irq_enb, 0); + + /* waiting for write to complete */ + wait_for_completion(&info->comp); + /* wait for data to flushed-out before reset the prefetch */ + do { + gpmc_hwcontrol(info->gpmc_cs, GPMC_PREFETCH_COUNT, 0, 0, &ret); + } while (ret); + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_write_buf16(mtd, buf, len); + else + omap_write_buf8(mtd, buf, len); +} + /** * omap_verify_buf - Verify chip data against buffer * @mtd: MTD device structure @@ -811,6 +978,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->gpmc_cs = pdata->cs; info->phys_base = pdata->phys_base; + info->gpmc_irq = pdata->gpmc_irq; info->mtd.priv = &info->nand; info->mtd.name = dev_name(&pdev->dev); @@ -874,7 +1042,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.read_buf = omap_read_buf_dma_pref; info->nand.write_buf = omap_write_buf_dma_pref; } + } else if (use_interrupt) { + err = request_irq(info->gpmc_irq, omap_nand_irq, + IRQF_SHARED, info->mtd.name, info); + if (err) { + printk(KERN_INFO"failure requesting irq %i." + " Prefetch will work in mpu" + " poling mode.\n", + info->gpmc_irq); + } else { + info->nand.read_buf = omap_read_buf_irq_pref; + info->nand.write_buf = omap_write_buf_irq_pref; + } } + } else { if (info->nand.options & NAND_BUSWIDTH_16) { info->nand.read_buf = omap_read_buf16; @@ -964,11 +1145,19 @@ static int __init omap_nand_init(void) /* This check is required if driver is being * loaded run time as a module */ - if ((1 == use_dma) && (0 == use_prefetch)) { - printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 " - "without use_prefetch'. Prefetch will not be" - " used in either mode (mpu or dma)\n"); + + if ((0 == use_prefetch) && (1 == (use_dma | use_interrupt))) { + printk(KERN_INFO "Wrong parameters: Neither 'dma' nor 'irq' " + "can used without 'use_prefetch' selected.\n"); + printk(KERN_INFO "Prefetch will not be used in any mode: " + "poll, mpu or dma\n"); + } else if ((1 == use_prefetch) && (1 == (use_interrupt & use_dma))) { + printk(KERN_INFO "Wrong parameters: Both DMA and IRQ" + " modes can not be used together.\n"); + printk(KERN_INFO "It has to be selected at compile " + "time and same will be used.\n"); } + return platform_driver_register(&omap_nand_driver); } From patchwork Wed Aug 4 22:43:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 117170 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74MiMQo015141 for ; Wed, 4 Aug 2010 22:44:22 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758086Ab0HDWoF (ORCPT ); Wed, 4 Aug 2010 18:44:05 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:60624 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757567Ab0HDWoD (ORCPT ); Wed, 4 Aug 2010 18:44:03 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o74MhxrV017632 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 4 Aug 2010 17:43:59 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o74MhsBQ001532; Wed, 4 Aug 2010 17:43:54 -0500 (CDT) From: Benoit Cousson To: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, paul@pwsan.com Cc: rnayak@ti.com, santosh.shilimkar@ti.com, Benoit Cousson Subject: [RFC PATCH] OMAP: hwmod: Add debugfs support for omap_hwmod Date: Thu, 5 Aug 2010 00:43:53 +0200 Message-Id: <1280961833-25002-1-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.6.1.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 22:44:22 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 63b2d88..2f2b25b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -17,7 +17,9 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) -obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o +obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o +obj-$(CONFIG_DEBUG_FS) += omap_hwmod_debug.o + # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o diff --git a/arch/arm/mach-omap2/omap_hwmod_debug.c b/arch/arm/mach-omap2/omap_hwmod_debug.c new file mode 100644 index 0000000..3f48977 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_debug.c @@ -0,0 +1,387 @@ +/* + * omap_hwmod debugfs implementation + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Benoit Cousson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Expose a debufs interface in order to check and modify hwmod state + * The current directory structure is: + * + * hwmods + * +-hwmod_mpu + * +-hwmod_dsp + * . + * . + * +-hwmod_xxx : hwmod node + * +-state : internal state (RO) + * +-summary : global view of hwmod definition + * +-resets : reset lines + * +-rst1 : reset state / control (RW) + * +-rst2 : + * + * To do: + * - Add irq / dma dump + * - Add clock dump + */ +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +/* + * DEBUGFS helper macros + * + * This code is already used in several omap drivers, so eventually it will be + * good to move that to plat-omap and share the same code. + */ + +#define DEFINE_DEBUGFS_SHOW(__fops, __show) \ +static int __fops ## _open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, __show, inode->i_private); \ +} \ +static const struct file_operations __fops = { \ + .owner = THIS_MODULE, \ + .open = __fops ## _open, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ +}; + +/* + * Aggregate reset information in a specific structure, because the reset + * node does not contain any link to the parent hwmod structure + */ +struct reset_info { + struct omap_hwmod *oh; + const char *name; + u8 rst_shift; +}; + +/* internal hwmod states */ +static const char* states[_HWMOD_STATE_LAST + 1] = { + [_HWMOD_STATE_UNKNOWN] = "unknown", + [_HWMOD_STATE_REGISTERED] = "registered", + [_HWMOD_STATE_CLKS_INITED] = "clks_inited", + [_HWMOD_STATE_INITIALIZED] = "initialized", + [_HWMOD_STATE_ENABLED] = "enabled", + [_HWMOD_STATE_IDLE] = "idle", + [_HWMOD_STATE_DISABLED] = "disabled", +}; + +const char * _state_str(int state) +{ + if (state < 0 || state > _HWMOD_STATE_LAST) + return "invalid_state"; + + return states[state]; +} + +static int _set_state(void *data, u64 val) +{ + *(u8 *)data = val; + return 0; +} +static int _get_state(void *data, u64 *val) +{ + *val = *(u8 *)data; + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(state_fops, _get_state, _set_state, "%llu\n"); + +static int default_open(struct inode *inode, struct file *file) +{ + if (inode->i_private) + file->private_data = inode->i_private; + + return 0; +} + +#define MAX_BUFFER_SIZE 16 + +static ssize_t read_hwmod_state(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + char buf[MAX_BUFFER_SIZE]; + struct omap_hwmod *oh = file->private_data; + const char *msg = _state_str(oh->_state); + + int len = snprintf(buf, MAX_BUFFER_SIZE, "%s\n", msg); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t write_hwmod_state(struct file *file, const char __user *user_buf, + size_t count, loff_t *ppos) +{ + char buf[32]; + int buf_size; + char *p; + int len; + struct omap_hwmod *oh = file->private_data; + + if (!oh || !oh->name) + return -EINVAL; + + buf_size = min(count, (sizeof(buf)-1)); + if (copy_from_user(buf, user_buf, buf_size)) + return -EFAULT; + + p = memchr(buf, '\n', buf_size); + len = p ? p - buf : buf_size; + buf[len] = '\0'; + + if (!strncmp(buf, "enable", len)) + omap_hwmod_enable(oh); + else if (!strncmp(buf, "idle", len)) + omap_hwmod_idle(oh); + else if (!strncmp(buf, "disable", len)) + omap_hwmod_shutdown(oh); + else if (!strncmp(buf, "reset", len)) + omap_hwmod_reset(oh); + else + pr_warning("write_hwmod_state: invalid state: %s\n", buf); + + return count; +} + +static const struct file_operations hwmod_state_fops = { + .read = read_hwmod_state, + .write = write_hwmod_state, + .open = default_open, +}; + +/** + * _reset_get - helper function for debugfs read to reset line + * @data: pointer to data initialized during debugfs_create_file. In this + * case this is a pointer to struct reset_info + * @val: pointer to the value that will be read and propagate to the debufs + * interface + * + * Returns: 0 if the reset is deasserted or asserted (0 or 1), any other states + * are invalid, so return -EINVAL in that case. + */ +static int _reset_get(void *data, u64 *val) +{ + struct reset_info *info = data; + int state; + + state = omap_hwmod_hardreset_state(info->oh, info->name); + + pr_debug("_reset_get: %s:%d %d\n", info->name, info->rst_shift, state); + + *val = (u64)state; + + if (state >= 0) + return 0; + + return *val; +} + +/** + * _reset_set - helper function for debugfs write to reset line + * @data: pointer to data initialized during debugfs_create_file. In this + * case this is a pointer to struct reset_info + * @val: value that should written from the debufs interface + * + * Assert or deassert the reset line depending of the value written + * on the debugfs "rst" file entry + * Returns -EINVAL if val is not 0 or 1. + */ +static int _reset_set(void *data, u64 val) +{ + struct reset_info *info = data; + int ret = -EINVAL; + + pr_debug("_reset_set: %s[%d]: %llu\n", info->name, info->rst_shift, + val); + + if (val == 1) + ret = omap_hwmod_hardreset_assert(info->oh, info->name); + else if (val == 0) + ret = omap_hwmod_hardreset_deassert(info->oh, info->name); + + return ret; +} + +DEFINE_SIMPLE_ATTRIBUTE(reset_fops, _reset_get, _reset_set, "%llu\n"); + + + +static struct omap_hwmod_addr_space* _print_addresses(struct seq_file *s, + struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os = NULL; + struct omap_hwmod_addr_space *mem; + int j; + + if (!oh || oh->slaves_cnt == 0) { + seq_printf(s, " address: N/A\n"); + return NULL; + } + + for (j = 0; j < oh->slaves_cnt; j++) { + int i; + + os = oh->slaves[j]; + if (!os->addr) + continue; + + if (os->user & OCP_USER_MPU) { + for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) + seq_printf(s, " address: 0x%08x-0x%08x (mpu)\n", + mem->pa_start, mem->pa_end); + } else { + for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) + seq_printf(s, " address: 0x%08x-0x%08x\n", + mem->pa_start, mem->pa_end); + } + } + + return NULL; +} + +static int show_hwmod_summary(struct omap_hwmod *oh, void* param) +{ + struct seq_file *s = param; + int i; + + if (!oh || !oh->name) + return -EINVAL; + + seq_printf(s, "%s\n", oh->name); + seq_printf(s, " state: %s:%d\n", _state_str(oh->_state), + oh->_state); + seq_printf(s, " class: %s\n", oh->class->name); + seq_printf(s, " flags: 0x%04x\n", oh->flags); + + _print_addresses(s, oh); + + if (!IS_ERR_OR_NULL(oh->_clk)) + seq_printf(s, " clock: %s\n", oh->_clk->name); + + if (oh->rst_lines_cnt > 0) + seq_printf(s, " resets(%d):\n", oh->rst_lines_cnt); + for (i = 0; i < oh->rst_lines_cnt; i++) { + int state = omap_hwmod_hardreset_state(oh, + oh->rst_lines[i].name); + seq_printf(s, " %s:%d\n", oh->rst_lines[i].name, + state); + } + + if (oh->mpu_irqs_cnt > 0) + seq_printf(s, " irqs(%d):\n", oh->mpu_irqs_cnt); + for (i = 0; i < oh->mpu_irqs_cnt; i++) + seq_printf(s, " %s:%d\n", oh->mpu_irqs[i].name, + oh->mpu_irqs[i].irq); + + if (oh->sdma_reqs_cnt > 0) + seq_printf(s, " dmas(%d):\n", oh->sdma_reqs_cnt); + for (i = 0; i < oh->sdma_reqs_cnt; i++) + seq_printf(s, " %s:%d\n", oh->sdma_reqs[i].name, + oh->sdma_reqs[i].dma_req); + + return 0; +} + +static int show_hwmod(struct seq_file *s, void *unused) +{ + struct omap_hwmod *oh = s->private; + + show_hwmod_summary(oh, s); + + return 0; +} +DEFINE_DEBUGFS_SHOW(_hwmod_fops, show_hwmod); + +/** + * create_debugfs_entry - create a debugfs entry per omap_hwmod + * @oh: struct omap_hwmod * + * @parent: reference to the parent directory dentry needed for the creation + * of the files inside the debugfs directory + * + * Create a directory entry for each hwmod. + * Each directory will contain at least one state file and potentially + * some files that will represent the HW reset lines of that IP. + */ +static int create_debugfs_entry(struct omap_hwmod *oh, void* parent) +{ + struct dentry *d, *fd; + int i; + + if (!oh || !oh->name) + return -EINVAL; + + pr_debug("creating debugfs entry: %s[%p]\n", oh->name, oh); + + d = debugfs_create_dir(oh->name, parent); + if (IS_ERR(d)) + return PTR_ERR(d); + + fd = debugfs_create_file("summary", S_IRUGO, d, oh, &_hwmod_fops); + if (IS_ERR(fd)) + return PTR_ERR(fd); + + fd = debugfs_create_file("state", S_IRUGO|S_IWUSR, d, oh, + &hwmod_state_fops); + if (IS_ERR(fd)) + return PTR_ERR(fd); + + if (oh->rst_lines_cnt > 0) { + struct dentry *drst = debugfs_create_dir("resets", d); + if (IS_ERR(drst)) + return PTR_ERR(drst); + + /* Create one directory entry per reset line */ + for (i = 0; i < oh->rst_lines_cnt; i++) { + struct reset_info *info; + const char *name = oh->rst_lines[i].name; + + /* XXX need to find a way to free that memory */ + info = kmalloc(sizeof(struct reset_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->oh = oh; + info->name = oh->rst_lines[i].name; + info->rst_shift = oh->rst_lines[i].rst_shift; + + debugfs_create_file(name, S_IRUGO|S_IWUSR, drst, info, + &reset_fops); + } + } + + return 0; +} + +/* hwmod_debugfs_init - Initialize the debugfs directory tree for hwmods */ +static int __init hwmod_debugfs_init(void) +{ + struct dentry *d; + + pr_warning("omap_hwmod: Initialize debugfs support"); + + d = debugfs_create_dir("hwmods", NULL); + if (IS_ERR(d)) + return PTR_ERR(d); + + omap_hwmod_for_each(create_debugfs_entry, d); + + return 0; +} +late_initcall(hwmod_debugfs_init); diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 5941183..4a0b723 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -394,7 +394,13 @@ struct omap_hwmod_omap4_prcm { * INITIALIZED: reset (optionally), initialized, enabled, disabled * (optionally) * - * + * _HWMOD_STATE_UNKNOWN + * _HWMOD_STATE_REGISTERED + * _HWMOD_STATE_CLKS_INITED + * _HWMOD_STATE_INITIALIZED + * _HWMOD_STATE_ENABLED + * _HWMOD_STATE_IDLE + * _HWMOD_STATE_DISABLED */ #define _HWMOD_STATE_UNKNOWN 0 #define _HWMOD_STATE_REGISTERED 1 @@ -403,6 +409,7 @@ struct omap_hwmod_omap4_prcm { #define _HWMOD_STATE_ENABLED 4 #define _HWMOD_STATE_IDLE 5 #define _HWMOD_STATE_DISABLED 6 +#define _HWMOD_STATE_LAST _HWMOD_STATE_DISABLED /** * struct omap_hwmod_class - the type of an IP block From patchwork Wed Jul 7 09:44:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110593 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679iHIs027815 for ; Wed, 7 Jul 2010 09:44:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754544Ab0GGJoQ (ORCPT ); Wed, 7 Jul 2010 05:44:16 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:58842 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754518Ab0GGJoP (ORCPT ); Wed, 7 Jul 2010 05:44:15 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRAs-000IEU-Lp; Wed, 07 Jul 2010 09:44:14 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1/KcwXIfD18JYd4wnuX56Pq Subject: [PATCH 04/13] omap3: pandora: add NAND and wifi support To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: linux-omap@vger.kernel.org, Grazvydas Ignotas Date: Wed, 07 Jul 2010 12:44:11 +0300 Message-ID: <20100707094411.2562.54091.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:18 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 7a12729..a58bdef 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -25,6 +25,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -41,13 +44,50 @@ #include #include #include +#include #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" +#define PANDORA_WIFI_IRQ_GPIO 21 +#define PANDORA_WIFI_NRESET_GPIO 23 #define OMAP3_PANDORA_TS_GPIO 94 +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition omap3pandora_nand_partitions[] = { + { + .name = "xloader", + .offset = 0, + .size = 4 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = 15 * NAND_BLOCK_SIZE, + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = 1 * NAND_BLOCK_SIZE, + }, { + .name = "boot", + .offset = MTDPART_OFS_APPEND, + .size = 80 * NAND_BLOCK_SIZE, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_nand_platform_data pandora_nand_data = { + .cs = 0, + .devsize = 1, /* '0' for 8-bit, '1' for 16-bit device */ + .parts = omap3pandora_nand_partitions, + .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions), +}; + static struct gpio_led pandora_gpio_leds[] = { { .name = "pandora::sd1", @@ -246,12 +286,33 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { static int omap3pandora_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { + int ret, gpio_32khz; + /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ omap3pandora_mmc[0].gpio_cd = gpio + 0; omap3pandora_mmc[1].gpio_cd = gpio + 1; omap2_hsmmc_init(omap3pandora_mmc); + /* gpio + 13 drives 32kHz buffer for wifi module */ + gpio_32khz = gpio + 13; + ret = gpio_request(gpio_32khz, "wifi 32kHz"); + if (ret < 0) { + pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret); + goto fail; + } + + ret = gpio_direction_output(gpio_32khz, 1); + if (ret < 0) { + pr_err("Cannot set GPIO line %d, ret=%d\n", gpio_32khz, ret); + goto fail_direction; + } + return 0; + +fail_direction: + gpio_free(gpio_32khz); +fail: + return -ENODEV; } static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { @@ -530,10 +591,67 @@ static void __init omap3pandora_init_irq(void) omap_gpio_init(); } +static void pandora_wl1251_set_power(bool enable) +{ + /* + * Keep power always on until wl1251_sdio driver learns to re-init + * the chip after powering it down and back up. + */ +} + +static struct wl12xx_platform_data pandora_wl1251_pdata = { + .set_power = pandora_wl1251_set_power, + .use_eeprom = true, +}; + +static struct platform_device pandora_wl1251_data = { + .name = "wl1251_data", + .id = -1, + .dev = { + .platform_data = &pandora_wl1251_pdata, + }, +}; + +static void pandora_wl1251_init(void) +{ + int ret; + + ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq"); + if (ret < 0) + goto fail; + + ret = gpio_direction_input(PANDORA_WIFI_IRQ_GPIO); + if (ret < 0) + goto fail_irq; + + pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO); + if (pandora_wl1251_pdata.irq < 0) + goto fail_irq; + + ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset"); + if (ret < 0) + goto fail_irq; + + /* start powered so that it probes with MMC subsystem */ + ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1); + if (ret < 0) + goto fail_nreset; + + return; + +fail_nreset: + gpio_free(PANDORA_WIFI_NRESET_GPIO); +fail_irq: + gpio_free(PANDORA_WIFI_IRQ_GPIO); +fail: + printk(KERN_ERR "wl1251 board initialisation failed\n"); +} + static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_leds_gpio, &pandora_keys_gpio, &pandora_dss_device, + &pandora_wl1251_data, }; static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -566,6 +684,7 @@ static void __init omap3pandora_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3pandora_i2c_init(); + pandora_wl1251_init(); platform_add_devices(omap3pandora_devices, ARRAY_SIZE(omap3pandora_devices)); omap_serial_init(); @@ -574,6 +693,7 @@ static void __init omap3pandora_init(void) omap3pandora_ads7846_init(); usb_ehci_init(&ehci_pdata); usb_musb_init(&musb_board_data); + gpmc_nand_init(&pandora_nand_data); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); From patchwork Sun May 16 15:46:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99976 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkZgf025331 for ; Sun, 16 May 2010 15:46:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753758Ab0EPPqe (ORCPT ); Sun, 16 May 2010 11:46:34 -0400 Received: from fg-out-1718.google.com ([72.14.220.159]:5081 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753628Ab0EPPqd (ORCPT ); Sun, 16 May 2010 11:46:33 -0400 Received: by fg-out-1718.google.com with SMTP id d23so2359940fga.1 for ; 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Sun, 16 May 2010 08:46:32 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 12/14] dspbridge: move mmufault to deh Date: Sun, 16 May 2010 18:46:03 +0300 Message-Id: <1274024765-21076-13-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:35 +0000 (UTC) diff --git a/drivers/dsp/bridge/Makefile b/drivers/dsp/bridge/Makefile index 4c2f923..39624d4 100644 --- a/drivers/dsp/bridge/Makefile +++ b/drivers/dsp/bridge/Makefile @@ -5,7 +5,7 @@ libservices = services/sync.o services/cfg.o \ services/ntfy.o services/services.o libcore = core/chnl_sm.o core/msg_sm.o core/io_sm.o core/tiomap3430.o \ core/tiomap3430_pwr.o core/tiomap_io.o \ - core/mmu_fault.o core/ue_deh.o core/wdt.o core/dsp-clock.o + core/ue_deh.o core/wdt.o core/dsp-clock.o libpmgr = pmgr/chnl.o pmgr/io.o pmgr/msg.o pmgr/cod.o pmgr/dev.o pmgr/dspapi.o \ pmgr/dmm.o pmgr/cmm.o pmgr/dbll.o librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \ diff --git a/drivers/dsp/bridge/core/mmu_fault.c b/drivers/dsp/bridge/core/mmu_fault.c deleted file mode 100644 index 49034cf..0000000 --- a/drivers/dsp/bridge/core/mmu_fault.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * mmu_fault.c - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Implements DSP MMU fault handling functions. - * - * Copyright (C) 2005-2006 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -/* ----------------------------------- DSP/BIOS Bridge */ -#include -#include -#include - -/* ----------------------------------- Trace & Debug */ -#include -#include - -/* ----------------------------------- OS Adaptation Layer */ -#include - -/* ----------------------------------- Link Driver */ -#include - -/* ------------------------------------ Hardware Abstraction Layer */ -#include -#include - -/* ----------------------------------- This */ -#include "_deh.h" -#include -#include "_tiomap_mmu.h" -#include "_tiomap.h" -#include "mmu_fault.h" - -/* - * ======== mmu_fault_dpc ======== - * Deferred procedure call to handle DSP MMU fault. - */ -void mmu_fault_dpc(IN unsigned long pRefData) -{ - struct deh_mgr *hdeh_mgr = (struct deh_mgr *)pRefData; - - if (!hdeh_mgr) - return; - - bridge_deh_notify(hdeh_mgr, DSP_MMUFAULT, 0L); -} - -/* - * ======== mmu_fault_isr ======== - * ISR to be triggered by a DSP MMU fault interrupt. - */ -irqreturn_t mmu_fault_isr(int irq, IN void *pRefData) -{ - struct deh_mgr *deh_mgr_obj = pRefData; - struct cfg_hostres *resources; - u32 dmmu_event_mask; - - if (!deh_mgr_obj) - return IRQ_HANDLED; - - resources = deh_mgr_obj->hbridge_context->resources; - if (!resources) { - dev_dbg(bridge, "%s: Failed to get Host Resources\n", - __func__); - return IRQ_HANDLED; - } - - hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); - if (dmmu_event_mask == HW_MMU_TRANSLATION_FAULT) { - hw_mmu_fault_addr_read(resources->dw_dmmu_base, &deh_mgr_obj->fault_addr); - dev_info(bridge, "%s: status=0x%x, fault_addr=0x%x\n", __func__, - dmmu_event_mask, deh_mgr_obj->fault_addr); - /* - * Schedule a DPC directly. In the future, it may be - * necessary to check if DSP MMU fault is intended for - * Bridge. - */ - tasklet_schedule(&deh_mgr_obj->dpc_tasklet); - - /* Disable the MMU events, else once we clear it will - * start to raise INTs again */ - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_TRANSLATION_FAULT); - } else { - hw_mmu_event_disable(resources->dw_dmmu_base, - HW_MMU_ALL_INTERRUPTS); - } - return IRQ_HANDLED; -} diff --git a/drivers/dsp/bridge/core/mmu_fault.h b/drivers/dsp/bridge/core/mmu_fault.h deleted file mode 100644 index 537e6e7..0000000 --- a/drivers/dsp/bridge/core/mmu_fault.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * mmu_fault.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Defines DSP MMU fault handling functions. - * - * Copyright (C) 2005-2006 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef MMU_FAULT_ -#define MMU_FAULT_ - -/* - * ======== mmu_fault_dpc ======== - * Deferred procedure call to handle DSP MMU fault. - */ -void mmu_fault_dpc(IN unsigned long pRefData); - -/* - * ======== mmu_fault_isr ======== - * ISR to be triggered by a DSP MMU fault interrupt. - */ -irqreturn_t mmu_fault_isr(int irq, IN void *pRefData); - -#endif /* MMU_FAULT_ */ diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 6035757..d44c895 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -46,7 +46,6 @@ #include /* ----------------------------------- This */ -#include "mmu_fault.h" #include "_tiomap.h" #include "_deh.h" #include "_tiomap_mmu.h" @@ -62,6 +61,55 @@ static struct omap_dm_timer *timer; +static void mmu_fault_dpc(unsigned long data) +{ + struct deh_mgr *hdeh_mgr = (void *)data; + + if (!hdeh_mgr) + return; + + bridge_deh_notify(hdeh_mgr, DSP_MMUFAULT, 0); +} + +static irqreturn_t mmu_fault_isr(int irq, void *data) +{ + struct deh_mgr *deh_mgr_obj = data; + struct cfg_hostres *resources; + u32 dmmu_event_mask; + + if (!deh_mgr_obj) + return IRQ_HANDLED; + + resources = deh_mgr_obj->hbridge_context->resources; + if (!resources) { + dev_dbg(bridge, "%s: Failed to get Host Resources\n", + __func__); + return IRQ_HANDLED; + } + + hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); + if (dmmu_event_mask == HW_MMU_TRANSLATION_FAULT) { + hw_mmu_fault_addr_read(resources->dw_dmmu_base, &deh_mgr_obj->fault_addr); + dev_info(bridge, "%s: status=0x%x, fault_addr=0x%x\n", __func__, + dmmu_event_mask, deh_mgr_obj->fault_addr); + /* + * Schedule a DPC directly. In the future, it may be + * necessary to check if DSP MMU fault is intended for + * Bridge. + */ + tasklet_schedule(&deh_mgr_obj->dpc_tasklet); + + /* Disable the MMU events, else once we clear it will + * start to raise INTs again */ + hw_mmu_event_disable(resources->dw_dmmu_base, + HW_MMU_TRANSLATION_FAULT); + } else { + hw_mmu_event_disable(resources->dw_dmmu_base, + HW_MMU_ALL_INTERRUPTS); + } + return IRQ_HANDLED; +} + dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, struct dev_object *hdev_obj) { From patchwork Tue Jul 20 17:55:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 113036 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6KHpVje017562 for ; Tue, 20 Jul 2010 17:51:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758639Ab0GTRva (ORCPT ); Tue, 20 Jul 2010 13:51:30 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:57090 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753630Ab0GTRv3 (ORCPT ); Tue, 20 Jul 2010 13:51:29 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6KHpOLo031478 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 20 Jul 2010 12:51:24 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6KHpNS1024190; Tue, 20 Jul 2010 12:51:23 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6KHpLr2011995; Tue, 20 Jul 2010 12:51:22 -0500 (CDT) From: Ernesto Ramos To: linux-omap@vger.kernel.org Cc: felipe.contreras@nokia.com, ameya.palande@nokia.com, Hiroshi.DOYU@nokia.com, nm@ti.com, Ernesto Ramos Subject: [PATCH] staging:ti dspbridge: avoid possible NULL dereference panic Date: Tue, 20 Jul 2010 12:55:49 -0500 Message-Id: <1279648549-16603-1-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 20 Jul 2010 17:51:49 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/pmgr/dspapi.c b/drivers/staging/tidspbridge/pmgr/dspapi.c index 8a568b3..71b9b5b 100644 --- a/drivers/staging/tidspbridge/pmgr/dspapi.c +++ b/drivers/staging/tidspbridge/pmgr/dspapi.c @@ -539,7 +539,7 @@ func_end: */ u32 mgrwrap_wait_for_bridge_events(union Trapped_Args *args, void *pr_ctxt) { - int status = 0, real_status = 0; + int status = 0; struct dsp_notification *anotifications[MAX_EVENTS]; struct dsp_notification notifications[MAX_EVENTS]; u32 index, i; @@ -554,19 +554,21 @@ u32 mgrwrap_wait_for_bridge_events(union Trapped_Args *args, void *pr_ctxt) /* get the events */ for (i = 0; i < count; i++) { CP_FM_USR(¬ifications[i], anotifications[i], status, 1); - if (!status) { - /* set the array of pointers to kernel structures */ - anotifications[i] = ¬ifications[i]; + if (status || !notifications[i].handle) { + status = -EINVAL; + break; } + /* set the array of pointers to kernel structures */ + anotifications[i] = ¬ifications[i]; } if (!status) { - real_status = mgr_wait_for_bridge_events(anotifications, count, + status = mgr_wait_for_bridge_events(anotifications, count, &index, args->args_mgr_wait. utimeout); } CP_TO_USR(args->args_mgr_wait.pu_index, &index, status, 1); - return real_status; + return status; } /* From patchwork Fri Jul 2 10:18:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 109850 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o62AIgV7014445 for ; Fri, 2 Jul 2010 10:18:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754474Ab0GBKSo (ORCPT ); Fri, 2 Jul 2010 06:18:44 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:42369 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752570Ab0GBKSk (ORCPT ); Fri, 2 Jul 2010 06:18:40 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o62AIZcK004517 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 2 Jul 2010 05:18:37 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o62AIWCw017722; Fri, 2 Jul 2010 15:48:32 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o62AIV2A032235; Fri, 2 Jul 2010 15:48:31 +0530 Received: (from a0393109@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o62AIVvX032233; Fri, 2 Jul 2010 15:48:31 +0530 From: Thara Gopinath To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, b-cousson@ti.com, vishwanath.bs@ti.com, sawant@ti.com, p-basak2@ti.com, Thara Gopinath Subject: [RFC 4/7] OMAP: Voltage layer changes to support DVFS. Date: Fri, 2 Jul 2010 15:48:26 +0530 Message-Id: <1278065909-32148-5-git-send-email-thara@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1278065909-32148-4-git-send-email-thara@ti.com> References: <1278065909-32148-1-git-send-email-thara@ti.com> <1278065909-32148-2-git-send-email-thara@ti.com> <1278065909-32148-3-git-send-email-thara@ti.com> <1278065909-32148-4-git-send-email-thara@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 02 Jul 2010 10:18:49 +0000 (UTC) diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index a2f30a4..1e6712e 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -137,6 +137,8 @@ struct omap_vdd_info{ struct omap_volt_domain volt_domain; spinlock_t user_lock; struct plist_head user_list; + struct device **dev_list; + int dev_count; int volt_data_count; unsigned long nominal_volt; u8 cmdval_reg; @@ -387,6 +389,10 @@ static void __init omap3_vdd_data_configure(struct omap_vdd_info *vdd) spin_lock_init(&vdd->user_lock); plist_head_init(&vdd->user_list, &vdd->user_lock); + /* Get the devices associated with this VDD */ + vdd->dev_list = opp_init_voltage_params(&vdd->volt_domain, + &vdd->dev_count); + if (!strcmp(vdd->volt_domain.name, "mpu")) { if (cpu_is_omap3630()) { vdd->vp_reg.vlimitto_vddmin = @@ -1073,7 +1079,8 @@ void omap_voltageprocessor_disable(struct omap_volt_domain *volt_domain) } /** - * omap_voltage_scale : API to scale voltage of a particular voltage domain. + * omap_voltage_scale_vdd : API to scale voltage of a particular + * voltage domain. * @volt_domain: pointer to the VDD which is to be scaled. * @target_vsel : The target voltage of the voltage domain * @current_vsel : the current voltage of the voltage domain. @@ -1081,7 +1088,7 @@ void omap_voltageprocessor_disable(struct omap_volt_domain *volt_domain) * This API should be called by the kernel to do the voltage scaling * for a particular voltage domain during dvfs or any other situation. */ -int omap_voltage_scale(struct omap_volt_domain *volt_domain, +int omap_voltage_scale_vdd(struct omap_volt_domain *volt_domain, unsigned long target_volt) { struct omap_vdd_info *vdd; @@ -1290,6 +1297,84 @@ struct omap_volt_domain *omap_volt_domain_get(char *name) } /** + * omap_voltage_scale : API to scale the devices associated with a + * voltage domain vdd voltage. + * @volt_domain : the voltage domain to be scaled + * @volt : the new voltage for the voltage domain + * + * This API runs through the list of devices associated with the + * voltage domain and scales the device rates to those corresponding + * to the new voltage of the voltage domain. This API also scales + * the voltage domain voltage to the new value. Returns 0 on success + * else the error value. + */ +int omap_voltage_scale(struct omap_volt_domain *volt_domain, + unsigned long volt) +{ + unsigned long curr_volt; + int is_volt_scaled = 0, i; + struct omap_vdd_info *vdd; + + if (!volt_domain || IS_ERR(volt_domain)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return -EINVAL; + } + + vdd = container_of(volt_domain, struct omap_vdd_info, volt_domain); + curr_volt = get_curr_voltage(volt_domain); + + if (curr_volt == volt) { + is_volt_scaled = 1; + } else if (curr_volt < volt) { + omap_voltage_scale_vdd(volt_domain, volt); + is_volt_scaled = 1; + } + + for (i = 0; i < vdd->dev_count; i++) { + struct device_opp *dev_opp; + struct omap_opp *opp; + unsigned long freq; + + dev_opp = opp_find_dev_opp(vdd->dev_list[i]); + if (IS_ERR(dev_opp)) { + dev_err(vdd->dev_list[i], "%s: Unable to find device" + "opp table\n", __func__); + continue; + } + if (!dev_opp->set_rate) { + dev_err(vdd->dev_list[i], "%s: No set_rate API" + "for scaling opp\n", __func__); + continue; + } + + opp = opp_find_voltage(vdd->dev_list[i], volt); + if (IS_ERR(opp)) { + dev_err(vdd->dev_list[i], "%s: Unable to find OPP for" + "volt%ld\n", __func__, volt); + continue; + } + + freq = opp_get_freq(opp); + + if (dev_opp->get_rate) { + if (freq == dev_opp->get_rate(vdd->dev_list[i])) { + dev_err(vdd->dev_list[i], "%s: Already at the" + "requested rate %ld\n", + __func__, freq); + continue; + } + } + + dev_opp->set_rate(vdd->dev_list[i], freq); + } + + if (!is_volt_scaled) + omap_voltage_scale_vdd(volt_domain, volt); + + return 0; +} + +/** * omap_voltage_init : Volatage init API which does VP and VC init. */ static int __init omap_voltage_init(void) diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h index bc1e4d3..072ee76 100644 --- a/arch/arm/plat-omap/include/plat/voltage.h +++ b/arch/arm/plat-omap/include/plat/voltage.h @@ -120,8 +120,10 @@ unsigned long omap_voltageprocessor_get_curr_volt( struct omap_volt_domain *volt_domain); void omap_voltageprocessor_enable(struct omap_volt_domain *volt_domain); void omap_voltageprocessor_disable(struct omap_volt_domain *volt_domain); -int omap_voltage_scale(struct omap_volt_domain *volt_domain, +int omap_voltage_scale_vdd(struct omap_volt_domain *volt_domain, unsigned long target_volt); +int omap_voltage_scale(struct omap_volt_domain *volt_domain, + unsigned long volt); void omap_reset_voltage(struct omap_volt_domain *volt_domain); int omap_get_voltage_table(struct omap_volt_domain *volt_domain, struct omap_volt_data **volt_data); From patchwork Fri Jul 2 10:18:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 109851 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o62AIgV8014445 for ; Fri, 2 Jul 2010 10:18:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754579Ab0GBKSs (ORCPT ); Fri, 2 Jul 2010 06:18:48 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:56034 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752478Ab0GBKSm (ORCPT ); Fri, 2 Jul 2010 06:18:42 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o62AIZNh030906 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 2 Jul 2010 05:18:38 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o62AIUwk017717; Fri, 2 Jul 2010 15:48:31 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o62AIUUv032225; Fri, 2 Jul 2010 15:48:30 +0530 Received: (from a0393109@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o62AIU79032223; Fri, 2 Jul 2010 15:48:30 +0530 From: Thara Gopinath To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, b-cousson@ti.com, vishwanath.bs@ti.com, sawant@ti.com, p-basak2@ti.com, Thara Gopinath Subject: [RFC 2/7] OMAP: Introduce API in the OPP layer to find the opp entry corresponding to a voltage. Date: Fri, 2 Jul 2010 15:48:24 +0530 Message-Id: <1278065909-32148-3-git-send-email-thara@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1278065909-32148-2-git-send-email-thara@ti.com> References: <1278065909-32148-1-git-send-email-thara@ti.com> <1278065909-32148-2-git-send-email-thara@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 02 Jul 2010 10:18:50 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/opp.h b/arch/arm/plat-omap/include/plat/opp.h index 29e3d03..893731f 100644 --- a/arch/arm/plat-omap/include/plat/opp.h +++ b/arch/arm/plat-omap/include/plat/opp.h @@ -75,6 +75,8 @@ struct omap_opp *opp_find_freq_floor(struct device *dev, unsigned long *freq); struct omap_opp *opp_find_freq_ceil(struct device *dev, unsigned long *freq); +struct omap_opp *opp_find_voltage(struct device *dev, unsigned long volt); + int opp_add(const struct omap_opp_def *opp_def); int opp_enable(struct omap_opp *opp); diff --git a/arch/arm/plat-omap/opp.c b/arch/arm/plat-omap/opp.c index 0273497..070ff5b 100644 --- a/arch/arm/plat-omap/opp.c +++ b/arch/arm/plat-omap/opp.c @@ -302,6 +302,34 @@ struct omap_opp *opp_find_freq_floor(struct device *dev, unsigned long *freq) return opp; } +/** + * opp_find_voltage() - search for an exact voltage + * @dev: device pointer associated with the opp type + * @volt: voltage to search for + * + * Searches for exact match in the opp list and returns handle to the matching + * opp if found, else returns ERR_PTR in case of error and should be handled + * using IS_ERR. + */ +struct omap_opp *opp_find_voltage(struct device *dev, unsigned long volt) +{ + struct device_opp *dev_opp; + struct omap_opp *temp_opp, *opp = ERR_PTR(-ENODEV); + + dev_opp = find_device_opp(dev); + if (IS_ERR(dev_opp)) + return opp; + + list_for_each_entry(temp_opp, &dev_opp->opp_list, node) { + if (temp_opp->enabled && temp_opp->u_volt == volt) { + opp = temp_opp; + break; + } + } + + return opp; +} + /* wrapper to reuse converting opp_def to opp struct */ static void omap_opp_populate(struct omap_opp *opp, const struct omap_opp_def *opp_def) From patchwork Fri Jul 2 10:18:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 109852 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o62AIpv4014491 for ; Fri, 2 Jul 2010 10:18:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754635Ab0GBKSt (ORCPT ); Fri, 2 Jul 2010 06:18:49 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:38687 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753344Ab0GBKSk (ORCPT ); Fri, 2 Jul 2010 06:18:40 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o62AIZV1032659 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 2 Jul 2010 05:18:38 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o62AIVql017719; Fri, 2 Jul 2010 15:48:31 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o62AIVrf032230; Fri, 2 Jul 2010 15:48:31 +0530 Received: (from a0393109@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o62AIUUF032228; Fri, 2 Jul 2010 15:48:30 +0530 From: Thara Gopinath To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, b-cousson@ti.com, vishwanath.bs@ti.com, sawant@ti.com, p-basak2@ti.com, Thara Gopinath Subject: [RFC 3/7] OMAP: Introduce voltage domain pointer and device specific set rate and get rate in device opp structures. Date: Fri, 2 Jul 2010 15:48:25 +0530 Message-Id: <1278065909-32148-4-git-send-email-thara@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1278065909-32148-3-git-send-email-thara@ti.com> References: <1278065909-32148-1-git-send-email-thara@ti.com> <1278065909-32148-2-git-send-email-thara@ti.com> <1278065909-32148-3-git-send-email-thara@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 02 Jul 2010 10:18:52 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/opp.h b/arch/arm/plat-omap/include/plat/opp.h index 893731f..15e1e70 100644 --- a/arch/arm/plat-omap/include/plat/opp.h +++ b/arch/arm/plat-omap/include/plat/opp.h @@ -16,6 +16,7 @@ #include #include +#include #include @@ -38,21 +39,45 @@ */ struct omap_opp_def { char *hwmod_name; + char *vdd_name; unsigned long freq; unsigned long u_volt; + int (*set_rate)(struct device *dev, unsigned long rate); + unsigned long (*get_rate) (struct device *dev); + bool enabled; }; +struct device_opp { + struct list_head node; + char *vdd_name; + + struct omap_hwmod *oh; + struct device *dev; + struct omap_volt_domain *volt_domain; + + struct list_head opp_list; + u32 opp_count; + u32 enabled_opp_count; + + int (*set_rate)(struct device *dev, unsigned long rate); + unsigned long (*get_rate) (struct device *dev); +}; + /* * Initialization wrapper used to define an OPP. * To point at the end of a terminator of a list of OPPs, * use OMAP_OPP_DEF(0, 0, 0) */ -#define OMAP_OPP_DEF(_hwmod_name, _enabled, _freq, _uv) \ +#define OMAP_OPP_DEF(_hwmod_name, _vdd_name, _set_rate, _get_rate, \ + _enabled, _freq, _uv) \ { \ .hwmod_name = _hwmod_name, \ + .vdd_name = _vdd_name, \ + .set_rate = _set_rate, \ + .get_rate = _get_rate, \ .enabled = _enabled, \ .freq = _freq, \ .u_volt = _uv, \ @@ -77,6 +102,8 @@ struct omap_opp *opp_find_freq_ceil(struct device *dev, unsigned long *freq); struct omap_opp *opp_find_voltage(struct device *dev, unsigned long volt); +struct device_opp *opp_find_dev_opp(struct device *dev); + int opp_add(const struct omap_opp_def *opp_def); int opp_enable(struct omap_opp *opp); @@ -89,6 +116,9 @@ u8 __deprecated opp_get_opp_id(struct omap_opp *opp); void opp_init_cpufreq_table(struct device *dev, struct cpufreq_frequency_table **table); + +struct device **opp_init_voltage_params(struct omap_volt_domain *volt_domain, + int *dev_count); #else static inline unsigned long opp_get_voltage(const struct omap_opp *opp) { @@ -124,6 +154,11 @@ static inline struct omap_opp *opp_find_freq_ceil(struct omap_opp *oppl, return ERR_PTR(-EINVAL); } +static inline struct device_opp *opp_find_dev_opp(struct device *dev) +{ + return ERR_PTR(-EINVAL); +} + static inline struct omap_opp *opp_add(struct omap_opp *oppl, const struct omap_opp_def *opp_def) { diff --git a/arch/arm/plat-omap/opp.c b/arch/arm/plat-omap/opp.c index 070ff5b..9bc53e8 100644 --- a/arch/arm/plat-omap/opp.c +++ b/arch/arm/plat-omap/opp.c @@ -22,6 +22,7 @@ #include #include #include +#include /** * struct omap_opp - OMAP OPP description structure @@ -43,17 +44,6 @@ struct omap_opp { struct device_opp *dev_opp; /* containing device_opp struct */ }; -struct device_opp { - struct list_head node; - - struct omap_hwmod *oh; - struct device *dev; - - struct list_head opp_list; - u32 opp_count; - u32 enabled_opp_count; -}; - static LIST_HEAD(dev_opp_list); /** @@ -330,6 +320,11 @@ struct omap_opp *opp_find_voltage(struct device *dev, unsigned long volt) return opp; } +struct device_opp *opp_find_dev_opp(struct device *dev) +{ + return find_device_opp(dev); +} + /* wrapper to reuse converting opp_def to opp struct */ static void omap_opp_populate(struct omap_opp *opp, const struct omap_opp_def *opp_def) @@ -385,6 +380,11 @@ int opp_add(const struct omap_opp_def *opp_def) dev_opp->oh = oh; dev_opp->dev = &oh->od->pdev.dev; + dev_opp->vdd_name = kzalloc(strlen(opp_def->vdd_name) + 1, + GFP_KERNEL); + strcpy(dev_opp->vdd_name, opp_def->vdd_name); + dev_opp->set_rate = opp_def->set_rate; + dev_opp->get_rate = opp_def->get_rate; INIT_LIST_HEAD(&dev_opp->opp_list); list_add(&dev_opp->node, &dev_opp_list); @@ -511,3 +511,28 @@ void opp_init_cpufreq_table(struct device *dev, *table = &freq_table[0]; } + +struct device **opp_init_voltage_params(struct omap_volt_domain *volt_domain, + int *dev_count) +{ + struct device_opp *dev_opp; + struct device **dev_list; + int count = 0, i = 0; + + list_for_each_entry(dev_opp, &dev_opp_list, node) { + if (!strcmp(dev_opp->vdd_name, volt_domain->name)) { + dev_opp->volt_domain = volt_domain; + count++; + } + } + + dev_list = kzalloc(sizeof(struct device *) * count, GFP_KERNEL); + + list_for_each_entry(dev_opp, &dev_opp_list, node) { + if (dev_opp->volt_domain == volt_domain) + dev_list[i++] = dev_opp->dev; + } + + *dev_count = count; + return dev_list; +} From patchwork Wed Jul 7 09:44:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 110592 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o679iDOq027803 for ; Wed, 7 Jul 2010 09:44:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754541Ab0GGJoM (ORCPT ); Wed, 7 Jul 2010 05:44:12 -0400 Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:59442 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754518Ab0GGJoK (ORCPT ); Wed, 7 Jul 2010 05:44:10 -0400 Received: from muru.com ([72.249.23.125] helo=baageli.muru.com) by mho-02-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OWRAn-000Jd1-Tl; Wed, 07 Jul 2010 09:44:10 +0000 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX18/kg4uF9t9UUR599RbfPwc Subject: [PATCH 03/13] omap3: pandora: update gpio-keys data To: linux-arm-kernel@lists.infradead.org From: Tony Lindgren Cc: linux-omap@vger.kernel.org, Grazvydas Ignotas Date: Wed, 07 Jul 2010 12:44:08 +0300 Message-ID: <20100707094408.2562.12431.stgit@baageli.muru.com> In-Reply-To: <20100707094308.2562.91921.stgit@baageli.muru.com> References: <20100707094308.2562.91921.stgit@baageli.muru.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 09:44:14 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index db06dc9..7a12729 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -48,9 +48,6 @@ #define OMAP3_PANDORA_TS_GPIO 94 -/* hardware debounce: (value + 1) * 31us */ -#define GPIO_DEBOUNCE_TIME 127 - static struct gpio_led pandora_gpio_leds[] = { { .name = "pandora::sd1", @@ -88,6 +85,7 @@ static struct platform_device pandora_leds_gpio = { .type = ev_type, \ .code = ev_code, \ .active_low = act_low, \ + .debounce_interval = 4, \ .desc = "btn " descr, \ } @@ -99,14 +97,14 @@ static struct gpio_keys_button pandora_gpio_keys[] = { GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), - GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"), - GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"), - GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"), - GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"), - GPIO_BUTTON_LOW(102, BTN_TL, "l"), - GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), - GPIO_BUTTON_LOW(105, BTN_TR, "r"), - GPIO_BUTTON_LOW(107, BTN_TR2, "r2"), + GPIO_BUTTON_LOW(109, KEY_PAGEUP, "game 1"), + GPIO_BUTTON_LOW(111, KEY_END, "game 2"), + GPIO_BUTTON_LOW(106, KEY_PAGEDOWN, "game 3"), + GPIO_BUTTON_LOW(101, KEY_HOME, "game 4"), + GPIO_BUTTON_LOW(102, KEY_RIGHTSHIFT, "l"), + GPIO_BUTTON_LOW(97, KEY_KPPLUS, "l2"), + GPIO_BUTTON_LOW(105, KEY_RIGHTCTRL, "r"), + GPIO_BUTTON_LOW(107, KEY_KPMINUS, "r2"), GPIO_BUTTON_LOW(104, KEY_LEFTCTRL, "ctrl"), GPIO_BUTTON_LOW(99, KEY_MENU, "menu"), GPIO_BUTTON_LOW(176, KEY_COFFEE, "hold"), @@ -127,14 +125,7 @@ static struct platform_device pandora_keys_gpio = { }, }; -static void __init pandora_keys_gpio_init(void) -{ - /* set debounce time for GPIO banks 4 and 6 */ - gpio_set_debounce(32 * 3, GPIO_DEBOUNCE_TIME); - gpio_set_debounce(32 * 5, GPIO_DEBOUNCE_TIME); -} - -static int board_keymap[] = { +static const uint32_t board_keymap[] = { /* row, col, code */ KEY(0, 0, KEY_9), KEY(0, 1, KEY_8), @@ -582,7 +573,6 @@ static void __init omap3pandora_init(void) ARRAY_SIZE(omap3pandora_spi_board_info)); omap3pandora_ads7846_init(); usb_ehci_init(&ehci_pdata); - pandora_keys_gpio_init(); usb_musb_init(&musb_board_data); /* Ensure SDRC pins are mux'd for self-refresh */ From patchwork Thu Jul 8 12:10:51 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 110827 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68CBIwZ029247 for ; Thu, 8 Jul 2010 12:11:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756619Ab0GHMKz (ORCPT ); Thu, 8 Jul 2010 08:10:55 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50877 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755739Ab0GHMKx (ORCPT ); Thu, 8 Jul 2010 08:10:53 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68CAqi7031599 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 07:10:52 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o68CAnkq013754; Thu, 8 Jul 2010 07:10:50 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Thu, 8 Jul 2010 17:40:51 +0530 (IST) Message-ID: <56025.10.24.255.17.1278591051.squirrel@dbdmail.itg.ti.com> Date: Thu, 8 Jul 2010 17:40:51 +0530 (IST) Subject: [RFC] [PATCH] mfd: Support for TWL6030 PWM From: "Hemanth V" To: sameo@linux.intel.com Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 12:11:18 +0000 (UTC) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index c7c11ef..4459fe5 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -162,6 +162,15 @@ config TWL6030_GPADC Say yes here if you want support for the TWL6030 General Purpose A/D Convertor. +config TWL6030_PWM + tristate "TWL6030 PWM (Pulse Width Modulator) Support" + depends on TWL4030_CORE + select HAVE_PWM + default n + help + Say yes here if you want support for TWL6030 PWM. + This is used to control charging LED brightness. + config MFD_TMIO bool default n diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 204a974..e697101 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o obj-$(CONFIG_TWL4030_CODEC) += twl4030-codec.o obj-$(CONFIG_TWL6030_GPADC) += twl6030-gpadc.o +obj-$(CONFIG_TWL6030_PWM) += twl6030-pwm.o obj-$(CONFIG_MFD_MC13783) += mc13783-core.o @@ -63,4 +64,4 @@ obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o obj-$(CONFIG_AB4500_CORE) += ab4500-core.o obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o obj-$(CONFIG_PMIC_ADP5520) += adp5520.o -obj-$(CONFIG_LPC_SCH) += lpc_sch.o \ No newline at end of file +obj-$(CONFIG_LPC_SCH) += lpc_sch.o diff --git a/drivers/mfd/twl6030-pwm.c b/drivers/mfd/twl6030-pwm.c new file mode 100644 index 0000000..5d25bdc --- /dev/null +++ b/drivers/mfd/twl6030-pwm.c @@ -0,0 +1,163 @@ +/* + * twl6030_pwm.c + * Driver for PHOENIX (TWL6030) Pulse Width Modulator + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include + +#define LED_PWM_CTRL1 0xF4 +#define LED_PWM_CTRL2 0xF5 + +/* Max value for CTRL1 register */ +#define PWM_CTRL1_MAX 255 + +/* Pull down disable */ +#define PWM_CTRL2_DIS_PD (1 << 6) + +/* Current control 2.5 milli Amps */ +#define PWM_CTRL2_CURR_02 (2 << 4) + +/* LED supply source */ +#define PWM_CTRL2_SRC_VAC (1 << 2) + +/* LED modes */ +#define PWM_CTRL2_MODE_HW (0 << 0) +#define PWM_CTRL2_MODE_SW (1 << 0) +#define PWM_CTRL2_MODE_DIS (2 << 0) + +#define PWM_CTRL2_MODE_MASK 0x3 + +struct pwm_device { + const char *label; + unsigned int pwm_id; +}; + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + u8 duty_cycle; + int ret; + + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) + return -EINVAL; + + duty_cycle = (duty_ns * PWM_CTRL1_MAX) / period_ns; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, duty_cycle, LED_PWM_CTRL1); + + if (ret < 0) { + pr_err("%s: Failed to configure PWM, Error %d\n", + pwm->label, ret); + return ret; + } + return 0; +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + u8 val; + int ret; + + ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret); + return ret; + } + + /* Change mode to software control */ + val &= ~PWM_CTRL2_MODE_MASK; + val |= PWM_CTRL2_MODE_SW; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret); + return ret; + } + + twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); + return 0; +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + u8 val; + int ret; + + ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to disable PWM, Error %d\n", + pwm->label, ret); + return; + } + + val &= ~PWM_CTRL2_MODE_MASK; + val |= PWM_CTRL2_MODE_HW; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to disable PWM, Error %d\n", + pwm->label, ret); + return; + } + return; +} +EXPORT_SYMBOL(pwm_disable); + +struct pwm_device *pwm_request(int pwm_id, const char *label) +{ + u8 val; + int ret; + struct pwm_device *pwm; + + pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm == NULL) { + pr_err("%s: failed to allocate memory\n", label); + return NULL; + } + + pwm->label = label; + pwm->pwm_id = pwm_id; + + /* Configure PWM */ + val = PWM_CTRL2_DIS_PD | PWM_CTRL2_CURR_02 | PWM_CTRL2_SRC_VAC | + PWM_CTRL2_MODE_HW; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); + + if (ret < 0) { + pr_err("%s: Failed to configure PWM, Error %d\n", + pwm->label, ret); + + kfree(pwm); + return NULL; + } + + return pwm; +} +EXPORT_SYMBOL(pwm_request); + +void pwm_free(struct pwm_device *pwm) +{ + pwm_disable(pwm); + kfree(pwm); +} +EXPORT_SYMBOL(pwm_free); From patchwork Thu Jul 8 11:04:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 110823 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68B5LBf018821 for ; Thu, 8 Jul 2010 11:05:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756054Ab0GHLFN (ORCPT ); Thu, 8 Jul 2010 07:05:13 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:52482 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753480Ab0GHLFK (ORCPT ); Thu, 8 Jul 2010 07:05:10 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68B4whu017134 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 06:05:01 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68B4tgM028334; Thu, 8 Jul 2010 16:34:56 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o68B4t1g017024; Thu, 8 Jul 2010 16:34:55 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o68B4tUw017021; Thu, 8 Jul 2010 16:34:55 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Anand Gadiyar , Ajay Kumar Gupta Subject: [PATCH 2/2] usb: musb: do not override DMA mode in channel program Date: Thu, 8 Jul 2010 16:34:55 +0530 Message-Id: <1278587095-16978-3-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1278587095-16978-2-git-send-email-ajay.gupta@ti.com> References: <1278587095-16978-1-git-send-email-ajay.gupta@ti.com> <1278587095-16978-2-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 11:05:21 +0000 (UTC) diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index dc66e43..6dc107f 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c @@ -173,10 +173,7 @@ static int dma_channel_program(struct dma_channel *channel, musb_channel->max_packet_sz = packet_sz; channel->status = MUSB_DMA_STATUS_BUSY; - if ((mode == 1) && (len >= packet_sz)) - configure_channel(channel, packet_sz, 1, dma_addr, len); - else - configure_channel(channel, packet_sz, 0, dma_addr, len); + configure_channel(channel, packet_sz, mode, dma_addr, len); return true; } From patchwork Thu Jul 8 11:04:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 110822 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68B5LBe018821 for ; Thu, 8 Jul 2010 11:05:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756011Ab0GHLFK (ORCPT ); Thu, 8 Jul 2010 07:05:10 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:55262 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755153Ab0GHLFI (ORCPT ); Thu, 8 Jul 2010 07:05:08 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68B4wFS025205 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 06:05:01 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68B4t3H028333; Thu, 8 Jul 2010 16:34:56 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o68B4tpo017018; Thu, 8 Jul 2010 16:34:55 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o68B4tIp017015; Thu, 8 Jul 2010 16:34:55 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Anand Gadiyar , Ajay Kumar Gupta Subject: [PATCH 1/2] musb: Kill board specific pinmux from driver file Date: Thu, 8 Jul 2010 16:34:54 +0530 Message-Id: <1278587095-16978-2-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1278587095-16978-1-git-send-email-ajay.gupta@ti.com> References: <1278587095-16978-1-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 11:05:21 +0000 (UTC) Acked-by: Tony Lindgren diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index e06d65e..2111a24 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -32,8 +32,6 @@ #include #include -#include - #include "musb_core.h" #include "omap2430.h" @@ -194,10 +192,6 @@ int __init musb_platform_init(struct musb *musb, void *board_data) u32 l; struct omap_musb_board_data *data = board_data; -#if defined(CONFIG_ARCH_OMAP2430) - omap_cfg_reg(AE5_2430_USB0HS_STP); -#endif - /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. From patchwork Fri Jun 25 00:39:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Que, Simon" X-Patchwork-Id: 107979 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5P0djVi009584 for ; Fri, 25 Jun 2010 00:39:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753436Ab0FYAjm (ORCPT ); Thu, 24 Jun 2010 20:39:42 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:44131 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753091Ab0FYAjl (ORCPT ); Thu, 24 Jun 2010 20:39:41 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5P0dfJa005743 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 24 Jun 2010 19:39:41 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o5P0de6x003988; Thu, 24 Jun 2010 19:39:40 -0500 (CDT) Received: from dlee74.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5P0deht010767; Thu, 24 Jun 2010 19:39:40 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dlee74.ent.ti.com ([157.170.170.8]) with mapi; Thu, 24 Jun 2010 19:39:40 -0500 From: "Que, Simon" To: "linux-omap@vger.kernel.org" CC: "Kanigeri, Hari" , Ohad Ben-Cohen Date: Thu, 24 Jun 2010 19:39:38 -0500 Subject: [RFC] omap: Thread-Topic: [RFC] omap: Thread-Index: AcsT/uSyE+vCHOyESneG/KF0kTr/Fg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 25 Jun 2010 00:39:46 +0000 (UTC) ===================================================================== diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 9f73d79..a13c188 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -182,3 +182,13 @@ config OMAP3_SDRC_AC_TIMING wish to say no. Selecting yes without understanding what is going on could result in system crashes; +config OMAP_HWSPINLOCK_NUM_RESERVED + int "Number of hardware spinlocks reserved for system use" + depends on ARCH_OMAP + default 8 + range 0 32 + help + Choose a number of hardware spinlocks to reserve for internal use. + The rest will be unreserved and availble for general use. Make + that the number of reserved locks does not exceed the total number + available locks. diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 6725b3a..14af19a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -170,3 +170,5 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) + +obj-y += hwspinlocks.o \ No newline at end of file diff --git a/arch/arm/mach-omap2/hwspinlocks.c b/arch/arm/mach-omap2/hwspinlocks.c new file mode 100644 index 0000000..de813a0 --- /dev/null +++ b/arch/arm/mach-omap2/hwspinlocks.c @@ -0,0 +1,126 @@ +/* + * OMAP hardware spinlock driver + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* Base address of HW spinlock module */ +#define HWSPINLOCK_BASE (L4_44XX_BASE + 0xF6000) +#define HWSPINLOCK_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(HWSPINLOCK_BASE + (reg)) + +/* Spinlock register offsets */ +#define HWSPINLOCK_REVISION 0x0000 +#define HWSPINLOCK_SYSCONFIG 0x0010 +#define HWSPINLOCK_SYSSTATUS 0x0014 +#define HWSPINLOCK_LOCK_BASE 0x0800 + +/* Spinlock register addresses */ +#define HWSPINLOCK_REVISION_REG \ + HWSPINLOCK_REGADDR(HWSPINLOCK_REVISION) +#define HWSPINLOCK_SYSCONFIG_REG \ + HWSPINLOCK_REGADDR(HWSPINLOCK_SYSCONFIG) +#define HWSPINLOCK_SYSSTATUS_REG \ + HWSPINLOCK_REGADDR(HWSPINLOCK_SYSSTATUS) +#define HWSPINLOCK_LOCK_REG(i) \ + HWSPINLOCK_REGADDR(HWSPINLOCK_LOCK_BASE + 0x4 * (i)) + +/* Spinlock count code */ +#define HWSPINLOCK_32_REGS 1 +#define HWSPINLOCK_64_REGS 2 +#define HWSPINLOCK_128_REGS 4 +#define HWSPINLOCK_256_REGS 8 +#define HWSPINLOCK_NUMLOCKS_OFFSET 24 + + +/* Initialization function */ +int __init hwspinlocks_init(void) +{ + int i; + int retval = 0; + + struct platform_device *pdev; + struct hwspinlock_plat_info *pdata; + void __iomem *base; + int num_locks; + bool is_reserved; + + /* Determine number of locks */ + switch (__raw_readl(HWSPINLOCK_SYSSTATUS_REG) >> + HWSPINLOCK_NUMLOCKS_OFFSET) { + case HWSPINLOCK_32_REGS: + num_locks = 32; + break; + case HWSPINLOCK_64_REGS: + num_locks = 64; + break; + case HWSPINLOCK_128_REGS: + num_locks = 128; + break; + case HWSPINLOCK_256_REGS: + num_locks = 256; + break; + default: + return -EINVAL; /* Invalid spinlock count code */ + } + + /* Device drivers */ + for (i = 0; i < num_locks; i++) { + pdev = platform_device_alloc("hwspinlock", i); + + base = HWSPINLOCK_LOCK_REG(i); /* Get register address */ + + /* Some locks are reserved for system use */ + if (i < CONFIG_OMAP_HWSPINLOCK_NUM_RESERVED) + is_reserved = true; + else + is_reserved = false; + + /* Pass data to device initialization */ + pdata = kzalloc(sizeof(struct hwspinlock_plat_info), + GFP_KERNEL); + pdata->num_locks = num_locks; + pdata->io_base = base; + pdata->is_reserved = is_reserved; + retval = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (retval) + goto device_add_fail; + + retval = platform_device_add(pdev); + if (retval) + goto device_add_fail; + continue; +device_add_fail: + platform_device_put(pdev); + } + + return retval; +} +module_init(hwspinlocks_init); + diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index a37abf5..fb98ff9 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -32,4 +32,5 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o obj-$(CONFIG_OMAP_REMOTE_PROC) += remoteproc.o -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +obj-y += hwspinlock.o \ No newline at end of file diff --git a/arch/arm/plat-omap/hwspinlock.c b/arch/arm/plat-omap/hwspinlock.c new file mode 100644 index 0000000..327a524 --- /dev/null +++ b/arch/arm/plat-omap/hwspinlock.c @@ -0,0 +1,331 @@ +/* + * OMAP hardware spinlock driver + * + * Copyright (C) 2010 Texas Instruments. All rights reserved. + * + * Contact: Simon Que + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* for managing a hardware spinlock module */ +struct hwspinlock_state { + bool is_init; /* For first-time initialization */ + int num_locks; /* Total number of locks in system */ + spinlock_t local_lock; /* Local protection */ +}; + +/* Points to the hardware spinlock module */ +static struct hwspinlock_state hwspinlock_state; +static struct hwspinlock_state *hwspinlock_module = &hwspinlock_state; + +/* Spinlock object */ +struct hwspinlock { + void __iomem *io_base; + bool is_reserved; + bool is_allocated; + struct platform_device *pdev; +}; + +/* Array of spinlocks */ +static struct hwspinlock *hwspinlocks; + +/* API functions */ + +/* Busy loop to acquire a spinlock */ +int hwspinlock_lock(struct hwspinlock *handle) +{ + int retval; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + /* Attempt to acquire the lock by reading from it */ + do { + retval = __raw_readl(handle->io_base); + } while (retval == HWSPINLOCK_BUSY); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_lock); + +/* Attempt to acquire a spinlock once */ +int hwspinlock_trylock(struct hwspinlock *handle) +{ + int retval = 0; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + /* Attempt to acquire the lock by reading from it */ + retval = __raw_readl(handle->io_base); + + return retval; +} +EXPORT_SYMBOL(hwspinlock_trylock); + +/* Release a spinlock */ +int hwspinlock_unlock(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + /* Release it by writing 0 to it */ + __raw_writel(0, handle->io_base); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_unlock); + +/* Busy loop to acquire a spinlock, disabling interrupts/preemption */ +int hwspinlock_lock_irqsave(struct hwspinlock *handle, unsigned long *flags) +{ + int retval; + unsigned long temp_flags; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + if (WARN_ON(flags == NULL)) + return -EINVAL; + + /* Attempt to acquire the lock by reading from it */ + do { + preempt_disable(); /* Disable preemption */ + local_irq_save(temp_flags); /* Disable interrupts */ + + retval = __raw_readl(handle->io_base); + + /* Restore interrupts and preemption if not successful */ + if (retval == HWSPINLOCK_BUSY) { + local_irq_restore(temp_flags); + preempt_enable(); + } + } while (retval == HWSPINLOCK_BUSY); + + *flags = temp_flags; /* Return IRQ state */ + + return 0; +} +EXPORT_SYMBOL(hwspinlock_lock_irqsave); + +/* Attempt to acquire a spinlock once, disabling interrupts/preemption */ +int hwspinlock_trylock_irqsave(struct hwspinlock *handle, unsigned long *flags) +{ + int retval = 0; + unsigned long temp_flags; + + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(in_atomic() || in_irq())) + return -EPERM; + + if (WARN_ON(flags == NULL)) + return -EINVAL; + + preempt_disable(); /* Disable preemption */ + local_irq_save(temp_flags); /* Disable interrupts */ + + /* Attempt to acquire the lock by reading from it */ + retval = __raw_readl(handle->io_base); + + /* Restore interrupts and preemption if not successful */ + if (retval == HWSPINLOCK_BUSY) { + local_irq_restore(temp_flags); + preempt_enable(); + } else + *flags = temp_flags; /* Return IRQ state */ + + return retval; +} +EXPORT_SYMBOL(hwspinlock_trylock_irqsave); + +/* Unlock a spinlock that was locked with irq/preempt disabled */ +int hwspinlock_unlock_irqrestore(struct hwspinlock *handle, unsigned long + flags) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + /* Release it by writing 0 to it */ + __raw_writel(0, handle->io_base); + + /* Restore interrupts and preemption */ + local_irq_restore(flags); + preempt_enable(); + + return 0; +} +EXPORT_SYMBOL(hwspinlock_unlock_irqrestore); + +/* Request an unclaimed spinlock */ +struct hwspinlock *hwspinlock_request(void) +{ + int i; + bool found = false; + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + /* Search for an unclaimed, unreserved lock */ + for (i = 0; i < hwspinlock_module->num_locks && !found; i++) { + if (!hwspinlocks[i].is_allocated && + !hwspinlocks[i].is_reserved) { + found = true; + handle = &hwspinlocks[i]; + } + } + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + + /* Return error if no more locks available */ + if (!found) + return NULL; + + handle->is_allocated = true; + + return handle; +} +EXPORT_SYMBOL(hwspinlock_request); + +/* Request an unclaimed spinlock by ID */ +struct hwspinlock *hwspinlock_request_specific(unsigned int id) +{ + struct hwspinlock *handle = NULL; + unsigned long flags; + + spin_lock_irqsave(&hwspinlock_module->local_lock, flags); + + if (WARN_ON(!hwspinlocks[id].is_reserved)) + goto exit; + + if (WARN_ON(hwspinlocks[id].is_allocated)) + goto exit; + + handle = &hwspinlocks[id]; + handle->is_allocated = true; + +exit: + spin_unlock_irqrestore(&hwspinlock_module->local_lock, flags); + return handle; +} +EXPORT_SYMBOL(hwspinlock_request_specific); + +/* Release a claimed spinlock */ +int hwspinlock_free(struct hwspinlock *handle) +{ + if (WARN_ON(handle == NULL)) + return -EINVAL; + + if (WARN_ON(!handle->is_allocated)) + return -ENOMEM; + + handle->is_allocated = false; + + return 0; +} +EXPORT_SYMBOL(hwspinlock_free); + +/* Probe function */ +static int __devinit hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_plat_info *pdata = pdev->dev.platform_data; + int id = pdev->id; + + /* Set up the spinlock count and array */ + if (!hwspinlock_module->is_init) { + hwspinlock_module->num_locks = pdata->num_locks; + + /* Allocate spinlock device objects */ + hwspinlocks = kmalloc(sizeof(struct hwspinlock) * + hwspinlock_module->num_locks, GFP_KERNEL); + if (WARN_ON(hwspinlocks == NULL)) + return -ENOMEM; + + /* Initialize local lock */ + spin_lock_init(&hwspinlock_module->local_lock); + + /* Only do initialization once */ + hwspinlock_module->is_init = true; + } + + hwspinlocks[id].pdev = pdev; + + hwspinlocks[id].is_reserved = pdata->is_reserved; + hwspinlocks[id].is_allocated = false; + hwspinlocks[id].io_base = pdata->io_base; + + return 0; +} + +static struct platform_driver hwspinlock_driver = { + .probe = hwspinlock_probe, + .driver = { + .name = "hwspinlock", + }, +}; + +/* Initialization function */ +static int __init hwspinlock_init(void) +{ + int retval = 0; + + /* Register spinlock driver */ + retval = platform_driver_register(&hwspinlock_driver); + + /* Make sure the it was properly initialized */ + if (WARN_ON(!hwspinlock_module->is_init)) + return -EACCES; + + return retval; +} + +/* Cleanup function */ +static void __exit hwspinlock_exit(void) +{ + platform_driver_unregister(&hwspinlock_driver); + + /* Free spinlock device objects */ + if (hwspinlock_module->is_init) + kfree(hwspinlocks); +} + +module_init(hwspinlock_init); +module_exit(hwspinlock_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver"); +MODULE_AUTHOR("Simon Que"); +MODULE_AUTHOR("Hari Kanigeri"); diff --git a/arch/arm/plat-omap/include/plat/hwspinlock.h b/arch/arm/plat-omap/include/plat/hwspinlock.h new file mode 100644 index 0000000..1cdf7a8 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/hwspinlock.h @@ -0,0 +1,35 @@ +/* hwspinlock.h */ + +#ifndef HWSPINLOCK_H +#define HWSPINLOCK_H + +#include +#include + +/* Read values from the spinlock register */ +#define HWSPINLOCK_ACQUIRED 0 +#define HWSPINLOCK_BUSY 1 + +/* Device data */ +struct hwspinlock_plat_info { + int num_locks; /* Number of locks (initialization) */ + void __iomem *io_base; /* Address of spinlock register */ + bool is_reserved; /* Reserved for system use? */ +}; + +struct hwspinlock; + +int hwspinlock_lock(struct hwspinlock *handle); +int hwspinlock_trylock(struct hwspinlock *handle); +int hwspinlock_unlock(struct hwspinlock *handle); + +int hwspinlock_lock_irqsave(struct hwspinlock *handle, unsigned long *flags); +int hwspinlock_trylock_irqsave(struct hwspinlock *handle, unsigned long *flags); +int hwspinlock_unlock_irqrestore(struct hwspinlock *handle, unsigned long + flags); + +struct hwspinlock *hwspinlock_request(void); +struct hwspinlock *hwspinlock_request_specific(unsigned int id); +int hwspinlock_free(struct hwspinlock *hwspinlock_ptr); + +#endif /* HWSPINLOCK_H */ From patchwork Wed May 5 14:27:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97100 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ERwOe002626 for ; Wed, 5 May 2010 14:27:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933969Ab0EEO1w (ORCPT ); Wed, 5 May 2010 10:27:52 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34075 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932234Ab0EEO1v (ORCPT ); Wed, 5 May 2010 10:27:51 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERBjh005144; Wed, 5 May 2010 09:27:49 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:48 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:48 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfR5016232; Wed, 5 May 2010 17:27:47 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 03/21] OMAP: DSS2: Taal: Add locks to protect taal data access Date: Wed, 5 May 2010 17:27:23 +0300 Message-Id: <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:48.0100 (UTC) FILETIME=[22A88C40:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:00 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 8fbb94e..0eed328 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -364,6 +364,8 @@ static ssize_t taal_num_errors_show(struct device *dev, u8 errors; int r; + mutex_lock(&td->lock); + if (td->enabled) { dsi_bus_lock(); r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors); @@ -372,6 +374,8 @@ static ssize_t taal_num_errors_show(struct device *dev, r = -ENODEV; } + mutex_unlock(&td->lock); + if (r) return r; @@ -386,6 +390,8 @@ static ssize_t taal_hw_revision_show(struct device *dev, u8 id1, id2, id3; int r; + mutex_lock(&td->lock); + if (td->enabled) { dsi_bus_lock(); r = taal_get_id(&id1, &id2, &id3); @@ -394,6 +400,8 @@ static ssize_t taal_hw_revision_show(struct device *dev, r = -ENODEV; } + mutex_unlock(&td->lock); + if (r) return r; @@ -443,6 +451,8 @@ static ssize_t store_cabc_mode(struct device *dev, if (i == ARRAY_SIZE(cabc_modes)) return -EINVAL; + mutex_lock(&td->lock); + if (td->enabled) { dsi_bus_lock(); if (!td->cabc_broken) @@ -452,6 +462,8 @@ static ssize_t store_cabc_mode(struct device *dev, td->cabc_mode = i; + mutex_unlock(&td->lock); + return count; } From patchwork Thu Apr 1 00:29:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Madhusudhan X-Patchwork-Id: 90037 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o310Ts0l007050 for ; Thu, 1 Apr 2010 00:29:54 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755832Ab0DAA3x (ORCPT ); Wed, 31 Mar 2010 20:29:53 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59446 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750795Ab0DAA3w (ORCPT ); Wed, 31 Mar 2010 20:29:52 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o310TbFF018624 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 31 Mar 2010 19:29:37 -0500 Received: from webmail.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o310TYKG022864; Wed, 31 Mar 2010 19:29:35 -0500 (CDT) Received: from 192.168.10.89 (proxying for 128.247.79.84) (SquirrelMail authenticated user x0070977); by dbdmail.itg.ti.com with HTTP; Thu, 1 Apr 2010 05:59:36 +0530 (IST) Message-ID: <40837.192.168.10.89.1270081776.squirrel@dbdmail.itg.ti.com> Date: Thu, 1 Apr 2010 05:59:36 +0530 (IST) Subject: [PATCH]OMAP HSMMC: Fix a bug in card remove scenario From: "Madhusudhan Chikkature" To: akpm@linux-foundation.org Cc: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Apr 2010 00:29:55 +0000 (UTC) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 83f0aff..e9caf69 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -1179,15 +1179,10 @@ static void omap_hsmmc_detect(struct work_struct *work) carddetect = -ENOSYS; } - if (carddetect) { + if (carddetect) mmc_detect_change(host->mmc, (HZ * 200) / 1000); - } else { - mmc_host_enable(host->mmc); - omap_hsmmc_reset_controller_fsm(host, SRD); - mmc_host_lazy_disable(host->mmc); - + else mmc_detect_change(host->mmc, (HZ * 50) / 1000); - } } /* From patchwork Fri Jul 23 23:22:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Sin X-Patchwork-Id: 114029 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NN7Gnu030447 for ; Fri, 23 Jul 2010 23:07:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759322Ab0GWXHO (ORCPT ); Fri, 23 Jul 2010 19:07:14 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:33958 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759353Ab0GWXHN (ORCPT ); Fri, 23 Jul 2010 19:07:13 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6NN6oVL025954 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 23 Jul 2010 18:06:50 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6NN6ibQ017667; Fri, 23 Jul 2010 18:06:44 -0500 (CDT) Received: from localhost.localdomain (neo.am.dhcp.ti.com [128.247.75.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBDHgJP19206; Mon, 13 Dec 1915 12:42:19 -0500 (CDT) From: David Sin To: , , Tony Lindgren , Russell King Cc: Hari Kanigeri , Ohad Ben-Cohen , Vaibhav Hiremath , Santosh Shilimkar , Lajos Molnar , David Sin , Ravi Ramachandra Subject: [RFC 2/8] TILER-DMM: Container manager interface and utility definitons Date: Fri, 23 Jul 2010 18:22:22 -0500 Message-Id: <1279927348-21750-3-git-send-email-davidsin@ti.com> X-Mailer: git-send-email 1.6.6.2 In-Reply-To: <1279927348-21750-2-git-send-email-davidsin@ti.com> References: <1279927348-21750-1-git-send-email-davidsin@ti.com> <1279927348-21750-2-git-send-email-davidsin@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 23:07:17 +0000 (UTC) diff --git a/drivers/media/video/tiler/tcm.h b/drivers/media/video/tiler/tcm.h new file mode 100644 index 0000000..52a022a --- /dev/null +++ b/drivers/media/video/tiler/tcm.h @@ -0,0 +1,209 @@ +/* + * tcm.h + * + * TILER container manager specification and support functions for TI + * TILER driver. + * + * Author: Lajos Molnar + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef TCM_H +#define TCM_H + +struct tcm; + +/* point */ +struct tcm_pt { + u16 x; + u16 y; +}; + +/* 2d area */ +struct tcm_area { + struct tcm *tcm; /* parent */ + struct tcm_pt p0; + struct tcm_pt p1; +}; + +struct tcm { + u16 width, height; /* container dimensions */ + + /* 'pvt' structure shall contain any tcm details (attr) along with + linked list of allocated areas and mutex for mutually exclusive access + to the list. It may also contain copies of width and height to notice + any changes to the publicly available width and height fields. */ + void *pvt; + + /* function table */ + s32 (*reserve_2d)(struct tcm *tcm, u16 height, u16 width, u8 align, + struct tcm_area *area); + s32 (*free) (struct tcm *tcm, struct tcm_area *area); + void (*deinit) (struct tcm *tcm); +}; + +/*============================================================================= + BASIC TILER CONTAINER MANAGER INTERFACE +=============================================================================*/ + +/* + * NOTE: + * + * Since some basic parameter checking is done outside the TCM algorithms, + * TCM implementation do NOT have to check the following: + * + * area pointer is NULL + * width and height fits within container + * number of pages is more than the size of the container + * + */ + +/** + * Template for _tcm_init method. Define as: + * TCM_INIT(_tcm_init) + * + * Allocates and initializes a tiler container manager. + * + * @param width Width of container + * @param height Height of container + * @param attr Container manager specific configuration + * arguments. Please describe these in + * your header file. + * + * @return Pointer to the allocated and initialized container + * manager. NULL on failure. DO NOT leak any memory on + * failure! + */ +#define TCM_INIT(name, attr_t) \ +struct tcm *name(u16 width, u16 height, typeof(attr_t) *attr); + +/** + * Deinitialize tiler container manager. + * + * @param tcm Pointer to container manager. + * + * @return 0 on success, non-0 error value on error. The call + * should free as much memory as possible and meaningful + * even on failure. Some error codes: -ENODEV: invalid + * manager. + */ +static inline void tcm_deinit(struct tcm *tcm) +{ + if (tcm) + tcm->deinit(tcm); +} + +/** + * Reserves a 2D area in the container. + * + * @param tcm Pointer to container manager. + * @param height Height(in pages) of area to be reserved. + * @param width Width(in pages) of area to be reserved. + * @param align Alignment requirement for top-left corner of area. Not + * all values may be supported by the container manager, + * but it must support 0 (1), 32 and 64. + * 0 value is equivalent to 1. + * @param area Pointer to where the reserved area should be stored. + * + * @return 0 on success. Non-0 error code on failure. Also, + * the tcm field of the area will be set to NULL on + * failure. Some error codes: -ENODEV: invalid manager, + * -EINVAL: invalid area, -ENOMEM: not enough space for + * allocation. + */ +static inline s32 tcm_reserve_2d(struct tcm *tcm, u16 width, u16 height, + u16 align, struct tcm_area *area) +{ + /* perform rudimentary error checking */ + s32 res = (tcm == NULL ? -ENODEV : + (area == NULL || width == 0 || height == 0 || + /* align must be a 2 power */ + align & (align - 1)) ? -EINVAL : + (height > tcm->height || width > tcm->width) ? -ENOMEM : + tcm->reserve_2d(tcm, height, width, align, area)); + + if (area) + area->tcm = res ? NULL : tcm; + + return res; +} + +/** + * Free a previously reserved area from the container. + * + * @param area Pointer to area reserved by a prior call to tcm_reserve_2d call, + * whether it was successful or not. (Note: all fields of + * the structure must match.) + * + * @return 0 on success. Non-0 error code on failure. Also, the tcm + * field of the area is set to NULL on success to avoid subsequent + * freeing. This call will succeed even if supplying + * the area from a failed reserved call. + */ +static inline s32 tcm_free(struct tcm_area *area) +{ + s32 res = 0; /* free succeeds by default */ + + if (area && area->tcm) { + res = area->tcm->free(area->tcm, area); + if (res == 0) + area->tcm = NULL; + } + + return res; +} + +/*============================================================================= + HELPER FUNCTION FOR ANY TILER CONTAINER MANAGER +=============================================================================*/ + +/* Verify if a tcm area is logically valid */ +static inline bool tcm_area_is_valid(struct tcm_area *area) +{ + return area && area->tcm && + /* coordinate bounds */ + area->p1.x < area->tcm->width && + area->p1.y < area->tcm->height && + area->p0.y <= area->p1.y && + area->p0.x <= area->p1.x; +} + +/* see if a coordinate is within an area */ +static inline bool __tcm_is_in(struct tcm_pt *p, struct tcm_area *a) +{ + return p->x >= a->p0.x && p->x <= a->p1.x && + p->y >= a->p0.y && p->y <= a->p1.y; +} + +/* calculate area width */ +static inline u16 __tcm_area_width(struct tcm_area *area) +{ + return area->p1.x - area->p0.x + 1; +} + +/* calculate area height */ +static inline u16 __tcm_area_height(struct tcm_area *area) +{ + return area->p1.y - area->p0.y + 1; +} + +/* calculate number of slots in an area */ +static inline u16 __tcm_sizeof(struct tcm_area *area) +{ + return __tcm_area_width(area) * __tcm_area_height(area); +} +#define tcm_sizeof(area) __tcm_sizeof(&(area)) +#define tcm_awidth(area) __tcm_area_width(&(area)) +#define tcm_aheight(area) __tcm_area_height(&(area)) +#define tcm_is_in(pt, area) __tcm_is_in(&(pt), &(area)) + +#endif diff --git a/drivers/media/video/tiler/tcm/tcm-utils.h b/drivers/media/video/tiler/tcm/tcm-utils.h new file mode 100644 index 0000000..0d1260a --- /dev/null +++ b/drivers/media/video/tiler/tcm/tcm-utils.h @@ -0,0 +1,54 @@ +/* + * tcm_utils.h + * + * Utility functions for implementing TILER container managers. + * + * Author: Lajos Molnar + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef TCM_UTILS_H +#define TCM_UTILS_H + +#include "../tcm.h" + +/* TCM_ALG_NAME must be defined to use the debug methods */ + +#ifdef DEBUG +#define IFDEBUG(x) x +#else +/* compile-check debug statements even if not DEBUG */ +#define IFDEBUG(x) do { if (0) x; } while (0) +#endif + +#define P(level, fmt, ...) \ + IFDEBUG(printk(level TCM_ALG_NAME ":%d:%s()" fmt "\n", \ + __LINE__, __func__, ##__VA_ARGS__)) + +#define P1(fmt, ...) P(KERN_NOTICE, fmt, ##__VA_ARGS__) +#define P2(fmt, ...) P(KERN_INFO, fmt, ##__VA_ARGS__) +#define P3(fmt, ...) P(KERN_DEBUG, fmt, ##__VA_ARGS__) + +#define PA(level, msg, p_area) P##level(msg " (%03d %03d)-(%03d %03d)\n", \ + (p_area)->p0.x, (p_area)->p0.y, (p_area)->p1.x, (p_area)->p1.y) + +/* assign coordinates to area */ +static inline +void assign(struct tcm_area *a, u16 x0, u16 y0, u16 x1, u16 y1) +{ + a->p0.x = x0; + a->p0.y = y0; + a->p1.x = x1; + a->p1.y = y1; +} + +#endif From patchwork Sun Jul 25 17:05:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shishkin X-Patchwork-Id: 114146 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6PHPioD016295 for ; Sun, 25 Jul 2010 17:25:44 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751468Ab0GYRZn (ORCPT ); Sun, 25 Jul 2010 13:25:43 -0400 Received: from filtteri1.pp.htv.fi ([213.243.153.184]:60065 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750955Ab0GYRZm (ORCPT ); Sun, 25 Jul 2010 13:25:42 -0400 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id A2F2321B053; Sun, 25 Jul 2010 20:11:14 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp6.welho.com ([213.243.153.40]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id 4tgAvyLoj4bd; Sun, 25 Jul 2010 20:11:14 +0300 (EEST) Received: from ukko (cs27003010.pp.htv.fi [89.27.3.10]) by smtp6.welho.com (Postfix) with ESMTP id 4C33E5BC002; Sun, 25 Jul 2010 20:11:14 +0300 (EEST) Received: from ash by ukko with local (Exim 4.72) (envelope-from ) id 1Od4eo-0001yp-To; Sun, 25 Jul 2010 20:06:34 +0300 From: Alexander Shishkin To: linux-arm-kernel@lists.infradead.org Cc: Alexander Shishkin , Tony Lindgren , Russell King , Paul Walmsley , Santosh Shilimkar , Kevin Hilman , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] omap3: move EMU peripheral addresses to a platform header Date: Sun, 25 Jul 2010 20:05:18 +0300 Message-Id: <1280077520-7538-6-git-send-email-virtuoso@slind.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <13B9B4C6EF24D648824FF11BE896716203BADA0745@dlee02.ent.ti.com> References: <13B9B4C6EF24D648824FF11BE896716203BADA0745@dlee02.ent.ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 25 Jul 2010 17:25:44 +0000 (UTC) diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c index 9c442e2..6b41745 100644 --- a/arch/arm/mach-omap2/emu.c +++ b/arch/arm/mach-omap2/emu.c @@ -24,19 +24,13 @@ MODULE_LICENSE("GPL"); MODULE_AUTHOR("Alexander Shishkin"); -/* Cortex CoreSight components within omap3xxx EMU */ -#define ETM_BASE (L4_EMU_34XX_PHYS + 0x10000) -#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000) -#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000) -#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000) - static struct amba_device omap3_etb_device = { .dev = { .init_name = "etb", }, .res = { - .start = ETB_BASE, - .end = ETB_BASE + SZ_4K - 1, + .start = OMAP34XX_ETB_PHYS, + .end = OMAP34XX_ETB_PHYS + OMAP34XX_ETB_SIZE - 1, .flags = IORESOURCE_MEM, }, .periphid = 0x000bb907, @@ -47,8 +41,8 @@ static struct amba_device omap3_etm_device = { .init_name = "etm", }, .res = { - .start = ETM_BASE, - .end = ETM_BASE + SZ_4K - 1, + .start = OMAP34XX_ETM_PHYS, + .end = OMAP34XX_ETM_PHYS + OMAP34XX_ETM_SIZE - 1, .flags = IORESOURCE_MEM, }, .periphid = 0x102bb921, diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index 128b549..81f736a 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -185,6 +185,26 @@ /* 3430 IVA - currently unmapped */ +#define OMAP34XX_DBG_OFFSET (0x00011000) +#define OMAP34XX_DBG_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DBG_OFFSET) +#define OMAP34XX_DBG_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DBG_OFFSET) +#define OMAP34XX_DBG_SIZE SZ_4K + +#define OMAP34XX_ETM_OFFSET (0x00010000) +#define OMAP34XX_ETM_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETM_OFFSET) +#define OMAP34XX_ETM_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETM_OFFSET) +#define OMAP34XX_ETM_SIZE SZ_4K + +#define OMAP34XX_ETB_OFFSET (0x0001b000) +#define OMAP34XX_ETB_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETB_OFFSET) +#define OMAP34XX_ETB_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETB_OFFSET) +#define OMAP34XX_ETB_SIZE SZ_4K + +#define OMAP34XX_DAP_OFFSET (0x0001d000) +#define OMAP34XX_DAP_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DAP_OFFSET) +#define OMAP34XX_DAP_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DAP_OFFSET) +#define OMAP34XX_DAP_SIZE SZ_4K + /* * ---------------------------------------------------------------------------- * Omap4 specific IO mapping From patchwork Sun Jul 25 17:05:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shishkin X-Patchwork-Id: 114147 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6PHPjkk016303 for ; Sun, 25 Jul 2010 17:25:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751206Ab0GYRZn (ORCPT ); Sun, 25 Jul 2010 13:25:43 -0400 Received: from filtteri1.pp.htv.fi ([213.243.153.184]:60078 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750995Ab0GYRZm (ORCPT ); Sun, 25 Jul 2010 13:25:42 -0400 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id 7941021B057; Sun, 25 Jul 2010 20:11:24 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id cQiwfE3IzN7F; Sun, 25 Jul 2010 20:11:24 +0300 (EEST) Received: from ukko (cs27003010.pp.htv.fi [89.27.3.10]) by smtp5.welho.com (Postfix) with ESMTP id 229B45BC005; Sun, 25 Jul 2010 20:11:24 +0300 (EEST) Received: from ash by ukko with local (Exim 4.72) (envelope-from ) id 1Od4ey-0001yv-OO; Sun, 25 Jul 2010 20:06:44 +0300 From: Alexander Shishkin To: linux-arm-kernel@lists.infradead.org Cc: Alexander Shishkin , Tony Lindgren , Russell King , Paul Walmsley , Kevin Hilman , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] omap3: make coresight register save across OFF modes a sysfs option Date: Sun, 25 Jul 2010 20:05:20 +0300 Message-Id: <1280077520-7538-8-git-send-email-virtuoso@slind.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <13B9B4C6EF24D648824FF11BE896716203BADA0745@dlee02.ent.ti.com> References: <13B9B4C6EF24D648824FF11BE896716203BADA0745@dlee02.ent.ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 25 Jul 2010 17:25:45 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index f5b4ff4..3a64ce4 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -49,6 +49,7 @@ ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o +obj-$(CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG) += debug34xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 diff --git a/arch/arm/mach-omap2/debug34xx.c b/arch/arm/mach-omap2/debug34xx.c new file mode 100644 index 0000000..698e83a --- /dev/null +++ b/arch/arm/mach-omap2/debug34xx.c @@ -0,0 +1,66 @@ +/* + * Control saving and restoring of coresight components' state during + * OFF mode. + * + * Copyright (C) 2010 Nokia Corporation + * Alexander Shishkin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include "pm.h" + +/* + * Pointer to a place in sram where the ETM/debug state save + * flag is. It can be calculated after the omap_sram_idle is + * pushed to sram. + */ +static unsigned int *_etm_save; + +/* + * sysfs file /sys/power/coresight_save controls whether the + * state of coresight components should be saved and restored + * across OFF modes. + */ +static ssize_t coresight_save_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", *_etm_save); +} + +static ssize_t coresight_save_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned int value; + + if (sscanf(buf, "%u", &value) != 1) + return -EINVAL; + + *_etm_save = !!value; + + return n; +} + +static struct kobj_attribute coresight_save_attr = + __ATTR(coresight_save, 0644, coresight_save_show, coresight_save_store); + +int omap3_coresight_pm_init(void *sram_addr) +{ + int ret; + + /* the last word from the top of omap_sram_idle */ + _etm_save = (unsigned *)((u8 *)sram_addr + omap34xx_cpu_suspend_sz - 4); + + ret = sysfs_create_file(power_kobj, &coresight_save_attr.attr); + + return ret; +} + diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 3de6ece..0321834 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -76,6 +76,12 @@ extern void omap34xx_cpu_suspend(u32 *addr, int save_state); extern void save_secure_ram_context(u32 *addr); extern void omap3_save_scratchpad_contents(void); +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG +int omap3_coresight_pm_init(void *sram_addr); +#else +#define omap3_coresight_pm_init(x) do {} while (0) +#endif + extern unsigned int omap24xx_idle_loop_suspend_sz; extern unsigned int omap34xx_suspend_sz; extern unsigned int save_secure_ram_context_sz; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index fb4994a..c389e65 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -1096,6 +1096,9 @@ static int __init omap3_pm_init(void) core_clkdm = clkdm_lookup("core_clkdm"); omap_push_sram_idle(); + + omap3_coresight_pm_init(_omap_sram_idle); + #ifdef CONFIG_SUSPEND suspend_set_ops(&omap_pm_ops); #endif /* CONFIG_SUSPEND */ From patchwork Tue May 18 23:46:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 100641 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4INl140020435 for ; Tue, 18 May 2010 23:47:01 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754785Ab0ERXq7 (ORCPT ); Tue, 18 May 2010 19:46:59 -0400 Received: from mail-gw0-f46.google.com ([74.125.83.46]:47856 "EHLO mail-gw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752565Ab0ERXq6 (ORCPT ); Tue, 18 May 2010 19:46:58 -0400 Received: by gwaa20 with SMTP id a20so1475503gwa.19 for ; Tue, 18 May 2010 16:46:57 -0700 (PDT) Received: by 10.101.136.9 with SMTP id o9mr8830383ann.103.1274226417252; Tue, 18 May 2010 16:46:57 -0700 (PDT) Received: from localhost (deeprootsystems.com [216.254.16.51]) by mx.google.com with ESMTPS id m39sm4859657ann.11.2010.05.18.16.46.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 18 May 2010 16:46:56 -0700 (PDT) From: Kevin Hilman To: linux-input@vger.kernel.org Cc: linux-omap@vger.kernel.org, Dmitry Torokhov , Michael Roth , Pavel Machek , Andrew Morton , Mike Frysinger , linux-kernel@vger.kernel.org Subject: [PATCH] touchscreen: ads7846: please don't touch free'd memory Date: Tue, 18 May 2010 16:46:53 -0700 Message-Id: <1274226413-8520-1-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.7.0.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 18 May 2010 23:47:01 +0000 (UTC) diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c index 532279c..1da2369 100644 --- a/drivers/input/touchscreen/ads7846.c +++ b/drivers/input/touchscreen/ads7846.c @@ -815,6 +815,9 @@ static int ads7846_suspend(struct spi_device *spi, pm_message_t message) { struct ads7846 *ts = dev_get_drvdata(&spi->dev); + if (WARN_ON_ONCE(!ts)) + return 0; + spin_lock_irq(&ts->lock); ts->is_suspended = 1; @@ -833,6 +836,9 @@ static int ads7846_resume(struct spi_device *spi) { struct ads7846 *ts = dev_get_drvdata(&spi->dev); + if (WARN_ON_ONCE(!ts)) + return 0; + if (device_may_wakeup(&ts->spi->dev)) disable_irq_wake(ts->spi->irq); @@ -1231,6 +1237,7 @@ static int __devinit ads7846_probe(struct spi_device *spi) input_free_device(input_dev); kfree(packet); kfree(ts); + dev_set_drvdata(&spi->dev, NULL); return err; } @@ -1240,6 +1247,9 @@ static int __devexit ads7846_remove(struct spi_device *spi) device_init_wakeup(&spi->dev, false); + if (WARN_ON_ONCE(!ts)) + return 0; + ads784x_hwmon_unregister(spi, ts); input_unregister_device(ts->input); From patchwork Fri Jul 23 23:22:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Sin X-Patchwork-Id: 114028 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NN7F56030439 for ; Fri, 23 Jul 2010 23:07:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759486Ab0GWXHN (ORCPT ); Fri, 23 Jul 2010 19:07:13 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:53209 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759171Ab0GWXHM (ORCPT ); Fri, 23 Jul 2010 19:07:12 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6NN6qMD012196 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 23 Jul 2010 18:06:52 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6NN6o4d007397; Fri, 23 Jul 2010 18:06:50 -0500 (CDT) Received: from localhost.localdomain (neo.am.dhcp.ti.com [128.247.75.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBDHgOP19215; Mon, 13 Dec 1915 12:42:24 -0500 (CDT) From: David Sin To: , , Tony Lindgren , Russell King Cc: Hari Kanigeri , Ohad Ben-Cohen , Vaibhav Hiremath , Santosh Shilimkar , Lajos Molnar , David Sin Subject: [RFC 4/8] TILER-DMM: TILER Memory Manager interface and implementation Date: Fri, 23 Jul 2010 18:22:24 -0500 Message-Id: <1279927348-21750-5-git-send-email-davidsin@ti.com> X-Mailer: git-send-email 1.6.6.2 In-Reply-To: <1279927348-21750-4-git-send-email-davidsin@ti.com> References: <1279927348-21750-1-git-send-email-davidsin@ti.com> <1279927348-21750-2-git-send-email-davidsin@ti.com> <1279927348-21750-3-git-send-email-davidsin@ti.com> <1279927348-21750-4-git-send-email-davidsin@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 23:07:15 +0000 (UTC) diff --git a/drivers/media/video/tiler/tmm-pat.c b/drivers/media/video/tiler/tmm-pat.c new file mode 100644 index 0000000..ccd32b4 --- /dev/null +++ b/drivers/media/video/tiler/tmm-pat.c @@ -0,0 +1,274 @@ +/* + * tmm-pat.c + * + * DMM driver support functions for TI TILER hardware block. + * + * Authors: Lajos Molnar + * David Sin + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tmm.h" + +/* Page size granularity can be 4k, 16k, or 64k */ +#define DMM_PAGE 0x1000 + +/* Memory limit to cache free pages. TILER will eventually use this much */ +static u32 cache_limit = CONFIG_TILER_CACHE_LIMIT << 20; +module_param_named(cache, cache_limit, uint, 0644); +MODULE_PARM_DESC(cache, "Cache free pages if total memory is under this limit"); + +/* global state - statically initialized */ +static LIST_HEAD(free_list); /* page cache: list of free pages */ +static u32 total_mem; /* total memory allocated (free & used) */ +static u32 refs; /* number of tmm_pat instances */ +static DEFINE_MUTEX(mtx); /* global mutex */ + +/* The page struct pointer and physical address of each page.*/ +struct mem { + struct list_head list; + struct page *pg; /* page struct */ + u32 pa; /* physical address */ +}; + +/* Used to keep track of mem per tmm_pat_get_pages call */ +struct fast { + struct list_head list; + struct mem **mem; /* array of page info */ + u32 *pa; /* array of physical addresses */ + u32 num; /* number of pages */ +}; + +/* TMM PAT private structure */ +struct dmm_mem { + struct list_head fast_list; + struct dmm *dmm; +}; + +/** + * Frees pages in a fast structure. Moves pages to the free list if there + * are less pages used than max_to_keep. Otherwise, it frees the pages + */ +static void free_fast(struct fast *f) +{ + s32 i = 0; + + /* mutex is locked */ + for (i = 0; i < f->num; i++) { + if (total_mem < cache_limit) { + /* cache free page if under the limit */ + list_add(&f->mem[i]->list, &free_list); + } else { + /* otherwise, free */ + total_mem -= PAGE_SIZE; + __free_page(f->mem[i]->pg); + } + } + kfree(f->pa); + kfree(f->mem); + /* remove only if element was added */ + if (f->list.next) + list_del(&f->list); + kfree(f); +} + +/* allocate and flush a page */ +static struct mem *alloc_mem(void) +{ + struct mem *m = kzalloc(sizeof(*m), GFP_KERNEL); + if (!m) + return NULL; + + m->pg = alloc_page(GFP_KERNEL | GFP_DMA); + if (!m->pg) { + kfree(m); + return NULL; + } + + m->pa = page_to_phys(m->pg); + + /* flush the cache entry for each page we allocate. */ + dmac_flush_range(page_address(m->pg), + page_address(m->pg) + PAGE_SIZE); + outer_flush_range(m->pa, m->pa + PAGE_SIZE); + + return m; +} + +static void free_page_cache(void) +{ + struct mem *m, *m_; + + /* mutex is locked */ + list_for_each_entry_safe(m, m_, &free_list, list) { + __free_page(m->pg); + total_mem -= PAGE_SIZE; + list_del(&m->list); + kfree(m); + } +} + +static void tmm_pat_deinit(struct tmm *tmm) +{ + struct fast *f, *f_; + struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt; + + mutex_lock(&mtx); + + /* free all outstanding used memory */ + list_for_each_entry_safe(f, f_, &pvt->fast_list, list) + free_fast(f); + + /* if this is the last tmm_pat, free all memory */ + if (--refs == 0) + free_page_cache(); + + mutex_unlock(&mtx); +} + +static u32 *tmm_pat_get_pages(struct tmm *tmm, u32 n) +{ + struct mem *m; + struct fast *f; + struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt; + + f = kzalloc(sizeof(*f), GFP_KERNEL); + if (!f) + return NULL; + + /* array of mem struct pointers */ + f->mem = kzalloc(n * sizeof(*f->mem), GFP_KERNEL); + + /* array of physical addresses */ + f->pa = kzalloc(n * sizeof(*f->pa), GFP_KERNEL); + + /* no pages have been allocated yet (needed for cleanup) */ + f->num = 0; + + if (!f->mem || !f->pa) + goto cleanup; + + /* fill out fast struct mem array with free pages */ + mutex_lock(&mtx); + while (f->num < n) { + /* if there is a free cached page use it */ + if (!list_empty(&free_list)) { + /* unbind first element from list */ + m = list_first_entry(&free_list, typeof(*m), list); + list_del(&m->list); + } else { + mutex_unlock(&mtx); + + /** + * Unlock mutex during allocation and cache flushing. + */ + m = alloc_mem(); + if (!m) + goto cleanup; + + mutex_lock(&mtx); + total_mem += PAGE_SIZE; + } + + f->mem[f->num] = m; + f->pa[f->num++] = m->pa; + } + + list_add(&f->list, &pvt->fast_list); + mutex_unlock(&mtx); + return f->pa; + +cleanup: + free_fast(f); + return NULL; +} + +static void tmm_pat_free_pages(struct tmm *tmm, u32 *page_list) +{ + struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt; + struct fast *f, *f_; + + mutex_lock(&mtx); + /* find fast struct based on 1st page */ + list_for_each_entry_safe(f, f_, &pvt->fast_list, list) { + if (f->pa[0] == page_list[0]) { + free_fast(f); + break; + } + } + mutex_unlock(&mtx); +} + +static s32 tmm_pat_map(struct tmm *tmm, struct pat_area area, u32 page_pa) +{ + struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt; + struct pat pat_desc = {0}; + + /* send pat descriptor to dmm driver */ + pat_desc.ctrl.dir = 0; + pat_desc.ctrl.ini = 0; + pat_desc.ctrl.lut_id = 0; + pat_desc.ctrl.start = 1; + pat_desc.ctrl.sync = 0; + pat_desc.area = area; + pat_desc.next = NULL; + + /* must be a 16-byte aligned physical address */ + pat_desc.data = page_pa; + return dmm_pat_refill(pvt->dmm, &pat_desc, MANUAL); +} + +struct tmm *tmm_pat_init(u32 pat_id) +{ + struct tmm *tmm = NULL; + struct dmm_mem *pvt = NULL; + + struct dmm *dmm = dmm_pat_init(pat_id); + if (dmm) + tmm = kzalloc(sizeof(*tmm), GFP_KERNEL); + if (tmm) + pvt = kzalloc(sizeof(*pvt), GFP_KERNEL); + if (pvt) { + /* private data */ + pvt->dmm = dmm; + INIT_LIST_HEAD(&pvt->fast_list); + + /* increate tmm_pat references */ + mutex_lock(&mtx); + refs++; + mutex_unlock(&mtx); + + /* public data */ + tmm->pvt = pvt; + tmm->deinit = tmm_pat_deinit; + tmm->get = tmm_pat_get_pages; + tmm->free = tmm_pat_free_pages; + tmm->map = tmm_pat_map; + tmm->clear = NULL; /* not yet supported */ + + return tmm; + } + + kfree(pvt); + kfree(tmm); + dmm_pat_release(dmm); + return NULL; +} +EXPORT_SYMBOL(tmm_pat_init); diff --git a/drivers/media/video/tiler/tmm.h b/drivers/media/video/tiler/tmm.h new file mode 100644 index 0000000..fbdc1e2 --- /dev/null +++ b/drivers/media/video/tiler/tmm.h @@ -0,0 +1,109 @@ +/* + * tmm.h + * + * TMM interface definition for TI TILER driver. + * + * Author: Lajos Molnar + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef TMM_H +#define TMM_H + +#include +/** + * TMM interface + */ +struct tmm { + void *pvt; + + /* function table */ + u32 *(*get) (struct tmm *tmm, u32 num_pages); + void (*free) (struct tmm *tmm, u32 *pages); + s32 (*map) (struct tmm *tmm, struct pat_area area, u32 page_pa); + void (*clear) (struct tmm *tmm, struct pat_area area); + void (*deinit) (struct tmm *tmm); +}; + +/** + * Request a set of pages from the DMM free page stack. + * @return a pointer to a list of physical page addresses. + */ +static inline +u32 *tmm_get(struct tmm *tmm, u32 num_pages) +{ + if (tmm && tmm->pvt) + return tmm->get(tmm, num_pages); + return NULL; +} + +/** + * Return a set of used pages to the DMM free page stack. + * @param list a pointer to a list of physical page addresses. + */ +static inline +void tmm_free(struct tmm *tmm, u32 *pages) +{ + if (tmm && tmm->pvt) + tmm->free(tmm, pages); +} + +/** + * Program the physical address translator. + * @param area PAT area + * @param list of pages + */ +static inline +s32 tmm_map(struct tmm *tmm, struct pat_area area, u32 page_pa) +{ + if (tmm && tmm->map && tmm->pvt) + return tmm->map(tmm, area, page_pa); + return -ENODEV; +} + +/** + * Clears the physical address translator. + * @param area PAT area + */ +static inline +void tmm_clear(struct tmm *tmm, struct pat_area area) +{ + if (tmm && tmm->clear && tmm->pvt) + tmm->clear(tmm, area); +} + +/** + * Checks whether tiler memory manager supports mapping + */ +static inline +bool tmm_can_map(struct tmm *tmm) +{ + return tmm && tmm->map; +} + +/** + * Deinitialize tiler memory manager + */ +static inline +void tmm_deinit(struct tmm *tmm) +{ + if (tmm && tmm->pvt) + tmm->deinit(tmm); +} + +/** + * TMM implementation for PAT support. + * + * Initialize TMM for PAT with given id. + */ +struct tmm *tmm_pat_init(u32 pat_id); + +#endif From patchwork Mon Jun 21 18:42:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 107236 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5LIh1FH016035 for ; Mon, 21 Jun 2010 18:43:02 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754741Ab0FUSm6 (ORCPT ); Mon, 21 Jun 2010 14:42:58 -0400 Received: from smtp.nokia.com ([192.100.122.230]:32718 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752441Ab0FUSm6 (ORCPT ); Mon, 21 Jun 2010 14:42:58 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o5LIgV7x006971; Mon, 21 Jun 2010 21:42:44 +0300 Received: from vaepf101.NOE.Nokia.com ([10.160.244.86]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 21 Jun 2010 21:42:41 +0300 Received: from [10.162.252.10] ([10.162.252.10]) by vaepf101.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 21 Jun 2010 21:42:41 +0300 Message-ID: <4C1FB2A0.6000503@nokia.com> Date: Mon, 21 Jun 2010 21:42:40 +0300 From: Adrian Hunter User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: kishore kadiyala CC: "linux-mmc@vger.kernel.org" , "linux-omap@vger.kernel.org" , "tony@atomide.com" , "madhu.cr@ti.com" , "akpm@linux-foundation.org" Subject: Re: [PATCH v5 2/2] OMAP4 HSMMC: Adding card detect support for MMC1 Controller References: <43584.10.24.255.17.1276788439.squirrel@dbdmail.itg.ti.com> In-Reply-To: <43584.10.24.255.17.1276788439.squirrel@dbdmail.itg.ti.com> X-OriginalArrivalTime: 21 Jun 2010 18:42:41.0620 (UTC) FILETIME=[87B8C140:01CB1171] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 21 Jun 2010 18:43:02 +0000 (UTC) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index e9caf69..f792cff 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -465,8 +465,6 @@ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) int ret; if (gpio_is_valid(pdata->slots[0].switch_pin)) { - pdata->suspend = omap_hsmmc_suspend_cdirq; - pdata->resume = omap_hsmmc_resume_cdirq; if (pdata->slots[0].cover) pdata->slots[0].get_cover_state = omap_hsmmc_get_cover_state; @@ -2160,6 +2158,8 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) "Unable to grab MMC CD IRQ\n"); goto err_irq_cd; } + pdata->suspend = omap_hsmmc_suspend_cdirq; + pdata->resume = omap_hsmmc_resume_cdirq; } OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); From patchwork Mon Jun 21 19:36:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Uribe de Leon, Armando" X-Patchwork-Id: 107238 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5LJaAUL029925 for ; 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Mon, 21 Jun 2010 14:36:02 -0500 From: "Uribe de Leon, Armando" To: "linux-omap@vger.kernel.org" CC: "felipe.contreras@nokia.com" , "ameya.palande@nokia.com" , "hiroshi.doyu@nokia.com" Date: Mon, 21 Jun 2010 14:36:02 -0500 Subject: [PATCH] DSPBRIDGE: decrease message pending in case of timeout Thread-Topic: [PATCH] DSPBRIDGE: decrease message pending in case of timeout Thread-Index: AcsRePtizamVBcLlR1SvQ/60a+AQAQ== Message-ID: <67059DBF19D7214F9C66BB0EA91BA90EC32E9FCC@dlee04.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 21 Jun 2010 19:36:10 +0000 (UTC) diff --git a/drivers/dsp/bridge/wmd/msg_sm.c b/drivers/dsp/bridge/wmd/msg_sm.c index b505c5e..d56b46b 100644 --- a/drivers/dsp/bridge/wmd/msg_sm.c +++ b/drivers/dsp/bridge/wmd/msg_sm.c @@ -446,12 +446,16 @@ int bridge_msg_put(struct msg_queue *msg_queue_obj, syncs[1] = msg_queue_obj->sync_done; status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index); - if (DSP_FAILED(status)) - goto func_end; /* Enter critical section */ spin_lock_bh(&hmsg_mgr->msg_mgr_lock); + msg_queue_obj->io_msg_pend--; + + if (DSP_FAILED(status)) { + spin_unlock_bh(&hmsg_mgr->msg_mgr_lock); + goto func_end; + } + if (msg_queue_obj->done) { - msg_queue_obj->io_msg_pend--; /* Exit critical section */ spin_unlock_bh(&hmsg_mgr->msg_mgr_lock); /* Signal that we're not going to access msg_queue_obj @@ -484,7 +488,6 @@ int bridge_msg_put(struct msg_queue *msg_queue_obj, From patchwork Thu Aug 5 22:24:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117581 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75MgU7I029854 for ; Thu, 5 Aug 2010 22:42:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761042Ab0HEWle (ORCPT ); Thu, 5 Aug 2010 18:41:34 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:57514 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760829Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOIOA032460 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:18 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o75MOFWf002380; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOFf27278; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 21308C265; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 11/12] omap3: sr: sr_exit should be static Date: Thu, 5 Aug 2010 17:24:11 -0500 Message-Id: <1281047052-21346-12-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:42:31 +0000 (UTC) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 9b5a10e..a723ac7 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -968,7 +968,7 @@ static int __init sr_init(void) return 0; } -void __exit sr_exit(void) +static void __exit sr_exit(void) { platform_driver_unregister(&smartreflex_driver); } From patchwork Thu Aug 5 22:24:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 117580 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75MgU7H029854 for ; Thu, 5 Aug 2010 22:42:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761015Ab0HEWld (ORCPT ); Thu, 5 Aug 2010 18:41:33 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:57513 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760828Ab0HEWYU (ORCPT ); Thu, 5 Aug 2010 18:24:20 -0400 Received: from dflp52.itg.ti.com ([128.247.22.96]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o75MOIEl032461 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 5 Aug 2010 17:24:18 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dflp52.itg.ti.com (8.13.7/8.13.7) with ESMTP id o75MOFUf026057; Thu, 5 Aug 2010 17:24:16 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o75MOFf27274; Thu, 5 Aug 2010 17:24:15 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 1AFD9C263; Thu, 5 Aug 2010 17:24:13 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Thara Gopinath Subject: [PM-SR][PATCH 08/12] omap3: sr: cleanup pr_xxx Date: Thu, 5 Aug 2010 17:24:08 -0500 Message-Id: <1281047052-21346-9-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1281047052-21346-1-git-send-email-nm@ti.com> References: <1281047052-21346-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:42:30 +0000 (UTC) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 57fc9b2..d63691b 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -804,8 +804,9 @@ static int omap_sr_params_store(void *data, u64 val) u32 *option = data; *option = val; } else { - pr_notice("DEBUG option not enabled!\n \ - echo 1 > pm_debug/enable_sr_vp_debug - to enable\n"); + pr_notice("%s: DEBUG option not enabled! " + "echo 1 > pm_debug/enable_sr_vp_debug to enable\n", + __func__); } return 0; } From patchwork Wed Jul 28 14:45:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114784 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SEg4wB011700 for ; Wed, 28 Jul 2010 14:42:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755246Ab0G1OlK (ORCPT ); Wed, 28 Jul 2010 10:41:10 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:35275 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754864Ab0G1OlH (ORCPT ); Wed, 28 Jul 2010 10:41:07 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SEekvC031472 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 09:40:46 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6SEei7O010946; Wed, 28 Jul 2010 09:40:45 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SEehVN016736; Wed, 28 Jul 2010 09:40:44 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH 06/10] staging:ti dspbridge: remove DSP_FAILED macro from core Date: Wed, 28 Jul 2010 09:45:29 -0500 Message-Id: <1280328333-31336-7-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 In-Reply-To: <1280328333-31336-6-git-send-email-ernesto@ti.com> References: <1280328333-31336-1-git-send-email-ernesto@ti.com> <1280328333-31336-2-git-send-email-ernesto@ti.com> <1280328333-31336-3-git-send-email-ernesto@ti.com> <1280328333-31336-4-git-send-email-ernesto@ti.com> <1280328333-31336-5-git-send-email-ernesto@ti.com> <1280328333-31336-6-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 14:42:04 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 1b23141..bee2b23 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -135,7 +135,7 @@ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *host_buf, if (!dev_ctxt) status = -EFAULT; - if (DSP_FAILED(status)) + if (status) goto func_end; if (pchnl->chnl_type == CHNL_PCPY && pchnl->chnl_id > 1 && host_buf) { @@ -266,7 +266,7 @@ int bridge_chnl_cancel_io(struct chnl_object *chnl_obj) } else { status = -EFAULT; } - if (DSP_FAILED(status)) + if (status) goto func_end; /* Mark this channel as cancelled, to prevent further IORequests or @@ -372,7 +372,7 @@ func_cont: kfree(pchnl); pchnl = NULL; } - DBC_ENSURE(DSP_FAILED(status) || !pchnl); + DBC_ENSURE(status || !pchnl); return status; } @@ -428,7 +428,7 @@ int bridge_chnl_create(struct chnl_mgr **channel_mgr, status = -ENOMEM; } - if (DSP_FAILED(status)) { + if (status) { bridge_chnl_destroy(chnl_mgr_obj); *channel_mgr = NULL; } else { @@ -456,7 +456,7 @@ int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr) status = bridge_chnl_close(chnl_mgr_obj->ap_channel [chnl_id]); - if (DSP_FAILED(status)) + if (status) dev_dbg(bridge, "%s: Error status 0x%x\n", __func__, status); } @@ -509,7 +509,7 @@ int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 timeout) while (!LST_IS_EMPTY(pchnl->pio_requests) && !status) { status = bridge_chnl_get_ioc(chnl_obj, timeout, &chnl_ioc_obj); - if (DSP_FAILED(status)) + if (status) continue; if (chnl_ioc_obj.status & CHNL_IOCSTATTIMEOUT) @@ -522,7 +522,7 @@ int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 timeout) pchnl->dw_state &= ~CHNL_STATECANCEL; } } - DBC_ENSURE(DSP_FAILED(status) || LST_IS_EMPTY(pchnl->pio_requests)); + DBC_ENSURE(status || LST_IS_EMPTY(pchnl->pio_requests)); return status; } @@ -592,7 +592,7 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout, if (!dev_ctxt) status = -EFAULT; - if (DSP_FAILED(status)) + if (status) goto func_end; ioc.status = CHNL_IOCSTATCOMPLETE; @@ -806,7 +806,7 @@ int bridge_chnl_open(struct chnl_object **chnl, } } } - if (DSP_FAILED(status)) + if (status) goto func_end; DBC_ASSERT(ch_id < chnl_mgr_obj->max_channels); @@ -860,7 +860,7 @@ int bridge_chnl_open(struct chnl_object **chnl, } } - if (DSP_FAILED(status)) { + if (status) { /* Free memory */ if (pchnl->pio_completions) { free_chirp_list(pchnl->pio_completions); diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 1d433a9..02c660d 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -242,7 +242,7 @@ int bridge_io_create(struct io_mgr **io_man, status = -EIO; } func_end: - if (DSP_FAILED(status)) { + if (status) { /* Cleanup */ bridge_io_destroy(pio_mgr); if (io_man) @@ -357,13 +357,13 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) /* Get start and length of channel part of shared memory */ status = cod_get_sym_value(cod_man, CHNL_SHARED_BUFFER_BASE_SYM, &ul_shm_base); - if (DSP_FAILED(status)) { + if (status) { status = -EFAULT; goto func_end; } status = cod_get_sym_value(cod_man, CHNL_SHARED_BUFFER_LIMIT_SYM, &ul_shm_limit); - if (DSP_FAILED(status)) { + if (status) { status = -EFAULT; goto func_end; } @@ -414,18 +414,18 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) status = cod_get_sym_value(cod_man, SHM0_SHARED_END_SYM, &shm0_end); #endif - if (DSP_FAILED(status)) + if (status) status = -EFAULT; } if (!status) { status = cod_get_sym_value(cod_man, DYNEXTBASE, &ul_dyn_ext_base); - if (DSP_FAILED(status)) + if (status) status = -EFAULT; } if (!status) { status = cod_get_sym_value(cod_man, EXTEND, &ul_ext_end); - if (DSP_FAILED(status)) + if (status) status = -EFAULT; } if (!status) { @@ -469,7 +469,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) status = -ENOMEM; } } - if (DSP_FAILED(status)) + if (status) goto func_end; pa_curr = ul_gpp_pa; @@ -508,7 +508,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) pa_curr, va_curr, page_size[i], map_attrs, NULL); - if (DSP_FAILED(status)) + if (status) goto func_end; pa_curr += page_size[i]; va_curr += page_size[i]; @@ -581,7 +581,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) ae_proc[ndx].ul_gpp_va, ae_proc[ndx].ul_dsp_va * hio_mgr->word_size, page_size[i]); - if (DSP_FAILED(status)) + if (status) goto func_end; } pa_curr += page_size[i]; @@ -645,7 +645,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) NULL); } } - if (DSP_FAILED(status)) + if (status) goto func_end; } @@ -662,7 +662,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) (hio_mgr->hbridge_context, l4_peripheral_table[i].phys_addr, l4_peripheral_table[i].dsp_virt_addr, HW_PAGE_SIZE4KB, map_attrs, NULL); - if (DSP_FAILED(status)) + if (status) goto func_end; i++; } @@ -707,7 +707,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) hio_mgr->intf_fxns->pfn_dev_cntrl(hio_mgr->hbridge_context, BRDIOCTL_SETMMUCONFIG, ae_proc); - if (DSP_FAILED(status)) + if (status) goto func_end; ul_shm_base = hio_mgr->ext_proc_info.ty_tlb[0].ul_gpp_phys; ul_shm_base += ul_shm_base_offset; @@ -756,7 +756,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) /* Get the start address of trace buffer */ status = cod_get_sym_value(cod_man, SYS_PUTCBEG, &hio_mgr->ul_trace_buffer_begin); - if (DSP_FAILED(status)) { + if (status) { status = -EFAULT; goto func_end; } @@ -767,7 +767,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) /* Get the end address of trace buffer */ status = cod_get_sym_value(cod_man, SYS_PUTCEND, &hio_mgr->ul_trace_buffer_end); - if (DSP_FAILED(status)) { + if (status) { status = -EFAULT; goto func_end; } @@ -777,7 +777,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) /* Get the current address of DSP write pointer */ status = cod_get_sym_value(cod_man, BRIDGE_SYS_PUTC_CURRENT, &hio_mgr->ul_trace_buffer_current); - if (DSP_FAILED(status)) { + if (status) { status = -EFAULT; goto func_end; } @@ -852,7 +852,7 @@ static void io_dispatch_pm(struct io_mgr *pio_mgr) status = pio_mgr->intf_fxns-> pfn_dev_cntrl(pio_mgr->hbridge_context, BRDIOCTL_PWR_HIBERNATE, parg); - if (DSP_FAILED(status)) + if (status) pr_err("%s: hibernate cmd failed 0x%x\n", __func__, status); } else if (parg[0] == MBX_PM_OPP_REQ) { @@ -861,16 +861,16 @@ static void io_dispatch_pm(struct io_mgr *pio_mgr) status = pio_mgr->intf_fxns-> pfn_dev_cntrl(pio_mgr->hbridge_context, BRDIOCTL_CONSTRAINT_REQUEST, parg); - if (DSP_FAILED(status)) + if (status) dev_dbg(bridge, "PM: Failed to set constraint " - "= 0x%x \n", parg[1]); + "= 0x%x\n", parg[1]); } else { dev_dbg(bridge, "PM: clk control value of msg = 0x%x\n", parg[0]); status = pio_mgr->intf_fxns-> pfn_dev_cntrl(pio_mgr->hbridge_context, BRDIOCTL_CLK_CTRL, parg); - if (DSP_FAILED(status)) + if (status) dev_dbg(bridge, "PM: Failed to ctrl the DSP clk" "= 0x%x\n", *parg); } @@ -1849,7 +1849,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context) status = cod_get_sym_value(cod_mgr, COD_TRACECURPOS, &trace_cur_pos); - if (DSP_FAILED(status)) + if (status) goto func_end; ul_num_bytes = (ul_trace_end - ul_trace_begin); @@ -1857,7 +1857,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context) ul_num_words = ul_num_bytes * ul_word_size; status = dev_get_intf_fxns(dev_obj, &intf_fxns); - if (DSP_FAILED(status)) + if (status) goto func_end; psz_buf = kzalloc(ul_num_bytes + 2, GFP_ATOMIC); @@ -1867,7 +1867,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context) (u8 *)psz_buf, (u32)ul_trace_begin, ul_num_bytes, 0); - if (DSP_FAILED(status)) + if (status) goto func_end; /* Pack and do newline conversion */ @@ -1881,7 +1881,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context) status = (*intf_fxns->pfn_brd_read)(pbridge_context, (u8 *)&trace_cur_pos, (u32)trace_cur_pos, 4, 0); - if (DSP_FAILED(status)) + if (status) goto func_end; /* Pack and do newline conversion */ pr_info("DSP Trace Buffer Begin:\n" @@ -1967,7 +1967,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context) status = -ENOMEM; } func_end: - if (DSP_FAILED(status)) + if (status) dev_dbg(bridge, "%s Failed, status 0x%x\n", __func__, status); return status; } @@ -2025,7 +2025,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context) cod_get_sym_value(code_mgr, COD_TRACEBEG, &trace_begin); pr_debug("%s: trace_begin Value 0x%x\n", __func__, trace_begin); - if (DSP_FAILED(status)) + if (status) pr_debug("%s: Failed on cod_get_sym_value.\n", __func__); } @@ -2049,7 +2049,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context) (u8 *)&mmu_fault_dbg_info, (u32)trace_begin, sizeof(mmu_fault_dbg_info), 0); - if (DSP_FAILED(status)) + if (status) break; poll_cnt++; @@ -2084,7 +2084,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context) status = (*intf_fxns->pfn_brd_read)(bridge_context, (u8 *)buffer, (u32)trace_begin, total_size, 0); - if (DSP_FAILED(status)) { + if (status) { pr_debug("%s: Failed to Read Trace Buffer.\n", __func__); goto func_end; @@ -2101,7 +2101,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context) status = cod_get_sym_value(code_mgr, DYNEXTBASE, &dyn_ext_base); - if (DSP_FAILED(status)) { + if (status) { status = -EFAULT; goto func_end; } @@ -2219,7 +2219,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context) int status = 0; status = dev_get_intf_fxns(dev_object, &intf_fxns); - if (DSP_FAILED(status)) { + if (status) { pr_debug("%s: Failed on dev_get_intf_fxns.\n", __func__); goto func_end; } @@ -2233,7 +2233,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context) /* Lookup the address of the modules_header structure */ status = cod_get_sym_value(code_mgr, "_DLModules", &module_dsp_addr); - if (DSP_FAILED(status)) { + if (status) { pr_debug("%s: Failed on cod_get_sym_value for _DLModules.\n", __func__); goto func_end; @@ -2245,7 +2245,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context) status = (*intf_fxns->pfn_brd_read)(bridge_context, (u8 *) &modules_hdr, (u32) module_dsp_addr, sizeof(modules_hdr), 0); - if (DSP_FAILED(status)) { + if (status) { pr_debug("%s: Failed failed to read modules header.\n", __func__); goto func_end; @@ -2280,7 +2280,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context) status = (*intf_fxns->pfn_brd_read)(bridge_context, (u8 *)module_struct, module_dsp_addr, module_size, 0); - if (DSP_FAILED(status)) { + if (status) { pr_debug( "%s: Failed to read dll_module stuct for 0x%x.\n", __func__, module_dsp_addr); diff --git a/drivers/staging/tidspbridge/core/msg_sm.c b/drivers/staging/tidspbridge/core/msg_sm.c index 85ca448..87712e2 100644 --- a/drivers/staging/tidspbridge/core/msg_sm.c +++ b/drivers/staging/tidspbridge/core/msg_sm.c @@ -210,7 +210,7 @@ int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, status = add_new_msg(msg_q->msg_free_list); } } - if (DSP_FAILED(status)) { + if (status) { /* Stay inside CS to prevent others from taking any * of the newly allocated message frames. */ delete_msg_queue(msg_q, num_allocated); @@ -439,7 +439,7 @@ int bridge_msg_put(struct msg_queue *msg_queue_obj, syncs[1] = msg_queue_obj->sync_done; status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index); - if (DSP_FAILED(status)) + if (status) goto func_end; /* Enter critical section */ spin_lock_bh(&hmsg_mgr->msg_mgr_lock); diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 8f25a05..9673acb 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -1318,7 +1318,7 @@ static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt, } status = pte_set(dev_context->pt_attrs, pa, va, HW_PAGE_SIZE4KB, &hw_attrs); - if (DSP_FAILED(status)) + if (status) break; va += HW_PAGE_SIZE4KB; @@ -1344,7 +1344,7 @@ static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt, status = pte_set(dev_context->pt_attrs, page_to_phys(mapped_page), va, HW_PAGE_SIZE4KB, &hw_attrs); - if (DSP_FAILED(status)) + if (status) break; if (mapped_pages) diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c index d938645..b789f8f 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c +++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c @@ -228,7 +228,7 @@ int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd, /* Turn off DSP Peripheral clocks */ status = dsp_clock_disable_all(dev_context->dsp_per_clks); - if (DSP_FAILED(status)) + if (status) return status; #ifdef CONFIG_TIDSPBRIDGE_DVFS else if (target_pwr_state == PWRDM_POWER_OFF) { From patchwork Mon Aug 9 14:36:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 118399 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o79EauCH010026 for ; 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Mon, 9 Aug 2010 20:06:27 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Paul Walmsley , Rajendra Nayak , Kevin Hilman Subject: [PATCH 2/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430 Date: Mon, 9 Aug 2010 20:06:23 +0530 Message-Id: <1281364586-26323-2-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1281364586-26323-1-git-send-email-rnayak@ti.com> References: <1281364586-26323-1-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 09 Aug 2010 14:36:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 3cc768e..892e733 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -15,9 +15,12 @@ #include #include #include +#include +#include #include "omap_hwmod_common_data.h" +#include "cm-regbits-24xx.h" #include "prm-regbits-24xx.h" /* @@ -71,6 +74,8 @@ static struct omap_hwmod omap2420_l3_main_hwmod = { }; static struct omap_hwmod omap2420_l4_wkup_hwmod; +static struct omap_hwmod omap2420_i2c1_hwmod; +static struct omap_hwmod omap2420_i2c2_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { @@ -79,6 +84,45 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2420_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2420_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { &omap2420_l3_main__l4_core, @@ -87,6 +131,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { &omap2420_l4_core__l4_wkup, + &omap2420_l4_core__i2c1, + &omap2420_l4_core__i2c2 }; /* L4 CORE */ @@ -165,6 +211,92 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = SYSC_HAS_SOFTRESET, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr; + +/* I2C1 */ + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { + &omap2420_l4_core__i2c1, +}; + +static struct omap_hwmod omap2420_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_chs = i2c1_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(i2c1_sdma_chs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C1_SHIFT, + }, + }, + .slaves = omap2420_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* I2C2 */ + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { + &omap2420_l4_core__i2c2, +}; + +static struct omap_hwmod omap2420_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_chs = i2c2_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(i2c2_sdma_chs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C2_SHIFT, + }, + }, + .slaves = omap2420_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, @@ -178,5 +310,3 @@ int __init omap2420_hwmod_init(void) { return omap_hwmod_init(omap2420_hwmods); } - - diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4526628..1f75a21 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -15,10 +15,13 @@ #include #include #include +#include +#include #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" /* * OMAP2430 hardware module integration data @@ -71,6 +74,47 @@ static struct omap_hwmod omap2430_l3_main_hwmod = { }; static struct omap_hwmod omap2430_l4_wkup_hwmod; +static struct omap_hwmod omap2430_i2c1_hwmod; +static struct omap_hwmod omap2430_i2c2_hwmod; + +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2430_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2430_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -165,6 +209,100 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr; + +/* I2C1 */ + +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { + &omap2430_l4_core__i2c1, +}; + +static struct omap_hwmod omap2430_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_chs = i2c1_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(i2c1_sdma_chs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS1_SHIFT, + }, + }, + .slaves = omap2430_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* I2C2 */ + +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { + &omap2430_l4_core__i2c2, +}; + +static struct omap_hwmod omap2430_i2c2_hwmod = { + .name = "i2c2_hwmod", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_chs = i2c2_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(i2c2_sdma_chs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS2_SHIFT, + }, + }, + .slaves = omap2430_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, @@ -178,5 +316,3 @@ int __init omap2430_hwmod_init(void) { return omap_hwmod_init(omap2430_hwmods); } - - From patchwork Wed May 5 12:10:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Munegowda, Keshava" X-Patchwork-Id: 97059 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45CAThv005098 for ; Wed, 5 May 2010 12:10:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932234Ab0EEMKZ (ORCPT ); Wed, 5 May 2010 08:10:25 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:41845 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756634Ab0EEMKZ convert rfc822-to-8bit (ORCPT ); Wed, 5 May 2010 08:10:25 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o45CAJRC029071 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 5 May 2010 07:10:21 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o45CAIZh001182; Wed, 5 May 2010 17:40:18 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Wed, 5 May 2010 17:40:19 +0530 From: "Munegowda, Keshava" To: "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "tony@atomide.com" Date: Wed, 5 May 2010 17:40:16 +0530 Subject: [PATCH]omap:mux.c waring removal Thread-Topic: [PATCH]omap:mux.c waring removal Thread-Index: AcrsS+wyQB4ATrINQ8KEZZkNo5i5zg== Message-ID: <0680EC522D0CC943BC586913CF3768C003B3165175@dbde02.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 12:10:29 +0000 (UTC) Index: linux-2.6/arch/arm/mach-omap2/mux.c =================================================================== --- linux-2.6.orig/arch/arm/mach-omap2/mux.c 2010-05-05 05:28:47.000000000 +0530 +++ linux-2.6/arch/arm/mach-omap2/mux.c 2010-05-05 05:29:02.000000000 +0530 @@ -49,7 +49,9 @@ struct list_head node; }; +#ifdef CONFIG_ARCH_OMAP3 static unsigned long mux_phys; +#endif static void __iomem *mux_base; u16 omap_mux_read(u16 reg) From patchwork Mon Apr 12 10:42:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindraj.R" X-Patchwork-Id: 92029 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3CAgPfn005298 for ; Mon, 12 Apr 2010 10:42:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753653Ab0DLKmZ (ORCPT ); Mon, 12 Apr 2010 06:42:25 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:43000 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753308Ab0DLKmY (ORCPT ); Mon, 12 Apr 2010 06:42:24 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3CAgNie029275 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Apr 2010 05:42:23 -0500 Received: from webmail.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3CAgKku007870; Mon, 12 Apr 2010 05:42:21 -0500 (CDT) Received: from 192.168.10.89 (proxying for 10.24.255.18) (SquirrelMail authenticated user x0100947); by dbdmail.itg.ti.com with HTTP; Mon, 12 Apr 2010 16:12:22 +0530 (IST) Message-ID: <33577.192.168.10.89.1271068942.squirrel@dbdmail.itg.ti.com> Date: Mon, 12 Apr 2010 16:12:22 +0530 (IST) Subject: [PATCH 2/3] Serial: Remove 8250 driver assumptions From: "Govindraj.R" To: linux-omap@vger.kernel.org Cc: "Kevin Hilman" , "Tony Lindgren" User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Apr 2010 10:42:26 +0000 (UTC) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 3771254..14ed9fb 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -60,7 +60,11 @@ struct omap_uart_state { struct clk *fck; int clocked; - struct plat_serial8250_port *p; + int irq; + int regshift; + int irqflags; + void __iomem *membase; + resource_size_t mapbase; struct list_head node; struct platform_device pdev; @@ -127,12 +131,52 @@ static struct plat_serial8250_port serial_platform_data3[] = { } }; +static struct omap_uart_state omap_uart[] = { + { + .pdev = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data0, + }, + }, + }, { + .pdev = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = serial_platform_data1, + }, + }, + }, { + .pdev = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = serial_platform_data2, + }, + }, + }, +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) + { + .pdev = { + .name = "serial8250", + .id = 3, + .dev = { + .platform_data = serial_platform_data3, + }, + }, + }, +#endif +}; + + void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) { - serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; - serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; - serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; - serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; + omap_uart[0].mapbase = omap2_globals->uart1_phys; + omap_uart[1].mapbase = omap2_globals->uart2_phys; + omap_uart[2].mapbase = omap2_globals->uart3_phys; + omap_uart[3].mapbase = omap2_globals->uart4_phys; } static inline unsigned int __serial_read_reg(struct uart_port *up, @@ -142,7 +186,7 @@ static inline unsigned int __serial_read_reg(struct uart_port *up, return (unsigned int)__raw_readb(up->membase + offset); } -static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, +static inline unsigned int serial_read_reg(struct omap_uart_state *up, int offset) { offset <<= up->regshift; @@ -156,11 +200,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset, __raw_writeb(value, up->membase + offset); } -static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, +static inline void serial_write_reg(struct omap_uart_state *uart, int offset, int value) { - offset <<= p->regshift; - __raw_writeb(value, p->membase + offset); + offset <<= uart->regshift; + __raw_writeb(value, uart->membase + offset); } /* @@ -170,12 +214,11 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, */ static inline void __init omap_uart_reset(struct omap_uart_state *uart) { - struct plat_serial8250_port *p = uart->p; - - serial_write_reg(p, UART_OMAP_MDR1, 0x07); - serial_write_reg(p, UART_OMAP_SCR, 0x08); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); - serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); + serial_write_reg(uart, UART_OMAP_MDR1, 0x07); + serial_write_reg(uart, UART_OMAP_SCR, 0x08); + serial_write_reg(uart, UART_OMAP_MDR1, 0x00); + serial_write_reg(uart, UART_OMAP_SYSC, (0x02 << 3) | + (1 << 2) | (1 << 0)); } #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) @@ -183,20 +226,19 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) static void omap_uart_save_context(struct omap_uart_state *uart) { u16 lcr = 0; - struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; - lcr = serial_read_reg(p, UART_LCR); - serial_write_reg(p, UART_LCR, 0xBF); - uart->dll = serial_read_reg(p, UART_DLL); - uart->dlh = serial_read_reg(p, UART_DLM); - serial_write_reg(p, UART_LCR, lcr); - uart->ier = serial_read_reg(p, UART_IER); - uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); - uart->scr = serial_read_reg(p, UART_OMAP_SCR); - uart->wer = serial_read_reg(p, UART_OMAP_WER); + lcr = serial_read_reg(uart, UART_LCR); + serial_write_reg(uart, UART_LCR, 0xBF); + uart->dll = serial_read_reg(uart, UART_DLL); + uart->dlh = serial_read_reg(uart, UART_DLM); + serial_write_reg(uart, UART_LCR, lcr); + uart->ier = serial_read_reg(uart, UART_IER); + uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); + uart->scr = serial_read_reg(uart, UART_OMAP_SCR); + uart->wer = serial_read_reg(uart, UART_OMAP_WER); uart->context_valid = 1; } @@ -204,7 +246,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart) static void omap_uart_restore_context(struct omap_uart_state *uart) { u16 efr = 0; - struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; @@ -214,25 +255,25 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) uart->context_valid = 0; - serial_write_reg(p, UART_OMAP_MDR1, 0x7); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - efr = serial_read_reg(p, UART_EFR); - serial_write_reg(p, UART_EFR, UART_EFR_ECB); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, 0x0); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_DLL, uart->dll); - serial_write_reg(p, UART_DLM, uart->dlh); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, uart->ier); - serial_write_reg(p, UART_FCR, 0xA1); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_EFR, efr); - serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); - serial_write_reg(p, UART_OMAP_SCR, uart->scr); - serial_write_reg(p, UART_OMAP_WER, uart->wer); - serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ + serial_write_reg(uart, UART_OMAP_MDR1, 0x7); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + efr = serial_read_reg(uart, UART_EFR); + serial_write_reg(uart, UART_EFR, UART_EFR_ECB); + serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(uart, UART_IER, 0x0); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_DLL, uart->dll); + serial_write_reg(uart, UART_DLM, uart->dlh); + serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(uart, UART_IER, uart->ier); + serial_write_reg(uart, UART_FCR, 0xA1); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_EFR, efr); + serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); + serial_write_reg(uart, UART_OMAP_SCR, uart->scr); + serial_write_reg(uart, UART_OMAP_WER, uart->wer); + serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); + serial_write_reg(uart, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} @@ -300,16 +341,15 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart) static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, int enable) { - struct plat_serial8250_port *p = uart->p; u16 sysc; - sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; + sysc = serial_read_reg(uart, UART_OMAP_SYSC) & 0x7; if (enable) sysc |= 0x2 << 3; else sysc |= 0x1 << 3; - serial_write_reg(p, UART_OMAP_SYSC, sysc); + serial_write_reg(uart, UART_OMAP_SYSC, sysc); } static void omap_uart_block_sleep(struct omap_uart_state *uart) @@ -430,9 +470,24 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) return IRQ_NONE; } +static void omap_uart_irq_port_init(struct omap_uart_state *uart) +{ + switch (uart->num) { + case 0: + uart->irq = INT_24XX_UART1_IRQ; + break; + case 1: + uart->irq = INT_24XX_UART2_IRQ; + break; + case 2: + uart->irq = INT_24XX_UART3_IRQ; + break; + } + uart->regshift = 2; +} + static void omap_uart_idle_init(struct omap_uart_state *uart) { - struct plat_serial8250_port *p = uart->p; int ret; uart->can_sleep = 0; @@ -495,8 +550,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) uart->padconf = 0; } - p->irqflags |= IRQF_SHARED; - ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, + uart->irqflags |= IRQF_SHARED; + ret = request_irq(uart->irq, omap_uart_interrupt, IRQF_SHARED, "serial idle", (void *)uart); WARN_ON(ret); } @@ -508,10 +563,10 @@ void omap_uart_enable_irqs(int enable) list_for_each_entry(uart, &uart_list, node) { if (enable) - ret = request_irq(uart->p->irq, omap_uart_interrupt, + ret = request_irq(uart->irq, omap_uart_interrupt, IRQF_SHARED, "serial idle", (void *)uart); else - free_irq(uart->p->irq, (void *)uart); + free_irq(uart->irq, (void *)uart); } } @@ -558,46 +613,6 @@ DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} #define DEV_CREATE_FILE(dev, attr) #endif /* CONFIG_PM */ - -static struct omap_uart_state omap_uart[] = { - { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data0, - }, - }, - }, { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = serial_platform_data1, - }, - }, - }, { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = serial_platform_data2, - }, - }, - }, -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - { - .pdev = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = serial_platform_data3, - }, - }, - }, -#endif -}; - /* * Override the default 8250 read handler: mem_serial_in() * Empty RX fifo read causes an abort on omap3630 and omap4 @@ -630,6 +645,7 @@ static void serial_out_override(struct uart_port *up, int offset, int value) } __serial_write_reg(up, offset, value); } + void __init omap_serial_early_init(void) { int i, nr_ports; @@ -652,8 +668,17 @@ void __init omap_serial_early_init(void) struct device *dev = &pdev->dev; struct plat_serial8250_port *p = dev->platform_data; + uart->num = i; + /* + * Populate irq value independently into + * omap_uart_state structure. + * Dont want to depend on 8250 structure. + * TODO: will be removed while adding hwmod + */ + omap_uart_irq_port_init(uart); + /* Don't map zero-based physical address */ - if (p->mapbase == 0) { + if (uart->mapbase == 0) { dev_warn(dev, "no physical address for uart#%d," " so skipping early_init...\n", i); continue; @@ -662,8 +687,8 @@ void __init omap_serial_early_init(void) * Module 4KB + L4 interconnect 4KB * Static mapping, never released */ - p->membase = ioremap(p->mapbase, SZ_8K); - if (!p->membase) { + uart->membase = ioremap(uart->mapbase, SZ_8K); + if (!uart->membase) { dev_err(dev, "ioremap failed for uart%i\n", i + 1); continue; } @@ -688,12 +713,12 @@ void __init omap_serial_early_init(void) continue; } - uart->num = i; p->private_data = uart; - uart->p = p; + p->membase = uart->membase; + p->mapbase = uart->mapbase; if (cpu_is_omap44xx()) - p->irq += 32; + uart->irq += 32; } } @@ -713,7 +738,7 @@ void __init omap_serial_init_port(int port) struct omap_uart_state *uart; struct platform_device *pdev; struct device *dev; - + struct plat_serial8250_port *p; BUG_ON(port < 0); BUG_ON(port >= ARRAY_SIZE(omap_uart)); @@ -733,36 +758,37 @@ void __init omap_serial_init_port(int port) omap_uart_reset(uart); omap_uart_idle_init(uart); + p = dev->platform_data; + /* + * omap44xx: Never read empty UART fifo + * omap3xxx: Never read empty UART fifo on UARTs + * with IP rev >=0x52 + */ + if (cpu_is_omap44xx()) { + p->serial_in = serial_in_override; + p->serial_out = serial_out_override; + } else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) + >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { + p->serial_in = serial_in_override; + p->serial_out = serial_out_override; + } + list_add_tail(&uart->node, &uart_list); if (WARN_ON(platform_device_register(pdev))) return; if ((cpu_is_omap34xx() && uart->padconf) || - (uart->wk_en && uart->wk_mask)) { + (uart->wk_en && uart->wk_mask)) { device_init_wakeup(dev, true); DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); } - - /* - * omap44xx: Never read empty UART fifo - * omap3xxx: Never read empty UART fifo on UARTs - * with IP rev >=0x52 - */ - if (cpu_is_omap44xx()) { - uart->p->serial_in = serial_in_override; - uart->p->serial_out = serial_out_override; - } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { - uart->p->serial_in = serial_in_override; - uart->p->serial_out = serial_out_override; - } } /** * omap_serial_init() - intialize all supported serial ports * - * Initializes all available UARTs as serial ports. Platforms + * Initializes all available UARTs as serial ports. Platforms * can call this function when they want to have default behaviour * for serial ports (e.g initialize them all as serial ports). */ From patchwork Mon Apr 12 10:42:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindraj.R" X-Patchwork-Id: 92028 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3CAgFiN005264 for ; Mon, 12 Apr 2010 10:42:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753635Ab0DLKmO (ORCPT ); Mon, 12 Apr 2010 06:42:14 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:42994 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753546Ab0DLKmM (ORCPT ); Mon, 12 Apr 2010 06:42:12 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3CAg9us029262 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Apr 2010 05:42:10 -0500 Received: from webmail.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3CAg6db029933; Mon, 12 Apr 2010 05:42:07 -0500 (CDT) Received: from 192.168.10.89 (proxying for 10.24.255.18) (SquirrelMail authenticated user x0100947); by dbdmail.itg.ti.com with HTTP; Mon, 12 Apr 2010 16:12:08 +0530 (IST) Message-ID: <33339.192.168.10.89.1271068928.squirrel@dbdmail.itg.ti.com> Date: Mon, 12 Apr 2010 16:12:08 +0530 (IST) Subject: [PATCH 1/3] serial: Add OMAP high-speed UART driver From: "Govindraj.R" To: linux-omap@vger.kernel.org Cc: "Kevin Hilman" , "Tony Lindgren" , "Olof Johansson" User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Apr 2010 10:42:17 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h new file mode 100644 index 0000000..0d6f076 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -0,0 +1,129 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __OMAP_SERIAL_H__ +#define __OMAP_SERIAL_H__ + +#include +#include + +#include +#include + +#define DRIVER_NAME "omap-hsuart" + +/* + * Use tty device name as ttyO, [O -> OMAP] + * in bootargs we specify as console=ttyO0 if uart1 + * is used as console uart. + */ +#define OMAP_SERIAL_NAME "ttyO" + +#define OMAP_MDR1_DISABLE 0x07 +#define OMAP_MDR1_MODE13X 0x03 +#define OMAP_MDR1_MODE16X 0x00 +#define OMAP_MODE13X_SPEED 230400 + +/* + * LCR = 0XBF: Switch to Configuration Mode B. + * In configuration mode b allow access + * to EFR,DLL,DLH. + * Reference OMAP TRM Chapter 17 + * Section: 1.4.3 Mode Selection + */ +#define OMAP_UART_LCR_CONF_MDB 0XBF + +/* WER = 0x7F + * Enable module level wakeup in WER reg + */ +#define OMAP_UART_WER_MOD_WKUP 0X7F + +/* Enable XON/XOFF flow control on output */ +#define OMAP_UART_SW_TX 0x04 + +/* Enable XON/XOFF flow control on input */ +#define OMAP_UART_SW_RX 0x04 + +#define OMAP_UART_SYSC_RESET 0X07 +#define OMAP_UART_TCR_TRIG 0X0F +#define OMAP_UART_SW_CLR 0XF0 +#define OMAP_UART_FIFO_CLR 0X06 + +#define OMAP_UART_DMA_CH_FREE -1 + +#define RX_TIMEOUT (3 * HZ) +#define OMAP_MAX_HSUART_PORTS 4 + +#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA + +struct omap_uart_port_info { + bool dma_enabled; /* To specify DMA Mode */ + unsigned int uartclk; /* UART clock rate */ + void __iomem *membase; /* ioremap cookie or NULL */ + resource_size_t mapbase; /* resource base */ + unsigned long irqflags; /* request_irq flags */ + upf_t flags; /* UPF_* flags */ +}; + +struct uart_omap_dma { + u8 uart_dma_tx; + u8 uart_dma_rx; + int rx_dma_channel; + int tx_dma_channel; + dma_addr_t rx_buf_dma_phys; + dma_addr_t tx_buf_dma_phys; + unsigned int uart_base; + /* + * Buffer for rx dma.It is not required for tx because the buffer + * comes from port structure. + */ + unsigned char *rx_buf; + unsigned int prev_rx_dma_pos; + int tx_buf_size; + int tx_dma_used; + int rx_dma_used; + spinlock_t tx_lock; + spinlock_t rx_lock; + /* timer to poll activity on rx dma */ + struct timer_list rx_timer; + int rx_buf_size; + int rx_timeout; +}; + +struct uart_omap_port { + struct uart_port port; + struct uart_omap_dma uart_dma; + struct platform_device *pdev; + + unsigned char ier; + unsigned char lcr; + unsigned char mcr; + unsigned char fcr; + unsigned char efr; + + int use_dma; + /* + * Some bits in registers are cleared on a read, so they must + * be saved whenever the register is read but the bits will not + * be immediately processed. + */ + unsigned int lsr_break_flag; + unsigned char msr_saved_flags; + char name[20]; + unsigned long port_activity; +}; + +#endif /* __OMAP_SERIAL_H__ */ diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index f55c494..4346bfa 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1387,6 +1387,33 @@ config SERIAL_OF_PLATFORM Currently, only 8250 compatible ports are supported, but others can easily be added. +config SERIAL_OMAP + tristate "OMAP serial port support" + depends on ARCH_OMAP3 || ARCH_OMAP4 + select SERIAL_CORE + help + If you have a machine based on an Texas Instruments OMAP CPU you + can enable its onboard serial ports by enabling this option. + + By enabling this option you take advantage of dma feature available + with the omap-serial driver. DMA support can be enabled from platform + data. + +config SERIAL_OMAP_CONSOLE + bool "Console on OMAP serial port" + depends on SERIAL_OMAP + select SERIAL_CORE_CONSOLE + help + Select this option if you would like to use omap serial port as + console. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyOx". (Try "man bootparam" or see the documentation of + your boot loader about how to pass options to the kernel at + boot time.) + config SERIAL_OF_PLATFORM_NWPSERIAL tristate "NWP serial port driver" depends on PPC_OF && PPC_DCR diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6aa4723..87e4d7a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -83,3 +83,4 @@ obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o obj-$(CONFIG_SERIAL_QE) += ucc_uart.o obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o +obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o diff --git a/drivers/serial/omap-serial.c b/drivers/serial/omap-serial.c new file mode 100644 index 0000000..8071692 --- /dev/null +++ b/drivers/serial/omap-serial.c @@ -0,0 +1,1336 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Note: This driver is made seperate from 8250 driver as we cannot + * over load 8250 driver with omap platform specific configuration for + * features like DMA, it makes easier to implement features like DMA and + * hardware flow control and software flow control configuration with + * this driver as required for the omap-platform. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; + +/* Forward declaration of functions */ +static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); +static void serial_omap_rx_timeout(unsigned long uart_no); +static int serial_omap_start_rxdma(struct uart_omap_port *up); + +static inline unsigned int serial_in(struct uart_omap_port *up, int offset) +{ + offset <<= up->port.regshift; + return readw(up->port.membase + offset); +} + +static inline void serial_out(struct uart_omap_port *up, int offset, int value) +{ + offset <<= up->port.regshift; + writew(value, up->port.membase + offset); +} + +static inline void serial_omap_clear_fifos(struct uart_omap_port *up) +{ + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + serial_out(up, UART_FCR, 0); +} + +/** + * serial_omap_get_divisor() - calculate divisor value + * @port: uart port info + * @baud: baudrate for which divisor needs to be calculated. + * + * We have written our own function to get the divisor so as to support + * 13x mode. 3Mbps Baudrate as an different divisor. + * Reference OMAP TRM Chapter 17: + * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates + * referring to oversampling - divisor value + * baudrate 460,800 to 3,686,400 all have divisor 13 + * except 3,000,000 which has divisor value 16 + */ +static unsigned int +serial_omap_get_divisor(struct uart_port *port, unsigned int baud) +{ + unsigned int divisor; + + if (baud > OMAP_MODE13X_SPEED && baud != 3000000) + divisor = 13; + else + divisor = 16; + return port->uartclk/(baud * divisor); +} + +static void serial_omap_stop_rxdma(struct uart_omap_port *up) +{ + if (up->uart_dma.rx_dma_used) { + del_timer(&up->uart_dma.rx_timer); + omap_stop_dma(up->uart_dma.rx_dma_channel); + omap_free_dma(up->uart_dma.rx_dma_channel); + up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; + up->uart_dma.rx_dma_used = false; + } +} + +static void serial_omap_enable_ms(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); + up->ier |= UART_IER_MSI; + serial_out(up, UART_IER, up->ier); +} + +static void serial_omap_stop_tx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + if (up->use_dma && + up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { + /* + * Check if dma is still active. If yes do nothing, + * return. Else stop dma + */ + if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) + return; + omap_stop_dma(up->uart_dma.tx_dma_channel); + omap_free_dma(up->uart_dma.tx_dma_channel); + up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; + } + + if (up->ier & UART_IER_THRI) { + up->ier &= ~UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serial_omap_stop_rx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + if (up->use_dma) + serial_omap_stop_rxdma(up); + up->ier &= ~UART_IER_RLSI; + up->port.read_status_mask &= ~UART_LSR_DR; + serial_out(up, UART_IER, up->ier); +} + +static inline void receive_chars(struct uart_omap_port *up, int *status) +{ + struct tty_struct *tty = up->port.state->port.tty; + unsigned int flag; + unsigned char ch, lsr = *status; + int max_count = 256; + + do { + if (likely(lsr & UART_LSR_DR)) + ch = serial_in(up, UART_RX); + flag = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { + /* + * For statistics only + */ + if (lsr & UART_LSR_BI) { + lsr &= ~(UART_LSR_FE | UART_LSR_PE); + up->port.icount.brk++; + /* + * We do the SysRQ and SAK checking + * here because otherwise the break + * may get masked by ignore_status_mask + * or read_status_mask. + */ + if (uart_handle_break(&up->port)) + goto ignore_char; + } else if (lsr & UART_LSR_PE) + up->port.icount.parity++; + else if (lsr & UART_LSR_FE) + up->port.icount.frame++; + if (lsr & UART_LSR_OE) + up->port.icount.overrun++; + + /* + * Mask off conditions which should be ignored. + */ + lsr &= up->port.read_status_mask; + +#ifdef CONFIG_SERIAL_OMAP_CONSOLE + if (up->port.line == up->port.cons->index) { + /* Recover the break flag from console xmit */ + lsr |= up->lsr_break_flag; + up->lsr_break_flag = 0; + } +#endif + if (lsr & UART_LSR_BI) + flag = TTY_BREAK; + else if (lsr & UART_LSR_PE) + flag = TTY_PARITY; + else if (lsr & UART_LSR_FE) + flag = TTY_FRAME; + } + + if (uart_handle_sysrq_char(&up->port, ch)) + goto ignore_char; + uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); +ignore_char: + lsr = serial_in(up, UART_LSR); + } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); + spin_unlock(&up->port.lock); + tty_flip_buffer_push(tty); + spin_lock(&up->port.lock); +} + +static void transmit_chars(struct uart_omap_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count; + + if (up->port.x_char) { + serial_out(up, UART_TX, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { + serial_omap_stop_tx(&up->port); + return; + } + count = up->port.fifosize / 4; + do { + serial_out(up, UART_TX, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (uart_circ_empty(xmit)) + serial_omap_stop_tx(&up->port); +} + +static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) +{ + if (!(up->ier & UART_IER_THRI)) { + up->ier |= UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serial_omap_start_tx(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + struct circ_buf *xmit; + unsigned int start; + int ret = 0; + + if (!up->use_dma || up->port.x_char) { + serial_omap_enable_ier_thri(up); + return; + } + + xmit = &up->port.state->xmit; + if (uart_circ_empty(xmit) || up->uart_dma.tx_dma_used) + return; + + if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) + ret = omap_request_dma(up->uart_dma.uart_dma_tx, + "UART Tx DMA", + (void *)uart_tx_dma_callback, up, + &(up->uart_dma.tx_dma_channel)); + + if (ret < 0) { + serial_omap_enable_ier_thri(up); + return; + } + + start = up->uart_dma.tx_buf_dma_phys + + (xmit->tail & (UART_XMIT_SIZE - 1)); + spin_lock(&(up->uart_dma.tx_lock)); + up->uart_dma.tx_dma_used = true; + spin_unlock(&(up->uart_dma.tx_lock)); + + up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); + /* + * It is a circular buffer. See if the buffer has wounded back. + * If yes it will have to be transferred in two separate dma + * transfers + */ + if (start + up->uart_dma.tx_buf_size >= + up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) + up->uart_dma.tx_buf_size = + (up->uart_dma.tx_buf_dma_phys + + UART_XMIT_SIZE) - start; + + omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, start, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.tx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_tx, 0); + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.tx_dma_channel); +} + +static unsigned int check_modem_status(struct uart_omap_port *up) +{ + int status; + status = serial_in(up, UART_MSR); + + status |= up->msr_saved_flags; + up->msr_saved_flags = 0; + + if ((status & UART_MSR_ANY_DELTA) == 0) + return status; + if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && + up->port.state != NULL) { + if (status & UART_MSR_TERI) + up->port.icount.rng++; + if (status & UART_MSR_DDSR) + up->port.icount.dsr++; + if (status & UART_MSR_DDCD) + uart_handle_dcd_change + (&up->port, status & UART_MSR_DCD); + if (status & UART_MSR_DCTS) + uart_handle_cts_change + (&up->port, status & UART_MSR_CTS); + wake_up_interruptible(&up->port.state->port.delta_msr_wait); + } + + return status; +} + +/** + * serial_omap_irq() - This handles the interrupt from one port + * @irq: uart port irq number + * @dev_id: uart port info + */ +static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) +{ + struct uart_omap_port *up = dev_id; + unsigned int iir, lsr; + unsigned long flags; + + spin_lock_irqsave(&up->port.lock, flags); + iir = serial_in(up, UART_IIR); + if (iir & UART_IIR_NO_INT) + return IRQ_NONE; + + lsr = serial_in(up, UART_LSR); + if (iir & UART_IER_RLSI) { + if (up->use_dma) + up->ier &= ~UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + if (!up->use_dma || + serial_omap_start_rxdma(up) != 0) + if (lsr & UART_LSR_DR) + receive_chars(up, &lsr); + } + + check_modem_status(up); + if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) + transmit_chars(up); + + spin_unlock_irqrestore(&up->port.lock, flags); + up->port_activity = jiffies; + return IRQ_HANDLED; +} + +static unsigned int serial_omap_tx_empty(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + unsigned int ret = 0; + + dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); + spin_lock_irqsave(&up->port.lock, flags); + ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; + spin_unlock_irqrestore(&up->port.lock, flags); + + return ret; +} + +static unsigned int serial_omap_get_mctrl(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char status; + unsigned int ret = 0; + + status = check_modem_status(up); + dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); + + if (status & UART_MSR_DCD) + ret |= TIOCM_CAR; + if (status & UART_MSR_RI) + ret |= TIOCM_RNG; + if (status & UART_MSR_DSR) + ret |= TIOCM_DSR; + if (status & UART_MSR_CTS) + ret |= TIOCM_CTS; + return ret; +} + +static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char mcr = 0; + + dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); + if (mctrl & TIOCM_RTS) + mcr |= UART_MCR_RTS; + if (mctrl & TIOCM_DTR) + mcr |= UART_MCR_DTR; + if (mctrl & TIOCM_OUT1) + mcr |= UART_MCR_OUT1; + if (mctrl & TIOCM_OUT2) + mcr |= UART_MCR_OUT2; + if (mctrl & TIOCM_LOOP) + mcr |= UART_MCR_LOOP; + + mcr |= up->mcr; + serial_out(up, UART_MCR, mcr); +} + +static void serial_omap_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + + dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); + spin_lock_irqsave(&up->port.lock, flags); + if (break_state == -1) + up->lcr |= UART_LCR_SBC; + else + up->lcr &= ~UART_LCR_SBC; + serial_out(up, UART_LCR, up->lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int serial_omap_startup(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + int retval; + + /* + * Allocate the IRQ + */ + retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, + up->name, up); + if (retval) + return retval; + + dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); + + /* + * Clear the FIFO buffers and disable them. + * (they will be reenabled in set_termios()) + */ + serial_omap_clear_fifos(up); + /* For Hardware flow control */ + serial_out(up, UART_MCR, UART_MCR_RTS); + + /* + * Clear the interrupt registers. + */ + (void) serial_in(up, UART_LSR); + if (serial_in(up, UART_LSR) & UART_LSR_DR) + (void) serial_in(up, UART_RX); + (void) serial_in(up, UART_IIR); + (void) serial_in(up, UART_MSR); + + /* + * Now, initialize the UART + */ + serial_out(up, UART_LCR, UART_LCR_WLEN8); + spin_lock_irqsave(&up->port.lock, flags); + /* + * Most PC uarts need OUT2 raised to enable interrupts. + */ + up->port.mctrl |= TIOCM_OUT2; + serial_omap_set_mctrl(&up->port, up->port.mctrl); + spin_unlock_irqrestore(&up->port.lock, flags); + + up->msr_saved_flags = 0; + if (up->use_dma) { + free_page((unsigned long)up->port.state->xmit.buf); + up->port.state->xmit.buf = dma_alloc_coherent(NULL, + UART_XMIT_SIZE, + (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), + 0); + init_timer(&(up->uart_dma.rx_timer)); + up->uart_dma.rx_timer.function = serial_omap_rx_timeout; + up->uart_dma.rx_timer.data = up->pdev->id; + /* Currently the buffer size is 4KB. Can increase it */ + up->uart_dma.rx_buf = dma_alloc_coherent(NULL, + up->uart_dma.rx_buf_size, + (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); + } + /* + * Finally, enable interrupts. Note: Modem status interrupts + * are set via set_termios(), which will be occurring imminently + * anyway, so we don't enable them here. + */ + up->ier = UART_IER_RLSI | UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + + up->port_activity = jiffies; + return 0; +} + +static void serial_omap_shutdown(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned long flags = 0; + + dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); + /* + * Disable interrupts from this port + */ + up->ier = 0; + serial_out(up, UART_IER, 0); + + spin_lock_irqsave(&up->port.lock, flags); + up->port.mctrl &= ~TIOCM_OUT2; + serial_omap_set_mctrl(&up->port, up->port.mctrl); + spin_unlock_irqrestore(&up->port.lock, flags); + + /* + * Disable break condition and FIFOs + */ + serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); + serial_omap_clear_fifos(up); + + /* + * Read data port to reset things, and then free the irq + */ + if (serial_in(up, UART_LSR) & UART_LSR_DR) + (void) serial_in(up, UART_RX); + if (up->use_dma) { + int tmp; + dma_free_coherent(up->port.dev, + UART_XMIT_SIZE, up->port.state->xmit.buf, + up->uart_dma.tx_buf_dma_phys); + up->port.state->xmit.buf = NULL; + serial_omap_stop_rx(port); + dma_free_coherent(up->port.dev, + up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, + up->uart_dma.rx_buf_dma_phys); + up->uart_dma.rx_buf = NULL; + tmp = serial_in(up, UART_OMAP_SYSC) & OMAP_UART_SYSC_RESET; + serial_out(up, UART_OMAP_SYSC, tmp); /* force-idle */ + } + free_irq(up->port.irq, up); +} + +static inline void +serial_omap_configure_xonxoff + (struct uart_omap_port *up, struct ktermios *termios) +{ + unsigned char efr = 0; + + up->lcr = serial_in(up, UART_LCR); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); + + serial_out(up, UART_XON1, termios->c_cc[VSTART]); + serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); + + /* clear SW control mode bits */ + efr = up->efr; + efr &= OMAP_UART_SW_CLR; + + /* + * IXON Flag: + * Enable XON/XOFF flow control on output. + * Transmit XON1, XOFF1 + */ + if (termios->c_iflag & IXON) + efr |= OMAP_UART_SW_TX; + + /* + * IXOFF Flag: + * Enable XON/XOFF flow control on input. + * Receiver compares XON1, XOFF1. + */ + if (termios->c_iflag & IXOFF) + efr |= OMAP_UART_SW_RX; + + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + up->mcr = serial_in(up, UART_MCR); + + /* + * IXANY Flag: + * Enable any character to restart output. + * Operation resumes after receiving any + * character after recognition of the XOFF character + */ + if (termios->c_iflag & IXANY) + up->mcr |= UART_MCR_XONANY; + + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); + /* Enable special char function UARTi.EFR_REG[5] and + * load the new software flow control mode IXON or IXOFF + * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. + */ + serial_out(up, UART_EFR, efr | UART_EFR_SCD); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); + serial_out(up, UART_LCR, up->lcr); +} + +static void +serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char cval = 0; + unsigned char efr = 0; + unsigned long flags = 0; + unsigned int baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + cval = UART_LCR_WLEN5; + break; + case CS6: + cval = UART_LCR_WLEN6; + break; + case CS7: + cval = UART_LCR_WLEN7; + break; + default: + case CS8: + cval = UART_LCR_WLEN8; + break; + } + + if (termios->c_cflag & CSTOPB) + cval |= UART_LCR_STOP; + if (termios->c_cflag & PARENB) + cval |= UART_LCR_PARITY; + if (!(termios->c_cflag & PARODD)) + cval |= UART_LCR_EPAR; + + /* + * Ask the core to calculate the divisor for us. + */ + + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); + quot = serial_omap_get_divisor(port, baud); + + up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | + UART_FCR_ENABLE_FIFO; + if (up->use_dma) + up->fcr |= UART_FCR_DMA_SELECT; + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= UART_LSR_BI; + + /* + * Characters to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= UART_LSR_BI; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_OE; + } + + /* + * ignore all characters if CREAD is not set + */ + if ((termios->c_cflag & CREAD) == 0) + up->port.ignore_status_mask |= UART_LSR_DR; + + /* + * Modem status interrupts + */ + up->ier &= ~UART_IER_MSI; + if (UART_ENABLE_MS(&up->port, termios->c_cflag)) + up->ier |= UART_IER_MSI; + serial_out(up, UART_IER, up->ier); + serial_out(up, UART_LCR, cval); /* reset DLAB */ + + /* FIFOs and DMA Settings */ + + /* FCR can be changed only when the + * baud clock is not running + * DLL_REG and DLH_REG set to 0. + */ + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_DLL, 0); + serial_out(up, UART_DLM, 0); + serial_out(up, UART_LCR, 0); + + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_LCR, 0); + up->mcr = serial_in(up, UART_MCR); + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + /* FIFO ENABLE, DMA MODE */ + serial_out(up, UART_FCR, up->fcr); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + if (up->use_dma) { + serial_out(up, UART_TI752_TLR, 0); + serial_out(up, UART_OMAP_SCR, + (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8)); + } + + serial_out(up, UART_EFR, up->efr); + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_MCR, up->mcr); + + /* Protocol, Baud Rate, and Interrupt Settings */ + serial_out(up, UART_LCR, 0x0); + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_DISABLE); + /* + * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) + * The access to uart register after MDR1 Access + * causes UART to corrupt data. + * + * Need a delay = 5 L4 clock cycles + + * 5 UART functional clock cycle (@48MHz = ~0.2uS) + */ + udelay(2); + /* TX and RX FIFO Clear */ + serial_out(up, UART_FCR, (up->fcr | OMAP_UART_FIFO_CLR)); + + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_LCR, 0); + serial_out(up, UART_IER, 0); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ + serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ + + serial_out(up, UART_LCR, 0); + serial_out(up, UART_IER, up->ier); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + + serial_out(up, UART_EFR, up->efr); + serial_out(up, UART_LCR, cval); + + if (baud > 230400 && baud != 3000000) + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE13X); + else + serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE16X); + + serial_out(up, UART_LCR, 0x0); + /* + * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) + */ + udelay(2); + /* TX and RX FIFO Clear */ + serial_out(up, UART_FCR, (up->fcr | OMAP_UART_FIFO_CLR)); + + serial_out(up, UART_LCR, cval); + + /* Hardware Flow Control Configuration */ + + if (termios->c_cflag & CRTSCTS) { + efr |= (UART_EFR_CTS | UART_EFR_RTS); + serial_out(up, UART_LCR, UART_LCR_DLAB); + + up->mcr = serial_in(up, UART_MCR); + serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); + + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + up->efr = serial_in(up, UART_EFR); + serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); + + serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); + serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ + serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); + serial_out(up, UART_LCR, cval); + } + + serial_omap_set_mctrl(&up->port, up->port.mctrl); + /* Software Flow Control Configuration */ + if (termios->c_iflag & (IXON | IXOFF)) + serial_omap_configure_xonxoff(up, termios); + + spin_unlock_irqrestore(&up->port.lock, flags); + dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); +} + +static void +serial_omap_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + unsigned char efr; + + dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); + efr = serial_in(up, UART_EFR); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_EFR, efr | UART_EFR_ECB); + serial_out(up, UART_LCR, 0); + + serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); + serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_EFR, efr); + serial_out(up, UART_LCR, 0); + /* Enable module level wake up */ + serial_out(up, UART_OMAP_WER, + (state != 0) ? OMAP_UART_WER_MOD_WKUP : 0); +} + +static void serial_omap_release_port(struct uart_port *port) +{ + dev_dbg(port->dev, "serial_omap_release_port+\n"); +} + +static int serial_omap_request_port(struct uart_port *port) +{ + dev_dbg(port->dev, "serial_omap_request_port+\n"); + return 0; +} + +static void serial_omap_config_port(struct uart_port *port, int flags) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", + up->pdev->id); + up->port.type = PORT_OMAP; +} + +static int +serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + /* we don't want the core code to modify any port params */ + dev_dbg(port->dev, "serial_omap_verify_port+\n"); + return -EINVAL; +} + +static const char * +serial_omap_type(struct uart_port *port) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); + return up->name; +} + +#ifdef CONFIG_SERIAL_OMAP_CONSOLE + +static struct uart_omap_port *serial_omap_console_ports[4]; + +static struct uart_driver serial_omap_reg; + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void wait_for_xmitr(struct uart_omap_port *up) +{ + unsigned int status, tmout = 10000; + + /* Wait up to 10ms for the character(s) to be sent. */ + do { + status = serial_in(up, UART_LSR); + + if (status & UART_LSR_BI) + up->lsr_break_flag = UART_LSR_BI; + + if (--tmout == 0) + break; + udelay(1); + } while ((status & BOTH_EMPTY) != BOTH_EMPTY); + + /* Wait up to 1s for flow control if necessary */ + if (up->port.flags & UPF_CONS_FLOW) { + tmout = 1000000; + for (tmout = 1000000; tmout; tmout--) { + unsigned int msr = serial_in(up, UART_MSR); + up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; + if (msr & UART_MSR_CTS) + break; + udelay(1); + } + } +} + +static void serial_omap_console_putchar(struct uart_port *port, int ch) +{ + struct uart_omap_port *up = (struct uart_omap_port *)port; + + wait_for_xmitr(up); + serial_out(up, UART_TX, ch); +} + +static void +serial_omap_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_omap_port *up = serial_omap_console_ports[co->index]; + unsigned int ier; + + /* + * First save the IER then disable the interrupts + */ + ier = serial_in(up, UART_IER); + serial_out(up, UART_IER, 0); + + uart_console_write(&up->port, s, count, serial_omap_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + wait_for_xmitr(up); + serial_out(up, UART_IER, ier); + /* + * The receive handling will happen properly because the + * receive ready bit will still be set; it is not cleared + * on read. However, modem control will not, we must + * call it if we have saved something in the saved flags + * while processing with interrupts off. + */ + if (up->msr_saved_flags) + check_modem_status(up); +} + +static int __init +serial_omap_console_setup(struct console *co, char *options) +{ + struct uart_omap_port *up; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + int r; + + if (serial_omap_console_ports[co->index] == NULL) + return -ENODEV; + up = serial_omap_console_ports[co->index]; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + r = uart_set_options(&up->port, co, baud, parity, bits, flow); + + return r; +} + +static struct console serial_omap_console = { + .name = OMAP_SERIAL_NAME, + .write = serial_omap_console_write, + .device = uart_console_device, + .setup = serial_omap_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &serial_omap_reg, +}; + +static void serial_omap_add_console_port(struct uart_omap_port *up) +{ + serial_omap_console_ports[up->pdev->id] = up; +} + +#define OMAP_CONSOLE (&serial_omap_console) + +#else + +#define OMAP_CONSOLE NULL + +static inline void serial_omap_add_console_port(struct uart_omap_port *up) +{} + +#endif + +struct uart_ops serial_omap_pops = { + .tx_empty = serial_omap_tx_empty, + .set_mctrl = serial_omap_set_mctrl, + .get_mctrl = serial_omap_get_mctrl, + .stop_tx = serial_omap_stop_tx, + .start_tx = serial_omap_start_tx, + .stop_rx = serial_omap_stop_rx, + .enable_ms = serial_omap_enable_ms, + .break_ctl = serial_omap_break_ctl, + .startup = serial_omap_startup, + .shutdown = serial_omap_shutdown, + .set_termios = serial_omap_set_termios, + .pm = serial_omap_pm, + .type = serial_omap_type, + .release_port = serial_omap_release_port, + .request_port = serial_omap_request_port, + .config_port = serial_omap_config_port, + .verify_port = serial_omap_verify_port, +}; + +static struct uart_driver serial_omap_reg = { + .owner = THIS_MODULE, + .driver_name = "OMAP-SERIAL", + .dev_name = OMAP_SERIAL_NAME, + .nr = OMAP_MAX_HSUART_PORTS, + .cons = OMAP_CONSOLE, +}; + +static int +serial_omap_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct uart_omap_port *up = platform_get_drvdata(pdev); + + if (up) + uart_suspend_port(&serial_omap_reg, &up->port); + return 0; +} + +static int serial_omap_resume(struct platform_device *dev) +{ + struct uart_omap_port *up = platform_get_drvdata(dev); + + if (up) + uart_resume_port(&serial_omap_reg, &up->port); + return 0; +} + +static void serial_omap_rx_timeout(unsigned long uart_no) +{ + struct uart_omap_port *up = ui[uart_no]; + unsigned int curr_dma_pos, curr_transmitted_size; + unsigned int ret = 0; + + curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); + if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || + (curr_dma_pos == 0)) { + if (jiffies_to_msecs(jiffies - up->port_activity) < + RX_TIMEOUT) { + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + } else { + serial_omap_stop_rxdma(up); + up->ier |= UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + } + return; + } + + curr_transmitted_size = curr_dma_pos - + up->uart_dma.prev_rx_dma_pos; + up->port.icount.rx += curr_transmitted_size; + tty_insert_flip_string(up->port.state->port.tty, + up->uart_dma.rx_buf + + (up->uart_dma.prev_rx_dma_pos - + up->uart_dma.rx_buf_dma_phys), + curr_transmitted_size); + tty_flip_buffer_push(up->port.state->port.tty); + up->uart_dma.prev_rx_dma_pos = curr_dma_pos; + if (up->uart_dma.rx_buf_size + + up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { + ret = serial_omap_start_rxdma(up); + if (ret < 0) { + serial_omap_stop_rxdma(up); + up->ier |= UART_IER_RDI; + serial_out(up, UART_IER, up->ier); + } + } else { + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + } + up->port_activity = jiffies; +} + +static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) +{ + return; +} + +static int serial_omap_start_rxdma(struct uart_omap_port *up) +{ + int ret = 0; + + if (up->uart_dma.rx_dma_channel == -1) { + ret = omap_request_dma(up->uart_dma.uart_dma_rx, + "UART Rx DMA", + (void *)uart_rx_dma_callback, up, + &(up->uart_dma.rx_dma_channel)); + if (ret < 0) + return ret; + + omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, + up->uart_dma.rx_buf_dma_phys, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.rx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_rx, 0); + } + up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.rx_dma_channel); + mod_timer(&up->uart_dma.rx_timer, jiffies + + usecs_to_jiffies(up->uart_dma.rx_timeout)); + up->uart_dma.rx_dma_used = true; + return ret; +} + +static void serial_omap_continue_tx(struct uart_omap_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int start = up->uart_dma.tx_buf_dma_phys + + (xmit->tail & (UART_XMIT_SIZE - 1)); + + if (uart_circ_empty(xmit)) + return; + + up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); + /* + * It is a circular buffer. See if the buffer has wounded back. + * If yes it will have to be transferred in two separate dma + * transfers + */ + if (start + up->uart_dma.tx_buf_size >= + up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) + up->uart_dma.tx_buf_size = + (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; + omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_CONSTANT, + up->uart_dma.uart_base, 0, 0); + omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, + OMAP_DMA_AMODE_POST_INC, start, 0, 0); + omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, + OMAP_DMA_DATA_TYPE_S8, + up->uart_dma.tx_buf_size, 1, + OMAP_DMA_SYNC_ELEMENT, + up->uart_dma.uart_dma_tx, 0); + /* FIXME: Cache maintenance needed here? */ + omap_start_dma(up->uart_dma.tx_dma_channel); +} + +static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) +{ + struct uart_omap_port *up = (struct uart_omap_port *)data; + struct circ_buf *xmit = &up->port.state->xmit; + + xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ + (UART_XMIT_SIZE - 1); + up->port.icount.tx += up->uart_dma.tx_buf_size; + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (uart_circ_empty(xmit)) { + spin_lock(&(up->uart_dma.tx_lock)); + serial_omap_stop_tx(&up->port); + up->uart_dma.tx_dma_used = false; + spin_unlock(&(up->uart_dma.tx_lock)); + } else { + omap_stop_dma(up->uart_dma.tx_dma_channel); + serial_omap_continue_tx(up); + } + up->port_activity = jiffies; + return; +} + +static int serial_omap_probe(struct platform_device *pdev) +{ + struct uart_omap_port *up; + struct resource *mem, *irq, *dma_tx, *dma_rx; + struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; + int ret = -ENOSPC; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "no mem resource?\n"); + return -ENODEV; + } + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!irq) { + dev_err(&pdev->dev, "no irq resource?\n"); + return -ENODEV; + } + + if (!request_mem_region(mem->start, (mem->end - mem->start) + 1, + pdev->dev.driver->name)) { + dev_err(&pdev->dev, "memory region already claimed\n"); + return -EBUSY; + } + + dma_rx = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!dma_rx) { + ret = -EINVAL; + goto err; + } + + dma_tx = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (!dma_tx) { + ret = -EINVAL; + goto err; + } + + up = kzalloc(sizeof(*up), GFP_KERNEL); + if (up == NULL) { + ret = -ENOMEM; + goto do_release_region; + } + sprintf(up->name, "OMAP UART%d", pdev->id); + up->pdev = pdev; + up->port.dev = &pdev->dev; + up->port.type = PORT_OMAP; + up->port.iotype = UPIO_MEM; + up->port.irq = irq->start; + + up->port.regshift = 2; + up->port.fifosize = 64; + up->port.ops = &serial_omap_pops; + up->port.line = pdev->id; + + up->port.membase = omap_up_info->membase; + up->port.mapbase = omap_up_info->mapbase; + up->port.flags = omap_up_info->flags; + up->port.irqflags = omap_up_info->irqflags; + up->port.uartclk = omap_up_info->uartclk; + up->uart_dma.uart_base = mem->start; + + if (omap_up_info->dma_enabled) { + up->uart_dma.uart_dma_tx = dma_tx->start; + up->uart_dma.uart_dma_rx = dma_rx->start; + up->use_dma = 1; + up->uart_dma.rx_buf_size = 4096; + up->uart_dma.rx_timeout = 1; + spin_lock_init(&(up->uart_dma.tx_lock)); + spin_lock_init(&(up->uart_dma.rx_lock)); + up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; + up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; + } + + ui[pdev->id] = up; + serial_omap_add_console_port(up); + + ret = uart_add_one_port(&serial_omap_reg, &up->port); + if (ret != 0) + goto do_release_region; + + platform_set_drvdata(pdev, up); + return 0; +err: + dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", + pdev->id, __func__, ret); +do_release_region: + release_mem_region(mem->start, (mem->end - mem->start) + 1); + return ret; +} + +static int serial_omap_remove(struct platform_device *dev) +{ + struct uart_omap_port *up = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + if (up) { + uart_remove_one_port(&serial_omap_reg, &up->port); + kfree(up); + } + return 0; +} + +static struct platform_driver serial_omap_driver = { + .probe = serial_omap_probe, + .remove = serial_omap_remove, + + .suspend = serial_omap_suspend, + .resume = serial_omap_resume, + .driver = { + .name = DRIVER_NAME, + }, +}; + +int __init serial_omap_init(void) +{ + int ret; + + ret = uart_register_driver(&serial_omap_reg); + if (ret != 0) + return ret; + ret = platform_driver_register(&serial_omap_driver); + if (ret != 0) + uart_unregister_driver(&serial_omap_reg); + return ret; +} + +void __exit serial_omap_exit(void) +{ + platform_driver_unregister(&serial_omap_driver); + uart_unregister_driver(&serial_omap_reg); +} + +module_init(serial_omap_init); +module_exit(serial_omap_exit); + +MODULE_DESCRIPTION("OMAP High Speed UART driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 78dd1e7..caaa311 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -182,6 +182,9 @@ /* Aeroflex Gaisler GRLIB APBUART */ #define PORT_APBUART 90 +/* TI OMAP-UART */ +#define PORT_OMAP 91 + #ifdef __KERNEL__ #include From patchwork Wed Apr 28 14:51:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 95684 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3SEpcFZ009542 for ; Wed, 28 Apr 2010 14:51:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752792Ab0D1Ovh (ORCPT ); Wed, 28 Apr 2010 10:51:37 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:58082 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750859Ab0D1Ovg (ORCPT ); Wed, 28 Apr 2010 10:51:36 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3SEpU9N004704 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Apr 2010 09:51:32 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3SEpOpW027280; Wed, 28 Apr 2010 20:21:25 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Nishanth Menon , Tony Lindgren Subject: [PATCH] OMAP3630: Update ES1.1 silicon revision detection Date: Wed, 28 Apr 2010 20:21:20 +0530 Message-Id: <1272466280-2784-1-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.6.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Apr 2010 14:51:38 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a..dd26092 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -259,11 +259,20 @@ void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; break; case 0xb891: - /* FALLTHROUGH */ - default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; + /* Handle 36xx devices */ omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + /* Fall through */ + default: + /* Use the latest known revision as default */ + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + } } } @@ -339,6 +348,9 @@ void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 7514174..04c7baa 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -66,6 +66,7 @@ unsigned int omap_rev(void); * family. This difference can be handled separately. */ #define OMAP_REVBITS_00 0x00 +#define OMAP_REVBITS_01 0x01 #define OMAP_REVBITS_10 0x10 #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 @@ -376,6 +377,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3430_REV_ES3_1_2 0x34305034 #define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -411,6 +413,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) #define CHIP_IS_OMAP4430ES1 (1 << 8) +#define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) From patchwork Wed May 5 14:27:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97110 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5PE002693 for ; Wed, 5 May 2010 14:28:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934838Ab0EEO2Q (ORCPT ); Wed, 5 May 2010 10:28:16 -0400 Received: from smtp.nokia.com ([192.100.122.230]:65041 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932540Ab0EEO2O (ORCPT ); Wed, 5 May 2010 10:28:14 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ES5AL008349; Wed, 5 May 2010 17:28:11 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:08 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:08 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRJ016232; Wed, 5 May 2010 17:28:06 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 17/21] OMAP: DSS2: Taal: Configure ESD check in DSI panel data Date: Wed, 5 May 2010 17:27:37 +0300 Message-Id: <025c12267d4bd88e1f59d9e13aafec247fe3c730.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <690ef5c45aee3fb87a40fa03039356f8238925dc.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> <690ef5c45aee3fb87a40fa03039356f8238925dc.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:08.0320 (UTC) FILETIME=[2EB5E000:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:21 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 538829b..9502a4d 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -62,7 +62,6 @@ #define DCS_GET_ID2 0xdb #define DCS_GET_ID3 0xdc -/* #define TAAL_USE_ESD_CHECK */ #define TAAL_ESD_CHECK_PERIOD msecs_to_jiffies(5000) static irqreturn_t taal_te_isr(int irq, void *data); @@ -793,6 +792,7 @@ static void taal_power_off(struct omap_dss_device *dssdev) static int taal_enable(struct omap_dss_device *dssdev) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; dev_dbg(&dssdev->dev, "enable\n"); @@ -813,9 +813,9 @@ static int taal_enable(struct omap_dss_device *dssdev) if (r) goto err; -#ifdef TAAL_USE_ESD_CHECK - queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD); -#endif + if (panel_data->use_esd_check) + queue_delayed_work(td->esd_wq, &td->esd_work, + TAAL_ESD_CHECK_PERIOD); dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; @@ -885,6 +885,7 @@ err: static int taal_resume(struct omap_dss_device *dssdev) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; dev_dbg(&dssdev->dev, "resume\n"); @@ -906,10 +907,9 @@ static int taal_resume(struct omap_dss_device *dssdev) dssdev->state = OMAP_DSS_DISPLAY_DISABLED; } else { dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -#ifdef TAAL_USE_ESD_CHECK - queue_delayed_work(td->esd_wq, &td->esd_work, - TAAL_ESD_CHECK_PERIOD); -#endif + if (panel_data->use_esd_check) + queue_delayed_work(td->esd_wq, &td->esd_work, + TAAL_ESD_CHECK_PERIOD); } mutex_unlock(&td->lock); From patchwork Mon May 10 10:37:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 98132 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4AAb1hR006457 for ; Mon, 10 May 2010 10:37:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756601Ab0EJKg7 (ORCPT ); Mon, 10 May 2010 06:36:59 -0400 Received: from smtp.nokia.com ([192.100.105.134]:57442 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756593Ab0EJKg4 (ORCPT ); Mon, 10 May 2010 06:36:56 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4AAZFO8002673; Mon, 10 May 2010 05:35:43 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 May 2010 13:35:40 +0300 Received: from mgw-da02.ext.nokia.com ([147.243.128.26]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 May 2010 13:35:39 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4AAZPpX022644; Mon, 10 May 2010 13:35:33 +0300 From: Eduardo Valentin To: LKML , linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: Russell King , Andrew Morton , ext Tony Lindgren , ext Kevin Hilman , Peter De-Schrijver , santosh.shilimkar@ti.com, Ambresh , felipe.balbi@nokia.com, Eduardo Valentin Subject: [PATCHv4 2/4] mach-omap2: export omap2 info under /proc/socinfo Date: Mon, 10 May 2010 13:37:35 +0300 Message-Id: <1273487857-32281-3-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273487857-32281-1-git-send-email-eduardo.valentin@nokia.com> References: <1273487857-32281-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 10 May 2010 10:35:39.0759 (UTC) FILETIME=[88C91FF0:01CAF02C] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 10 May 2010 10:37:09 +0000 (UTC) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c5408bf..7456967 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -798,6 +798,7 @@ config ARCH_OMAP select GENERIC_TIME select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL + select PROC_SOC_INFO help Support for TI's OMAP platform (OMAP1 and OMAP2). diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a..8ecd8e2 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -18,6 +18,7 @@ #include #include #include +#include #include @@ -101,10 +102,12 @@ static struct omap_id omap_ids[] __initdata = { static void __iomem *tap_base; static u16 tap_prod_id; +#define SOCINFO_SZ 128 +static char socinfo[SOCINFO_SZ]; void __init omap24xx_check_revision(void) { - int i, j; + int i, j, sz; u32 idcode, prod_id; u16 hawkeye; u8 dev_type, rev; @@ -152,10 +155,11 @@ void __init omap24xx_check_revision(void) j = i; } - pr_info("OMAP%04x", omap_rev() >> 16); + sz = snprintf(socinfo, SOCINFO_SZ, "OMAP%04x", omap_rev() >> 16); if ((omap_rev() >> 8) & 0x0f) - pr_info("ES%x", (omap_rev() >> 12) & 0xf); - pr_info("\n"); + snprintf(socinfo + sz, SOCINFO_SZ - sz, "ES%x", + (omap_rev() >> 12) & 0xf); + pr_info("%s\n", socinfo); } #define OMAP3_CHECK_FEATURE(status,feat) \ @@ -286,7 +290,9 @@ void __init omap4_check_revision(void) if ((hawkeye == 0xb852) && (rev == 0x0)) { omap_revision = OMAP4430_REV_ES1_0; omap_chip.oc |= CHIP_IS_OMAP4430ES1; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); + snprintf(socinfo, SOCINFO_SZ, "OMAP%04x %s\n", + omap_rev() >> 16, rev_name); + pr_info("%s\n", socinfo); return; } @@ -356,7 +362,8 @@ void __init omap3_cpuinfo(void) } /* Print verbose information */ - pr_info("%s ES%s (", cpu_name, cpu_rev); + snprintf(socinfo, SOCINFO_SZ, "%s ES%s", cpu_name, cpu_rev); + pr_info("%s (", socinfo); OMAP3_SHOW_FEATURE(l2cache); OMAP3_SHOW_FEATURE(iva); @@ -425,3 +432,32 @@ void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) else tap_prod_id = 0x0208; } + +static int c_show(struct seq_file *m, void *v) +{ + seq_printf(m, "SoC\t: %s\n", socinfo); + + return 0; +} + +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +static void c_stop(struct seq_file *m, void *v) +{ +} + +const struct seq_operations socinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_show +}; From patchwork Wed May 5 14:27:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97112 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESNLh002787 for ; Wed, 5 May 2010 14:28:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934854Ab0EEO2X (ORCPT ); Wed, 5 May 2010 10:28:23 -0400 Received: from smtp.nokia.com ([192.100.122.230]:65036 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934770Ab0EEO2M (ORCPT ); Wed, 5 May 2010 10:28:12 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERrlr008227; Wed, 5 May 2010 17:28:08 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:07 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:06 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRI016232; Wed, 5 May 2010 17:28:05 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 16/21] OMAP: DSS2: Taal: Use Nokia DSI panel data Date: Wed, 5 May 2010 17:27:36 +0300 Message-Id: <690ef5c45aee3fb87a40fa03039356f8238925dc.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:06.0569 (UTC) FILETIME=[2DAAB190:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:25 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 0c259ab..538829b 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -33,6 +33,7 @@ #include #include +#include /* DSI Virtual channel. Hardcoded for now. */ #define TCH 0 @@ -85,7 +86,6 @@ struct taal_data { bool mirror; bool te_enabled; - bool use_ext_te; atomic_t do_update; struct { @@ -107,6 +107,12 @@ struct taal_data { struct delayed_work esd_work; }; +static inline struct nokia_dsi_panel_data +*get_panel_data(const struct omap_dss_device *dssdev) +{ + return (struct nokia_dsi_panel_data *) dssdev->data; +} + static void taal_esd_work(struct work_struct *work); static void hw_guard_start(struct taal_data *td, int guard_msec) @@ -288,6 +294,7 @@ static int taal_bl_update_status(struct backlight_device *dev) { struct omap_dss_device *dssdev = dev_get_drvdata(&dev->dev); struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; int level; @@ -310,10 +317,10 @@ static int taal_bl_update_status(struct backlight_device *dev) r = 0; } } else { - if (!dssdev->set_backlight) + if (!panel_data->set_backlight) r = -EINVAL; else - r = dssdev->set_backlight(dssdev, level); + r = panel_data->set_backlight(dssdev, level); } mutex_unlock(&td->lock); @@ -503,16 +510,18 @@ static struct attribute_group taal_attr_group = { static void taal_hw_reset(struct omap_dss_device *dssdev) { - if (dssdev->reset_gpio == -1) + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); + + if (panel_data->reset_gpio == -1) return; - gpio_set_value(dssdev->reset_gpio, 1); + gpio_set_value(panel_data->reset_gpio, 1); udelay(10); /* reset the panel */ - gpio_set_value(dssdev->reset_gpio, 0); + gpio_set_value(panel_data->reset_gpio, 0); /* assert reset for at least 10us */ udelay(10); - gpio_set_value(dssdev->reset_gpio, 1); + gpio_set_value(panel_data->reset_gpio, 1); /* wait 5ms after releasing reset */ msleep(5); } @@ -522,6 +531,7 @@ static int taal_probe(struct omap_dss_device *dssdev) struct backlight_properties props; struct taal_data *td; struct backlight_device *bldev; + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; const struct omap_video_timings taal_panel_timings = { @@ -531,6 +541,11 @@ static int taal_probe(struct omap_dss_device *dssdev) dev_dbg(&dssdev->dev, "probe\n"); + if (!panel_data || !panel_data->name) { + r = -EINVAL; + goto err; + } + dssdev->panel.config = OMAP_DSS_LCD_TFT; dssdev->panel.timings = taal_panel_timings; dssdev->ctrl.pixel_size = 24; @@ -561,7 +576,7 @@ static int taal_probe(struct omap_dss_device *dssdev) /* if no platform set_backlight() defined, presume DSI backlight * control */ memset(&props, 0, sizeof(props)); - if (!dssdev->set_backlight) + if (!panel_data->set_backlight) td->use_dsi_bl = true; if (td->use_dsi_bl) @@ -586,8 +601,8 @@ static int taal_probe(struct omap_dss_device *dssdev) taal_bl_update_status(bldev); - if (dssdev->phy.dsi.ext_te) { - int gpio = dssdev->phy.dsi.ext_te_gpio; + if (panel_data->use_ext_te) { + int gpio = panel_data->ext_te_gpio; r = gpio_request(gpio, "taal irq"); if (r) { @@ -610,8 +625,6 @@ static int taal_probe(struct omap_dss_device *dssdev) INIT_DELAYED_WORK_DEFERRABLE(&td->te_timeout_work, taal_te_timeout_work_callback); - td->use_ext_te = true; - dev_dbg(&dssdev->dev, "Using GPIO TE\n"); } @@ -623,11 +636,11 @@ static int taal_probe(struct omap_dss_device *dssdev) return 0; err_sysfs: - if (td->use_ext_te) - free_irq(gpio_to_irq(dssdev->phy.dsi.ext_te_gpio), dssdev); + if (panel_data->use_ext_te) + free_irq(gpio_to_irq(panel_data->ext_te_gpio), dssdev); err_irq: - if (td->use_ext_te) - gpio_free(dssdev->phy.dsi.ext_te_gpio); + if (panel_data->use_ext_te) + gpio_free(panel_data->ext_te_gpio); err_gpio: backlight_device_unregister(bldev); err_bl: @@ -641,14 +654,15 @@ err: static void taal_remove(struct omap_dss_device *dssdev) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); struct backlight_device *bldev; dev_dbg(&dssdev->dev, "remove\n"); sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group); - if (td->use_ext_te) { - int gpio = dssdev->phy.dsi.ext_te_gpio; + if (panel_data->use_ext_te) { + int gpio = panel_data->ext_te_gpio; free_irq(gpio_to_irq(gpio), dssdev); gpio_free(gpio); } @@ -958,6 +972,7 @@ static int taal_update(struct omap_dss_device *dssdev, u16 x, u16 y, u16 w, u16 h) { struct taal_data *td = dev_get_drvdata(&dssdev->dev); + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; dev_dbg(&dssdev->dev, "update %d, %d, %d x %d\n", x, y, w, h); @@ -978,7 +993,7 @@ static int taal_update(struct omap_dss_device *dssdev, if (r) goto err; - if (td->te_enabled && td->use_ext_te) { + if (td->te_enabled && panel_data->use_ext_te) { td->update_region.x = x; td->update_region.y = y; td->update_region.w = w; @@ -1021,6 +1036,7 @@ static int taal_sync(struct omap_dss_device *dssdev) static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) { + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; if (enable) @@ -1028,7 +1044,7 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) else r = taal_dcs_write_0(DCS_TEAR_OFF); - if (!td->use_ext_te) + if (!panel_data->use_ext_te) omapdss_dsi_enable_te(dssdev, enable); /* XXX for some reason, DSI TE breaks if we don't wait here. @@ -1272,6 +1288,7 @@ static void taal_esd_work(struct work_struct *work) struct taal_data *td = container_of(work, struct taal_data, esd_work.work); struct omap_dss_device *dssdev = td->dssdev; + struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); u8 state1, state2; int r; @@ -1312,7 +1329,7 @@ static void taal_esd_work(struct work_struct *work) } /* Self-diagnostics result is also shown on TE GPIO line. We need * to re-enable TE after self diagnostics */ - if (td->use_ext_te && td->te_enabled) { + if (td->te_enabled && panel_data->use_ext_te) { r = taal_dcs_write_1(DCS_TEAR_ON, 0); if (r) goto err; From patchwork Wed May 5 14:27:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97113 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESRaX002803 for ; Wed, 5 May 2010 14:28:27 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934858Ab0EEO2Y (ORCPT ); Wed, 5 May 2010 10:28:24 -0400 Received: from smtp.nokia.com ([192.100.122.233]:17877 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934822Ab0EEO2X (ORCPT ); Wed, 5 May 2010 10:28:23 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ESIcO027878; Wed, 5 May 2010 17:28:19 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:18 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:13 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRN016232; Wed, 5 May 2010 17:28:12 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 21/21] OMAP: DSS2: Taal: CABC workaround is Taal specific Date: Wed, 5 May 2010 17:27:41 +0300 Message-Id: <04807eb255f204f61884b06cde6819e0a087ea33.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <1b93af2daf403f2fe822469b71c12ea7eb1cc68a.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> <690ef5c45aee3fb87a40fa03039356f8238925dc.1273067195.git.ext-jani.1.nikula@nokia.com> <025c12267d4bd88e1f59d9e13aafec247fe3c730.1273067195.git.ext-jani.1.nikula@nokia.com> <5e7384699d72bad3865dc9604b18ad05775bfb27.1273067195.git.ext-jani.1.nikula@nokia.com> <1b93af2daf403f2fe822469b71c12ea7eb1cc68a.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:13.0929 (UTC) FILETIME=[320DBD90:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:27 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 617723b..981e38d 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -856,8 +856,9 @@ static int taal_power_on(struct omap_dss_device *dssdev) if (r) goto err; - /* on early revisions CABC is broken */ - if (id2 == 0x00 || id2 == 0xff || id2 == 0x81) + /* on early Taal revisions CABC is broken */ + if (td->panel_config->type == PANEL_TAAL && + (id2 == 0x00 || id2 == 0xff || id2 == 0x81)) td->cabc_broken = true; r = taal_dcs_write_1(DCS_BRIGHTNESS, 0xff); From patchwork Mon May 10 10:37:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 98137 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4AAc28K006717 for ; Mon, 10 May 2010 10:38:02 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756543Ab0EJKhN (ORCPT ); Mon, 10 May 2010 06:37:13 -0400 Received: from smtp.nokia.com ([192.100.105.134]:57445 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756599Ab0EJKg6 (ORCPT ); Mon, 10 May 2010 06:36:58 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4AAZFOL002673; Mon, 10 May 2010 05:35:55 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 May 2010 13:35:47 +0300 Received: from mgw-da02.ext.nokia.com ([147.243.128.26]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 May 2010 13:35:47 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4AAZPpZ022644; Mon, 10 May 2010 13:35:40 +0300 From: Eduardo Valentin To: LKML , linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: Russell King , Andrew Morton , ext Tony Lindgren , ext Kevin Hilman , Peter De-Schrijver , santosh.shilimkar@ti.com, Ambresh , felipe.balbi@nokia.com, Eduardo Valentin Subject: [PATCHv4 4/4] OMAP3: export chip IDCODE, Production ID and Die ID Date: Mon, 10 May 2010 13:37:37 +0300 Message-Id: <1273487857-32281-5-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273487857-32281-1-git-send-email-eduardo.valentin@nokia.com> References: <1273487857-32281-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 10 May 2010 10:35:47.0603 (UTC) FILETIME=[8D760630:01CAF02C] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 10 May 2010 10:38:03 +0000 (UTC) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 839b21b..8010cfb 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1809,6 +1809,8 @@ and is between 256 and 4096 characters. It is defined in the file waiting for the ACK, so if this is set too high interrupts *may* be lost! + omap3_die_id [OMAP] Append DIE ID info under /proc/socinfo + omap_mux= [OMAP] Override bootloader pin multiplexing. Format: ... For example, to override I2C bus2: diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2455dcc..fb8abed 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -169,3 +169,13 @@ config OMAP3_SDRC_AC_TIMING wish to say no. Selecting yes without understanding what is going on could result in system crashes; +config OMAP3_EXPORT_DIE_ID + bool "Export DIE ID code under /proc/socinfo" + depends on ARCH_OMAP3 + default n + help + Say Y here if you need DIE ID code to be exported via /proc/socinfo + in production systems. You will need also to explicitly flag it by + appending the "omap3_die_id" parameter to your boot command line. + + diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 8ecd8e2..9663066 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -77,6 +77,10 @@ EXPORT_SYMBOL(omap_type); /*----------------------------------------------------------------------------*/ #define OMAP_TAP_IDCODE 0x0204 +#define OMAP_TAP_PROD_ID_0 0x0208 +#define OMAP_TAP_PROD_ID_1 0x020c +#define OMAP_TAP_PROD_ID_2 0x0210 +#define OMAP_TAP_PROD_ID_3 0x0214 #define OMAP_TAP_DIE_ID_0 0x0218 #define OMAP_TAP_DIE_ID_1 0x021C #define OMAP_TAP_DIE_ID_2 0x0220 @@ -305,6 +309,7 @@ void __init omap4_check_revision(void) void __init omap3_cpuinfo(void) { + int sz; u8 rev = GET_OMAP_REVISION(); char cpu_name[16], cpu_rev[16]; @@ -362,7 +367,7 @@ void __init omap3_cpuinfo(void) } /* Print verbose information */ - snprintf(socinfo, SOCINFO_SZ, "%s ES%s", cpu_name, cpu_rev); + sz = snprintf(socinfo, SOCINFO_SZ, "%s ES%s", cpu_name, cpu_rev); pr_info("%s (", socinfo); OMAP3_SHOW_FEATURE(l2cache); @@ -373,7 +378,35 @@ void __init omap3_cpuinfo(void) OMAP3_SHOW_FEATURE(192mhz_clk); printk(")\n"); + + /* Append OMAP3 IDCODE and Production ID to system_soc_info */ + snprintf(socinfo + sz, SOCINFO_SZ - sz, + "\nIDCODE\t: %08x\nPr. ID\t: %08x %08x %08x %08x", + read_tap_reg(OMAP_TAP_IDCODE), + read_tap_reg(OMAP_TAP_PROD_ID_0), + read_tap_reg(OMAP_TAP_PROD_ID_1), + read_tap_reg(OMAP_TAP_PROD_ID_2), + read_tap_reg(OMAP_TAP_PROD_ID_3)); + +} + +#ifdef CONFIG_OMAP3_EXPORT_DIE_ID +static int __init omap3_die_id_setup(char *s) +{ + int sz; + + sz = strlen(socinfo); + snprintf(socinfo + sz, SOCINFO_SZ - sz, + "\nDie ID\t: %08x %08x %08x %08x", + read_tap_reg(OMAP_TAP_DIE_ID_0), + read_tap_reg(OMAP_TAP_DIE_ID_1), + read_tap_reg(OMAP_TAP_DIE_ID_2), + read_tap_reg(OMAP_TAP_DIE_ID_3)); + + return 1; } +__setup("omap3_die_id", omap3_die_id_setup); +#endif /* * Try to detect the exact revision of the omap we're running on From patchwork Wed May 5 14:27:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97115 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESTjg002812 for ; Wed, 5 May 2010 14:28:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934843Ab0EEO2T (ORCPT ); Wed, 5 May 2010 10:28:19 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34144 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932540Ab0EEO2R (ORCPT ); Wed, 5 May 2010 10:28:17 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ES7sC005953; Wed, 5 May 2010 09:28:16 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:11 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:10 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRL016232; Wed, 5 May 2010 17:28:09 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 19/21] OMAP: DSS2: Taal: Print panel name in addition to revision Date: Wed, 5 May 2010 17:27:39 +0300 Message-Id: <5e7384699d72bad3865dc9604b18ad05775bfb27.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> <690ef5c45aee3fb87a40fa03039356f8238925dc.1273067195.git.ext-jani.1.nikula@nokia.com> <025c12267d4bd88e1f59d9e13aafec247fe3c730.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:10.0803 (UTC) FILETIME=[3030C030:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:35 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 9f40f32..b73cd12 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -811,8 +811,8 @@ static int taal_power_on(struct omap_dss_device *dssdev) td->enabled = 1; if (!td->intro_printed) { - dev_info(&dssdev->dev, "revision %02x.%02x.%02x\n", - id1, id2, id3); + dev_info(&dssdev->dev, "%s panel revision %02x.%02x.%02x\n", + td->panel_config->name, id1, id2, id3); if (td->cabc_broken) dev_info(&dssdev->dev, "old Taal version, CABC disabled\n"); From patchwork Wed May 5 14:27:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97116 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESTjh002812 for ; Wed, 5 May 2010 14:28:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934860Ab0EEO23 (ORCPT ); Wed, 5 May 2010 10:28:29 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34150 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932540Ab0EEO2U (ORCPT ); Wed, 5 May 2010 10:28:20 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ES7sG005953; Wed, 5 May 2010 09:28:18 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:12 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:05 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRH016232; Wed, 5 May 2010 17:28:04 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 15/21] OMAP: DSS2: Add Nokia DSI command mode panel configuration struct Date: Wed, 5 May 2010 17:27:35 +0300 Message-Id: <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:05.0414 (UTC) FILETIME=[2CFA7460:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:36 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h new file mode 100644 index 0000000..01ab657 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h @@ -0,0 +1,31 @@ +#ifndef __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H +#define __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H + +#include "display.h" + +/** + * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration + * @name: panel name + * @use_ext_te: use external TE + * @ext_te_gpio: external TE GPIO + * @use_esd_check: perform ESD checks + * @max_backlight_level: maximum backlight level + * @set_backlight: pointer to backlight set function + * @get_backlight: pointer to backlight get function + */ +struct nokia_dsi_panel_data { + const char *name; + + int reset_gpio; + + bool use_ext_te; + int ext_te_gpio; + + bool use_esd_check; + + int max_backlight_level; + int (*set_backlight)(struct omap_dss_device *dssdev, int level); + int (*get_backlight)(struct omap_dss_device *dssdev); +}; + +#endif /* __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H */ From patchwork Wed May 5 14:27:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97117 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESTji002812 for ; Wed, 5 May 2010 14:28:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934862Ab0EEO2b (ORCPT ); Wed, 5 May 2010 10:28:31 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34147 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932530Ab0EEO2S (ORCPT ); Wed, 5 May 2010 10:28:18 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ES7sE005953; Wed, 5 May 2010 09:28:17 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:11 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:09 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRK016232; Wed, 5 May 2010 17:28:08 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 18/21] OMAP: DSS2: Taal: Add panel specific configuration structure Date: Wed, 5 May 2010 17:27:38 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <025c12267d4bd88e1f59d9e13aafec247fe3c730.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> <4f2a95d67d2b8004f4a2055681690920ebeb8e8f.1273067195.git.ext-jani.1.nikula@nokia.com> <690ef5c45aee3fb87a40fa03039356f8238925dc.1273067195.git.ext-jani.1.nikula@nokia.com> <025c12267d4bd88e1f59d9e13aafec247fe3c730.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:09.0726 (UTC) FILETIME=[2F8C69E0:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:37 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 9502a4d..9f40f32 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -68,6 +68,58 @@ static irqreturn_t taal_te_isr(int irq, void *data); static void taal_te_timeout_work_callback(struct work_struct *work); static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable); +/** + * struct panel_config - panel configuration + * @name: panel name + * @type: panel type + * @timings: panel resolution + * @sleep: various panel specific delays, passed to msleep() if non-zero + * @reset_sequence: reset sequence timings, passed to udelay() if non-zero + */ +struct panel_config { + const char *name; + int type; + + struct omap_video_timings timings; + + struct { + unsigned int sleep_in; + unsigned int sleep_out; + unsigned int hw_reset; + unsigned int enable_te; + } sleep; + + struct { + unsigned int high; + unsigned int low; + } reset_sequence; +}; + +enum { + PANEL_TAAL, +}; + +static struct panel_config panel_configs[] = { + { + .name = "taal", + .type = PANEL_TAAL, + .timings = { + .x_res = 864, + .y_res = 480, + }, + .sleep = { + .sleep_in = 5, + .sleep_out = 5, + .hw_reset = 5, + .enable_te = 100, /* possible panel bug */ + }, + .reset_sequence = { + .high = 10, + .low = 10, + }, + }, +}; + struct taal_data { struct mutex lock; @@ -104,6 +156,8 @@ struct taal_data { struct workqueue_struct *esd_wq; struct delayed_work esd_work; + + struct panel_config *panel_config; }; static inline struct nokia_dsi_panel_data @@ -173,7 +227,8 @@ static int taal_sleep_in(struct taal_data *td) hw_guard_start(td, 120); - msleep(5); + if (td->panel_config->sleep.sleep_in) + msleep(td->panel_config->sleep.sleep_in); return 0; } @@ -190,7 +245,8 @@ static int taal_sleep_out(struct taal_data *td) hw_guard_start(td, 120); - msleep(5); + if (td->panel_config->sleep.sleep_out) + msleep(td->panel_config->sleep.sleep_out); return 0; } @@ -509,20 +565,24 @@ static struct attribute_group taal_attr_group = { static void taal_hw_reset(struct omap_dss_device *dssdev) { + struct taal_data *td = dev_get_drvdata(&dssdev->dev); struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); if (panel_data->reset_gpio == -1) return; gpio_set_value(panel_data->reset_gpio, 1); - udelay(10); + if (td->panel_config->reset_sequence.high) + udelay(td->panel_config->reset_sequence.high); /* reset the panel */ gpio_set_value(panel_data->reset_gpio, 0); - /* assert reset for at least 10us */ - udelay(10); + /* assert reset */ + if (td->panel_config->reset_sequence.low) + udelay(td->panel_config->reset_sequence.low); gpio_set_value(panel_data->reset_gpio, 1); - /* wait 5ms after releasing reset */ - msleep(5); + /* wait after releasing reset */ + if (td->panel_config->sleep.hw_reset) + msleep(td->panel_config->sleep.hw_reset); } static int taal_probe(struct omap_dss_device *dssdev) @@ -531,12 +591,8 @@ static int taal_probe(struct omap_dss_device *dssdev) struct taal_data *td; struct backlight_device *bldev; struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); - int r; - - const struct omap_video_timings taal_panel_timings = { - .x_res = 864, - .y_res = 480, - }; + struct panel_config *panel_config = NULL; + int r, i; dev_dbg(&dssdev->dev, "probe\n"); @@ -545,8 +601,20 @@ static int taal_probe(struct omap_dss_device *dssdev) goto err; } + for (i = 0; i < ARRAY_SIZE(panel_configs); i++) { + if (strcmp(panel_data->name, panel_configs[i].name) == 0) { + panel_config = &panel_configs[i]; + break; + } + } + + if (!panel_config) { + r = -EINVAL; + goto err; + } + dssdev->panel.config = OMAP_DSS_LCD_TFT; - dssdev->panel.timings = taal_panel_timings; + dssdev->panel.timings = panel_config->timings; dssdev->ctrl.pixel_size = 24; td = kzalloc(sizeof(*td), GFP_KERNEL); @@ -555,6 +623,7 @@ static int taal_probe(struct omap_dss_device *dssdev) goto err; } td->dssdev = dssdev; + td->panel_config = panel_config; mutex_init(&td->lock); @@ -686,9 +755,6 @@ static int taal_power_on(struct omap_dss_device *dssdev) u8 id1, id2, id3; int r; - /* it seems we have to wait a bit until taal is ready */ - msleep(5); - r = omapdss_dsi_display_enable(dssdev); if (r) { dev_err(&dssdev->dev, "failed to enable DSI\n"); @@ -774,7 +840,7 @@ static void taal_power_off(struct omap_dss_device *dssdev) r = taal_dcs_write_0(DCS_DISPLAY_OFF); if (!r) { r = taal_sleep_in(td); - /* wait a bit so that the message goes through */ + /* HACK: wait a bit so that the message goes through */ msleep(10); } @@ -1036,6 +1102,7 @@ static int taal_sync(struct omap_dss_device *dssdev) static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) { + struct taal_data *td = dev_get_drvdata(&dssdev->dev); struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev); int r; @@ -1047,9 +1114,8 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) if (!panel_data->use_ext_te) omapdss_dsi_enable_te(dssdev, enable); - /* XXX for some reason, DSI TE breaks if we don't wait here. - * Panel bug? Needs more studying */ - msleep(100); + if (td->panel_config->sleep.enable_te) + msleep(td->panel_config->sleep.enable_te); return r; } From patchwork Wed May 5 14:27:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97118 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESTjj002812 for ; Wed, 5 May 2010 14:28:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934863Ab0EEO2e (ORCPT ); Wed, 5 May 2010 10:28:34 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34113 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934710Ab0EEO2D (ORCPT ); Wed, 5 May 2010 10:28:03 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERw9u005894; Wed, 5 May 2010 09:28:01 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:00 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:59 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRD016232; Wed, 5 May 2010 17:27:58 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 11/21] OMAP: DSS2: Taal: Check taal_power_on() return value in taal_resume() Date: Wed, 5 May 2010 17:27:31 +0300 Message-Id: <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:59.0413 (UTC) FILETIME=[2966C650:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:44 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index af159c1..7b5f845 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -882,7 +882,10 @@ static int taal_resume(struct omap_dss_device *dssdev) dsi_bus_unlock(); - dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; + if (r) + dssdev->state = OMAP_DSS_DISPLAY_DISABLED; + else + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; mutex_unlock(&td->lock); From patchwork Wed May 5 14:27:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97119 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ESTjk002812 for ; Wed, 5 May 2010 14:28:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934865Ab0EEO2e (ORCPT ); Wed, 5 May 2010 10:28:34 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34117 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934716Ab0EEO2D (ORCPT ); Wed, 5 May 2010 10:28:03 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERjQS005558; Wed, 5 May 2010 09:28:02 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:58 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:27:58 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRC016232; Wed, 5 May 2010 17:27:56 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 10/21] OMAP: DSS2: Taal: Change DSI bus locking to avoid deadlock in ESD work Date: Wed, 5 May 2010 17:27:30 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:27:58.0226 (UTC) FILETIME=[28B1A720:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:47 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 214d3cf..af159c1 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -672,8 +672,6 @@ static int taal_power_on(struct omap_dss_device *dssdev) /* it seems we have to wait a bit until taal is ready */ msleep(5); - dsi_bus_lock(); - r = omapdss_dsi_display_enable(dssdev); if (r) { dev_err(&dssdev->dev, "failed to enable DSI\n"); @@ -744,8 +742,6 @@ static int taal_power_on(struct omap_dss_device *dssdev) omapdss_dsi_vc_enable_hs(TCH, true); - dsi_bus_unlock(); - return 0; err: dev_err(&dssdev->dev, "error while enabling panel, issuing HW reset\n"); @@ -754,8 +750,6 @@ err: omapdss_dsi_display_disable(dssdev); err0: - dsi_bus_unlock(); - return r; } @@ -764,8 +758,6 @@ static void taal_power_off(struct omap_dss_device *dssdev) struct taal_data *td = dev_get_drvdata(&dssdev->dev); int r; - dsi_bus_lock(); - cancel_delayed_work(&td->esd_work); r = taal_dcs_write_0(DCS_DISPLAY_OFF); @@ -784,8 +776,6 @@ static void taal_power_off(struct omap_dss_device *dssdev) omapdss_dsi_display_disable(dssdev); td->enabled = 0; - - dsi_bus_unlock(); } static int taal_enable(struct omap_dss_device *dssdev) @@ -802,7 +792,12 @@ static int taal_enable(struct omap_dss_device *dssdev) goto err; } + dsi_bus_lock(); + r = taal_power_on(dssdev); + + dsi_bus_unlock(); + if (r) goto err; @@ -825,9 +820,13 @@ static void taal_disable(struct omap_dss_device *dssdev) mutex_lock(&td->lock); + dsi_bus_lock(); + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) taal_power_off(dssdev); + dsi_bus_unlock(); + dssdev->state = OMAP_DSS_DISPLAY_DISABLED; mutex_unlock(&td->lock); @@ -847,7 +846,12 @@ static int taal_suspend(struct omap_dss_device *dssdev) goto err; } + dsi_bus_lock(); + taal_power_off(dssdev); + + dsi_bus_unlock(); + dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; mutex_unlock(&td->lock); @@ -872,7 +876,12 @@ static int taal_resume(struct omap_dss_device *dssdev) goto err; } + dsi_bus_lock(); + r = taal_power_on(dssdev); + + dsi_bus_unlock(); + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; mutex_unlock(&td->lock); From patchwork Mon May 10 10:37:34 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 98139 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4AAc28M006717 for ; Mon, 10 May 2010 10:38:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756647Ab0EJKhq (ORCPT ); Mon, 10 May 2010 06:37:46 -0400 Received: from smtp.nokia.com ([192.100.122.230]:61260 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756594Ab0EJKg5 (ORCPT ); Mon, 10 May 2010 06:36:57 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4AAZbV2003113; Mon, 10 May 2010 13:35:38 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 May 2010 13:35:36 +0300 Received: from mgw-da02.ext.nokia.com ([147.243.128.26]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 May 2010 13:35:35 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4AAZPpW022644; Mon, 10 May 2010 13:35:30 +0300 From: Eduardo Valentin To: LKML , linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: Russell King , Andrew Morton , ext Tony Lindgren , ext Kevin Hilman , Peter De-Schrijver , santosh.shilimkar@ti.com, Ambresh , felipe.balbi@nokia.com, Eduardo Valentin Subject: [PATCHv4 1/4] procfs: Introduce socinfo under /proc Date: Mon, 10 May 2010 13:37:34 +0300 Message-Id: <1273487857-32281-2-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273487857-32281-1-git-send-email-eduardo.valentin@nokia.com> References: <1273487857-32281-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 10 May 2010 10:35:36.0259 (UTC) FILETIME=[86B31130:01CAF02C] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 10 May 2010 10:38:04 +0000 (UTC) diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index a4f30fa..039bcb7 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -415,6 +415,7 @@ Table 1-5: Kernel info in /proc bus Directory containing bus specific information cmdline Kernel command line cpuinfo Info about the CPU + socinfo Info about the System on Chip devices Available devices (block and character) dma Used DMS channels filesystems Supported filesystems diff --git a/fs/proc/Kconfig b/fs/proc/Kconfig index 50f8f06..e683d62 100644 --- a/fs/proc/Kconfig +++ b/fs/proc/Kconfig @@ -67,3 +67,10 @@ config PROC_PAGE_MONITOR /proc/pid/smaps, /proc/pid/clear_refs, /proc/pid/pagemap, /proc/kpagecount, and /proc/kpageflags. Disabling these interfaces will reduce the size of the kernel by approximately 4kb. + +config PROC_SOCINFO + default y + depends on PROC_FS + bool "Enable /proc/socinfo" if EMBEDDED + help + Say Y here if you need to see information about the your System on Chip. diff --git a/fs/proc/Makefile b/fs/proc/Makefile index 11a7b5c..7757d44 100644 --- a/fs/proc/Makefile +++ b/fs/proc/Makefile @@ -26,3 +26,4 @@ proc-$(CONFIG_PROC_VMCORE) += vmcore.o proc-$(CONFIG_PROC_DEVICETREE) += proc_devtree.o proc-$(CONFIG_PRINTK) += kmsg.o proc-$(CONFIG_PROC_PAGE_MONITOR) += page.o +proc-$(CONFIG_PROC_SOCINFO) += socinfo.o diff --git a/fs/proc/socinfo.c b/fs/proc/socinfo.c new file mode 100644 index 0000000..05bfc4f --- /dev/null +++ b/fs/proc/socinfo.c @@ -0,0 +1,33 @@ +/* + * fs/proc/socinfo.c + * + * Copyright (C) 2010 Nokia Corporation + * + * Contact: Eduardo Valentin + * + * proc socinfo file + */ +#include +#include +#include +#include + +extern const struct seq_operations socinfo_op; +static int socinfo_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &socinfo_op); +} + +static const struct file_operations proc_socinfo_operations = { + .open = socinfo_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init proc_socinfo_init(void) +{ + proc_create("socinfo", 0, NULL, &proc_socinfo_operations); + return 0; +} +module_init(proc_socinfo_init); From patchwork Tue Jul 20 04:05:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 112949 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6K46G67018955 for ; Tue, 20 Jul 2010 04:06:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750786Ab0GTEGJ (ORCPT ); Tue, 20 Jul 2010 00:06:09 -0400 Received: from mail-iw0-f174.google.com ([209.85.214.174]:55711 "EHLO mail-iw0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750743Ab0GTEGI (ORCPT ); Tue, 20 Jul 2010 00:06:08 -0400 Received: by iwn7 with SMTP id 7so5352484iwn.19 for ; Mon, 19 Jul 2010 21:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=UIeQgkUx18fPoG/OoLrRqnNVF9n83zIb9Jk/d6xrWxU=; b=ZchgIcZO+P6EBo6cEmTOl6deVQx9dpuEKraB3WdWYqVT4AITHVynqyIadxXQYNr9qv suuHx/qLh99homb5FqqHya8g5ovP/hmXvaHgTAooRLwZg03niCjOkWRbmY7RsaOuJOwy PGkLmuQhnpYjmi1isCpUx7O67emDCuvSjAVrY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=oMdxLSwhQ1CQ+8yT5Eag3WkxRVpYAUKpWP+wu2AnS76HzB4fDZc3+XyT9IlnQ19xDG oors9r5Hekla7AzgfyVy3acn+5Krl3Cbmjwue4SevYrMo3VoE6L5KfdOPiEiEHgmkO3j 6yoGZ4jOeujR4fscuN5/4jU/wdfb8ifRBUTqo= Received: by 10.231.156.66 with SMTP id v2mr6570035ibw.107.1279598766418; Mon, 19 Jul 2010 21:06:06 -0700 (PDT) Received: from localhost ([12.130.106.87]) by mx.google.com with ESMTPS id r3sm27094861ibk.19.2010.07.19.21.06.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 19 Jul 2010 21:06:05 -0700 (PDT) From: Cory Maccarrone To: linux-omap@vger.kernel.org Cc: Cory Maccarrone Subject: [PATCH 1/7] [OMAP] gpio: Allow for extended GPIO space Date: Mon, 19 Jul 2010 21:05:35 -0700 Message-Id: <1279598741-18607-2-git-send-email-darkstar6262@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279598741-18607-1-git-send-email-darkstar6262@gmail.com> References: <1279598741-18607-1-git-send-email-darkstar6262@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 20 Jul 2010 04:06:16 +0000 (UTC) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index e2ed952..5bc7a79 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -2,6 +2,24 @@ if ARCH_OMAP menu "TI OMAP Common Features" +config OMAP_GPIO_EXTRA + int + default 128 if OMAP_GPIO_EXTRA128 + default 64 if OMAP_GPIO_EXTRA64 + default 0 + +config OMAP_GPIO_EXTRA64 + bool + help + Add an extra 64 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + +config OMAP_GPIO_EXTRA128 + bool + help + Add an extra 128 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + config ARCH_OMAP_OTG bool diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index de1c604..d21b790 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -86,6 +86,13 @@ extern void omap_gpio_restore_context(void); * The original OMAP-specfic calls should eventually be removed. */ +/* + * Some boards require extra gpio capacity to support external + * devices that need GPIO. + */ + +#define ARCH_NR_GPIOS (256 + CONFIG_OMAP_GPIO_EXTRA) + #include #include From patchwork Sun Aug 8 17:05:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Nikula X-Patchwork-Id: 118279 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o78H59CA007279 for ; Sun, 8 Aug 2010 17:05:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751682Ab0HHREb (ORCPT ); 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Sun, 08 Aug 2010 10:04:29 -0700 (PDT) Received: from localhost (host-94-101-4-66.igua.fi [94.101.4.66]) by mx.google.com with ESMTPS id a48sm6294549eei.1.2010.08.08.10.04.25 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 08 Aug 2010 10:04:26 -0700 (PDT) From: Jarkko Nikula To: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org, Samuel Ortiz , Jarkko Nikula , Carlos Eduardo Aguiar Subject: [PATCH 1/2] mfd: menelaus: Fix mmc slot 2 misconfiguration Date: Sun, 8 Aug 2010 20:05:23 +0300 Message-Id: <1281287124-26693-1-git-send-email-jhnikula@gmail.com> X-Mailer: git-send-email 1.7.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 08 Aug 2010 17:05:09 +0000 (UTC) diff --git a/drivers/mfd/menelaus.c b/drivers/mfd/menelaus.c index a3fb4bc..e02b574 100644 --- a/drivers/mfd/menelaus.c +++ b/drivers/mfd/menelaus.c @@ -356,9 +356,9 @@ int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_en) int b; if (enable) - ret |= 1 << 1; + val |= 1 << 1; else - ret &= ~(1 << 1); + val &= ~(1 << 1); b = menelaus_read_reg(MENELAUS_MCT_CTRL2); b &= ~0x03; b |= power; From patchwork Thu May 6 01:15:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Candelaria Villareal, Jorge" X-Patchwork-Id: 97250 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o461QdmF005057 for ; Thu, 6 May 2010 01:26:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753178Ab0EFB0j (ORCPT ); Wed, 5 May 2010 21:26:39 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:51582 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752538Ab0EFB0h (ORCPT ); Wed, 5 May 2010 21:26:37 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o461Qa6Y005559 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 5 May 2010 20:26:36 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o461QZNp026043; Wed, 5 May 2010 20:26:36 -0500 (CDT) Received: from localhost.localdomain (x0107209-ubuntu.sasken-mty.naucm.ext.ti.com [10.87.231.217]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o461QZVZ018668; Wed, 5 May 2010 20:26:35 -0500 (CDT) From: Jorge Eduardo Candelaria To: linux-omap@vger.kernel.org Cc: Jorge Eduardo Candelaria , Margarita Olaya Cabrera Subject: [PATCH v2 2/2] ARM: McBSP: Add support for omap4 in McBSP driver Date: Wed, 5 May 2010 20:15:46 -0500 Message-Id: <1273108546-2507-3-git-send-email-jorge.candelaria@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1273108546-2507-2-git-send-email-jorge.candelaria@ti.com> References: <1273108546-2507-1-git-send-email-jorge.candelaria@ti.com> <1273108546-2507-2-git-send-email-jorge.candelaria@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 06 May 2010 01:26:41 +0000 (UTC) diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 6696eb6..9a0e788 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -489,7 +489,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -511,7 +511,7 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -587,7 +587,7 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) * Enable wakup behavior, smart idle and all wakeups * REVISIT: some wakeups may be unnecessary */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -610,7 +610,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) /* * Disable wakup behavior, smart idle and all wakeups */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -859,7 +859,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { /* Release the transmitter and receiver */ w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); @@ -889,7 +889,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset transmitter */ tx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { w = MCBSP_READ_CACHE(mcbsp, XCCR); w |= (tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); @@ -899,7 +899,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset receiver */ rx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx) { w = MCBSP_READ_CACHE(mcbsp, RCCR); w |= (rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); From patchwork Wed Jun 30 23:59:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 108973 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5UNrwa6014167 for ; Wed, 30 Jun 2010 23:53:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757601Ab0F3XwH (ORCPT ); Wed, 30 Jun 2010 19:52:07 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:37393 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755393Ab0F3Xud (ORCPT ); Wed, 30 Jun 2010 19:50:33 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5UNoW6c018479 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 30 Jun 2010 18:50:32 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o5UNoV0W014720; Wed, 30 Jun 2010 18:50:31 -0500 (CDT) Received: from localhost (x0095840-desktop.am.dhcp.ti.com [128.247.77.44]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o5UNoVP07686; Wed, 30 Jun 2010 18:50:31 -0500 (CDT) From: Fernando Guzman Lugo To: , Cc: , , , , Fernando Guzman Lugo Subject: [PATCHv3 4/9] dspbridge: remove custom mmu code from tiomap3430.c Date: Wed, 30 Jun 2010 18:59:56 -0500 Message-Id: <1277942401-3566-5-git-send-email-x0095840@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277942401-3566-4-git-send-email-x0095840@ti.com> References: <1277942401-3566-1-git-send-email-x0095840@ti.com> <1277942401-3566-2-git-send-email-x0095840@ti.com> <1277942401-3566-3-git-send-email-x0095840@ti.com> <1277942401-3566-4-git-send-email-x0095840@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 30 Jun 2010 23:53:58 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/_tiomap.h b/drivers/dsp/bridge/core/_tiomap.h index 4aa2358..c41fd8e 100644 --- a/drivers/dsp/bridge/core/_tiomap.h +++ b/drivers/dsp/bridge/core/_tiomap.h @@ -356,7 +356,6 @@ struct bridge_dev_context { /* TC Settings */ bool tc_word_swap_on; /* Traffic Controller Word Swap */ - struct pg_table_attrs *pt_attrs; u32 dsp_per_clks; }; diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 88f5167..96cceea 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -105,56 +105,9 @@ static int bridge_dev_create(OUT struct bridge_dev_context static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, u32 dw_cmd, IN OUT void *pargs); static int bridge_dev_destroy(struct bridge_dev_context *dev_context); -static u32 user_va2_pa(struct mm_struct *mm, u32 address); -static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, - u32 va, u32 size, - struct hw_mmu_map_attrs_t *map_attrs); -static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va, - u32 size, struct hw_mmu_map_attrs_t *attrs); -static int mem_map_vmalloc(struct bridge_dev_context *hDevContext, - u32 ul_mpu_addr, u32 ulVirtAddr, - u32 ul_num_bytes, - struct hw_mmu_map_attrs_t *hw_attrs); bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr); -/* ----------------------------------- Globals */ - -/* Attributes of L2 page tables for DSP MMU */ -struct page_info { - u32 num_entries; /* Number of valid PTEs in the L2 PT */ -}; - -/* Attributes used to manage the DSP MMU page tables */ -struct pg_table_attrs { - spinlock_t pg_lock; /* Critical section object handle */ - - u32 l1_base_pa; /* Physical address of the L1 PT */ - u32 l1_base_va; /* Virtual address of the L1 PT */ - u32 l1_size; /* Size of the L1 PT */ - u32 l1_tbl_alloc_pa; - /* Physical address of Allocated mem for L1 table. May not be aligned */ - u32 l1_tbl_alloc_va; - /* Virtual address of Allocated mem for L1 table. May not be aligned */ - u32 l1_tbl_alloc_sz; - /* Size of consistent memory allocated for L1 table. - * May not be aligned */ - - u32 l2_base_pa; /* Physical address of the L2 PT */ - u32 l2_base_va; /* Virtual address of the L2 PT */ - u32 l2_size; /* Size of the L2 PT */ - u32 l2_tbl_alloc_pa; - /* Physical address of Allocated mem for L2 table. May not be aligned */ - u32 l2_tbl_alloc_va; - /* Virtual address of Allocated mem for L2 table. May not be aligned */ - u32 l2_tbl_alloc_sz; - /* Size of consistent memory allocated for L2 table. - * May not be aligned */ - - u32 l2_num_pages; /* Number of allocated L2 PT */ - /* Array [l2_num_pages] of L2 PT info structs */ - struct page_info *pg_info; -}; /* * This Bridge driver's function interface table. @@ -210,32 +163,6 @@ static struct bridge_drv_interface drv_interface_fxns = { bridge_msg_set_queue_id, }; -static inline void tlb_flush_all(const void __iomem *base) -{ - __raw_writeb(__raw_readb(base + MMU_GFLUSH) | 1, base + MMU_GFLUSH); -} - -static inline void flush_all(struct bridge_dev_context *dev_context) -{ - if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION || - dev_context->dw_brd_state == BRD_HIBERNATION) - wake_dsp(dev_context, NULL); - - tlb_flush_all(dev_context->dw_dsp_mmu_base); -} - -static void bad_page_dump(u32 pa, struct page *pg) -{ - pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa); - pr_emerg("Bad page state in process '%s'\n" - "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n" - "Backtrace:\n", - current->comm, pg, (int)(2 * sizeof(unsigned long)), - (unsigned long)pg->flags, pg->mapping, - page_mapcount(pg), page_count(pg)); - dump_stack(); -} - /* * ======== bridge_drv_entry ======== * purpose: @@ -637,7 +564,6 @@ static int bridge_brd_stop(struct bridge_dev_context *hDevContext) { int status = 0; struct bridge_dev_context *dev_context = hDevContext; - struct pg_table_attrs *pt_attrs; u32 dsp_pwr_state; int clk_status; struct dspbridge_platform_data *pdata = @@ -677,15 +603,6 @@ static int bridge_brd_stop(struct bridge_dev_context *hDevContext) dsp_wdt_enable(false); - /* This is a good place to clear the MMU page tables as well */ - if (dev_context->pt_attrs) { - pt_attrs = dev_context->pt_attrs; - memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size); - memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size); - memset((u8 *) pt_attrs->pg_info, 0x00, - (pt_attrs->l2_num_pages * sizeof(struct page_info))); - } - /* Reset DSP */ (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, OMAP3430_RST1_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); @@ -725,7 +642,6 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) { int status = 0; struct bridge_dev_context *dev_context = hDevContext; - struct pg_table_attrs *pt_attrs; int clk_status; struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; @@ -747,15 +663,6 @@ static int bridge_brd_delete(struct bridge_dev_context *hDevContext) dev_context->dw_brd_state = BRD_STOPPED; /* update board state */ - /* This is a good place to clear the MMU page tables as well */ - if (dev_context->pt_attrs) { - pt_attrs = dev_context->pt_attrs; - memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size); - memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size); - memset((u8 *) pt_attrs->pg_info, 0x00, - (pt_attrs->l2_num_pages * sizeof(struct page_info))); - } - /* Reset DSP */ (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2, OMAP3430_RST1_IVA2, OMAP3430_IVA2_MOD, RM_RSTCTRL); @@ -836,10 +743,6 @@ static int bridge_dev_create(OUT struct bridge_dev_context struct bridge_dev_context *dev_context = NULL; s32 entry_ndx; struct cfg_hostres *resources = pConfig; - struct pg_table_attrs *pt_attrs; - u32 pg_tbl_pa; - u32 pg_tbl_va; - u32 align_size; struct drv_data *drv_datap = dev_get_drvdata(bridge); /* Allocate and initialize a data structure to contain the bridge driver @@ -871,97 +774,11 @@ static int bridge_dev_create(OUT struct bridge_dev_context if (!dev_context->dw_dsp_base_addr) status = -EPERM; - pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL); - if (pt_attrs != NULL) { - /* Assuming that we use only DSP's memory map - * until 0x4000:0000 , we would need only 1024 - * L1 enties i.e L1 size = 4K */ - pt_attrs->l1_size = 0x1000; - align_size = pt_attrs->l1_size; - /* Align sizes are expected to be power of 2 */ - /* we like to get aligned on L1 table size */ - pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size, - align_size, &pg_tbl_pa); - - /* Check if the PA is aligned for us */ - if ((pg_tbl_pa) & (align_size - 1)) { - /* PA not aligned to page table size , - * try with more allocation and align */ - mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa, - pt_attrs->l1_size); - /* we like to get aligned on L1 table size */ - pg_tbl_va = - (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2, - align_size, &pg_tbl_pa); - /* We should be able to get aligned table now */ - pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa; - pt_attrs->l1_tbl_alloc_va = pg_tbl_va; - pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2; - /* Align the PA to the next 'align' boundary */ - pt_attrs->l1_base_pa = - ((pg_tbl_pa) + - (align_size - 1)) & (~(align_size - 1)); - pt_attrs->l1_base_va = - pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa); - } else { - /* We got aligned PA, cool */ - pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa; - pt_attrs->l1_tbl_alloc_va = pg_tbl_va; - pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size; - pt_attrs->l1_base_pa = pg_tbl_pa; - pt_attrs->l1_base_va = pg_tbl_va; - } - if (pt_attrs->l1_base_va) - memset((u8 *) pt_attrs->l1_base_va, 0x00, - pt_attrs->l1_size); - - /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM + - * L4 pages */ - pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6); - pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE * - pt_attrs->l2_num_pages; - align_size = 4; /* Make it u32 aligned */ - /* we like to get aligned on L1 table size */ - pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size, - align_size, &pg_tbl_pa); - pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa; - pt_attrs->l2_tbl_alloc_va = pg_tbl_va; - pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size; - pt_attrs->l2_base_pa = pg_tbl_pa; - pt_attrs->l2_base_va = pg_tbl_va; - - if (pt_attrs->l2_base_va) - memset((u8 *) pt_attrs->l2_base_va, 0x00, - pt_attrs->l2_size); - - pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages * - sizeof(struct page_info), GFP_KERNEL); - dev_dbg(bridge, - "L1 pa %x, va %x, size %x\n L2 pa %x, va " - "%x, size %x\n", pt_attrs->l1_base_pa, - pt_attrs->l1_base_va, pt_attrs->l1_size, - pt_attrs->l2_base_pa, pt_attrs->l2_base_va, - pt_attrs->l2_size); - dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n", - pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info); - } - if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) && - (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL)) - dev_context->pt_attrs = pt_attrs; - else - status = -ENOMEM; - if (DSP_SUCCEEDED(status)) { - spin_lock_init(&pt_attrs->pg_lock); dev_context->tc_word_swap_on = drv_datap->tc_wordswapon; - - /* Set the Clock Divisor for the DSP module */ - udelay(5); /* MMU address is obtained from the host * resources struct */ dev_context->dw_dsp_mmu_base = resources->dw_dmmu_base; - } - if (DSP_SUCCEEDED(status)) { dev_context->hdev_obj = hdev_obj; dev_context->ul_int_mask = 0; /* Store current board state. */ @@ -970,23 +787,6 @@ static int bridge_dev_create(OUT struct bridge_dev_context /* Return ptr to our device state to the DSP API for storage */ *ppDevContext = dev_context; } else { - if (pt_attrs != NULL) { - kfree(pt_attrs->pg_info); - - if (pt_attrs->l2_tbl_alloc_va) { - mem_free_phys_mem((void *) - pt_attrs->l2_tbl_alloc_va, - pt_attrs->l2_tbl_alloc_pa, - pt_attrs->l2_tbl_alloc_sz); - } - if (pt_attrs->l1_tbl_alloc_va) { - mem_free_phys_mem((void *) - pt_attrs->l1_tbl_alloc_va, - pt_attrs->l1_tbl_alloc_pa, - pt_attrs->l1_tbl_alloc_sz); - } - } - kfree(pt_attrs); kfree(dev_context); } func_end: @@ -1054,7 +854,6 @@ static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, */ static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) { - struct pg_table_attrs *pt_attrs; int status = 0; struct bridge_dev_context *dev_context = (struct bridge_dev_context *) hDevContext; @@ -1068,23 +867,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *hDevContext) /* first put the device to stop state */ bridge_brd_delete(dev_context); - if (dev_context->pt_attrs) { - pt_attrs = dev_context->pt_attrs; - kfree(pt_attrs->pg_info); - - if (pt_attrs->l2_tbl_alloc_va) { - mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va, - pt_attrs->l2_tbl_alloc_pa, - pt_attrs->l2_tbl_alloc_sz); - } - if (pt_attrs->l1_tbl_alloc_va) { - mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va, - pt_attrs->l1_tbl_alloc_pa, - pt_attrs->l1_tbl_alloc_sz); - } - kfree(pt_attrs); - - } if (dev_context->resources) { host_res = dev_context->resources; @@ -1315,258 +1097,6 @@ int user_to_dsp_unmap(struct iommu *mmu, u32 da) } /* - * ======== user_va2_pa ======== - * Purpose: - * This function walks through the page tables to convert a userland - * virtual address to physical address - */ -static u32 user_va2_pa(struct mm_struct *mm, u32 address) -{ - pgd_t *pgd; - pmd_t *pmd; - pte_t *ptep, pte; - - pgd = pgd_offset(mm, address); - if (!(pgd_none(*pgd) || pgd_bad(*pgd))) { - pmd = pmd_offset(pgd, address); - if (!(pmd_none(*pmd) || pmd_bad(*pmd))) { - ptep = pte_offset_map(pmd, address); - if (ptep) { - pte = *ptep; - if (pte_present(pte)) - return pte & PAGE_MASK; - } - } - } - - return 0; -} - -/* - * ======== pte_update ======== - * This function calculates the optimum page-aligned addresses and sizes - * Caller must pass page-aligned values - */ -static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, - u32 va, u32 size, - struct hw_mmu_map_attrs_t *map_attrs) -{ - u32 i; - u32 all_bits; - u32 pa_curr = pa; - u32 va_curr = va; - u32 num_bytes = size; - struct bridge_dev_context *dev_context = hDevContext; - int status = 0; - u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB, - HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB - }; - - while (num_bytes && DSP_SUCCEEDED(status)) { - /* To find the max. page size with which both PA & VA are - * aligned */ - all_bits = pa_curr | va_curr; - - for (i = 0; i < 4; i++) { - if ((num_bytes >= page_size[i]) && ((all_bits & - (page_size[i] - - 1)) == 0)) { - status = - pte_set(dev_context->pt_attrs, pa_curr, - va_curr, page_size[i], map_attrs); - pa_curr += page_size[i]; - va_curr += page_size[i]; - num_bytes -= page_size[i]; - /* Don't try smaller sizes. Hopefully we have - * reached an address aligned to a bigger page - * size */ - break; - } - } - } - - return status; -} - -/* - * ======== pte_set ======== - * This function calculates PTE address (MPU virtual) to be updated - * It also manages the L2 page tables - */ -static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va, - u32 size, struct hw_mmu_map_attrs_t *attrs) -{ - u32 i; - u32 pte_val; - u32 pte_addr_l1; - u32 pte_size; - /* Base address of the PT that will be updated */ - u32 pg_tbl_va; - u32 l1_base_va; - /* Compiler warns that the next three variables might be used - * uninitialized in this function. Doesn't seem so. Working around, - * anyways. */ - u32 l2_base_va = 0; - u32 l2_base_pa = 0; - u32 l2_page_num = 0; - int status = 0; - - l1_base_va = pt->l1_base_va; - pg_tbl_va = l1_base_va; - if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) { - /* Find whether the L1 PTE points to a valid L2 PT */ - pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va); - if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) { - pte_val = *(u32 *) pte_addr_l1; - pte_size = hw_mmu_pte_size_l1(pte_val); - } else { - return -EPERM; - } - spin_lock(&pt->pg_lock); - if (pte_size == HW_MMU_COARSE_PAGE_SIZE) { - /* Get the L2 PA from the L1 PTE, and find - * corresponding L2 VA */ - l2_base_pa = hw_mmu_pte_coarse_l1(pte_val); - l2_base_va = - l2_base_pa - pt->l2_base_pa + pt->l2_base_va; - l2_page_num = - (l2_base_pa - - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE; - } else if (pte_size == 0) { - /* L1 PTE is invalid. Allocate a L2 PT and - * point the L1 PTE to it */ - /* Find a free L2 PT. */ - for (i = 0; (i < pt->l2_num_pages) && - (pt->pg_info[i].num_entries != 0); i++) - ;; - if (i < pt->l2_num_pages) { - l2_page_num = i; - l2_base_pa = pt->l2_base_pa + (l2_page_num * - HW_MMU_COARSE_PAGE_SIZE); - l2_base_va = pt->l2_base_va + (l2_page_num * - HW_MMU_COARSE_PAGE_SIZE); - /* Endianness attributes are ignored for - * HW_MMU_COARSE_PAGE_SIZE */ - status = - hw_mmu_pte_set(l1_base_va, l2_base_pa, va, - HW_MMU_COARSE_PAGE_SIZE, - attrs); - } else { - status = -ENOMEM; - } - } else { - /* Found valid L1 PTE of another size. - * Should not overwrite it. */ - status = -EPERM; - } - if (DSP_SUCCEEDED(status)) { - pg_tbl_va = l2_base_va; - if (size == HW_PAGE_SIZE64KB) - pt->pg_info[l2_page_num].num_entries += 16; - else - pt->pg_info[l2_page_num].num_entries++; - dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum " - "%x, num_entries %x\n", l2_base_va, - l2_base_pa, l2_page_num, - pt->pg_info[l2_page_num].num_entries); - } - spin_unlock(&pt->pg_lock); - } - if (DSP_SUCCEEDED(status)) { - dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n", - pg_tbl_va, pa, va, size); - dev_dbg(bridge, "PTE: endianism %x, element_size %x, " - "mixed_size %x\n", attrs->endianism, - attrs->element_size, attrs->mixed_size); - status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs); - } - - return status; -} - -/* Memory map kernel VA -- memory allocated with vmalloc */ -static int mem_map_vmalloc(struct bridge_dev_context *dev_context, - u32 ul_mpu_addr, u32 ulVirtAddr, - u32 ul_num_bytes, - struct hw_mmu_map_attrs_t *hw_attrs) -{ - int status = 0; - struct page *page[1]; - u32 i; - u32 pa_curr; - u32 pa_next; - u32 va_curr; - u32 size_curr; - u32 num_pages; - u32 pa; - u32 num_of4k_pages; - u32 temp = 0; - - /* - * Do Kernel va to pa translation. - * Combine physically contiguous regions to reduce TLBs. - * Pass the translated pa to pte_update. - */ - num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */ - i = 0; - va_curr = ul_mpu_addr; - page[0] = vmalloc_to_page((void *)va_curr); - pa_next = page_to_phys(page[0]); - while (DSP_SUCCEEDED(status) && (i < num_pages)) { - /* - * Reuse pa_next from the previous iteraion to avoid - * an extra va2pa call - */ - pa_curr = pa_next; - size_curr = PAGE_SIZE; - /* - * If the next page is physically contiguous, - * map it with the current one by increasing - * the size of the region to be mapped - */ - while (++i < num_pages) { - page[0] = - vmalloc_to_page((void *)(va_curr + size_curr)); - pa_next = page_to_phys(page[0]); - - if (pa_next == (pa_curr + size_curr)) - size_curr += PAGE_SIZE; - else - break; - - } - if (pa_next == 0) { - status = -ENOMEM; - break; - } - pa = pa_curr; - num_of4k_pages = size_curr / HW_PAGE_SIZE4KB; - while (temp++ < num_of4k_pages) { - get_page(PHYS_TO_PAGE(pa)); - pa += HW_PAGE_SIZE4KB; - } - status = pte_update(dev_context, pa_curr, ulVirtAddr + - (va_curr - ul_mpu_addr), size_curr, - hw_attrs); - va_curr += size_curr; - } - if (DSP_SUCCEEDED(status)) - status = 0; - else - status = -EPERM; - - /* - * In any case, flush the TLB - * This is called from here instead from pte_update to avoid unnecessary - * repetition while mapping non-contiguous physical regions of a virtual - * region - */ - flush_all(dev_context); - dev_dbg(bridge, "%s status %x\n", __func__, status); - return status; -} - -/* * ======== wait_for_start ======== * Wait for the singal from DSP that it has started, or time out. */ From patchwork Sat Jul 10 07:08:33 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vikram pandita X-Patchwork-Id: 111209 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A77WHN008251 for ; Sat, 10 Jul 2010 07:07:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751840Ab0GJHHS (ORCPT ); Sat, 10 Jul 2010 03:07:18 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:33406 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751655Ab0GJHHL (ORCPT ); Sat, 10 Jul 2010 03:07:11 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A77Atj018644 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sat, 10 Jul 2010 02:07:10 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6A778Mo005586; Sat, 10 Jul 2010 02:07:08 -0500 (CDT) Received: from vip-tid (lta0307903-128247075087.am.dhcp.ti.com [128.247.75.87]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6A778P14563; Sat, 10 Jul 2010 02:07:08 -0500 (CDT) Received: from vip-tid (localhost.localdomain [127.0.0.1]) by vip-tid (Postfix) with ESMTP id 6BC8229C826; Sat, 10 Jul 2010 02:08:35 -0500 (CDT) Received: (from vikram@localhost) by vip-tid (8.14.3/8.14.3/Submit) id o6A78Zu7031300; Sat, 10 Jul 2010 02:08:35 -0500 X-Authentication-Warning: vip-tid: vikram set sender to vikram.pandita@ti.com using -f From: Vikram Pandita To: linux-omap@vger.kernel.org Cc: Vikram Pandita Subject: [PATCH 3/3] omap4: SRAM start and size change for EMU/HS devices Date: Sat, 10 Jul 2010 02:08:33 -0500 Message-Id: <1278745713-31255-4-git-send-email-vikram.pandita@ti.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1278745713-31255-3-git-send-email-vikram.pandita@ti.com> References: <1278745713-31255-1-git-send-email-vikram.pandita@ti.com> <1278745713-31255-2-git-send-email-vikram.pandita@ti.com> <1278745713-31255-3-git-send-email-vikram.pandita@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 07:07:32 +0000 (UTC) On OMAP4 the SRAM configuration is: GP Device: Start Address: 0x4030 0000 Size: 0xE000 (56KB) EMU/HS Device: Start Address: 0x4030 4000 Size: 0xA000 (40KB) Implement this mapping in the sram file Signed-off-by: Vikram Pandita --- arch/arm/plat-omap/sram.c | 17 +++++++++++++---- 1 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 112b807..3c7c9a6 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -53,7 +53,7 @@ #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2PLUS) #define SRAM_BOOTLOADER_SZ 0x00 #else #define SRAM_BOOTLOADER_SZ 0x80 @@ -134,9 +134,18 @@ void __init omap_detect_sram(void) omap_sram_size = 0x8000; /* 32K */ } } else if (cpu_is_omap44xx()) { - omap_sram_base = OMAP4_SRAM_PUB_VA; - omap_sram_start = OMAP4_SRAM_PUB_PA; - omap_sram_size = 0xa000; /* 40K */ + if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || + (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { + /* 40K For Public SRAM */ + omap_sram_base = OMAP4_SRAM_PUB_VA; + omap_sram_start = OMAP4_SRAM_PUB_PA; + omap_sram_size = 0xA000; + } else { + /* 56 KB SRAM on GP device */ + omap_sram_base = OMAP4_SRAM_VA; + omap_sram_start = OMAP4_SRAM_PA; + omap_sram_size = 0xE000; + } } else { omap_sram_base = OMAP2_SRAM_PUB_VA; omap_sram_start = OMAP2_SRAM_PUB_PA; From patchwork Wed Jun 16 11:39:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 106479 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5GBeNOJ021041 for ; Wed, 16 Jun 2010 11:40:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758890Ab0FPLkV (ORCPT ); Wed, 16 Jun 2010 07:40:21 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:48883 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758871Ab0FPLkH (ORCPT ); Wed, 16 Jun 2010 07:40:07 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5GBe4v0009598 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 16 Jun 2010 06:40:06 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5GBe0RW004081; Wed, 16 Jun 2010 17:10:02 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: Sukumar Ghorai , Vimal Singh Subject: [PATCH v3 3/8] omap3: add support for NAND on zoom3 board Date: Wed, 16 Jun 2010 17:09:55 +0530 Message-Id: <1276688400-4812-4-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1276688400-4812-3-git-send-email-s-ghorai@ti.com> References: <1276688400-4812-1-git-send-email-s-ghorai@ti.com> <1276688400-4812-2-git-send-email-s-ghorai@ti.com> <1276688400-4812-3-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 16 Jun 2010 11:40:23 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index e7159b0..00f4cfd 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -131,6 +131,7 @@ obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ board-zoom-peripherals.o \ + board-flash.o \ hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 3314704..692c6c6 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -34,6 +34,47 @@ static void __init omap_zoom_map_io(void) static struct omap_board_config_kernel zoom_config[] __initdata = { }; +static struct mtd_partition zoom_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "system", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ + }, + { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, + { + .name = "cache", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, +}; + static void __init omap_zoom_init_irq(void) { omap_board_config = zoom_config; @@ -66,6 +107,8 @@ static void __init omap_zoom_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); zoom_peripherals_init(); + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); zoom_debugboard_init(); omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); From patchwork Wed Jun 23 02:16:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 107529 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5N2GRQ3012060 for ; Wed, 23 Jun 2010 02:16:27 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750998Ab0FWCQ0 (ORCPT ); Tue, 22 Jun 2010 22:16:26 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:45145 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751039Ab0FWCQW (ORCPT ); Tue, 22 Jun 2010 22:16:22 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5N2GKLT021653 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 21:16:20 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5N2GIoL014377; Tue, 22 Jun 2010 21:16:18 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o5N2GIP15216; Tue, 22 Jun 2010 21:16:18 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id B4D91C252; Tue, 22 Jun 2010 21:16:17 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Venkatraman S , Senthilvadivu Guruswamy , Tony Lindgren , Nishanth Menon Subject: [PATCH 7/9] omap: introduce omap4 feature Date: Tue, 22 Jun 2010 21:16:13 -0500 Message-Id: <1277259375-18521-8-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277259375-18521-1-git-send-email-nm@ti.com> References: <1277259375-18521-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 23 Jun 2010 02:16:28 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 01555b6..e3f5994 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -267,6 +267,19 @@ static void __init omap3_check_revision(void) } } +static void __init omap4_check_features(void) +{ + /* + * TODO: add a better check feature once we have + * more decent feature check + */ + if (cpu_is_omap4430()) + omap_features |= OMAP_HAS_L2CACHE | + OMAP_HAS_IVA | + OMAP_HAS_SGX | + OMAP_HAS_NEON; +} + static void __init omap4_check_revision(void) { u32 idcode; @@ -382,6 +395,7 @@ void __init omap2_check_revision(void) return; } else if (cpu_is_omap44xx()) { omap4_check_revision(); + omap4_check_features(); return; } else { pr_err("OMAP revision unknown, please fix!\n"); From patchwork Wed Jun 23 02:16:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 107527 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5N2GPlf012042 for ; Wed, 23 Jun 2010 02:16:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751356Ab0FWCQX (ORCPT ); Tue, 22 Jun 2010 22:16:23 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:45674 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750998Ab0FWCQW (ORCPT ); Tue, 22 Jun 2010 22:16:22 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5N2GLGe026813 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 21:16:21 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5N2GJGD014383; Tue, 22 Jun 2010 21:16:19 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o5N2GIP15235; Tue, 22 Jun 2010 21:16:19 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id BE7CFC256; Tue, 22 Jun 2010 21:16:17 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Venkatraman S , Senthilvadivu Guruswamy , Tony Lindgren , Nishanth Menon Subject: [PATCH 8/9] omap: introduce omap24xx generic features Date: Tue, 22 Jun 2010 21:16:14 -0500 Message-Id: <1277259375-18521-9-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277259375-18521-1-git-send-email-nm@ti.com> References: <1277259375-18521-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 23 Jun 2010 02:16:25 +0000 (UTC) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index e3f5994..fe634dd 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -102,6 +102,16 @@ static struct omap_id omap_ids[] __initdata = { static void __iomem *tap_base; static u16 tap_prod_id; +static void __init omap24xx_check_features(void) +{ + /* + * TODO: add a better check feature once we have + * more decent feature check + */ + omap_features |= OMAP_HAS_L2CACHE | + OMAP_HAS_IVA; +} + static void __init omap24xx_check_revision(void) { int i, j; @@ -388,6 +398,7 @@ void __init omap2_check_revision(void) */ if (cpu_is_omap24xx()) { omap24xx_check_revision(); + omap24xx_check_features(); } else if (cpu_is_omap34xx()) { omap3_check_revision(); omap3_check_features(); From patchwork Wed Jun 16 11:39:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukumar Ghorai X-Patchwork-Id: 106475 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5GBeEnZ020994 for ; Wed, 16 Jun 2010 11:40:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758888Ab0FPLkL (ORCPT ); Wed, 16 Jun 2010 07:40:11 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:36775 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758881Ab0FPLkI (ORCPT ); Wed, 16 Jun 2010 07:40:08 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5GBe5fb003611 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 16 Jun 2010 06:40:07 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5GBe0RY004081; Wed, 16 Jun 2010 17:10:03 +0530 (IST) From: Sukumar Ghorai To: linux-omap@vger.kernel.org Cc: Sukumar Ghorai , Vimal Singh Subject: [PATCH v3 5/8] omap3: add support for NAND on LDP board Date: Wed, 16 Jun 2010 17:09:57 +0530 Message-Id: <1276688400-4812-6-git-send-email-s-ghorai@ti.com> X-Mailer: git-send-email 1.5.4.7 In-Reply-To: <1276688400-4812-5-git-send-email-s-ghorai@ti.com> References: <1276688400-4812-1-git-send-email-s-ghorai@ti.com> <1276688400-4812-2-git-send-email-s-ghorai@ti.com> <1276688400-4812-3-git-send-email-s-ghorai@ti.com> <1276688400-4812-4-git-send-email-s-ghorai@ti.com> <1276688400-4812-5-git-send-email-s-ghorai@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 16 Jun 2010 11:40:14 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 6c67126..af715fa 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -108,6 +108,7 @@ obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ + board-flash.o \ hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ hsmmc.o diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index fefd7e6..778afab 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -388,6 +389,38 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; +static struct mtd_partition ldp_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "File System - NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = MTDPART_SIZ_FULL, /* 96MB, 0x6000000 */ + }, + +}; + static void __init omap_ldp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -400,6 +433,8 @@ static void __init omap_ldp_init(void) ads7846_dev_init(); omap_serial_init(); usb_musb_init(&musb_board_data); + board_nand_init(ldp_nand_partitions, + ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ From patchwork Fri Mar 12 15:39:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 85268 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2CDshL0000493 for ; Fri, 12 Mar 2010 13:54:43 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757955Ab0CLNym (ORCPT ); Fri, 12 Mar 2010 08:54:42 -0500 Received: from smtp.nokia.com ([192.100.105.134]:53980 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757705Ab0CLNyl (ORCPT ); Fri, 12 Mar 2010 08:54:41 -0500 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CDrxZ5008613 for ; Fri, 12 Mar 2010 07:54:40 -0600 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 15:54:35 +0200 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Mar 2010 15:54:34 +0200 Received: from localhost.localdomain (sokoban.nmp.nokia.com [172.22.215.13]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2CDsV8i003701 for ; Fri, 12 Mar 2010 15:54:32 +0200 From: Tero Kristo To: linux-omap@vger.kernel.org Subject: [PATCHv7 1/7] OMAP3: PM: Added support functions for omap3 pwrdm handling Date: Fri, 12 Mar 2010 17:39:11 +0200 Message-Id: <1268408357-15621-1-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <> References: <> X-OriginalArrivalTime: 12 Mar 2010 13:54:35.0307 (UTC) FILETIME=[8C8DF7B0:01CAC1EB] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 12 Mar 2010 13:54:46 +0000 (UTC) diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index b761be5..5f35911 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -67,6 +67,8 @@ static inline void omap3_pm_init_vc(struct prm_setup_vc *setup_vc) extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); +extern int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); +extern int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm); extern u32 wakeup_timer_seconds; extern struct omap_dm_timer *gptimer_wakeup; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index a30941a..da4e684 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -576,6 +576,68 @@ int omap3_can_sleep(void) return 1; } +struct powerdomain_data { + u8 next_state; +}; + +static struct powerdomain_data mpu_pwrdm_data; +static struct powerdomain_data core_pwrdm_data; +static struct powerdomain_data neon_pwrdm_data; + +static struct powerdomain_data *get_pwrdm_data(struct powerdomain *pwrdm) +{ + if (pwrdm == mpu_pwrdm) + return &mpu_pwrdm_data; + else if (pwrdm == core_pwrdm) + return &core_pwrdm_data; + else if (pwrdm == neon_pwrdm) + return &neon_pwrdm_data; + return NULL; +} + +static void omap3_pwrdm_init_pwrst_cache(struct powerdomain *pwrdm) +{ + struct powerdomain_data *data = get_pwrdm_data(pwrdm); + if (data) + data->next_state = pwrdm_read_next_pwrst(pwrdm); +} + +int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + struct powerdomain_data *data = get_pwrdm_data(pwrdm); + u8 prg_pwrst; + + if (!data) + return pwrdm_set_next_pwrst(pwrdm, pwrst); + + if (data->next_state == pwrst) + return 0; + + if (pwrst == PWRDM_POWER_INACTIVE) + prg_pwrst = PWRDM_POWER_ON; + else + prg_pwrst = pwrst; + + pwrdm_set_next_pwrst(pwrdm, prg_pwrst); + + if (pwrst == PWRDM_POWER_ON) + omap2_clkdm_deny_idle(pwrdm->pwrdm_clkdms[0]); + else + omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); + + data->next_state = pwrst; + return 0; +} + +int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + struct powerdomain_data *data = get_pwrdm_data(pwrdm); + + if (!data) + return pwrdm_read_next_pwrst(pwrdm); + return data->next_state; +} + /* This sets pwrdm state (other than mpu & core. Currently only ON & * RET are supported. Function is assuming that clkdm doesn't have * hw_sup mode enabled. */ @@ -604,7 +666,7 @@ int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) pwrdm_wait_transition(pwrdm); } - ret = pwrdm_set_next_pwrst(pwrdm, state); + ret = omap3_pwrdm_set_next_pwrst(pwrdm, state); if (ret) { printk(KERN_ERR "Unable to set state of powerdomain: %s\n", pwrdm->name); @@ -1103,6 +1165,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) if (!pwrdm->pwrsts) return 0; + omap3_pwrdm_init_pwrst_cache(pwrdm); pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); if (!pwrst) return -ENOMEM; From patchwork Wed Jun 23 00:11:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 107522 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5N0C8TU022157 for ; Wed, 23 Jun 2010 00:12:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752985Ab0FWALv (ORCPT ); Tue, 22 Jun 2010 20:11:51 -0400 Received: from mail-ww0-f46.google.com ([74.125.82.46]:46372 "EHLO mail-ww0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752914Ab0FWALt (ORCPT ); Tue, 22 Jun 2010 20:11:49 -0400 Received: by wwc33 with SMTP id 33so584186wwc.19 for ; Tue, 22 Jun 2010 17:11:48 -0700 (PDT) Received: by 10.227.127.85 with SMTP id f21mr6945288wbs.115.1277251908207; Tue, 22 Jun 2010 17:11:48 -0700 (PDT) Received: from localhost.localdomain (89-139-43-41.bb.netvision.net.il [89.139.43.41]) by mx.google.com with ESMTPS id d37sm5042171wej.42.2010.06.22.17.11.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 22 Jun 2010 17:11:47 -0700 (PDT) From: Ohad Ben-Cohen To: Cc: Hiroshi Doyu , Omar Ramirez Luna , Ohad Ben-Cohen Subject: [PATCH 4/4] dspbridge: use mailbox API to set rx callback Date: Wed, 23 Jun 2010 03:11:36 +0300 Message-Id: <1277251896-6890-4-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1277251896-6890-1-git-send-email-ohad@wizery.com> References: <1277251896-6890-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 23 Jun 2010 00:12:10 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 35c6678..1190c79 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -555,7 +555,7 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, * Enable Mailbox events and also drain any pending * stale messages. */ - dev_context->mbox = omap_mbox_get("dsp"); + dev_context->mbox = omap_mbox_get("dsp", (int (*)(void *))io_mbox_msg); if (IS_ERR(dev_context->mbox)) { dev_context->mbox = NULL; pr_err("%s: Failed to get dsp mailbox handle\n", @@ -565,8 +565,6 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, } if (DSP_SUCCEEDED(status)) { - dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg; - /*PM_IVA2GRPSEL_PER = 0xC0;*/ temp = (u32) *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)); From patchwork Sat Jul 10 02:23:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sapiens, Rene" X-Patchwork-Id: 111202 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6A2Tmfw002688 for ; Sat, 10 Jul 2010 02:29:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753988Ab0GJC2h (ORCPT ); Fri, 9 Jul 2010 22:28:37 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:45285 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752366Ab0GJCZS (ORCPT ); Fri, 9 Jul 2010 22:25:18 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PC0u007085 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Jul 2010 21:25:12 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6A2PB3B014566; Fri, 9 Jul 2010 21:25:11 -0500 (CDT) Received: from localhost.localdomain (renesapiens.sasken-mty.naucm.ext.ti.com [10.87.230.77]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6A2P68G021595; Fri, 9 Jul 2010 21:25:11 -0500 (CDT) From: Rene Sapiens To: greg@kroah.com Cc: gregkh@suse.de, omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Rene Sapiens Subject: [PATCH 04/15] staging:ti dspbridge: Rename words with camel case Date: Fri, 9 Jul 2010 21:23:58 -0500 Message-Id: <1278728649-21012-5-git-send-email-rene.sapiens@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> References: <1278728649-21012-1-git-send-email-rene.sapiens@ti.com> <1278728649-21012-2-git-send-email-rene.sapiens@ti.com> <1278728649-21012-3-git-send-email-rene.sapiens@ti.com> <1278728649-21012-4-git-send-email-rene.sapiens@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 10 Jul 2010 02:29:49 +0000 (UTC) The intention of this patch is to rename the remaining variables with camel case. Variables will be renamed avoiding camel case and Hungarian notation. The words to be renamed in this patch are: ======================================== pArb to arb pbAlreadyAttached to already_attached pBaseAddr to base_addr pbHostBuf to host_buff pBufVa to buf_va pChnlInfo to channel_info pConfig to config_param pContent to content pContext to context pdcdProps to dcd_prop pDepLibUuids to dep_lib_uuids pDevNodeString to dev_node_strg pDispAttrs to disp_attrs pDsp to dsp pdwAutoStart to auto_start pdwChnl to chnl ======================================== Signed-off-by: Rene Sapiens --- drivers/staging/tidspbridge/core/chnl_sm.c | 6 ++-- drivers/staging/tidspbridge/core/tiomap3430.c | 36 ++++++++++---------- drivers/staging/tidspbridge/core/tiomap_io.c | 16 ++++---- drivers/staging/tidspbridge/core/tiomap_io.h | 6 ++-- .../staging/tidspbridge/include/dspbridge/cfg.h | 6 ++-- .../staging/tidspbridge/include/dspbridge/cmm.h | 4 +- .../staging/tidspbridge/include/dspbridge/cod.h | 4 +- .../staging/tidspbridge/include/dspbridge/dbdcd.h | 6 ++-- .../staging/tidspbridge/include/dspbridge/dev.h | 14 ++++---- .../staging/tidspbridge/include/dspbridge/disp.h | 6 ++-- .../staging/tidspbridge/include/dspbridge/drv.h | 12 +++--- .../tidspbridge/include/dspbridge/dspdefs.h | 10 +++--- .../staging/tidspbridge/include/dspbridge/io_sm.h | 16 ++++---- drivers/staging/tidspbridge/pmgr/cmm.c | 6 ++-- drivers/staging/tidspbridge/pmgr/cod.c | 4 +- drivers/staging/tidspbridge/pmgr/dbll.c | 10 +++--- drivers/staging/tidspbridge/pmgr/dev.c | 14 ++++---- drivers/staging/tidspbridge/rmgr/dbdcd.c | 14 ++++---- drivers/staging/tidspbridge/rmgr/disp.c | 10 +++--- drivers/staging/tidspbridge/rmgr/drv.c | 14 ++++---- drivers/staging/tidspbridge/rmgr/node.c | 12 +++--- drivers/staging/tidspbridge/services/cfg.c | 10 +++--- 22 files changed, 118 insertions(+), 118 deletions(-) mode change 100644 => 100755 drivers/staging/tidspbridge/core/tiomap3430.c mode change 100644 => 100755 drivers/staging/tidspbridge/include/dspbridge/io_sm.h diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 362e01e..834172d 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -80,7 +80,7 @@ static void free_chirp_list(struct lst_list *pList); static struct chnl_irp *make_new_chirp(void); static int search_free_channel(struct chnl_mgr *chnl_mgr_obj, - OUT u32 *pdwChnl); + OUT u32 *chnl); /* * ======== bridge_chnl_add_io_req ======== @@ -996,7 +996,7 @@ static struct chnl_irp *make_new_chirp(void) * Search for a free channel slot in the array of channel pointers. */ static int search_free_channel(struct chnl_mgr *chnl_mgr_obj, - OUT u32 *pdwChnl) + OUT u32 *chnl) { int status = -ENOSR; u32 i; @@ -1006,7 +1006,7 @@ static int search_free_channel(struct chnl_mgr *chnl_mgr_obj, for (i = 0; i < chnl_mgr_obj->max_channels; i++) { if (chnl_mgr_obj->ap_channel[i] == NULL) { status = 0; - *pdwChnl = i; + *chnl = i; break; } } diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 7ed0382..dd7436d --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -76,7 +76,7 @@ /* Forward Declarations: */ static int bridge_brd_monitor(struct bridge_dev_context *dev_context); static int bridge_brd_read(struct bridge_dev_context *dev_context, - OUT u8 *pbHostBuf, + OUT u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); static int bridge_brd_start(struct bridge_dev_context *dev_context, @@ -85,7 +85,7 @@ static int bridge_brd_status(struct bridge_dev_context *dev_context, int *pdwState); static int bridge_brd_stop(struct bridge_dev_context *dev_context); static int bridge_brd_write(struct bridge_dev_context *dev_context, - IN u8 *pbHostBuf, + IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt, @@ -94,7 +94,7 @@ static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt, u32 ulDspDestAddr, u32 ulDspSrcAddr, u32 ul_num_bytes, u32 ulMemType); static int bridge_brd_mem_write(struct bridge_dev_context *dev_context, - IN u8 *pbHostBuf, u32 dsp_addr, + IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt, u32 ul_mpu_addr, u32 ulVirtAddr, @@ -105,7 +105,7 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt, static int bridge_dev_create(OUT struct bridge_dev_context **ppDevContext, struct dev_object *hdev_obj, - IN struct cfg_hostres *pConfig); + IN struct cfg_hostres *config_param); static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, u32 dw_cmd, IN OUT void *pargs); static int bridge_dev_destroy(struct bridge_dev_context *dev_context); @@ -304,7 +304,7 @@ static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt) * Reads buffers for DSP memory. */ static int bridge_brd_read(struct bridge_dev_context *dev_ctxt, - OUT u8 *pbHostBuf, u32 dsp_addr, + OUT u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; @@ -321,12 +321,12 @@ static int bridge_brd_read(struct bridge_dev_context *dev_ctxt, dev_context->dw_internal_size) { offset = dsp_addr - dev_context->dw_dsp_start_add; } else { - status = read_ext_dsp_data(dev_context, pbHostBuf, dsp_addr, + status = read_ext_dsp_data(dev_context, host_buff, dsp_addr, ul_num_bytes, ulMemType); return status; } /* copy the data from DSP memory, */ - memcpy(pbHostBuf, (void *)(dsp_base_addr + offset), ul_num_bytes); + memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes); return status; } @@ -765,7 +765,7 @@ static int bridge_brd_status(struct bridge_dev_context *dev_ctxt, * Copies the buffers to DSP internal or external memory. */ static int bridge_brd_write(struct bridge_dev_context *dev_ctxt, - IN u8 *pbHostBuf, u32 dsp_addr, + IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; @@ -777,10 +777,10 @@ static int bridge_brd_write(struct bridge_dev_context *dev_ctxt, } if ((dsp_addr - dev_context->dw_dsp_start_add) < dev_context->dw_internal_size) { - status = write_dsp_data(dev_ctxt, pbHostBuf, dsp_addr, + status = write_dsp_data(dev_ctxt, host_buff, dsp_addr, ul_num_bytes, ulMemType); } else { - status = write_ext_dsp_data(dev_context, pbHostBuf, dsp_addr, + status = write_ext_dsp_data(dev_context, host_buff, dsp_addr, ul_num_bytes, ulMemType, false); } @@ -794,12 +794,12 @@ static int bridge_brd_write(struct bridge_dev_context *dev_ctxt, static int bridge_dev_create(OUT struct bridge_dev_context **ppDevContext, struct dev_object *hdev_obj, - IN struct cfg_hostres *pConfig) + IN struct cfg_hostres *config_param) { int status = 0; struct bridge_dev_context *dev_context = NULL; s32 entry_ndx; - struct cfg_hostres *resources = pConfig; + struct cfg_hostres *resources = config_param; struct pg_table_attrs *pt_attrs; u32 pg_tbl_pa; u32 pg_tbl_va; @@ -825,10 +825,10 @@ static int bridge_dev_create(OUT struct bridge_dev_context dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0; } dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *) - (pConfig-> + (config_param-> dw_mem_base [3]), - pConfig-> + config_param-> dw_mem_length [3]); if (!dev_context->dw_dsp_base_addr) @@ -1147,7 +1147,7 @@ static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt, /* Mem Write does not halt the DSP to write unlike bridge_brd_write */ static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt, - IN u8 *pbHostBuf, u32 dsp_addr, + IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; @@ -1161,16 +1161,16 @@ static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt, if (dsp_addr < (dev_context->dw_dsp_start_add + dev_context->dw_internal_size)) { status = - write_dsp_data(dev_ctxt, pbHostBuf, dsp_addr, + write_dsp_data(dev_ctxt, host_buff, dsp_addr, ul_bytes, ulMemType); } else { - status = write_ext_dsp_data(dev_ctxt, pbHostBuf, + status = write_ext_dsp_data(dev_ctxt, host_buff, dsp_addr, ul_bytes, ulMemType, true); } ul_remain_bytes -= ul_bytes; dsp_addr += ul_bytes; - pbHostBuf = pbHostBuf + ul_bytes; + host_buff = host_buff + ul_bytes; } return status; } diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c index 945f871..0ac4f8c 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.c +++ b/drivers/staging/tidspbridge/core/tiomap_io.c @@ -51,7 +51,7 @@ bool symbols_reloaded = true; * Copies DSP external memory buffers to the host side buffers. */ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt, - OUT u8 *pbHostBuf, u32 dsp_addr, + OUT u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; @@ -168,7 +168,7 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt, offset = dsp_addr - ul_ext_base; if (DSP_SUCCEEDED(status)) - memcpy(pbHostBuf, (u8 *) dw_base_addr + offset, ul_num_bytes); + memcpy(host_buff, (u8 *) dw_base_addr + offset, ul_num_bytes); return status; } @@ -179,7 +179,7 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt, * Copies buffers to the DSP internal/external memory. */ int write_dsp_data(struct bridge_dev_context *dev_ctxt, - IN u8 *pbHostBuf, u32 dsp_addr, u32 ul_num_bytes, + IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType) { u32 offset; @@ -211,9 +211,9 @@ int write_dsp_data(struct bridge_dev_context *dev_ctxt, return -EPERM; } if (ul_num_bytes) - memcpy((u8 *) (dw_base_addr + offset), pbHostBuf, ul_num_bytes); + memcpy((u8 *) (dw_base_addr + offset), host_buff, ul_num_bytes); else - *((u32 *) pbHostBuf) = dw_base_addr + offset; + *((u32 *) host_buff) = dw_base_addr + offset; return status; } @@ -225,7 +225,7 @@ int write_dsp_data(struct bridge_dev_context *dev_ctxt, * */ int write_ext_dsp_data(struct bridge_dev_context *dev_context, - IN u8 *pbHostBuf, u32 dsp_addr, + IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType, bool dynamic_load) { @@ -371,10 +371,10 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context, } if (DSP_SUCCEEDED(ret)) { if (ul_num_bytes) - memcpy((u8 *) dw_base_addr + dw_offset, pbHostBuf, + memcpy((u8 *) dw_base_addr + dw_offset, host_buff, ul_num_bytes); else - *((u32 *) pbHostBuf) = dw_base_addr + dw_offset; + *((u32 *) host_buff) = dw_base_addr + dw_offset; } /* Unmap here to force remap for other Ext loads */ if ((dynamic_load || trace_load) && dev_context->dw_dsp_ext_base_addr) { diff --git a/drivers/staging/tidspbridge/core/tiomap_io.h b/drivers/staging/tidspbridge/core/tiomap_io.h index b398f54..cff8691 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.h +++ b/drivers/staging/tidspbridge/core/tiomap_io.h @@ -48,14 +48,14 @@ * is configured by the combination of DSP MMU and shm Memory manager in the CDB */ extern int read_ext_dsp_data(struct bridge_dev_context *dev_context, - OUT u8 *pbHostBuf, u32 dsp_addr, + OUT u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); /* * ======== write_dsp_data ======== */ extern int write_dsp_data(struct bridge_dev_context *dev_context, - OUT u8 *pbHostBuf, u32 dsp_addr, + OUT u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType); /* @@ -65,7 +65,7 @@ extern int write_dsp_data(struct bridge_dev_context *dev_context, * shm Memory manager in the CDB */ extern int write_ext_dsp_data(struct bridge_dev_context *dev_context, - IN u8 *pbHostBuf, u32 dsp_addr, + IN u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes, u32 ulMemType, bool dynamic_load); diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfg.h b/drivers/staging/tidspbridge/include/dspbridge/cfg.h index 58064e0..0eadd71 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cfg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cfg.h @@ -40,7 +40,7 @@ extern void cfg_exit(void); * Retreive the autostart mask, if any, for this board. * Parameters: * dev_node_obj: Handle to the dev_node who's driver we are querying. - * pdwAutoStart: Ptr to location for 32 bit autostart mask. + * auto_start: Ptr to location for 32 bit autostart mask. * Returns: * 0: Success. * -EFAULT: dev_node_obj is invalid. @@ -48,10 +48,10 @@ extern void cfg_exit(void); * Requires: * CFG initialized. * Ensures: - * 0: *pdwAutoStart contains autostart mask for this devnode. + * 0: *auto_start contains autostart mask for this devnode. */ extern int cfg_get_auto_start(IN struct cfg_devnode *dev_node_obj, - OUT u32 *pdwAutoStart); + OUT u32 *auto_start); /* * ======== cfg_get_cd_version ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index 5fbb051..d36972e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -325,7 +325,7 @@ extern int cmm_xlator_delete(struct cmm_xlatorobject *xlator, * Does not free client process VM. * Parameters: * xlator: handle to translator. - * pBufVa Virtual address of PA to free. + * buf_va Virtual address of PA to free. * Returns: * 0: Success. * -EFAULT: Bad translator handle. @@ -334,7 +334,7 @@ extern int cmm_xlator_delete(struct cmm_xlatorobject *xlator, * */ extern int cmm_xlator_free_buf(struct cmm_xlatorobject *xlator, - void *pBufVa); + void *buf_va); /* * ======== cmm_xlator_info ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index ae711df..92f3cf7 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -279,7 +279,7 @@ extern bool cod_init(void); * num_argc: number of arguments in the args array * args: array of strings for arguments to DSP program * write_fxn: board-specific function to write data to DSP system - * pArb: arbitrary pointer to be passed as first arg to write_fxn + * arb: arbitrary pointer to be passed as first arg to write_fxn * envp: array of environment strings for DSP exec. * Returns: * 0: Success. @@ -295,7 +295,7 @@ extern bool cod_init(void); */ extern int cod_load_base(struct cod_manager *cod_mgr_obj, u32 num_argc, char *args[], - cod_writefxn pfn_write, void *pArb, + cod_writefxn pfn_write, void *arb, char *envp[]); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h index 6658b74..2a2b655 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h @@ -154,7 +154,7 @@ extern void dcd_exit(void); * hdcd_mgr: A DCD manager handle. * uuid_obj: Pointer to a dsp_uuid for a library. * num_libs: Size of uuid array (number of library uuids). - * pDepLibUuids: Array of dependent library uuids to be filled in. + * dep_lib_uuids: Array of dependent library uuids to be filled in. * pPersistentDepLibs: Array indicating if corresponding lib is persistent. * phase: phase to obtain correct input library * Returns: @@ -166,13 +166,13 @@ extern void dcd_exit(void); * DCD initialized. * Valid hdcd_mgr. * uuid_obj != NULL - * pDepLibUuids != NULL. + * dep_lib_uuids != NULL. * Ensures: */ extern int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, u16 num_libs, - OUT struct dsp_uuid *pDepLibUuids, + OUT struct dsp_uuid *dep_lib_uuids, OUT bool *pPersistentDepLibs, IN enum nldr_phase phase); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index 72d4591..2e18edf 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -37,10 +37,10 @@ * ======== dev_brd_write_fxn ======== * Purpose: * Exported function to be used as the COD write function. This function - * is passed a handle to a DEV_hObject by ZL in pArb, then calls the + * is passed a handle to a DEV_hObject by ZL in arb, then calls the * device's bridge_brd_write() function. * Parameters: - * pArb: Handle to a Device Object. + * arb: Handle to a Device Object. * dev_ctxt: Handle to Bridge driver defined device info. * dsp_addr: Address on DSP board (Destination). * pHostBuf: Pointer to host buffer (Source). @@ -48,13 +48,13 @@ * ulMemType: Memory space on DSP to which to transfer. * Returns: * Number of bytes written. Returns 0 if the DEV_hObject passed in via - * pArb is invalid. + * arb is invalid. * Requires: * DEV Initialized. * pHostBuf != NULL * Ensures: */ -extern u32 dev_brd_write_fxn(void *pArb, +extern u32 dev_brd_write_fxn(void *arb, u32 ulDspAddr, void *pHostBuf, u32 ul_num_bytes, u32 mem_space); @@ -585,7 +585,7 @@ extern int dev_is_locked(IN struct dev_object *hdev_obj); extern int dev_insert_proc_object(IN struct dev_object *hdev_obj, IN u32 proc_obj, - OUT bool *pbAlreadyAttached); + OUT bool *already_attached); /* * ======== dev_remove_proc_object ======== @@ -595,7 +595,7 @@ extern int dev_insert_proc_object(IN struct dev_object * Parameters: * p_proc_object: Ptr to ProcObject to insert. * dev_obj: Ptr to Dev Object where the list is. - * pbAlreadyAttached: Ptr to return the bool + * already_attached: Ptr to return the bool * Returns: * 0: If successful. * -EPERM Failure to Remove the PROC Object from the list @@ -604,7 +604,7 @@ extern int dev_insert_proc_object(IN struct dev_object * proc_obj != 0 * dev_obj->proc_list != NULL * !LST_IS_EMPTY(dev_obj->proc_list) - * pbAlreadyAttached !=NULL + * already_attached !=NULL * Ensures: * Details: * List will be deleted when the DEV is destroyed. diff --git a/drivers/staging/tidspbridge/include/dspbridge/disp.h b/drivers/staging/tidspbridge/include/dspbridge/disp.h index 2c63db9..59fb431 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/disp.h +++ b/drivers/staging/tidspbridge/include/dspbridge/disp.h @@ -34,14 +34,14 @@ * Parameters: * phDispObject: Location to store node dispatcher object on output. * hdev_obj: Device for this processor. - * pDispAttrs: Node dispatcher attributes. + * disp_attrs: Node dispatcher attributes. * Returns: * 0: Success; * -ENOMEM: Insufficient memory for requested resources. * -EPERM: Unable to create dispatcher. * Requires: * disp_init(void) called. - * pDispAttrs != NULL. + * disp_attrs != NULL. * hdev_obj != NULL. * phDispObject != NULL. * Ensures: @@ -50,7 +50,7 @@ */ extern int disp_create(OUT struct disp_object **phDispObject, struct dev_object *hdev_obj, - IN CONST struct disp_attr *pDispAttrs); + IN CONST struct disp_attr *disp_attrs); /* * ======== disp_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index f9b9634..14bb4a5 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -382,7 +382,7 @@ extern int drv_remove_dev_object(struct drv_object *hdrv_obj, * Assigns the Resources or Releases them. * Parameters: * dw_context: Path to the driver Registry Key. - * pDevNodeString: Ptr to dev_node String stored in the Device Ext. + * dev_node_strg: Ptr to dev_node String stored in the Device Ext. * Returns: * TRUE if success; FALSE otherwise. * Requires: @@ -394,7 +394,7 @@ extern int drv_remove_dev_object(struct drv_object *hdrv_obj, * later used by the CFG module. */ extern int drv_request_resources(IN u32 dw_context, - OUT u32 *pDevNodeString); + OUT u32 *dev_node_strg); /* * ======== drv_release_resources ======== @@ -509,14 +509,14 @@ extern void mem_free_phys_mem(void *pVirtualAddress, * Purpose: * Unmap the linear address mapped in MEM_LINEAR_ADDRESS. * Parameters: - * pBaseAddr: Ptr to mapped memory (as returned by MEM_LINEAR_ADDRESS()). + * base_addr: Ptr to mapped memory (as returned by MEM_LINEAR_ADDRESS()). * Returns: * Requires: * - MEM initialized. - * - pBaseAddr is a valid linear address mapped in MEM_LINEAR_ADDRESS. + * - base_addr is a valid linear address mapped in MEM_LINEAR_ADDRESS. * Ensures: - * - pBaseAddr no longer points to a valid linear address. + * - base_addr no longer points to a valid linear address. */ -#define MEM_UNMAP_LINEAR_ADDRESS(pBaseAddr) {} +#define MEM_UNMAP_LINEAR_ADDRESS(base_addr) {} #endif /* DRV_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index fc8f8d3..19301b2 100755 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -560,7 +560,7 @@ typedef int(*fxn_chnl_flushio) (struct chnl_object *chnl_obj, * if (pInfo != NULL). */ typedef int(*fxn_chnl_getinfo) (struct chnl_object *chnl_obj, - OUT struct chnl_info *pChnlInfo); + OUT struct chnl_info *channel_info); /* * ======== bridge_chnl_get_mgr_info ======== @@ -649,7 +649,7 @@ typedef int(*fxn_chnl_registernotify) * Parameters: * phDevContext: Ptr to location to store a Bridge device context. * hdev_obj: Handle to a Device Object, created and managed by DSP API. - * pConfig: Ptr to configuration parameters provided by the + * config_param: Ptr to configuration parameters provided by the * Configuration Manager during device loading. * pDspConfig: DSP resources, as specified in the registry key for this * device. @@ -659,9 +659,9 @@ typedef int(*fxn_chnl_registernotify) * Requires: * phDevContext != NULL; * hdev_obj != NULL; - * pConfig != NULL; + * config_param != NULL; * pDspConfig != NULL; - * Fields in pConfig and pDspConfig contain valid values. + * Fields in config_param and pDspConfig contain valid values. * Ensures: * 0: All Bridge driver specific DSP resource and other * board context has been allocated. @@ -683,7 +683,7 @@ typedef int(*fxn_dev_create) (OUT struct bridge_dev_context struct dev_object * hdev_obj, IN struct cfg_hostres - * pConfig); + * config_param); /* * ======== bridge_dev_ctrl ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index 8b0cd7f..7e598ee --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -34,12 +34,12 @@ ((((s32)&(((type *)0)->field)) / wordsize) + (u32)base) /* Access can be different SM access word size (e.g. 16/32 bit words) */ -#define IO_SET_VALUE(pContext, type, base, field, value) (base->field = value) -#define IO_GET_VALUE(pContext, type, base, field) (base->field) -#define IO_OR_VALUE(pContext, type, base, field, value) (base->field |= value) -#define IO_AND_VALUE(pContext, type, base, field, value) (base->field &= value) -#define IO_SET_LONG(pContext, type, base, field, value) (base->field = value) -#define IO_GET_LONG(pContext, type, base, field) (base->field) +#define IO_SET_VALUE(context, type, base, field, value) (base->field = value) +#define IO_GET_VALUE(context, type, base, field) (base->field) +#define IO_OR_VALUE(context, type, base, field, value) (base->field |= value) +#define IO_AND_VALUE(context, type, base, field, value) (base->field &= value) +#define IO_SET_LONG(context, type, base, field, value) (base->field = value) +#define IO_GET_LONG(context, type, base, field) (base->field) #ifdef CONFIG_TIDSPBRIDGE_DVFS /* The maximum number of OPPs that are supported */ @@ -144,7 +144,7 @@ extern void iosm_schedule(struct io_mgr *hio_mgr); * uDDMAChnlId: DDMA channel identifier. * uNumDesc: Number of buffer descriptors(equals # of IOReqs & * Chirps) - * pDsp: Dsp address; + * dsp: Dsp address; * Returns: * Requires: * uDDMAChnlId < DDMA_MAXDDMACHNLS @@ -155,7 +155,7 @@ extern void iosm_schedule(struct io_mgr *hio_mgr); * Ensures: */ extern void io_ddma_init_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId, - u32 uNumDesc, void *pDsp); + u32 uNumDesc, void *dsp); /* * ======== io_ddma_clear_chnl_desc ======== diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index b302db5..ff1621c 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -1044,19 +1044,19 @@ void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, void *pVaBuf, * Free the given SM buffer and descriptor. * Does not free virtual memory. */ -int cmm_xlator_free_buf(struct cmm_xlatorobject *xlator, void *pBufVa) +int cmm_xlator_free_buf(struct cmm_xlatorobject *xlator, void *buf_va) { struct cmm_xlator *xlator_obj = (struct cmm_xlator *)xlator; int status = -EPERM; void *buf_pa = NULL; DBC_REQUIRE(refs > 0); - DBC_REQUIRE(pBufVa != NULL); + DBC_REQUIRE(buf_va != NULL); DBC_REQUIRE(xlator_obj->ul_seg_id > 0); if (xlator_obj) { /* convert Va to Pa so we can free it. */ - buf_pa = cmm_xlator_translate(xlator, pBufVa, CMM_VA2PA); + buf_pa = cmm_xlator_translate(xlator, buf_va, CMM_VA2PA); if (buf_pa) { status = cmm_free_buf(xlator_obj->hcmm_mgr, buf_pa, xlator_obj->ul_seg_id); diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index 7682035..8317d03 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -493,7 +493,7 @@ bool cod_init(void) * terminating args arrays, if num_argc is very large. */ int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], - cod_writefxn pfn_write, void *pArb, char *envp[]) + cod_writefxn pfn_write, void *arb, char *envp[]) { dbll_flags flags; struct dbll_attrs save_attrs; @@ -525,7 +525,7 @@ int cod_load_base(struct cod_manager *hmgr, u32 num_argc, char *args[], new_attrs = save_attrs; new_attrs.write = (dbll_write_fxn) pfn_write; - new_attrs.input_params = pArb; + new_attrs.input_params = arb; new_attrs.alloc = (dbll_alloc_fxn) no_op; new_attrs.free = (dbll_free_fxn) no_op; new_attrs.log_write = NULL; diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index 1f67193..29918cc 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -728,7 +728,7 @@ func_cont: * Get the content of a COFF section. */ int dbll_read_sect(struct dbll_library_obj *lib, char *name, - char *pContent, u32 size) + char *content, u32 size) { struct dbll_library_obj *zl_lib = (struct dbll_library_obj *)lib; bool opened_doff = false; @@ -740,7 +740,7 @@ int dbll_read_sect(struct dbll_library_obj *lib, char *name, DBC_REQUIRE(refs > 0); DBC_REQUIRE(zl_lib); DBC_REQUIRE(name != NULL); - DBC_REQUIRE(pContent != NULL); + DBC_REQUIRE(content != NULL); DBC_REQUIRE(size != 0); /* If DOFF file is not open, we open it. */ @@ -780,7 +780,7 @@ int dbll_read_sect(struct dbll_library_obj *lib, char *name, if (ul_sect_size > size) { status = -EPERM; } else { - if (!dload_get_section(zl_lib->desc, sect, pContent)) + if (!dload_get_section(zl_lib->desc, sect, content)) status = -EBADF; } @@ -790,8 +790,8 @@ func_cont: opened_doff = false; } - dev_dbg(bridge, "%s: lib: %p name: %s pContent: %p size: 0x%x, " - "status 0x%x\n", __func__, lib, name, pContent, size, status); + dev_dbg(bridge, "%s: lib: %p name: %s content: %p size: 0x%x, " + "status 0x%x\n", __func__, lib, name, content, size, status); return status; } diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index eb4799d..2e4726e 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -100,10 +100,10 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, * is passed a handle to a DEV_hObject, then calls the * device's bridge_brd_write() function. */ -u32 dev_brd_write_fxn(void *pArb, u32 ulDspAddr, void *pHostBuf, +u32 dev_brd_write_fxn(void *arb, u32 ulDspAddr, void *pHostBuf, u32 ul_num_bytes, u32 mem_space) { - struct dev_object *dev_obj = (struct dev_object *)pArb; + struct dev_object *dev_obj = (struct dev_object *)arb; u32 ul_written = 0; int status; @@ -961,20 +961,20 @@ static int init_cod_mgr(struct dev_object *dev_obj) * Parameters: * p_proc_object: Ptr to ProcObject to insert. * dev_obj: Ptr to Dev Object where the list is. - * pbAlreadyAttached: Ptr to return the bool + * already_attached: Ptr to return the bool * Returns: * 0: If successful. * Requires: * List Exists * hdev_obj is Valid handle * DEV Initialized - * pbAlreadyAttached != NULL + * already_attached != NULL * proc_obj != 0 * Ensures: * 0 and List is not Empty. */ int dev_insert_proc_object(struct dev_object *hdev_obj, - u32 proc_obj, OUT bool *pbAlreadyAttached) + u32 proc_obj, OUT bool *already_attached) { int status = 0; struct dev_object *dev_obj = (struct dev_object *)hdev_obj; @@ -983,9 +983,9 @@ int dev_insert_proc_object(struct dev_object *hdev_obj, DBC_REQUIRE(dev_obj); DBC_REQUIRE(proc_obj != 0); DBC_REQUIRE(dev_obj->proc_list != NULL); - DBC_REQUIRE(pbAlreadyAttached != NULL); + DBC_REQUIRE(already_attached != NULL); if (!LST_IS_EMPTY(dev_obj->proc_list)) - *pbAlreadyAttached = true; + *already_attached = true; /* Add DevObject to tail. */ lst_put_tail(dev_obj->proc_list, (struct list_head *)proc_obj); diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 9d05166..be98c4c 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -71,7 +71,7 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, IN OUT u16 *pNumLibs, OPTIONAL OUT u16 *pNumPersLibs, - OPTIONAL OUT struct dsp_uuid *pDepLibUuids, + OPTIONAL OUT struct dsp_uuid *dep_lib_uuids, OPTIONAL OUT bool *pPersistentDepLibs, IN enum nldr_phase phase); @@ -327,7 +327,7 @@ void dcd_exit(void) */ int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, - u16 num_libs, OUT struct dsp_uuid *pDepLibUuids, + u16 num_libs, OUT struct dsp_uuid *dep_lib_uuids, OUT bool *pPersistentDepLibs, IN enum nldr_phase phase) { @@ -336,11 +336,11 @@ int dcd_get_dep_libs(IN struct dcd_manager *hdcd_mgr, DBC_REQUIRE(refs > 0); DBC_REQUIRE(hdcd_mgr); DBC_REQUIRE(uuid_obj != NULL); - DBC_REQUIRE(pDepLibUuids != NULL); + DBC_REQUIRE(dep_lib_uuids != NULL); DBC_REQUIRE(pPersistentDepLibs != NULL); status = - get_dep_lib_info(hdcd_mgr, uuid_obj, &num_libs, NULL, pDepLibUuids, + get_dep_lib_info(hdcd_mgr, uuid_obj, &num_libs, NULL, dep_lib_uuids, pPersistentDepLibs, phase); return status; @@ -1393,7 +1393,7 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, IN struct dsp_uuid *uuid_obj, IN OUT u16 *pNumLibs, OPTIONAL OUT u16 *pNumPersLibs, - OPTIONAL OUT struct dsp_uuid *pDepLibUuids, + OPTIONAL OUT struct dsp_uuid *dep_lib_uuids, OPTIONAL OUT bool *pPersistentDepLibs, enum nldr_phase phase) { @@ -1407,7 +1407,7 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, u32 dw_data_size = COD_MAXPATHLENGTH; char seps[] = ", "; char *token = NULL; - bool get_uuids = (pDepLibUuids != NULL); + bool get_uuids = (dep_lib_uuids != NULL); u16 dep_libs = 0; int status = 0; @@ -1476,7 +1476,7 @@ static int get_dep_lib_info(IN struct dcd_manager *hdcd_mgr, } else { /* Retrieve UUID string. */ uuid_uuid_from_string(token, - &(pDepLibUuids + &(dep_lib_uuids [dep_libs])); /* Is this library persistent? */ token = strsep(&psz_cur, seps); diff --git a/drivers/staging/tidspbridge/rmgr/disp.c b/drivers/staging/tidspbridge/rmgr/disp.c index 1bcd403..5f51d50 100644 --- a/drivers/staging/tidspbridge/rmgr/disp.c +++ b/drivers/staging/tidspbridge/rmgr/disp.c @@ -89,7 +89,7 @@ static int send_message(struct disp_object *disp_obj, u32 timeout, */ int disp_create(OUT struct disp_object **phDispObject, struct dev_object *hdev_obj, - IN CONST struct disp_attr *pDispAttrs) + IN CONST struct disp_attr *disp_attrs) { struct disp_object *disp_obj; struct bridge_drv_interface *intf_fxns; @@ -100,7 +100,7 @@ int disp_create(OUT struct disp_object **phDispObject, DBC_REQUIRE(refs > 0); DBC_REQUIRE(phDispObject != NULL); - DBC_REQUIRE(pDispAttrs != NULL); + DBC_REQUIRE(disp_attrs != NULL); DBC_REQUIRE(hdev_obj != NULL); *phDispObject = NULL; @@ -142,14 +142,14 @@ int disp_create(OUT struct disp_object **phDispObject, /* Open channels for communicating with the RMS */ chnl_attr_obj.uio_reqs = CHNLIOREQS; chnl_attr_obj.event_obj = NULL; - ul_chnl_id = pDispAttrs->ul_chnl_offset + CHNLTORMSOFFSET; + ul_chnl_id = disp_attrs->ul_chnl_offset + CHNLTORMSOFFSET; status = (*intf_fxns->pfn_chnl_open) (&(disp_obj->chnl_to_dsp), disp_obj->hchnl_mgr, CHNL_MODETODSP, ul_chnl_id, &chnl_attr_obj); if (DSP_SUCCEEDED(status)) { - ul_chnl_id = pDispAttrs->ul_chnl_offset + CHNLFROMRMSOFFSET; + ul_chnl_id = disp_attrs->ul_chnl_offset + CHNLFROMRMSOFFSET; status = (*intf_fxns->pfn_chnl_open) (&(disp_obj->chnl_from_dsp), disp_obj->hchnl_mgr, @@ -158,7 +158,7 @@ int disp_create(OUT struct disp_object **phDispObject, } if (DSP_SUCCEEDED(status)) { /* Allocate buffer for commands, replies */ - disp_obj->ul_bufsize = pDispAttrs->ul_chnl_buf_size; + disp_obj->ul_bufsize = disp_attrs->ul_chnl_buf_size; disp_obj->ul_bufsize_rms = RMS_COMMANDBUFSIZE; disp_obj->pbuf = kzalloc(disp_obj->ul_bufsize, GFP_KERNEL); if (disp_obj->pbuf == NULL) diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 4abfd81..78211a6 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -730,14 +730,14 @@ int drv_remove_dev_object(struct drv_object *driver_obj, * Purpose: * Requests resources from the OS. */ -int drv_request_resources(u32 dw_context, u32 *pDevNodeString) +int drv_request_resources(u32 dw_context, u32 *dev_node_strg) { int status = 0; struct drv_object *pdrv_object; struct drv_ext *pszdev_node; DBC_REQUIRE(dw_context != 0); - DBC_REQUIRE(pDevNodeString != NULL); + DBC_REQUIRE(dev_node_strg != NULL); /* * Allocate memory to hold the string. This will live untill @@ -754,22 +754,22 @@ int drv_request_resources(u32 dw_context, u32 *pDevNodeString) (char *)dw_context, MAXREGPATHLENGTH - 1); pszdev_node->sz_string[MAXREGPATHLENGTH - 1] = '\0'; /* Update the Driver Object List */ - *pDevNodeString = (u32) pszdev_node->sz_string; + *dev_node_strg = (u32) pszdev_node->sz_string; lst_put_tail(pdrv_object->dev_node_string, (struct list_head *)pszdev_node); } else { status = -ENOMEM; - *pDevNodeString = 0; + *dev_node_strg = 0; } } else { dev_dbg(bridge, "%s: Failed to get Driver Object from Registry", __func__); - *pDevNodeString = 0; + *dev_node_strg = 0; } - DBC_ENSURE((DSP_SUCCEEDED(status) && pDevNodeString != NULL && + DBC_ENSURE((DSP_SUCCEEDED(status) && dev_node_strg != NULL && !LST_IS_EMPTY(pdrv_object->dev_node_string)) || - (DSP_FAILED(status) && *pDevNodeString == 0)); + (DSP_FAILED(status) && *dev_node_strg == 0)); return status; } diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index d19d990..7cffca4 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -253,7 +253,7 @@ static int get_fxn_address(struct node_object *hnode, u32 * pulFxnAddr, static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, CONST struct dsp_uuid *pNodeId, - struct dcd_genericobj *pdcdProps); + struct dcd_genericobj *dcd_prop); static int get_proc_props(struct node_mgr *hnode_mgr, struct dev_object *hdev_obj); static int get_rms_fxns(struct node_mgr *hnode_mgr); @@ -2891,19 +2891,19 @@ void get_node_info(struct node_object *hnode, struct dsp_nodeinfo *pNodeInfo) static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, CONST struct dsp_uuid *pNodeId, - struct dcd_genericobj *pdcdProps) + struct dcd_genericobj *dcd_prop) { u32 len; struct node_msgargs *pmsg_args; struct node_taskargs *task_arg_obj; enum node_type node_type = NODE_TASK; struct dsp_ndbprops *pndb_props = - &(pdcdProps->obj_data.node_obj.ndb_props); + &(dcd_prop->obj_data.node_obj.ndb_props); int status = 0; char sz_uuid[MAXUUIDLEN]; status = dcd_get_object_def(hdcd_mgr, (struct dsp_uuid *)pNodeId, - DSP_DCDNODETYPE, pdcdProps); + DSP_DCDNODETYPE, dcd_prop); if (DSP_SUCCEEDED(status)) { hnode->ntype = node_type = pndb_props->ntype; @@ -2917,9 +2917,9 @@ static int get_node_props(struct dcd_manager *hdcd_mgr, if (node_type != NODE_DEVICE) { pmsg_args = &(hnode->create_args.asa.node_msg_args); pmsg_args->seg_id = - pdcdProps->obj_data.node_obj.msg_segid; + dcd_prop->obj_data.node_obj.msg_segid; pmsg_args->notify_type = - pdcdProps->obj_data.node_obj.msg_notify_type; + dcd_prop->obj_data.node_obj.msg_notify_type; pmsg_args->max_msgs = pndb_props->message_depth; dev_dbg(bridge, "(node) Max Number of Messages: 0x%x\n", pmsg_args->max_msgs); diff --git a/drivers/staging/tidspbridge/services/cfg.c b/drivers/staging/tidspbridge/services/cfg.c index 243fea9..cc138f7 100644 --- a/drivers/staging/tidspbridge/services/cfg.c +++ b/drivers/staging/tidspbridge/services/cfg.c @@ -50,22 +50,22 @@ void cfg_exit(void) * Retreive the autostart mask, if any, for this board. */ int cfg_get_auto_start(struct cfg_devnode *dev_node_obj, - OUT u32 *pdwAutoStart) + OUT u32 *auto_start) { int status = 0; u32 dw_buf_size; struct drv_data *drv_datap = dev_get_drvdata(bridge); - dw_buf_size = sizeof(*pdwAutoStart); + dw_buf_size = sizeof(*auto_start); if (!dev_node_obj) status = -EFAULT; - if (!pdwAutoStart || !drv_datap) + if (!auto_start || !drv_datap) status = -EFAULT; if (DSP_SUCCEEDED(status)) - *pdwAutoStart = (drv_datap->base_img) ? 1 : 0; + *auto_start = (drv_datap->base_img) ? 1 : 0; DBC_ENSURE((status == 0 && - (*pdwAutoStart == 0 || *pdwAutoStart == 1)) + (*auto_start == 0 || *auto_start == 1)) || status != 0); return status; } From patchwork Wed Jun 30 05:55:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zach Pfeffer X-Patchwork-Id: 108739 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5U5ub9E002537 for ; Wed, 30 Jun 2010 05:56:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750907Ab0F3F4C (ORCPT ); Wed, 30 Jun 2010 01:56:02 -0400 Received: from wolverine01.qualcomm.com ([199.106.114.254]:4937 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752057Ab0F3F4A (ORCPT ); Wed, 30 Jun 2010 01:56:00 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6028"; a="46016245" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine01.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 29 Jun 2010 22:55:57 -0700 Received: from localhost.localdomain (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 5011710004BF; Tue, 29 Jun 2010 22:55:59 -0700 (PDT) From: Zach Pfeffer To: mel@csn.ul.ie Cc: andi@firstfloor.org, dwalker@codeaurora.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zach Pfeffer Subject: [RFC 3/3] mm: iommu: The Virtual Contiguous Memory Manager Date: Tue, 29 Jun 2010 22:55:50 -0700 Message-Id: <1277877350-2147-3-git-send-email-zpfeffer@codeaurora.org> X-Mailer: git-send-email 1.7.0.2 In-Reply-To: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org> References: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 30 Jun 2010 05:56:38 +0000 (UTC) different pools. This allows fine grained control of block and physical placement, a feature many advanced IOMMU devices need. Once a user has made a reservation on a VCM and allocated physical memory, the two graph end-points are joined in a backing step. This step allows multiple reservations to map the same physical location. Many of the functions in the API take various attributes that provide fine grained control of the objects they create. For instance, reservations can map cachable memory and physical allocations can be constrained to use a particular subset of block sizes. Signed-off-by: Zach Pfeffer --- arch/arm/mm/vcm.c | 1901 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/vcm.h | 701 +++++++++++++++++ include/linux/vcm_types.h | 318 ++++++++ 3 files changed, 2920 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mm/vcm.c create mode 100644 include/linux/vcm.h create mode 100644 include/linux/vcm_types.h diff --git a/arch/arm/mm/vcm.c b/arch/arm/mm/vcm.c new file mode 100644 index 0000000..04ff2d4 --- /dev/null +++ b/arch/arm/mm/vcm.c @@ -0,0 +1,1901 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_SMMU +#include +#endif + +/* alloc_vm_area */ +#include +#include +#include + +/* may be temporary */ +#include + +#include +#include + +#define BOOTMEM_SZ SZ_32M +#define BOOTMEM_ALIGN SZ_1M + +#define CONT_SZ SZ_8M +#define CONT_ALIGN SZ_1M + +#define ONE_TO_ONE_CHK 1 + +#define vcm_err(a, ...) \ + pr_err("ERROR %s %i " a, __func__, __LINE__, ##__VA_ARGS__) + +static void *bootmem; +static void *bootmem_cont; +static struct vcm *cont_vcm_id; +static struct phys_chunk *cont_phys_chunk; + +DEFINE_SPINLOCK(vcmlock); + +static int vcm_no_res(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + return list_empty(&vcm->res_head); +fail: + return -EINVAL; +} + +static int vcm_no_assoc(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + return list_empty(&vcm->assoc_head); +fail: + return -EINVAL; +} + +static int vcm_all_activated(struct vcm *vcm) +{ + struct avcm *avcm; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm) + if (!avcm->is_active) + return 0; + + return 1; +fail: + return -1; +} + +static void vcm_destroy_common(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return; + } + + memset(vcm, 0, sizeof(*vcm)); + kfree(vcm); +} + +static struct vcm *vcm_create_common(void) +{ + struct vcm *vcm = 0; + + vcm = kzalloc(sizeof(*vcm), GFP_KERNEL); + if (!vcm) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret 0\n", + sizeof(*vcm)); + goto fail; + } + + INIT_LIST_HEAD(&vcm->res_head); + INIT_LIST_HEAD(&vcm->assoc_head); + + return vcm; + +fail: + return NULL; +} + + +static int vcm_create_pool(struct vcm *vcm, size_t start_addr, size_t len) +{ + int ret = 0; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + vcm->start_addr = start_addr; + vcm->len = len; + + vcm->pool = gen_pool_create(PAGE_SHIFT, -1); + if (!vcm->pool) { + vcm_err("gen_pool_create(%x, -1) ret 0\n", PAGE_SHIFT); + goto fail; + } + + ret = gen_pool_add(vcm->pool, start_addr, len, -1); + if (ret) { + vcm_err("gen_pool_add(%p, %p, %i, -1) ret %i\n", vcm->pool, + (void *) start_addr, len, ret); + goto fail2; + } + + return 0; + +fail2: + gen_pool_destroy(vcm->pool); +fail: + return -1; +} + + +static struct vcm *vcm_create_flagged(int flag, size_t start_addr, size_t len) +{ + int ret = 0; + struct vcm *vcm = 0; + + vcm = vcm_create_common(); + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + /* special one-to-one mapping case */ + if ((flag & ONE_TO_ONE_CHK) && + bootmem_cont && + __pa(bootmem_cont) && + start_addr == __pa(bootmem_cont) && + len == CONT_SZ) { + vcm->type = VCM_ONE_TO_ONE; + } else { + ret = vcm_create_pool(vcm, start_addr, len); + vcm->type = VCM_DEVICE; + } + + if (ret) { + vcm_err("vcm_create_pool(%p, %p, %i) ret %i\n", vcm, + (void *) start_addr, len, ret); + goto fail2; + } + + return vcm; + +fail2: + vcm_destroy_common(vcm); +fail: + return NULL; +} + +struct vcm *vcm_create(size_t start_addr, size_t len) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + vcm = vcm_create_flagged(ONE_TO_ONE_CHK, start_addr, len); + spin_unlock_irqrestore(&vcmlock, flags); + return vcm; +} + + +static int ext_vcm_id_valid(size_t ext_vcm_id) +{ + return ((ext_vcm_id == VCM_PREBUILT_KERNEL) || + (ext_vcm_id == VCM_PREBUILT_USER)); +} + + +struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id) +{ + unsigned long flags; + struct vcm *vcm = 0; + + spin_lock_irqsave(&vcmlock, flags); + + if (!ext_vcm_id_valid(ext_vcm_id)) { + vcm_err("ext_vcm_id_valid(%i) ret 0\n", ext_vcm_id); + goto fail; + } + + vcm = vcm_create_common(); + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (ext_vcm_id == VCM_PREBUILT_KERNEL) + vcm->type = VCM_EXT_KERNEL; + else if (ext_vcm_id == VCM_PREBUILT_USER) + vcm->type = VCM_EXT_USER; + else { + vcm_err("UNREACHABLE ext_vcm_id is illegal\n"); + goto fail_free; + } + + /* TODO: set kernel and userspace start_addr and len, if this + * makes sense */ + + spin_unlock_irqrestore(&vcmlock, flags); + return vcm; + +fail_free: + vcm_destroy_common(vcm); +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return NULL; +} + + +struct vcm *vcm_clone(struct vcm *vcm_id) +{ + return 0; +} + + +/* No lock needed, vcm->start_addr is never updated after creation */ +size_t vcm_get_start_addr(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return 1; + } + + return vcm->start_addr; +} + + +/* No lock needed, vcm->len is never updated after creation */ +size_t vcm_get_len(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + return 0; + } + + return vcm->len; +} + + +static int vcm_free_common_rule(struct vcm *vcm) +{ + int ret; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + ret = vcm_no_res(vcm); + if (!ret) { + vcm_err("vcm_no_res(%p) ret 0\n", vcm); + goto fail_busy; + } + + if (ret == -EINVAL) { + vcm_err("vcm_no_res(%p) ret -EINVAL\n", vcm); + goto fail; + } + + ret = vcm_no_assoc(vcm); + if (!ret) { + vcm_err("vcm_no_assoc(%p) ret 0\n", vcm); + goto fail_busy; + } + + if (ret == -EINVAL) { + vcm_err("vcm_no_assoc(%p) ret -EINVAL\n", vcm); + goto fail; + } + + return 0; + +fail_busy: + return -EBUSY; +fail: + return -EINVAL; +} + + +static int vcm_free_pool_rule(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + /* A vcm always has a valid pool, don't free the vcm because + what we got is probably invalid. + */ + if (!vcm->pool) { + vcm_err("NULL vcm->pool\n"); + goto fail; + } + + return 0; + +fail: + return -EINVAL; +} + + +static void vcm_free_common(struct vcm *vcm) +{ + memset(vcm, 0, sizeof(*vcm)); + + kfree(vcm); +} + + +static int vcm_free_pool(struct vcm *vcm) +{ + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + gen_pool_destroy(vcm->pool); + + return 0; + +fail: + return -1; +} + + +static int __vcm_free(struct vcm *vcm) +{ + int ret; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + ret = vcm_free_common_rule(vcm); + if (ret != 0) { + vcm_err("vcm_free_common_rule(%p) ret %i\n", vcm, ret); + goto fail; + } + + if (vcm->type == VCM_DEVICE) { + ret = vcm_free_pool_rule(vcm); + if (ret != 0) { + vcm_err("vcm_free_pool_rule(%p) ret %i\n", + (void *) vcm, ret); + goto fail; + } + + ret = vcm_free_pool(vcm); + if (ret != 0) { + vcm_err("vcm_free_pool(%p) ret %i", (void *) vcm, ret); + goto fail; + } + } + + vcm_free_common(vcm); + + return 0; + +fail: + return -EINVAL; +} + +int vcm_free(struct vcm *vcm) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + ret = __vcm_free(vcm); + spin_unlock_irqrestore(&vcmlock, flags); + + return ret; +} + + +static struct res *__vcm_reserve(struct vcm *vcm, size_t len, uint32_t attr) +{ + struct res *res = NULL; + + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (len == 0) { + vcm_err("len is 0\n"); + goto fail; + } + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret 0", sizeof(*res)); + goto fail; + } + + INIT_LIST_HEAD(&res->res_elm); + res->vcm_id = vcm; + res->len = len; + res->attr = attr; + + if (len/SZ_1M) + res->alignment_req = SZ_1M; + else if (len/SZ_64K) + res->alignment_req = SZ_64K; + else + res->alignment_req = SZ_4K; + + res->aligned_len = res->alignment_req + len; + + switch (vcm->type) { + case VCM_DEVICE: + /* should always be not zero */ + if (!vcm->pool) { + vcm_err("NULL vcm->pool\n"); + goto fail2; + } + + res->ptr = gen_pool_alloc(vcm->pool, res->aligned_len); + if (!res->ptr) { + vcm_err("gen_pool_alloc(%p, %i) ret 0\n", + vcm->pool, res->aligned_len); + goto fail2; + } + + /* Calculate alignment... this will all change anyway */ + res->aligned_ptr = res->ptr + + (res->alignment_req - + (res->ptr & (res->alignment_req - 1))); + + break; + case VCM_EXT_KERNEL: + res->vm_area = alloc_vm_area(res->aligned_len); + res->mapped = 0; /* be explicit */ + if (!res->vm_area) { + vcm_err("NULL res->vm_area\n"); + goto fail2; + } + + res->aligned_ptr = (size_t) res->vm_area->addr + + (res->alignment_req - + ((size_t) res->vm_area->addr & + (res->alignment_req - 1))); + + break; + case VCM_ONE_TO_ONE: + break; + default: + vcm_err("%i is an invalid vcm->type\n", vcm->type); + goto fail2; + } + + list_add_tail(&res->res_elm, &vcm->res_head); + + return res; + +fail2: + kfree(res); +fail: + return 0; +} + + +struct res *vcm_reserve(struct vcm *vcm, size_t len, uint32_t attr) +{ + unsigned long flags; + struct res *res; + + spin_lock_irqsave(&vcmlock, flags); + res = __vcm_reserve(vcm, len, attr); + spin_unlock_irqrestore(&vcmlock, flags); + + return res; +} + + +struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm* vcm, + size_t len, uint32_t attr) +{ + return 0; +} + + +/* No lock needed, res->vcm_id is never updated after creation */ +struct vcm *vcm_get_vcm_from_res(struct res *res) +{ + if (!res) { + vcm_err("NULL res\n"); + return 0; + } + + return res->vcm_id; +} + + +static int __vcm_unreserve(struct res *res) +{ + struct vcm *vcm; + + if (!res) { + vcm_err("NULL res\n"); + goto fail; + } + + if (!res->vcm_id) { + vcm_err("NULL res->vcm_id\n"); + goto fail; + } + + vcm = res->vcm_id; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + switch (vcm->type) { + case VCM_DEVICE: + if (!res->vcm_id->pool) { + vcm_err("NULL (res->vcm_id))->pool\n"); + goto fail; + } + + /* res->ptr could be zero, this isn't an error */ + gen_pool_free(res->vcm_id->pool, res->ptr, + res->aligned_len); + break; + case VCM_EXT_KERNEL: + if (res->mapped) { + vcm_err("res->mapped is true\n"); + goto fail; + } + + /* This may take a little explaining. + * In the kernel vunmap will free res->vm_area + * so if we've called it then we shouldn't call + * free_vm_area(). If we've called it we set + * res->vm_area to 0. + */ + if (res->vm_area) { + free_vm_area(res->vm_area); + res->vm_area = 0; + } + + break; + case VCM_ONE_TO_ONE: + break; + default: + vcm_err("%i is an invalid vcm->type\n", vcm->type); + goto fail; + } + + list_del(&res->res_elm); + + /* be extra careful by clearing the memory before freeing it */ + memset(res, 0, sizeof(*res)); + + kfree(res); + + return 0; + +fail: + return -EINVAL; +} + + +int vcm_unreserve(struct res *res) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + ret = __vcm_unreserve(res); + spin_unlock_irqrestore(&vcmlock, flags); + + return ret; +} + + +/* No lock needed, res->len is never updated after creation */ +size_t vcm_get_res_len(struct res *res) +{ + if (!res) { + vcm_err("res is 0\n"); + return 0; + } + + return res->len; +} + + +int vcm_set_res_attr(struct res *res, uint32_t attr) +{ + return 0; +} + + +uint32_t vcm_get_res_attr(struct res *res) +{ + return 0; +} + + +size_t vcm_get_num_res(struct vcm *vcm) +{ + return 0; +} + + +struct res *vcm_get_next_res(struct vcm *vcm, struct res *res) +{ + return 0; +} + + +size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, + size_t from_off, size_t len) +{ + return 0; +} + + +size_t vcm_get_min_page_size(void) +{ + return PAGE_SIZE; +} + + +static int vcm_to_smmu_attr(uint32_t attr) +{ + int smmu_attr = 0; + + switch (attr & VCM_CACHE_POLICY) { + case VCM_NOTCACHED: + smmu_attr = VCM_DEV_ATTR_NONCACHED; + break; + case VCM_WB_WA: + smmu_attr = VCM_DEV_ATTR_CACHED_WB_WA; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + case VCM_WB_NWA: + smmu_attr = VCM_DEV_ATTR_CACHED_WB_NWA; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + case VCM_WT: + smmu_attr = VCM_DEV_ATTR_CACHED_WT; + smmu_attr |= VCM_DEV_ATTR_SH; + break; + default: + return -1; + } + + return smmu_attr; +} + + +/* TBD if you vcm_back again what happens? */ +int vcm_back(struct res *res, struct physmem *physmem) +{ + unsigned long flags; + struct vcm *vcm; + struct phys_chunk *chunk; + size_t va = 0; + int ret; + int attr; + + spin_lock_irqsave(&vcmlock, flags); + + if (!res) { + vcm_err("NULL res\n"); + goto fail; + } + + vcm = res->vcm_id; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + switch (vcm->type) { + case VCM_DEVICE: + case VCM_EXT_KERNEL: /* hack part 1 */ + attr = vcm_to_smmu_attr(res->attr); + if (attr == -1) { + vcm_err("Bad SMMU attr\n"); + goto fail; + } + break; + default: + attr = 0; + break; + } + + if (!physmem) { + vcm_err("NULL physmem\n"); + goto fail; + } + + if (res->len == 0) { + vcm_err("res->len is 0\n"); + goto fail; + } + + if (physmem->len == 0) { + vcm_err("physmem->len is 0\n"); + goto fail; + } + + if (res->len != physmem->len) { + vcm_err("res->len (%i) != physmem->len (%i)\n", + res->len, physmem->len); + goto fail; + } + + if (physmem->is_cont) { + if (physmem->res == 0) { + vcm_err("cont physmem->res is 0"); + goto fail; + } + } else { + /* fail if no physmem */ + if (list_empty(&physmem->alloc_head.allocated)) { + vcm_err("no allocated phys memory"); + goto fail; + } + } + + ret = vcm_no_assoc(res->vcm_id); + if (ret == 1) { + vcm_err("can't back un associated VCM\n"); + goto fail; + } + + if (ret == -1) { + vcm_err("vcm_no_assoc() ret -1\n"); + goto fail; + } + + ret = vcm_all_activated(res->vcm_id); + if (ret == 0) { + vcm_err("can't back, not all associations are activated\n"); + goto fail_eagain; + } + + if (ret == -1) { + vcm_err("vcm_all_activated() ret -1\n"); + goto fail; + } + + va = res->aligned_ptr; + + list_for_each_entry(chunk, &physmem->alloc_head.allocated, + allocated) { + struct vcm *vcm = res->vcm_id; + size_t chunk_size = vcm_alloc_idx_to_size(chunk->size_idx); + + switch (vcm->type) { + case VCM_DEVICE: + { +#ifdef CONFIG_SMMU + struct avcm *avcm; + /* map all */ + list_for_each_entry(avcm, &vcm->assoc_head, + assoc_elm) { + + ret = smmu_map( + (struct smmu_dev *) avcm->dev_id, + chunk->pa, va, chunk_size, attr); + if (ret != 0) { + vcm_err("smmu_map(%p, %p, %p, 0x%x," + "0x%x)" + " ret %i", + (void *) avcm->dev_id, + (void *) chunk->pa, + (void *) va, + (int) chunk_size, attr, ret); + goto fail; + /* TODO handle weird inter-map case */ + } + } + break; +#else + vcm_err("No SMMU support - VCM_DEVICE not supported\n"); + goto fail; +#endif + } + + case VCM_EXT_KERNEL: + { + unsigned int pages_in_chunk = chunk_size / PAGE_SIZE; + unsigned long loc_va = va; + unsigned long loc_pa = chunk->pa; + + const struct mem_type *mtype; + + /* TODO: get this based on MEMTYPE */ + mtype = get_mem_type(MT_DEVICE); + if (!mtype) { + vcm_err("mtype is 0\n"); + goto fail; + } + + /* TODO: Map with the same chunk size */ + while (pages_in_chunk--) { + ret = ioremap_page(loc_va, + loc_pa, + mtype); + if (ret != 0) { + vcm_err("ioremap_page(%p, %p, %p) ret" + " %i", (void *) loc_va, + (void *) loc_pa, + (void *) mtype, ret); + goto fail; + /* TODO handle weird + inter-map case */ + } + + /* hack part 2 */ + /* we're changing the PT entry behind + * linux's back + */ + ret = cpu_set_attr(loc_va, PAGE_SIZE, attr); + if (ret != 0) { + vcm_err("cpu_set_attr(%p, %lu, %x)" + "ret %i\n", + (void *) loc_va, PAGE_SIZE, + attr, ret); + goto fail; + /* TODO handle weird + inter-map case */ + } + + res->mapped = 1; + + loc_va += PAGE_SIZE; + loc_pa += PAGE_SIZE; + } + + flush_cache_vmap(va, loc_va); + break; + } + case VCM_ONE_TO_ONE: + va = chunk->pa; + break; + default: + /* this should never happen */ + goto fail; + } + + va += chunk_size; + /* also add res to the allocated chunk list of refs */ + } + + /* note the reservation */ + res->physmem_id = physmem; + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_eagain: + spin_unlock_irqrestore(&vcmlock, flags); + return -EAGAIN; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_unback(struct res *res) +{ + unsigned long flags; + struct vcm *vcm; + struct physmem *physmem; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + + if (!res) + goto fail; + + vcm = res->vcm_id; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!res->physmem_id) { + vcm_err("can't unback a non-backed reservation\n"); + goto fail; + } + + physmem = res->physmem_id; + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + if (list_empty(&physmem->alloc_head.allocated)) { + vcm_err("physmem allocation is empty\n"); + goto fail; + } + + ret = vcm_no_assoc(res->vcm_id); + if (ret == 1) { + vcm_err("can't unback a unassociated reservation\n"); + goto fail; + } + + if (ret == -1) { + vcm_err("vcm_no_assoc(%p) ret -1\n", (void *) res->vcm_id); + goto fail; + } + + ret = vcm_all_activated(res->vcm_id); + if (ret == 0) { + vcm_err("can't unback, not all associations are active\n"); + goto fail_eagain; + } + + if (ret == -1) { + vcm_err("vcm_all_activated(%p) ret -1\n", (void *) res->vcm_id); + goto fail; + } + + + switch (vcm->type) { + case VCM_EXT_KERNEL: + if (!res->mapped) { + vcm_err("can't unback an unmapped VCM_EXT_KERNEL" + " VCM\n"); + goto fail; + } + + /* vunmap free's vm_area */ + vunmap(res->vm_area->addr); + res->vm_area = 0; + + res->mapped = 0; + break; + + case VCM_DEVICE: + { +#ifdef CONFIG_SMMU + struct phys_chunk *chunk; + size_t va = res->aligned_ptr; + + list_for_each_entry(chunk, &physmem->alloc_head.allocated, + allocated) { + struct vcm *vcm = res->vcm_id; + size_t chunk_size = + vcm_alloc_idx_to_size(chunk->size_idx); + struct avcm *avcm; + + /* un map all */ + list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm) { + ret = smmu_unmap( + (struct smmu_dev *) avcm->dev_id, + va, chunk_size); + if (ret != 0) { + vcm_err("smmu_unmap(%p, %p, 0x%x)" + " ret %i", + (void *) avcm->dev_id, + (void *) va, + (int) chunk_size, ret); + goto fail; + /* TODO handle weird inter-unmap state*/ + } + } + va += chunk_size; + /* may to a light unback, depending on the requested + * functionality + */ + } +#else + vcm_err("No SMMU support - VCM_DEVICE memory not supported\n"); + goto fail; +#endif + break; + } + + case VCM_ONE_TO_ONE: + break; + default: + /* this should never happen */ + goto fail; + } + + /* clear the reservation */ + res->physmem_id = 0; + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_eagain: + spin_unlock_irqrestore(&vcmlock, flags); + return -EAGAIN; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +enum memtarget_t vcm_get_memtype_of_res(struct res *res) +{ + return VCM_INVALID; +} + +static int vcm_free_max_munch_cont(struct phys_chunk *head) +{ + struct phys_chunk *chunk, *tmp; + + if (!head) + return -1; + + list_for_each_entry_safe(chunk, tmp, &head->allocated, + allocated) { + list_del_init(&chunk->allocated); + } + + return 0; +} + +static int vcm_alloc_max_munch_cont(size_t start_addr, size_t len, + struct phys_chunk *head) +{ + /* this function should always succeed, since it + parallels a VCM */ + + int i, j; + + if (!head) { + vcm_err("head is NULL in continuous map.\n"); + goto fail; + } + + if (start_addr < __pa(bootmem_cont)) { + vcm_err("phys start addr (%p) < base (%p)\n", + (void *) start_addr, (void *) __pa(bootmem_cont)); + goto fail; + } + + if ((start_addr + len) >= (__pa(bootmem_cont) + CONT_SZ)) { + vcm_err("requested region (%p + %i) > " + " available region (%p + %i)", + (void *) start_addr, (int) len, + (void *) __pa(bootmem_cont), CONT_SZ); + goto fail; + } + + i = (start_addr - __pa(bootmem_cont))/SZ_4K; + + for (j = 0; j < ARRAY_SIZE(chunk_sizes); ++j) { + while (len/chunk_sizes[j]) { + if (!list_empty(&cont_phys_chunk[i].allocated)) { + vcm_err("chunk %i ( addr %p) already mapped\n", + i, (void *) (start_addr + + (i*chunk_sizes[j]))); + goto fail_free; + } + list_add_tail(&cont_phys_chunk[i].allocated, + &head->allocated); + cont_phys_chunk[i].size_idx = j; + + len -= chunk_sizes[j]; + i += chunk_sizes[j]/SZ_4K; + } + } + + if (len % SZ_4K) { + if (!list_empty(&cont_phys_chunk[i].allocated)) { + vcm_err("chunk %i (addr %p) already mapped\n", + i, (void *) (start_addr + (i*SZ_4K))); + goto fail_free; + } + len -= SZ_4K; + list_add_tail(&cont_phys_chunk[i].allocated, + &head->allocated); + + i++; + } + + return i; + +fail_free: + { + struct phys_chunk *chunk, *tmp; + /* just remove from list, if we're double alloc'ing + we don't want to stamp on the other guy */ + list_for_each_entry_safe(chunk, tmp, &head->allocated, + allocated) { + list_del(&chunk->allocated); + } + } +fail: + return 0; +} + +struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len, + uint32_t attr) +{ + unsigned long flags; + int ret; + struct physmem *physmem = NULL; + int blocks_allocated; + + spin_lock_irqsave(&vcmlock, flags); + + physmem = kzalloc(sizeof(*physmem), GFP_KERNEL); + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + physmem->memtype = memtype; + physmem->len = len; + physmem->attr = attr; + + INIT_LIST_HEAD(&physmem->alloc_head.allocated); + + if (attr & VCM_PHYS_CONT) { + if (!cont_vcm_id) { + vcm_err("cont_vcm_id is NULL\n"); + goto fail2; + } + + physmem->is_cont = 1; + + /* TODO: get attributes */ + physmem->res = __vcm_reserve(cont_vcm_id, len, 0); + if (physmem->res == 0) { + vcm_err("contiguous space allocation failed\n"); + goto fail2; + } + + /* if we're here we know we have memory, create + the shadow physmem links*/ + blocks_allocated = + vcm_alloc_max_munch_cont( + vcm_get_dev_addr(physmem->res), + len, + &physmem->alloc_head); + + if (blocks_allocated == 0) { + vcm_err("shadow physmem allocation failed\n"); + goto fail3; + } + } else { + blocks_allocated = vcm_alloc_max_munch(len, + &physmem->alloc_head); + if (blocks_allocated == 0) { + vcm_err("physical allocation failed:" + " vcm_alloc_max_munch(%i, %p) ret 0\n", + len, &physmem->alloc_head); + goto fail2; + } + } + + spin_unlock_irqrestore(&vcmlock, flags); + return physmem; + +fail3: + ret = __vcm_unreserve(physmem->res); + if (ret != 0) { + vcm_err("vcm_unreserve(%p) ret %i during cleanup", + (void *) physmem->res, ret); + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + } +fail2: + kfree(physmem); +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +} + + +int vcm_phys_free(struct physmem *physmem) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&vcmlock, flags); + + if (!physmem) { + vcm_err("physmem is NULL\n"); + goto fail; + } + + if (physmem->is_cont) { + if (physmem->res == 0) { + vcm_err("contiguous reservation is NULL\n"); + goto fail; + } + + ret = vcm_free_max_munch_cont(&physmem->alloc_head); + if (ret != 0) { + vcm_err("failed to free physical blocks:" + " vcm_free_max_munch_cont(%p) ret %i\n", + (void *) &physmem->alloc_head, ret); + goto fail; + } + + ret = __vcm_unreserve(physmem->res); + if (ret != 0) { + vcm_err("failed to free virtual blocks:" + " vcm_unreserve(%p) ret %i\n", + (void *) physmem->res, ret); + goto fail; + } + + } else { + + ret = vcm_alloc_free_blocks(&physmem->alloc_head); + if (ret != 0) { + vcm_err("failed to free physical blocks:" + " vcm_alloc_free_blocks(%p) ret %i\n", + (void *) &physmem->alloc_head, ret); + goto fail; + } + } + + memset(physmem, 0, sizeof(*physmem)); + + kfree(physmem); + + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +struct avcm *vcm_assoc(struct vcm *vcm, size_t dev_id, uint32_t attr) +{ + unsigned long flags; + struct avcm *avcm = NULL; + + spin_lock_irqsave(&vcmlock, flags); + + if (!vcm) { + vcm_err("vcm is NULL\n"); + goto fail; + } + + if (!dev_id) { + vcm_err("dev_id is NULL\n"); + goto fail; + } + + if (vcm->type == VCM_EXT_KERNEL && !list_empty(&vcm->assoc_head)) { + vcm_err("only one device may be assocoated with a" + " VCM_EXT_KERNEL\n"); + goto fail; + } + + avcm = kzalloc(sizeof(*avcm), GFP_KERNEL); + if (!avcm) { + vcm_err("kzalloc(%i, GFP_KERNEL) ret NULL\n", sizeof(*avcm)); + goto fail; + } + + avcm->dev_id = dev_id; + + avcm->vcm_id = vcm; + avcm->attr = attr; + avcm->is_active = 0; + + INIT_LIST_HEAD(&avcm->assoc_elm); + list_add(&avcm->assoc_elm, &vcm->assoc_head); + + spin_unlock_irqrestore(&vcmlock, flags); + return avcm; + +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +} + + +int vcm_deassoc(struct avcm *avcm) +{ + unsigned long flags; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) { + vcm_err("avcm is NULL\n"); + goto fail; + } + + if (list_empty(&avcm->assoc_elm)) { + vcm_err("nothing to deassociate\n"); + goto fail; + } + + if (avcm->is_active) { + vcm_err("association still activated\n"); + goto fail_busy; + } + + list_del(&avcm->assoc_elm); + + memset(avcm, 0, sizeof(*avcm)); + + kfree(avcm); + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +fail_busy: + spin_unlock_irqrestore(&vcmlock, flags); + return -EBUSY; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_set_assoc_attr(struct avcm *avcm, uint32_t attr) +{ + return 0; +} + + +uint32_t vcm_get_assoc_attr(struct avcm *avcm) +{ + return 0; +} + + +int vcm_activate(struct avcm *avcm) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) { + vcm_err("avcm is NULL\n"); + goto fail; + } + + vcm = avcm->vcm_id; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!avcm->dev_id) { + vcm_err("cannot activate without a device\n"); + goto fail_nodev; + } + + if (avcm->is_active) { + vcm_err("double activate\n"); + goto fail_busy; + } + + if (vcm->type == VCM_DEVICE) { +#ifdef CONFIG_SMMU + int ret = smmu_is_active((struct smmu_dev *) avcm->dev_id); + if (ret == -1) { + vcm_err("smmu_is_active(%p) ret -1\n", + (void *) avcm->dev_id); + goto fail_dev; + } + + if (ret == 1) { + vcm_err("SMMU is already active\n"); + goto fail_busy; + } + + /* TODO, pmem check */ + ret = smmu_activate((struct smmu_dev *) avcm->dev_id); + if (ret != 0) { + vcm_err("smmu_activate(%p) ret %i" + " SMMU failed to activate\n", + (void *) avcm->dev_id, ret); + goto fail_dev; + } +#else + vcm_err("No SMMU support - cannot activate/deactivate\n"); + goto fail_nodev; +#endif + } + + avcm->is_active = 1; + spin_unlock_irqrestore(&vcmlock, flags); + return 0; + +#ifdef CONFIG_SMMU +fail_dev: + spin_unlock_irqrestore(&vcmlock, flags); + return -1; +#endif +fail_busy: + spin_unlock_irqrestore(&vcmlock, flags); + return -EBUSY; +fail_nodev: + spin_unlock_irqrestore(&vcmlock, flags); + return -ENODEV; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + + +int vcm_deactivate(struct avcm *avcm) +{ + unsigned long flags; + struct vcm *vcm; + + spin_lock_irqsave(&vcmlock, flags); + + if (!avcm) + goto fail; + + vcm = avcm->vcm_id; + if (!vcm) { + vcm_err("NULL vcm\n"); + goto fail; + } + + if (!avcm->dev_id) { + vcm_err("cannot deactivate without a device\n"); + goto fail; + } + + if (!avcm->is_active) { + vcm_err("double deactivate\n"); + goto fail_nobusy; + } + + if (vcm->type == VCM_DEVICE) { +#ifdef CONFIG_SMMU + int ret = smmu_is_active((struct smmu_dev *) avcm->dev_id); + if (ret == -1) { + vcm_err("smmu_is_active(%p) ret %i\n", + (void *) avcm->dev_id, ret); + goto fail_dev; + } + + if (ret == 0) { + vcm_err("double SMMU deactivation\n"); + goto fail_nobusy; + } + + /* TODO, pmem check */ + ret = smmu_deactivate((struct smmu_dev *) avcm->dev_id); + if (ret != 0) { + vcm_err("smmu_deactivate(%p) ret %i\n", + (void *) avcm->dev_id, ret); + goto fail_dev; + } +#else + vcm_err("No SMMU support - cannot activate/deactivate\n"); + goto fail; +#endif + } + + avcm->is_active = 0; + spin_unlock_irqrestore(&vcmlock, flags); + return 0; +#ifdef CONFIG_SMMU +fail_dev: + spin_unlock_irqrestore(&vcmlock, flags); + return -1; +#endif +fail_nobusy: + spin_unlock_irqrestore(&vcmlock, flags); + return -ENOENT; +fail: + spin_unlock_irqrestore(&vcmlock, flags); + return -EINVAL; +} + +struct bound *vcm_create_bound(struct vcm *vcm, size_t len) +{ + return 0; +} + + +int vcm_free_bound(struct bound *bound) +{ + return -1; +} + + +struct res *vcm_reserve_from_bound(struct bound *bound, size_t len, + uint32_t attr) +{ + return 0; +} + + +size_t vcm_get_bound_start_addr(struct bound *bound) +{ + return 0; +} + + +size_t vcm_get_bound_len(struct bound *bound) +{ + return 0; +} + + +struct physmem *vcm_map_phys_addr(size_t phys, size_t len) +{ + return 0; +} + + +size_t vcm_get_next_phys_addr(struct physmem *physmem, size_t phys, size_t *len) +{ + return 0; +} + + +size_t vcm_get_dev_addr(struct res *res) +{ + if (!res) { + vcm_err("res is NULL\n"); + return 0; + } + + return res->aligned_ptr; +} + + +struct res *vcm_get_res(size_t dev_addr, struct vcm *vcm) +{ + return 0; +} + + +size_t vcm_translate(size_t src_dev, struct vcm *src_vcm, struct vcm *dst_vcm) +{ + return 0; +} + + +size_t vcm_get_phys_num_res(size_t phys) +{ + return 0; +} + + +struct res *vcm_get_next_phys_res(size_t phys, struct res *res_id, size_t *len) +{ + return 0; +} + + +size_t vcm_get_pgtbl_pa(struct vcm *vcm) +{ + return 0; +} + + +/* No lock needed, smmu_translate has its own lock */ +size_t vcm_dev_addr_to_phys_addr(size_t dev_id, size_t dev_addr) +{ +#ifdef CONFIG_SMMU + int ret; + ret = smmu_translate((struct smmu_dev *) dev_id, dev_addr); + if (ret == -1) + vcm_err("smmu_translate(%p, %p) ret %i\n", + (void *) dev_id, (void *) dev_addr, ret); + + return ret; +#else + vcm_err("No support for SMMU - manual translation not supported\n"); + return -1; +#endif +} + + +/* No lock needed, bootmem_cont never changes after */ +size_t vcm_get_cont_memtype_pa(enum memtype_t memtype) +{ + if (memtype != VCM_MEMTYPE_0) { + vcm_err("memtype != VCM_MEMTYPE_0\n"); + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont 0\n"); + goto fail; + } + + return (size_t) __pa(bootmem_cont); +fail: + return 0; +} + + +/* No lock needed, constant */ +size_t vcm_get_cont_memtype_len(enum memtype_t memtype) +{ + if (memtype != VCM_MEMTYPE_0) { + vcm_err("memtype != VCM_MEMTYPE_0\n"); + return 0; + } + + return CONT_SZ; +} + +int vcm_hook(size_t dev_id, vcm_handler handler, void *data) +{ +#ifdef CONFIG_SMMU + int ret; + + ret = smmu_hook_irpt((struct smmu_dev *) dev_id, handler, data); + if (ret != 0) + vcm_err("smmu_hook_irpt(%p, %p, %p) ret %i\n", (void *) dev_id, + (void *) handler, (void *) data, ret); + + return ret; +#else + vcm_err("No support for SMMU - interrupts not supported\n"); + return -1; +#endif +} + + +size_t vcm_hw_ver(size_t dev_id) +{ + return 0; +} + + +static int vcm_cont_phys_chunk_init(void) +{ + int i; + int cont_pa; + + if (!cont_phys_chunk) { + vcm_err("cont_phys_chunk 0\n"); + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont 0\n"); + goto fail; + } + + cont_pa = (int) __pa(bootmem_cont); + + for (i = 0; i < CONT_SZ/PAGE_SIZE; ++i) { + cont_phys_chunk[i].pa = (int) cont_pa; cont_pa += PAGE_SIZE; + cont_phys_chunk[i].size_idx = IDX_4K; + INIT_LIST_HEAD(&cont_phys_chunk[i].allocated); + } + + return 0; + +fail: + return -1; +} + + +int vcm_sys_init(void) +{ + int ret; + printk(KERN_INFO "VCM Initialization\n"); + if (!bootmem) { + vcm_err("bootmem is 0\n"); + ret = -1; + goto fail; + } + + if (!bootmem_cont) { + vcm_err("bootmem_cont is 0\n"); + ret = -1; + goto fail; + } + + ret = vcm_setup_tex_classes(); + if (ret != 0) { + printk(KERN_INFO "Could not determine TEX attribute mapping\n"); + ret = -1; + goto fail; + } + + + ret = vcm_alloc_init(__pa(bootmem)); + if (ret != 0) { + vcm_err("vcm_alloc_init(%p) ret %i\n", (void *) __pa(bootmem), + ret); + ret = -1; + goto fail; + } + + cont_phys_chunk = kzalloc(sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE), + GFP_KERNEL); + if (!cont_phys_chunk) { + vcm_err("kzalloc(%lu, GFP_KERNEL) ret 0", + sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE)); + goto fail_free; + } + + /* the address and size will hit our special case unless we + pass an override */ + cont_vcm_id = vcm_create_flagged(0, __pa(bootmem_cont), CONT_SZ); + if (cont_vcm_id == 0) { + vcm_err("vcm_create_flagged(0, %p, %i) ret 0\n", + (void *) __pa(bootmem_cont), CONT_SZ); + ret = -1; + goto fail_free2; + } + + ret = vcm_cont_phys_chunk_init(); + if (ret != 0) { + vcm_err("vcm_cont_phys_chunk_init() ret %i\n", ret); + goto fail_free3; + } + + printk(KERN_INFO "VCM Initialization OK\n"); + return 0; + +fail_free3: + ret = __vcm_free(cont_vcm_id); + if (ret != 0) { + vcm_err("vcm_free(%p) ret %i during failure path\n", + (void *) cont_vcm_id, ret); + return -1; + } + +fail_free2: + kfree(cont_phys_chunk); + cont_phys_chunk = 0; + +fail_free: + ret = vcm_alloc_destroy(); + if (ret != 0) + vcm_err("vcm_alloc_destroy() ret %i during failure path\n", + ret); + + ret = -1; +fail: + return ret; +} + + +int vcm_sys_destroy(void) +{ + int ret = 0; + + if (!cont_phys_chunk) { + vcm_err("cont_phys_chunk is 0\n"); + return -1; + } + + if (!cont_vcm_id) { + vcm_err("cont_vcm_id is 0\n"); + return -1; + } + + ret = __vcm_free(cont_vcm_id); + if (ret != 0) { + vcm_err("vcm_free(%p) ret %i\n", (void *) cont_vcm_id, ret); + return -1; + } + + cont_vcm_id = 0; + + kfree(cont_phys_chunk); + cont_phys_chunk = 0; + + ret = vcm_alloc_destroy(); + if (ret != 0) { + vcm_err("vcm_alloc_destroy() ret %i\n", ret); + return -1; + } + + return ret; +} + +int vcm_init(void) +{ + int ret; + + bootmem = __alloc_bootmem(BOOTMEM_SZ, BOOTMEM_ALIGN, 0); + if (!bootmem) { + vcm_err("segregated block pool alloc failed:" + " __alloc_bootmem(%i, %i, 0)\n", + BOOTMEM_SZ, BOOTMEM_ALIGN); + goto fail; + } + + bootmem_cont = __alloc_bootmem(CONT_SZ, CONT_ALIGN, 0); + if (!bootmem_cont) { + vcm_err("contiguous pool alloc failed:" + " __alloc_bootmem(%i, %i, 0)\n", + CONT_SZ, CONT_ALIGN); + goto fail_free; + } + + ret = vcm_sys_init(); + if (ret != 0) { + vcm_err("vcm_sys_init() ret %i\n", ret); + goto fail_free2; + } + + return 0; + +fail_free2: + free_bootmem(__pa(bootmem_cont), CONT_SZ); +fail_free: + free_bootmem(__pa(bootmem), BOOTMEM_SZ); +fail: + return -1; +}; + +/* Useful for testing, and if VCM is ever unloaded */ +void vcm_exit(void) +{ + int ret; + + if (!bootmem_cont) { + vcm_err("bootmem_cont is 0\n"); + goto fail; + } + + if (!bootmem) { + vcm_err("bootmem is 0\n"); + goto fail; + } + + ret = vcm_sys_destroy(); + if (ret != 0) { + vcm_err("vcm_sys_destroy() ret %i\n", ret); + goto fail; + } + + free_bootmem(__pa(bootmem_cont), CONT_SZ); + free_bootmem(__pa(bootmem), BOOTMEM_SZ); +fail: + return; +} +early_initcall(vcm_init); +module_exit(vcm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Zach Pfeffer "); diff --git a/include/linux/vcm.h b/include/linux/vcm.h new file mode 100644 index 0000000..d2a1cd1 --- /dev/null +++ b/include/linux/vcm.h @@ -0,0 +1,701 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _VCM_H_ +#define _VCM_H_ + +/* All undefined types must be defined using platform specific headers */ + +#include + +/* + * Virtual contiguous memory (VCM) region primitives. + * + * Current memory mapping software uses a CPU centric management + * model. This makes sense in general, average hardware only contains an + * CPU MMU and possibly a graphics MMU. If every device in the system + * has one or more MMUs a CPU centric MM programming model breaks down. + * + * Looking at mapping from a system-wide perspective reveals a general + * graph problem. Each node that talks to memory, either through an MMU + * or directly (via physical memory) can be thought of as the device end + * of a mapping edge. The other edge is the physical memory that is + * mapped. + * + * In the direct mapped case, it is useful to give the device an + * MMU. This one-to-one MMU allows direct mapped devices to + * participate in graph management, they simply see memory through a + * one-to-one mapping. + * + * The CPU nodes can also be brought under the same mapping + * abstraction with the use of a light overlay on the existing + * VMM. This light overlay brings the VMM's page table abstraction for + * each process and the kernel into the graph management API. + * + * Taken together this system wide approach provides a capability that + * is greater than the sum of its parts by allowing users to reason + * about system wide mapping issues without getting bogged down in CPU + * centric device page table management issues. + */ + + +/* + * Creating, freeing and managing VCMs. + * + * A VCM region is a virtual space that can be reserved from and + * associated with one or more devices. At creation the user can + * specify an offset to start addresses and a length of the entire VCM + * region. Reservations out of a VCM region are always contiguous. + */ + +/** + * vcm_create() - Create a VCM region + * @start_addr The starting address of the VCM region. + * @len The len of the VCM region. This must be at least + * vcm_get_min_page_size() bytes. + * + * A VCM typically abstracts a page table. + * + * All functions in this API are passed and return opaque things + * because the underlying implementations will vary. The goal + * is really graph management. vcm_create() creates the "device end" + * of an edge in the mapping graph. + * + * The return value is non-zero if a VCM has successfully been + * created. It will return zero if a VCM region cannot be created or + * len is invalid. + */ +struct vcm *vcm_create(size_t start_addr, size_t len); + + +/** + * vcm_create_from_prebuilt() - Create a VCM region from an existing region + * @ext_vcm_id An external opaque value that allows the + * implementation to reference an already built table. + * + * The ext_vcm_id will probably reference a page table that's been built + * by the VM. + * + * The platform specific implementation will provide this. + * + * The return value is non-zero if a VCM has successfully been created. + */ +struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id); + + +/** + * vcm_clone() - Clone a VCM + * @vcm_id A VCM to clone from. + * + * Perform a VCM "deep copy." The resulting VCM will match the original at + * the point of cloning. Subsequent updates to either VCM will only be + * seen by that VCM. + * + * The return value is non-zero if a VCM has been successfully cloned. + */ +struct vcm *vcm_clone(struct vcm *vcm_id); + + +/** + * vcm_get_start_addr() - Get the starting address of the VCM region. + * @vcm_id The VCM we're interested in getting the starting address of. + * + * The return value will be 1 if an error has occurred. + */ +size_t vcm_get_start_addr(struct vcm *vcm_id); + + +/** + * vcm_get_len() - Get the length of the VCM region. + * @vcm_id The VCM we're interested in reading the length from. + * + * The return value will be non-zero for a valid VCM. VCM regions + * cannot have 0 len. + */ +size_t vcm_get_len(struct vcm *vcm_id); + + +/** + * vcm_free() - Free a VCM. + * @vcm_id The VCM we're interested in freeing. + * + * The return value is 0 if the VCM has been freed or: + * -EBUSY The VCM region contains reservations or has been associated + * (active or not) and cannot be freed. + * -EINVAL The vcm argument is invalid. + */ +int vcm_free(struct vcm *vcm_id); + + +/* + * Creating, freeing and managing reservations out of a VCM. + * + */ + +/** + * vcm_reserve() - Create a reservation from a VCM region. + * @vcm_id The VCM region to reserve from. + * @len The length of the reservation. Must be at least + * vcm_get_min_page_size() bytes. + * @attr See 'Reservation Attributes'. + * + * A reservation, res_t, is a contiguous range from a VCM region. + * + * The return value is non-zero if a reservation has been successfully + * created. It is 0 if any of the parameters are invalid. + */ +struct res *vcm_reserve(struct vcm *vcm_id, size_t len, uint32_t attr); + + +/** + * vcm_reserve_at() - Make a reservation at a given logical location. + * @memtarget A logical location to start the reservation from. + * @vcm_id The VCM region to start the reservation from. + * @len The length of the reservation. + * @attr See 'Reservation Attributes'. + * + * The return value is non-zero if a reservation has been successfully + * created. + */ +struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm *vcm_id, + size_t len, uint32_t attr); + + +/** + * vcm_get_vcm_from_res() - Return the VCM region of a reservation. + * @res_id The reservation to return the VCM region of. + * + * Te return value will be non-zero if the reservation is valid. A valid + * reservation is always associated with a VCM region; there is no such + * thing as an orphan reservation. + */ +struct vcm *vcm_get_vcm_from_res(struct res *res_id); + + +/** + * vcm_unreserve() - Unreserve the reservation. + * @res_id The reservation to unreserve. + * + * The return value will be 0 if the reservation was successfully + * unreserved and: + * -EBUSY The reservation is still backed, + * -EINVAL The vcm argument is invalid. + */ +int vcm_unreserve(struct res *res_id); + + +/** + * vcm_get_res_len() - Return a reservations contiguous length. + * @res_id The reservation of interest. + * + * The return value will be 0 if res is invalid; reservations cannot + * have 0 length so there's no error return value ambiguity. + */ +size_t vcm_get_res_len(struct res *res_id); + + +/** + * vcm_set_res_attr() - Set attributes of an existing reservation. + * @res_id An existing reservation of interest. + * @attr See 'Reservation Attributes'. + * + * This function can only be used on an existing reservation; there + * are no orphan reservations. All attributes can be set on a existing + * reservation. + * + * The return value will be 0 for a success, otherwise it will be: + * -EINVAL res or attr are invalid. + */ +int vcm_set_res_attr(struct res *res_id, uint32_t attr); + + +/** + * vcm_get_res_attr() - Return a reservation's attributes. + * @res_id An existing reservation of interest. + * + * The return value will be 0 if res is invalid. + */ +uint32_t vcm_get_res_attr(struct res *res_id); + + +/** + * vcm_get_num_res() - Return the number of reservations in a VCM region. + * @vcm_id The VCM region of interest. + */ +size_t vcm_get_num_res(struct vcm *vcm_id); + + +/** + * vcm_get_next_res() - Read each reservation one at a time. + * @vcm_id The VCM region of interest. + * @res_id Contains the last reservation. Pass NULL on the first call. + * + * This function works like a foreach reservation in a VCM region. + * + * The return value will be non-zero for each reservation in a VCM. A + * zero indicates no further reservations. + */ +struct res *vcm_get_next_res(struct vcm *vcm_id, struct res *res_id); + + +/** + * vcm_res_copy() - Copy len bytes from one reservation to another. + * @to The reservation to copy to. + * @from The reservation to copy from. + * @len The length of bytes to copy. + * + * The return value is the number of bytes copied. + */ +size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, size_t + from_off, size_t len); + + +/** + * vcm_get_min_page_size() - Return the minimum page size supported by + * the architecture. + */ +size_t vcm_get_min_page_size(void); + + +/** + * vcm_back() - Physically back a reservation. + * @res_id The reservation containing the virtual contiguous region to + * back. + * @physmem_id The physical memory that will back the virtual contiguous + * memory region. + * + * One VCM can be associated with multiple devices. When you vcm_back() + * each association must be active. This is not strictly necessary. It may + * be changed in the future. + * + * This function returns 0 on a successful physical backing. Otherwise + * it returns: + * -EINVAL res or physmem is invalid or res's len + * is different from physmem's len. + * -EAGAIN try again, one of the devices hasn't been activated. + */ +int vcm_back(struct res *res_id, struct physmem *physmem_id); + + +/** + * vcm_unback() - Unback a reservation. + * @res_id The reservation to unback. + * + * One VCM can be associated with multiple devices. When you vcm_unback() + * each association must be active. + * + * This function returns 0 on a successful unbacking. Otherwise + * it returns: + * -EINVAL res is invalid. + * -EAGAIN try again, one of the devices hasn't been activated. + */ +int vcm_unback(struct res *res_id); + + +/** + * vcm_phys_alloc() - Allocate physical memory for the VCM region. + * @memtype The memory type to allocate. + * @len The length of the allocation. + * @attr See 'Physical Allocation Attributes'. + * + * This function will allocate chunks of memory according to the attr + * it is passed. + * + * The return value is non-zero if physical memory has been + * successfully allocated. + */ +struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len, + uint32_t attr); + + +/** + * vcm_phys_free() - Free a physical allocation. + * @physmem_id The physical allocation to free. + * + * The return value is 0 if the physical allocation has been freed or: + * -EBUSY Their are reservation mapping the physical memory. + * -EINVAL The physmem argument is invalid. + */ +int vcm_phys_free(struct physmem *physmem_id); + + +/** + * vcm_get_physmem_from_res() - Return a reservation's physmem_id + * @ res_id An existing reservation of interest. + * + * The return value will be non-zero on success, otherwise it will be: + * -EINVAL res is invalid + * -ENOMEM res is unbacked + */ +struct physmem *vcm_get_physmem_from_res(struct res *res_id); + + +/** + * vcm_get_memtype_of_physalloc() - Return the memtype of a reservation. + * @physmem_id The physical allocation of interest. + * + * This function returns the memtype of a reservation or VCM_INVALID + * if res is invalid. + */ +enum memtype_t vcm_get_memtype_of_physalloc(struct physmem *physmem_id); + + +/* + * Associate a VCM with a device, activate that association and remove it. + * + */ + +/** + * vcm_assoc() - Associate a VCM with a device. + * @vcm_id The VCM region of interest. + * @dev_id The device to associate the VCM with. + * @attr See 'Association Attributes'. + * + * This function returns non-zero if a association is made. It returns 0 + * if any of its parameters are invalid or VCM_ATTR_VALID is not present. + */ +struct avcm *vcm_assoc(struct vcm *vcm_id, size_t dev_id, uint32_t attr); + + +/** + * vcm_deassoc() - Deassociate a VCM from a device. + * @avcm_id The association we want to break. + * + * The function returns 0 on success or: + * -EBUSY The association is currently activated. + * -EINVAL The avcm parameter is invalid. + */ +int vcm_deassoc(struct avcm *avcm_id); + + +/** + * vcm_set_assoc_attr() - Set an AVCM's attributes. + * @avcm_id The AVCM of interest. + * @attr The new attr. See 'Association Attributes'. + * + * Every attribute can be set at runtime if an association isn't activated. + * + * This function returns 0 on success or: + * -EBUSY The association is currently activated. + * -EINVAL The avcm parameter is invalid. + */ +int vcm_set_assoc_attr(struct avcm *avcm_id, uint32_t attr); + + +/** + * vcm_get_assoc_attr() - Return an AVCM's attributes. + * @avcm_id The AVCM of interest. + * + * This function returns 0 on error. + */ +uint32_t vcm_get_assoc_attr(struct avcm *avcm_id); + + +/** + * vcm_activate() - Activate an AVCM. + * @avcm_id The AVCM to activate. + * + * You have to deactivate, before you activate. + * + * This function returns 0 on success or: + * -EINVAL avcm is invalid + * -ENODEV no device + * -EBUSY device is already active + * -1 hardware failure + */ +int vcm_activate(struct avcm *avcm_id); + + +/** + * vcm_deactivate() - Deactivate an association. + * @avcm_id The AVCM to deactivate. + * + * This function returns 0 on success or: + * -ENOENT avcm is not activate + * -EINVAL avcm is invalid + * -1 hardware failure + */ +int vcm_deactivate(struct avcm *avcm_id); + + +/** + * vcm_is_active() - Query if an AVCM is active. + * @avcm_id The AVCM of interest. + * + * returns 0 for not active, 1 for active or -EINVAL for error. + * + */ +int vcm_is_active(struct avcm *avcm_id); + + + +/* + * Create, manage and remove a boundary in a VCM. + */ + +/** + * vcm_create_bound() - Create a bound in a VCM. + * @vcm_id The VCM that needs a bound. + * @len The len of the bound. + * + * The allocator picks the virtual addresses of the bound. + * + * This function returns non-zero if a bound was created. + */ +struct bound *vcm_create_bound(struct vcm *vcm_id, size_t len); + + +/** + * vcm_free_bound() - Free a bound. + * @bound_id The bound to remove. + * + * This function returns 0 if bound has been removed or: + * -EBUSY The bound contains reservations and cannot be removed. + * -EINVAL The bound is invalid. + */ +int vcm_free_bound(struct bound *bound_id); + + +/** + * vcm_reserve_from_bound() - Make a reservation from a bounded area. + * @bound_id The bound to reserve from. + * @len The len of the reservation. + * @attr See 'Reservation Attributes'. + * + * The return value is non-zero on success. It is 0 if any parameter + * is invalid. + */ +struct res *vcm_reserve_from_bound(struct bound *bound_id, size_t len, + uint32_t attr); + + +/** + * vcm_get_bound_start_addr() - Return the starting device address of the bound. + * @bound_id The bound of interest. + * + * On success this function returns the starting addres of the bound. On error + * it returns: + * 1 bound_id is invalid. + */ +size_t vcm_get_bound_start_addr(struct bound *bound_id); + + +/** + * vcm_get_bound_len() - Return the len of a bound. + * @bound_id The bound of interest. + * + * This function return non-zero on success, 0 on failure. + */ +size_t vcm_get_bound_len(struct bound *bound_id); + + + +/* + * Perform low-level control over VCM regions and reservations. + */ + +/** + * vcm_map_phys_addr() - Produce a physmem_id from a contiguous + * physical address + * + * @phys The physical address of the contiguous range. + * @len The len of the contiguous address range. + * + * Returns non-zero on success, 0 on failure. + */ +struct physmem *vcm_map_phys_addr(size_t phys, size_t len); + + +/** + * vcm_get_next_phys_addr() - Get the next physical addr and len of a + * physmem_id. + * @res_id The physmem_id of interest. + * @phys The current physical address. Set this to NULL to start the + * iteration. + * @len An output: the len of the next physical segment. + * + * physmem_id's may contain physically discontiguous sections. This + * function returns the next physical address and len. Pass NULL to + * phys to get the first physical address. The len of the physical + * segment is returned in *len. + * + * Returns 0 if there is no next physical address. + */ +size_t vcm_get_next_phys_addr(struct physmem *physmem_id, size_t phys, + size_t *len); + + +/** + * vcm_get_dev_addr() - Return the device address of a reservation. + * @res_id The reservation of interest. + * + * + * On success this function returns the device address of a reservation. On + * error it returns: + * 1 res_id is invalid. + * + * Note: This may return a kernel address if the reservation was + * created from vcm_create_from_prebuilt() and the prebuilt ext_vcm_id + * references a VM page table. + */ +size_t vcm_get_dev_addr(struct res *res_id); + + +/** + * vcm_get_res() - Return the reservation from a device address and a VCM + * @dev_addr The device address of interest. + * @vcm_id The VCM that contains the reservation + * + * This function returns 0 if there is no reservation whose device + * address is dev_addr. + */ +struct res *vcm_get_res(size_t dev_addr, struct vcm *vcm_id); + + +/** + * vcm_translate() - Translate from one device address to another. + * @src_dev_id The source device address. + * @src_vcm_id The source VCM region. + * @dst_vcm_id The destination VCM region. + * + * Derive the device address from a VCM region that maps the same physical + * memory as a device address from another VCM region. + * + * On success this function returns the device address of a translation. On + * error it returns: + * 1 res_id is invalid. + */ +size_t vcm_translate(size_t src_dev_id, struct vcm *src_vcm_id, + struct vcm *dst_vcm_id); + + +/** + * vcm_get_phys_num_res() - Return the number of reservations mapping a + * physical address. + * @phys The physical address to read. + */ +size_t vcm_get_phys_num_res(size_t phys); + + +/** + * vcm_get_next_phys_res() - Return the next reservation mapped to a physical + * address. + * @phys The physical address to map. + * @res_id The starting reservation. Set this to NULL for the first + * reservation. + * @len The virtual length of the reservation + * + * This function returns 0 for the last reservation or no reservation. + */ +struct res *vcm_get_next_phys_res(size_t phys, struct res *res_id, size_t *len); + + +/** + * vcm_get_pgtbl_pa() - Return the physcial address of a VCM's page table. + * @vcm_id The VCM region of interest. + * + * This function returns non-zero on success. + */ +size_t vcm_get_pgtbl_pa(struct vcm *vcm_id); + + +/** + * vcm_get_cont_memtype_pa() - Return the phys base addr of a memtype's + * first contiguous region. + * @memtype The memtype of interest. + * + * This function returns non-zero on success. A zero return indicates that + * the given memtype does not have a contiguous region or that the memtype + * is invalid. + */ +size_t vcm_get_cont_memtype_pa(enum memtype_t memtype); + + +/** + * vcm_get_cont_memtype_len() - Return the len of a memtype's + * first contiguous region. + * @memtype The memtype of interest. + * + * This function returns non-zero on success. A zero return indicates that + * the given memtype does not have a contiguous region or that the memtype + * is invalid. + */ +size_t vcm_get_cont_memtype_len(enum memtype_t memtype); + + +/** + * vcm_dev_addr_to_phys_addr() - Perform a device address page-table lookup. + * @dev_id The device that has the table. + * @dev_addr The device address to map. + * + * This function returns the pa of a va from a device's page-table. It will + * fault if the dev_addr is not mapped. + */ +size_t vcm_dev_addr_to_phys_addr(size_t dev_id, size_t dev_addr); + + +/* + * Fault Hooks + * + * vcm_hook() + */ + +/** + * vcm_hook() - Add a fault handler. + * @dev_id The device. + * @handler The handler. + * @data A private piece of data that will get passed to the handler. + * + * This function returns 0 for a successful registration or: + * -EINVAL The arguments are invalid. + */ +int vcm_hook(size_t dev_id, vcm_handler handler, void *data); + + + +/* + * Low level, platform agnostic, HW control. + * + * vcm_hw_ver() + */ + +/** + * vcm_hw_ver() - Return the hardware version of a device, if it has one. + * @dev_id The device. + */ +size_t vcm_hw_ver(size_t dev_id); + + + +/* bring-up init, destroy */ +int vcm_sys_init(void); +int vcm_sys_destroy(void); + +#endif /* _VCM_H_ */ + diff --git a/include/linux/vcm_types.h b/include/linux/vcm_types.h new file mode 100644 index 0000000..2cc4770 --- /dev/null +++ b/include/linux/vcm_types.h @@ -0,0 +1,318 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef VCM_TYPES_H +#define VCM_TYPES_H + +#include +#include +#include +#include +#include +#include + +/* + * Reservation Attributes + * + * Used in vcm_reserve(), vcm_reserve_at(), vcm_set_res_attr() and + * vcm_reserve_bound(). + * + * VCM_READ Specifies that the reservation can be read. + * VCM_WRITE Specifies that the reservation can be written. + * VCM_EXECUTE Specifies that the reservation can be executed. + * VCM_USER Specifies that this reservation is used for + * userspace access. + * VCM_SUPERVISOR Specifies that this reservation is used for + * supervisor access. + * VCM_SECURE Specifies that the target of the reservation is + * secure. The usage of this setting is TBD. + * + * Caching behavior as a 4 bit field: + * VCM_NOTCACHED The VCM region is not cached. + * VCM_INNER_WB_WA The VCM region is inner cached + * and is write-back and write-allocate. + * VCM_INNER_WT_NWA The VCM region is inner cached and is + * write-through and no-write-allocate. + * VCM_INNER_WB_NWA The VCM region is inner cached and is + * write-back and no-write-allocate. + * VCM_OUTER_WB_WA The VCM region is outer cached and is + * write-back and write-allocate. + * VCM_OUTER_WT_NWA The VCM region is outer cached and is + * write-through and no-write-allocate. + * VCM_OUTER_WB_NWA The VCM region is outer cached and is + * write-back and no-write-allocate. + * VCM_WB_WA The VCM region is cached and is write + * -back and write-allocate. + * VCM_WT_NWA The VCM region is cached and is write + * -through and no-write-allocate. + * VCM_WB_NWA The VCM region is cached and is write + * -back and no-write-allocate. + */ + +#define VCM_CACHE_POLICY (0xF << 0) + +#define VCM_READ (1UL << 9) +#define VCM_WRITE (1UL << 8) +#define VCM_EXECUTE (1UL << 7) +#define VCM_USER (1UL << 6) +#define VCM_SUPERVISOR (1UL << 5) +#define VCM_SECURE (1UL << 4) +#define VCM_NOTCACHED (0UL << 0) +#define VCM_WB_WA (1UL << 0) +#define VCM_WB_NWA (2UL << 0) +#define VCM_WT (3UL << 0) + + +/* + * Physical Allocation Attributes + * + * Used in vcm_phys_alloc(). + * + * Alignment as a power of 2 starting at 4 KB. 5 bit field. + * 1 = 4KB, 2 = 8KB, etc. + * + * Specifies that the reservation should have the + * alignment specified. + * + * VCM_4KB Specifies that the reservation should use 4KB pages. + * VCM_64KB Specifies that the reservation should use 64KB pages. + * VCM_1MB specifies that the reservation should use 1MB pages. + * VCM_ALL Specifies that the reservation should use all + * available page sizes. + * VCM_PHYS_CONT Specifies that a reservation should be backed with + * physically contiguous memory. + * VCM_COHERENT Specifies that the reservation must be kept coherent + * because it's shared. + */ + +#define VCM_ALIGNMENT_MASK (0x1FUL << 6) /* 5-bit field */ +#define VCM_4KB (1UL << 5) +#define VCM_64KB (1UL << 4) +#define VCM_1MB (1UL << 3) +#define VCM_ALL (1UL << 2) +#define VCM_PAGE_SEL_MASK (0xFUL << 2) +#define VCM_PHYS_CONT (1UL << 1) +#define VCM_COHERENT (1UL << 0) + + +#define SHIFT_4KB (12) + +#define ALIGN_REQ_BYTES(attr) (1UL << (((attr & VCM_ALIGNMENT_MASK) >> 6) + 12)) +/* set the alignment in pow 2, 0 = 4KB */ +#define SET_ALIGN_REQ_BYTES(attr, align) \ + ((attr & ~VCM_ALIGNMENT_MASK) | ((align << 6) & VCM_ALIGNMENT_MASK)) + +/* + * Association Attributes + * + * Used in vcm_assoc(), vcm_set_assoc_attr(). + * + * VCM_USE_LOW_BASE Use the low base register. + * VCM_USE_HIGH_BASE Use the high base register. + * + * VCM_SPLIT A 5 bit field that defines the + * high/low split. This value defines + * the number of 0's left-filled into the + * split register. Addresses that match + * this will use VCM_USE_LOW_BASE + * otherwise they'll use + * VCM_USE_HIGH_BASE. An all 0's value + * directs all translations to + * VCM_USE_LOW_BASE. + */ + +#define VCM_SPLIT (1UL << 3) +#define VCM_USE_LOW_BASE (1UL << 2) +#define VCM_USE_HIGH_BASE (1UL << 1) + + +/* + * External VCMs + * + * Used in vcm_create_from_prebuilt() + * + * Externally created VCM IDs for creating kernel and user space + * mappings to VCMs and kernel and user space buffers out of + * VCM_MEMTYPE_0,1,2, etc. + * + */ +#define VCM_PREBUILT_KERNEL 1 +#define VCM_PREBUILT_USER 2 + +/** + * enum memtarget_t - A logical location in a VCM. + * + * VCM_START Indicates the start of a VCM_REGION. + */ +enum memtarget_t { + VCM_START +}; + + +/** + * enum memtype_t - A logical location in a VCM. + * + * VCM_MEMTYPE_0 Generic memory type 0 + * VCM_MEMTYPE_1 Generic memory type 1 + * VCM_MEMTYPE_2 Generic memory type 2 + * + * A memtype encapsulates a platform specific memory arrangement. The + * memtype needn't refer to a single type of memory, it can refer to a + * set of memories that can back a reservation. + * + */ +enum memtype_t { + VCM_INVALID, + VCM_MEMTYPE_0, + VCM_MEMTYPE_1, + VCM_MEMTYPE_2, +}; + + +/** + * vcm_handler - The signature of the fault hook. + * @dev_id The device id of the faulting device. + * @data The generic data pointer. + * @fault_data System specific common fault data. + * + * The handler should return 0 for success. This indicates that the + * fault was handled. A non-zero return value is an error and will be + * propagated up the stack. + */ +typedef int (*vcm_handler)(size_t dev_id, void *data, void *fault_data); + + +enum vcm_type { + VCM_DEVICE, + VCM_EXT_KERNEL, + VCM_EXT_USER, + VCM_ONE_TO_ONE, +}; + + +/** + * vcm - A Virtually Contiguous Memory region. + * @start_addr The starting address of the VCM region. + * @len The len of the VCM region. This must be at least + * vcm_min() bytes. + */ +struct vcm { + enum vcm_type type; + + size_t start_addr; + size_t len; + + size_t dev_id; /* opaque device control */ + + /* allocator dependent */ + struct gen_pool *pool; + + struct list_head res_head; + + /* this will be a very short list */ + struct list_head assoc_head; +}; + +/** + * avcm - A VCM to device association + * @vcm The VCM region of interest. + * @dev_id The device to associate the VCM with. + * @attr See 'Association Attributes'. + */ +struct avcm { + struct vcm *vcm_id; + size_t dev_id; + uint32_t attr; + + struct list_head assoc_elm; + + int is_active; /* is this particular association active */ +}; + +/** + * bound - A boundary to reserve from in a VCM region. + * @vcm The VCM that needs a bound. + * @len The len of the bound. + */ +struct bound { + struct vcm *vcm_id; + size_t len; +}; + + +/** + * physmem - A physical memory allocation. + * @memtype The memory type of the VCM region. + * @len The len of the physical memory allocation. + * @attr See 'Physical Allocation Attributes'. + * + */ + +struct physmem { + enum memtype_t memtype; + size_t len; + uint32_t attr; + + struct phys_chunk alloc_head; + + /* if the physmem is cont then use the built in VCM */ + int is_cont; + struct res *res; +}; + +/** + * res - A reservation in a VCM region. + * @vcm The VCM region to reserve from. + * @len The length of the reservation. Must be at least vcm_min() + * bytes. + * @attr See 'Reservation Attributes'. + */ +struct res { + struct vcm *vcm_id; + struct physmem *physmem_id; + size_t len; + uint32_t attr; + + /* allocator dependent */ + size_t alignment_req; + size_t aligned_len; + unsigned long ptr; + size_t aligned_ptr; + + struct list_head res_elm; + + + /* type VCM_EXT_KERNEL */ + struct vm_struct *vm_area; + int mapped; +}; + +extern int chunk_sizes[NUM_CHUNK_SIZES]; + +#endif /* VCM_TYPES_H */ From patchwork Fri May 7 06:47:48 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Munegowda, Keshava" X-Patchwork-Id: 97596 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o476ltPP015155 for ; Fri, 7 May 2010 06:47:55 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751579Ab0EGGry (ORCPT ); Fri, 7 May 2010 02:47:54 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:46083 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751124Ab0EGGry convert rfc822-to-8bit (ORCPT ); Fri, 7 May 2010 02:47:54 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o476loHe005740 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 7 May 2010 01:47:52 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o476lm3h003404; Fri, 7 May 2010 12:17:49 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Fri, 7 May 2010 12:17:49 +0530 From: "Munegowda, Keshava" To: "linux-omap@vger.kernel.org" , "tony@atomide.com" Date: Fri, 7 May 2010 12:17:48 +0530 Subject: RE: [PATCH V2]omap: mux.c warning removal Thread-Topic: RE: [PATCH V2]omap: mux.c warning removal Thread-Index: AcrtsTTTwTUfkYV7TiWgK3XcrPsKLA== Message-ID: <0680EC522D0CC943BC586913CF3768C003B31655C3@dbde02.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 07 May 2010 06:47:56 +0000 (UTC) Index: linux-2.6/arch/arm/mach-omap2/mux.c =================================================================== --- linux-2.6.orig/arch/arm/mach-omap2/mux.c 2010-05-05 23:59:19.000000000 +0530 +++ linux-2.6/arch/arm/mach-omap2/mux.c 2010-05-06 00:00:07.000000000 +0530 @@ -49,7 +49,7 @@ struct list_head node; }; -static unsigned long mux_phys; + static void __iomem *mux_base; u16 omap_mux_read(u16 reg) @@ -373,6 +373,7 @@ #ifdef CONFIG_ARCH_OMAP3 static LIST_HEAD(muxmodes); static DEFINE_MUTEX(muxmode_mutex); +static unsigned long mux_phys; #ifdef CONFIG_OMAP_MUX From patchwork Thu Jun 24 08:14:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jan sebastien X-Patchwork-Id: 107805 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5O8GZpE015350 for ; Thu, 24 Jun 2010 08:16:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753970Ab0FXIQ0 (ORCPT ); Thu, 24 Jun 2010 04:16:26 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39183 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751048Ab0FXIQZ (ORCPT ); Thu, 24 Jun 2010 04:16:25 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5O8GNw7020559 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 24 Jun 2010 03:16:23 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o5O8GKGg000651; Thu, 24 Jun 2010 03:16:21 -0500 (CDT) From: Sebastien Jan To: Steve Glendinning , netdev@vger.kernel.org Cc: linux-omap@vger.kernel.org, Sebastien Jan Subject: [PATCH] smsc95xx: Add module parameter to override MAC address Date: Thu, 24 Jun 2010 10:14:14 +0200 Message-Id: <1277367254-9345-1-git-send-email-s-jan@ti.com> X-Mailer: git-send-email 1.6.3.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 24 Jun 2010 08:17:07 +0000 (UTC) diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c index 3135af6..0ba06d9 100644 --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c @@ -46,6 +46,7 @@ #define SMSC95XX_INTERNAL_PHY_ID (1) #define SMSC95XX_TX_OVERHEAD (8) #define SMSC95XX_TX_OVERHEAD_CSUM (12) +#define MAC_ADDR_LEN (6) struct smsc95xx_priv { u32 mac_cr; @@ -63,6 +64,10 @@ static int turbo_mode = true; module_param(turbo_mode, bool, 0644); MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); +static char *macaddr = ":"; +module_param(macaddr, charp, 0); +MODULE_PARM_DESC(macaddr, "MAC address"); + static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data) { u32 *buf = kmalloc(4, GFP_KERNEL); @@ -637,8 +642,59 @@ static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); } +/* Check the macaddr module parameter for a MAC address */ +static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac) +{ + int i, j, got_num, num; + u8 mtbl[MAC_ADDR_LEN]; + + if (macaddr[0] == ':') + return 0; + + i = 0; + j = 0; + num = 0; + got_num = 0; + while (j < MAC_ADDR_LEN) { + if (macaddr[i] && macaddr[i] != ':') { + got_num++; + if ('0' <= macaddr[i] && macaddr[i] <= '9') + num = num * 16 + macaddr[i] - '0'; + else if ('A' <= macaddr[i] && macaddr[i] <= 'F') + num = num * 16 + 10 + macaddr[i] - 'A'; + else if ('a' <= macaddr[i] && macaddr[i] <= 'f') + num = num * 16 + 10 + macaddr[i] - 'a'; + else + break; + i++; + } else if (got_num == 2) { + mtbl[j++] = (u8) num; + num = 0; + got_num = 0; + i++; + } else { + break; + } + } + + if (j == MAC_ADDR_LEN && !macaddr[i]) { + netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: " + "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2], + mtbl[3], mtbl[4], mtbl[5]); + for (i = 0; i < MAC_ADDR_LEN; i++) + dev_mac[i] = mtbl[i]; + return 1; + } else { + return 0; + } +} + static void smsc95xx_init_mac_address(struct usbnet *dev) { + /* Check module parameters */ + if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr)) + return; + /* try reading mac address from EEPROM */ if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, dev->net->dev_addr) == 0) { From patchwork Thu Jul 8 08:33:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 110795 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o688XLCS026213 for ; Thu, 8 Jul 2010 08:33:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754492Ab0GHIdT (ORCPT ); Thu, 8 Jul 2010 04:33:19 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40741 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754175Ab0GHIdR (ORCPT ); Thu, 8 Jul 2010 04:33:17 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o688X8LH013572 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 03:33:10 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o688X3Tv010638; Thu, 8 Jul 2010 14:03:04 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o688X3Xt030100; Thu, 8 Jul 2010 14:03:03 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o688X3HB030097; Thu, 8 Jul 2010 14:03:03 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Ajay Kumar Gupta Subject: [PATCH 3/4] usb: ulpi: fix compilation warning Date: Thu, 8 Jul 2010 14:03:01 +0530 Message-Id: <1278577982-30046-4-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1278577982-30046-3-git-send-email-ajay.gupta@ti.com> References: <1278577982-30046-1-git-send-email-ajay.gupta@ti.com> <1278577982-30046-2-git-send-email-ajay.gupta@ti.com> <1278577982-30046-3-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 08:33:29 +0000 (UTC) diff --git a/include/linux/usb/ulpi.h b/include/linux/usb/ulpi.h index 2369d07..900d97b 100644 --- a/include/linux/usb/ulpi.h +++ b/include/linux/usb/ulpi.h @@ -11,6 +11,7 @@ #ifndef __LINUX_USB_ULPI_H #define __LINUX_USB_ULPI_H +#include /*-------------------------------------------------------------------------*/ /* From patchwork Tue May 18 20:13:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liam Girdwood X-Patchwork-Id: 100595 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4IKDrc6020751 for ; Tue, 18 May 2010 20:13:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756538Ab0ERUNw (ORCPT ); Tue, 18 May 2010 16:13:52 -0400 Received: from mail-wy0-f174.google.com ([74.125.82.174]:48480 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754806Ab0ERUNv (ORCPT ); Tue, 18 May 2010 16:13:51 -0400 Received: by mail-wy0-f174.google.com with SMTP id 39so1699320wyb.19 for ; Tue, 18 May 2010 13:13:50 -0700 (PDT) Received: by 10.227.152.212 with SMTP id h20mr6878693wbw.176.1274213630585; Tue, 18 May 2010 13:13:50 -0700 (PDT) Received: from localhost.localdomain (host81-136-218-57.in-addr.btopenworld.com [81.136.218.57]) by mx.google.com with ESMTPS id l23sm50762912wbb.8.2010.05.18.13.13.48 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 18 May 2010 13:13:49 -0700 (PDT) From: Liam Girdwood To: , Cc: Liam Girdwood , Mark Brown , Peter Ujfalusi , Jarkko Nikula , Tony Lindgren Subject: [PATCH 2/4] OMAP: mcbsp - add smart idle configuration API Date: Tue, 18 May 2010 21:13:12 +0100 Message-Id: <1274213594-26554-3-git-send-email-lrg@slimlogic.co.uk> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1274213594-26554-1-git-send-email-lrg@slimlogic.co.uk> References: <1274213594-26554-1-git-send-email-lrg@slimlogic.co.uk> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 18 May 2010 20:13:53 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index f8823f4..3f9fb71 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -278,6 +278,15 @@ #define ENAWAKEUP 0x0004 #define SOFTRST 0x0002 +#define MCBSP_CLK_ACT_IOFF_POFF 0 +#define MCBSP_CLK_ACT_ION_POFF 1 +#define MCBSP_CLK_ACT_IOFF_PON 2 +#define MCBSP_CLK_ACT_ION_PON 3 + +#define MCBSP_IDLE_FORCE 0 +#define MCBSP_IDLE_NONE 1 +#define MCBSP_IDLE_SMART 2 + /********************** McBSP SSELCR bit definitions ***********************/ #define SIDETONEEN 0x0400 @@ -456,6 +465,7 @@ struct omap_mcbsp { #ifdef CONFIG_ARCH_OMAP3 struct omap_mcbsp_st_data *st_data; int dma_op_mode; + int idle_mode; u16 max_tx_thres; u16 max_rx_thres; #endif @@ -477,6 +487,11 @@ u16 omap_mcbsp_get_tx_delay(unsigned int id); u16 omap_mcbsp_get_rx_delay(unsigned int id); int omap_mcbsp_get_dma_op_mode(unsigned int id); int omap_mcbsp_set_dma_op_mode(unsigned int id, unsigned int mode); +int omap_mcbsp_set_idle_smart(unsigned int id, unsigned int clk_activity, + unsigned int wake); +int omap_mcbsp_set_idle_none(unsigned int id); +int omap_mcbsp_set_idle_force(unsigned int id); +int omap_mcbsp_get_idle_mode(unsigned int id); #else static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { } diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index cc2b73c..7785050 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1743,6 +1743,128 @@ static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) omap_st_remove(mcbsp); } } + +/* assert standby requests when idle */ +int omap_mcbsp_set_idle_smart(unsigned int id, unsigned int clk_activity, + u32 wakeup) +{ + struct omap_mcbsp *mcbsp; + u16 syscon; + int ret = 0; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + spin_lock_irq(&mcbsp->lock); + if (!mcbsp->free) { + ret = -EBUSY; + goto unlock; + } + + syscon = MCBSP_READ(mcbsp, SYSCON) & + ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); + MCBSP_WRITE(mcbsp, WAKEUPEN, wakeup); + MCBSP_WRITE(mcbsp, SYSCON, + syscon | SIDLEMODE(MCBSP_IDLE_SMART) | + CLOCKACTIVITY(clk_activity) | ENAWAKEUP); + mcbsp->idle_mode = MCBSP_IDLE_SMART; + +unlock: + spin_unlock_irq(&mcbsp->lock); + return ret; +} +EXPORT_SYMBOL(omap_mcbsp_set_idle_smart); + +/* never assert standby requests */ +int omap_mcbsp_set_idle_none(unsigned int id) +{ + struct omap_mcbsp *mcbsp; + u16 syscon; + int ret = 0; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + spin_lock_irq(&mcbsp->lock); + if (!mcbsp->free) { + ret = -EBUSY; + goto unlock; + } + + syscon = MCBSP_READ(mcbsp, SYSCON) & + ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); + + MCBSP_WRITE(mcbsp, SYSCON, syscon | SIDLEMODE(MCBSP_IDLE_NONE)); + MCBSP_WRITE(mcbsp, WAKEUPEN, 0); + mcbsp->idle_mode = MCBSP_IDLE_NONE; + +unlock: + spin_unlock_irq(&mcbsp->lock); + return ret; +} +EXPORT_SYMBOL(omap_mcbsp_set_idle_none); + +/* unconditionally assert standby requests */ +int omap_mcbsp_set_idle_force(unsigned int id) +{ + struct omap_mcbsp *mcbsp; + u16 syscon; + int ret = 0; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + spin_lock_irq(&mcbsp->lock); + if (!mcbsp->free) { + ret = -EBUSY; + goto unlock; + } + + syscon = MCBSP_READ(mcbsp, SYSCON) & + ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); + /* + * HW bug workaround - If no_idle mode is taken, we need to + * go to smart_idle before going to always_idle, or the + * device will not hit retention anymore. + */ + syscon |= SIDLEMODE(MCBSP_IDLE_SMART); + MCBSP_WRITE(mcbsp, SYSCON, syscon); + syscon &= ~(SIDLEMODE(0x03)); + + MCBSP_WRITE(mcbsp, SYSCON, syscon | SIDLEMODE(MCBSP_IDLE_FORCE)); + MCBSP_WRITE(mcbsp, WAKEUPEN, 0); + mcbsp->idle_mode = MCBSP_IDLE_FORCE; + +unlock: + spin_unlock_irq(&mcbsp->lock); + return ret; +} +EXPORT_SYMBOL(omap_mcbsp_set_idle_force); + +int omap_mcbsp_get_idle_mode(unsigned int id) +{ + struct omap_mcbsp *mcbsp; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + return mcbsp->idle_mode; +} +EXPORT_SYMBOL(omap_mcbsp_get_idle_mode); + + #else static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {} static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {} From patchwork Tue Jul 20 21:41:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kanigeri, Hari" X-Patchwork-Id: 113088 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6KLV1W6032136 for ; Tue, 20 Jul 2010 21:31:01 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754742Ab0GTVa7 (ORCPT ); Tue, 20 Jul 2010 17:30:59 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:46289 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752122Ab0GTVa6 (ORCPT ); Tue, 20 Jul 2010 17:30:58 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6KLUtuD029418 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 20 Jul 2010 16:30:55 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6KLUsXR001656; Tue, 20 Jul 2010 16:30:54 -0500 (CDT) Received: from localhost (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBAG6ZP24219; Fri, 10 Dec 1915 11:06:35 -0500 (CDT) From: Hari Kanigeri To: Linux Omap , Tony Lindgren , Hiroshi DOYU Cc: Ohad Ben-Cohen , Hari Kanigeri Subject: [PATCH 2/2] omap:mailbox-provide multiple reader support Date: Tue, 20 Jul 2010 16:41:36 -0500 Message-Id: <1279662096-3121-3-git-send-email-h-kanigeri2@ti.com> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1279662096-3121-1-git-send-email-h-kanigeri2@ti.com> References: <1279662096-3121-1-git-send-email-h-kanigeri2@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 20 Jul 2010 21:31:01 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h index 0486d64..c8e47d8 100644 --- a/arch/arm/plat-omap/include/plat/mailbox.h +++ b/arch/arm/plat-omap/include/plat/mailbox.h @@ -68,13 +68,15 @@ struct omap_mbox { void *priv; void (*err_notify)(void); + atomic_t use_count; + struct blocking_notifier_head notifier; }; int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); void omap_mbox_init_seq(struct omap_mbox *); -struct omap_mbox *omap_mbox_get(const char *); -void omap_mbox_put(struct omap_mbox *); +struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb); +void omap_mbox_put(struct omap_mbox *, struct notifier_block *nb); int omap_mbox_register(struct device *parent, struct omap_mbox *); int omap_mbox_unregister(struct omap_mbox *); diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index baac315..f9f2af4 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -149,8 +149,8 @@ static void mbox_rx_work(struct work_struct *work) if (unlikely(len != sizeof(msg))) pr_err("%s: kfifo_out anomaly detected\n", __func__); - if (mq->callback) - mq->callback((void *)msg); + blocking_notifier_call_chain(&mq->mbox->notifier, len, + (void *)msg); } } @@ -252,28 +252,30 @@ static int omap_mbox_startup(struct omap_mbox *mbox) } } - ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, - mbox->name, mbox); - if (unlikely(ret)) { - printk(KERN_ERR - "failed to register mailbox interrupt:%d\n", ret); - goto fail_request_irq; - } + if (atomic_inc_return(&mbox->use_count) == 1) { + ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, + mbox->name, mbox); + if (unlikely(ret)) { + printk(KERN_ERR "failed to register mailbox interrupt:" + "%d\n", ret); + goto fail_request_irq; + } - mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); - if (!mq) { - ret = -ENOMEM; - goto fail_alloc_txq; - } - mbox->txq = mq; + mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); + if (!mq) { + ret = -ENOMEM; + goto fail_alloc_txq; + } + mbox->txq = mq; - mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); - if (!mq) { - ret = -ENOMEM; - goto fail_alloc_rxq; + mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); + if (!mq) { + ret = -ENOMEM; + goto fail_alloc_rxq; + } + mbox->rxq = mq; + mq->mbox = mbox; } - mbox->rxq = mq; - return 0; fail_alloc_rxq: @@ -281,6 +283,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox) fail_alloc_txq: free_irq(mbox->irq, mbox); fail_request_irq: + atomic_dec(&mbox->use_count); if (likely(mbox->ops->shutdown)) { if (atomic_dec_return(&mbox_refcount) == 0) mbox->ops->shutdown(mbox); @@ -291,10 +294,12 @@ static int omap_mbox_startup(struct omap_mbox *mbox) static void omap_mbox_fini(struct omap_mbox *mbox) { - mbox_queue_free(mbox->txq); - mbox_queue_free(mbox->rxq); - free_irq(mbox->irq, mbox); + if (atomic_dec_return(&mbox->use_count) == 0) { + mbox_queue_free(mbox->txq); + mbox_queue_free(mbox->rxq); + free_irq(mbox->irq, mbox); + } if (likely(mbox->ops->shutdown)) { if (atomic_dec_return(&mbox_refcount) == 0) @@ -314,7 +319,7 @@ static struct omap_mbox **find_mboxes(const char *name) return p; } -struct omap_mbox *omap_mbox_get(const char *name) +struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb) { struct omap_mbox *mbox; int ret; @@ -325,19 +330,21 @@ struct omap_mbox *omap_mbox_get(const char *name) spin_unlock(&mboxes_lock); return ERR_PTR(-ENOENT); } - spin_unlock(&mboxes_lock); ret = omap_mbox_startup(mbox); if (ret) return ERR_PTR(-ENODEV); + if (nb) + blocking_notifier_chain_register(&mbox->notifier, nb); return mbox; } EXPORT_SYMBOL(omap_mbox_get); -void omap_mbox_put(struct omap_mbox *mbox) +void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb) { + blocking_notifier_chain_unregister(&mbox->notifier, nb); omap_mbox_fini(mbox); } EXPORT_SYMBOL(omap_mbox_put); @@ -361,6 +368,8 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) } *tmp = mbox; spin_unlock(&mboxes_lock); + BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier); + atomic_set(&mbox->use_count, 0); return 0; From patchwork Tue Jul 20 21:41:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kanigeri, Hari" X-Patchwork-Id: 113089 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6KLV427032176 for ; Tue, 20 Jul 2010 21:31:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752122Ab0GTVbB (ORCPT ); Tue, 20 Jul 2010 17:31:01 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:60280 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752234Ab0GTVa6 (ORCPT ); Tue, 20 Jul 2010 17:30:58 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6KLUs9p005849 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 20 Jul 2010 16:30:55 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6KLUsb6015500; Tue, 20 Jul 2010 16:30:54 -0500 (CDT) Received: from localhost (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBAG6ZP24215; Fri, 10 Dec 1915 11:06:35 -0500 (CDT) From: Hari Kanigeri To: Linux Omap , Tony Lindgren , Hiroshi DOYU Cc: Ohad Ben-Cohen , Hari Kanigeri Subject: [PATCH 1/2] omap:mailbox-make mailbox reference counter atomic Date: Tue, 20 Jul 2010 16:41:35 -0500 Message-Id: <1279662096-3121-2-git-send-email-h-kanigeri2@ti.com> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1279662096-3121-1-git-send-email-h-kanigeri2@ti.com> References: <1279662096-3121-1-git-send-email-h-kanigeri2@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 20 Jul 2010 21:31:05 +0000 (UTC) diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index b06d3de..baac315 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -35,7 +35,7 @@ static struct omap_mbox *mboxes; static DEFINE_SPINLOCK(mboxes_lock); static bool rq_full; -static int mbox_configured; +static atomic_t mbox_refcount = ATOMIC_INIT(0); /* Mailbox FIFO handle functions */ static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) @@ -243,16 +243,13 @@ static int omap_mbox_startup(struct omap_mbox *mbox) struct omap_mbox_queue *mq; if (likely(mbox->ops->startup)) { - spin_lock(&mboxes_lock); - if (!mbox_configured) + if (atomic_inc_return(&mbox_refcount) == 1) ret = mbox->ops->startup(mbox); if (unlikely(ret)) { - spin_unlock(&mboxes_lock); + atomic_dec(&mbox_refcount); return ret; } - mbox_configured++; - spin_unlock(&mboxes_lock); } ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, @@ -284,8 +281,10 @@ static int omap_mbox_startup(struct omap_mbox *mbox) fail_alloc_txq: free_irq(mbox->irq, mbox); fail_request_irq: - if (likely(mbox->ops->shutdown)) - mbox->ops->shutdown(mbox); + if (likely(mbox->ops->shutdown)) { + if (atomic_dec_return(&mbox_refcount) == 0) + mbox->ops->shutdown(mbox); + } return ret; } @@ -298,12 +297,8 @@ static void omap_mbox_fini(struct omap_mbox *mbox) free_irq(mbox->irq, mbox); if (likely(mbox->ops->shutdown)) { - spin_lock(&mboxes_lock); - if (mbox_configured > 0) - mbox_configured--; - if (!mbox_configured) + if (atomic_dec_return(&mbox_refcount) == 0) mbox->ops->shutdown(mbox); - spin_unlock(&mboxes_lock); } } From patchwork Wed Mar 24 15:03:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjeev Premi X-Patchwork-Id: 87929 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2OF4Al3005877 for ; Wed, 24 Mar 2010 15:04:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755634Ab0CXPEJ (ORCPT ); Wed, 24 Mar 2010 11:04:09 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:40391 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755429Ab0CXPEI (ORCPT ); Wed, 24 Mar 2010 11:04:08 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2OF433W024735 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 24 Mar 2010 10:04:06 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2OF42LW013485; Wed, 24 Mar 2010 20:34:03 +0530 (IST) From: Sanjeev Premi To: linux-omap@vger.kernel.org Cc: Sanjeev Premi Subject: [PATCH] omap: Macros for comapring si revisions Date: Wed, 24 Mar 2010 20:33:47 +0530 Message-Id: <1269443027-14973-1-git-send-email-premi@ti.com> X-Mailer: git-send-email 1.6.6.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 24 Mar 2010 15:04:11 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 7514174..00507d1 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -72,6 +72,11 @@ unsigned int omap_rev(void); #define OMAP_REVBITS_40 0x40 /* + * Get the CPU Id for OMAP devices + */ +#define GET_OMAP_ID() ((omap_rev() >> 16) & 0xffff) + +/* * Get the CPU revision for OMAP devices */ #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) @@ -458,4 +463,149 @@ OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) + +/* + * Mapping revision to silicon classes + */ +#define OMAP34XX_ES_1_0 OMAP_REVBITS_00 +#define OMAP34XX_ES_2_0 OMAP_REVBITS_10 +#define OMAP34XX_ES_2_1 OMAP_REVBITS_20 +#define OMAP34XX_ES_3_0 OMAP_REVBITS_30 +#define OMAP34XX_ES_3_1 OMAP_REVBITS_40 + +/* + * Mapping revision to individual silicons + */ +#define OMAP3430_ES_1_0 OMAP_REVBITS_00 +#define OMAP3430_ES_2_0 OMAP_REVBITS_10 +#define OMAP3430_ES_2_1 OMAP_REVBITS_20 +#define OMAP3430_ES_3_0 OMAP_REVBITS_30 +#define OMAP3430_ES_3_1 OMAP_REVBITS_40 + + +/* + * Inline functions to compare revision for specific silicons + */ +static inline bool is_omap_rev_lt (u16 id, u16 rev) +{ + if (((GET_OMAP_ID()) == id) && + ((GET_OMAP_REVISION()) < rev)) + return true; + else + return false; +} + +static inline bool is_omap_rev_le (u16 id, u16 rev) +{ + if (((GET_OMAP_ID()) == id) && + ((GET_OMAP_REVISION()) <= rev)) + return true; + else + return false; +} + +static inline bool is_omap_rev_eq (u16 id, u16 rev) +{ + if (((GET_OMAP_ID()) == id) && + ((GET_OMAP_REVISION()) == rev)) + return true; + else + return false; +} + +static inline bool is_omap_rev_ne (u16 id, u16 rev) +{ + if (((GET_OMAP_ID()) == id) && + ((GET_OMAP_REVISION()) != rev)) + return true; + else + return false; +} + +static inline bool is_omap_rev_gt (u16 id, u16 rev) +{ + if (((GET_OMAP_ID()) == id) && + ((GET_OMAP_REVISION()) > rev)) + return true; + else + return false; +} + +static inline bool is_omap_rev_ge (u16 id, u16 rev) +{ + if (((GET_OMAP_ID()) == id) && + ((GET_OMAP_REVISION()) >= rev)) + return true; + else + return false; +} + +#define cpu_rev_lt(id, rev) is_omap_rev_lt(0x##id, OMAP##id##_##rev) +#define cpu_rev_le(id, rev) is_omap_rev_le(0x##id, OMAP##id##_##rev) +#define cpu_rev_eq(id, rev) is_omap_rev_eq(0x##id, OMAP##id##_##rev) +#define cpu_rev_ne(id, rev) is_omap_rev_ne(0x##id, OMAP##id##_##rev) +#define cpu_rev_gt(id, rev) is_omap_rev_gt(0x##id, OMAP##id##_##rev) +#define cpu_rev_ge(id, rev) is_omap_rev_ge(0x##id, OMAP##id##_##rev) + + +/* + * Inline functions to compare revision for class of silicons + */ +static inline bool is_class_rev_lt (u16 c, u16 rev) +{ + if (((GET_OMAP_CLASS) == c) && ((GET_OMAP_REVISION()) < rev)) + return true; + else + return false; + + return true; +} + +static inline bool is_class_rev_le (u16 c, u16 rev) +{ + if (((GET_OMAP_CLASS) == c) && ((GET_OMAP_REVISION()) <= rev)) + return true; + else + return false; + + return true; +} + +static inline bool is_class_rev_eq (u16 c, u16 rev) +{ + if (((GET_OMAP_CLASS) == c) && ((GET_OMAP_REVISION()) == rev)) + return true; + else + return false; + + return true; +} + +static inline bool is_class_rev_gt (u16 c, u16 rev) +{ + if (((GET_OMAP_CLASS) == c) && ((GET_OMAP_REVISION()) > rev)) + return true; + else + return false; + + return true; +} + +static inline bool is_class_rev_ge (u16 c, u16 rev) +{ + if (((GET_OMAP_CLASS) == c) && ((GET_OMAP_REVISION()) >= rev)) + return true; + else + return false; + + return true; +} + +#define class_rev_lt(c, rev) is_class_rev_lt(0x##c, OMAP##c##XX_##rev) +#define class_rev_le(c, rev) is_class_rev_le(0x##c, OMAP##c##XX_##rev) +#define class_rev_eq(c, rev) is_class_rev_eq(0x##c, OMAP##c##XX_##rev) +#define class_rev_ne(c, rev) is_class_rev_ne(0x##c, OMAP##c##XX_##rev) +#define class_rev_gt(c, rev) is_class_rev_gt(0x##c, OMAP##c##XX_##rev) +#define class_rev_ge(c, rev) is_class_rev_ge(0x##c, OMAP##c##XX_##rev) + #endif From patchwork Thu Jul 8 08:32:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 110796 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o688XLCT026213 for ; Thu, 8 Jul 2010 08:33:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754601Ab0GHIdU (ORCPT ); Thu, 8 Jul 2010 04:33:20 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40744 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754111Ab0GHIdT (ORCPT ); Thu, 8 Jul 2010 04:33:19 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o688X87M013573 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 03:33:10 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o688X38H010636; Thu, 8 Jul 2010 14:03:04 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o688X3n6030088; Thu, 8 Jul 2010 14:03:03 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o688X392030085; Thu, 8 Jul 2010 14:03:03 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, felipe.balbi@nokia.com, gregkh@suse.de, Anand Gadiyar , Ajay Kumar Gupta Subject: [PATCH 1/4] usb: musb: use correct register widths in register dumps Date: Thu, 8 Jul 2010 14:02:59 +0530 Message-Id: <1278577982-30046-2-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1278577982-30046-1-git-send-email-ajay.gupta@ti.com> References: <1278577982-30046-1-git-send-email-ajay.gupta@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 08:33:29 +0000 (UTC) diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c index bba76af..c79a5e3 100644 --- a/drivers/usb/musb/musb_debugfs.c +++ b/drivers/usb/musb/musb_debugfs.c @@ -92,29 +92,29 @@ static const struct musb_register_map musb_regmap[] = { { "LS_EOF1", 0x7E, 8 }, { "SOFT_RST", 0x7F, 8 }, { "DMA_CNTLch0", 0x204, 16 }, - { "DMA_ADDRch0", 0x208, 16 }, - { "DMA_COUNTch0", 0x20C, 16 }, + { "DMA_ADDRch0", 0x208, 32 }, + { "DMA_COUNTch0", 0x20C, 32 }, { "DMA_CNTLch1", 0x214, 16 }, - { "DMA_ADDRch1", 0x218, 16 }, - { "DMA_COUNTch1", 0x21C, 16 }, + { "DMA_ADDRch1", 0x218, 32 }, + { "DMA_COUNTch1", 0x21C, 32 }, { "DMA_CNTLch2", 0x224, 16 }, - { "DMA_ADDRch2", 0x228, 16 }, - { "DMA_COUNTch2", 0x22C, 16 }, + { "DMA_ADDRch2", 0x228, 32 }, + { "DMA_COUNTch2", 0x22C, 32 }, { "DMA_CNTLch3", 0x234, 16 }, - { "DMA_ADDRch3", 0x238, 16 }, - { "DMA_COUNTch3", 0x23C, 16 }, + { "DMA_ADDRch3", 0x238, 32 }, + { "DMA_COUNTch3", 0x23C, 32 }, { "DMA_CNTLch4", 0x244, 16 }, - { "DMA_ADDRch4", 0x248, 16 }, - { "DMA_COUNTch4", 0x24C, 16 }, + { "DMA_ADDRch4", 0x248, 32 }, + { "DMA_COUNTch4", 0x24C, 32 }, { "DMA_CNTLch5", 0x254, 16 }, - { "DMA_ADDRch5", 0x258, 16 }, - { "DMA_COUNTch5", 0x25C, 16 }, + { "DMA_ADDRch5", 0x258, 32 }, + { "DMA_COUNTch5", 0x25C, 32 }, { "DMA_CNTLch6", 0x264, 16 }, - { "DMA_ADDRch6", 0x268, 16 }, - { "DMA_COUNTch6", 0x26C, 16 }, + { "DMA_ADDRch6", 0x268, 32 }, + { "DMA_COUNTch6", 0x26C, 32 }, { "DMA_CNTLch7", 0x274, 16 }, - { "DMA_ADDRch7", 0x278, 16 }, - { "DMA_COUNTch7", 0x27C, 16 }, + { "DMA_ADDRch7", 0x278, 32 }, + { "DMA_COUNTch7", 0x27C, 32 }, { } /* Terminating Entry */ }; From patchwork Wed Mar 17 12:35:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 86320 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2HCb815016706 for ; Wed, 17 Mar 2010 12:37:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754817Ab0CQMhG (ORCPT ); Wed, 17 Mar 2010 08:37:06 -0400 Received: from smtp.nokia.com ([192.100.105.134]:17515 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754716Ab0CQMhD (ORCPT ); Wed, 17 Mar 2010 08:37:03 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2HCb1BW024381; Wed, 17 Mar 2010 07:37:02 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 17 Mar 2010 14:35:28 +0200 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 17 Mar 2010 14:35:27 +0200 Received: from localhost.localdomain (ucofw-nat2.nokia.com [131.228.1.90]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2HCZMLq012147; Wed, 17 Mar 2010 14:35:26 +0200 From: Roger Quadros To: Tomi.Valkeinen@nokia.com Cc: linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCHv2 3/3] OMAP: DSS2: Use vdds_sdi regulator supply in SDI Date: Wed, 17 Mar 2010 14:35:21 +0200 Message-Id: <1268829321-29769-4-git-send-email-roger.quadros@nokia.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1268829321-29769-3-git-send-email-roger.quadros@nokia.com> References: <1268829321-29769-1-git-send-email-roger.quadros@nokia.com> <1268829321-29769-2-git-send-email-roger.quadros@nokia.com> <1268829321-29769-3-git-send-email-roger.quadros@nokia.com> X-OriginalArrivalTime: 17 Mar 2010 12:35:27.0903 (UTC) FILETIME=[52F25AF0:01CAC5CE] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Mar 2010 12:37:14 +0000 (UTC) diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c index 3de3c1e..ee07a3c 100644 --- a/drivers/video/omap2/dss/sdi.c +++ b/drivers/video/omap2/dss/sdi.c @@ -23,13 +23,16 @@ #include #include #include +#include #include +#include #include "dss.h" static struct { bool skip_init; bool update_enabled; + struct regulator *vdds_sdi_reg; } sdi; static void sdi_basic_init(void) @@ -57,6 +60,10 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) goto err0; } + r = regulator_enable(sdi.vdds_sdi_reg); + if (r) + goto err1; + /* In case of skip_init sdi_init has already enabled the clocks */ if (!sdi.skip_init) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); @@ -120,6 +127,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) return 0; err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + regulator_disable(sdi.vdds_sdi_reg); err1: omap_dss_stop_device(dssdev); err0: @@ -135,6 +143,8 @@ void omapdss_sdi_display_disable(struct omap_dss_device *dssdev) dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + regulator_disable(sdi.vdds_sdi_reg); + omap_dss_stop_device(dssdev); } EXPORT_SYMBOL(omapdss_sdi_display_disable); @@ -151,6 +161,11 @@ int sdi_init(bool skip_init) /* we store this for first display enable, then clear it */ sdi.skip_init = skip_init; + sdi.vdds_sdi_reg = dss_get_vdds_sdi(); + if (IS_ERR(sdi.vdds_sdi_reg)) { + DSSERR("can't get VDDS_SDI regulator\n"); + return PTR_ERR(sdi.vdds_sdi_reg); + } /* * Enable clocks already here, otherwise there would be a toggle * of them until sdi_display_enable is called. From patchwork Sat Jul 31 17:44:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 116227 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6VHjPUB009529 for ; Sat, 31 Jul 2010 17:45:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752460Ab0GaRpZ (ORCPT ); Sat, 31 Jul 2010 13:45:25 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:45609 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751072Ab0GaRpY (ORCPT ); Sat, 31 Jul 2010 13:45:24 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6VHidkC003255 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 31 Jul 2010 12:44:41 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6VHicfG027979; Sat, 31 Jul 2010 23:14:38 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o6VHibKo004553; Sat, 31 Jul 2010 23:14:37 +0530 Received: (from a0393909@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o6VHibh1004551; Sat, 31 Jul 2010 23:14:37 +0530 From: Santosh Shilimkar To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org, Santosh Shilimkar , Catalin Marinas Subject: [PATCH 1/4] ARM: l2x0: Fix coding-style in the cache-l2x0.h Date: Sat, 31 Jul 2010 23:14:37 +0530 Message-Id: <1280598277-4521-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 31 Jul 2010 17:45:26 +0000 (UTC) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 6bcba48..d833355 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -21,9 +21,6 @@ #define __ASM_ARM_HARDWARE_L2X0_H #define L2X0_CACHE_ID 0x000 -#define L2X0_CACHE_ID_PART_MASK (0xf << 6) -#define L2X0_CACHE_ID_PART_L210 (1 << 6) -#define L2X0_CACHE_ID_PART_L310 (3 << 6) #define L2X0_CACHE_TYPE 0x004 #define L2X0_CTRL 0x100 #define L2X0_AUX_CTRL 0x104 @@ -54,6 +51,11 @@ #define L2X0_LINE_TAG 0xF30 #define L2X0_DEBUG_CTRL 0xF40 +/* Registers shifts and masks */ +#define L2X0_CACHE_ID_PART_MASK (0xf << 6) +#define L2X0_CACHE_ID_PART_L210 (1 << 6) +#define L2X0_CACHE_ID_PART_L310 (3 << 6) + #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); #endif From patchwork Wed Apr 21 23:57:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 93980 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3LNwQES014178 for ; Wed, 21 Apr 2010 23:58:27 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754596Ab0DUX6W (ORCPT ); Wed, 21 Apr 2010 19:58:22 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:49588 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752607Ab0DUX6V (ORCPT ); Wed, 21 Apr 2010 19:58:21 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3LNvnNv029004 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 21 Apr 2010 18:57:49 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3LNvmBr024417; Wed, 21 Apr 2010 18:57:48 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3LNvmYc006326; Wed, 21 Apr 2010 18:57:48 -0500 (CDT) Received: from [128.247.75.1] (128.247.75.1) by dlee73.ent.ti.com (157.170.170.88) with Microsoft SMTP Server id 8.1.358.0; Wed, 21 Apr 2010 18:57:48 -0500 Message-ID: <4BCF90FB.4080108@ti.com> Date: Wed, 21 Apr 2010 18:57:47 -0500 From: Nishanth Menon User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: "Kanigeri, Hari" CC: =?ISO-8859-1?Q?=22V=EDctor_M=2E_J=E1quez_L=2E=22?= , "Gomez Castellanos, Ivan" , "linux-omap@vger.kernel.org" , Hiroshi DOYU , Felipe Contreras , Ameya Palande Subject: Re: [PATCH 03/13] DSPBRIDGE: Moving functions from mem.c to drv.c References: <818EF96F5A7CC84789DD014773DB09548F6481CF@dlee01.ent.ti.com> <20100416103658.GA18995@lit.local.igalia.com> <8F7AF80515AF0D4D93307E594F3CB40E4B21669A@dlee03.ent.ti.com> In-Reply-To: <8F7AF80515AF0D4D93307E594F3CB40E4B21669A@dlee03.ent.ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Apr 2010 23:58:27 +0000 (UTC) From ea35037b8bf9af0ef068248f74ce6c9dcde4df6c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 21 Apr 2010 14:49:28 -0500 Subject: [PATCH] DSPBRIDGE: mem: no more cache handling quick hack to use map and unmap to handle invalid and clean ops Signed-off-by: Nishanth Menon --- drivers/dsp/bridge/services/mem.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dsp/bridge/services/mem.c b/drivers/dsp/bridge/services/mem.c index 916a49f..49033e7 100644 --- a/drivers/dsp/bridge/services/mem.c +++ b/drivers/dsp/bridge/services/mem.c @@ -224,13 +224,13 @@ void mem_flush_cache(void *pMemBuf, u32 byte_size, s32 FlushType) switch (FlushType) { /* invalidate only */ case PROC_INVALIDATE_MEM: - dmac_inv_range(pMemBuf, pMemBuf + byte_size); + dmac_unmap_area(pMemBuf, byte_size, DMA_TO_DEVICE); outer_inv_range(__pa((u32) pMemBuf), __pa((u32) pMemBuf + byte_size)); break; /* writeback only */ case PROC_WRITEBACK_MEM: - dmac_clean_range(pMemBuf, pMemBuf + byte_size); + dmac_map_area(pMemBuf, byte_size, DMA_FROM_DEVICE); outer_clean_range(__pa((u32) pMemBuf), __pa((u32) pMemBuf + byte_size)); break; -- 1.6.3.3 From patchwork Sun Jul 4 13:36:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110145 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64Dadsl004743 for ; Sun, 4 Jul 2010 13:36:39 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757863Ab0GDNgj (ORCPT ); Sun, 4 Jul 2010 09:36:39 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:65451 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757856Ab0GDNgi (ORCPT ); Sun, 4 Jul 2010 09:36:38 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so2295721bwz.19 for ; Sun, 04 Jul 2010 06:36:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Sun, 04 Jul 2010 13:36:40 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index ee33abb..8909c41 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -114,7 +114,7 @@ struct io_mgr { struct mgr_processorextinfo ext_proc_info; struct cmm_object *hcmm_mgr; /* Shared Mem Mngr */ struct work_struct io_workq; /* workqueue */ -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG u32 ul_trace_buffer_begin; /* Trace message start address */ u32 ul_trace_buffer_end; /* Trace message end address */ u32 ul_trace_buffer_current; /* Trace message current address */ @@ -210,7 +210,7 @@ int bridge_io_create(OUT struct io_mgr **phIOMgr, } /* Initialize chnl_mgr object */ -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG pio_mgr->pmsg = NULL; #endif pio_mgr->hchnl_mgr = hchnl_mgr; @@ -265,7 +265,7 @@ int bridge_io_destroy(struct io_mgr *hio_mgr) /* Free IO DPC object */ tasklet_kill(&hio_mgr->dpc_tasklet); -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG kfree(hio_mgr->pmsg); #endif dsp_wdt_exit(); @@ -407,7 +407,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) status = -EFAULT; } if (DSP_SUCCEEDED(status)) { -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG status = cod_get_sym_value(cod_man, DSP_TRACESEC_END, &shm0_end); #else @@ -752,7 +752,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) hmsg_mgr->max_msgs); memset((void *)hio_mgr->shared_mem, 0, sizeof(struct shm)); -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG /* Get the start address of trace buffer */ status = cod_get_sym_value(cod_man, SYS_PUTCBEG, &hio_mgr->ul_trace_buffer_begin); @@ -949,7 +949,7 @@ void io_dpc(IN OUT unsigned long pRefData) (pio_mgr->intr_val < DEH_LIMIT)) { /* Notify DSP/BIOS exception */ if (hdeh_mgr) { -#ifndef DSP_TRACE_BUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG print_dsp_debug_trace(pio_mgr); #endif bridge_deh_notify(hdeh_mgr, DSP_SYSERROR, @@ -961,7 +961,7 @@ void io_dpc(IN OUT unsigned long pRefData) if (msg_mgr_obj) io_dispatch_msg(pio_mgr, msg_mgr_obj); #endif -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG if (pio_mgr->intr_val & MBX_DBG_SYSPRINTF) { /* Notify DSP Trace message */ print_dsp_debug_trace(pio_mgr); @@ -1810,7 +1810,7 @@ int bridge_io_get_proc_load(IN struct io_mgr *hio_mgr, return 0; } -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG void print_dsp_debug_trace(struct io_mgr *hio_mgr) { u32 ul_new_message_length = 0, ul_gpp_cur_pointer; diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index c3557ef..6e67f10 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -302,7 +302,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context); void dump_dl_modules(struct bridge_dev_context *bridge_context); -#ifndef DSP_TRACEBUF_DISABLED +#ifdef CONFIG_TIDSPBRIDGE_DEBUG void print_dsp_debug_trace(struct io_mgr *hio_mgr); #endif From patchwork Tue May 11 07:27:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 98626 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B7RON0020445 for ; Tue, 11 May 2010 07:27:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932335Ab0EKH1X (ORCPT ); Tue, 11 May 2010 03:27:23 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:33035 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932173Ab0EKH1S (ORCPT ); Tue, 11 May 2010 03:27:18 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B7RDhP000555 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 11 May 2010 02:27:15 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B7RCkg006421; Tue, 11 May 2010 12:57:12 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4B7RC7q009870; Tue, 11 May 2010 12:57:12 +0530 Received: (from x0016154@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4B7RBcX009868; Tue, 11 May 2010 12:57:12 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak Subject: [PATCH 4/5] OMAP4 clockdomain: Fix omap2_clkdm_clk_enable/disable api for 44xx Date: Tue, 11 May 2010 12:57:09 +0530 Message-Id: <1273562830-9758-5-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1273562830-9758-4-git-send-email-rnayak@ti.com> References: <1273562830-9758-1-git-send-email-rnayak@ti.com> <1273562830-9758-2-git-send-email-rnayak@ti.com> <1273562830-9758-3-git-send-email-rnayak@ti.com> <1273562830-9758-4-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 07:27:25 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 6e568ec..13dcd6f 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -994,6 +994,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) v = omap2_clkdm_clktrctrl_read(clkdm); + if (cpu_is_omap44xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) + return 0; + if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) { /* Disable HW transitions when we are changing deps */ @@ -1056,6 +1059,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) v = omap2_clkdm_clktrctrl_read(clkdm); + if (cpu_is_omap44xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) + return 0; + if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) { /* Disable HW transitions when we are changing deps */ From patchwork Tue May 11 07:27:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 98625 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B7ROMx020445 for ; Tue, 11 May 2010 07:27:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757215Ab0EKH1W (ORCPT ); Tue, 11 May 2010 03:27:22 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40868 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757300Ab0EKH1Q (ORCPT ); Tue, 11 May 2010 03:27:16 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B7RDLd019744 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 11 May 2010 02:27:15 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B7RCSH006427; Tue, 11 May 2010 12:57:12 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4B7RC0X009875; Tue, 11 May 2010 12:57:12 +0530 Received: (from x0016154@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4B7RCK3009873; Tue, 11 May 2010 12:57:12 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak Subject: [PATCH 5/5] OMAP4 powerdomain: Support LOWPOWERSTATECHANGE for powerdomains Date: Tue, 11 May 2010 12:57:10 +0530 Message-Id: <1273562830-9758-6-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1273562830-9758-5-git-send-email-rnayak@ti.com> References: <1273562830-9758-1-git-send-email-rnayak@ti.com> <1273562830-9758-2-git-send-email-rnayak@ti.com> <1273562830-9758-3-git-send-email-rnayak@ti.com> <1273562830-9758-4-git-send-email-rnayak@ti.com> <1273562830-9758-5-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 07:27:25 +0000 (UTC) diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index ebfce7d..7e000bc 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -978,6 +978,34 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) } /** + * pwrdm_set_lowpwrstchange - Request a low power state change + * @pwrdm: struct powerdomain * + * + * Allows a powerdomain to transtion to a lower power sleep state + * from an existing sleep state without waking up the powerdomain. + * Returns -EINVAL if the powerdomain pointer is null or if the + * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0 + * upon success. + */ +int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) +{ + if (!pwrdm) + return -EINVAL; + + if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) + return -EINVAL; + + pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n", + pwrdm->name); + + prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, + (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), + pwrdm->prcm_offs, pwrstctrl_reg_offs); + + return 0; +} + +/** * pwrdm_wait_transition - wait for powerdomain power transition to finish * @pwrdm: struct powerdomain * to wait for * diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h index ad2fbd7..0e88f8c 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ b/arch/arm/mach-omap2/powerdomains44xx.h @@ -54,6 +54,7 @@ static struct powerdomain core_44xx_pwrdm = { [3] = PWRDM_POWER_ON, /* ducati_l2ram */ [4] = PWRDM_POWER_ON, /* ducati_unicache */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* gfx_44xx_pwrdm: 3D accelerator power domain */ @@ -69,6 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* gfx_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* abe_44xx_pwrdm: Audio back end power domain */ @@ -87,6 +89,7 @@ static struct powerdomain abe_44xx_pwrdm = { [0] = PWRDM_POWER_ON, /* aessmem */ [1] = PWRDM_POWER_ON, /* periphmem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* dss_44xx_pwrdm: Display subsystem power domain */ @@ -103,6 +106,7 @@ static struct powerdomain dss_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* dss_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* tesla_44xx_pwrdm: Tesla processor power domain */ @@ -123,6 +127,7 @@ static struct powerdomain tesla_44xx_pwrdm = { [1] = PWRDM_POWER_ON, /* tesla_l1 */ [2] = PWRDM_POWER_ON, /* tesla_l2 */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* wkup_44xx_pwrdm: Wake-up power domain */ @@ -227,6 +232,7 @@ static struct powerdomain ivahd_44xx_pwrdm = { [2] = PWRDM_POWER_ON, /* tcm1_mem */ [3] = PWRDM_POWER_ON, /* tcm2_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* cam_44xx_pwrdm: Camera subsystem power domain */ @@ -242,6 +248,7 @@ static struct powerdomain cam_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* cam_mem */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ @@ -258,6 +265,7 @@ static struct powerdomain l3init_44xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRDM_POWER_ON, /* l3init_bank1 */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* l4per_44xx_pwrdm: Target peripherals power domain */ @@ -276,6 +284,7 @@ static struct powerdomain l4per_44xx_pwrdm = { [0] = PWRDM_POWER_ON, /* nonretained_bank */ [1] = PWRDM_POWER_ON, /* retained_bank */ }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; /* diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index e7cc7e6..fb6ec74 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -50,6 +50,12 @@ * in MEM bank 1 position. This is * true for OMAP3430 */ +#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* + * support to transition from a + * sleep state to a lower sleep + * state without waking up the + * powerdomain + */ /* * Number of memory banks that are power-controllable. On OMAP4430, the From patchwork Tue May 11 07:27:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 98624 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B7ROMw020445 for ; Tue, 11 May 2010 07:27:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932326Ab0EKH1U (ORCPT ); Tue, 11 May 2010 03:27:20 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40867 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757266Ab0EKH1Q (ORCPT ); Tue, 11 May 2010 03:27:16 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B7RDwt019743 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 11 May 2010 02:27:15 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B7RBCR006417; Tue, 11 May 2010 12:57:12 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4B7RBDK009860; Tue, 11 May 2010 12:57:11 +0530 Received: (from x0016154@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4B7RBAc009858; Tue, 11 May 2010 12:57:11 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak Subject: [PATCH 2/5] OMAP: timers: Fix clock source names for OMAP4 Date: Tue, 11 May 2010 12:57:07 +0530 Message-Id: <1273562830-9758-3-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1273562830-9758-2-git-send-email-rnayak@ti.com> References: <1273562830-9758-1-git-send-email-rnayak@ti.com> <1273562830-9758-2-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 07:27:24 +0000 (UTC) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 4d99dfb..c64875f 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -264,8 +264,8 @@ static struct omap_dm_timer omap4_dm_timers[] = { { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, }; static const char *omap4_dm_source_names[] __initdata = { - "sys_ck", - "omap_32k_fck", + "sys_clkin_ck", + "sys_32k_ck", NULL }; static struct clk *omap4_dm_source_clocks[2]; From patchwork Tue May 11 07:27:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 98623 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B7ROMv020445 for ; Tue, 11 May 2010 07:27:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932281Ab0EKH1T (ORCPT ); Tue, 11 May 2010 03:27:19 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59551 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757215Ab0EKH1Q (ORCPT ); Tue, 11 May 2010 03:27:16 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B7RDpL006839 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 11 May 2010 02:27:15 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B7RBvA006416; Tue, 11 May 2010 12:57:12 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4B7RBTL009855; Tue, 11 May 2010 12:57:11 +0530 Received: (from x0016154@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4B7RBSh009853; Tue, 11 May 2010 12:57:11 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak Subject: [PATCH 1/5] OMAP4 clock: Support clk_set_parent Date: Tue, 11 May 2010 12:57:06 +0530 Message-Id: <1273562830-9758-2-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1273562830-9758-1-git-send-email-rnayak@ti.com> References: <1273562830-9758-1-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 07:27:24 +0000 (UTC) diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 5261a09..701e4ea 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -140,9 +140,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent) unsigned long flags; int ret = -EINVAL; - if (cpu_is_omap44xx()) - /* OMAP4 clk framework not supported yet */ - return 0; if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) return ret; From patchwork Tue May 11 07:27:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 98622 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B7ROMu020445 for ; Tue, 11 May 2010 07:27:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932180Ab0EKH1S (ORCPT ); Tue, 11 May 2010 03:27:18 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59549 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754095Ab0EKH1Q (ORCPT ); Tue, 11 May 2010 03:27:16 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B7RDHj006837 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 11 May 2010 02:27:15 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B7RBvt006420; Tue, 11 May 2010 12:57:12 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4B7RBG4009865; Tue, 11 May 2010 12:57:11 +0530 Received: (from x0016154@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4B7RB6O009863; Tue, 11 May 2010 12:57:11 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak Subject: [PATCH 3/5] OMAP4 powerdomain: Fix pwrsts flags for ALWAYS ON domains Date: Tue, 11 May 2010 12:57:08 +0530 Message-Id: <1273562830-9758-4-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1273562830-9758-3-git-send-email-rnayak@ti.com> References: <1273562830-9758-1-git-send-email-rnayak@ti.com> <1273562830-9758-2-git-send-email-rnayak@ti.com> <1273562830-9758-3-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 07:27:24 +0000 (UTC) diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h index c101514..ad2fbd7 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ b/arch/arm/mach-omap2/powerdomains44xx.h @@ -130,7 +130,7 @@ static struct powerdomain wkup_44xx_pwrdm = { .name = "wkup_pwrdm", .prcm_offs = OMAP4430_PRM_WKUP_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRDM_POWER_ON, + .pwrsts = PWRSTS_ON, .banks = 1, .pwrsts_mem_ret = { [0] = PWRDM_POWER_OFF, /* wkup_bank */ @@ -286,7 +286,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = { .name = "always_on_core_pwrdm", .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRDM_POWER_ON, + .pwrsts = PWRSTS_ON, }; /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index d82b2c0..e7cc7e6 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -31,6 +31,7 @@ #define PWRDM_MAX_PWRSTS 4 /* Powerdomain allowable state bitfields */ +#define PWRSTS_ON (1 << PWRDM_POWER_ON) #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_ON)) From patchwork Sat Jul 31 17:46:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 116229 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6VHkH8k009678 for ; Sat, 31 Jul 2010 17:46:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753307Ab0GaRqQ (ORCPT ); Sat, 31 Jul 2010 13:46:16 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33226 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752917Ab0GaRqP (ORCPT ); Sat, 31 Jul 2010 13:46:15 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6VHk21G021563 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 31 Jul 2010 12:46:04 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6VHk1c3028058; Sat, 31 Jul 2010 23:16:01 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o6VHk14R004806; Sat, 31 Jul 2010 23:16:01 +0530 Received: (from a0393909@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o6VHk1qi004804; Sat, 31 Jul 2010 23:16:01 +0530 From: Santosh Shilimkar To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org, Santosh Shilimkar , Catalin Marinas Subject: [PATCH 3/4] ARM: l2x0: Determine the cache size Date: Sat, 31 Jul 2010 23:16:01 +0530 Message-Id: <1280598361-4773-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 31 Jul 2010 17:46:17 +0000 (UTC) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index d833355..4633d2a 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -55,6 +55,7 @@ #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L210 (1 << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) +#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 9e384fd..b2938d4 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -28,6 +28,7 @@ static void __iomem *l2x0_base; static DEFINE_SPINLOCK(l2x0_lock); static uint32_t l2x0_way_mask; /* Bitmask of active ways */ +static uint32_t l2x0_size; static inline void cache_wait(void __iomem *reg, unsigned long mask) { @@ -233,6 +234,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { __u32 aux; __u32 cache_id; + __u32 way_size = 0; int ways; const char *type; @@ -267,6 +269,13 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) l2x0_way_mask = (1 << ways) - 1; /* + * L2 cache Size = Way size * Number of ways + */ + way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; + way_size = 1 << (way_size + 3); + l2x0_size = ways * way_size; + + /* * Check if l2x0 controller is already enabled. * If you are booting from non-secure mode * accessing the below registers will fault. @@ -291,6 +300,6 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.disable = l2x0_disable; printk(KERN_INFO "%s cache controller enabled\n", type); - printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", - ways, cache_id, aux); + printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d KB\n", + ways, cache_id, aux, l2x0_size); } From patchwork Sat Jul 31 17:45:48 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 116228 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6VHjPUD009529 for ; Sat, 31 Jul 2010 17:45:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752568Ab0GaRp4 (ORCPT ); Sat, 31 Jul 2010 13:45:56 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:52940 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752540Ab0GaRpz (ORCPT ); Sat, 31 Jul 2010 13:45:55 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6VHjoCu004206 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 31 Jul 2010 12:45:52 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6VHjmoG028051; Sat, 31 Jul 2010 23:15:48 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o6VHjm4V004760; Sat, 31 Jul 2010 23:15:48 +0530 Received: (from a0393909@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o6VHjmwc004757; Sat, 31 Jul 2010 23:15:48 +0530 From: Santosh Shilimkar To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org, Santosh Shilimkar Subject: [PATCH 2/4] omap4: l2x0: Override the default l2x0_disable Date: Sat, 31 Jul 2010 23:15:48 +0530 Message-Id: <1280598348-4721-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 31 Jul 2010 17:45:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 13dc979..b557cc2 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -44,6 +44,13 @@ void __init gic_init_irq(void) } #ifdef CONFIG_CACHE_L2X0 + +static void omap4_l2x0_disable(void) +{ + /* Disable PL310 L2 Cache controller */ + omap_smc1(0x102, 0x0); +} + static int __init omap_l2_cache_init(void) { /* @@ -66,6 +73,12 @@ static int __init omap_l2_cache_init(void) */ l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + /* + * Override default outer_cache.disable with a OMAP4 + * specific one + */ + outer_cache.disable = omap4_l2x0_disable; + return 0; } early_initcall(omap_l2_cache_init); From patchwork Sun May 16 15:45:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99966 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkDSN025134 for ; Sun, 16 May 2010 15:46:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753129Ab0EPPqP (ORCPT ); Sun, 16 May 2010 11:46:15 -0400 Received: from fg-out-1718.google.com ([72.14.220.159]:5081 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753108Ab0EPPqO (ORCPT ); Sun, 16 May 2010 11:46:14 -0400 Received: by fg-out-1718.google.com with SMTP id d23so2359940fga.1 for ; Sun, 16 May 2010 08:46:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=guO6p7maAroRx91WYZSwMXNRZtyIgNRTUUS/RUuJXQM=; b=Cex3J4IKy1DvhTKQ+B9A2Ra7F/zxxzKbZecta4Jam/2TlmLtjIi+PycC0kuS/a4iks NUVR9/C/o1sxlG0gocQyQrp9l1l1JEoRgsfwXrIvUSteA+hVYnElI7uiRaTCKt6lRIGx /R3xbn+WxacWSy8tVC1qC24kgPfhTs8IA+dEo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=xJA2Y3+8SKhNnoBrl4UNGQ737Zd+mSeYcFlLbtGl1w+YChVBqMI5YWjhoJ5HErmMR7 95v8FBPVMKoiXZLqMf2ByuOELAxtSUW991UeB84vPNn4AQW4bD+S4PUSUJddNyzX0cnw 3qVmvIyNSfB/z2Ye5zzMr2jse91U3/4ee8fA4= Received: by 10.86.119.19 with SMTP id r19mr6726994fgc.76.1274024772942; Sun, 16 May 2010 08:46:12 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id 3sm3767211fge.10.2010.05.16.08.46.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:12 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 02/14] dspbridge: deh: trivial cleanups Date: Sun, 16 May 2010 18:45:53 +0300 Message-Id: <1274024765-21076-3-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:15 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 48c11e9..605cec7 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -60,11 +60,6 @@ /* Max time to check for GP Timer IRQ */ #define GPTIMER_IRQ_WAIT_MAX_CNT 1000 -static struct hw_mmu_map_attrs_t map_attrs = { HW_LITTLE_ENDIAN, - HW_ELEM_SIZE16BIT, - HW_MMU_CPUES -}; - static void *dummy_va_addr; static struct omap_dm_timer *timer; @@ -72,7 +67,7 @@ static struct omap_dm_timer *timer; dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, struct dev_object *hdev_obj) { - dsp_status status = DSP_SOK; + dsp_status status; struct deh_mgr *deh_mgr; struct bridge_dev_context *hbridge_context = NULL; @@ -81,23 +76,20 @@ dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, * the base image. */ /* Get WMD context info. */ dev_get_bridge_context(hdev_obj, &hbridge_context); - DBC_ASSERT(hbridge_context); - dummy_va_addr = NULL; /* Allocate IO manager object: */ deh_mgr = kzalloc(sizeof(struct deh_mgr), GFP_KERNEL); if (!deh_mgr) { status = -ENOMEM; - goto leave; + goto err; } /* Create an NTFY object to manage notifications */ deh_mgr->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL); - if (deh_mgr->ntfy_obj) { - ntfy_init(deh_mgr->ntfy_obj); - } else { + if (!deh_mgr->ntfy_obj) { status = -ENOMEM; goto err; } + ntfy_init(deh_mgr->ntfy_obj); /* Create a MMUfault DPC */ tasklet_init(&deh_mgr->dpc_tasklet, mmu_fault_dpc, (u32) deh_mgr); @@ -110,32 +102,25 @@ dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, deh_mgr->err_info.dw_val3 = 0L; /* Install ISR function for DSP MMU fault */ - if ((request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0, - "DspBridge\tiommu fault", - (void *)deh_mgr)) == 0) - status = DSP_SOK; - else - status = -EPERM; + status = request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0, + "DspBridge\tiommu fault", deh_mgr); + if (status < 0) + goto err; -err: - if (DSP_FAILED(status)) { - /* If create failed, cleanup */ - bridge_deh_destroy(deh_mgr); - deh_mgr = NULL; - } else { - timer = omap_dm_timer_request_specific( - GPTIMER_FOR_DSP_MMU_FAULT); - if (timer) { - omap_dm_timer_disable(timer); - } else { - pr_err("%s: GPTimer not available\n", __func__); - return -ENODEV; - } + timer = omap_dm_timer_request_specific(GPTIMER_FOR_DSP_MMU_FAULT); + if (!timer) { + pr_err("%s: GPTimer not available\n", __func__); + status = -ENODEV; + goto err; } + omap_dm_timer_disable(timer); -leave: *ret_deh_mgr = deh_mgr; + return 0; +err: + bridge_deh_destroy(deh_mgr); + *ret_deh_mgr = NULL; return status; } @@ -164,36 +149,31 @@ dsp_status bridge_deh_destroy(struct deh_mgr *deh_mgr) omap_dm_timer_free(timer); timer = NULL; - return DSP_SOK; + return 0; } dsp_status bridge_deh_register_notify(struct deh_mgr *deh_mgr, u32 event_mask, u32 notify_type, struct dsp_notification *hnotification) { - dsp_status status = DSP_SOK; - if (!deh_mgr) return -EFAULT; if (event_mask) - status = ntfy_register(deh_mgr->ntfy_obj, hnotification, - event_mask, notify_type); + return ntfy_register(deh_mgr->ntfy_obj, hnotification, + event_mask, notify_type); else - status = ntfy_unregister(deh_mgr->ntfy_obj, hnotification); - - return status; + return ntfy_unregister(deh_mgr->ntfy_obj, hnotification); } static void wait_for_timer(void) { - u32 cnt = 0; + int c; omap_dm_timer_enable(timer); /* Enable overflow interrupt */ - omap_dm_timer_set_int_enable(timer, - GPTIMER_IRQ_OVERFLOW); + omap_dm_timer_set_int_enable(timer, GPTIMER_IRQ_OVERFLOW); /* * Set counter value to overflow counter after * one tick and start timer. @@ -204,15 +184,11 @@ static void wait_for_timer(void) udelay(80); /* Check interrupt status and wait for interrupt */ - cnt = 0; - while (!(omap_dm_timer_read_status(timer) & - GPTIMER_IRQ_OVERFLOW)) { - if (cnt++ >= GPTIMER_IRQ_WAIT_MAX_CNT) { - pr_err("%s: GPTimer interrupt failed\n", - __func__); - break; - } - } + for (c = 0; c < GPTIMER_IRQ_WAIT_MAX_CNT; c++) + if ((omap_dm_timer_read_status(timer) & GPTIMER_IRQ_OVERFLOW)) + return; + + pr_err("%s: GPTimer interrupt failed\n", __func__); omap_dm_timer_disable(timer); } @@ -220,16 +196,19 @@ static void wait_for_timer(void) void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) { struct bridge_dev_context *dev_context; - dsp_status status = DSP_SOK; u32 hw_mmu_max_tlb_count = 31; struct cfg_hostres *resources; - hw_status hw_status_obj; + struct hw_mmu_map_attrs_t map_attrs = { + .endianism = HW_LITTLE_ENDIAN, + .element_size = HW_ELEM_SIZE16BIT, + .mixed_size = HW_MMU_CPUES, + }; if (!deh_mgr) return; dev_info(bridge, "%s: device exception\n", __func__); - dev_context = (struct bridge_dev_context *)deh_mgr->hbridge_context; + dev_context = deh_mgr->hbridge_context; resources = dev_context->resources; switch (ulEventMask) { @@ -256,8 +235,6 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) (unsigned int) deh_mgr->err_info.dw_val2, (unsigned int) fault_addr); dummy_va_addr = (void*)__get_free_page(GFP_ATOMIC); - dev_context = (struct bridge_dev_context *) - deh_mgr->hbridge_context; print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); @@ -272,20 +249,16 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) dev_context->num_tlb_entries = dev_context->fixed_tlb_entries; } - if (DSP_SUCCEEDED(status)) { - hw_status_obj = - hw_mmu_tlb_add(resources->dw_dmmu_base, - virt_to_phys(dummy_va_addr), fault_addr, - HW_PAGE_SIZE4KB, 1, - &map_attrs, HW_SET, HW_SET); - } + hw_mmu_tlb_add(resources->dw_dmmu_base, + virt_to_phys(dummy_va_addr), fault_addr, + HW_PAGE_SIZE4KB, 1, + &map_attrs, HW_SET, HW_SET); wait_for_timer(); - /* Clear MMU interrupt */ hw_mmu_event_ack(resources->dw_dmmu_base, HW_MMU_TRANSLATION_FAULT); - dump_dsp_stack(deh_mgr->hbridge_context); + dump_dsp_stack(dev_context); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR case DSP_PWRERROR: @@ -334,9 +307,6 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) dsp_status bridge_deh_get_info(struct deh_mgr *deh_mgr, struct dsp_errorinfo *pErrInfo) { - DBC_REQUIRE(deh_mgr); - DBC_REQUIRE(pErrInfo); - if (!deh_mgr) return -EFAULT; @@ -346,7 +316,7 @@ dsp_status bridge_deh_get_info(struct deh_mgr *deh_mgr, pErrInfo->dw_val2 = deh_mgr->err_info.dw_val2; pErrInfo->dw_val3 = deh_mgr->err_info.dw_val3; - return DSP_SOK; + return 0; } void bridge_deh_release_dummy_mem(void) From patchwork Sun Apr 25 10:39:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Y, Kishore" X-Patchwork-Id: 94934 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3PAc9ke013631 for ; Sun, 25 Apr 2010 10:38:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752703Ab0DYKiI (ORCPT ); Sun, 25 Apr 2010 06:38:08 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51284 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751918Ab0DYKiG convert rfc822-to-8bit (ORCPT ); Sun, 25 Apr 2010 06:38:06 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3PAc0Fo023470 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 25 Apr 2010 05:38:02 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3PAbwLR026699; Sun, 25 Apr 2010 16:07:58 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Sun, 25 Apr 2010 16:07:58 +0530 From: "Y, Kishore" To: Tomi Valkeinen CC: "linux-omap@vger.kernel.org" Date: Sun, 25 Apr 2010 16:09:21 +0530 Subject: [PATCH V2] OMAP3630:DSS2:Enable Pre-Multiplied Alpha Support Thread-Topic: [PATCH V2] OMAP3630:DSS2:Enable Pre-Multiplied Alpha Support Thread-Index: AcrkY5DeJacJWmTJQpGz7ZyBPeLxcg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 25 Apr 2010 10:38:10 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 1c529ce..545d793 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -299,6 +299,7 @@ struct omap_overlay_info { u16 out_width; /* if 0, out_width == width */ u16 out_height; /* if 0, out_height == height */ u8 global_alpha; + u8 pre_alpha_mult; }; struct omap_overlay { diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index e777e35..16770c5 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -788,6 +788,11 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) dispc_write_reg(vsi_reg[plane-1], val); } +static void _dispc_set_alpha_blend_attrs(enum omap_plane plane, bool enable) +{ + REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28); +} + static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha) { @@ -1520,7 +1525,8 @@ static int _dispc_setup_plane(enum omap_plane plane, bool ilace, enum omap_dss_rotation_type rotation_type, u8 rotation, int mirror, - u8 global_alpha) + u8 global_alpha, + u8 pre_alpha_mult) { const int maxdownscale = cpu_is_omap34xx() ? 4 : 2; bool five_taps = 0; @@ -1703,6 +1709,9 @@ static int _dispc_setup_plane(enum omap_plane plane, _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode); + if (cpu_is_omap3630() && (plane != OMAP_DSS_VIDEO1)) + _dispc_set_alpha_blend_attrs(plane, pre_alpha_mult); + if (plane != OMAP_DSS_VIDEO1) _dispc_setup_global_alpha(plane, global_alpha); @@ -3151,7 +3160,8 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_color_mode color_mode, bool ilace, enum omap_dss_rotation_type rotation_type, - u8 rotation, bool mirror, u8 global_alpha) + u8 rotation, bool mirror, u8 global_alpha, + u8 pre_alpha_mult) { int r = 0; @@ -3173,7 +3183,8 @@ int dispc_setup_plane(enum omap_plane plane, color_mode, ilace, rotation_type, rotation, mirror, - global_alpha); + global_alpha, + pre_alpha_mult); enable_clocks(0); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index ad3d16e..3534577 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -293,7 +293,8 @@ int dispc_setup_plane(enum omap_plane plane, bool ilace, enum omap_dss_rotation_type rotation_type, u8 rotation, bool mirror, - u8 global_alpha); + u8 global_alpha, + u8 pre_alpha_mult); bool dispc_go_busy(enum omap_channel channel); void dispc_go(enum omap_channel channel); diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index 0820986..c12fa14 100644 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -405,6 +405,7 @@ struct overlay_cache_data { u16 out_width; /* if 0, out_width == width */ u16 out_height; /* if 0, out_height == height */ u8 global_alpha; + u8 pre_alpha_mult; enum omap_channel channel; bool replication; @@ -816,7 +817,8 @@ static int configure_overlay(enum omap_plane plane) c->rotation_type, c->rotation, c->mirror, - c->global_alpha); + c->global_alpha, + c->pre_alpha_mult); if (r) { /* this shouldn't happen */ @@ -1199,6 +1201,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) oc->out_width = ovl->info.out_width; oc->out_height = ovl->info.out_height; oc->global_alpha = ovl->info.global_alpha; + oc->pre_alpha_mult = ovl->info.pre_alpha_mult; oc->replication = dss_use_replication(dssdev, ovl->info.color_mode); diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 8233658..cb630ba 100644 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -255,6 +255,37 @@ static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl, return size; } +static ssize_t overlay_pre_alpha_multiplication_show(struct omap_overlay *ovl, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", + ovl->info.pre_alpha_mult); +} + +static ssize_t overlay_pre_alpha_multiplication_store(struct omap_overlay *ovl, + const char *buf, size_t size) +{ + int r; + struct omap_overlay_info info; + + ovl->get_overlay_info(ovl, &info); + + /* only GFX and Video2 plane support pre alpha multiplication */ + info.pre_alpha_mult = simple_strtoul(buf, NULL, 10); + + r = ovl->set_overlay_info(ovl, &info); + if (r) + return r; + + if (ovl->manager) { + r = ovl->manager->apply(ovl->manager); + if (r) + return r; + } + + return size; +} + struct overlay_attribute { struct attribute attr; ssize_t (*show)(struct omap_overlay *, char *); @@ -278,6 +309,9 @@ static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR, overlay_enabled_show, overlay_enabled_store); static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR, overlay_global_alpha_show, overlay_global_alpha_store); +static OVERLAY_ATTR(pre_alpha_multiplication, S_IRUGO|S_IWUSR, + overlay_pre_alpha_multiplication_show, + overlay_pre_alpha_multiplication_store); static struct attribute *overlay_sysfs_attrs[] = { &overlay_attr_name.attr, @@ -288,6 +322,7 @@ static struct attribute *overlay_sysfs_attrs[] = { &overlay_attr_output_size.attr, &overlay_attr_enabled.attr, &overlay_attr_global_alpha.attr, + &overlay_attr_pre_alpha_multiplication.attr, NULL }; From patchwork Thu Jun 10 11:23:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Senthilvadivu Guruswamy X-Patchwork-Id: 105373 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5ABObeR007547 for ; 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Thu, 10 Jun 2010 16:53:57 +0530 From: Guruswamy Senthilvadivu To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, tony@atomide.com, tomi.valkeinen@nokia.com, hvaibhav@ti.com Cc: Senthilvadivu Guruswamy Subject: [PATCH v3 1/3] DSS2: Allow FB_OMAP2 to build without VRFB Date: Thu, 10 Jun 2010 16:53:55 +0530 Message-Id: <1276169037-2598-1-git-send-email-svadivu@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 10 Jun 2010 11:24:38 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h index d8a03ce..3792bde 100644 --- a/arch/arm/plat-omap/include/plat/vrfb.h +++ b/arch/arm/plat-omap/include/plat/vrfb.h @@ -35,6 +35,7 @@ struct vrfb { bool yuv_mode; }; +#ifdef CONFIG_OMAP2_VRFB extern int omap_vrfb_request_ctx(struct vrfb *vrfb); extern void omap_vrfb_release_ctx(struct vrfb *vrfb); extern void omap_vrfb_adjust_size(u16 *width, u16 *height, @@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot); extern void omap_vrfb_restore_context(void); +#else +static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; } +static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {} +static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, + u8 bytespp) {} +static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) + { return 0; } +static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) + { return 0; } +static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, + u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} +static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot) + { return 0; } +static inline void omap_vrfb_restore_context(void) {} +#endif #endif /* __VRFB_H */ From patchwork Wed May 19 09:40:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 100834 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4J9h0he018877 for ; Wed, 19 May 2010 09:43:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755897Ab0ESJm7 (ORCPT ); Wed, 19 May 2010 05:42:59 -0400 Received: from smtp.nokia.com ([192.100.122.230]:42377 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752671Ab0ESJm6 (ORCPT ); Wed, 19 May 2010 05:42:58 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4J9gb7K004913; Wed, 19 May 2010 12:42:55 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 19 May 2010 12:42:43 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 19 May 2010 12:42:23 +0300 Received: from scadufax.research.nokia.com (esdhcp041223.research.nokia.com [172.21.41.223]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4J9gKOZ003573; Wed, 19 May 2010 12:42:22 +0300 From: felipe.balbi@nokia.com To: Kevin Hilman Cc: Linux OMAP Mailing List , Felipe Balbi Subject: [PATCH 2/3] arm: omap: let pm code always handle musb pm init Date: Wed, 19 May 2010 12:40:17 +0300 Message-Id: <1274262018-32631-2-git-send-email-felipe.balbi@nokia.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274262018-32631-1-git-send-email-felipe.balbi@nokia.com> References: <1274262018-32631-1-git-send-email-felipe.balbi@nokia.com> X-OriginalArrivalTime: 19 May 2010 09:42:23.0389 (UTC) FILETIME=[955184D0:01CAF737] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 19 May 2010 09:43:00 +0000 (UTC) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 48857a4..cec9d8b 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -516,12 +516,6 @@ void omap_sram_idle(void) omap3_prcm_restore_context(); omap3_sram_restore_context(); omap2_sms_restore_context(); - /* - * Errata 1.164 fix : OTG autoidle can prevent - * sleep - */ - if (cpu_is_omap3430()) - usb_musb_disable_autoidle(); } omap_uart_resume_idle(0); omap_uart_resume_idle(1); @@ -1242,6 +1236,9 @@ static int __init omap3_pm_init(void) pm_dbg_regset_init(2); omap3_save_scratchpad_contents(); + + /* Errata 1.164 fix : OTG autoidle can prevent sleep */ + usb_musb_pm_init(); err1: return ret; err2: diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 085e22e..de3e768 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -44,12 +44,12 @@ static struct platform_device dummy_pdev = { }, }; -static void __iomem *otg_base; -static struct clk *otg_clk; - -static void __init usb_musb_pm_init(void) +void __init usb_musb_pm_init(void) { - struct device *dev = &dummy_pdev.dev; + struct device *dev = &dummy_pdev.dev; + void __iomem *otg_base; + struct clk *otg_clk; + unsigned long r; if (!cpu_is_omap34xx()) return; @@ -81,6 +81,10 @@ static void __init usb_musb_pm_init(void) __raw_readl(otg_base + OTG_SYSSTATUS))) cpu_relax(); + r = __raw_readl(otg_base + OTG_SYSCONFIG); + r &= ~(1 << 0); + __raw_writel(r, otg_base + OTG_SYSCONFIG); + clk_disable(otg_clk); out1: @@ -90,18 +94,6 @@ out0: iounmap(otg_base); } -void usb_musb_disable_autoidle(void) -{ - if (otg_clk) { - unsigned long reg; - - clk_enable(otg_clk); - reg = __raw_readl(otg_base + OTG_SYSCONFIG); - __raw_writel(reg & ~1, otg_base + OTG_SYSCONFIG); - clk_disable(otg_clk); - } -} - #ifdef CONFIG_USB_MUSB_SOC static struct resource musb_resources[] = { @@ -181,13 +173,10 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) if (platform_device_register(&musb_device) < 0) printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); - - usb_musb_pm_init(); } #else void __init usb_musb_init(struct omap_musb_board_data *board_data) { - usb_musb_pm_init(); } #endif /* CONFIG_USB_MUSB_SOC */ diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index ec7c025..cae3508 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -56,7 +56,7 @@ extern void usb_musb_init(struct omap_musb_board_data *board_data); extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata); /* This is needed for OMAP3 errata 1.164: enabled autoidle can prevent sleep */ -extern void usb_musb_disable_autoidle(void); +extern void usb_musb_pm_init(void); #endif From patchwork Thu Jun 10 11:23:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Senthilvadivu Guruswamy X-Patchwork-Id: 105372 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5ABObeQ007547 for ; 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Thu, 10 Jun 2010 16:53:58 +0530 From: Guruswamy Senthilvadivu To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, tony@atomide.com, tomi.valkeinen@nokia.com, hvaibhav@ti.com Cc: Senthilvadivu Guruswamy Subject: [PATCH v3 3/3] DSS2 FB Allow usage of def_vrfb only for omap2,3 Date: Thu, 10 Jun 2010 16:53:57 +0530 Message-Id: <1276169037-2598-3-git-send-email-svadivu@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1276169037-2598-2-git-send-email-svadivu@ti.com> References: <1276169037-2598-1-git-send-email-svadivu@ti.com> <1276169037-2598-2-git-send-email-svadivu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 10 Jun 2010 11:24:38 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 4b4506d..0f79db8 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -2128,6 +2128,16 @@ static int omapfb_probe(struct platform_device *pdev) goto err0; } + /* TODO : Replace cpu check with omap_has_vrfb once HAS_FEATURE + * available for OMAP2 and OMAP3 + */ + if (def_vrfb && (!cpu_is_omap24xx()) && (!cpu_is_omap34xx())) { + def_vrfb = 0; + dev_warn(&pdev->dev, "VRFB is not in this device," + "using DMA for rotation\n"); + } + + mutex_init(&fbdev->mtx); fbdev->dev = &pdev->dev; From patchwork Thu Aug 5 08:36:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawel Moll X-Patchwork-Id: 117255 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o7593WRd012936 for ; Thu, 5 Aug 2010 09:03:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759853Ab0HEJDb (ORCPT ); Thu, 5 Aug 2010 05:03:31 -0400 Received: from stallman.rootnode.net ([89.248.165.10]:46947 "EHLO stallman.rootnode.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758834Ab0HEJD3 (ORCPT ); Thu, 5 Aug 2010 05:03:29 -0400 X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 09:03:37 +0000 (UTC) X-Greylist: delayed 1631 seconds by postgrey-1.27 at vger.kernel.org; Thu, 05 Aug 2010 05:03:29 EDT Received: from localhost.localdomain (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by stallman.rootnode.net (Exchange) with ESMTP id 37D2E4B7B for ; Thu, 5 Aug 2010 10:36:17 +0200 (CEST) From: Pawel Moll To: linux-omap@vger.kernel.org Subject: [PATCH] omap: Update omap3evm board support Date: Thu, 5 Aug 2010 09:36:14 +0100 Message-Id: <1280997374-2314-1-git-send-email-mail@pawelmoll.com> X-Mailer: git-send-email 1.6.3.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig index 5db9a6b..fd5980a 100644 --- a/arch/arm/configs/omap3_defconfig +++ b/arch/arm/configs/omap3_defconfig @@ -182,6 +182,7 @@ CONFIG_MENELAUS=y CONFIG_TWL4030_CORE=y CONFIG_TWL4030_POWER=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_TWL4030=y CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y @@ -190,6 +191,10 @@ CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y CONFIG_FB_OMAP_LCD_VGA=y +CONFIG_OMAP2_DSS=y +CONFIG_FB_OMAP2=y +CONFIG_PANEL_GENERIC=y +CONFIG_PANEL_SHARP_LS037V7DW01=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 6494dbd..d180be7 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -157,8 +158,8 @@ static inline void __init omap3evm_init_smsc911x(void) { return; } #define OMAP3EVM_LCD_PANEL_ENVDD 153 #define OMAP3EVM_LCD_PANEL_QVGA 154 #define OMAP3EVM_LCD_PANEL_RESB 155 -#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210 #define OMAP3EVM_DVI_PANEL_EN_GPIO 199 +#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210 static int lcd_enabled; static int dvi_enabled; @@ -243,7 +244,11 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev) static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev) { + /* We don't really want to cut off the panel power, as the touch panel + * is powered from the same source... */ +#if 0 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); +#endif if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); @@ -381,7 +386,7 @@ static struct gpio_led gpio_leds[] = { { .name = "omap3evm::ledb", /* normally not visible (board underside) */ - .default_trigger = "default-on", + .default_trigger = "heartbeat", .gpio = -EINVAL, /* gets replaced */ .active_low = true, }, @@ -419,15 +424,15 @@ static int omap3evm_twl_gpio_setup(struct device *dev, */ /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ - gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + gpio_request(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, "EN_LCD_BKL"); + gpio_direction_output(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); /* gpio + 7 == DVI Enable */ gpio_request(gpio + 7, "EN_DVI"); gpio_direction_output(gpio + 7, 0); /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; + gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1; platform_device_register(&leds_gpio); @@ -493,10 +498,8 @@ static struct twl4030_codec_data omap3evm_codec_data = { .audio = &omap3evm_audio_data, }; -static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &omap3_evm_dss_device.dev, -}; +static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); /* VDAC for DSS driving S-Video */ static struct regulator_init_data omap3_evm_vdac = { @@ -514,10 +517,8 @@ static struct regulator_init_data omap3_evm_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_evm_vpll2_supply = { - .supply = "vdvi", - .dev = &omap3_evm_lcd_device.dev, -}; +static struct regulator_consumer_supply omap3_evm_vpll2_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); static struct regulator_init_data omap3_evm_vpll2 = { .constraints = { @@ -573,6 +574,29 @@ static int __init omap3_evm_i2c_init(void) return 0; } +static struct regulator_consumer_supply ads7846_consumer_supply = + REGULATOR_SUPPLY("vcc", "spi1.0"); + +struct regulator_init_data ads7846_vcc_initdata = { + .consumer_supplies = &ads7846_consumer_supply, + .num_consumer_supplies = 1, +}; + +static struct fixed_voltage_config ads7846_vcc_config = { + .supply_name = "VIO_1v8", + .microvolts = 1800000, + .gpio = -1, + .init_data = &ads7846_vcc_initdata, +}; + +static struct platform_device omap3_evm_ads7846_vcc_device = { + .name = "reg-fixed-voltage", + .id = -1, + .dev = { + .platform_data = &ads7846_vcc_config, + }, +}; + static void ads7846_dev_init(void) { if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0) @@ -631,6 +655,7 @@ static void __init omap3_evm_init_irq(void) } static struct platform_device *omap3_evm_devices[] __initdata = { + &omap3_evm_ads7846_vcc_device, &omap3_evm_dss_device, }; From patchwork Sat May 29 05:28:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 103014 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4T5SiW1012535 for ; Sat, 29 May 2010 05:28:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751411Ab0E2F2t (ORCPT ); Sat, 29 May 2010 01:28:49 -0400 Received: from mail-iw0-f174.google.com ([209.85.214.174]:33300 "EHLO mail-iw0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751271Ab0E2F2s (ORCPT ); Sat, 29 May 2010 01:28:48 -0400 Received: by mail-iw0-f174.google.com with SMTP id 6so160874iwn.19 for ; Fri, 28 May 2010 22:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; 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Sat, 29 May 2010 05:28:50 +0000 (UTC) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 78b49a6..52f61f6 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -2,6 +2,24 @@ if ARCH_OMAP menu "TI OMAP Implementations" +config OMAP_GPIO_EXTRA + int + default 128 if OMAP_GPIO_EXTRA128 + default 64 if OMAP_GPIO_EXTRA64 + default 0 + +config OMAP_GPIO_EXTRA64 + bool + help + Add an extra 64 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + +config OMAP_GPIO_EXTRA128 + bool + help + Add an extra 128 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + config ARCH_OMAP_OTG bool diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index de1c604..d21b790 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -86,6 +86,13 @@ extern void omap_gpio_restore_context(void); * The original OMAP-specfic calls should eventually be removed. */ +/* + * Some boards require extra gpio capacity to support external + * devices that need GPIO. + */ + +#define ARCH_NR_GPIOS (256 + CONFIG_OMAP_GPIO_EXTRA) + #include #include From patchwork Wed May 19 09:40:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 100832 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4J9gXPE018733 for ; Wed, 19 May 2010 09:42:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753794Ab0ESJmd (ORCPT ); Wed, 19 May 2010 05:42:33 -0400 Received: from smtp.nokia.com ([192.100.122.233]:30537 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752671Ab0ESJmc (ORCPT ); Wed, 19 May 2010 05:42:32 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4J9g3bi023388; Wed, 19 May 2010 12:42:26 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 19 May 2010 12:42:24 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 19 May 2010 12:42:24 +0300 Received: from scadufax.research.nokia.com (esdhcp041223.research.nokia.com [172.21.41.223]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4J9gKOa003573; Wed, 19 May 2010 12:42:23 +0300 From: felipe.balbi@nokia.com To: Kevin Hilman Cc: Linux OMAP Mailing List , Felipe Balbi Subject: [PATCH 3/3] arm: omap: musb: do not issue SOFTRESET on omap3630 Date: Wed, 19 May 2010 12:40:18 +0300 Message-Id: <1274262018-32631-3-git-send-email-felipe.balbi@nokia.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274262018-32631-1-git-send-email-felipe.balbi@nokia.com> References: <1274262018-32631-1-git-send-email-felipe.balbi@nokia.com> X-OriginalArrivalTime: 19 May 2010 09:42:24.0792 (UTC) FILETIME=[96279980:01CAF737] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 19 May 2010 09:42:34 +0000 (UTC) diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index de3e768..97dae0d 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -54,6 +54,10 @@ void __init usb_musb_pm_init(void) if (!cpu_is_omap34xx()) return; + /* Errata ID i445 fix : Do not use SOFTRESET with OMAP3630 */ + if (cpu_is_omap3630()) + return; + otg_base = ioremap(OMAP34XX_HSUSB_OTG_BASE, SZ_4K); if (WARN_ON(!otg_base)) return; From patchwork Wed Jul 21 17:33:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113400 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONH007938 for ; Wed, 21 Jul 2010 17:35:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758178Ab0GURea (ORCPT ); Wed, 21 Jul 2010 13:34:30 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757616Ab0GURe2 (ORCPT ); Wed, 21 Jul 2010 13:34:28 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:27 -0700 (PDT) Received: by 10.204.126.82 with SMTP id b18mr388224bks.124.1279733667194; Wed, 21 Jul 2010 10:34:27 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:26 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 02/20] wireless: wl1271: remove SDIO IDs from driver Date: Wed, 21 Jul 2010 20:33:36 +0300 Message-Id: <1279733634-21974-3-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:09 +0000 (UTC) diff --git a/drivers/net/wireless/wl12xx/wl1271_sdio.c b/drivers/net/wireless/wl12xx/wl1271_sdio.c index d3d6f30..9903ae9 100644 --- a/drivers/net/wireless/wl12xx/wl1271_sdio.c +++ b/drivers/net/wireless/wl12xx/wl1271_sdio.c @@ -37,14 +37,6 @@ #define RX71_WL1271_IRQ_GPIO 42 -#ifndef SDIO_VENDOR_ID_TI -#define SDIO_VENDOR_ID_TI 0x0097 -#endif - -#ifndef SDIO_DEVICE_ID_TI_WL1271 -#define SDIO_DEVICE_ID_TI_WL1271 0x4076 -#endif - static const struct sdio_device_id wl1271_devices[] = { { SDIO_DEVICE(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271) }, {} From patchwork Mon Jul 26 22:28:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 114361 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6QMSGoN019310 for ; Mon, 26 Jul 2010 22:28:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755057Ab0GZW2N (ORCPT ); Mon, 26 Jul 2010 18:28:13 -0400 Received: from utopia.booyaka.com ([72.9.107.138]:51148 "EHLO utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751874Ab0GZW2N (ORCPT ); Mon, 26 Jul 2010 18:28:13 -0400 Received: (qmail 477 invoked by uid 1019); 26 Jul 2010 22:28:12 -0000 Date: Mon, 26 Jul 2010 16:28:12 -0600 (MDT) From: Paul Walmsley To: Dmitry Torokhov , Tony Lindgren cc: Laurent Pinchart , Amit Kucheria , linux-input@vger.kernel.org, linux-omap@vger.kernel.org, stable@kernel.org Subject: [PATCH] Input: OMAP: RX51: fix 'KEY_10' compile breakage Message-ID: User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 26 Jul 2010 22:28:16 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index c5555ca..0348392 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -220,10 +220,10 @@ static int board_keymap[] = { KEY(4, 4, KEY_LEFTCTRL), KEY(4, 5, KEY_RIGHTALT), KEY(4, 6, KEY_LEFTSHIFT), - KEY(4, 8, KEY_10), + KEY(4, 8, KEY_F10), KEY(5, 0, KEY_Y), - KEY(5, 8, KEY_11), + KEY(5, 8, KEY_F11), KEY(6, 0, KEY_U), From patchwork Wed Jul 21 17:33:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113402 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONL007938 for ; Wed, 21 Jul 2010 17:35:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758267Ab0GUReh (ORCPT ); Wed, 21 Jul 2010 13:34:37 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756699Ab0GUReg (ORCPT ); Wed, 21 Jul 2010 13:34:36 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:35 -0700 (PDT) Received: by 10.204.150.74 with SMTP id x10mr366988bkv.130.1279733674714; Wed, 21 Jul 2010 10:34:34 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.30 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:33 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 04/20] omap zoom2: wlan board muxing Date: Wed, 21 Jul 2010 20:33:38 +0300 Message-Id: <1279733634-21974-5-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:10 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 803ef14..1520a2c 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -71,6 +71,19 @@ static struct twl4030_platform_data zoom2_twldata = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else From patchwork Wed Jul 21 17:33:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113403 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONM007938 for ; Wed, 21 Jul 2010 17:35:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758301Ab0GURen (ORCPT ); Wed, 21 Jul 2010 13:34:43 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757616Ab0GURel (ORCPT ); Wed, 21 Jul 2010 13:34:41 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:40 -0700 (PDT) Received: by 10.204.47.193 with SMTP id o1mr349522bkf.134.1279733678115; Wed, 21 Jul 2010 10:34:38 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:37 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 05/20] omap zoom3: wlan board muxing Date: Wed, 21 Jul 2010 20:33:39 +0300 Message-Id: <1279733634-21974-6-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:10 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 3314704..7d17046 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -46,6 +46,19 @@ static void __init omap_zoom_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else From patchwork Wed Jul 21 17:33:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113405 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONO007938 for ; Wed, 21 Jul 2010 17:35:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758316Ab0GURer (ORCPT ); Wed, 21 Jul 2010 13:34:47 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756699Ab0GURep (ORCPT ); Wed, 21 Jul 2010 13:34:45 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:44 -0700 (PDT) Received: by 10.204.73.130 with SMTP id q2mr370323bkj.137.1279733683974; Wed, 21 Jul 2010 10:34:43 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:42 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 06/20] wireless: wl1271: make wl12xx.h common to both spi and sdio Date: Wed, 21 Jul 2010 20:33:40 +0300 Message-Id: <1279733634-21974-7-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:11 +0000 (UTC) diff --git a/drivers/net/wireless/wl12xx/wl1251_sdio.c b/drivers/net/wireless/wl12xx/wl1251_sdio.c index c561332..416d5aa 100644 --- a/drivers/net/wireless/wl12xx/wl1251_sdio.c +++ b/drivers/net/wireless/wl12xx/wl1251_sdio.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include "wl1251.h" diff --git a/drivers/net/wireless/wl12xx/wl1251_spi.c b/drivers/net/wireless/wl12xx/wl1251_spi.c index e814742..4847b6a 100644 --- a/drivers/net/wireless/wl12xx/wl1251_spi.c +++ b/drivers/net/wireless/wl12xx/wl1251_spi.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include "wl1251.h" #include "wl1251_reg.h" diff --git a/drivers/net/wireless/wl12xx/wl1271_spi.c b/drivers/net/wireless/wl12xx/wl1271_spi.c index 5189b81..e866049 100644 --- a/drivers/net/wireless/wl12xx/wl1271_spi.c +++ b/drivers/net/wireless/wl12xx/wl1271_spi.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include "wl1271.h" diff --git a/include/linux/spi/wl12xx.h b/include/linux/spi/wl12xx.h deleted file mode 100644 index a223ecb..0000000 --- a/include/linux/spi/wl12xx.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of wl12xx - * - * Copyright (C) 2009 Nokia Corporation - * - * Contact: Kalle Valo - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef _LINUX_SPI_WL12XX_H -#define _LINUX_SPI_WL12XX_H - -struct wl12xx_platform_data { - void (*set_power)(bool enable); - /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */ - int irq; - bool use_eeprom; -}; - -#endif diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h new file mode 100644 index 0000000..137ac89 --- /dev/null +++ b/include/linux/wl12xx.h @@ -0,0 +1,34 @@ +/* + * This file is part of wl12xx + * + * Copyright (C) 2009 Nokia Corporation + * + * Contact: Kalle Valo + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef _LINUX_WL12XX_H +#define _LINUX_WL12XX_H + +struct wl12xx_platform_data { + void (*set_power)(bool enable); + /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */ + int irq; + bool use_eeprom; +}; + +#endif From patchwork Wed Jul 7 17:24:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 110681 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o67HOSFU013119 for ; Wed, 7 Jul 2010 17:24:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753099Ab0GGRY1 (ORCPT ); Wed, 7 Jul 2010 13:24:27 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:35119 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751394Ab0GGRY0 (ORCPT ); Wed, 7 Jul 2010 13:24:26 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o67HOHnD027807 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 7 Jul 2010 12:24:17 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o67HOG5e020494; Wed, 7 Jul 2010 12:24:16 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o67HOGSL002893; Wed, 7 Jul 2010 12:24:16 -0500 (CDT) Received: from [128.247.74.250] (128.247.74.250) by dlee73.ent.ti.com (157.170.170.88) with Microsoft SMTP Server id 8.1.358.0; Wed, 7 Jul 2010 12:24:16 -0500 Message-ID: <4C34B840.3060907@ti.com> Date: Wed, 7 Jul 2010 12:24:16 -0500 From: Nishanth Menon User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: Tony Lindgren CC: linux-omap , Angelo Arrifano , "Zebediah C. McClure" , Alistair Buxton , Grazvydas Ignotas , Paul Walmsley , "Premi, Sanjeev" , "Shilimkar, Santosh" , "Guruswamy, Senthilvadivu" , Kevin Hilman , "DebBarma, Tarun Kanti" , Tomi Valkeinen , Aaro Koskinen , "Pandita, Vikram" , "S, Vishwanath" Subject: Re: [PATCH 3/9 v3] omap: generic: introduce a single check_revision References: <1277483122-3616-1-git-send-email-nm@ti.com> <20100707123633.GT1920@atomide.com> In-Reply-To: <20100707123633.GT1920@atomide.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 07 Jul 2010 17:24:28 +0000 (UTC) From f72070e575433ad07ed018aef5c43677424003d0 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 21 May 2010 12:09:33 -0500 Subject: [PATCH 2/7] omap: generic: introduce a single check_revision Introduce a single omap generic check_revision that routes the request to the right revision of check_revision. Note: OMAP1 and OMAP2+ are not built into a single kernel. Cc: Tony Lindgren Cc: Angelo Arrifano Cc: "Zebediah C. McClure" Cc: Alistair Buxton Cc: Grazvydas Ignotas Cc: Paul Walmsley Cc: Sanjeev Premi Cc: Santosh Shilimkar Cc: Senthilvadivu Gurusamy Cc: Kevin Hilman Cc: Tarun Kanti DebBarma Cc: Tomi Valkeinen Cc: Aaro Koskinen Cc: Vikram Pandita Cc: Vishwanath S Cc: linux-omap@vger.kernel.org Signed-off-by: Nishanth Menon --- arch/arm/mach-omap1/io.c | 1 - arch/arm/mach-omap2/id.c | 2 +- arch/arm/mach-omap2/io.c | 2 +- arch/arm/plat-omap/include/plat/cpu.h | 3 ++- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 0ce3fec..4f9ee73 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -20,7 +20,6 @@ #include "clock.h" -extern void omap_check_revision(void); extern void omap_sram_init(void); /* diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index c7bf0e1..80f0950 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -371,7 +371,7 @@ static void __init omap3_cpuinfo(void) /* * Try to detect the exact revision of the omap we're running on */ -void __init omap2_check_revision(void) +void __init omap_check_revision(void) { /* * At this point we have an idea about the processor revision set diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b9ea70b..75883fe 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -238,7 +238,7 @@ static void __init _omap2_map_common_io(void) local_flush_tlb_all(); flush_cache_all(); - omap2_check_revision(); + omap_check_revision(); omap_sram_init(); } diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 7514174..d25ba40 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -431,7 +431,8 @@ IS_OMAP_TYPE(3517, 0x3517) int omap_chip_is(struct omap_chip_id oci); -void omap2_check_revision(void); + +void omap_check_revision(void); /* * Runtime detection of OMAP3 features -- 1.6.3.3 From patchwork Wed Jul 21 17:33:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 113407 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LHYONQ007938 for ; Wed, 21 Jul 2010 17:35:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758399Ab0GUReu (ORCPT ); Wed, 21 Jul 2010 13:34:50 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:59315 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756699Ab0GURes (ORCPT ); Wed, 21 Jul 2010 13:34:48 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so374531bwz.19 for ; Wed, 21 Jul 2010 10:34:47 -0700 (PDT) Received: by 10.204.126.223 with SMTP id d31mr365446bks.146.1279733687715; Wed, 21 Jul 2010 10:34:47 -0700 (PDT) Received: from localhost.localdomain (93-172-119-238.bb.netvision.net.il [93.172.119.238]) by mx.google.com with ESMTPS id f10sm29348743bkl.5.2010.07.21.10.34.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Jul 2010 10:34:46 -0700 (PDT) From: Ohad Ben-Cohen To: , , Cc: , , Chikkature Rajashekar Madhusudhan , Luciano Coelho , , San Mehat , Roger Quadros , Tony Lindgren , Nicolas Pitre , Pandita Vikram , Kalle Valo , Ohad Ben-Cohen Subject: [PATCH v2 07/20] wireless: wl1271: support return value for the set power func Date: Wed, 21 Jul 2010 20:33:41 +0300 Message-Id: <1279733634-21974-8-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1279733634-21974-1-git-send-email-ohad@wizery.com> References: <1279733634-21974-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 17:35:12 +0000 (UTC) diff --git a/drivers/net/wireless/wl12xx/wl1271.h b/drivers/net/wireless/wl12xx/wl1271.h index 6f1b6b5..a21cdb2 100644 --- a/drivers/net/wireless/wl12xx/wl1271.h +++ b/drivers/net/wireless/wl12xx/wl1271.h @@ -340,7 +340,7 @@ struct wl1271_if_operations { bool fixed); void (*reset)(struct wl1271 *wl); void (*init)(struct wl1271 *wl); - void (*power)(struct wl1271 *wl, bool enable); + int (*power)(struct wl1271 *wl, bool enable); struct device* (*dev)(struct wl1271 *wl); void (*enable_irq)(struct wl1271 *wl); void (*disable_irq)(struct wl1271 *wl); diff --git a/drivers/net/wireless/wl12xx/wl1271_io.h b/drivers/net/wireless/wl12xx/wl1271_io.h index bc806c7..4a5b92c 100644 --- a/drivers/net/wireless/wl12xx/wl1271_io.h +++ b/drivers/net/wireless/wl12xx/wl1271_io.h @@ -144,10 +144,12 @@ static inline void wl1271_power_off(struct wl1271 *wl) clear_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); } -static inline void wl1271_power_on(struct wl1271 *wl) +static inline int wl1271_power_on(struct wl1271 *wl) { - wl->if_ops->power(wl, true); - set_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); + int ret = wl->if_ops->power(wl, true); + if (ret == 0) + set_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); + return ret; } diff --git a/drivers/net/wireless/wl12xx/wl1271_main.c b/drivers/net/wireless/wl12xx/wl1271_main.c index b7d9137..6bd748e 100644 --- a/drivers/net/wireless/wl12xx/wl1271_main.c +++ b/drivers/net/wireless/wl12xx/wl1271_main.c @@ -620,7 +620,9 @@ static int wl1271_chip_wakeup(struct wl1271 *wl) int ret = 0; msleep(WL1271_PRE_POWER_ON_SLEEP); - wl1271_power_on(wl); + ret = wl1271_power_on(wl); + if (ret < 0) + goto out; msleep(WL1271_POWER_ON_SLEEP); wl1271_io_reset(wl); wl1271_io_init(wl); diff --git a/drivers/net/wireless/wl12xx/wl1271_sdio.c b/drivers/net/wireless/wl12xx/wl1271_sdio.c index 9903ae9..571c6b9 100644 --- a/drivers/net/wireless/wl12xx/wl1271_sdio.c +++ b/drivers/net/wireless/wl12xx/wl1271_sdio.c @@ -144,7 +144,7 @@ static void wl1271_sdio_raw_write(struct wl1271 *wl, int addr, void *buf, } -static void wl1271_sdio_set_power(struct wl1271 *wl, bool enable) +static int wl1271_sdio_set_power(struct wl1271 *wl, bool enable) { struct sdio_func *func = wl_to_func(wl); @@ -159,6 +159,8 @@ static void wl1271_sdio_set_power(struct wl1271 *wl, bool enable) sdio_disable_func(func); sdio_release_host(func); } + + return 0; } static struct wl1271_if_operations sdio_ops = { diff --git a/drivers/net/wireless/wl12xx/wl1271_spi.c b/drivers/net/wireless/wl12xx/wl1271_spi.c index e866049..85a167f 100644 --- a/drivers/net/wireless/wl12xx/wl1271_spi.c +++ b/drivers/net/wireless/wl12xx/wl1271_spi.c @@ -313,10 +313,12 @@ static irqreturn_t wl1271_irq(int irq, void *cookie) return IRQ_HANDLED; } -static void wl1271_spi_set_power(struct wl1271 *wl, bool enable) +static int wl1271_spi_set_power(struct wl1271 *wl, bool enable) { if (wl->set_power) wl->set_power(enable); + + return 0; } static struct wl1271_if_operations spi_ops = { From patchwork Tue Jun 22 15:01:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107412 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF1f2w017732 for ; Tue, 22 Jun 2010 15:01:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758763Ab0FVPBi (ORCPT ); Tue, 22 Jun 2010 11:01:38 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41827 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758650Ab0FVPBb (ORCPT ); Tue, 22 Jun 2010 11:01:31 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1P0u024615 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:28 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZt026711; Tue, 22 Jun 2010 20:31:23 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 13/13] OMAP: GPIO: Remove omap_gpio_init() Date: Tue, 22 Jun 2010 20:31:56 +0530 Message-Id: <1277218916-15213-14-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-13-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> <1277218916-15213-3-git-send-email-charu@ti.com> <1277218916-15213-4-git-send-email-charu@ti.com> <1277218916-15213-5-git-send-email-charu@ti.com> <1277218916-15213-6-git-send-email-charu@ti.com> <1277218916-15213-7-git-send-email-charu@ti.com> <1277218916-15213-8-git-send-email-charu@ti.com> <1277218916-15213-9-git-send-email-charu@ti.com> <1277218916-15213-10-git-send-email-charu@ti.com> <1277218916-15213-11-git-send-email-charu@ti.com> <1277218916-15213-12-git-send-email-charu@ti.com> <1277218916-15213-13-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:42 +0000 (UTC) diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index fdd1dd5..75d1bd0 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -136,7 +136,6 @@ static void __init ams_delta_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static struct map_desc ams_delta_io_desc[] __initdata = { diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 096f2ed..8d9d6e8 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -313,7 +313,6 @@ static void __init omap_fsample_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); fsample_init_smc91x(); } diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index d1100e4..dd04ef5 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -383,7 +383,6 @@ static void __init h2_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); h2_init_smc91x(); } diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index a53ab82..ac8af4b 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -422,7 +422,6 @@ static void __init h3_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); h3_init_smc91x(); } diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 8e313b4..6ff6f30 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -278,7 +278,6 @@ static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); - omap_gpio_init(); omap_board_config = htcherald_config; omap_board_config_size = ARRAY_SIZE(htcherald_config); diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 5d12fd3..28bb2cd 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -290,7 +290,6 @@ static void __init innovator_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { omap1510_fpga_init_irq(); diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 71e1a3f..6ea838c 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -379,7 +379,6 @@ static void __init omap_nokia770_init(void) platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); spi_register_board_info(nokia770_spi_board_info, ARRAY_SIZE(nokia770_spi_board_info)); - omap_gpio_init(); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); omap_dsp_init(); diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 80d8620..2db7712 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -283,7 +283,6 @@ static void __init osk_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); osk_init_smc91x(); osk_init_cf(); } diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 569b4c9..3864eab 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -63,7 +63,6 @@ static void __init omap_palmte_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static const int palmte_keymap[] = { diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 6641de9..8e3174d 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -62,7 +62,6 @@ omap_palmz71_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static int palmz71_keymap[] = { diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index e854d57..d9f1ce7 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -281,7 +281,6 @@ static void __init omap_perseus2_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); perseus2_init_smc91x(); } /* Only FPGA needs to be mapped here. All others are done with ioremap */ diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 2fb1e5f..f19e32c 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -409,7 +409,6 @@ static void __init omap_sx1_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } /*----------------------------------------*/ diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 87b9436..df5e975 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -158,7 +158,6 @@ static void __init voiceblue_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); - omap_gpio_init(); } static void __init voiceblue_init(void) diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index a11a575..07a75d2 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -148,7 +148,6 @@ static void __init omap_2430sdp_init_irq(void) omap_board_config_size = ARRAY_SIZE(sdp2430_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static struct twl4030_gpio_platform_data sdp2430_gpio_data = { diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index f474a80..abc4d28 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -328,7 +328,6 @@ static void __init omap_3430sdp_init_irq(void) omap3_pm_init_cpuidle(omap3_cpuidle_params_table); omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); omap_init_irq(); - omap_gpio_init(); } static int sdp3430_batt_table[] = { diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 504d2bd..3a47578 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -82,7 +82,6 @@ static void __init omap_sdp_init_irq(void) omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index e4a5d66..0094cfb 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -131,7 +131,6 @@ static void __init omap_4430sdp_init_irq(void) omap2_gp_clockevent_set_gptimer(1); #endif gic_init_irq(); - omap_gpio_init(); } static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index af383a8..abf2703 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -372,7 +372,6 @@ static void __init am3517_evm_init_irq(void) omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index aa69fb9..269cd73 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -279,7 +279,6 @@ static void __init omap_apollon_init_irq(void) omap_board_config_size = ARRAY_SIZE(apollon_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); apollon_init_smc91x(); } diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index e679a2c..af6d039 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -705,7 +705,6 @@ static void __init cm_t35_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static void __init cm_t35_map_io(void) diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 77022b5..55addbc 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -472,7 +472,6 @@ static void __init devkit8000_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static void __init devkit8000_ads7846_init(void) diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 0665f2c..bd4e4ef 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -314,7 +314,6 @@ static void __init omap_h4_init_irq(void) omap_board_config_size = ARRAY_SIZE(h4_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); h4_init_flash(); } diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d55c57b..0e004cb 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -406,7 +406,6 @@ static void __init igep2_init_irq(void) omap_board_config_size = ARRAY_SIZE(igep2_config); omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct twl4030_codec_audio_data igep2_audio_data = { diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index fefd7e6..f60cda8 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -291,7 +291,6 @@ static void __init omap_ldp_init_irq(void) omap_board_config_size = ARRAY_SIZE(ldp_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); ldp_init_smsc911x(); } diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 3ccc34e..8efaacd 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -646,7 +646,6 @@ static void __init n8x0_init_irq(void) { omap2_init_common_hw(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static void __init n8x0_init_machine(void) diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 69b154c..19da4fa 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -410,7 +410,6 @@ static void __init omap3_beagle_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_beagle_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index b952610..f67e611 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -627,7 +627,6 @@ static void __init omap3_evm_init_irq(void) omap_board_config_size = ARRAY_SIZE(omap3_evm_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); omap_init_irq(); - omap_gpio_init(); } static struct platform_device *omap3_evm_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index db06dc9..ef415e3 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -536,7 +536,6 @@ static void __init omap3pandora_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct platform_device *omap3pandora_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index a04cffd..bccf466 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -588,7 +588,6 @@ static void __init omap3_stalker_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_stalker_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 2f5f823..252aaed 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -444,7 +444,6 @@ static void __init omap3_touchbook_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_touchbook_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 79ac414..6fa95e5 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -399,7 +399,6 @@ static void __init overo_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct platform_device *overo_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 1b86b5b..4e9b749 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -108,7 +108,6 @@ static void __init rx51_init_irq(void) sdrc_params = rx51_get_sdram_timings(); omap2_init_common_hw(sdrc_params, sdrc_params); omap_init_irq(); - omap_gpio_init(); } extern void __init rx51_peripherals_init(void); diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 803ef14..67bee0a 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -31,7 +31,6 @@ static void __init omap_zoom2_init_irq(void) omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } /* REVISIT: These audio entries can be removed once MFD code is merged */ diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 3314704..4285d43 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -41,7 +41,6 @@ static void __init omap_zoom_init_irq(void) omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 7f8ef27..e6d7abe 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2109,12 +2109,6 @@ static int __init omap_gpio_drv_reg(void) } postcore_initcall(omap_gpio_drv_reg); -/* TODO: Remove omap_gpio_init() and its usage from board files */ -int __init omap_gpio_init(void) -{ - return 0; -} - static int __init omap_gpio_sysinit(void) { int ret = 0; diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index b7adc5a..3c158cf 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -94,7 +94,6 @@ struct omap_gpio_platform_data { /* TODO: Analyze removing gpio_bank_count usage from driver code */ extern int gpio_bank_count; -extern int omap_gpio_init(void); /* Call from board init only */ extern void omap2_gpio_prepare_for_idle(int power_state); extern void omap2_gpio_resume_after_idle(void); extern void omap_set_gpio_debounce(int gpio, int enable); From patchwork Mon Aug 2 15:29:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 116546 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FUOxA014464 for ; Mon, 2 Aug 2010 15:30:55 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752969Ab0HBPay (ORCPT ); Mon, 2 Aug 2010 11:30:54 -0400 Received: from mail-pw0-f46.google.com ([209.85.160.46]:46764 "EHLO mail-pw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752102Ab0HBPay (ORCPT ); Mon, 2 Aug 2010 11:30:54 -0400 Received: by pwi5 with SMTP id 5so1384845pwi.19 for ; Mon, 02 Aug 2010 08:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=CCFXbM77z5CAWfdRBM0/EnDSSQUU4HXS7LBvjtRAOT0=; b=xRlz9Z2I1jBUrkeuQkTc96ZEdociV1dct2JauoY3t9EBqAANKf3CTF3Bnhlsrkfb8T oSJ2WHPdD8AbtrRBtttA52L4yC7P4pWFeWxjfNXG9AP2TXg3KfmZz3xlu4H5lzM/BzNC 7FKh3W0sWj5gJgn+V9ZFQsjLyoBLywoDkBp1c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=j3Ah49ALZONAwcINHcuqmIEYsJF4Je4M7H1VdCkg+gmNGnkFQpuJiYczfBi5t38VED QScBQE+pP3vVy+yUc7bUJtQQWh0d9EiPsebZcQixPDqfDwJgAmEIqRtjGymit3wixHLL Eyj6IENAlZlPEljtFMZkdYdWkFb9j5I0s/Fx0= Received: by 10.142.157.6 with SMTP id f6mr5437712wfe.181.1280763053690; Mon, 02 Aug 2010 08:30:53 -0700 (PDT) Received: from localhost (97-126-99-222.tukw.qwest.net [97.126.99.222]) by mx.google.com with ESMTPS id n20sm5582983ibe.11.2010.08.02.08.30.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Aug 2010 08:30:52 -0700 (PDT) From: Cory Maccarrone To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Cory Maccarrone Subject: [PATCH 5/5] [htcherald] Add board support for UARTs, bluetooth Date: Mon, 2 Aug 2010 08:29:36 -0700 Message-Id: <1280762976-17284-6-git-send-email-darkstar6262@gmail.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> References: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:30:55 +0000 (UTC) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index facfaeb..0b8cb18 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -42,7 +42,7 @@ obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o -obj-$(CONFIG_MACH_HERALD) += board-htcherald.o +obj-$(CONFIG_MACH_HERALD) += board-htcherald.o htc-bt.o ifeq ($(CONFIG_ARCH_OMAP15XX),y) # Innovator-1510 FPGA diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 1b12b75..cf4b908 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -47,8 +47,10 @@ #include #include #include +#include #include +#include #include @@ -138,6 +140,7 @@ Happy Times 0 1 0 x x x 0 x #define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) #define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) +#define HTCPLD_GPIO_BT_POWER HTCPLD_BASE(1, 4) #define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) #define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) #define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) @@ -423,6 +426,22 @@ static struct omap_mmc_platform_data htc_mmc1_data = { static struct omap_mmc_platform_data *htc_mmc_data[1]; #endif +/* Bluetooth */ +#define HTCHERALD_GPIO_BT_ENABLE 125 + +static struct htc_bt_data htcherald_bt_data = { + .uart_clock = "uart1_ck", + .gpio_pwr = HTCPLD_GPIO_BT_POWER, + .gpio_enable = HTCHERALD_GPIO_BT_ENABLE, +}; + +static struct platform_device bt_device = { + .name = "htc-bt", + .id = -1, + .dev = { + .platform_data = &htcherald_bt_data, + }, +}; /* Platform devices for the Herald */ static struct platform_device *devices[] __initdata = { @@ -431,6 +450,7 @@ static struct platform_device *devices[] __initdata = { &htcpld_device, &gpio_leds_device, &herald_gpiokeys_device, + &bt_device, }; /* @@ -574,6 +594,7 @@ done: printk(KERN_INFO "USB setup complete.\n"); } + static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); @@ -595,6 +616,8 @@ static void __init htcherald_init(void) omap_register_i2c_bus(1, 100, NULL, 0); + omap_serial_init(); + #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) htc_mmc_data[0] = &htc_mmc1_data; omap1_init_mmc(htc_mmc_data, 1); From patchwork Tue Jun 22 15:01:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107410 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF1axU017688 for ; Tue, 22 Jun 2010 15:01:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758769Ab0FVPBj (ORCPT ); Tue, 22 Jun 2010 11:01:39 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33376 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758640Ab0FVPBb (ORCPT ); Tue, 22 Jun 2010 11:01:31 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1PlV031365 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:27 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZr026711; Tue, 22 Jun 2010 20:31:22 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 11/13] OMAP: GPIO: Introduce support for OMAP2PLUS chip GPIO init Date: Tue, 22 Jun 2010 20:31:54 +0530 Message-Id: <1277218916-15213-12-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-11-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> <1277218916-15213-3-git-send-email-charu@ti.com> <1277218916-15213-4-git-send-email-charu@ti.com> <1277218916-15213-5-git-send-email-charu@ti.com> <1277218916-15213-6-git-send-email-charu@ti.com> <1277218916-15213-7-git-send-email-charu@ti.com> <1277218916-15213-8-git-send-email-charu@ti.com> <1277218916-15213-9-git-send-email-charu@ti.com> <1277218916-15213-10-git-send-email-charu@ti.com> <1277218916-15213-11-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:40 +0000 (UTC) diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c new file mode 100644 index 0000000..a5b0b60 --- /dev/null +++ b/arch/arm/mach-omap2/gpio.c @@ -0,0 +1,86 @@ +/* + * gpio.c - OMAP2PLUS-specific gpio code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Author: + * Charulatha V + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +static struct omap_device_pm_latency omap_gpio_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +static int omap2_init_gpio(struct omap_hwmod *oh, void *user) +{ + struct omap_device *od; + struct omap_gpio_platform_data *pdata; + char *name = "omap-gpio"; + static int id; + struct omap_gpio_dev_attr *gpio_dev_data; + + if (!oh) + pr_err("Could not look up omap gpio %d\n", id + 1); + + pdata = kzalloc(sizeof(struct omap_gpio_platform_data), + GFP_KERNEL); + if (!pdata) { + pr_err("Memory allocation failed gpio%d\n", id + 1); + return -ENOMEM; + } + + gpio_dev_data = (struct omap_gpio_dev_attr *)oh->dev_attr; + + pdata->gpio_attr = gpio_dev_data; + pdata->virtual_irq_start = IH_GPIO_BASE + 32 * id; + switch (oh->class->rev) { + case 0: + case 1: + pdata->bank_type = METHOD_GPIO_24XX; + break; + case 2: + pdata->bank_type = METHOD_GPIO_44XX; + break; + default: + WARN(1, "Invalid gpio bank_type\n"); + break; + } + gpio_bank_count++; + + od = omap_device_build(name, id, oh, pdata, + sizeof(*pdata), omap_gpio_latency, + ARRAY_SIZE(omap_gpio_latency), + false); + WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", + name, oh->name); + + id++; + return 0; +} + +/* + * gpio_init needs to be done before + * machine_init functions access gpio APIs. + * Hence gpio_init is a postcore_initcall. + */ +static int __init omap2_gpio_init(void) +{ + return omap_hwmod_for_each_by_class("gpio", omap2_init_gpio, + NULL); +} +postcore_initcall(omap2_gpio_init); From patchwork Tue Jun 22 15:01:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107411 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF1f2v017732 for ; Tue, 22 Jun 2010 15:01:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758785Ab0FVPBj (ORCPT ); Tue, 22 Jun 2010 11:01:39 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41826 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756022Ab0FVPBb (ORCPT ); Tue, 22 Jun 2010 11:01:31 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1P2B024614 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:27 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZs026711; Tue, 22 Jun 2010 20:31:22 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 12/13] OMAP: GPIO: Implement GPIO as a platform device Date: Tue, 22 Jun 2010 20:31:55 +0530 Message-Id: <1277218916-15213-13-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-12-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> <1277218916-15213-3-git-send-email-charu@ti.com> <1277218916-15213-4-git-send-email-charu@ti.com> <1277218916-15213-5-git-send-email-charu@ti.com> <1277218916-15213-6-git-send-email-charu@ti.com> <1277218916-15213-7-git-send-email-charu@ti.com> <1277218916-15213-8-git-send-email-charu@ti.com> <1277218916-15213-9-git-send-email-charu@ti.com> <1277218916-15213-10-git-send-email-charu@ti.com> <1277218916-15213-11-git-send-email-charu@ti.com> <1277218916-15213-12-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:42 +0000 (UTC) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index fd4df71..69f293d 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -46,6 +46,12 @@ ifeq ($(CONFIG_ARCH_OMAP15XX),y) obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o endif +# GPIO +obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o +obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o +obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o +obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o + # LEDs support led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o led-$(CONFIG_MACH_OMAP_H3) += leds-h2p2-debug.o diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index aa8558a..5c2a0a1 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -99,7 +99,7 @@ static struct arm_idlect1_clk armper_ck = { * activation. [ GPIO code for 1510 ] */ static struct clk arm_gpio_ck = { - .name = "arm_gpio_ck", + .name = "ick", .ops = &clkops_generic, .parent = &ck_dpll1, .flags = ENABLE_ON_INIT, @@ -589,7 +589,7 @@ static struct omap_clk omap_clks[] = { CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), + CLK("omap-gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ae5f36f..0756b84 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o gpio.o omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 3ea616a..7f8ef27 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -21,7 +21,10 @@ #include #include #include +#include +#include +#include #include #include #include @@ -32,7 +35,6 @@ /* * OMAP1510 GPIO registers */ -#define OMAP1510_GPIO_BASE 0xfffce000 #define OMAP1510_GPIO_DATA_INPUT 0x00 #define OMAP1510_GPIO_DATA_OUTPUT 0x04 #define OMAP1510_GPIO_DIR_CONTROL 0x08 @@ -46,10 +48,6 @@ /* * OMAP1610 specific GPIO registers */ -#define OMAP1610_GPIO1_BASE 0xfffbe400 -#define OMAP1610_GPIO2_BASE 0xfffbec00 -#define OMAP1610_GPIO3_BASE 0xfffbb400 -#define OMAP1610_GPIO4_BASE 0xfffbbc00 #define OMAP1610_GPIO_REVISION 0x0000 #define OMAP1610_GPIO_SYSCONFIG 0x0010 #define OMAP1610_GPIO_SYSSTATUS 0x0014 @@ -71,12 +69,6 @@ /* * OMAP7XX specific GPIO registers */ -#define OMAP7XX_GPIO1_BASE 0xfffbc000 -#define OMAP7XX_GPIO2_BASE 0xfffbc800 -#define OMAP7XX_GPIO3_BASE 0xfffbd000 -#define OMAP7XX_GPIO4_BASE 0xfffbd800 -#define OMAP7XX_GPIO5_BASE 0xfffbe000 -#define OMAP7XX_GPIO6_BASE 0xfffbe800 #define OMAP7XX_GPIO_DATA_INPUT 0x00 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 #define OMAP7XX_GPIO_DIR_CONTROL 0x08 @@ -84,22 +76,6 @@ #define OMAP7XX_GPIO_INT_MASK 0x10 #define OMAP7XX_GPIO_INT_STATUS 0x14 -#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE - -/* - * omap24xx specific GPIO registers - */ -#define OMAP242X_GPIO1_BASE 0x48018000 -#define OMAP242X_GPIO2_BASE 0x4801a000 -#define OMAP242X_GPIO3_BASE 0x4801c000 -#define OMAP242X_GPIO4_BASE 0x4801e000 - -#define OMAP243X_GPIO1_BASE 0x4900C000 -#define OMAP243X_GPIO2_BASE 0x4900E000 -#define OMAP243X_GPIO3_BASE 0x49010000 -#define OMAP243X_GPIO4_BASE 0x49012000 -#define OMAP243X_GPIO5_BASE 0x480B6000 - #define OMAP24XX_GPIO_REVISION 0x0000 #define OMAP24XX_GPIO_SYSCONFIG 0x0010 #define OMAP24XX_GPIO_SYSSTATUS 0x0014 @@ -159,26 +135,6 @@ #define OMAP4_GPIO_SETWKUENA 0x0184 #define OMAP4_GPIO_CLEARDATAOUT 0x0190 #define OMAP4_GPIO_SETDATAOUT 0x0194 -/* - * omap34xx specific GPIO registers - */ - -#define OMAP34XX_GPIO1_BASE 0x48310000 -#define OMAP34XX_GPIO2_BASE 0x49050000 -#define OMAP34XX_GPIO3_BASE 0x49052000 -#define OMAP34XX_GPIO4_BASE 0x49054000 -#define OMAP34XX_GPIO5_BASE 0x49056000 -#define OMAP34XX_GPIO6_BASE 0x49058000 - -/* - * OMAP44XX specific GPIO registers - */ -#define OMAP44XX_GPIO1_BASE 0x4a310000 -#define OMAP44XX_GPIO2_BASE 0x48055000 -#define OMAP44XX_GPIO3_BASE 0x48057000 -#define OMAP44XX_GPIO4_BASE 0x48059000 -#define OMAP44XX_GPIO5_BASE 0x4805B000 -#define OMAP44XX_GPIO6_BASE 0x4805D000 struct gpio_bank { unsigned long pbase; @@ -203,102 +159,11 @@ struct gpio_bank { struct clk *dbck; u32 mod_usage; u32 dbck_enable_mask; + struct device *dev; + bool dbck_flag; }; -#define METHOD_MPUIO 0 -#define METHOD_GPIO_1510 1 -#define METHOD_GPIO_1610 2 -#define METHOD_GPIO_7XX 3 -#define METHOD_GPIO_24XX 5 -#define METHOD_GPIO_44XX 6 - -#ifdef CONFIG_ARCH_OMAP16XX -static struct gpio_bank gpio_bank_1610[5] = { - { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, - METHOD_MPUIO }, - { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_1610 }, - { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, - METHOD_GPIO_1610 }, - { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, - METHOD_GPIO_1610 }, - { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, - METHOD_GPIO_1610 }, -}; -#endif - -#ifdef CONFIG_ARCH_OMAP15XX -static struct gpio_bank gpio_bank_1510[2] = { - { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, - METHOD_MPUIO }, - { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_1510 } -}; -#endif - -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -static struct gpio_bank gpio_bank_7xx[7] = { - { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, - METHOD_MPUIO }, - { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_7XX }, - { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, - METHOD_GPIO_7XX }, - { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, - METHOD_GPIO_7XX }, - { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, - METHOD_GPIO_7XX }, - { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, - METHOD_GPIO_7XX }, - { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, - METHOD_GPIO_7XX }, -}; -#endif - -#ifdef CONFIG_ARCH_OMAP2 - -static struct gpio_bank gpio_bank_242x[4] = { - { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_24XX }, - { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, - METHOD_GPIO_24XX }, - { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, - METHOD_GPIO_24XX }, - { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, - METHOD_GPIO_24XX }, -}; - -static struct gpio_bank gpio_bank_243x[5] = { - { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_24XX }, - { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, - METHOD_GPIO_24XX }, - { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, - METHOD_GPIO_24XX }, - { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, - METHOD_GPIO_24XX }, - { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, - METHOD_GPIO_24XX }, -}; - -#endif - #ifdef CONFIG_ARCH_OMAP3 -static struct gpio_bank gpio_bank_34xx[6] = { - { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_24XX }, - { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, - METHOD_GPIO_24XX }, - { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, - METHOD_GPIO_24XX }, - { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, - METHOD_GPIO_24XX }, - { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, - METHOD_GPIO_24XX }, - { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, - METHOD_GPIO_24XX }, -}; - struct omap3_gpio_regs { u32 sysconfig; u32 irqenable1; @@ -316,26 +181,16 @@ struct omap3_gpio_regs { static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; #endif -#ifdef CONFIG_ARCH_OMAP4 -static struct gpio_bank gpio_bank_44xx[6] = { - { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, - METHOD_GPIO_44XX }, - { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, - METHOD_GPIO_44XX }, - { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, - METHOD_GPIO_44XX }, - { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, - METHOD_GPIO_44XX }, - { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, - METHOD_GPIO_44XX }, - { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, - METHOD_GPIO_44XX }, -}; +/* + * TODO: Cleanup gpio_bank usage as it is having information + * related to all instances of the device + */ +static struct gpio_bank *gpio_bank; -#endif +static int gpio_bank_width; -static struct gpio_bank *gpio_bank; -static int gpio_bank_count; +/* TODO: Analyze removing gpio_bank_count usage from driver code */ +int gpio_bank_count; static inline struct gpio_bank *get_gpio_bank(int gpio) { @@ -638,6 +493,9 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, u32 val; u32 l; + if (!bank->dbck_flag) + return; + if (debounce < 32) debounce = 0x01; else if (debounce > 7936) @@ -647,7 +505,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, l = 1 << get_gpio_index(gpio); - if (cpu_is_omap44xx()) + if (bank->method == METHOD_GPIO_44XX) reg += OMAP4_GPIO_DEBOUNCINGTIME; else reg += OMAP24XX_GPIO_DEBOUNCE_VAL; @@ -655,21 +513,28 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, __raw_writel(debounce, reg); reg = bank->base; - if (cpu_is_omap44xx()) + if (bank->method == METHOD_GPIO_44XX) reg += OMAP4_GPIO_DEBOUNCENABLE; else reg += OMAP24XX_GPIO_DEBOUNCE_EN; val = __raw_readl(reg); + if (!bank->dbck) { + struct platform_device *pdev = to_platform_device(bank->dev); + struct omap_device *odev = to_omap_device(pdev); + if (odev->hwmods[0]->opt_clks->_clk) + bank->dbck = odev->hwmods[0]->opt_clks->_clk; + if (IS_ERR(bank->dbck)) + dev_err(bank->dev, "Could not get gpio dbck\n"); + } + if (debounce) { val |= l; - if (cpu_is_omap34xx() || cpu_is_omap44xx()) - clk_enable(bank->dbck); + clk_enable(bank->dbck); } else { val &= ~l; - if (cpu_is_omap34xx() || cpu_is_omap44xx()) - clk_disable(bank->dbck); + clk_disable(bank->dbck); } bank->dbck_enable_mask = val; @@ -1536,7 +1401,8 @@ static struct platform_device omap_mpuio_device = { static inline void mpuio_init(void) { - platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); + struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0)); + platform_set_drvdata(&omap_mpuio_device, bank); if (platform_driver_register(&omap_mpuio_driver) == 0) (void) platform_device_register(&omap_mpuio_device); @@ -1669,24 +1535,6 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset) /*---------------------------------------------------------------------*/ -static int initialized; -#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) -static struct clk * gpio_ick; -#endif - -#if defined(CONFIG_ARCH_OMAP2) -static struct clk * gpio_fck; -#endif - -#if defined(CONFIG_ARCH_OMAP2430) -static struct clk * gpio5_ick; -static struct clk * gpio5_fck; -#endif - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; -#endif - static void __init omap_gpio_show_rev(void) { u32 rev; @@ -1709,6 +1557,18 @@ static void __init omap_gpio_show_rev(void) */ static struct lock_class_key gpio_lock_class; +static inline int init_gpio_info(struct platform_device *pdev) +{ + /* TODO: Analyze removing gpio_bank_count usage from driver code */ + gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), + GFP_KERNEL); + if (!gpio_bank) { + dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); + return -ENOMEM; + } + return 0; +} + static void omap_gpio_mod_init(struct gpio_bank *bank, int id) { if (cpu_class_is_omap2()) { @@ -1775,16 +1635,9 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id) static void __init omap_gpio_chip_init(struct gpio_bank *bank) { - int j, gpio_bank_bits = 16; + int j; static int gpio; - if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) - gpio_bank_bits = 32; /* 7xx has 32-bit GPIOs */ - - if ((bank->method == METHOD_GPIO_24XX) || - (bank->method == METHOD_GPIO_44XX)) - gpio_bank_bits = 32; - bank->mod_usage = 0; /* REVISIT eventually switch from OMAP-specific gpio structs * over to the generic ones @@ -1806,14 +1659,14 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) } else { bank->chip.label = "gpio"; bank->chip.base = gpio; - gpio += gpio_bank_bits; + gpio += gpio_bank_width; } - bank->chip.ngpio = gpio_bank_bits; + bank->chip.ngpio = gpio_bank_width; gpiochip_add(&bank->chip); for (j = bank->virtual_irq_start; - j < bank->virtual_irq_start + gpio_bank_bits; j++) { + j < bank->virtual_irq_start + gpio_bank_width; j++) { lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); set_irq_chip_data(j, bank); if (bank_is_mpuio(bank)) @@ -1827,140 +1680,68 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) set_irq_data(bank->irq, bank); } -static int __init _omap_gpio_init(void) +static int __devinit omap_gpio_probe(struct platform_device *pdev) { - int i; - int gpio = 0; + static int gpio_init_done; + struct omap_gpio_platform_data *pdata; + int id; struct gpio_bank *bank; - int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ - char clk_name[11]; + struct resource *res; - initialized = 1; + if (!pdev || !pdev->dev.platform_data) + return -EINVAL; -#if defined(CONFIG_ARCH_OMAP1) - if (cpu_is_omap15xx()) { - gpio_ick = clk_get(NULL, "arm_gpio_ck"); - if (IS_ERR(gpio_ick)) - printk("Could not get arm_gpio_ck\n"); - else - clk_enable(gpio_ick); - } -#endif -#if defined(CONFIG_ARCH_OMAP2) - if (cpu_class_is_omap2()) { - gpio_ick = clk_get(NULL, "gpios_ick"); - if (IS_ERR(gpio_ick)) - printk("Could not get gpios_ick\n"); - else - clk_enable(gpio_ick); - gpio_fck = clk_get(NULL, "gpios_fck"); - if (IS_ERR(gpio_fck)) - printk("Could not get gpios_fck\n"); - else - clk_enable(gpio_fck); + pdata = pdev->dev.platform_data; - /* - * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK - */ -#if defined(CONFIG_ARCH_OMAP2430) - if (cpu_is_omap2430()) { - gpio5_ick = clk_get(NULL, "gpio5_ick"); - if (IS_ERR(gpio5_ick)) - printk("Could not get gpio5_ick\n"); - else - clk_enable(gpio5_ick); - gpio5_fck = clk_get(NULL, "gpio5_fck"); - if (IS_ERR(gpio5_fck)) - printk("Could not get gpio5_fck\n"); - else - clk_enable(gpio5_fck); - } -#endif - } -#endif + if (!gpio_init_done) { + int ret; -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { - sprintf(clk_name, "gpio%d_ick", i + 1); - gpio_iclks[i] = clk_get(NULL, clk_name); - if (IS_ERR(gpio_iclks[i])) - printk(KERN_ERR "Could not get %s\n", clk_name); - else - clk_enable(gpio_iclks[i]); - } + gpio_bank_width = pdata->gpio_attr->gpio_bank_width; + ret = init_gpio_info(pdev); + if (ret) + return ret; } -#endif + id = pdev->id; + bank = &gpio_bank[id]; -#ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap15xx()) { - gpio_bank_count = 2; - gpio_bank = gpio_bank_1510; - bank_size = SZ_2K; - } -#endif -#if defined(CONFIG_ARCH_OMAP16XX) - if (cpu_is_omap16xx()) { - gpio_bank_count = 5; - gpio_bank = gpio_bank_1610; - bank_size = SZ_2K; - } -#endif -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - if (cpu_is_omap7xx()) { - gpio_bank_count = 7; - gpio_bank = gpio_bank_7xx; - bank_size = SZ_2K; - } -#endif -#ifdef CONFIG_ARCH_OMAP2 - if (cpu_is_omap242x()) { - gpio_bank_count = 4; - gpio_bank = gpio_bank_242x; - } - if (cpu_is_omap243x()) { - gpio_bank_count = 5; - gpio_bank = gpio_bank_243x; - } -#endif -#ifdef CONFIG_ARCH_OMAP3 - if (cpu_is_omap34xx()) { - gpio_bank_count = OMAP34XX_NR_GPIOS; - gpio_bank = gpio_bank_34xx; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (unlikely(!res)) { + dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); + return -ENODEV; } -#endif -#ifdef CONFIG_ARCH_OMAP4 - if (cpu_is_omap44xx()) { - gpio_bank_count = OMAP34XX_NR_GPIOS; - gpio_bank = gpio_bank_44xx; + bank->irq = res->start; + bank->virtual_irq_start = pdata->virtual_irq_start; + bank->method = pdata->bank_type; + bank->dev = &pdev->dev; + bank->dbck_flag = pdata->gpio_attr->dbck_flag; + + spin_lock_init(&bank->lock); + + /* Static mapping, never released */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (unlikely(!res)) { + dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); + return -ENODEV; } -#endif - for (i = 0; i < gpio_bank_count; i++) { - bank = &gpio_bank[i]; - spin_lock_init(&bank->lock); + bank->base = ioremap(res->start, resource_size(res)); + if (!bank->base) { + dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); + return -ENOMEM; + } - /* Static mapping, never released */ - bank->base = ioremap(bank->pbase, bank_size); - if (!bank->base) { - printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); - continue; - } + pm_runtime_enable(bank->dev); + pm_runtime_get_sync(bank->dev); - omap_gpio_mod_init(bank, i); - omap_gpio_chip_init(bank); + omap_gpio_mod_init(bank, id); + omap_gpio_chip_init(bank); - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - sprintf(clk_name, "gpio%d_dbck", i + 1); - bank->dbck = clk_get(NULL, clk_name); - if (IS_ERR(bank->dbck)) - printk(KERN_ERR "Could not get %s\n", clk_name); - } + if (!gpio_init_done) { + omap_gpio_show_rev(); + gpio_init_done = 1; } - omap_gpio_show_rev(); - return 0; } @@ -2310,25 +2091,34 @@ void omap_gpio_restore_context(void) } #endif +static struct platform_driver omap_gpio_driver = { + .probe = omap_gpio_probe, + .driver = { + .name = "omap-gpio", + }, +}; + /* - * This may get called early from board specific init - * for boards that have interrupts routed via FPGA. + * gpio driver register needs to be done before + * machine_init functions access gpio APIs. + * Hence omap_gpio_drv_reg() is a postcore_initcall. */ +static int __init omap_gpio_drv_reg(void) +{ + return platform_driver_register(&omap_gpio_driver); +} +postcore_initcall(omap_gpio_drv_reg); + +/* TODO: Remove omap_gpio_init() and its usage from board files */ int __init omap_gpio_init(void) { - if (!initialized) - return _omap_gpio_init(); - else - return 0; + return 0; } static int __init omap_gpio_sysinit(void) { int ret = 0; - if (!initialized) - ret = _omap_gpio_init(); - mpuio_init(); #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 212ce22..b7adc5a 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -91,6 +91,9 @@ struct omap_gpio_platform_data { struct omap_gpio_dev_attr *gpio_attr; }; +/* TODO: Analyze removing gpio_bank_count usage from driver code */ +extern int gpio_bank_count; + extern int omap_gpio_init(void); /* Call from board init only */ extern void omap2_gpio_prepare_for_idle(int power_state); extern void omap2_gpio_resume_after_idle(void); From patchwork Sat May 1 17:38:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shishkin X-Patchwork-Id: 96292 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o41HfJ17030043 for ; Sat, 1 May 2010 17:41:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754123Ab0EARlS (ORCPT ); Sat, 1 May 2010 13:41:18 -0400 Received: from smtp.nokia.com ([192.100.105.134]:44762 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751501Ab0EARlR (ORCPT ); Sat, 1 May 2010 13:41:17 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o41Hf8I7021641; Sat, 1 May 2010 12:41:11 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Sat, 1 May 2010 20:41:08 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Sat, 1 May 2010 20:41:08 +0300 Received: from trapdoor (esdhcp040182.research.nokia.com [172.21.40.182]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o41Hf7Rj027833 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Sat, 1 May 2010 20:41:07 +0300 Received: from ash by trapdoor with local (Exim 4.71) (envelope-from ) id 1O8GgW-0001Bm-KP; Sat, 01 May 2010 20:41:00 +0300 From: virtuoso@slind.org To: tony@atomide.com Cc: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, r-woodruff2@ti.com, Alexander Shishkin Subject: [PATCH 3/6] etm: do a dummy read from OSSRR during initialization Date: Sat, 1 May 2010 20:38:18 +0300 Message-Id: <1272735501-2963-4-git-send-email-virtuoso@slind.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1272735501-2963-1-git-send-email-virtuoso@slind.org> References: <1272735501-2963-1-git-send-email-virtuoso@slind.org> X-OriginalArrivalTime: 01 May 2010 17:41:08.0197 (UTC) FILETIME=[7B33E150:01CAE955] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 01 May 2010 17:41:21 +0000 (UTC) diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index d08062b..73b824a 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -558,7 +558,9 @@ static int __init etm_probe(struct amba_device *dev, struct amba_id *id) t->etm_portsz = 1; etm_unlock(t); - ret = etm_readl(t, ETMMR_PDSR); + (void)etm_readl(t, ETMMR_PDSR); + /* dummy first read */ + (void)etm_readl(&tracer, ETMMR_OSSRR); t->ncmppairs = etm_readl(t, ETMR_CONFCODE) & 0xf; etm_writel(t, 0x440, ETMR_CTRL); From patchwork Tue Jun 22 15:01:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 107414 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5MF1jm5017872 for ; Tue, 22 Jun 2010 15:01:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758808Ab0FVPBp (ORCPT ); Tue, 22 Jun 2010 11:01:45 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33365 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758559Ab0FVPB3 (ORCPT ); Tue, 22 Jun 2010 11:01:29 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5MF1OTq031361 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 22 Jun 2010 10:01:26 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5MF1IZn026711; Tue, 22 Jun 2010 20:31:21 +0530 (IST) From: Charulatha V To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, tony@atomide.com, rnayak@ti.com, p-basak2@ti.com, b-cousson@ti.com, Charulatha V Subject: [PATCH:v4 07/13] OMAP: GPIO: add GPIO hwmods structures for OMAP3 Date: Tue, 22 Jun 2010 20:31:50 +0530 Message-Id: <1277218916-15213-8-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1277218916-15213-7-git-send-email-charu@ti.com> References: <1277218916-15213-1-git-send-email-charu@ti.com> <1277218916-15213-2-git-send-email-charu@ti.com> <1277218916-15213-3-git-send-email-charu@ti.com> <1277218916-15213-4-git-send-email-charu@ti.com> <1277218916-15213-5-git-send-email-charu@ti.com> <1277218916-15213-6-git-send-email-charu@ti.com> <1277218916-15213-7-git-send-email-charu@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 22 Jun 2010 15:01:46 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index fe92b5d..d454ee1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -82,6 +83,12 @@ static struct omap_hwmod omap3xxx_l3_hwmod = { }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; +static struct omap_hwmod omap3xxx_gpio1_hwmod; +static struct omap_hwmod omap3xxx_gpio2_hwmod; +static struct omap_hwmod omap3xxx_gpio3_hwmod; +static struct omap_hwmod omap3xxx_gpio4_hwmod; +static struct omap_hwmod omap3xxx_gpio5_hwmod; +static struct omap_hwmod omap3xxx_gpio6_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -90,6 +97,114 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 WKUP -> GPIO1 interface */ +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = OMAP34XX_GPIO1_BASE, + .pa_end = OMAP34XX_GPIO1_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .clk = "gpio1_ick", + .addr = omap3xxx_gpio1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO2 interface */ +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = OMAP34XX_GPIO2_BASE, + .pa_end = OMAP34XX_GPIO2_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .clk = "gpio2_ick", + .addr = omap3xxx_gpio2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO3 interface */ +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = OMAP34XX_GPIO3_BASE, + .pa_end = OMAP34XX_GPIO3_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .clk = "gpio3_ick", + .addr = omap3xxx_gpio3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO4 interface */ +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = OMAP34XX_GPIO4_BASE, + .pa_end = OMAP34XX_GPIO4_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .clk = "gpio4_ick", + .addr = omap3xxx_gpio4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO5 interface */ +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = OMAP34XX_GPIO5_BASE, + .pa_end = OMAP34XX_GPIO5_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap3xxx_gpio5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> GPIO6 interface */ +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = OMAP34XX_GPIO6_BASE, + .pa_end = OMAP34XX_GPIO6_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .clk = "gpio6_ick", + .addr = omap3xxx_gpio6_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3__l4_core, @@ -208,6 +323,251 @@ static struct omap_hwmod omap3xxx_iva2_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* GPIO common */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .gpio_bank_width = 32, + .dbck_flag = true, +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap3xxx_gpio_sysc, + .rev = 1, +}; + +/* GPIO1 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK1 }, +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { + &omap3xxx_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap3xxx_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap3xxx_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), + .main_clk = NULL, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = 3, + }, + }, + .slaves = omap3xxx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO2 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK2 }, +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { + &omap3xxx_l4_per__gpio2, +}; + +static struct omap_hwmod omap3xxx_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap3xxx_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), + .main_clk = NULL, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = 13, + }, + }, + .slaves = omap3xxx_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO3 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK3 }, +}; + +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { + &omap3xxx_l4_per__gpio3, +}; + +static struct omap_hwmod omap3xxx_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap3xxx_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), + .main_clk = NULL, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = 14, + }, + }, + .slaves = omap3xxx_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO4 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK4 }, +}; + +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { + &omap3xxx_l4_per__gpio4, +}; + +static struct omap_hwmod omap3xxx_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap3xxx_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), + .main_clk = NULL, + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = 15, + }, + }, + .slaves = omap3xxx_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + + +/* GPIO5 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK5 }, +}; + +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { + &omap3xxx_l4_per__gpio5, +}; + +static struct omap_hwmod omap3xxx_gpio5_hwmod = { + .name = "gpio5", + .mpu_irqs = omap3xxx_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), + .main_clk = NULL, + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO5_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = 16, + }, + }, + .slaves = omap3xxx_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* GPIO6 */ + +static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { + { .name = "gpio_mpu_irq", .irq = INT_34XX_GPIO_BANK6 }, +}; + +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { + &omap3xxx_l4_per__gpio6, +}; + +static struct omap_hwmod omap3xxx_gpio6_hwmod = { + .name = "gpio6", + .mpu_irqs = omap3xxx_gpio6_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), + .main_clk = NULL, + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = 17, + }, + }, + .slaves = omap3xxx_gpio6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_hwmod, &omap3xxx_l4_core_hwmod, @@ -215,6 +575,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva2_hwmod, + &omap3xxx_gpio1_hwmod, + &omap3xxx_gpio2_hwmod, + &omap3xxx_gpio3_hwmod, + &omap3xxx_gpio4_hwmod, + &omap3xxx_gpio5_hwmod, + &omap3xxx_gpio6_hwmod, NULL, }; From patchwork Sat May 1 17:38:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shishkin X-Patchwork-Id: 96294 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o41HfMwd030048 for ; Sat, 1 May 2010 17:41:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756548Ab0EARlW (ORCPT ); Sat, 1 May 2010 13:41:22 -0400 Received: from smtp.nokia.com ([192.100.105.134]:44777 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755764Ab0EARlV (ORCPT ); Sat, 1 May 2010 13:41:21 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o41Hf0HG021635; Sat, 1 May 2010 12:41:16 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Sat, 1 May 2010 20:41:07 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Sat, 1 May 2010 20:41:06 +0300 Received: from trapdoor (esdhcp040182.research.nokia.com [172.21.40.182]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o41Hf5tm030677 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Sat, 1 May 2010 20:41:05 +0300 Received: from ash by trapdoor with local (Exim 4.71) (envelope-from ) id 1O8GgU-0001Bf-I7; Sat, 01 May 2010 20:40:58 +0300 From: virtuoso@slind.org To: tony@atomide.com Cc: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, r-woodruff2@ti.com, Alexander Shishkin Subject: [PATCH 2/6] coresight: cosmetic fixes Date: Sat, 1 May 2010 20:38:17 +0300 Message-Id: <1272735501-2963-3-git-send-email-virtuoso@slind.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1272735501-2963-1-git-send-email-virtuoso@slind.org> References: <1272735501-2963-1-git-send-email-virtuoso@slind.org> X-OriginalArrivalTime: 01 May 2010 17:41:06.0994 (UTC) FILETIME=[7A7C5120:01CAE955] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 01 May 2010 17:41:25 +0000 (UTC) diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index d846051..7ecd793 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -100,10 +100,10 @@ /* ETM status register, "ETM Architecture", 3.3.2 */ #define ETMR_STATUS (0x10) -#define ETMST_OVERFLOW (1 << 0) -#define ETMST_PROGBIT (1 << 1) -#define ETMST_STARTSTOP (1 << 2) -#define ETMST_TRIGGER (1 << 3) +#define ETMST_OVERFLOW BIT(0) +#define ETMST_PROGBIT BIT(1) +#define ETMST_STARTSTOP BIT(2) +#define ETMST_TRIGGER BIT(3) #define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT) #define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP) @@ -111,7 +111,7 @@ #define ETMR_TRACEENCTRL2 0x1c #define ETMR_TRACEENCTRL 0x24 -#define ETMTE_INCLEXCL (1 << 24) +#define ETMTE_INCLEXCL BIT(24) #define ETMR_TRACEENEVT 0x20 #define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ ETMCTRL_DATA_DO_ADDR | \ @@ -134,12 +134,12 @@ #define ETBR_CTRL 0x20 #define ETBR_FORMATTERCTRL 0x304 #define ETBFF_ENFTC 1 -#define ETBFF_ENFCONT (1 << 1) -#define ETBFF_FONFLIN (1 << 4) -#define ETBFF_MANUAL_FLUSH (1 << 6) -#define ETBFF_TRIGIN (1 << 8) -#define ETBFF_TRIGEVT (1 << 9) -#define ETBFF_TRIGFL (1 << 10) +#define ETBFF_ENFCONT BIT(1) +#define ETBFF_FONFLIN BIT(4) +#define ETBFF_MANUAL_FLUSH BIT(6) +#define ETBFF_TRIGIN BIT(8) +#define ETBFF_TRIGEVT BIT(9) +#define ETBFF_TRIGFL BIT(10) #define etb_writel(t, v, x) \ (__raw_writel((v), (t)->etb_regs + (x))) From patchwork Thu Jun 17 05:12:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nagarajan, Rajkumar" X-Patchwork-Id: 106610 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5H5Cftt023008 for ; Thu, 17 Jun 2010 05:12:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752174Ab0FQFMY (ORCPT ); Thu, 17 Jun 2010 01:12:24 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:40806 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751065Ab0FQFMX convert rfc822-to-8bit (ORCPT ); Thu, 17 Jun 2010 01:12:23 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5H5CK55031700 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 17 Jun 2010 00:12:22 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5H5CJRQ007155 for ; Thu, 17 Jun 2010 10:42:19 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Thu, 17 Jun 2010 10:42:19 +0530 From: "Nagarajan, Rajkumar" To: "linux-omap@vger.kernel.org" Date: Thu, 17 Jun 2010 10:42:18 +0530 Subject: [PATCH] OMAP: DSS: Fix for dsi_pll to dpll4 clk switch Thread-Topic: [PATCH] OMAP: DSS: Fix for dsi_pll to dpll4 clk switch Thread-Index: AcsN3KFTH1TMfQNTQKKa6PBLc7N3wg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 05:12:42 +0000 (UTC) diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c index 960e977..5d778d6 100644 --- a/drivers/video/omap2/dss/dpi.c +++ b/drivers/video/omap2/dss/dpi.c @@ -214,10 +214,15 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev) #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); + dispc_go(OMAP_DSS_CHANNEL_LCD); + while (dispc_go_busy(OMAP_DSS_CHANNEL_LCD)) + ; dsi_pll_uninit(); dss_clk_disable(DSS_CLK_FCK2); #endif + dispc_enable_channel(OMAP_DSS_CHANNEL_LCD, 0); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); if (cpu_is_omap34xx()) From patchwork Wed May 19 22:10:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kanigeri, Hari" X-Patchwork-Id: 101087 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4JM4HDS004425 for ; Wed, 19 May 2010 22:04:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751394Ab0ESWER (ORCPT ); Wed, 19 May 2010 18:04:17 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:57070 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751359Ab0ESWEQ (ORCPT ); Wed, 19 May 2010 18:04:16 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4JM4Fn6015976 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 19 May 2010 17:04:15 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4JM4ErM014310; Wed, 19 May 2010 17:04:14 -0500 (CDT) Received: from localhost (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o4JM4EP12106; Wed, 19 May 2010 17:04:14 -0500 (CDT) From: Hari Kanigeri To: Paul Walmsley , Linux Omap Cc: Hari Kanigeri Subject: [PATCH] omap:hwmod-remove prm header from prm-regbits-xxxx headers Date: Wed, 19 May 2010 17:10:29 -0500 Message-Id: <1274307029-22032-1-git-send-email-h-kanigeri2@ti.com> X-Mailer: git-send-email 1.7.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 19 May 2010 22:04:17 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 667633c..88cc9ca 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -26,6 +26,7 @@ #include "omap_hwmod_common_data.h" #include "cm.h" +#include "prm.h" #include "prm-regbits-44xx.h" /* Base offset for all OMAP4 interrupts external to MPUSS */ diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 4002051..fd763b5 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -14,7 +14,6 @@ * published by the Free Software Foundation. */ -#include "prm.h" /* Bits shared between registers */ diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 8f21bae..ef7fd5e 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -14,7 +14,6 @@ * published by the Free Software Foundation. */ -#include "prm.h" /* Shared register bits */ diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 597be4a..ef7af7e 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -22,7 +22,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H -#include "prm.h" /* From patchwork Wed Mar 17 22:46:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ville.syrjala@nokia.com X-Patchwork-Id: 86566 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2HMkkJ3022397 for ; Wed, 17 Mar 2010 22:46:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756232Ab0CQWqo (ORCPT ); Wed, 17 Mar 2010 18:46:44 -0400 Received: from smtp.nokia.com ([192.100.122.233]:28622 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756226Ab0CQWqn (ORCPT ); Wed, 17 Mar 2010 18:46:43 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2HMkAN4030525; Thu, 18 Mar 2010 00:46:41 +0200 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:40 +0200 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:40 +0200 Received: from stinkpad (esdhcp04093.research.nokia.com [172.21.40.93]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with SMTP id o2HMkbJ8014864; Thu, 18 Mar 2010 00:46:37 +0200 Received: by stinkpad (sSMTP sendmail emulation); Thu, 18 Mar 2010 00:46:37 +0200 From: ville.syrjala@nokia.com To: "Tomi Valkeinen" Cc: "Imre Deak" , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Subject: [PATCH v4 3/8] DSS2: OMAPFB: Skip unnecessary set_overlay_info() Date: Thu, 18 Mar 2010 00:46:18 +0200 Message-Id: <1268865983-16270-4-git-send-email-ville.syrjala@nokia.com> X-Mailer: git-send-email 1.6.4.4 In-Reply-To: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> References: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> MIME-Version: 1.0 X-OriginalArrivalTime: 17 Mar 2010 22:46:40.0274 (UTC) FILETIME=[B5621720:01CAC623] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Mar 2010 22:46:47 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h index cd54fdb..c9866be 100644 --- a/drivers/video/omap2/omapfb/omapfb.h +++ b/drivers/video/omap2/omapfb/omapfb.h @@ -148,6 +148,8 @@ static inline int omapfb_overlay_enable(struct omap_overlay *ovl, struct omap_overlay_info info; ovl->get_overlay_info(ovl, &info); + if (info.enabled == enable) + return 0; info.enabled = enable; return ovl->set_overlay_info(ovl, &info); } From patchwork Sat May 1 17:38:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shishkin X-Patchwork-Id: 96295 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o41HfMwe030048 for ; Sat, 1 May 2010 17:41:27 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756799Ab0EARlY (ORCPT ); Sat, 1 May 2010 13:41:24 -0400 Received: from smtp.nokia.com ([192.100.105.134]:44780 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756345Ab0EARlW (ORCPT ); Sat, 1 May 2010 13:41:22 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o41Hf0HJ021635; Sat, 1 May 2010 12:41:17 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Sat, 1 May 2010 20:41:10 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Sat, 1 May 2010 20:41:10 +0300 Received: from trapdoor (esdhcp040182.research.nokia.com [172.21.40.182]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o41Hf8oH030696 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Sat, 1 May 2010 20:41:08 +0300 Received: from ash by trapdoor with local (Exim 4.71) (envelope-from ) id 1O8GgX-0001Bs-Kt; Sat, 01 May 2010 20:41:01 +0300 From: virtuoso@slind.org To: tony@atomide.com Cc: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, r-woodruff2@ti.com, Alexander Shishkin Subject: [PATCH 4/6] omap3: move EMU peripheral addresses to a platform header Date: Sat, 1 May 2010 20:38:19 +0300 Message-Id: <1272735501-2963-5-git-send-email-virtuoso@slind.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1272735501-2963-1-git-send-email-virtuoso@slind.org> References: <1272735501-2963-1-git-send-email-virtuoso@slind.org> X-OriginalArrivalTime: 01 May 2010 17:41:10.0375 (UTC) FILETIME=[7C803770:01CAE955] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 01 May 2010 17:41:27 +0000 (UTC) diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c index 9c442e2..6b41745 100644 --- a/arch/arm/mach-omap2/emu.c +++ b/arch/arm/mach-omap2/emu.c @@ -24,19 +24,13 @@ MODULE_LICENSE("GPL"); MODULE_AUTHOR("Alexander Shishkin"); -/* Cortex CoreSight components within omap3xxx EMU */ -#define ETM_BASE (L4_EMU_34XX_PHYS + 0x10000) -#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000) -#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000) -#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000) - static struct amba_device omap3_etb_device = { .dev = { .init_name = "etb", }, .res = { - .start = ETB_BASE, - .end = ETB_BASE + SZ_4K - 1, + .start = OMAP34XX_ETB_PHYS, + .end = OMAP34XX_ETB_PHYS + OMAP34XX_ETB_SIZE - 1, .flags = IORESOURCE_MEM, }, .periphid = 0x000bb907, @@ -47,8 +41,8 @@ static struct amba_device omap3_etm_device = { .init_name = "etm", }, .res = { - .start = ETM_BASE, - .end = ETM_BASE + SZ_4K - 1, + .start = OMAP34XX_ETM_PHYS, + .end = OMAP34XX_ETM_PHYS + OMAP34XX_ETM_SIZE - 1, .flags = IORESOURCE_MEM, }, .periphid = 0x102bb921, diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index 128b549..81f736a 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -185,6 +185,26 @@ /* 3430 IVA - currently unmapped */ +#define OMAP34XX_DBG_OFFSET (0x00011000) +#define OMAP34XX_DBG_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DBG_OFFSET) +#define OMAP34XX_DBG_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DBG_OFFSET) +#define OMAP34XX_DBG_SIZE SZ_4K + +#define OMAP34XX_ETM_OFFSET (0x00010000) +#define OMAP34XX_ETM_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETM_OFFSET) +#define OMAP34XX_ETM_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETM_OFFSET) +#define OMAP34XX_ETM_SIZE SZ_4K + +#define OMAP34XX_ETB_OFFSET (0x0001b000) +#define OMAP34XX_ETB_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETB_OFFSET) +#define OMAP34XX_ETB_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETB_OFFSET) +#define OMAP34XX_ETB_SIZE SZ_4K + +#define OMAP34XX_DAP_OFFSET (0x0001d000) +#define OMAP34XX_DAP_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DAP_OFFSET) +#define OMAP34XX_DAP_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DAP_OFFSET) +#define OMAP34XX_DAP_SIZE SZ_4K + /* * ---------------------------------------------------------------------------- * Omap4 specific IO mapping From patchwork Fri Apr 30 14:43:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 95884 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3UGoavf002285 for ; Fri, 30 Apr 2010 16:50:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757075Ab0D3Qss (ORCPT ); Fri, 30 Apr 2010 12:48:48 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:38440 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757556Ab0D3Qsn (ORCPT ); Fri, 30 Apr 2010 12:48:43 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3UEhYsE022357 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 30 Apr 2010 09:43:34 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3UEhTDG021405; Fri, 30 Apr 2010 09:43:30 -0500 (CDT) Received: from 10.24.255.18 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Fri, 30 Apr 2010 20:13:31 +0530 (IST) Message-ID: <12046.10.24.255.18.1272638611.squirrel@dbdmail.itg.ti.com> Date: Fri, 30 Apr 2010 20:13:31 +0530 (IST) Subject: [RFC] [PATCH 1/2] CMA3000 Accelerometer Driver From: "Hemanth V" To: linux-input@vger.kernel.org, linux-omap@vger.kernel.org Cc: Ossi.Kauppinen@vti.fi, hemanthv@ti.com User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 30 Apr 2010 16:50:49 +0000 (UTC) diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 16ec523..4752a00 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -319,4 +319,13 @@ config INPUT_PCAP To compile this driver as a module, choose M here: the module will be called pcap_keys. +config INPUT_CMA3000_I2C + tristate "VTI CMA3000 Tri-axis accelerometer" + depends on I2C + help + Say Y here if you want to use VTI CMA3000 Accelerometer + through I2C interface. + + To compile this driver as a module, choose M here: the + module will be called cma3000_dxx endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index a8b8485..94d6eda 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -30,4 +30,4 @@ obj-$(CONFIG_INPUT_WINBOND_CIR) += winbond-cir.o obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o - +obj-$(CONFIG_INPUT_CMA3000_I2C) += cma3000_d0x_i2c.o cma3000_d0x.o diff --git a/drivers/input/misc/cma3000_d0x.c b/drivers/input/misc/cma3000_d0x.c new file mode 100644 index 0000000..c0d0ea1 --- /dev/null +++ b/drivers/input/misc/cma3000_d0x.c @@ -0,0 +1,627 @@ +/* + * cma3000_d0x.c + * VTI CMA3000_D0x Accelerometer driver + * Supports I2C/SPI interfaces + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#include "cma3000_d0x.h" + +#define CMA3000_WHOAMI 0x00 +#define CMA3000_REVID 0x01 +#define CMA3000_CTRL 0x02 +#define CMA3000_STATUS 0x03 +#define CMA3000_RSTR 0x04 +#define CMA3000_INTSTATUS 0x05 +#define CMA3000_DOUTX 0x06 +#define CMA3000_DOUTY 0x07 +#define CMA3000_DOUTZ 0x08 +#define CMA3000_MDTHR 0x09 +#define CMA3000_MDFFTMR 0x0A +#define CMA3000_FFTHR 0x0B + +#define CMA3000_RANGE2G (1 << 7) +#define CMA3000_RANGE8G (0 << 7) +#define CMA3000_MODEMASK (7 << 1) +#define CMA3000_GRANGEMASK (1 << 7) + +#define CMA3000_STATUS_PERR 1 +#define CMA3000_INTSTATUS_FFDET (1 << 2) + +/* Settling time delay in ms */ +#define CMA3000_SETDELAY 30 + +/* Delay for clearing interrupt in us */ +#define CMA3000_INTDELAY 44 + + +/* + * Bit weights in mg for each of the seven bits, + * eight bit is the sign bit + */ +static int bit_to_2g[7] = {18, 36, 71, 143, 286, 571, 1142}; +static int bit_to_8g[7] = {71, 143, 286, 571, 1142, 2286, 4571}; + +/* + * Conversion for each of the eight modes to g, depending + * on G range i.e 2G or 8G + */ + +static int *mode_to_mg[8][2] = { + {NULL, NULL }, + {bit_to_8g, bit_to_2g}, + {bit_to_8g, bit_to_2g}, + {bit_to_8g, bit_to_8g}, + {bit_to_8g, bit_to_8g}, + {bit_to_8g, bit_to_2g}, + {bit_to_8g, bit_to_2g}, + {NULL, NULL }, +}; + +static ssize_t cma3000_show_attr_mode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + uint8_t mode; + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_CTRL, "ctrl"); + ret = sprintf(buf, "%d\n", (mode & CMA3000_MODEMASK) >> 1); + return ret; +} + +static ssize_t cma3000_store_attr_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + uint8_t ctrl; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + if (val < CMAMODE_DEFAULT || val > CMAMODE_POFF) + return -EINVAL; + + mutex_lock(&data->mutex); + val &= (CMA3000_MODEMASK >> 1); + ctrl = cma3000_read(data, CMA3000_CTRL, "ctrl"); + ctrl &= ~CMA3000_MODEMASK; + ctrl |= (val << 1); + + data->pdata.mode = val; + + disable_irq(data->client->irq); + cma3000_set(data, CMA3000_CTRL, ctrl, "ctrl"); + + /* Settling time delay required after mode change */ + msleep(CMA3000_SETDELAY); + + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + return count; +} + +static ssize_t cma3000_show_attr_grange(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + uint8_t mode; + int g_range; + + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_CTRL, "ctrl"); + g_range = (mode & CMA3000_GRANGEMASK) ? CMARANGE_2G : CMARANGE_8G; + ret = sprintf(buf, "%d\n", g_range); + + return ret; +} + +static ssize_t cma3000_store_attr_grange(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error, g_range, fuzz_x, fuzz_y, fuzz_z; + uint8_t ctrl; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + mutex_lock(&data->mutex); + ctrl = cma3000_read(data, CMA3000_CTRL, "ctrl"); + ctrl &= ~CMA3000_GRANGEMASK; + + if (val == CMARANGE_2G) { + ctrl |= CMA3000_RANGE2G; + data->pdata.g_range = CMARANGE_2G; + } else if (val == CMARANGE_8G) { + ctrl |= CMA3000_RANGE8G; + data->pdata.g_range = CMARANGE_8G; + } else { + error = -EINVAL; + goto err_op_failed; + } + + g_range = data->pdata.g_range; + fuzz_x = data->pdata.fuzz_x; + fuzz_y = data->pdata.fuzz_y; + fuzz_z = data->pdata.fuzz_z; + + disable_irq(data->client->irq); + cma3000_set(data, CMA3000_CTRL, ctrl, "ctrl"); + + input_set_abs_params(data->input_dev, ABS_X, -g_range, + g_range, fuzz_x, 0); + input_set_abs_params(data->input_dev, ABS_Y, -g_range, + g_range, fuzz_y, 0); + input_set_abs_params(data->input_dev, ABS_Z, -g_range, + g_range, fuzz_z, 0); + + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + return count; + +err_op_failed: + mutex_unlock(&data->mutex); + return error; +} + +static ssize_t cma3000_show_attr_mdthr(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + uint8_t mode; + + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_MDTHR, "mdthr"); + ret = sprintf(buf, "%d\n", mode); + + return ret; +} + +static ssize_t cma3000_store_attr_mdthr(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + mutex_lock(&data->mutex); + data->pdata.mdthr = val; + + disable_irq(data->client->irq); + cma3000_set(data, CMA3000_MDTHR, val, "mdthr"); + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + return count; +} + +static ssize_t cma3000_show_attr_mdfftmr(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + uint8_t mode; + + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_MDFFTMR, "mdfftmr"); + ret = sprintf(buf, "%d\n", mode); + + return ret; +} + +static ssize_t cma3000_store_attr_mdfftmr(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + mutex_lock(&data->mutex); + data->pdata.mdfftmr = val; + + disable_irq(data->client->irq); + cma3000_set(data, CMA3000_MDFFTMR, val, "mdthr"); + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + return count; +} + +static ssize_t cma3000_show_attr_ffthr(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + uint8_t mode; + + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + + mode = cma3000_read(data, CMA3000_FFTHR, "ffthr"); + ret = sprintf(buf, "%d\n", mode); + + return ret; +} + +static ssize_t cma3000_store_attr_ffthr(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct cma3000_accl_data *data = platform_get_drvdata(pdev); + unsigned long val; + int error; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + mutex_lock(&data->mutex); + data->pdata.ffthr = val; + + disable_irq(data->client->irq); + cma3000_set(data, CMA3000_FFTHR, val, "mdthr"); + enable_irq(data->client->irq); + mutex_unlock(&data->mutex); + + return count; +} + +static DEVICE_ATTR(mode, S_IWUSR | S_IRUGO, + cma3000_show_attr_mode, cma3000_store_attr_mode); + +static DEVICE_ATTR(grange, S_IWUSR | S_IRUGO, + cma3000_show_attr_grange, cma3000_store_attr_grange); + +static DEVICE_ATTR(mdthr, S_IWUSR | S_IRUGO, + cma3000_show_attr_mdthr, cma3000_store_attr_mdthr); + +static DEVICE_ATTR(mdfftmr, S_IWUSR | S_IRUGO, + cma3000_show_attr_mdfftmr, cma3000_store_attr_mdfftmr); + +static DEVICE_ATTR(ffthr, S_IWUSR | S_IRUGO, + cma3000_show_attr_ffthr, cma3000_store_attr_ffthr); + + +static struct attribute *cma_attrs[] = { + &dev_attr_mode.attr, + &dev_attr_grange.attr, + &dev_attr_mdthr.attr, + &dev_attr_mdfftmr.attr, + &dev_attr_ffthr.attr, + NULL, +}; + +static struct attribute_group cma3000_attr_group = { + .attrs = cma_attrs, +}; + +static void cma3000_create_sysfs(struct cma3000_accl_data *data) +{ + int ret; + ret = sysfs_create_group(&data->client->dev.kobj, &cma3000_attr_group); + if (ret) + dev_err(&data->client->dev, + "failed to create sysfs entries\n"); + +} + +static void cma3000_remove_sysfs(struct cma3000_accl_data *data) +{ + sysfs_remove_group(&data->client->dev.kobj, &cma3000_attr_group); +} + +static void decode_mg(struct cma3000_accl_data *data, int *datax, + int *datay, int *dataz) +{ + int i, tmpx = 0, tmpy = 0, tmpz = 0; + + for (i = 0; i < 7; ++i) { + tmpx += (((*datax) & BIT(i)) >> i) * (data->bit_to_mg[i]); + tmpy += (((*datay) & BIT(i)) >> i) * (data->bit_to_mg[i]); + tmpz += (((*dataz) & BIT(i)) >> i) * (data->bit_to_mg[i]); + + } + + if ((*datax) & BIT(7)) + *datax = -tmpx; + else + *datax = tmpx; + + if ((*datay) & BIT(7)) + *datay = -tmpy; + else + *datay = tmpy; + + if ((*dataz) & BIT(7)) + *dataz = -tmpz; + else + *dataz = tmpz; +} + +static irqreturn_t cma3000_thread_irq(int irq, void *dev_id) +{ + struct cma3000_accl_data *data = dev_id; + int datax, datay, dataz; + u8 ctrl, mode, range, intr_status; + + intr_status = cma3000_read(data, CMA3000_INTSTATUS, "interrupt status"); + + /* Check if free fall is detected, report immediately */ + if (intr_status & CMA3000_INTSTATUS_FFDET) { + input_report_abs(data->input_dev, ABS_MISC, 1); + input_sync(data->input_dev); + } else { + input_report_abs(data->input_dev, ABS_MISC, 0); + } + + + /* Delay required between each read for interrupt clearing */ + datax = cma3000_read(data, CMA3000_DOUTX, "X"); + udelay(CMA3000_INTDELAY); + datay = cma3000_read(data, CMA3000_DOUTY, "Y"); + udelay(CMA3000_INTDELAY); + dataz = cma3000_read(data, CMA3000_DOUTZ, "Z"); + + ctrl = cma3000_read(data, CMA3000_CTRL, "ctrl"); + mode = (ctrl & CMA3000_MODEMASK) >> 1; + range = (ctrl & CMA3000_GRANGEMASK) >> 7; + + data->bit_to_mg = mode_to_mg[mode][range]; + + /* Interrupt not for this device */ + if (data->bit_to_mg == NULL) + return IRQ_NONE; + + /* Decode register values to milli g */ + decode_mg(data, &datax, &datay, &dataz); + + input_report_abs(data->input_dev, ABS_X, datax); + input_report_abs(data->input_dev, ABS_Y, datay); + input_report_abs(data->input_dev, ABS_Z, dataz); + input_sync(data->input_dev); + + return IRQ_HANDLED; +} + +static int cma3000_reset(struct cma3000_accl_data *data) +{ + int ret; + + /* Reset sequence */ + cma3000_set(data, CMA3000_RSTR, 0x02, "Reset"); + cma3000_set(data, CMA3000_RSTR, 0x0A, "Reset"); + cma3000_set(data, CMA3000_RSTR, 0x04, "Reset"); + + /* Settling time delay */ + mdelay(10); + + ret = cma3000_read(data, CMA3000_STATUS, "Status"); + if ((ret < 0) || (ret & CMA3000_STATUS_PERR)) { + dev_err(&data->client->dev, "Reset failed\n"); + return -EIO; + } + + return 0; +} + +int cma3000_poweron(struct cma3000_accl_data *data) +{ + uint8_t ctrl = 0, mdthr, mdfftmr, ffthr, mode; + int g_range, ret; + + g_range = data->pdata.g_range; + mode = data->pdata.mode; + mdthr = data->pdata.mdthr; + mdfftmr = data->pdata.mdfftmr; + ffthr = data->pdata.ffthr; + + if (mode < CMAMODE_DEFAULT || mode > CMAMODE_POFF) { + data->pdata.mode = CMAMODE_MOTDET; + mode = data->pdata.mode; + dev_info(&data->client->dev, + "Invalid mode specified, assuming Motion Detect\n"); + } + + if (g_range == CMARANGE_2G) { + ctrl = (mode << 1) | CMA3000_RANGE2G; + } else if (g_range == CMARANGE_8G) { + ctrl = (mode << 1) | CMA3000_RANGE8G; + } else { + dev_info(&data->client->dev, + "Invalid G range specified, assuming 8G\n"); + ctrl = (mode << 1) | CMA3000_RANGE8G; + data->pdata.g_range = CMARANGE_8G; + } + + + cma3000_set(data, CMA3000_MDTHR, mdthr, "Motion Detect Threshold"); + cma3000_set(data, CMA3000_MDFFTMR, mdfftmr, "Time register"); + cma3000_set(data, CMA3000_FFTHR, ffthr, "Free fall threshold"); + ret = cma3000_set(data, CMA3000_CTRL, ctrl, "Mode setting"); + if (ret < 0) + return -EIO; + + mdelay(CMA3000_SETDELAY); + + return 0; +} + +int cma3000_poweroff(struct cma3000_accl_data *data) +{ + int ret; + + ret = cma3000_set(data, CMA3000_CTRL, CMAMODE_POFF, "Mode setting"); + mdelay(CMA3000_SETDELAY); + + return ret; +} + +int cma3000_init(struct cma3000_accl_data *data) +{ + int ret = 0, fuzz_x, fuzz_y, fuzz_z, g_range; + uint32_t irqflags; + + if (data->client->dev.platform_data == NULL) { + dev_err(&data->client->dev, "platform data not found \n"); + goto err_op2_failed; + } + + memcpy(&(data->pdata), data->client->dev.platform_data, + sizeof(struct cma3000_platform_data)); + + ret = cma3000_reset(data); + if (ret) + goto err_op2_failed; + + ret = cma3000_read(data, CMA3000_REVID, "Revid"); + if (ret < 0) + goto err_op2_failed; + + pr_info("CMA3000 Acclerometer : Revision %x\n", ret); + + /* Bring it out of default power down state */ + ret = cma3000_poweron(data); + if (ret < 0) + goto err_op2_failed; + + fuzz_x = data->pdata.fuzz_x; + fuzz_y = data->pdata.fuzz_y; + fuzz_z = data->pdata.fuzz_z; + g_range = data->pdata.g_range; + irqflags = data->pdata.irqflags; + + data->input_dev = input_allocate_device(); + if (data->input_dev == NULL) { + ret = -ENOMEM; + dev_err(&data->client->dev, + "Failed to allocate input device\n"); + goto err_op2_failed; + } + + data->input_dev->name = "cma3000-acclerometer"; + +#ifdef CONFIG_INPUT_CMA3000_I2C + data->input_dev->id.bustype = BUS_I2C; +#endif + + __set_bit(EV_ABS, data->input_dev->evbit); + __set_bit(EV_MSC, data->input_dev->evbit); + + input_set_abs_params(data->input_dev, ABS_X, -g_range, + g_range, fuzz_x, 0); + input_set_abs_params(data->input_dev, ABS_Y, -g_range, + g_range, fuzz_y, 0); + input_set_abs_params(data->input_dev, ABS_Z, -g_range, + g_range, fuzz_z, 0); + input_set_abs_params(data->input_dev, ABS_MISC, 0, + 1, 0, 0); + + ret = input_register_device(data->input_dev); + if (ret) { + dev_err(&data->client->dev, + "Unable to register input device\n"); + goto err_op2_failed; + } + + mutex_init(&data->mutex); + + if (data->client->irq) { + ret = request_threaded_irq(data->client->irq, NULL, + cma3000_thread_irq, + irqflags | IRQF_ONESHOT, + data->client->name, data); + + if (ret < 0) { + dev_err(&data->client->dev, + "request_threaded_irq failed\n"); + goto err_op1_failed; + } + } + + cma3000_create_sysfs(data); + + return 0; + +err_op1_failed: + mutex_destroy(&data->mutex); + input_unregister_device(data->input_dev); +err_op2_failed: + if (data != NULL) { + if (data->input_dev != NULL) + input_free_device(data->input_dev); + } + + return ret; +} + +int cma3000_exit(struct cma3000_accl_data *data) +{ + int ret; + + ret = cma3000_poweroff(data); + + if (data->client->irq) + free_irq(data->client->irq, data); + + mutex_destroy(&data->mutex); + input_unregister_device(data->input_dev); + input_free_device(data->input_dev); + cma3000_remove_sysfs(data); + + return ret; +} diff --git a/drivers/input/misc/cma3000_d0x.h b/drivers/input/misc/cma3000_d0x.h new file mode 100644 index 0000000..906d29e --- /dev/null +++ b/drivers/input/misc/cma3000_d0x.h @@ -0,0 +1,46 @@ +/* + * cma3000_d0x.h + * VTI CMA3000_D0x Accelerometer driver + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef INPUT_CMA3000_H +#define INPUT_CMA3000_H + +#include +#include + +struct cma3000_accl_data { +#ifdef CONFIG_INPUT_CMA3000_I2C + struct i2c_client *client; +#endif + struct input_dev *input_dev; + struct cma3000_platform_data pdata; + + /* mutex for sysfs operations */ + struct mutex mutex; + int *bit_to_mg; +}; + +int cma3000_set(struct cma3000_accl_data *, u8, u8, char *); +int cma3000_read(struct cma3000_accl_data *, u8, char *); +int cma3000_init(struct cma3000_accl_data *); +int cma3000_exit(struct cma3000_accl_data *); +int cma3000_poweron(struct cma3000_accl_data *); +int cma3000_poweroff(struct cma3000_accl_data *); + +#endif diff --git a/drivers/input/misc/cma3000_d0x_i2c.c b/drivers/input/misc/cma3000_d0x_i2c.c new file mode 100644 index 0000000..d2ad638 --- /dev/null +++ b/drivers/input/misc/cma3000_d0x_i2c.c @@ -0,0 +1,136 @@ +/* + * cma3000_d0x_i2c.c + * + * Implements I2C interface for VTI CMA300_D0x Accelerometer driver + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include "cma3000_d0x.h" + +int cma3000_set(struct cma3000_accl_data *accl, u8 reg, u8 val, char *msg) +{ + int ret = i2c_smbus_write_byte_data(accl->client, reg, val); + if (ret < 0) + dev_err(&accl->client->dev, + "i2c_smbus_write_byte_data failed (%s)\n", msg); + return ret; +} + +int cma3000_read(struct cma3000_accl_data *accl, u8 reg, char *msg) +{ + int ret = i2c_smbus_read_byte_data(accl->client, reg); + if (ret < 0) + dev_err(&accl->client->dev, + "i2c_smbus_read_byte_data failed (%s)\n", msg); + return ret; +} + +static int __devinit cma3000_accl_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + struct cma3000_accl_data *data = NULL; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (data == NULL) { + ret = -ENOMEM; + goto err_op_failed; + } + + data->client = client; + i2c_set_clientdata(client, data); + + ret = cma3000_init(data); + if (ret) + goto err_op_failed; + + return 0; + +err_op_failed: + + if (data != NULL) + kfree(data); + + return ret; +} + +static int __devexit cma3000_accl_remove(struct i2c_client *client) +{ + struct cma3000_accl_data *data = i2c_get_clientdata(client); + int ret; + + ret = cma3000_exit(data); + i2c_set_clientdata(client, NULL); + kfree(data); + + return ret; +} + +#ifdef CONFIG_PM +static int cma3000_accl_suspend(struct i2c_client *client, pm_message_t mesg) +{ + struct cma3000_accl_data *data = i2c_get_clientdata(client); + + return cma3000_poweroff(data); +} + +static int cma3000_accl_resume(struct i2c_client *client) +{ + struct cma3000_accl_data *data = i2c_get_clientdata(client); + + return cma3000_poweron(data); +} +#endif + +static const struct i2c_device_id cma3000_id[] = { + { "cma3000_accl", 0 }, + { }, +}; + +static struct i2c_driver cma3000_accl_driver = { + .probe = cma3000_accl_probe, + .remove = cma3000_accl_remove, + .id_table = cma3000_id, +#ifdef CONFIG_PM + .suspend = cma3000_accl_suspend, + .resume = cma3000_accl_resume, +#endif + .driver = { + .name = "cma3000_accl" + }, +}; + +static int __init cma3000_accl_init(void) +{ + + return i2c_add_driver(&cma3000_accl_driver); +} + +static void __exit cma3000_accl_exit(void) +{ + i2c_del_driver(&cma3000_accl_driver); +} + +module_init(cma3000_accl_init); +module_exit(cma3000_accl_exit); + +MODULE_DESCRIPTION("CMA3000-D0x Accelerometer Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Hemanth V "); diff --git a/include/linux/i2c/cma3000.h b/include/linux/i2c/cma3000.h new file mode 100644 index 0000000..50aa3fc --- /dev/null +++ b/include/linux/i2c/cma3000.h @@ -0,0 +1,60 @@ +/* + * cma3000.h + * VTI CMA300_Dxx Accelerometer driver + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef _LINUX_CMA3000_I2C_H +#define _LINUX_CMA3000_I2C_H + +#define CMAMODE_DEFAULT 0 +#define CMAMODE_MEAS100 1 +#define CMAMODE_MEAS400 2 +#define CMAMODE_MEAS40 3 +#define CMAMODE_MOTDET 4 +#define CMAMODE_FF100 5 +#define CMAMODE_FF400 6 +#define CMAMODE_POFF 7 + +#define CMARANGE_2G 2000 +#define CMARANGE_8G 8000 + +/** + * struct cma3000_i2c_platform_data - CMA3000 Platform data + * @fuzz_x: Noise on X Axis + * @fuzz_y: Noise on Y Axis + * @fuzz_z: Noise on Z Axis + * @g_range: G range in milli g i.e 2000 or 8000 + * @mode: Operating mode + * @mdthr: Motion detect threshold value + * @mdfftmr: Motion detect and free fall time value + * @ffthr: Free fall threshold value + */ + +struct cma3000_platform_data { + int fuzz_x; + int fuzz_y; + int fuzz_z; + int g_range; + uint8_t mode; + uint8_t mdthr; + uint8_t mdfftmr; + uint8_t ffthr; + uint32_t irqflags; +}; + +#endif From patchwork Tue Jun 15 08:07:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 106163 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5F87tke016279 for ; Tue, 15 Jun 2010 08:07:55 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753543Ab0FOIHx (ORCPT ); Tue, 15 Jun 2010 04:07:53 -0400 Received: from mail-vw0-f46.google.com ([209.85.212.46]:49011 "EHLO mail-vw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753142Ab0FOIHv (ORCPT ); Tue, 15 Jun 2010 04:07:51 -0400 Received: by vws13 with SMTP id 13so931652vws.19 for ; Tue, 15 Jun 2010 01:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=Qy+yi5svNY8/4SHncNRh+S9zurkqcKbYz6ZYaBh7TvM=; b=xcS/On0HpYZ9nFZLGMg/3Cp1lHWyRodq5iGbMhNLYAp7Ggg+zgW8xHBKAyZ+CzHHin bLgZr+9YjbNA2HJBoe9EQHkqgPQcaNlaGrJIcsVTmiuyNz5V62ymuJFQkaDiY+3kDNE/ TR1WRO9jWL1U3vqxPZipX37x5K8e5QN8Pqgyk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=YtOhCjuYlkCojDXAhonPHX3mwBYciUpBvoDHgEhCMxN+2sVN+luGA5sPpAjAse1WYR wWIu5/NNqCWkXwlSlTaKXqprcI9Kz+DO6R/ewy5ks77bUWKSnaH96m2dqFTzUWTivtiv 9dkF/iHQZxDcXKpfDp1XSngzKOSfMfRYJ9wQs= MIME-Version: 1.0 Received: by 10.220.122.13 with SMTP id j13mr3781429vcr.270.1276589270038; Tue, 15 Jun 2010 01:07:50 -0700 (PDT) Received: by 10.220.159.131 with HTTP; Tue, 15 Jun 2010 01:07:49 -0700 (PDT) In-Reply-To: References: <003b01cad0f0$6ea78040$544ff780@am.dhcp.ti.com> <20100406163211.GA29117@nokia.com> <4BBB6767.7010202@ti.com> <20100406165720.GA17916@nokia.com> <00b401cad5e0$1d1868d0$544ff780@am.dhcp.ti.com> <4BBBC628.9030207@ti.com> <00c901cad5e7$9de54350$544ff780@am.dhcp.ti.com> <4BBBD87C.1040307@ti.com> <003601cad73c$98c3aa50$544ff780@am.dhcp.ti.com> <008f01cae1b2$6262c970$544ff780@am.dhcp.ti.com> Date: Tue, 15 Jun 2010 13:37:49 +0530 Message-ID: Subject: [PATCH v5] OMAP: Fix for bus width which improves SD card's peformance. From: kishore kadiyala To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: Madhusudhan , akpm@linux-foundation.org, tony@atomide.com, Nishanth Menon , felipe.balbi@nokia.com, Vimal Singh , "S, Venkatraman" , "Lavinen Jarkko (Nokia-D/Helsinki)" Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 15 Jun 2010 08:08:04 +0000 (UTC) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b032828..a0c8515 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2096,10 +2096,23 @@ static int __init omap_hsmmc_probe(struct mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; - if (mmc_slot(host).wires >= 8) + switch (mmc_slot(host).wires) { + case 8: mmc->caps |= MMC_CAP_8_BIT_DATA; - else if (mmc_slot(host).wires >= 4) + /* Fall through */ + case 4: mmc->caps |= MMC_CAP_4_BIT_DATA; + break; + case 1: + /* Nothing to crib here */ + case 0: + /* Assuming nothing was given by board, Core use's 1-Bit */ + break; + default: + /* Completely unexpected.. Core goes with 1-Bit Width */ + dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!" + "using 1 instead\n", mmc_slot(host).wires); + } if (mmc_slot(host).nonremovable) mmc->caps |= MMC_CAP_NONREMOVABLE; From patchwork Tue May 18 12:55:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gadiyar X-Patchwork-Id: 100477 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4ICtSKg008255 for ; Tue, 18 May 2010 12:55:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757241Ab0ERMz0 (ORCPT ); Tue, 18 May 2010 08:55:26 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:57003 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757198Ab0ERMz0 (ORCPT ); Tue, 18 May 2010 08:55:26 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4ICtM27031994 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 18 May 2010 07:55:25 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4ICtLVr011595; Tue, 18 May 2010 18:25:21 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o4ICtLYM003930; Tue, 18 May 2010 18:25:21 +0530 Received: (from a0393673@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o4ICtLZA003928; Tue, 18 May 2010 18:25:21 +0530 From: Anand Gadiyar To: linux-omap@vger.kernel.org Cc: Anand Gadiyar Subject: [PATCH] omap: trivial: checkpatch cleanups to board files Date: Tue, 18 May 2010 18:25:20 +0530 Message-Id: <1274187320-3900-1-git-send-email-gadiyar@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 18 May 2010 12:55:28 +0000 (UTC) Index: linux-omap-2.6/arch/arm/mach-omap2/board-am3517evm.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/board-am3517evm.c +++ linux-omap-2.6/arch/arm/mach-omap2/board-am3517evm.c @@ -287,7 +287,7 @@ static struct omap_dss_device am3517_evm .type = OMAP_DISPLAY_TYPE_DPI, .name = "lcd", .driver_name = "sharp_lq_panel", - .phy.dpi.data_lines = 16, + .phy.dpi.data_lines = 16, .platform_enable = am3517_evm_panel_enable_lcd, .platform_disable = am3517_evm_panel_disable_lcd, }; @@ -302,8 +302,8 @@ static void am3517_evm_panel_disable_tv( } static struct omap_dss_device am3517_evm_tv_device = { - .type = OMAP_DISPLAY_TYPE_VENC, - .name = "tv", + .type = OMAP_DISPLAY_TYPE_VENC, + .name = "tv", .driver_name = "venc", .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, .platform_enable = am3517_evm_panel_enable_tv, Index: linux-omap-2.6/arch/arm/mach-omap2/board-apollon.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/board-apollon.c +++ linux-omap-2.6/arch/arm/mach-omap2/board-apollon.c @@ -326,7 +326,7 @@ static void __init omap_apollon_init(voi omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); /* - * Make sure the serial ports are muxed on at this point. + * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on * if not needed. */ Index: linux-omap-2.6/arch/arm/mach-omap2/board-h4.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/board-h4.c +++ linux-omap-2.6/arch/arm/mach-omap2/board-h4.c @@ -138,11 +138,11 @@ static struct platform_device h4_flash_d static struct omap_kp_platform_data h4_kp_data = { .rows = 6, .cols = 7, - .keymap = h4_keymap, - .keymapsize = ARRAY_SIZE(h4_keymap), + .keymap = h4_keymap, + .keymapsize = ARRAY_SIZE(h4_keymap), .rep = 1, - .row_gpios = row_gpios, - .col_gpios = col_gpios, + .row_gpios = row_gpios, + .col_gpios = col_gpios, }; static struct platform_device h4_kp_device = { @@ -260,7 +260,7 @@ static void __init h4_init_flash(void) unsigned long base; if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) { - printk("Can't request GPMC CS for flash\n"); + printk(KERN_ERR "Can't request GPMC CS for flash\n"); return; } h4_flash_resource.start = base; Index: linux-omap-2.6/arch/arm/mach-omap2/board-igep0020.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/board-igep0020.c +++ linux-omap-2.6/arch/arm/mach-omap2/board-igep0020.c @@ -38,12 +38,12 @@ #define IGEP2_SMSC911X_CS 5 #define IGEP2_SMSC911X_GPIO 176 #define IGEP2_GPIO_USBH_NRESET 24 -#define IGEP2_GPIO_LED0_GREEN 26 -#define IGEP2_GPIO_LED0_RED 27 -#define IGEP2_GPIO_LED1_RED 28 +#define IGEP2_GPIO_LED0_GREEN 26 +#define IGEP2_GPIO_LED0_RED 27 +#define IGEP2_GPIO_LED1_RED 28 #define IGEP2_GPIO_DVI_PUP 170 -#define IGEP2_GPIO_WIFI_NPD 94 -#define IGEP2_GPIO_WIFI_NRESET 95 +#define IGEP2_GPIO_WIFI_NPD 94 +#define IGEP2_GPIO_WIFI_NRESET 95 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) @@ -518,7 +518,7 @@ static void __init igep2_init(void) if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) { gpio_export(IGEP2_GPIO_WIFI_NPD, 0); -/* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */ +/* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */ } else pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n"); Index: linux-omap-2.6/arch/arm/mach-omap2/board-ldp.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/board-ldp.c +++ linux-omap-2.6/arch/arm/mach-omap2/board-ldp.c @@ -141,7 +141,7 @@ static struct gpio_keys_button ldp_gpio_ .gpio = 104, .desc = "func 3", .active_low = 1, - .debounce_interval = 30, + .debounce_interval = 30, }, [4] = { .code = KEY_F4, Index: linux-omap-2.6/arch/arm/mach-omap2/board-rx51-peripherals.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/board-rx51-peripherals.c +++ linux-omap-2.6/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -59,7 +59,7 @@ static struct spi_board_info rx51_periph .modalias = "wl1251", .bus_num = 4, .chip_select = 0, - .max_speed_hz = 48000000, + .max_speed_hz = 48000000, .mode = SPI_MODE_3, .controller_data = &wl1251_mcspi_config, .platform_data = &wl1251_pdata, From patchwork Wed May 12 15:52:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abraham Arce X-Patchwork-Id: 99049 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4CFs69M024542 for ; Wed, 12 May 2010 15:54:06 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756716Ab0ELPwf (ORCPT ); Wed, 12 May 2010 11:52:35 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:34963 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756663Ab0ELPwd convert rfc822-to-8bit (ORCPT ); Wed, 12 May 2010 11:52:33 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4CFqWdM020649 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 12 May 2010 10:52:32 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4CFqVEo022849 for ; Wed, 12 May 2010 10:52:31 -0500 (CDT) Received: from dlee75.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4CFqVEt002429 for ; Wed, 12 May 2010 10:52:31 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dlee75.ent.ti.com ([157.170.170.72]) with mapi; Wed, 12 May 2010 10:52:31 -0500 From: "Arce, Abraham" To: "linux-omap@vger.kernel.org" Date: Wed, 12 May 2010 10:52:30 -0500 Subject: [RFC] [PATCH] OMAP: Remove compilation warnings Thread-Topic: [RFC] [PATCH] OMAP: Remove compilation warnings Thread-Index: Acrx6yDFFIrsABOgT0iYYcfqxM7Lkw== Message-ID: <27F9C60D11D683428E133F85D2BB4A53043E08FAEA@dlee03.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 12 May 2010 15:54:06 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index 8fc19ff..cf23547 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h @@ -55,7 +55,7 @@ * These can share data since they will never be present simultaneously * on the same device. */ -static struct clkdm_dep gfx_sgx_wkdeps[] = { +static __attribute__ ((unused)) struct clkdm_dep gfx_sgx_wkdeps[] = { { .clkdm_name = "core_l3_clkdm", .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 8b3d269..269449a 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -49,7 +49,7 @@ struct omap_mux_entry { struct list_head node; }; -static unsigned long mux_phys; +static __attribute__ ((unused)) unsigned long mux_phys; static void __iomem *mux_base; u16 omap_mux_read(u16 reg) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index dddc9d6..fffc7f2 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2071,7 +2071,7 @@ void omap2_gpio_prepare_for_retention(void) * IRQs will be generated. See OMAP2420 Errata item 1.101. */ for (i = 0; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l1, l2; + u32 l1 = 0, l2 = 0; if (!(bank->enabled_non_wakeup_gpios)) continue; @@ -2128,7 +2128,7 @@ void omap2_gpio_resume_after_retention(void) return; for (i = 0; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l, gen, gen0, gen1; + u32 l = 0, gen, gen0, gen1; if (!(bank->enabled_non_wakeup_gpios)) continue; From patchwork Sun May 16 15:46:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99979 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFlCUf025454 for ; Sun, 16 May 2010 15:47:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753763Ab0EPPrK (ORCPT ); Sun, 16 May 2010 11:47:10 -0400 Received: from mail-fx0-f46.google.com ([209.85.161.46]:52160 "EHLO mail-fx0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753899Ab0EPPrJ (ORCPT ); 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Sun, 16 May 2010 08:47:07 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras , Tony Lindgren Subject: [PATCH 1/5] omap: OMAP_DSP is not in mainline, remove it Date: Sun, 16 May 2010 18:46:57 +0300 Message-Id: <1274024821-21178-2-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024821-21178-1-git-send-email-felipe.contreras@gmail.com> References: <1274024821-21178-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:47:12 +0000 (UTC) diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index dc2e631..b552976 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -30,67 +30,6 @@ #include #include -#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) - -static struct dsp_platform_data dsp_pdata = { - .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list), -}; - -static struct resource omap_dsp_resources[] = { - { - .name = "dsp_mmu", - .start = -1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device omap_dsp_device = { - .name = "dsp", - .id = -1, - .num_resources = ARRAY_SIZE(omap_dsp_resources), - .resource = omap_dsp_resources, - .dev = { - .platform_data = &dsp_pdata, - }, -}; - -static inline void omap_init_dsp(void) -{ - struct resource *res; - int irq; - - if (cpu_is_omap15xx()) - irq = INT_1510_DSP_MMU; - else if (cpu_is_omap16xx()) - irq = INT_1610_DSP_MMU; - else if (cpu_is_omap24xx()) - irq = INT_24XX_DSP_MMU; - - res = platform_get_resource_byname(&omap_dsp_device, - IORESOURCE_IRQ, "dsp_mmu"); - res->start = irq; - - platform_device_register(&omap_dsp_device); -} - -int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev) -{ - static DEFINE_MUTEX(dsp_pdata_lock); - - spin_lock_init(&kdev->lock); - - mutex_lock(&dsp_pdata_lock); - list_add_tail(&kdev->entry, &dsp_pdata.kdev_list); - mutex_unlock(&dsp_pdata_lock); - - return 0; -} -EXPORT_SYMBOL(dsp_kfunc_device_register); - -#else -static inline void omap_init_dsp(void) { } -#endif /* CONFIG_OMAP_DSP */ - #if defined(CONFIG_MPU_BRIDGE) || defined(CONFIG_MPU_BRIDGE_MODULE) static unsigned long dspbridge_phys_mempool_base; @@ -410,7 +349,6 @@ static int __init omap_init_devices(void) /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - omap_init_dsp(); omap_init_kp(); omap_init_rng(); omap_init_uwire(); From patchwork Mon Jul 19 17:46:51 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: michael X-Patchwork-Id: 112728 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6JHl8Jv024580 for ; Mon, 19 Jul 2010 17:47:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933986Ab0GSRrG (ORCPT ); Mon, 19 Jul 2010 13:47:06 -0400 Received: from panicking.kicks-ass.org ([95.141.32.57]:42464 "EHLO panicking.kicks-ass.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932452Ab0GSRrF (ORCPT ); Mon, 19 Jul 2010 13:47:05 -0400 Received: from athedsl-4452745.home.otenet.gr ([79.129.225.121] helo=[192.168.1.12]) by panicking.kicks-ass.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1OauQb-0000nj-7n; Mon, 19 Jul 2010 17:46:57 +0000 Message-ID: <4C448F8B.7060908@panicking.kicks-ass.org> Date: Mon, 19 Jul 2010 19:46:51 +0200 From: Michael Trimarchi User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: Janakiram Sistla CC: Sergey Lapin , Amit Kucheria , sameo@linux.intel.com, List Linux Kernel , linux-omap@vger.kernel.org, Mikko Ylinen Subject: Re: [PATCH] mfd: twl4030: Driver for twl4030 madc module References: <1259146071-2372-1-git-send-email-amit.kucheria@verdurent.com> <48239d391001200412i7736354dg4e07076a63d7b966@mail.gmail.com> <4fb5db51001250134s19c309eax947617ae2fc26d5f@mail.gmail.com> In-Reply-To: <4fb5db51001250134s19c309eax947617ae2fc26d5f@mail.gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 19 Jul 2010 17:47:08 +0000 (UTC) diff --git a/drivers/mfd/twl4030-madc.c b/drivers/mfd/twl4030-madc.c index 2d2aa87..e12ac1a 100644 --- a/drivers/mfd/twl4030-madc.c +++ b/drivers/mfd/twl4030-madc.c @@ -478,6 +478,7 @@ static int __init twl4030_madc_probe(struct platform_device madc->imr = (pdata->irq_line == 1) ? TWL4030_MADC_IMR1 : TWL4030_MADC_IM madc->isr = (pdata->irq_line == 1) ? TWL4030_MADC_ISR1 : TWL4030_MADC_IS + madc->dev = &pdev->dev; ret = misc_register(&twl4030_madc_device); if (ret) { From patchwork Thu Apr 15 14:00:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 92755 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3FE0Br8017786 for ; Thu, 15 Apr 2010 14:01:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754146Ab0DOOAR (ORCPT ); Thu, 15 Apr 2010 10:00:17 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:46434 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753785Ab0DOOAP (ORCPT ); Thu, 15 Apr 2010 10:00:15 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3FE04x5015579 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 15 Apr 2010 09:00:06 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3FE01RI012810; Thu, 15 Apr 2010 19:30:02 +0530 (IST) From: hvaibhav@ti.com To: tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Vaibhav Hiremath Subject: [PATCH-RESEND 1/2] OMAP: LCD LS037V7DW01: Add Backlight driver support Date: Thu, 15 Apr 2010 19:30:00 +0530 Message-Id: <1271340001-19831-1-git-send-email-hvaibhav@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: References: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 15 Apr 2010 14:01:39 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c index 8d51a5e..d84feb0 100644 --- a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c +++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c @@ -20,10 +20,16 @@ #include #include #include +#include +#include #include #include +struct sharp_data { + struct backlight_device *bl; +}; + static struct omap_video_timings sharp_ls_timings = { .x_res = 480, .y_res = 640, @@ -39,18 +45,89 @@ static struct omap_video_timings sharp_ls_timings = { .vbp = 1, }; +static int sharp_ls_bl_update_status(struct backlight_device *bl) +{ + struct omap_dss_device *dssdev = dev_get_drvdata(&bl->dev); + int level; + + if (!dssdev->set_backlight) + return -EINVAL; + + if (bl->props.fb_blank == FB_BLANK_UNBLANK && + bl->props.power == FB_BLANK_UNBLANK) + level = bl->props.brightness; + else + level = 0; + + return dssdev->set_backlight(dssdev, level); +} + +static int sharp_ls_bl_get_brightness(struct backlight_device *bl) +{ + if (bl->props.fb_blank == FB_BLANK_UNBLANK && + bl->props.power == FB_BLANK_UNBLANK) + return bl->props.brightness; + + return 0; +} + +static const struct backlight_ops sharp_ls_bl_ops = { + .get_brightness = sharp_ls_bl_get_brightness, + .update_status = sharp_ls_bl_update_status, +}; + + + static int sharp_ls_panel_probe(struct omap_dss_device *dssdev) { + struct backlight_properties props; + struct backlight_device *bl; + struct sharp_data *sd; + int r; + dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS; dssdev->panel.acb = 0x28; dssdev->panel.timings = sharp_ls_timings; + sd = kzalloc(sizeof(*sd), GFP_KERNEL); + if (!sd) + return -ENOMEM; + + dev_set_drvdata(&dssdev->dev, sd); + + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = dssdev->max_backlight_level; + + bl = backlight_device_register("sharp-ls", &dssdev->dev, dssdev, + &sharp_ls_bl_ops, &props); + if (IS_ERR(bl)) { + r = PTR_ERR(bl); + kfree(sd); + return r; + } + sd->bl = bl; + + bl->props.fb_blank = FB_BLANK_UNBLANK; + bl->props.power = FB_BLANK_UNBLANK; + bl->props.brightness = dssdev->max_backlight_level; + r = sharp_ls_bl_update_status(bl); + if (r < 0) + dev_err(&dssdev->dev, "failed to set lcd brightness\n"); + return 0; } static void sharp_ls_panel_remove(struct omap_dss_device *dssdev) { + struct sharp_data *sd = dev_get_drvdata(&dssdev->dev); + struct backlight_device *bl = sd->bl; + + bl->props.power = FB_BLANK_POWERDOWN; + sharp_ls_bl_update_status(bl); + backlight_device_unregister(bl); + + kfree(sd); } static int sharp_ls_power_on(struct omap_dss_device *dssdev) From patchwork Thu Apr 15 14:00:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 92754 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3FE0Br4017786 for ; Thu, 15 Apr 2010 14:00:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754195Ab0DOOAO (ORCPT ); Thu, 15 Apr 2010 10:00:14 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59178 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754146Ab0DOOAN (ORCPT ); Thu, 15 Apr 2010 10:00:13 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3FE04gi001233 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 15 Apr 2010 09:00:07 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3FE01RJ012810; Thu, 15 Apr 2010 19:30:03 +0530 (IST) From: hvaibhav@ti.com To: tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Vaibhav Hiremath Subject: [PATCH-RESEND 2/2] OMAP: OMAP3EVM: Add LCD Backlight brightness hookup function Date: Thu, 15 Apr 2010 19:30:01 +0530 Message-Id: <1271340001-19831-2-git-send-email-hvaibhav@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: References: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 15 Apr 2010 14:00:50 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index f2a52c3..1d1956f 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -253,6 +253,38 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev) lcd_enabled = 0; } +/* + * PWMA/B register offsets (TWL4030_MODULE_PWMA) + */ +#define TWL_LED_EN 0x0 +#define TWL_LED_PWMON 0x0 +#define TWL_LED_PWMOFF 0x1 + +static int omap3evm_set_bl_intensity(struct omap_dss_device *dssdev, int level) +{ + unsigned char c; + + if (level > 100) + return -EINVAL; + /* + * Enable LEDA for backlight + */ + twl_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_EN); + + c = ((125 * (100 - level)) / 100); + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { + c += 1; + twl_i2c_write_u8(TWL4030_MODULE_PWMA, 0x7F, TWL_LED_PWMOFF); + twl_i2c_write_u8(TWL4030_MODULE_PWMA, c, TWL_LED_PWMON); + } else { + c += 2; + twl_i2c_write_u8(TWL4030_MODULE_PWMA, 0x1, TWL_LED_PWMON); + twl_i2c_write_u8(TWL4030_MODULE_PWMA, c, TWL_LED_PWMOFF); + } + + return 0; +} + static struct omap_dss_device omap3_evm_lcd_device = { .name = "lcd", .driver_name = "sharp_ls_panel", @@ -260,6 +292,8 @@ static struct omap_dss_device omap3_evm_lcd_device = { .phy.dpi.data_lines = 18, .platform_enable = omap3_evm_enable_lcd, .platform_disable = omap3_evm_disable_lcd, + .max_backlight_level = 100, + .set_backlight = omap3evm_set_bl_intensity, }; static int omap3_evm_enable_tv(struct omap_dss_device *dssdev) From patchwork Wed May 26 15:57:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julia Lawall X-Patchwork-Id: 102437 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4QFwo4K017584 for ; Wed, 26 May 2010 15:58:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756840Ab0EZP5s (ORCPT ); Wed, 26 May 2010 11:57:48 -0400 Received: from mgw1.diku.dk ([130.225.96.91]:46275 "EHLO mgw1.diku.dk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755491Ab0EZP5q (ORCPT ); Wed, 26 May 2010 11:57:46 -0400 Received: from localhost (localhost [127.0.0.1]) by mgw1.diku.dk (Postfix) with ESMTP id C26F552C555; Wed, 26 May 2010 17:57:45 +0200 (CEST) Received: from mgw1.diku.dk ([127.0.0.1]) by localhost (mgw1.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6uNPj9xI+dI3; Wed, 26 May 2010 17:57:41 +0200 (CEST) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw1.diku.dk (Postfix) with ESMTP id 730ED52C390; Wed, 26 May 2010 17:57:41 +0200 (CEST) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id A866A6DFB62; Wed, 26 May 2010 17:50:15 +0200 (CEST) Received: by ask.diku.dk (Postfix, from userid 3767) id 47B13200BF; Wed, 26 May 2010 17:57:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id 42010200BC; Wed, 26 May 2010 17:57:41 +0200 (CEST) Date: Wed, 26 May 2010 17:57:41 +0200 (CEST) From: Julia Lawall To: Tomi Valkeinen , linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH 12/17] drivers/video/omap2/displays: Add missing mutex_unlock Message-ID: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 26 May 2010 15:58:51 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c index 1f8eb70..07fbb8a 100644 --- a/drivers/video/omap2/displays/panel-acx565akm.c +++ b/drivers/video/omap2/displays/panel-acx565akm.c @@ -592,7 +592,7 @@ static int acx_panel_power_on(struct omap_dss_device *dssdev) r = omapdss_sdi_display_enable(dssdev); if (r) { pr_err("%s sdi enable failed\n", __func__); - return r; + goto fail_unlock; } /*FIXME tweak me */ @@ -633,6 +633,8 @@ static int acx_panel_power_on(struct omap_dss_device *dssdev) return acx565akm_bl_update_status(md->bl_dev); fail: omapdss_sdi_display_disable(dssdev); +fail_unlock: + mutex_unlock(&md->mutex); return r; } From patchwork Thu Apr 15 14:59:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grazvydas Ignotas X-Patchwork-Id: 92758 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3FEx7bx000538 for ; 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Thu, 15 Apr 2010 07:59:02 -0700 (PDT) Received: from localhost.localdomain (ip-88-119-226-136.static.b4net.lt [88.119.226.136]) by mx.google.com with ESMTPS id 16sm1242456bwz.5.2010.04.15.07.59.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Apr 2010 07:59:01 -0700 (PDT) From: Grazvydas Ignotas To: linux-fbdev@vger.kernel.org Cc: linux-omap@vger.kernel.org, Tomi Valkeinen , Grazvydas Ignotas Subject: [PATCH] OMAP: DSS2: TPO-TD03MTEA1: fix Kconfig dependency Date: Thu, 15 Apr 2010 17:59:03 +0300 Message-Id: <1271343543-14348-1-git-send-email-notasas@gmail.com> X-Mailer: git-send-email 1.6.3.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 15 Apr 2010 14:59:08 +0000 (UTC) diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig index dfb57ee..a2faf8a 100644 --- a/drivers/video/omap2/displays/Kconfig +++ b/drivers/video/omap2/displays/Kconfig @@ -33,7 +33,7 @@ config PANEL_TOPPOLY_TDO35S config PANEL_TPO_TD043MTEA1 tristate "TPO TD043MTEA1 LCD Panel" - depends on OMAP2_DSS && I2C + depends on OMAP2_DSS && SPI help LCD Panel used in OMAP3 Pandora From patchwork Tue Mar 2 10:29:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aggarwal, Anuj" X-Patchwork-Id: 83166 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o22ATq5X021130 for ; Tue, 2 Mar 2010 10:29:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751753Ab0CBK3w (ORCPT ); Tue, 2 Mar 2010 05:29:52 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:55200 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751546Ab0CBK3v (ORCPT ); Tue, 2 Mar 2010 05:29:51 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o22AThrB008875 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 2 Mar 2010 04:29:46 -0600 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o22AThRs028572; Tue, 2 Mar 2010 15:59:43 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o22AThMv003163; Tue, 2 Mar 2010 15:59:43 +0530 Received: (from a0393534@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o22ATgSM003160; Tue, 2 Mar 2010 15:59:43 +0530 From: Anuj Aggarwal To: tony@atomide.com Cc: linux-omap@vger.kernel.org, broonie@opensource.wolfsonmicro.com, lrg@slimlogic.co.uk, Anuj Aggarwal Subject: [PATCHv3 1/4] Regulator: OMAP: Creating TWL4030 file having supplies & init data Date: Tue, 2 Mar 2010 15:59:42 +0530 Message-Id: <1267525782-3131-1-git-send-email-anuj.aggarwal@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 02 Mar 2010 10:29:53 +0000 (UTC) diff --git a/arch/arm/mach-omap2/twl4030-pmic.c b/arch/arm/mach-omap2/twl4030-pmic.c new file mode 100644 index 0000000..0c0a860 --- /dev/null +++ b/arch/arm/mach-omap2/twl4030-pmic.c @@ -0,0 +1,175 @@ +/* + * twl4030-pmic.c + * + * Common regulator supplies and init data structs for TWL4030/TPS65950 + * PMIC for OMAP3 based EVMs. They can be used in various board-evm + * files for OMAP3 based platforms using TWL4030. + * + * Copyright (C) 2010 Texas Instrument Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include + +/* VDAC */ +struct regulator_consumer_supply twl4030_vdac_supply = { + .supply = "vdac", +}; + +/* VMMC1 */ +struct regulator_consumer_supply twl4030_vmmc1_supply = { + .supply = "vmmc", +}; + +/* VMMC2 */ +struct regulator_consumer_supply twl4030_vmmc2_supply = { + .supply = "vmmc", +}; + +/* VSIM */ +struct regulator_consumer_supply twl4030_vsim_supply = { + .supply = "vmmc_aux", +}; + +/* VPLL2 for digital video outputs */ +struct regulator_consumer_supply twl4030_vpll2_supply = { + .supply = "vdvi", +}; + +/* Regulator initialization data */ +/* VAUX1 */ +struct regulator_init_data twl4030_vaux1_data = { + .constraints = { + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VAUX2 */ +struct regulator_init_data twl4030_vaux2_data = { + .constraints = { + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VAUX3 */ +struct regulator_init_data twl4030_vaux3_data = { + .constraints = { + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VAUX4 */ +struct regulator_init_data twl4030_vaux4_data = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VMMC1 */ +struct regulator_init_data twl4030_vmmc1_data = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &twl4030_vmmc1_supply, +}; + +/* VMMC2 */ +struct regulator_init_data twl4030_vmmc2_data = { + .constraints = { + .min_uV = 1850000, + .max_uV = 1850000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &twl4030_vmmc2_supply, +}; + +/* VSIM */ +struct regulator_init_data twl4030_vsim_data = { + .constraints = { + .min_uV = 1800000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &twl4030_vsim_supply, +}; + +/* VDAC */ +struct regulator_init_data twl4030_vdac_data = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &twl4030_vdac_supply, +}; + +/* VPLL2 */ +struct regulator_init_data twl4030_vpll2_data = { + .constraints = { + .name = "VDVI", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &twl4030_vpll2_supply, +}; + diff --git a/arch/arm/mach-omap2/twl4030-pmic.h b/arch/arm/mach-omap2/twl4030-pmic.h new file mode 100644 index 0000000..7a863d6 --- /dev/null +++ b/arch/arm/mach-omap2/twl4030-pmic.h @@ -0,0 +1,34 @@ +/* + * twl4030-pmic.h + * + * Header for common regulator supplies and init data structs for + * TWL4030/TPS65950 PMIC for OMAP3 based EVMs. + * + * Copyright (C) 2010 Texas Instrument Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +extern struct regulator_consumer_supply twl4030_vdac_supply; +extern struct regulator_consumer_supply twl4030_vmmc1_supply; +extern struct regulator_consumer_supply twl4030_vmmc2_supply; +extern struct regulator_consumer_supply twl4030_vsim_supply; +extern struct regulator_consumer_supply twl4030_vpll2_supply; + +extern struct regulator_init_data twl4030_vaux1_data; +extern struct regulator_init_data twl4030_vaux2_data; +extern struct regulator_init_data twl4030_vaux3_data; +extern struct regulator_init_data twl4030_vaux4_data; +extern struct regulator_init_data twl4030_vmmc1_data; +extern struct regulator_init_data twl4030_vmmc2_data; +extern struct regulator_init_data twl4030_vsim_data; +extern struct regulator_init_data twl4030_vdac_data; +extern struct regulator_init_data twl4030_vpll2_data; + From patchwork Wed Jun 23 13:14:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ohad Ben Cohen X-Patchwork-Id: 107644 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5NDEhOr005966 for ; Wed, 23 Jun 2010 13:14:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752714Ab0FWNOY (ORCPT ); Wed, 23 Jun 2010 09:14:24 -0400 Received: from mail-fx0-f46.google.com ([209.85.161.46]:64206 "EHLO mail-fx0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752392Ab0FWNOX (ORCPT ); Wed, 23 Jun 2010 09:14:23 -0400 Received: by fxm10 with SMTP id 10so3072176fxm.19 for ; Wed, 23 Jun 2010 06:14:20 -0700 (PDT) Received: by 10.87.72.2 with SMTP id z2mr12751250fgk.29.1277298858142; Wed, 23 Jun 2010 06:14:18 -0700 (PDT) Received: from localhost.localdomain (93-173-8-42.bb.netvision.net.il [93.173.8.42]) by mx.google.com with ESMTPS id r9sm335743faq.1.2010.06.23.06.14.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 23 Jun 2010 06:14:16 -0700 (PDT) From: Ohad Ben-Cohen To: Greg KH Cc: , , Hebbar Shivananda , Ramos Falcon Ernesto , Anna Suman , Kanigeri Hari , Felipe Contreras , Felipe Balbi , Hiroshi DOYU , Gupta Ramesh , Guzman Lugo Fernando , Tony Lindgren , Ameya Palande , Gomez Castellanos Ivan , Andy Shevchenko , Armando Uribe De Leon , Deepak Chitriki , Menon Nishanth , Phil Carmody , Pitney Gilbert , Bhavin Shah , Omar Ramirez Luna , Ohad Ben-Cohen Subject: [PATCH 11/11] staging: ti dspbridge: enable driver building Date: Wed, 23 Jun 2010 16:14:00 +0300 Message-Id: <1277298840-18516-1-git-send-email-ohad@wizery.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1277298125-17991-1-git-send-email-ohad@wizery.com> References: <1277298125-17991-1-git-send-email-ohad@wizery.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 23 Jun 2010 13:15:10 +0000 (UTC) diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index cdd3ea3..ce1dfa8 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -151,5 +151,7 @@ source "drivers/staging/msm/Kconfig" source "drivers/staging/easycap/Kconfig" +source "drivers/staging/tidspbridge/Kconfig" + endif # !STAGING_EXCLUDE_BUILD endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index beceaff..7849818 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -56,3 +56,4 @@ obj-$(CONFIG_FB_XGI) += xgifb/ obj-$(CONFIG_TOUCHSCREEN_MRSTOUCH) += mrst-touchscreen/ obj-$(CONFIG_MSM_STAGING) += msm/ obj-$(CONFIG_EASYCAP) += easycap/ +obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/ diff --git a/drivers/staging/tidspbridge/Kconfig b/drivers/staging/tidspbridge/Kconfig new file mode 100644 index 0000000..37fa2b1 --- /dev/null +++ b/drivers/staging/tidspbridge/Kconfig @@ -0,0 +1,88 @@ +# +# DSP Bridge Driver Support +# + +menuconfig TIDSPBRIDGE + tristate "DSP Bridge driver" + default n + select OMAP_MBOX_FWK + help + DSP/BIOS Bridge is designed for platforms that contain a GPP and + one or more attached DSPs. The GPP is considered the master or + "host" processor, and the attached DSPs are processing resources + that can be utilized by applications and drivers running on the GPP. + + This driver depends on OMAP Mailbox (OMAP_MBOX_FWK). + +config BRIDGE_DVFS + bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)" + depends on TIDSPBRIDGE && OMAP_PM_SRF && CPU_FREQ + default n + help + DVFS allows DSP Bridge to initiate the operating point change to + scale the chip voltage and frequency in order to match the + performance and power consumption to the current processing + requirements. + +config BRIDGE_MEMPOOL_SIZE + hex "Physical memory pool size (Byte)" + depends on TIDSPBRIDGE + default 0x600000 + help + Allocate specified size of memory at booting time to avoid allocation + failure under heavy memory fragmentation after some use time. + +config BRIDGE_DEBUG + bool "DSP Bridge Debug Support" + depends on TIDSPBRIDGE + help + Say Y to enable Bridge debugging capabilities + +config BRIDGE_RECOVERY + bool "DSP Recovery Support" + depends on TIDSPBRIDGE + help + In case of DSP fatal error, BRIDGE driver will try to + recover itself. + +config BRIDGE_CACHE_LINE_CHECK + bool "Check buffers to be 128 byte aligned" + depends on TIDSPBRIDGE + default n + help + When the DSP processes data, the DSP cache controller loads 128-Byte + chunks (lines) from SDRAM and writes the data back in 128-Byte chunks. + If a DMM buffer does not start and end on a 128-Byte boundary, the data + preceding the start address (SA) from the 128-Byte boundary to the SA + and the data at addresses trailing the end address (EA) from the EA to + the next 128-Byte boundary will be loaded and written back as well. + This can lead to heap corruption. Say Y, to enforce the check for 128 + byte alignment, buffers failing this check will be rejected. + +config BRIDGE_WDT3 + bool "Enable WDT3 interruptions" + depends on TIDSPBRIDGE + default n + help + WTD3 is managed by DSP and once it is enabled, DSP side bridge is in + charge of refreshing the timer before overflow, if the DSP hangs MPU + will caught the interrupt and try to recover DSP. + +config WDT_TIMEOUT + int "DSP watchdog timer timeout (in secs)" + depends on BRIDGE_WDT3 + default 5 + help + Watchdog timer timeout value, after that time if the watchdog timer + counter is not reset the wdt overflow interrupt will be triggered + +comment "Bridge Notifications" + depends on TIDSPBRIDGE + +config BRIDGE_NTFY_PWRERR + bool "Notify DSP Power Error" + depends on TIDSPBRIDGE + help + Enable notifications to registered clients on the event of power errror + trying to suspend bridge driver. Say Y, to signal this event as a fatal + error, this will require a bridge restart to recover. diff --git a/drivers/staging/tidspbridge/Makefile b/drivers/staging/tidspbridge/Makefile new file mode 100644 index 0000000..6082ef0 --- /dev/null +++ b/drivers/staging/tidspbridge/Makefile @@ -0,0 +1,34 @@ +obj-$(CONFIG_TIDSPBRIDGE) += bridgedriver.o + +libgen = gen/gb.o gen/gs.o gen/gh.o gen/uuidutil.o +libservices = services/sync.o services/cfg.o \ + services/ntfy.o services/services.o +libcore = core/chnl_sm.o core/msg_sm.o core/io_sm.o core/tiomap3430.o \ + core/tiomap3430_pwr.o core/tiomap_io.o \ + core/mmu_fault.o core/ue_deh.o core/wdt.o core/dsp-clock.o +libpmgr = pmgr/chnl.o pmgr/io.o pmgr/msg.o pmgr/cod.o pmgr/dev.o pmgr/dspapi.o \ + pmgr/dmm.o pmgr/cmm.o pmgr/dbll.o +librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \ + rmgr/proc.o rmgr/pwr.o rmgr/rmm.o rmgr/strm.o rmgr/dspdrv.o \ + rmgr/nldr.o rmgr/drv_interface.o +libdload = dynload/cload.o dynload/getsection.o dynload/reloc.o \ + dynload/tramp.o +libhw = hw/hw_mmu.o + +bridgedriver-objs = $(libgen) $(libservices) $(libcore) $(libpmgr) $(librmgr) \ + $(libdload) $(libhw) + +#Machine dependent +ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \ + -DTICFG_PROC_VER -DTICFG_EVM_TYPE -DCHNL_SMCLASS \ + -DCHNL_MESSAGES -DUSE_LEVEL_1_MACROS + +ccflags-y += -Idrivers/staging/tidspbridge/include +ccflags-y += -Idrivers/staging/tidspbridge/services +ccflags-y += -Idrivers/staging/tidspbridge/core +ccflags-y += -Idrivers/staging/tidspbridge/pmgr +ccflags-y += -Idrivers/staging/tidspbridge/rmgr +ccflags-y += -Idrivers/staging/tidspbridge/dynload +ccflags-y += -Idrivers/staging/tidspbridge/hw +ccflags-y += -Iarch/arm + From patchwork Wed Mar 17 22:46:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ville.syrjala@nokia.com X-Patchwork-Id: 86565 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2HMkj7G022389 for ; Wed, 17 Mar 2010 22:46:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756229Ab0CQWqn (ORCPT ); Wed, 17 Mar 2010 18:46:43 -0400 Received: from smtp.nokia.com ([192.100.122.233]:28620 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756185Ab0CQWqn (ORCPT ); Wed, 17 Mar 2010 18:46:43 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2HMkAN2030525; Thu, 18 Mar 2010 00:46:40 +0200 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:34 +0200 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Mar 2010 00:46:34 +0200 Received: from stinkpad (esdhcp04093.research.nokia.com [172.21.40.93]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with SMTP id o2HMkVmt014797; Thu, 18 Mar 2010 00:46:31 +0200 Received: by stinkpad (sSMTP sendmail emulation); Thu, 18 Mar 2010 00:46:31 +0200 From: ville.syrjala@nokia.com To: "Tomi Valkeinen" Cc: "Imre Deak" , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Subject: [PATCH v4 1/8] DSS2: OMAPFB: Refactor overlay address calculations Date: Thu, 18 Mar 2010 00:46:16 +0200 Message-Id: <1268865983-16270-2-git-send-email-ville.syrjala@nokia.com> X-Mailer: git-send-email 1.6.4.4 In-Reply-To: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> References: <1268865983-16270-1-git-send-email-ville.syrjala@nokia.com> MIME-Version: 1.0 X-OriginalArrivalTime: 17 Mar 2010 22:46:34.0294 (UTC) FILETIME=[B1D19D60:01CAC623] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Mar 2010 22:46:45 +0000 (UTC) diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 4a76917..ea619a9 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -821,6 +821,40 @@ static unsigned calc_rotation_offset_vrfb(const struct fb_var_screeninfo *var, return offset; } +static void omapfb_calc_addr(const struct omapfb_info *ofbi, + const struct fb_var_screeninfo *var, + const struct fb_fix_screeninfo *fix, + int rotation, u32 *paddr, void __iomem **vaddr) +{ + u32 data_start_p; + void __iomem *data_start_v; + int offset; + + if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { + data_start_p = omapfb_get_region_rot_paddr(ofbi, rotation); + data_start_v = NULL; + } else { + data_start_p = omapfb_get_region_paddr(ofbi); + data_start_v = omapfb_get_region_vaddr(ofbi); + } + + if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) + offset = calc_rotation_offset_vrfb(var, fix, rotation); + else + offset = calc_rotation_offset_dma(var, fix, rotation); + + data_start_p += offset; + data_start_v += offset; + + if (offset) + DBG("offset %d, %d = %d\n", + var->xoffset, var->yoffset, offset); + + DBG("paddr %x, vaddr %p\n", data_start_p, data_start_v); + + *paddr = data_start_p; + *vaddr = data_start_v; +} /* setup overlay according to the fb */ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl, @@ -831,9 +865,8 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl, struct fb_var_screeninfo *var = &fbi->var; struct fb_fix_screeninfo *fix = &fbi->fix; enum omap_color_mode mode = 0; - int offset; - u32 data_start_p; - void __iomem *data_start_v; + u32 data_start_p = 0; + void __iomem *data_start_v = NULL; struct omap_overlay_info info; int xres, yres; int screen_width; @@ -860,28 +893,8 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl, yres = var->yres; } - - if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { - data_start_p = omapfb_get_region_rot_paddr(ofbi, rotation); - data_start_v = NULL; - } else { - data_start_p = omapfb_get_region_paddr(ofbi); - data_start_v = omapfb_get_region_vaddr(ofbi); - } - - if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) - offset = calc_rotation_offset_vrfb(var, fix, rotation); - else - offset = calc_rotation_offset_dma(var, fix, rotation); - - data_start_p += offset; - data_start_v += offset; - - if (offset) - DBG("offset %d, %d = %d\n", - var->xoffset, var->yoffset, offset); - - DBG("paddr %x, vaddr %p\n", data_start_p, data_start_v); + omapfb_calc_addr(ofbi, var, fix, rotation, + &data_start_p, &data_start_v); r = fb_mode_to_dss_mode(var, &mode); if (r) { From patchwork Tue May 11 14:15:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 98715 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4BECqxv019736 for ; Tue, 11 May 2010 14:12:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758154Ab0EKOMo (ORCPT ); Tue, 11 May 2010 10:12:44 -0400 Received: from smtp.nokia.com ([192.100.122.233]:50759 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758099Ab0EKOMl (ORCPT ); Tue, 11 May 2010 10:12:41 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4BEC94G013864; Tue, 11 May 2010 17:12:10 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 11 May 2010 17:12:07 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 11 May 2010 17:12:06 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4BEC3sP027143; Tue, 11 May 2010 17:12:05 +0300 From: Eduardo Valentin To: LKML , linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: Russell King , Andrew Morton , ext Tony Lindgren , ext Kevin Hilman , Peter De-Schrijver , santosh.shilimkar@ti.com, Ambresh , felipe.balbi@nokia.com, Jouni Hogander , Paul Mundt , Eduardo Valentin Subject: [PATCHv5 1/3] procfs: Introduce socinfo under /proc Date: Tue, 11 May 2010 17:15:29 +0300 Message-Id: <1273587331-24604-2-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273587331-24604-1-git-send-email-eduardo.valentin@nokia.com> References: <1273587331-24604-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 11 May 2010 14:12:06.0968 (UTC) FILETIME=[F02DB380:01CAF113] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 14:12:52 +0000 (UTC) diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index a4f30fa..039bcb7 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -415,6 +415,7 @@ Table 1-5: Kernel info in /proc bus Directory containing bus specific information cmdline Kernel command line cpuinfo Info about the CPU + socinfo Info about the System on Chip devices Available devices (block and character) dma Used DMS channels filesystems Supported filesystems diff --git a/fs/proc/Kconfig b/fs/proc/Kconfig index 50f8f06..e683d62 100644 --- a/fs/proc/Kconfig +++ b/fs/proc/Kconfig @@ -67,3 +67,10 @@ config PROC_PAGE_MONITOR /proc/pid/smaps, /proc/pid/clear_refs, /proc/pid/pagemap, /proc/kpagecount, and /proc/kpageflags. Disabling these interfaces will reduce the size of the kernel by approximately 4kb. + +config PROC_SOCINFO + default y + depends on PROC_FS + bool "Enable /proc/socinfo" if EMBEDDED + help + Say Y here if you need to see information about the your System on Chip. diff --git a/fs/proc/Makefile b/fs/proc/Makefile index 11a7b5c..7757d44 100644 --- a/fs/proc/Makefile +++ b/fs/proc/Makefile @@ -26,3 +26,4 @@ proc-$(CONFIG_PROC_VMCORE) += vmcore.o proc-$(CONFIG_PROC_DEVICETREE) += proc_devtree.o proc-$(CONFIG_PRINTK) += kmsg.o proc-$(CONFIG_PROC_PAGE_MONITOR) += page.o +proc-$(CONFIG_PROC_SOCINFO) += socinfo.o diff --git a/fs/proc/socinfo.c b/fs/proc/socinfo.c new file mode 100644 index 0000000..09a889d --- /dev/null +++ b/fs/proc/socinfo.c @@ -0,0 +1,80 @@ +/* + * fs/proc/socinfo.c + * + * Copyright (C) 2010 Nokia Corporation + * + * Contact: Eduardo Valentin + * + * proc socinfo file + */ +#include +#include +#include +#include +#include +#include + +/* + * Function pointer to soc core code which knows how to grab soc info + */ +static int (*socinfo_show)(struct seq_file *, void *); +static void *socinfo_data; +static DEFINE_MUTEX(socinfo_mutex); + +/** + * register_socinfo_show() - register a call back to provide SoC information + * @show: The function callback. It is expected to be in the same format + * as the .show of struct seq_operations. + * @data: A void * which will be passed as argument when show is called. + * + * This function will store the reference for a function and its data. The show + * argument will be called when filling up the seq_file of /proc/socinfo. + * Usually, this function should be called just once, while executing the SoC + * core initialization code. + */ +void register_socinfo_show(int (*show)(struct seq_file *, void *), void *data) +{ + mutex_lock(&socinfo_mutex); + socinfo_show = show; + socinfo_data = data; + mutex_unlock(&socinfo_mutex); +} + +static int socinfo_show_local(struct seq_file *sfile, void *data) +{ + int r; + + /* Just fall back to those who know how to grab the info */ + mutex_lock(&socinfo_mutex); + if (socinfo_show) + r = socinfo_show(sfile, socinfo_data); + else + r = seq_printf(sfile, "No data\n"); + mutex_unlock(&socinfo_mutex); + + return r; +} + +static int socinfo_open(struct inode *inode, struct file *file) +{ + return single_open(file, socinfo_show_local, NULL); +} + +static const struct file_operations proc_socinfo_operations = { + .owner = THIS_MODULE, + .open = socinfo_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init proc_socinfo_init(void) +{ + if (!proc_create("socinfo", 0, NULL, &proc_socinfo_operations)) { + pr_info("Failed to create /proc/socinfo\n"); + return -ENOMEM; + } + + return 0; +} +module_init(proc_socinfo_init); diff --git a/include/linux/socinfo.h b/include/linux/socinfo.h new file mode 100644 index 0000000..aa870f1 --- /dev/null +++ b/include/linux/socinfo.h @@ -0,0 +1,17 @@ +/* + * include/linux/socinfo.h + * + * Copyright (C) 2010 Nokia Corporation + * + * Contact: Eduardo Valentin + * + * proc socinfo file + */ + +#ifndef __SOCINFO_H +#define __SOCINFO_H + +#include + +void register_socinfo_show(int (*show)(struct seq_file *, void *), void *data); +#endif From patchwork Sun May 16 15:46:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99974 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkVf0025290 for ; Sun, 16 May 2010 15:46:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753626Ab0EPPqa (ORCPT ); Sun, 16 May 2010 11:46:30 -0400 Received: from fg-out-1718.google.com ([72.14.220.159]:5081 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753444Ab0EPPq3 (ORCPT ); Sun, 16 May 2010 11:46:29 -0400 Received: by fg-out-1718.google.com with SMTP id d23so2359940fga.1 for ; Sun, 16 May 2010 08:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=+d5OTzejBAVXsk96eLvdw6cM8Jw6MDDUuTbknFkncyw=; b=AUCtAb6WEwH65sKmd0OfvvAYwba8keuPOJamcRzCeje1zAgYW2vZ0oqBkDbcfJdz3x cUYnu/yXm8CoMljwAY8GHYymYUljphmjIRGcByIq38qC7fLxsvVksjQrQ2rP7rQ1b23q qI860kFIrQT3fT9WmNf2oz0Sqw0xfUHN+3Z5o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=ePAGF7s9n0E8i+ynyBu6xT3wvlJn17Qrt8CnlDG7EzPQcBiq36APO/HZ/CbGA2DAme eCqhPZ+OGctgtb7xni6joXDXx05gTBQwCYciHd9ogerf+uLN08pVBj7/OmbZUNyAKRSO I/Des4aTEZupxSnR0LWn+VGtbfk+MGa/IQfAM= Received: by 10.87.48.18 with SMTP id a18mr6726908fgk.53.1274024788736; Sun, 16 May 2010 08:46:28 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id 4sm11649460fgg.22.2010.05.16.08.46.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:28 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 10/14] dspbridge: deh: remove err_info Date: Sun, 16 May 2010 18:46:01 +0300 Message-Id: <1274024765-21076-11-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:31 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/dbdefs.h b/arch/arm/plat-omap/include/dspbridge/dbdefs.h index c6703a2..3c337e4 100644 --- a/arch/arm/plat-omap/include/dspbridge/dbdefs.h +++ b/arch/arm/plat-omap/include/dspbridge/dbdefs.h @@ -431,7 +431,6 @@ struct dsp_errorinfo { struct dsp_processorstate { u32 cb_struct; enum dsp_procstate proc_state; - struct dsp_errorinfo err_info; }; /* diff --git a/drivers/dsp/bridge/core/_deh.h b/drivers/dsp/bridge/core/_deh.h index 8da2212..32b84f3 100644 --- a/drivers/dsp/bridge/core/_deh.h +++ b/drivers/dsp/bridge/core/_deh.h @@ -26,7 +26,7 @@ struct deh_mgr { struct bridge_dev_context *hbridge_context; /* Bridge context. */ struct ntfy_object *ntfy_obj; /* NTFY object */ - struct dsp_errorinfo err_info; /* DSP exception info. */ + u32 fault_addr; /* MMU Fault DPC */ struct tasklet_struct dpc_tasklet; diff --git a/drivers/dsp/bridge/core/mmu_fault.c b/drivers/dsp/bridge/core/mmu_fault.c index 1de9cb4..49034cf 100644 --- a/drivers/dsp/bridge/core/mmu_fault.c +++ b/drivers/dsp/bridge/core/mmu_fault.c @@ -42,8 +42,6 @@ #include "_tiomap.h" #include "mmu_fault.h" -u32 fault_addr; - /* * ======== mmu_fault_dpc ======== * Deferred procedure call to handle DSP MMU fault. @@ -80,9 +78,9 @@ irqreturn_t mmu_fault_isr(int irq, IN void *pRefData) hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); if (dmmu_event_mask == HW_MMU_TRANSLATION_FAULT) { - hw_mmu_fault_addr_read(resources->dw_dmmu_base, &fault_addr); + hw_mmu_fault_addr_read(resources->dw_dmmu_base, &deh_mgr_obj->fault_addr); dev_info(bridge, "%s: status=0x%x, fault_addr=0x%x\n", __func__, - dmmu_event_mask, fault_addr); + dmmu_event_mask, deh_mgr_obj->fault_addr); /* * Schedule a DPC directly. In the future, it may be * necessary to check if DSP MMU fault is intended for @@ -90,11 +88,6 @@ irqreturn_t mmu_fault_isr(int irq, IN void *pRefData) */ tasklet_schedule(&deh_mgr_obj->dpc_tasklet); - /* Reset err_info structure before use. */ - deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT; - deh_mgr_obj->err_info.dw_val1 = fault_addr >> 16; - deh_mgr_obj->err_info.dw_val2 = fault_addr & 0xFFFF; - deh_mgr_obj->err_info.dw_val3 = 0L; /* Disable the MMU events, else once we clear it will * start to raise INTs again */ hw_mmu_event_disable(resources->dw_dmmu_base, diff --git a/drivers/dsp/bridge/core/mmu_fault.h b/drivers/dsp/bridge/core/mmu_fault.h index 74db489..537e6e7 100644 --- a/drivers/dsp/bridge/core/mmu_fault.h +++ b/drivers/dsp/bridge/core/mmu_fault.h @@ -19,8 +19,6 @@ #ifndef MMU_FAULT_ #define MMU_FAULT_ -extern u32 fault_addr; - /* * ======== mmu_fault_dpc ======== * Deferred procedure call to handle DSP MMU fault. diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 2388780..6035757 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -94,10 +94,6 @@ dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, /* Fill in context structure */ deh_mgr->hbridge_context = hbridge_context; - deh_mgr->err_info.dw_err_mask = 0L; - deh_mgr->err_info.dw_val1 = 0L; - deh_mgr->err_info.dw_val2 = 0L; - deh_mgr->err_info.dw_val3 = 0L; /* Install ISR function for DSP MMU fault */ status = request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0, @@ -189,7 +185,8 @@ static void wait_for_timer(void) omap_dm_timer_disable(timer); } -static void mmu_fault_print_stack(struct bridge_dev_context *dev_context) +static void mmu_fault_print_stack(struct bridge_dev_context *dev_context, + u32 fault_addr) { struct cfg_hostres *resources; struct hw_mmu_map_attrs_t map_attrs = { @@ -237,49 +234,28 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) switch (ulEventMask) { case DSP_SYSERROR: - /* reset err_info structure before use */ - deh_mgr->err_info.dw_err_mask = DSP_SYSERROR; - deh_mgr->err_info.dw_val1 = 0L; - deh_mgr->err_info.dw_val2 = 0L; - deh_mgr->err_info.dw_val3 = 0L; - deh_mgr->err_info.dw_val1 = dwErrInfo; dev_err(bridge, "%s: %s, err_info = 0x%x\n", __func__, "DSP_SYSERROR", dwErrInfo); dump_dl_modules(dev_context); dump_dsp_stack(dev_context); break; case DSP_MMUFAULT: - /* MMU fault routine should have set err info structure. */ - deh_mgr->err_info.dw_err_mask = DSP_MMUFAULT; dev_err(bridge, "%s: %s, err_info = 0x%x\n", __func__, "DSP_MMUFAULT", dwErrInfo); - dev_info(bridge, "%s: %s, high=0x%x, low=0x%x, " - "fault=0x%x\n", __func__, "DSP_MMUFAULT", - (unsigned int) deh_mgr->err_info.dw_val1, - (unsigned int) deh_mgr->err_info.dw_val2, - (unsigned int) fault_addr); + dev_info(bridge, "%s: %s, fault=0x%x\n", __func__, "DSP_MMUFAULT", + deh_mgr->fault_addr); print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); - mmu_fault_print_stack(dev_context); + mmu_fault_print_stack(dev_context, deh_mgr->fault_addr); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR case DSP_PWRERROR: - /* reset err_info structure before use */ - deh_mgr->err_info.dw_err_mask = DSP_PWRERROR; - deh_mgr->err_info.dw_val1 = 0L; - deh_mgr->err_info.dw_val2 = 0L; - deh_mgr->err_info.dw_val3 = 0L; - deh_mgr->err_info.dw_val1 = dwErrInfo; dev_err(bridge, "%s: %s, err_info = 0x%x\n", __func__, "DSP_PWRERROR", dwErrInfo); break; #endif /* CONFIG_BRIDGE_NTFY_PWRERR */ case DSP_WDTOVERFLOW: - deh_mgr->err_info.dw_err_mask = DSP_WDTOVERFLOW; - deh_mgr->err_info.dw_val1 = 0L; - deh_mgr->err_info.dw_val2 = 0L; - deh_mgr->err_info.dw_val3 = 0L; dev_err(bridge, "%s: DSP_WDTOVERFLOW\n", __func__); break; default: From patchwork Thu Apr 1 13:16:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 90138 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o31DGTvs007601 for ; Thu, 1 Apr 2010 13:16:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753938Ab0DANQa (ORCPT ); Thu, 1 Apr 2010 09:16:30 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:60133 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752814Ab0DANQ2 (ORCPT ); Thu, 1 Apr 2010 09:16:28 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o31DGJgp013547 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 1 Apr 2010 08:16:20 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o31DGG42025954; Thu, 1 Apr 2010 08:16:17 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Thu, 1 Apr 2010 18:46:19 +0530 (IST) Message-ID: <37391.10.24.255.17.1270127779.squirrel@dbdmail.itg.ti.com> Date: Thu, 1 Apr 2010 18:46:19 +0530 (IST) Subject: [PATCH 1/2] [STAGING] Synaptic : Remove non-standard multi touch support From: "Hemanth V" To: gregkh@suse.de, devel@driverdev.osuosl.org Cc: pavel@ucw.cz, linux-input@vger.kernel.org, linux-omap@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal References: In-Reply-To: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Apr 2010 13:16:52 +0000 (UTC) diff --git a/drivers/staging/dream/synaptics_i2c_rmi.c b/drivers/staging/dream/synaptics_i2c_rmi.c index 4de6bc9..7c1b980 100644 --- a/drivers/staging/dream/synaptics_i2c_rmi.c +++ b/drivers/staging/dream/synaptics_i2c_rmi.c @@ -108,9 +108,7 @@ static void decode_report(struct synaptics_ts_data *ts, u8 *buf) int f, a; int base = 2; int z = buf[1]; - int w = buf[0] >> 4; int finger = buf[0] & 7; - int finger2_pressed; for (f = 0; f < 2; f++) { u32 flip_flag = SYNAPTICS_FLIP_X; @@ -150,14 +148,7 @@ static void decode_report(struct synaptics_ts_data *ts, u8 *buf) input_report_abs(ts->input_dev, ABS_Y, pos[0][1]); } input_report_abs(ts->input_dev, ABS_PRESSURE, z); - input_report_abs(ts->input_dev, ABS_TOOL_WIDTH, w); input_report_key(ts->input_dev, BTN_TOUCH, finger); - finger2_pressed = finger > 1 && finger != 7; - input_report_key(ts->input_dev, BTN_2, finger2_pressed); - if (finger2_pressed) { - input_report_abs(ts->input_dev, ABS_HAT0X, pos[1][0]); - input_report_abs(ts->input_dev, ABS_HAT0Y, pos[1][1]); - } input_sync(ts->input_dev); } @@ -346,11 +337,6 @@ static void compute_areas(struct synaptics_ts_data *ts, -inactive_area_top, max_y + inactive_area_bottom, fuzz_y, 0); input_set_abs_params(ts->input_dev, ABS_PRESSURE, 0, 255, fuzz_p, 0); - input_set_abs_params(ts->input_dev, ABS_TOOL_WIDTH, 0, 15, fuzz_w, 0); - input_set_abs_params(ts->input_dev, ABS_HAT0X, -inactive_area_left, - max_x + inactive_area_right, fuzz_x, 0); - input_set_abs_params(ts->input_dev, ABS_HAT0Y, -inactive_area_top, - max_y + inactive_area_bottom, fuzz_y, 0); } static struct synaptics_i2c_rmi_platform_data fake_pdata; @@ -486,7 +472,6 @@ static int __devinit synaptics_ts_probe( __set_bit(EV_SYN, ts->input_dev->evbit); From patchwork Sun May 16 15:46:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99975 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkVf1025290 for ; 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b=IBQ3qlzX635OwbmNHWMUADEAXyYhc9WVctPOiG+RqvlEZW6GicW4funQcxmmT4iwb6 +ie19kb2mRgAO3rGZOb72zMaj9GSvU9wX66jz9bUs1qqEUSxJH/n0BQlHMdqjhPNiNQ+ 1PVjE//f/lpiWqehhC8xq87lYUYeezLyr/Ce8= Received: by 10.87.50.37 with SMTP id c37mr6741585fgk.68.1274024791057; Sun, 16 May 2010 08:46:31 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id d8sm11667122fga.21.2010.05.16.08.46.30 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:30 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 11/14] dspbridge: access deh directly Date: Sun, 16 May 2010 18:46:02 +0300 Message-Id: <1274024765-21076-12-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:33 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/dspdefs.h b/arch/arm/plat-omap/include/dspbridge/dspdefs.h index a5d410f..268c217 100644 --- a/arch/arm/plat-omap/include/dspbridge/dspdefs.h +++ b/arch/arm/plat-omap/include/dspbridge/dspdefs.h @@ -731,57 +731,6 @@ typedef dsp_status(*fxn_dev_ctrl) (struct bridge_dev_context *hDevContext, typedef dsp_status(*fxn_dev_destroy) (struct bridge_dev_context *hDevContext); /* - * ======== bridge_deh_create ======== - * Purpose: - * Create an object that manages DSP exceptions from the GPP. - * Parameters: - * phDehMgr: Location to store DEH manager on output. - * hdev_obj: Handle to DEV object. - * Returns: - * DSP_SOK: Success. - * -ENOMEM: Memory allocation failure. - * -EPERM: Creation failed. - * Requires: - * hdev_obj != NULL; - * phDehMgr != NULL; - * Ensures: - */ -typedef dsp_status(*fxn_deh_create) (OUT struct deh_mgr - **phDehMgr, struct dev_object *hdev_obj); - -/* - * ======== bridge_deh_destroy ======== - * Purpose: - * Destroy the DEH object. - * Parameters: - * hdeh_mgr: Handle to DEH manager object. - * Returns: - * DSP_SOK: Success. - * -EPERM: Destroy failed. - * Requires: - * hdeh_mgr != NULL; - * Ensures: - */ -typedef dsp_status(*fxn_deh_destroy) (struct deh_mgr *hdeh_mgr); - -/* - * ======== bridge_deh_register_notify ======== - * Purpose: - * Register for DEH event notification. - * Parameters: - * hdeh_mgr: Handle to DEH manager object. - * Returns: - * DSP_SOK: Success. - * -EPERM: Destroy failed. - * Requires: - * hdeh_mgr != NULL; - * Ensures: - */ -typedef dsp_status(*fxn_deh_registernotify) - (struct deh_mgr *hdeh_mgr, - u32 event_mask, u32 notify_type, struct dsp_notification *hnotification); - -/* * ======== bridge_io_create ======== * Purpose: * Create an object that manages I/O between CHNL and msg_ctrl. @@ -1066,11 +1015,6 @@ struct bridge_drv_interface { fxn_chnl_idle pfn_chnl_idle; /* Idle the channel */ /* Register for notif. */ fxn_chnl_registernotify pfn_chnl_register_notify; - fxn_deh_create pfn_deh_create; /* Create DEH manager */ - fxn_deh_destroy pfn_deh_destroy; /* Destroy DEH manager */ - fxn_deh_notify pfn_deh_notify; /* Notify of DSP error */ - /* register for deh notif. */ - fxn_deh_registernotify pfn_deh_register_notify; fxn_io_create pfn_io_create; /* Create IO manager */ fxn_io_destroy pfn_io_destroy; /* Destroy IO manager */ fxn_io_onloaded pfn_io_on_loaded; /* Notify of program loaded */ diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 99bf966..f6b421e 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -192,11 +192,6 @@ static struct bridge_drv_interface drv_interface_fxns = { bridge_chnl_get_mgr_info, bridge_chnl_idle, bridge_chnl_register_notify, - /* The following DEH functions are provided by tihelen_ue_deh.c */ - bridge_deh_create, - bridge_deh_destroy, - bridge_deh_notify, - bridge_deh_register_notify, /* The following IO functions are provided by chnl_io.lib: */ bridge_io_create, bridge_io_destroy, diff --git a/drivers/dsp/bridge/pmgr/dev.c b/drivers/dsp/bridge/pmgr/dev.c index b1c8d8b..3f7eb47 100644 --- a/drivers/dsp/bridge/pmgr/dev.c +++ b/drivers/dsp/bridge/pmgr/dev.c @@ -49,6 +49,7 @@ #include #include #include +#include /* ----------------------------------- This */ #include @@ -235,8 +236,7 @@ dsp_status dev_create_device(OUT struct dev_object **phDevObject, /* Only create DEH manager if we have an IO manager */ if (DSP_SUCCEEDED(status)) { /* Instantiate the DEH module */ - status = (*dev_obj->bridge_interface.pfn_deh_create) - (&dev_obj->hdeh_mgr, dev_obj); + status = bridge_deh_create(&dev_obj->hdeh_mgr, dev_obj); } /* Create DMM mgr . */ status = dmm_create(&dev_obj->dmm_mgr, @@ -371,8 +371,7 @@ dsp_status dev_destroy_device(struct dev_object *hdev_obj) if (dev_obj->hdeh_mgr) { /* Uninitialize DEH module. */ - (*dev_obj->bridge_interface.pfn_deh_destroy) - (dev_obj->hdeh_mgr); + bridge_deh_destroy(dev_obj->hdeh_mgr); dev_obj->hdeh_mgr = NULL; } if (dev_obj->hcmm_mgr) { @@ -1117,10 +1116,6 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, STORE_FXN(fxn_chnl_getmgrinfo, pfn_chnl_get_mgr_info); STORE_FXN(fxn_chnl_idle, pfn_chnl_idle); STORE_FXN(fxn_chnl_registernotify, pfn_chnl_register_notify); - STORE_FXN(fxn_deh_create, pfn_deh_create); - STORE_FXN(fxn_deh_destroy, pfn_deh_destroy); - STORE_FXN(fxn_deh_notify, pfn_deh_notify); - STORE_FXN(fxn_deh_registernotify, pfn_deh_register_notify); STORE_FXN(fxn_io_create, pfn_io_create); STORE_FXN(fxn_io_destroy, pfn_io_destroy); STORE_FXN(fxn_io_onloaded, pfn_io_on_loaded); @@ -1157,10 +1152,6 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, DBC_ENSURE(intf_fxns->pfn_chnl_get_mgr_info != NULL); DBC_ENSURE(intf_fxns->pfn_chnl_idle != NULL); DBC_ENSURE(intf_fxns->pfn_chnl_register_notify != NULL); - DBC_ENSURE(intf_fxns->pfn_deh_create != NULL); - DBC_ENSURE(intf_fxns->pfn_deh_destroy != NULL); - DBC_ENSURE(intf_fxns->pfn_deh_notify != NULL); - DBC_ENSURE(intf_fxns->pfn_deh_register_notify != NULL); DBC_ENSURE(intf_fxns->pfn_io_create != NULL); DBC_ENSURE(intf_fxns->pfn_io_destroy != NULL); DBC_ENSURE(intf_fxns->pfn_io_on_loaded != NULL); diff --git a/drivers/dsp/bridge/rmgr/node.c b/drivers/dsp/bridge/rmgr/node.c index cdd60e6..23aed68 100644 --- a/drivers/dsp/bridge/rmgr/node.c +++ b/drivers/dsp/bridge/rmgr/node.c @@ -69,6 +69,8 @@ #include #include <_tiomap.h> +#include + #define HOSTPREFIX "/host" #define PIPEPREFIX "/dbpipe" @@ -2470,8 +2472,7 @@ dsp_status node_terminate(struct node_object *hnode, OUT dsp_status *pstatus) if (!hdeh_mgr) goto func_cont; - (*intf_fxns->pfn_deh_notify)(hdeh_mgr, DSP_SYSERROR, - DSP_EXCEPTIONABORT); + bridge_deh_notify(hdeh_mgr, DSP_SYSERROR, DSP_EXCEPTIONABORT); } } func_cont: diff --git a/drivers/dsp/bridge/rmgr/proc.c b/drivers/dsp/bridge/rmgr/proc.c index f86958a..1cccc89 100644 --- a/drivers/dsp/bridge/rmgr/proc.c +++ b/drivers/dsp/bridge/rmgr/proc.c @@ -1192,22 +1192,20 @@ dsp_status proc_register_notify(void *hprocessor, u32 event_mask, status = dev_get_deh_mgr(p_proc_object->hdev_obj, &hdeh_mgr); - DBC_ASSERT(p_proc_object-> - intf_fxns->pfn_deh_register_notify); status = - (*p_proc_object-> - intf_fxns->pfn_deh_register_notify) - (hdeh_mgr, event_mask, notify_type, - hnotification); + bridge_deh_register_notify(hdeh_mgr, + event_mask, + notify_type, + hnotification); } } else { status = dev_get_deh_mgr(p_proc_object->hdev_obj, &hdeh_mgr); - DBC_ASSERT(p_proc_object-> - intf_fxns->pfn_deh_register_notify); status = - (*p_proc_object->intf_fxns->pfn_deh_register_notify) - (hdeh_mgr, event_mask, notify_type, hnotification); + bridge_deh_register_notify(hdeh_mgr, + event_mask, + notify_type, + hnotification); } } From patchwork Thu Jul 22 09:13:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjeev Premi X-Patchwork-Id: 113535 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6M9Ec07024295 for ; Thu, 22 Jul 2010 09:14:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753812Ab0GVJOh (ORCPT ); Thu, 22 Jul 2010 05:14:37 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:59205 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753286Ab0GVJOh (ORCPT ); Thu, 22 Jul 2010 05:14:37 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6M9EXCO028662 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 22 Jul 2010 04:14:36 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6M9EWEU019361; Thu, 22 Jul 2010 14:44:33 +0530 (IST) From: Sanjeev Premi To: linux-omap@vger.kernel.org Cc: Yogesh Marathe , Sanjeev Premi Subject: [PATCH] omap3: Remove non-existent config option Date: Thu, 22 Jul 2010 14:43:47 +0530 Message-Id: <1279790027-2509-1-git-send-email-premi@ti.com> X-Mailer: git-send-email 1.6.6.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 22 Jul 2010 09:14:39 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index f5a1aad..bb8c01d 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -35,7 +35,6 @@ static struct iommu_device omap3_devices[] = { .clk_name = "cam_ick", }, }, -#if defined(CONFIG_MPU_BRIDGE_IOMMU) { .base = 0x5d000000, .irq = 28, @@ -45,7 +44,6 @@ static struct iommu_device omap3_devices[] = { .clk_name = "iva2_ck", }, }, -#endif }; #define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices) static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; From patchwork Mon Apr 26 08:24:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 95014 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3Q8PgQU022703 for ; Mon, 26 Apr 2010 08:25:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751371Ab0DZIZm (ORCPT ); Mon, 26 Apr 2010 04:25:42 -0400 Received: from smtp.nokia.com ([192.100.122.230]:17163 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750716Ab0DZIZl (ORCPT ); Mon, 26 Apr 2010 04:25:41 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3Q8PUJw024920; Mon, 26 Apr 2010 11:25:35 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 11:25:26 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 11:25:21 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3Q8P59k032417; Mon, 26 Apr 2010 11:25:16 +0300 From: Eduardo Valentin To: ext Kevin Hilman , ext Tony Lindgren Cc: "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , Linux-OMAP , Eduardo Valentin Subject: [PATCH 3/4] mach-omap1: Add SoC info data for OMAP into /proc/cpuinfo1 Date: Mon, 26 Apr 2010 11:24:52 +0300 Message-Id: <1272270293-18568-4-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1272270293-18568-1-git-send-email-eduardo.valentin@nokia.com> References: <1272270293-18568-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 26 Apr 2010 08:25:21.0927 (UTC) FILETIME=[03362170:01CAE51A] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 26 Apr 2010 08:25:43 +0000 (UTC) diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index a0e3560..9622e9f 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -194,11 +194,17 @@ void __init omap_check_revision(void) printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type); } - printk(KERN_INFO "OMAP%04x", omap_revision >> 16); - if ((omap_revision >> 8) & 0xff) - printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff); - printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n", - die_rev, omap_revision & 0xff, system_serial_low, - system_serial_high); + snprintf(system_soc_info, SYSTEM_SOC_INFO_SIZE, "OMAP%04x", + omap_revision >> 16); + if ((omap_revision >> 8) & 0xff) { + int sz = strlen(system_soc_info); + + snprintf(system_soc_info + sz, SYSTEM_SOC_INFO_SIZE - sz, + "%x", (omap_revision >> 8) & 0xff); + } + pr_info("%s revision %i handled as %02xxx id: %08x%08x\n", + system_soc_info, die_rev, omap_revision & 0xff, + system_serial_low, system_serial_high); + } From patchwork Wed May 5 14:27:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 97106 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o45ES5PA002693 for ; Wed, 5 May 2010 14:28:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934805Ab0EEO2I (ORCPT ); Wed, 5 May 2010 10:28:08 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34118 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934757Ab0EEO2E (ORCPT ); Wed, 5 May 2010 10:28:04 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERs3R005616; Wed, 5 May 2010 09:28:02 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:01 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 5 May 2010 17:28:01 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o45ERfRE016232; Wed, 5 May 2010 17:27:59 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v3 12/21] OMAP: DSS2: Taal: Change ESD work management Date: Wed, 5 May 2010 17:27:32 +0300 Message-Id: <8665676eca5bbd3be35b63f7110f629e94a6babe.1273067195.git.ext-jani.1.nikula@nokia.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> References: <1dfb7728d4d3ba8ceff808563e5a9f4c40aa3e9f.1273067195.git.ext-jani.1.nikula@nokia.com> <6b813e9f0008e23e7981f6ca35501f56c292858a.1273067195.git.ext-jani.1.nikula@nokia.com> <94d9d7bebbf7588bd77b65e6a46044240140a350.1273067195.git.ext-jani.1.nikula@nokia.com> <61a89461654fe44174902f6e29b8acded7529b67.1273067195.git.ext-jani.1.nikula@nokia.com> <16a98ca1b45ba9b9bb30f23d242449c1d440df07.1273067195.git.ext-jani.1.nikula@nokia.com> <0cfff2a3cbb4231b41b382caf8aab7c52f47b0d5.1273067195.git.ext-jani.1.nikula@nokia.com> <4cb510ffbc3216e2a7dac16edaff5fb1980b3315.1273067195.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 05 May 2010 14:28:01.0133 (UTC) FILETIME=[2A6D39D0:01CAEC5F] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 05 May 2010 14:28:16 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 7b5f845..fa4c67b 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -654,7 +654,7 @@ static void taal_remove(struct omap_dss_device *dssdev) taal_bl_update_status(bldev); backlight_device_unregister(bldev); - cancel_delayed_work_sync(&td->esd_work); + cancel_delayed_work(&td->esd_work); destroy_workqueue(td->esd_wq); /* reset, to be sure that the panel is in a valid state */ @@ -725,10 +725,6 @@ static int taal_power_on(struct omap_dss_device *dssdev) if (r) goto err; -#ifdef TAAL_USE_ESD_CHECK - queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD); -#endif - td->enabled = 1; if (!td->intro_printed) { @@ -758,8 +754,6 @@ static void taal_power_off(struct omap_dss_device *dssdev) struct taal_data *td = dev_get_drvdata(&dssdev->dev); int r; - cancel_delayed_work(&td->esd_work); - r = taal_dcs_write_0(DCS_DISPLAY_OFF); if (!r) { r = taal_sleep_in(td); @@ -801,6 +795,10 @@ static int taal_enable(struct omap_dss_device *dssdev) if (r) goto err; +#ifdef TAAL_USE_ESD_CHECK + queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD); +#endif + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; mutex_unlock(&td->lock); @@ -820,6 +818,8 @@ static void taal_disable(struct omap_dss_device *dssdev) mutex_lock(&td->lock); + cancel_delayed_work(&td->esd_work); + dsi_bus_lock(); if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) @@ -846,6 +846,8 @@ static int taal_suspend(struct omap_dss_device *dssdev) goto err; } + cancel_delayed_work(&td->esd_work); + dsi_bus_lock(); taal_power_off(dssdev); @@ -882,10 +884,15 @@ static int taal_resume(struct omap_dss_device *dssdev) dsi_bus_unlock(); - if (r) + if (r) { dssdev->state = OMAP_DSS_DISPLAY_DISABLED; - else + } else { dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; +#ifdef TAAL_USE_ESD_CHECK + queue_delayed_work(td->esd_wq, &td->esd_work, + TAAL_ESD_CHECK_PERIOD); +#endif + } mutex_unlock(&td->lock); From patchwork Mon Apr 26 08:24:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 95011 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3Q8M2hn021890 for ; Mon, 26 Apr 2010 08:25:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751312Ab0DZIZ1 (ORCPT ); Mon, 26 Apr 2010 04:25:27 -0400 Received: from smtp.nokia.com ([192.100.105.134]:34059 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750716Ab0DZIZ1 (ORCPT ); Mon, 26 Apr 2010 04:25:27 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3Q8OjPh020591; Mon, 26 Apr 2010 03:25:24 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 11:25:18 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 11:25:17 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3Q8P59i032417; Mon, 26 Apr 2010 11:25:13 +0300 From: Eduardo Valentin To: ext Kevin Hilman , ext Tony Lindgren Cc: "\\\"De-Schrijver Peter (Nokia-D/Helsinki)\\\"" , Linux-OMAP , Eduardo Valentin Subject: [PATCH 1/4] ARM: Introduce SoC Info into /proc/cpuinfo Date: Mon, 26 Apr 2010 11:24:50 +0300 Message-Id: <1272270293-18568-2-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1272270293-18568-1-git-send-email-eduardo.valentin@nokia.com> References: <1272270293-18568-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 26 Apr 2010 08:25:18.0368 (UTC) FILETIME=[01171200:01CAE51A] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 26 Apr 2010 08:25:28 +0000 (UTC) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4ace45e..53a9645 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -71,6 +71,8 @@ struct task_struct; extern unsigned int system_rev; extern unsigned int system_serial_low; extern unsigned int system_serial_high; +#define SYSTEM_SOC_INFO_SIZE 128 +extern char system_soc_info[SYSTEM_SOC_INFO_SIZE]; extern unsigned int mem_fclk_21285; struct pt_regs; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c91c77b..025d795 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -85,6 +85,9 @@ EXPORT_SYMBOL(system_serial_low); unsigned int system_serial_high; EXPORT_SYMBOL(system_serial_high); +char system_soc_info[SYSTEM_SOC_INFO_SIZE]; +EXPORT_SYMBOL(system_soc_info); + unsigned int elf_hwcap; EXPORT_SYMBOL(elf_hwcap); @@ -847,6 +850,8 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "Revision\t: %04x\n", system_rev); seq_printf(m, "Serial\t\t: %08x%08x\n", system_serial_high, system_serial_low); + if (strlen(system_soc_info)) + seq_printf(m, "SoC Info\t: %s\n", system_soc_info); return 0; } From patchwork Wed Jul 28 15:03:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 114812 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SF4TUw015809 for ; Wed, 28 Jul 2010 15:05:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754553Ab0G1PD7 (ORCPT ); Wed, 28 Jul 2010 11:03:59 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33586 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753882Ab0G1PD6 (ORCPT ); Wed, 28 Jul 2010 11:03:58 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SF3oB1030996 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 10:03:50 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6SF3opP029415; Wed, 28 Jul 2010 10:03:50 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6SF3oKA019060; Wed, 28 Jul 2010 10:03:50 -0500 (CDT) Received: from [128.247.74.250] (128.247.74.250) by dlee73.ent.ti.com (157.170.170.88) with Microsoft SMTP Server id 8.1.358.0; Wed, 28 Jul 2010 10:03:49 -0500 Message-ID: <4C5046D5.6010306@ti.com> Date: Wed, 28 Jul 2010 10:03:49 -0500 From: Nishanth Menon User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: "Ramos Falcon, Ernesto" CC: "gregkh@suse.de" , "Ramirez Luna, Omar" , "ohad@wizery.com" , "ameya.palande@nokia.com" , "felipe.contreras@nokia.com" , "Guzman Lugo, Fernando" , "linux-kernel@vger.kernel.org" , "andy.shevchenko@gmail.com" , "linux-omap@vger.kernel.org" Subject: Re: [PATCH 4/5] staging:ti dspbridge: remove unnecessary volatile variables References: <1280328052-31292-1-git-send-email-ernesto@ti.com> <1280328052-31292-2-git-send-email-ernesto@ti.com> <1280328052-31292-3-git-send-email-ernesto@ti.com> <1280328052-31292-4-git-send-email-ernesto@ti.com> <1280328052-31292-5-git-send-email-ernesto@ti.com> In-Reply-To: <1280328052-31292-5-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 15:05:17 +0000 (UTC) --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -1022,18 +1022,17 @@ void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, void *va_buf, DBC_REQUIRE(xlator_obj->ul_seg_id > 0); if (xlator_obj) { + void *t_buf = 0; attrs.ul_seg_id = xlator_obj->ul_seg_id; - *(volatile u32 *)va_buf = 0; /* Alloc SM */ pbuf = cmm_calloc_buf(xlator_obj->hcmm_mgr, pa_size, &attrs, NULL); if (pbuf) { /* convert to translator(node/strm) process Virtual * address */ - *(volatile u32 **)va_buf = - (u32 *) cmm_xlator_translate(xlator, - pbuf, CMM_PA2VA); + t_buf = cmm_xlator_translate(xlator, pbuf, CMM_PA2VA); } + writel(t_buf, va_buf); } return pbuf; From patchwork Fri Aug 6 07:03:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 117714 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o7672cg5025381 for ; Fri, 6 Aug 2010 07:02:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758123Ab0HFHCh (ORCPT ); Fri, 6 Aug 2010 03:02:37 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:61679 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754560Ab0HFHCg (ORCPT ); Fri, 6 Aug 2010 03:02:36 -0400 Received: from muru.com ([72.249.23.125] helo=localhost.localdomain) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OhGws-000KHR-Us; Fri, 06 Aug 2010 07:02:35 +0000 Received: from Mutt by mutt-smtp-wrapper.pl 1.2 (www.zdo.com/articles/mutt-smtp-wrapper.shtml) X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1/gY2DYC/Ym05+kwMWRMVMT Date: Fri, 6 Aug 2010 10:03:01 +0300 From: Tony Lindgren To: Kevin Hilman Cc: "Nayak, Rajendra" , "linux-omap@vger.kernel.org" Subject: [PATCH] omap: Use CONFIG_SMP for test_for_ipi and test_for_ltirq belong (Re: PM branch updated to v2.6.35, SRF dropped) Message-ID: <20100806070301.GA23778@atomide.com> References: <8739uu9em0.fsf@deeprootsystems.com> <5A47E75E594F054BAF48C5E4FC4B92AB0323E6947D@dbde02.ent.ti.com> <87tyn8ptkl.fsf@deeprootsystems.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87tyn8ptkl.fsf@deeprootsystems.com> User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 07:02:38 +0000 (UTC) From: Tony Lindgren Date: Thu, 5 Aug 2010 13:18:20 +0300 Subject: [PATCH] omap: Use CONFIG_SMP for test_for_ipi and test_for_ltirq belong Otherwise we get the following error when enabling CONFIG_SMP for omap3_defconfig: arch/arm/kernel/entry-armv.S: Assembler messages: arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ipi r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ltirq r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ipi r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ltirq r0,r6,r5,lr' Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 50fd749..06e64e1 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -177,7 +177,10 @@ omap_irq_base: .word 0 cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr .endm +#endif +#endif /* MULTI_OMAP2 */ +#ifdef CONFIG_SMP /* We assume that irqstat (the raw value of the IRQ acknowledge * register) is preserved from the macro above. * If there is an IPI, we immediately signal end of interrupt @@ -205,8 +208,7 @@ omap_irq_base: .word 0 streq \irqstat, [\base, #GIC_CPU_EOI] cmp \tmp, #0 .endm -#endif -#endif /* MULTI_OMAP2 */ +#endif /* CONFIG_SMP */ .macro irq_prio_table .endm From patchwork Wed Jul 28 14:56:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114810 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SEprEb013720 for ; Wed, 28 Jul 2010 14:51:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755098Ab0G1OvY (ORCPT ); Wed, 28 Jul 2010 10:51:24 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:42973 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754862Ab0G1OvX (ORCPT ); Wed, 28 Jul 2010 10:51:23 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SEpGd4005839 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 09:51:16 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6SEpER7014645; Wed, 28 Jul 2010 09:51:15 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SEpB2U025585; Wed, 28 Jul 2010 09:51:12 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH] staging:ti dspbridge: remove find_gcf from nldr.c Date: Wed, 28 Jul 2010 09:56:01 -0500 Message-Id: <1280328961-31409-1-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 14:51:53 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 23b44cf..f01bddd 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -35,6 +35,7 @@ #include #include +#include /* Name of section containing dynamic load mem */ #define DYNMEMSECT ".dspbridge_mem" @@ -304,7 +305,6 @@ static void unload_ovly(struct nldr_nodeobject *nldr_node_obj, static bool find_in_persistent_lib_array(struct nldr_nodeobject *nldr_node_obj, struct dbll_library_obj *lib); static u32 find_lcm(u32 a, u32 b); -static u32 find_gcf(u32 a, u32 b); /* * ======== nldr_allocate ======== @@ -1889,27 +1889,11 @@ static u32 find_lcm(u32 a, u32 b) { u32 ret; - ret = a * b / find_gcf(a, b); + ret = a * b / gcd(a, b); return ret; } -/* - * ================ Find GCF (Greatest Common Factor ) === - */ -static u32 find_gcf(u32 a, u32 b) -{ - u32 c; - - /* Get the GCF (Greatest common factor between the numbers, - * using Euclidian Algo */ - while ((c = (a % b))) { - a = b; - b = c; - } - return b; -} - #ifdef CONFIG_TIDSPBRIDGE_BACKTRACE /** * nldr_find_addr() - Find the closest symbol to the given address based on From patchwork Sun May 16 15:46:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99977 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkbgO025340 for ; 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b=abTDq38Nf3LWZhMHtzODjsnRN7LEHxl0MlyTHhNbKH2dfJyYIdl09umsvEDjBg6sbd bYQrGG6Yv4+DZGzX3u3zaCrujG6JT3VYXVD1QoJhWO/G0G+9+B5A66NkXPeg4GUxypIm dObACK7SpJ70hF46N5JU+XyPlI+qYHxwTp36w= Received: by 10.87.45.15 with SMTP id x15mr6772987fgj.42.1274024794773; Sun, 16 May 2010 08:46:34 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id 4sm11597158fgg.27.2010.05.16.08.46.33 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:34 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 13/14] dspbridge: deh: tidying up Date: Sun, 16 May 2010 18:46:04 +0300 Message-Id: <1274024765-21076-14-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:37 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/dspdeh.h b/arch/arm/plat-omap/include/dspbridge/dspdeh.h index 4c4d577..e5e83b4 100644 --- a/arch/arm/plat-omap/include/dspbridge/dspdeh.h +++ b/arch/arm/plat-omap/include/dspbridge/dspdeh.h @@ -23,21 +23,20 @@ #ifndef DSPDEH_ #define DSPDEH_ -#include +struct deh_mgr; +struct dev_object; +struct dsp_notification; -#include - -extern dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, +int bridge_deh_create(struct deh_mgr **ret_deh, struct dev_object *hdev_obj); -extern dsp_status bridge_deh_destroy(struct deh_mgr *deh_mgr); +int bridge_deh_destroy(struct deh_mgr *deh); -extern dsp_status bridge_deh_register_notify(struct deh_mgr *deh_mgr, +int bridge_deh_register_notify(struct deh_mgr *deh, u32 event_mask, u32 notify_type, struct dsp_notification *hnotification); -extern void bridge_deh_notify(struct deh_mgr *deh_mgr, - u32 ulEventMask, u32 dwErrInfo); +void bridge_deh_notify(struct deh_mgr *deh, int event, int info); #endif /* DSPDEH_ */ diff --git a/drivers/dsp/bridge/core/_deh.h b/drivers/dsp/bridge/core/_deh.h index 32b84f3..9fb727b 100644 --- a/drivers/dsp/bridge/core/_deh.h +++ b/drivers/dsp/bridge/core/_deh.h @@ -26,7 +26,6 @@ struct deh_mgr { struct bridge_dev_context *hbridge_context; /* Bridge context. */ struct ntfy_object *ntfy_obj; /* NTFY object */ - u32 fault_addr; /* MMU Fault DPC */ struct tasklet_struct dpc_tasklet; diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index d44c895..6ff73a2 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -16,41 +16,19 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ -/* ----------------------------------- Host OS */ -#include +#include +#include #include -/* ----------------------------------- DSP/BIOS Bridge */ -#include #include -#include - -/* ----------------------------------- Trace & Debug */ -#include - -/* ----------------------------------- OS Adaptation Layer */ -#include -#include -#include - -/* ----------------------------------- Link Driver */ #include - -/* ----------------------------------- Platform Manager */ #include -#include -#include - -/* ------------------------------------ Hardware Abstraction Layer */ -#include -#include - -/* ----------------------------------- This */ #include "_tiomap.h" #include "_deh.h" -#include "_tiomap_mmu.h" -#include "_tiomap_pwr.h" + #include +#include +#include /* GP Timer number to trigger interrupt for MMU-fault ISR on DSP */ #define GPTIMER_FOR_DSP_MMU_FAULT 8 @@ -60,44 +38,45 @@ #define GPTIMER_IRQ_WAIT_MAX_CNT 1000 static struct omap_dm_timer *timer; +static u32 fault_addr; static void mmu_fault_dpc(unsigned long data) { - struct deh_mgr *hdeh_mgr = (void *)data; + struct deh_mgr *deh = (void *)data; - if (!hdeh_mgr) + if (!deh) return; - bridge_deh_notify(hdeh_mgr, DSP_MMUFAULT, 0); + bridge_deh_notify(deh, DSP_MMUFAULT, 0); } static irqreturn_t mmu_fault_isr(int irq, void *data) { - struct deh_mgr *deh_mgr_obj = data; + struct deh_mgr *deh = data; struct cfg_hostres *resources; - u32 dmmu_event_mask; + u32 event; - if (!deh_mgr_obj) + if (!deh) return IRQ_HANDLED; - resources = deh_mgr_obj->hbridge_context->resources; + resources = deh->hbridge_context->resources; if (!resources) { dev_dbg(bridge, "%s: Failed to get Host Resources\n", __func__); return IRQ_HANDLED; } - hw_mmu_event_status(resources->dw_dmmu_base, &dmmu_event_mask); - if (dmmu_event_mask == HW_MMU_TRANSLATION_FAULT) { - hw_mmu_fault_addr_read(resources->dw_dmmu_base, &deh_mgr_obj->fault_addr); - dev_info(bridge, "%s: status=0x%x, fault_addr=0x%x\n", __func__, - dmmu_event_mask, deh_mgr_obj->fault_addr); + hw_mmu_event_status(resources->dw_dmmu_base, &event); + if (event == HW_MMU_TRANSLATION_FAULT) { + hw_mmu_fault_addr_read(resources->dw_dmmu_base, &fault_addr); + dev_dbg(bridge, "%s: event=0x%x, fault_addr=0x%x\n", __func__, + event, fault_addr); /* * Schedule a DPC directly. In the future, it may be * necessary to check if DSP MMU fault is intended for * Bridge. */ - tasklet_schedule(&deh_mgr_obj->dpc_tasklet); + tasklet_schedule(&deh->dpc_tasklet); /* Disable the MMU events, else once we clear it will * start to raise INTs again */ @@ -110,11 +89,11 @@ static irqreturn_t mmu_fault_isr(int irq, void *data) return IRQ_HANDLED; } -dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, +int bridge_deh_create(struct deh_mgr **ret_deh, struct dev_object *hdev_obj) { - dsp_status status; - struct deh_mgr *deh_mgr; + int status; + struct deh_mgr *deh; struct bridge_dev_context *hbridge_context = NULL; /* Message manager will be created when a file is loaded, since @@ -123,29 +102,29 @@ dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, /* Get WMD context info. */ dev_get_bridge_context(hdev_obj, &hbridge_context); /* Allocate IO manager object: */ - deh_mgr = kzalloc(sizeof(struct deh_mgr), GFP_KERNEL); - if (!deh_mgr) { + deh = kzalloc(sizeof(*deh), GFP_KERNEL); + if (!deh) { status = -ENOMEM; goto err; } /* Create an NTFY object to manage notifications */ - deh_mgr->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL); - if (!deh_mgr->ntfy_obj) { + deh->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL); + if (!deh->ntfy_obj) { status = -ENOMEM; goto err; } - ntfy_init(deh_mgr->ntfy_obj); + ntfy_init(deh->ntfy_obj); /* Create a MMUfault DPC */ - tasklet_init(&deh_mgr->dpc_tasklet, mmu_fault_dpc, (u32) deh_mgr); + tasklet_init(&deh->dpc_tasklet, mmu_fault_dpc, (u32) deh); /* Fill in context structure */ - deh_mgr->hbridge_context = hbridge_context; + deh->hbridge_context = hbridge_context; /* Install ISR function for DSP MMU fault */ status = request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0, - "DspBridge\tiommu fault", deh_mgr); + "DspBridge\tiommu fault", deh); if (status < 0) goto err; @@ -157,33 +136,33 @@ dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, } omap_dm_timer_disable(timer); - *ret_deh_mgr = deh_mgr; + *ret_deh = deh; return 0; err: - bridge_deh_destroy(deh_mgr); - *ret_deh_mgr = NULL; + bridge_deh_destroy(deh); + *ret_deh = NULL; return status; } -dsp_status bridge_deh_destroy(struct deh_mgr *deh_mgr) +int bridge_deh_destroy(struct deh_mgr *deh) { - if (!deh_mgr) + if (!deh) return -EFAULT; /* If notification object exists, delete it */ - if (deh_mgr->ntfy_obj) { - ntfy_delete(deh_mgr->ntfy_obj); - kfree(deh_mgr->ntfy_obj); + if (deh->ntfy_obj) { + ntfy_delete(deh->ntfy_obj); + kfree(deh->ntfy_obj); } /* Disable DSP MMU fault */ - free_irq(INT_DSP_MMU_IRQ, deh_mgr); + free_irq(INT_DSP_MMU_IRQ, deh); /* Free DPC object */ - tasklet_kill(&deh_mgr->dpc_tasklet); + tasklet_kill(&deh->dpc_tasklet); /* Deallocate the DEH manager object */ - kfree(deh_mgr); + kfree(deh); /* The GPTimer is no longer needed */ omap_dm_timer_free(timer); @@ -192,18 +171,18 @@ dsp_status bridge_deh_destroy(struct deh_mgr *deh_mgr) return 0; } -dsp_status bridge_deh_register_notify(struct deh_mgr *deh_mgr, u32 event_mask, +int bridge_deh_register_notify(struct deh_mgr *deh, u32 event_mask, u32 notify_type, struct dsp_notification *hnotification) { - if (!deh_mgr) + if (!deh) return -EFAULT; if (event_mask) - return ntfy_register(deh_mgr->ntfy_obj, hnotification, + return ntfy_register(deh->ntfy_obj, hnotification, event_mask, notify_type); else - return ntfy_unregister(deh_mgr->ntfy_obj, hnotification); + return ntfy_unregister(deh->ntfy_obj, hnotification); } static void wait_for_timer(void) @@ -233,8 +212,7 @@ static void wait_for_timer(void) omap_dm_timer_disable(timer); } -static void mmu_fault_print_stack(struct bridge_dev_context *dev_context, - u32 fault_addr) +static void mmu_fault_print_stack(struct bridge_dev_context *dev_context) { struct cfg_hostres *resources; struct hw_mmu_map_attrs_t map_attrs = { @@ -270,51 +248,50 @@ static void mmu_fault_print_stack(struct bridge_dev_context *dev_context, free_page((unsigned long)dummy_va_addr); } -void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) +static inline const char *event_to_string(int event) +{ + switch (event) { + case DSP_SYSERROR: return "DSP_SYSERROR"; break; + case DSP_MMUFAULT: return "DSP_MMUFAULT"; break; + case DSP_PWRERROR: return "DSP_PWRERROR"; break; + case DSP_WDTOVERFLOW: return "DSP_WDTOVERFLOW"; break; + default: return "unkown event"; break; + } +} + +void bridge_deh_notify(struct deh_mgr *deh, int event, int info) { struct bridge_dev_context *dev_context; + const char *str = event_to_string(event); - if (!deh_mgr) + if (!deh) return; - dev_info(bridge, "%s: device exception\n", __func__); - dev_context = deh_mgr->hbridge_context; + dev_dbg(bridge, "%s: device exception", __func__); + dev_context = deh->hbridge_context; - switch (ulEventMask) { + switch (event) { case DSP_SYSERROR: - dev_err(bridge, "%s: %s, err_info = 0x%x\n", - __func__, "DSP_SYSERROR", dwErrInfo); + dev_err(bridge, "%s: %s, info=0x%x", __func__, + str, info); dump_dl_modules(dev_context); dump_dsp_stack(dev_context); break; case DSP_MMUFAULT: - dev_err(bridge, "%s: %s, err_info = 0x%x\n", - __func__, "DSP_MMUFAULT", dwErrInfo); - dev_info(bridge, "%s: %s, fault=0x%x\n", __func__, "DSP_MMUFAULT", - deh_mgr->fault_addr); - + dev_err(bridge, "%s: %s, addr=0x%x", __func__, + str, fault_addr); print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); - mmu_fault_print_stack(dev_context, deh_mgr->fault_addr); - break; -#ifdef CONFIG_BRIDGE_NTFY_PWRERR - case DSP_PWRERROR: - dev_err(bridge, "%s: %s, err_info = 0x%x\n", - __func__, "DSP_PWRERROR", dwErrInfo); - break; -#endif /* CONFIG_BRIDGE_NTFY_PWRERR */ - case DSP_WDTOVERFLOW: - dev_err(bridge, "%s: DSP_WDTOVERFLOW\n", __func__); + mmu_fault_print_stack(dev_context); break; default: - dev_dbg(bridge, "%s: Unknown Error, err_info = 0x%x\n", - __func__, dwErrInfo); + dev_err(bridge, "%s: %s", __func__, str); break; } /* Filter subsequent notifications when an error occurs */ if (dev_context->dw_brd_state != BRD_ERROR) { - ntfy_notify(deh_mgr->ntfy_obj, ulEventMask); + ntfy_notify(deh->ntfy_obj, event); #ifdef CONFIG_BRIDGE_RECOVERY bridge_recover_schedule(); #endif From patchwork Wed Jul 14 19:46:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maurus Cuelenaere X-Patchwork-Id: 112055 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6EJklZn004543 for ; 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Wed, 14 Jul 2010 12:46:43 -0700 (PDT) Received: from wim2160 (d54C4B918.access.telenet.be [84.196.185.24]) by mx.google.com with ESMTPS id v59sm901332eeh.10.2010.07.14.12.46.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Jul 2010 12:46:42 -0700 (PDT) Message-ID: <4c3e1422.d37b0e0a.7b5e.092d@mx.google.com> Received: by wim2160 (sSMTP sendmail emulation); Wed, 14 Jul 2010 21:46:40 +0200 Date: Wed, 14 Jul 2010 21:46:40 +0200 From: Maurus Cuelenaere Subject: [PATCH] ARM: OMAP3: Add S-Video output to IGEPv2 board To: linux-omap@vger.kernel.org, tony@atomide.com Cc: linux-arm-kernel@lists.infradead.org, eballetbo@iseebcn.com Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 14 Jul 2010 19:46:47 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d55c57b..3ec48bd 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -310,8 +310,16 @@ static struct omap_dss_device igep2_dvi_device = { .platform_disable = igep2_disable_dvi, }; +static struct omap_dss_device igep2_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +}; + static struct omap_dss_device *igep2_dss_devices[] = { - &igep2_dvi_device + &igep2_dvi_device, + &igep2_tv_device, }; static struct omap_dss_board_info igep2_dss_data = { @@ -328,6 +336,25 @@ static struct platform_device igep2_dss_device = { }, }; +static struct regulator_consumer_supply igep2_vdda_dac_supply = { + .supply = "vdda_dac", + .dev = &igep2_dss_device.dev, +}; + +/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ +static struct regulator_init_data igep2_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep2_vdda_dac_supply, +}; + static struct regulator_consumer_supply igep2_vpll2_supply = { .supply = "vdds_dsi", .dev = &igep2_dss_device.dev, @@ -429,7 +456,7 @@ static struct twl4030_platform_data igep2_twldata = { .vmmc1 = &igep2_vmmc1, .vmmc2 = &igep2_vmmc2, .vpll2 = &igep2_vpll2, - + .vdac = &igep2_vdac, }; static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = { From patchwork Fri Aug 6 07:05:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 117715 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o7674qY4025668 for ; Fri, 6 Aug 2010 07:04:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933738Ab0HFHEu (ORCPT ); Fri, 6 Aug 2010 03:04:50 -0400 Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:64009 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933077Ab0HFHEt (ORCPT ); Fri, 6 Aug 2010 03:04:49 -0400 Received: from muru.com ([72.249.23.125] helo=localhost.localdomain) by mho-01-ewr.mailhop.org with esmtpa (Exim 4.68) (envelope-from ) id 1OhGz2-000LJj-Ru; Fri, 06 Aug 2010 07:04:49 +0000 Received: from Mutt by mutt-smtp-wrapper.pl 1.2 (www.zdo.com/articles/mutt-smtp-wrapper.shtml) X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 72.249.23.125 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX18ZWgFPouoUFWUs+PnY4j4Y Date: Fri, 6 Aug 2010 10:05:20 +0300 From: Tony Lindgren To: Kevin Hilman Cc: "Nayak, Rajendra" , "linux-omap@vger.kernel.org" Subject: [PATCH] omap: Fix sev instruction usage for multi-omap Message-ID: <20100806070519.GB23778@atomide.com> References: <8739uu9em0.fsf@deeprootsystems.com> <5A47E75E594F054BAF48C5E4FC4B92AB0323E6947D@dbde02.ent.ti.com> <87tyn8ptkl.fsf@deeprootsystems.com> <20100806070301.GA23778@atomide.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20100806070301.GA23778@atomide.com> User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 06 Aug 2010 07:04:52 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 63b2d88..88d3a1e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o +AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a # Functions loaded to SRAM diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index af3c20c..9e9f70e 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -102,8 +102,7 @@ static void __init wakeup_secondary(void) * Send a 'sev' to wake the secondary core from WFE. * Drain the outstanding writes to memory */ - dsb(); - set_event(); + dsb_sev(); mb(); } diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index 6a3ff65..5177a9c 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h @@ -19,13 +19,6 @@ #include -/* - * set_event() is used to wake up secondary core from wfe using sev. ROM - * code puts the second core into wfe(standby). - * - */ -#define set_event() __asm__ __volatile__ ("sev" : : : "memory") - /* Needed for secondary core boot */ extern void omap_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); From patchwork Sun May 16 15:45:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99970 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkL0O025236 for ; Sun, 16 May 2010 15:46:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753292Ab0EPPqW (ORCPT ); Sun, 16 May 2010 11:46:22 -0400 Received: from fg-out-1718.google.com ([72.14.220.159]:5081 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753268Ab0EPPqV (ORCPT ); Sun, 16 May 2010 11:46:21 -0400 Received: by fg-out-1718.google.com with SMTP id d23so2359940fga.1 for ; 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Sun, 16 May 2010 08:46:20 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 06/14] dspbridge: mmu: add hw_mmu_tlb_flush_all() Date: Sun, 16 May 2010 18:45:57 +0300 Message-Id: <1274024765-21076-7-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:23 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index 8a3eff9..d00eaaa 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -74,8 +74,6 @@ #define PAGES_II_LVL_TABLE 512 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT) -#define MMU_GFLUSH 0x60 - /* Forward Declarations: */ static dsp_status bridge_brd_monitor(struct bridge_dev_context *dev_context); static dsp_status bridge_brd_read(struct bridge_dev_context *dev_context, @@ -216,18 +214,13 @@ static struct bridge_drv_interface drv_interface_fxns = { bridge_msg_set_queue_id, }; -static inline void tlb_flush_all(const void __iomem *base) -{ - __raw_writeb(__raw_readb(base + MMU_GFLUSH) | 1, base + MMU_GFLUSH); -} - static inline void flush_all(struct bridge_dev_context *dev_context) { if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION || dev_context->dw_brd_state == BRD_HIBERNATION) wake_dsp(dev_context, NULL); - tlb_flush_all(dev_context->dw_dsp_mmu_base); + hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base); } static void bad_page_dump(u32 pa, struct page *pg) diff --git a/drivers/dsp/bridge/hw/hw_mmu.c b/drivers/dsp/bridge/hw/hw_mmu.c index 965b659..e593358 100644 --- a/drivers/dsp/bridge/hw/hw_mmu.c +++ b/drivers/dsp/bridge/hw/hw_mmu.c @@ -35,6 +35,7 @@ #define MMU_SMALL_PAGE_MASK 0xFFFFF000 #define MMU_LOAD_TLB 0x00000001 +#define MMU_GFLUSH 0x60 /* * hw_mmu_page_size_t: Enumerated Type used to specify the MMU Page Size(SLSS) @@ -585,3 +586,8 @@ static hw_status mmu_set_ram_entry(const void __iomem *baseAddress, return status; } + +void hw_mmu_tlb_flush_all(const void __iomem *base) +{ + __raw_writeb(1, base + MMU_GFLUSH); +} diff --git a/drivers/dsp/bridge/hw/hw_mmu.h b/drivers/dsp/bridge/hw/hw_mmu.h index 9b13468..0436974 100644 --- a/drivers/dsp/bridge/hw/hw_mmu.h +++ b/drivers/dsp/bridge/hw/hw_mmu.h @@ -97,6 +97,8 @@ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 page_size, u32 virtualAddr); +void hw_mmu_tlb_flush_all(const void __iomem *base); + static inline u32 hw_mmu_pte_addr_l1(u32 L1_base, u32 va) { u32 pte_addr; From patchwork Wed Mar 17 22:42:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Olaya, Margarita" X-Patchwork-Id: 86564 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2HMgdmp021239 for ; Wed, 17 Mar 2010 22:42:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756203Ab0CQWmr (ORCPT ); Wed, 17 Mar 2010 18:42:47 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51530 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755278Ab0CQWmq convert rfc822-to-8bit (ORCPT ); Wed, 17 Mar 2010 18:42:46 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2HMgdYA009714 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 17 Mar 2010 17:42:40 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o2HMgd1o001022; Wed, 17 Mar 2010 17:42:39 -0500 (CDT) Received: from dlee74.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2HMgdeL000118; Wed, 17 Mar 2010 17:42:39 -0500 (CDT) Received: from dlee06.ent.ti.com ([157.170.170.11]) by dlee74.ent.ti.com ([157.170.170.8]) with mapi; Wed, 17 Mar 2010 17:42:39 -0500 From: "Olaya, Margarita" To: "alsa-devel@alsa-project.org" , "linux-omap@vger.kernel.org" CC: "broonie@opensource.wolfsonmicro.com" , "lrg@slimlogic.co.uk" Date: Wed, 17 Mar 2010 17:42:38 -0500 Subject: [PATCHv6 2/2] ASoC: TWL6040: Add twl6040 codec driver Thread-Topic: [PATCHv6 2/2] ASoC: TWL6040: Add twl6040 codec driver Thread-Index: AcrGIyVqifUAoJd7TXKXRlxaUDg2Pg== Message-ID: <1889FA7136B567478A67D4B0F85B0CCE662AC372@dlee06.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 17 Mar 2010 22:42:48 +0000 (UTC) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 16c47ed..398cbb0 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -35,6 +35,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_TPA6130A2 if I2C select SND_SOC_TLV320DAC33 if I2C select SND_SOC_TWL4030 if TWL4030_CORE + select SND_SOC_TWL6040 if TWL4030_CORE select SND_SOC_UDA134X select SND_SOC_UDA1380 if I2C select SND_SOC_WM2000 if I2C @@ -168,6 +169,9 @@ config SND_SOC_TWL4030 select TWL4030_CODEC tristate +config SND_SOC_TWL6040 + tristate + config SND_SOC_UDA134X tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 6981777..98bd10c 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -22,6 +22,7 @@ snd-soc-tlv320aic26-objs := tlv320aic26.o snd-soc-tlv320aic3x-objs := tlv320aic3x.o snd-soc-tlv320dac33-objs := tlv320dac33.o snd-soc-twl4030-objs := twl4030.o +snd-soc-twl6040-objs := twl6040.o snd-soc-uda134x-objs := uda134x.o snd-soc-uda1380-objs := uda1380.o snd-soc-wm8350-objs := wm8350.o @@ -85,6 +86,7 @@ obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c new file mode 100644 index 0000000..b90bc60 --- /dev/null +++ b/sound/soc/codecs/twl6040.c @@ -0,0 +1,1227 @@ +/* + * ALSA SoC TWL6040 codec driver + * + * Author: Misael Lopez Cruz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "twl6040.h" + +#define TWL6040_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) +#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) + +/* codec private data */ +struct twl6040_data { + struct snd_soc_codec codec; + int audpwron; + int naudint; + int codec_powered; + int pll; + int non_lp; + unsigned int sysclk; + struct snd_pcm_hw_constraint_list *sysclk_constraints; + struct completion ready; +}; + +/* + * twl6040 register cache & default register settings + */ +static const u8 twl6040_reg[TWL6040_CACHEREGNUM] = { + 0x00, /* not used 0x00 */ + 0x4B, /* TWL6040_ASICID (ro) 0x01 */ + 0x00, /* TWL6040_ASICREV (ro) 0x02 */ + 0x00, /* TWL6040_INTID 0x03 */ + 0x00, /* TWL6040_INTMR 0x04 */ + 0x00, /* TWL6040_NCPCTRL 0x05 */ + 0x00, /* TWL6040_LDOCTL 0x06 */ + 0x60, /* TWL6040_HPPLLCTL 0x07 */ + 0x00, /* TWL6040_LPPLLCTL 0x08 */ + 0x4A, /* TWL6040_LPPLLDIV 0x09 */ + 0x00, /* TWL6040_AMICBCTL 0x0A */ + 0x00, /* TWL6040_DMICBCTL 0x0B */ + 0x18, /* TWL6040_MICLCTL 0x0C - No input selected on Left Mic */ + 0x18, /* TWL6040_MICRCTL 0x0D - No input selected on Right Mic */ + 0x00, /* TWL6040_MICGAIN 0x0E */ + 0x1B, /* TWL6040_LINEGAIN 0x0F */ + 0x00, /* TWL6040_HSLCTL 0x10 */ + 0x00, /* TWL6040_HSRCTL 0x11 */ + 0x00, /* TWL6040_HSGAIN 0x12 */ + 0x00, /* TWL6040_EARCTL 0x13 */ + 0x00, /* TWL6040_HFLCTL 0x14 */ + 0x00, /* TWL6040_HFLGAIN 0x15 */ + 0x00, /* TWL6040_HFRCTL 0x16 */ + 0x00, /* TWL6040_HFRGAIN 0x17 */ + 0x00, /* TWL6040_VIBCTLL 0x18 */ + 0x00, /* TWL6040_VIBDATL 0x19 */ + 0x00, /* TWL6040_VIBCTLR 0x1A */ + 0x00, /* TWL6040_VIBDATR 0x1B */ + 0x00, /* TWL6040_HKCTL1 0x1C */ + 0x00, /* TWL6040_HKCTL2 0x1D */ + 0x00, /* TWL6040_GPOCTL 0x1E */ + 0x00, /* TWL6040_ALB 0x1F */ + 0x00, /* TWL6040_DLB 0x20 */ + 0x00, /* not used 0x21 */ + 0x00, /* not used 0x22 */ + 0x00, /* not used 0x23 */ + 0x00, /* not used 0x24 */ + 0x00, /* not used 0x25 */ + 0x00, /* not used 0x26 */ + 0x00, /* not used 0x27 */ + 0x00, /* TWL6040_TRIM1 0x28 */ + 0x00, /* TWL6040_TRIM2 0x29 */ + 0x00, /* TWL6040_TRIM3 0x2A */ + 0x00, /* TWL6040_HSOTRIM 0x2B */ + 0x00, /* TWL6040_HFOTRIM 0x2C */ + 0x09, /* TWL6040_ACCCTL 0x2D */ + 0x00, /* TWL6040_STATUS (ro) 0x2E */ +}; + +/* + * twl6040 vio/gnd registers: + * registers under vio/gnd supply can be accessed + * before the power-up sequence, after NRESPWRON goes high + */ +static const int twl6040_vio_reg[TWL6040_VIOREGNUM] = { + TWL6040_REG_ASICID, + TWL6040_REG_ASICREV, + TWL6040_REG_INTID, + TWL6040_REG_INTMR, + TWL6040_REG_NCPCTL, + TWL6040_REG_LDOCTL, + TWL6040_REG_AMICBCTL, + TWL6040_REG_DMICBCTL, + TWL6040_REG_HKCTL1, + TWL6040_REG_HKCTL2, + TWL6040_REG_GPOCTL, + TWL6040_REG_TRIM1, + TWL6040_REG_TRIM2, + TWL6040_REG_TRIM3, + TWL6040_REG_HSOTRIM, + TWL6040_REG_HFOTRIM, + TWL6040_REG_ACCCTL, + TWL6040_REG_STATUS, +}; + +/* + * twl6040 vdd/vss registers: + * registers under vdd/vss supplies can only be accessed + * after the power-up sequence + */ +static const int twl6040_vdd_reg[TWL6040_VDDREGNUM] = { + TWL6040_REG_HPPLLCTL, + TWL6040_REG_LPPLLCTL, + TWL6040_REG_LPPLLDIV, + TWL6040_REG_MICLCTL, + TWL6040_REG_MICRCTL, + TWL6040_REG_MICGAIN, + TWL6040_REG_LINEGAIN, + TWL6040_REG_HSLCTL, + TWL6040_REG_HSRCTL, + TWL6040_REG_HSGAIN, + TWL6040_REG_EARCTL, + TWL6040_REG_HFLCTL, + TWL6040_REG_HFLGAIN, + TWL6040_REG_HFRCTL, + TWL6040_REG_HFRGAIN, + TWL6040_REG_VIBCTLL, + TWL6040_REG_VIBDATL, + TWL6040_REG_VIBCTLR, + TWL6040_REG_VIBDATR, + TWL6040_REG_ALB, + TWL6040_REG_DLB, +}; + +/* + * read twl6040 register cache + */ +static inline unsigned int twl6040_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 *cache = codec->reg_cache; + + if (reg >= TWL6040_CACHEREGNUM) + return -EIO; + + return cache[reg]; +} + +/* + * write twl6040 register cache + */ +static inline void twl6040_write_reg_cache(struct snd_soc_codec *codec, + u8 reg, u8 value) +{ + u8 *cache = codec->reg_cache; + + if (reg >= TWL6040_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * read from twl6040 hardware register + */ +static int twl6040_read_reg_volatile(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 value; + + if (reg >= TWL6040_CACHEREGNUM) + return -EIO; + + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg); + twl6040_write_reg_cache(codec, reg, value); + + return value; +} + +/* + * write to the twl6040 register space + */ +static int twl6040_write(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + if (reg >= TWL6040_CACHEREGNUM) + return -EIO; + + twl6040_write_reg_cache(codec, reg, value); + return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); +} + +static void twl6040_init_vio_regs(struct snd_soc_codec *codec) +{ + u8 *cache = codec->reg_cache; + int reg, i; + + /* allow registers to be accessed by i2c */ + twl6040_write(codec, TWL6040_REG_ACCCTL, cache[TWL6040_REG_ACCCTL]); + + for (i = 0; i < TWL6040_VIOREGNUM; i++) { + reg = twl6040_vio_reg[i]; + /* skip read-only registers (ASICID, ASICREV, STATUS) */ + switch (reg) { + case TWL6040_REG_ASICID: + case TWL6040_REG_ASICREV: + case TWL6040_REG_STATUS: + continue; + default: + break; + } + twl6040_write(codec, reg, cache[reg]); + } +} + +static void twl6040_init_vdd_regs(struct snd_soc_codec *codec) +{ + u8 *cache = codec->reg_cache; + int reg, i; + + for (i = 0; i < TWL6040_VDDREGNUM; i++) { + reg = twl6040_vdd_reg[i]; + twl6040_write(codec, reg, cache[reg]); + } +} + +/* twl6040 codec manual power-up sequence */ +static void twl6040_power_up(struct snd_soc_codec *codec) +{ + u8 ncpctl, ldoctl, lppllctl, accctl; + + ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL); + ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL); + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL); + + /* enable reference system */ + ldoctl |= TWL6040_REFENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + msleep(10); + /* enable internal oscillator */ + ldoctl |= TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(10); + /* enable high-side ldo */ + ldoctl |= TWL6040_HSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* enable negative charge pump */ + ncpctl |= TWL6040_NCPENA | TWL6040_NCPOPEN; + twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl); + udelay(488); + /* enable low-side ldo */ + ldoctl |= TWL6040_LSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* enable low-power pll */ + lppllctl |= TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + /* reset state machine */ + accctl |= TWL6040_RESETSPLIT; + twl6040_write(codec, TWL6040_REG_ACCCTL, accctl); + mdelay(5); + accctl &= ~TWL6040_RESETSPLIT; + twl6040_write(codec, TWL6040_REG_ACCCTL, accctl); + /* disable internal oscillator */ + ldoctl &= ~TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); +} + +/* twl6040 codec manual power-down sequence */ +static void twl6040_power_down(struct snd_soc_codec *codec) +{ + u8 ncpctl, ldoctl, lppllctl, accctl; + + ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL); + ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL); + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL); + + /* enable internal oscillator */ + ldoctl |= TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(10); + /* disable low-power pll */ + lppllctl &= ~TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + /* disable low-side ldo */ + ldoctl &= ~TWL6040_LSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* disable negative charge pump */ + ncpctl &= ~(TWL6040_NCPENA | TWL6040_NCPOPEN); + twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl); + udelay(488); + /* disable high-side ldo */ + ldoctl &= ~TWL6040_HSLDOENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + udelay(244); + /* disable internal oscillator */ + ldoctl &= ~TWL6040_OSCENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + /* disable reference system */ + ldoctl &= ~TWL6040_REFENA; + twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); + msleep(10); +} + +/* set headset dac and driver power mode */ +static int headset_power_mode(struct snd_soc_codec *codec, int high_perf) +{ + int hslctl, hsrctl; + int mask = TWL6040_HSDRVMODEL | TWL6040_HSDACMODEL; + + hslctl = twl6040_read_reg_cache(codec, TWL6040_REG_HSLCTL); + hsrctl = twl6040_read_reg_cache(codec, TWL6040_REG_HSRCTL); + + if (high_perf) { + hslctl &= ~mask; + hsrctl &= ~mask; + } else { + hslctl |= mask; + hsrctl |= mask; + } + + twl6040_write(codec, TWL6040_REG_HSLCTL, hslctl); + twl6040_write(codec, TWL6040_REG_HSRCTL, hsrctl); + + return 0; +} + +static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct twl6040_data *priv = codec->private_data; + + if (SND_SOC_DAPM_EVENT_ON(event)) + priv->non_lp++; + else + priv->non_lp--; + + return 0; +} + +/* audio interrupt handler */ +static irqreturn_t twl6040_naudint_handler(int irq, void *data) +{ + struct snd_soc_codec *codec = data; + struct twl6040_data *priv = codec->private_data; + u8 intid; + + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); + + switch (intid) { + case TWL6040_THINT: + dev_alert(codec->dev, "die temp over-limit detection\n"); + break; + case TWL6040_PLUGINT: + case TWL6040_UNPLUGINT: + case TWL6040_HOOKINT: + break; + case TWL6040_HFINT: + dev_alert(codec->dev, "hf drivers over current detection\n"); + break; + case TWL6040_VIBINT: + dev_alert(codec->dev, "vib drivers over current detection\n"); + break; + case TWL6040_READYINT: + complete(&priv->ready); + break; + default: + dev_err(codec->dev, "unknown audio interrupt %d\n", intid); + break; + } + + return IRQ_HANDLED; +} + +/* + * MICATT volume control: + * from -6 to 0 dB in 6 dB steps + */ +static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0); + +/* + * MICGAIN volume control: + * from 6 to 30 dB in 6 dB steps + */ +static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0); + +/* + * HSGAIN volume control: + * from -30 to 0 dB in 2 dB steps + */ +static DECLARE_TLV_DB_SCALE(hs_tlv, -3000, 200, 0); + +/* + * HFGAIN volume control: + * from -52 to 6 dB in 2 dB steps + */ +static DECLARE_TLV_DB_SCALE(hf_tlv, -5200, 200, 0); + +/* Left analog microphone selection */ +static const char *twl6040_amicl_texts[] = + {"Headset Mic", "Main Mic", "Aux/FM Left", "Off"}; + +/* Right analog microphone selection */ +static const char *twl6040_amicr_texts[] = + {"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"}; + +static const struct soc_enum twl6040_enum[] = { + SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 3, twl6040_amicl_texts), + SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 3, twl6040_amicr_texts), +}; + +static const struct snd_kcontrol_new amicl_control = + SOC_DAPM_ENUM("Route", twl6040_enum[0]); + +static const struct snd_kcontrol_new amicr_control = + SOC_DAPM_ENUM("Route", twl6040_enum[1]); + +/* Headset DAC playback switches */ +static const struct snd_kcontrol_new hsdacl_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSLCTL, 5, 1, 0); + +static const struct snd_kcontrol_new hsdacr_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSRCTL, 5, 1, 0); + +/* Handsfree DAC playback switches */ +static const struct snd_kcontrol_new hfdacl_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 2, 1, 0); + +static const struct snd_kcontrol_new hfdacr_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 2, 1, 0); + +/* Headset driver switches */ +static const struct snd_kcontrol_new hsl_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSLCTL, 2, 1, 0); + +static const struct snd_kcontrol_new hsr_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSRCTL, 2, 1, 0); + +/* Handsfree driver switches */ +static const struct snd_kcontrol_new hfl_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 4, 1, 0); + +static const struct snd_kcontrol_new hfr_driver_switch_controls = + SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 4, 1, 0); + +static const struct snd_kcontrol_new twl6040_snd_controls[] = { + /* Capture gains */ + SOC_DOUBLE_TLV("Capture Preamplifier Volume", + TWL6040_REG_MICGAIN, 6, 7, 1, 1, mic_preamp_tlv), + SOC_DOUBLE_TLV("Capture Volume", + TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv), + + /* Playback gains */ + SOC_DOUBLE_TLV("Headset Playback Volume", + TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv), + SOC_DOUBLE_R_TLV("Handsfree Playback Volume", + TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv), + +}; + +static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = { + /* Inputs */ + SND_SOC_DAPM_INPUT("MAINMIC"), + SND_SOC_DAPM_INPUT("HSMIC"), + SND_SOC_DAPM_INPUT("SUBMIC"), + SND_SOC_DAPM_INPUT("AFML"), + SND_SOC_DAPM_INPUT("AFMR"), + + /* Outputs */ + SND_SOC_DAPM_OUTPUT("HSOL"), + SND_SOC_DAPM_OUTPUT("HSOR"), + SND_SOC_DAPM_OUTPUT("HFL"), + SND_SOC_DAPM_OUTPUT("HFR"), + + /* Analog input muxes for the capture amplifiers */ + SND_SOC_DAPM_MUX("Analog Left Capture Route", + SND_SOC_NOPM, 0, 0, &amicl_control), + SND_SOC_DAPM_MUX("Analog Right Capture Route", + SND_SOC_NOPM, 0, 0, &amicr_control), + + /* Analog capture PGAs */ + SND_SOC_DAPM_PGA("MicAmpL", + TWL6040_REG_MICLCTL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("MicAmpR", + TWL6040_REG_MICRCTL, 0, 0, NULL, 0), + + /* ADCs */ + SND_SOC_DAPM_ADC("ADC Left", "Left Front Capture", + TWL6040_REG_MICLCTL, 2, 0), + SND_SOC_DAPM_ADC("ADC Right", "Right Front Capture", + TWL6040_REG_MICRCTL, 2, 0), + + /* Microphone bias */ + SND_SOC_DAPM_MICBIAS("Headset Mic Bias", + TWL6040_REG_AMICBCTL, 0, 0), + SND_SOC_DAPM_MICBIAS("Main Mic Bias", + TWL6040_REG_AMICBCTL, 4, 0), + SND_SOC_DAPM_MICBIAS("Digital Mic1 Bias", + TWL6040_REG_DMICBCTL, 0, 0), + SND_SOC_DAPM_MICBIAS("Digital Mic2 Bias", + TWL6040_REG_DMICBCTL, 4, 0), + + /* DACs */ + SND_SOC_DAPM_DAC("HSDAC Left", "Headset Playback", + TWL6040_REG_HSLCTL, 0, 0), + SND_SOC_DAPM_DAC("HSDAC Right", "Headset Playback", + TWL6040_REG_HSRCTL, 0, 0), + SND_SOC_DAPM_DAC_E("HFDAC Left", "Handsfree Playback", + TWL6040_REG_HFLCTL, 0, 0, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_DAC_E("HFDAC Right", "Handsfree Playback", + TWL6040_REG_HFRCTL, 0, 0, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + /* Analog playback switches */ + SND_SOC_DAPM_SWITCH("HSDAC Left Playback", + SND_SOC_NOPM, 0, 0, &hsdacl_switch_controls), + SND_SOC_DAPM_SWITCH("HSDAC Right Playback", + SND_SOC_NOPM, 0, 0, &hsdacr_switch_controls), + SND_SOC_DAPM_SWITCH("HFDAC Left Playback", + SND_SOC_NOPM, 0, 0, &hfdacl_switch_controls), + SND_SOC_DAPM_SWITCH("HFDAC Right Playback", + SND_SOC_NOPM, 0, 0, &hfdacr_switch_controls), + + SND_SOC_DAPM_SWITCH("Headset Left Driver", + SND_SOC_NOPM, 0, 0, &hsl_driver_switch_controls), + SND_SOC_DAPM_SWITCH("Headset Right Driver", + SND_SOC_NOPM, 0, 0, &hsr_driver_switch_controls), + SND_SOC_DAPM_SWITCH_E("Handsfree Left Driver", + SND_SOC_NOPM, 0, 0, &hfl_driver_switch_controls, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SWITCH_E("Handsfree Right Driver", + SND_SOC_NOPM, 0, 0, &hfr_driver_switch_controls, + twl6040_power_mode_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + /* Analog playback PGAs */ + SND_SOC_DAPM_PGA("HFDAC Left PGA", + TWL6040_REG_HFLCTL, 1, 0, NULL, 0), + SND_SOC_DAPM_PGA("HFDAC Right PGA", + TWL6040_REG_HFRCTL, 1, 0, NULL, 0), + +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* Capture path */ + {"Analog Left Capture Route", "Headset Mic", "HSMIC"}, + {"Analog Left Capture Route", "Main Mic", "MAINMIC"}, + {"Analog Left Capture Route", "Aux/FM Left", "AFML"}, + + {"Analog Right Capture Route", "Headset Mic", "HSMIC"}, + {"Analog Right Capture Route", "Sub Mic", "SUBMIC"}, + {"Analog Right Capture Route", "Aux/FM Right", "AFMR"}, + + {"MicAmpL", NULL, "Analog Left Capture Route"}, + {"MicAmpR", NULL, "Analog Right Capture Route"}, + + {"ADC Left", NULL, "MicAmpL"}, + {"ADC Right", NULL, "MicAmpR"}, + + /* Headset playback path */ + {"HSDAC Left Playback", "Switch", "HSDAC Left"}, + {"HSDAC Right Playback", "Switch", "HSDAC Right"}, + + {"Headset Left Driver", "Switch", "HSDAC Left Playback"}, + {"Headset Right Driver", "Switch", "HSDAC Right Playback"}, + + {"HSOL", NULL, "Headset Left Driver"}, + {"HSOR", NULL, "Headset Right Driver"}, + + /* Handsfree playback path */ + {"HFDAC Left Playback", "Switch", "HFDAC Left"}, + {"HFDAC Right Playback", "Switch", "HFDAC Right"}, + + {"HFDAC Left PGA", NULL, "HFDAC Left Playback"}, + {"HFDAC Right PGA", NULL, "HFDAC Right Playback"}, + + {"Handsfree Left Driver", "Switch", "HFDAC Left PGA"}, + {"Handsfree Right Driver", "Switch", "HFDAC Right PGA"}, + + {"HFL", NULL, "Handsfree Left Driver"}, + {"HFR", NULL, "Handsfree Right Driver"}, +}; + +static int twl6040_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, twl6040_dapm_widgets, + ARRAY_SIZE(twl6040_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(codec); + + return 0; +} + +static int twl6040_power_up_completion(struct snd_soc_codec *codec, + int naudint) +{ + struct twl6040_data *priv = codec->private_data; + int time_left; + u8 intid; + + time_left = wait_for_completion_timeout(&priv->ready, + msecs_to_jiffies(48)); + + if (!time_left) { + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, + TWL6040_REG_INTID); + if (!(intid & TWL6040_READYINT)) { + dev_err(codec->dev, "timeout waiting for READYINT\n"); + return -ETIMEDOUT; + } + } + + priv->codec_powered = 1; + + return 0; +} + +static int twl6040_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct twl6040_data *priv = codec->private_data; + int audpwron = priv->audpwron; + int naudint = priv->naudint; + int ret; + + switch (level) { + case SND_SOC_BIAS_ON: + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + if (priv->codec_powered) + break; + + if (gpio_is_valid(audpwron)) { + /* use AUDPWRON line */ + gpio_set_value(audpwron, 1); + + /* wait for power-up completion */ + ret = twl6040_power_up_completion(codec, naudint); + if (ret) + return ret; + + /* sync registers updated during power-up sequence */ + twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL); + twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL); + twl6040_read_reg_volatile(codec, TWL6040_REG_LPPLLCTL); + } else { + /* use manual power-up sequence */ + twl6040_power_up(codec); + priv->codec_powered = 1; + } + + /* initialize vdd/vss registers with reg_cache */ + twl6040_init_vdd_regs(codec); + break; + case SND_SOC_BIAS_OFF: + if (!priv->codec_powered) + break; + + if (gpio_is_valid(audpwron)) { + /* use AUDPWRON line */ + gpio_set_value(audpwron, 0); + + /* power-down sequence latency */ + udelay(500); + + /* sync registers updated during power-down sequence */ + twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL); + twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL); + twl6040_write_reg_cache(codec, TWL6040_REG_LPPLLCTL, + 0x00); + } else { + /* use manual power-down sequence */ + twl6040_power_down(codec); + } + + priv->codec_powered = 0; + break; + } + + codec->bias_level = level; + + return 0; +} + +/* set of rates for each pll: low-power and high-performance */ + +static unsigned int lp_rates[] = { + 88200, + 96000, +}; + +static struct snd_pcm_hw_constraint_list lp_constraints = { + .count = ARRAY_SIZE(lp_rates), + .list = lp_rates, +}; + +static unsigned int hp_rates[] = { + 96000, +}; + +static struct snd_pcm_hw_constraint_list hp_constraints = { + .count = ARRAY_SIZE(hp_rates), + .list = hp_rates, +}; + +static int twl6040_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct twl6040_data *priv = codec->private_data; + + if (!priv->sysclk) { + dev_err(codec->dev, + "no mclk configured, call set_sysclk() on init\n"); + return -EINVAL; + } + + /* + * capture is not supported at 17.64 MHz, + * it's reserved for headset low-power playback scenario + */ + if ((priv->sysclk == 17640000) && substream->stream) { + dev_err(codec->dev, + "capture mode is not supported at %dHz\n", + priv->sysclk); + return -EINVAL; + } + + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + priv->sysclk_constraints); + + return 0; +} + +static int twl6040_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct twl6040_data *priv = codec->private_data; + u8 lppllctl; + int rate; + + /* nothing to do for high-perf pll, it supports only 48 kHz */ + if (priv->pll == TWL6040_HPPLL_ID) + return 0; + + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + + rate = params_rate(params); + switch (rate) { + case 88200: + lppllctl |= TWL6040_LPLLFIN; + priv->sysclk = 17640000; + break; + case 96000: + lppllctl &= ~TWL6040_LPLLFIN; + priv->sysclk = 19200000; + break; + default: + dev_err(codec->dev, "unsupported rate %d\n", rate); + return -EINVAL; + } + + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + + return 0; +} + +static int twl6040_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct twl6040_data *priv = codec->private_data; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + /* + * low-power playback mode is restricted + * for headset path only + */ + if ((priv->sysclk == 17640000) && priv->non_lp) { + dev_err(codec->dev, + "some enabled paths aren't supported at %dHz\n", + priv->sysclk); + return -EPERM; + } + break; + default: + break; + } + + return 0; +} + +static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct twl6040_data *priv = codec->private_data; + u8 hppllctl, lppllctl; + + hppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_HPPLLCTL); + lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + + switch (clk_id) { + case TWL6040_SYSCLK_SEL_LPPLL: + switch (freq) { + case 32768: + /* headset dac and driver must be in low-power mode */ + headset_power_mode(codec, 0); + + /* clk32k input requires low-power pll */ + lppllctl |= TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + mdelay(5); + lppllctl &= ~TWL6040_HPLLSEL; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + hppllctl &= ~TWL6040_HPLLENA; + twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl); + break; + default: + dev_err(codec->dev, "unknown mclk freq %d\n", freq); + return -EINVAL; + } + + /* lppll divider */ + switch (priv->sysclk) { + case 17640000: + lppllctl |= TWL6040_LPLLFIN; + break; + case 19200000: + lppllctl &= ~TWL6040_LPLLFIN; + break; + default: + /* sysclk not yet configured */ + lppllctl &= ~TWL6040_LPLLFIN; + priv->sysclk = 19200000; + break; + } + + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + + priv->pll = TWL6040_LPPLL_ID; + priv->sysclk_constraints = &lp_constraints; + break; + case TWL6040_SYSCLK_SEL_HPPLL: + hppllctl &= ~TWL6040_MCLK_MSK; + + switch (freq) { + case 12000000: + /* mclk input, pll enabled */ + hppllctl |= TWL6040_MCLK_12000KHZ | + TWL6040_HPLLSQRBP | + TWL6040_HPLLENA; + break; + case 19200000: + /* mclk input, pll disabled */ + hppllctl |= TWL6040_MCLK_19200KHZ | + TWL6040_HPLLSQRBP | + TWL6040_HPLLBP; + break; + case 26000000: + /* mclk input, pll enabled */ + hppllctl |= TWL6040_MCLK_26000KHZ | + TWL6040_HPLLSQRBP | + TWL6040_HPLLENA; + break; + case 38400000: + /* clk slicer, pll disabled */ + hppllctl |= TWL6040_MCLK_38400KHZ | + TWL6040_HPLLSQRENA | + TWL6040_HPLLBP; + break; + default: + dev_err(codec->dev, "unknown mclk freq %d\n", freq); + return -EINVAL; + } + + /* headset dac and driver must be in high-performance mode */ + headset_power_mode(codec, 1); + + twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl); + udelay(500); + lppllctl |= TWL6040_HPLLSEL; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + lppllctl &= ~TWL6040_LPLLENA; + twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + + /* high-performance pll can provide only 19.2 MHz */ + priv->pll = TWL6040_HPPLL_ID; + priv->sysclk = 19200000; + priv->sysclk_constraints = &hp_constraints; + break; + default: + dev_err(codec->dev, "unknown clk_id %d\n", clk_id); + return -EINVAL; + } + + return 0; +} + +static struct snd_soc_dai_ops twl6040_dai_ops = { + .startup = twl6040_startup, + .hw_params = twl6040_hw_params, + .trigger = twl6040_trigger, + .set_sysclk = twl6040_set_dai_sysclk, +}; + +struct snd_soc_dai twl6040_dai = { + .name = "twl6040", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 4, + .rates = TWL6040_RATES, + .formats = TWL6040_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = TWL6040_RATES, + .formats = TWL6040_FORMATS, + }, + .ops = &twl6040_dai_ops, +}; +EXPORT_SYMBOL_GPL(twl6040_dai); + +#ifdef CONFIG_PM +static int twl6040_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int twl6040_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + twl6040_set_bias_level(codec, codec->suspend_bias_level); + + return 0; +} +#else +#define twl6040_suspend NULL +#define twl6040_resume NULL +#endif + +static struct snd_soc_codec *twl6040_codec; + +static int twl6040_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + int ret = 0; + + BUG_ON(!twl6040_codec); + + codec = twl6040_codec; + socdev->card->codec = codec; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(&pdev->dev, "failed to create pcms\n"); + return ret; + } + + snd_soc_add_controls(codec, twl6040_snd_controls, + ARRAY_SIZE(twl6040_snd_controls)); + twl6040_add_widgets(codec); + + if (ret < 0) { + dev_err(&pdev->dev, "failed to register card\n"); + goto card_err; + } + + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + return ret; +} + +static int twl6040_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_twl6040 = { + .probe = twl6040_probe, + .remove = twl6040_remove, + .suspend = twl6040_suspend, + .resume = twl6040_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_twl6040); + +static int __devinit twl6040_codec_probe(struct platform_device *pdev) +{ + struct twl4030_codec_data *twl_codec = pdev->dev.platform_data; + struct snd_soc_codec *codec; + struct twl6040_data *priv; + int audpwron, naudint; + int ret = 0; + + priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + if (twl_codec) { + audpwron = twl_codec->audpwron_gpio; + naudint = twl_codec->naudint_irq; + } else { + audpwron = -EINVAL; + naudint = 0; + } + + priv->audpwron = audpwron; + priv->naudint = naudint; + + codec = &priv->codec; + codec->dev = &pdev->dev; + twl6040_dai.dev = &pdev->dev; + + codec->name = "twl6040"; + codec->owner = THIS_MODULE; + codec->read = twl6040_read_reg_cache; + codec->write = twl6040_write; + codec->set_bias_level = twl6040_set_bias_level; + codec->private_data = priv; + codec->dai = &twl6040_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(twl6040_reg); + codec->reg_cache = kmemdup(twl6040_reg, sizeof(twl6040_reg), + GFP_KERNEL); + if (codec->reg_cache == NULL) { + ret = -ENOMEM; + goto cache_err; + } + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + init_completion(&priv->ready); + + if (gpio_is_valid(audpwron)) { + ret = gpio_request(audpwron, "audpwron"); + if (ret) + goto gpio1_err; + + ret = gpio_direction_output(audpwron, 0); + if (ret) + goto gpio2_err; + + priv->codec_powered = 0; + } + + if (naudint) { + /* audio interrupt */ + ret = request_threaded_irq(naudint, NULL, + twl6040_naudint_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "twl6040_codec", codec); + if (ret) + goto gpio2_err; + } else { + if (gpio_is_valid(audpwron)) { + /* enable only codec ready interrupt */ + twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, + ~TWL6040_READYMSK & TWL6040_ALLINT_MSK); + } else { + /* no interrupts at all */ + twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, + TWL6040_ALLINT_MSK); + } + } + + /* init vio registers */ + twl6040_init_vio_regs(codec); + + /* power on device */ + ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + if (ret) + goto irq_err; + + ret = snd_soc_register_codec(codec); + if (ret) + goto reg_err; + + twl6040_codec = codec; + + ret = snd_soc_register_dai(&twl6040_dai); + if (ret) + goto dai_err; + + return 0; + +dai_err: + snd_soc_unregister_codec(codec); + twl6040_codec = NULL; +reg_err: + twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); +irq_err: + if (naudint) + free_irq(naudint, codec); +gpio2_err: + if (gpio_is_valid(audpwron)) + gpio_free(audpwron); +gpio1_err: + kfree(codec->reg_cache); +cache_err: + kfree(priv); + return ret; +} + +static int __devexit twl6040_codec_remove(struct platform_device *pdev) +{ + struct twl6040_data *priv = twl6040_codec->private_data; + int audpwron = priv->audpwron; + int naudint = priv->naudint; + + if (gpio_is_valid(audpwron)) + gpio_free(audpwron); + + if (naudint) + free_irq(naudint, twl6040_codec); + + snd_soc_unregister_dai(&twl6040_dai); + snd_soc_unregister_codec(twl6040_codec); + + kfree(twl6040_codec); + twl6040_codec = NULL; + + return 0; +} + +static struct platform_driver twl6040_codec_driver = { + .driver = { + .name = "twl6040_codec", + .owner = THIS_MODULE, + }, + .probe = twl6040_codec_probe, + .remove = __devexit_p(twl6040_codec_remove), +}; + +static int __init twl6040_codec_init(void) +{ + return platform_driver_register(&twl6040_codec_driver); +} +module_init(twl6040_codec_init); + +static void __exit twl6040_codec_exit(void) +{ + platform_driver_unregister(&twl6040_codec_driver); +} +module_exit(twl6040_codec_exit); + +MODULE_DESCRIPTION("ASoC TWL6040 codec driver"); +MODULE_AUTHOR("Misael Lopez Cruz"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h new file mode 100644 index 0000000..c472070 --- /dev/null +++ b/sound/soc/codecs/twl6040.h @@ -0,0 +1,141 @@ +/* + * ALSA SoC TWL6040 codec driver + * + * Author: Misael Lopez Cruz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __TWL6040_H__ +#define __TWL6040_H__ + +#define TWL6040_REG_ASICID 0x01 +#define TWL6040_REG_ASICREV 0x02 +#define TWL6040_REG_INTID 0x03 +#define TWL6040_REG_INTMR 0x04 +#define TWL6040_REG_NCPCTL 0x05 +#define TWL6040_REG_LDOCTL 0x06 +#define TWL6040_REG_HPPLLCTL 0x07 +#define TWL6040_REG_LPPLLCTL 0x08 +#define TWL6040_REG_LPPLLDIV 0x09 +#define TWL6040_REG_AMICBCTL 0x0A +#define TWL6040_REG_DMICBCTL 0x0B +#define TWL6040_REG_MICLCTL 0x0C +#define TWL6040_REG_MICRCTL 0x0D +#define TWL6040_REG_MICGAIN 0x0E +#define TWL6040_REG_LINEGAIN 0x0F +#define TWL6040_REG_HSLCTL 0x10 +#define TWL6040_REG_HSRCTL 0x11 +#define TWL6040_REG_HSGAIN 0x12 +#define TWL6040_REG_EARCTL 0x13 +#define TWL6040_REG_HFLCTL 0x14 +#define TWL6040_REG_HFLGAIN 0x15 +#define TWL6040_REG_HFRCTL 0x16 +#define TWL6040_REG_HFRGAIN 0x17 +#define TWL6040_REG_VIBCTLL 0x18 +#define TWL6040_REG_VIBDATL 0x19 +#define TWL6040_REG_VIBCTLR 0x1A +#define TWL6040_REG_VIBDATR 0x1B +#define TWL6040_REG_HKCTL1 0x1C +#define TWL6040_REG_HKCTL2 0x1D +#define TWL6040_REG_GPOCTL 0x1E +#define TWL6040_REG_ALB 0x1F +#define TWL6040_REG_DLB 0x20 +#define TWL6040_REG_TRIM1 0x28 +#define TWL6040_REG_TRIM2 0x29 +#define TWL6040_REG_TRIM3 0x2A +#define TWL6040_REG_HSOTRIM 0x2B +#define TWL6040_REG_HFOTRIM 0x2C +#define TWL6040_REG_ACCCTL 0x2D +#define TWL6040_REG_STATUS 0x2E + +#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1) + +#define TWL6040_VIOREGNUM 18 +#define TWL6040_VDDREGNUM 21 + +/* INTID (0x03) fields */ + +#define TWL6040_THINT 0x01 +#define TWL6040_PLUGINT 0x02 +#define TWL6040_UNPLUGINT 0x04 +#define TWL6040_HOOKINT 0x08 +#define TWL6040_HFINT 0x10 +#define TWL6040_VIBINT 0x20 +#define TWL6040_READYINT 0x40 + +/* INTMR (0x04) fields */ + +#define TWL6040_READYMSK 0x40 +#define TWL6040_ALLINT_MSK 0x7B + +/* NCPCTL (0x05) fields */ + +#define TWL6040_NCPENA 0x01 +#define TWL6040_NCPOPEN 0x40 + +/* LDOCTL (0x06) fields */ + +#define TWL6040_LSLDOENA 0x01 +#define TWL6040_HSLDOENA 0x04 +#define TWL6040_REFENA 0x40 +#define TWL6040_OSCENA 0x80 + +/* HPPLLCTL (0x07) fields */ + +#define TWL6040_HPLLENA 0x01 +#define TWL6040_HPLLRST 0x02 +#define TWL6040_HPLLBP 0x04 +#define TWL6040_HPLLSQRENA 0x08 +#define TWL6040_HPLLSQRBP 0x10 +#define TWL6040_MCLK_12000KHZ (0 << 5) +#define TWL6040_MCLK_19200KHZ (1 << 5) +#define TWL6040_MCLK_26000KHZ (2 << 5) +#define TWL6040_MCLK_38400KHZ (3 << 5) +#define TWL6040_MCLK_MSK 0x60 + +/* LPPLLCTL (0x08) fields */ + +#define TWL6040_LPLLENA 0x01 +#define TWL6040_LPLLRST 0x02 +#define TWL6040_LPLLSEL 0x04 +#define TWL6040_LPLLFIN 0x08 +#define TWL6040_HPLLSEL 0x10 + +/* HSLCTL (0x10) fields */ + +#define TWL6040_HSDACMODEL 0x02 +#define TWL6040_HSDRVMODEL 0x08 + +/* HSRCTL (0x11) fields */ + +#define TWL6040_HSDACMODER 0x02 +#define TWL6040_HSDRVMODER 0x08 + +/* ACCCTL (0x2D) fields */ + +#define TWL6040_RESETSPLIT 0x04 + +#define TWL6040_SYSCLK_SEL_LPPLL 1 +#define TWL6040_SYSCLK_SEL_HPPLL 2 + +#define TWL6040_HPPLL_ID 1 +#define TWL6040_LPPLL_ID 2 + +extern struct snd_soc_dai twl6040_dai; +extern struct snd_soc_codec_device soc_codec_dev_twl6040; + +#endif /* End of __TWL6040_H__ */ From patchwork Mon Apr 19 14:51:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Koskinen, Aaro (Nokia - FI/Espoo)" X-Patchwork-Id: 93507 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3JEqXEC008111 for ; Mon, 19 Apr 2010 14:52:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754574Ab0DSOwW (ORCPT ); Mon, 19 Apr 2010 10:52:22 -0400 Received: from smtp.nokia.com ([192.100.122.233]:50920 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754534Ab0DSOwU (ORCPT ); Mon, 19 Apr 2010 10:52:20 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3JEpsH3022222; Mon, 19 Apr 2010 17:52:00 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:51:54 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:51:53 +0300 Received: from localhost.localdomain (esdhcp041196.research.nokia.com [172.21.41.196]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o3JEpqGj006580; Mon, 19 Apr 2010 17:51:52 +0300 From: Aaro Koskinen To: linux-input@vger.kernel.org, linux-omap@vger.kernel.org, dmitry.torokhov@gmail.com Cc: Lauri Leukkunen , Aaro Koskinen , David Brownell , Phil Carmody , Imre Deak , Hiroshi DOYU , Ari Kauppi , Tony Lindgren , Jarkko Nikula , Eero Nurkkala , Roman Tereshonkov Subject: [PATCH v4 1/2] input: touchscreen: introduce tsc2005 driver Date: Mon, 19 Apr 2010 17:51:03 +0300 Message-Id: <1271688664-21525-1-git-send-email-aaro.koskinen@nokia.com> X-Mailer: git-send-email 1.6.3.3 X-OriginalArrivalTime: 19 Apr 2010 14:51:53.0683 (UTC) FILETIME=[D9AF0230:01CADFCF] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 19 Apr 2010 14:52:34 +0000 (UTC) diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index dfafc76..72c1797 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -548,6 +548,17 @@ config TOUCHSCREEN_TOUCHIT213 To compile this driver as a module, choose M here: the module will be called touchit213. +config TOUCHSCREEN_TSC2005 + tristate "TSC2005 based touchscreens" + depends on SPI_MASTER + help + Say Y here if you have a TSC2005 based touchscreen. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called tsc2005. + config TOUCHSCREEN_TSC2007 tristate "TSC2007 based touchscreens" depends on I2C diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index d61a3b4..61fa8b5 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213) += touchit213.o obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o +obj-$(CONFIG_TOUCHSCREEN_TSC2005) += tsc2005.o obj-$(CONFIG_TOUCHSCREEN_TSC2007) += tsc2007.o obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o obj-$(CONFIG_TOUCHSCREEN_WACOM_W8001) += wacom_w8001.o diff --git a/drivers/input/touchscreen/tsc2005.c b/drivers/input/touchscreen/tsc2005.c new file mode 100644 index 0000000..27ee361 --- /dev/null +++ b/drivers/input/touchscreen/tsc2005.c @@ -0,0 +1,678 @@ +/* + * TSC2005 touchscreen driver + * + * Copyright (C) 2006-2010 Nokia Corporation + * + * Author: Lauri Leukkunen + * based on TSC2301 driver by Klaus K. Pedersen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * The touchscreen interface operates as follows: + * + * 1) Pen is pressed against the touchscreen. + * 2) TSC2005 performs AD conversion. + * 3) After the conversion is done TSC2005 drives DAV line down. + * 4) GPIO IRQ is received and tsc2005_irq_thread() is scheduled. + * 5) tsc2005_irq_thread() queues up an spi transfer to fetch the x, y, z1, z2 + * values. + * 6) tsc2005_irq_thread() reports coordinates to input layer and sets up + * tsc2005_penup_timer() to be called after TSC2005_PENUP_TIME_MS (40ms). + * 7) When the penup timer expires, there have not been touch or DAV interrupts + * during the last 40ms which means the pen has been lifted. + * + * ESD recovery via a hardware reset is done if the TSC2005 doesn't respond + * after a configurable period (in ms) of activity. If esd_timeout is 0, the + * watchdog is disabled. + */ + +/* control byte 1 */ +#define TSC2005_CMD 0x80 +#define TSC2005_CMD_NORMAL 0x00 +#define TSC2005_CMD_STOP 0x01 +#define TSC2005_CMD_12BIT 0x04 + +/* control byte 0 */ +#define TSC2005_REG_READ 0x0001 +#define TSC2005_REG_PND0 0x0002 +#define TSC2005_REG_X 0x0000 +#define TSC2005_REG_Y 0x0008 +#define TSC2005_REG_Z1 0x0010 +#define TSC2005_REG_Z2 0x0018 +#define TSC2005_REG_TEMP_HIGH 0x0050 +#define TSC2005_REG_CFR0 0x0060 +#define TSC2005_REG_CFR1 0x0068 +#define TSC2005_REG_CFR2 0x0070 + +/* configuration register 0 */ +#define TSC2005_CFR0_PRECHARGE_276US 0x0040 +#define TSC2005_CFR0_STABTIME_1MS 0x0300 +#define TSC2005_CFR0_CLOCK_1MHZ 0x1000 +#define TSC2005_CFR0_RESOLUTION12 0x2000 +#define TSC2005_CFR0_PENMODE 0x8000 +#define TSC2005_CFR0_INITVALUE (TSC2005_CFR0_STABTIME_1MS | \ + TSC2005_CFR0_CLOCK_1MHZ | \ + TSC2005_CFR0_RESOLUTION12 | \ + TSC2005_CFR0_PRECHARGE_276US | \ + TSC2005_CFR0_PENMODE) + +/* bits common to both read and write of configuration register 0 */ +#define TSC2005_CFR0_RW_MASK 0x3fff + +/* configuration register 1 */ +#define TSC2005_CFR1_BATCHDELAY_4MS 0x0003 +#define TSC2005_CFR1_INITVALUE TSC2005_CFR1_BATCHDELAY_4MS + +/* configuration register 2 */ +#define TSC2005_CFR2_MAVE_Z 0x0004 +#define TSC2005_CFR2_MAVE_Y 0x0008 +#define TSC2005_CFR2_MAVE_X 0x0010 +#define TSC2005_CFR2_AVG_7 0x0800 +#define TSC2005_CFR2_MEDIUM_15 0x3000 +#define TSC2005_CFR2_INITVALUE (TSC2005_CFR2_MAVE_X | \ + TSC2005_CFR2_MAVE_Y | \ + TSC2005_CFR2_MAVE_Z | \ + TSC2005_CFR2_MEDIUM_15 | \ + TSC2005_CFR2_AVG_7) + +#define MAX_12BIT 0xfff +#define TSC2005_SPI_MAX_SPEED_HZ 10000000 +#define TSC2005_PENUP_TIME_MS 40 + +struct tsc2005_spi_rd { + struct spi_transfer spi_xfer; + u32 spi_tx; + u32 spi_rx; +}; + +struct tsc2005 { + struct spi_device *spi; + + struct spi_message spi_read_msg; + struct tsc2005_spi_rd spi_x; + struct tsc2005_spi_rd spi_y; + struct tsc2005_spi_rd spi_z1; + struct tsc2005_spi_rd spi_z2; + + struct input_dev *idev; + char phys[32]; + + struct mutex mutex; + + struct timer_list penup_timer; + struct work_struct penup_work; + + unsigned int esd_timeout; + struct timer_list esd_timer; + struct work_struct esd_work; + + unsigned int x_plate_ohm; + + bool disabled; + unsigned int disable_depth; + + void (*set_reset)(bool enable); +}; + +static void tsc2005_cmd(struct tsc2005 *ts, u8 cmd) +{ + u8 tx; + struct spi_message msg; + struct spi_transfer xfer = { 0 }; + + tx = TSC2005_CMD | TSC2005_CMD_12BIT | cmd; + + xfer.tx_buf = &tx; + xfer.rx_buf = NULL; + xfer.len = 1; + xfer.bits_per_word = 8; + + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + spi_sync(ts->spi, &msg); +} + +static void tsc2005_write(struct tsc2005 *ts, u8 reg, u16 value) +{ + u32 tx; + struct spi_message msg; + struct spi_transfer xfer = { 0 }; + + tx = (reg | TSC2005_REG_PND0) << 16; + tx |= value; + + xfer.tx_buf = &tx; + xfer.rx_buf = NULL; + xfer.len = 4; + xfer.bits_per_word = 24; + + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + spi_sync(ts->spi, &msg); +} + +static void tsc2005_setup_read(struct tsc2005_spi_rd *rd, u8 reg, bool last) +{ + rd->spi_tx = (reg | TSC2005_REG_READ) << 16; + rd->spi_xfer.tx_buf = &rd->spi_tx; + rd->spi_xfer.rx_buf = &rd->spi_rx; + rd->spi_xfer.len = 4; + rd->spi_xfer.bits_per_word = 24; + rd->spi_xfer.cs_change = !last; +} + +static void tsc2005_read(struct tsc2005 *ts, u8 reg, u16 *value) +{ + struct spi_message msg; + struct tsc2005_spi_rd spi_rd = { { 0 }, 0, 0 }; + + tsc2005_setup_read(&spi_rd, reg, 1); + + spi_message_init(&msg); + spi_message_add_tail(&spi_rd.spi_xfer, &msg); + spi_sync(ts->spi, &msg); + *value = spi_rd.spi_rx; +} + +static void tsc2005_update_pen_state(struct tsc2005 *ts, + int x, int y, int pressure) +{ + if (pressure) { + input_report_abs(ts->idev, ABS_X, x); + input_report_abs(ts->idev, ABS_Y, y); + } + input_report_abs(ts->idev, ABS_PRESSURE, pressure); + input_report_key(ts->idev, BTN_TOUCH, !!pressure); + input_sync(ts->idev); + dev_dbg(&ts->spi->dev, "point(%4d,%4d), pressure (%4d)\n", x, y, + pressure); +} + +static irqreturn_t tsc2005_irq_handler(int irq, void *dev_id) +{ + struct tsc2005 *ts = dev_id; + + /* update the penup timer only if it's pending */ + mod_timer_pending(&ts->penup_timer, + jiffies + msecs_to_jiffies(TSC2005_PENUP_TIME_MS)); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t tsc2005_irq_thread(int irq, void *_ts) +{ + struct tsc2005 *ts = _ts; + unsigned int pressure; + u32 x; + u32 y; + u32 z1; + u32 z2; + + mutex_lock(&ts->mutex); + + if (unlikely(ts->disable_depth)) + goto out; + + /* read the coordinates */ + spi_sync(ts->spi, &ts->spi_read_msg); + x = ts->spi_x.spi_rx; + y = ts->spi_y.spi_rx; + z1 = ts->spi_z1.spi_rx; + z2 = ts->spi_z2.spi_rx; + + /* validate position */ + if (unlikely(x > MAX_12BIT || y > MAX_12BIT)) + goto out; + + /* skip coords if the pressure components are out of range */ + if (unlikely(z1 == 0 || z2 > MAX_12BIT || z1 >= z2)) + goto out; + + /* compute touch pressure resistance using equation #1 */ + pressure = x * (z2 - z1) / z1; + pressure = pressure * ts->x_plate_ohm / 4096; + if (unlikely(pressure > MAX_12BIT)) + goto out; + + tsc2005_update_pen_state(ts, x, y, pressure); + + /* set the penup timer */ + mod_timer(&ts->penup_timer, + jiffies + msecs_to_jiffies(TSC2005_PENUP_TIME_MS)); + + if (!ts->esd_timeout) + goto out; + + /* update the watchdog timer */ + mod_timer(&ts->esd_timer, + round_jiffies(jiffies + msecs_to_jiffies(ts->esd_timeout))); + +out: + mutex_unlock(&ts->mutex); + return IRQ_HANDLED; +} + +static void tsc2005_penup_timer(unsigned long data) +{ + struct tsc2005 *ts = (struct tsc2005 *)data; + + schedule_work(&ts->penup_work); +} + +static void tsc2005_penup_work(struct work_struct *work) +{ + struct tsc2005 *ts = container_of(work, struct tsc2005, penup_work); + + mutex_lock(&ts->mutex); + tsc2005_update_pen_state(ts, 0, 0, 0); + mutex_unlock(&ts->mutex); +} + +static void tsc2005_start_scan(struct tsc2005 *ts) +{ + tsc2005_write(ts, TSC2005_REG_CFR0, TSC2005_CFR0_INITVALUE); + tsc2005_write(ts, TSC2005_REG_CFR1, TSC2005_CFR1_INITVALUE); + tsc2005_write(ts, TSC2005_REG_CFR2, TSC2005_CFR2_INITVALUE); + tsc2005_cmd(ts, TSC2005_CMD_NORMAL); +} + +static void tsc2005_stop_scan(struct tsc2005 *ts) +{ + tsc2005_cmd(ts, TSC2005_CMD_STOP); +} + +/* must be called with mutex held */ +static void tsc2005_disable(struct tsc2005 *ts) +{ + if (ts->disable_depth++ != 0) + return; + disable_irq(ts->spi->irq); + if (ts->esd_timeout) + del_timer_sync(&ts->esd_timer); + del_timer_sync(&ts->penup_timer); + tsc2005_stop_scan(ts); +} + +/* must be called with mutex held */ +static void tsc2005_enable(struct tsc2005 *ts) +{ + if (--ts->disable_depth != 0) + return; + tsc2005_start_scan(ts); + enable_irq(ts->spi->irq); + if (!ts->esd_timeout) + return; + mod_timer(&ts->esd_timer, + round_jiffies(jiffies + msecs_to_jiffies(ts->esd_timeout))); +} + +static ssize_t tsc2005_disable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tsc2005 *ts = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", ts->disabled); +} + +static ssize_t tsc2005_disable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct tsc2005 *ts = dev_get_drvdata(dev); + unsigned long res; + int i; + + if (strict_strtoul(buf, 10, &res) < 0) + return -EINVAL; + i = res ? 1 : 0; + + mutex_lock(&ts->mutex); + if (i == ts->disabled) + goto out; + ts->disabled = i; + if (i) + tsc2005_disable(ts); + else + tsc2005_enable(ts); +out: + mutex_unlock(&ts->mutex); + return count; +} +static DEVICE_ATTR(disable, 0664, tsc2005_disable_show, tsc2005_disable_store); + +static ssize_t tsc2005_selftest_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tsc2005 *ts = dev_get_drvdata(dev); + u16 temp_high; + u16 temp_high_orig; + u16 temp_high_test; + unsigned int result; + + if (!ts->set_reset) { + dev_warn(&ts->spi->dev, + "unable to selftest: no reset function\n"); + result = 0; + goto out; + } + + mutex_lock(&ts->mutex); + + /* + * Test TSC2005 communications via temp high register. + */ + tsc2005_disable(ts); + result = 1; + tsc2005_read(ts, TSC2005_REG_TEMP_HIGH, &temp_high_orig); + temp_high_test = (temp_high_orig - 1) & MAX_12BIT; + tsc2005_write(ts, TSC2005_REG_TEMP_HIGH, temp_high_test); + tsc2005_read(ts, TSC2005_REG_TEMP_HIGH, &temp_high); + if (temp_high != temp_high_test) { + dev_warn(dev, "selftest failed: %d != %d\n", + temp_high, temp_high_test); + result = 0; + } + + /* hardware reset */ + ts->set_reset(0); + msleep(1); /* only 10us required */ + ts->set_reset(1); + tsc2005_enable(ts); + + /* test that the reset really happened */ + tsc2005_read(ts, TSC2005_REG_TEMP_HIGH, &temp_high); + if (temp_high != temp_high_orig) { + dev_warn(dev, "selftest failed after reset: %d != %d\n", + temp_high, temp_high_orig); + result = 0; + } + + mutex_unlock(&ts->mutex); + +out: + return sprintf(buf, "%u\n", result); +} +static DEVICE_ATTR(selftest, S_IRUGO, tsc2005_selftest_show, NULL); + +static void tsc2005_esd_timer(unsigned long data) +{ + struct tsc2005 *ts = (struct tsc2005 *)data; + + schedule_work(&ts->esd_work); +} + +static void tsc2005_esd_work(struct work_struct *work) +{ + struct tsc2005 *ts = container_of(work, struct tsc2005, esd_work); + u16 r; + + mutex_lock(&ts->mutex); + + if (ts->disable_depth) + goto out; + + /* + * If we cannot read our known value from configuration register 0 then + * reset the controller as if from power-up and start scanning again. + */ + tsc2005_read(ts, TSC2005_REG_CFR0, &r); + if ((r ^ TSC2005_CFR0_INITVALUE) & TSC2005_CFR0_RW_MASK) { + dev_info(&ts->spi->dev, "TSC2005 not responding - resetting\n"); + ts->set_reset(0); + msleep(1); /* only 10us required */ + ts->set_reset(1); + tsc2005_start_scan(ts); + } + + /* re-arm the watchdog */ + mod_timer(&ts->esd_timer, + round_jiffies(jiffies + msecs_to_jiffies(ts->esd_timeout))); + +out: + mutex_unlock(&ts->mutex); +} + +static void __devinit tsc2005_setup_spi_xfer(struct tsc2005 *ts) +{ + tsc2005_setup_read(&ts->spi_x, TSC2005_REG_X, 0); + tsc2005_setup_read(&ts->spi_y, TSC2005_REG_Y, 0); + tsc2005_setup_read(&ts->spi_z1, TSC2005_REG_Z1, 0); + tsc2005_setup_read(&ts->spi_z2, TSC2005_REG_Z2, 1); + + spi_message_init(&ts->spi_read_msg); + spi_message_add_tail(&ts->spi_x.spi_xfer, &ts->spi_read_msg); + spi_message_add_tail(&ts->spi_y.spi_xfer, &ts->spi_read_msg); + spi_message_add_tail(&ts->spi_z1.spi_xfer, &ts->spi_read_msg); + spi_message_add_tail(&ts->spi_z2.spi_xfer, &ts->spi_read_msg); +} + +static struct attribute *tsc2005_attrs[] = { + &dev_attr_disable.attr, + &dev_attr_selftest.attr, + NULL +}; + +static struct attribute_group tsc2005_attr_group = { + .attrs = tsc2005_attrs, +}; + +static int __devinit tsc2005_setup(struct tsc2005 *ts, + struct tsc2005_platform_data *pdata) +{ + int r; + int fudge_x; + int fudge_y; + int fudge_p; + int p_max; + int x_max; + int y_max; + + mutex_init(&ts->mutex); + + tsc2005_setup_spi_xfer(ts); + + init_timer(&ts->penup_timer); + setup_timer(&ts->penup_timer, tsc2005_penup_timer, (unsigned long)ts); + INIT_WORK(&ts->penup_work, tsc2005_penup_work); + + fudge_x = pdata->ts_x_fudge ? : 0; + fudge_y = pdata->ts_y_fudge ? : 0; + fudge_p = pdata->ts_pressure_fudge ? : 0; + x_max = pdata->ts_x_max ? : MAX_12BIT; + y_max = pdata->ts_y_max ? : MAX_12BIT; + p_max = pdata->ts_pressure_max ? : MAX_12BIT; + ts->x_plate_ohm = pdata->ts_x_plate_ohm ? : 0; + ts->esd_timeout = pdata->esd_timeout_ms; + ts->set_reset = pdata->set_reset; + + ts->idev = input_allocate_device(); + if (ts->idev == NULL) + return -ENOMEM; + ts->idev->name = "TSC2005 touchscreen"; + snprintf(ts->phys, sizeof(ts->phys), "%s/input-ts", + dev_name(&ts->spi->dev)); + ts->idev->phys = ts->phys; + ts->idev->evbit[0] = BIT(EV_ABS) | BIT(EV_KEY); + ts->idev->absbit[0] = BIT(ABS_X) | BIT(ABS_Y) | BIT(ABS_PRESSURE); + ts->idev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); + + input_set_abs_params(ts->idev, ABS_X, 0, x_max, fudge_x, 0); + input_set_abs_params(ts->idev, ABS_Y, 0, y_max, fudge_y, 0); + input_set_abs_params(ts->idev, ABS_PRESSURE, 0, p_max, fudge_p, 0); + + r = request_threaded_irq(ts->spi->irq, tsc2005_irq_handler, + tsc2005_irq_thread, IRQF_TRIGGER_RISING, + "tsc2005", ts); + if (r) { + dev_err(&ts->spi->dev, "request_threaded_irq(): %d\n", r); + goto err1; + } + set_irq_wake(ts->spi->irq, 1); + + r = input_register_device(ts->idev); + if (r) { + dev_err(&ts->spi->dev, "input_register_device(): %d\n", r); + goto err2; + } + + r = sysfs_create_group(&ts->spi->dev.kobj, &tsc2005_attr_group); + if (r) + dev_warn(&ts->spi->dev, "sysfs entry creation failed: %d\n", r); + + tsc2005_start_scan(ts); + + if (!ts->esd_timeout || !ts->set_reset) + goto done; + + /* start the optional ESD watchdog */ + setup_timer(&ts->esd_timer, tsc2005_esd_timer, (unsigned long)ts); + INIT_WORK(&ts->esd_work, tsc2005_esd_work); + mod_timer(&ts->esd_timer, + round_jiffies(jiffies + msecs_to_jiffies(ts->esd_timeout))); + +done: + return 0; + +err2: + free_irq(ts->spi->irq, ts); + +err1: + input_free_device(ts->idev); + return r; +} + +static int __devinit tsc2005_probe(struct spi_device *spi) +{ + struct tsc2005_platform_data *pdata = spi->dev.platform_data; + struct tsc2005 *ts; + int r; + + if (spi->irq < 0) { + dev_dbg(&spi->dev, "no irq\n"); + return -ENODEV; + } + + if (!pdata) { + dev_dbg(&spi->dev, "no platform data\n"); + return -ENODEV; + } + + ts = kzalloc(sizeof(*ts), GFP_KERNEL); + if (ts == NULL) + return -ENOMEM; + + dev_set_drvdata(&spi->dev, ts); + ts->spi = spi; + spi->dev.power.power_state = PMSG_ON; + spi->mode = SPI_MODE_0; + spi->bits_per_word = 8; + if (!spi->max_speed_hz) + spi->max_speed_hz = TSC2005_SPI_MAX_SPEED_HZ; + spi_setup(spi); + + r = tsc2005_setup(ts, pdata); + if (r) + kfree(ts); + return r; +} + +static int __devexit tsc2005_remove(struct spi_device *spi) +{ + struct tsc2005 *ts = dev_get_drvdata(&spi->dev); + + mutex_lock(&ts->mutex); + tsc2005_disable(ts); + mutex_unlock(&ts->mutex); + + if (ts->esd_timeout) + del_timer_sync(&ts->esd_timer); + del_timer_sync(&ts->penup_timer); + + flush_work(&ts->esd_work); + flush_work(&ts->penup_work); + + sysfs_remove_group(&ts->spi->dev.kobj, &tsc2005_attr_group); + free_irq(ts->spi->irq, ts); + input_unregister_device(ts->idev); + kfree(ts); + + return 0; +} + +#ifdef CONFIG_PM +static int tsc2005_suspend(struct spi_device *spi, pm_message_t mesg) +{ + struct tsc2005 *ts = dev_get_drvdata(&spi->dev); + + mutex_lock(&ts->mutex); + tsc2005_disable(ts); + mutex_unlock(&ts->mutex); + + return 0; +} + +static int tsc2005_resume(struct spi_device *spi) +{ + struct tsc2005 *ts = dev_get_drvdata(&spi->dev); + + mutex_lock(&ts->mutex); + tsc2005_enable(ts); + mutex_unlock(&ts->mutex); + + return 0; +} +#endif + +static struct spi_driver tsc2005_driver = { + .driver = { + .name = "tsc2005", + .owner = THIS_MODULE, + }, +#ifdef CONFIG_PM + .suspend = tsc2005_suspend, + .resume = tsc2005_resume, +#endif + .probe = tsc2005_probe, + .remove = __devexit_p(tsc2005_remove), +}; + +static int __init tsc2005_init(void) +{ + printk(KERN_INFO "TSC2005 driver initializing\n"); + return spi_register_driver(&tsc2005_driver); +} +module_init(tsc2005_init); + +static void __exit tsc2005_exit(void) +{ + spi_unregister_driver(&tsc2005_driver); +} +module_exit(tsc2005_exit); + +MODULE_AUTHOR("Lauri Leukkunen "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:tsc2005"); diff --git a/include/linux/spi/tsc2005.h b/include/linux/spi/tsc2005.h new file mode 100644 index 0000000..d9b0c84 --- /dev/null +++ b/include/linux/spi/tsc2005.h @@ -0,0 +1,41 @@ +/* + * This file is part of TSC2005 touchscreen driver + * + * Copyright (C) 2009-2010 Nokia Corporation + * + * Contact: Aaro Koskinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef _LINUX_SPI_TSC2005_H +#define _LINUX_SPI_TSC2005_H + +#include + +struct tsc2005_platform_data { + int ts_pressure_max; + int ts_pressure_fudge; + int ts_x_max; + int ts_x_fudge; + int ts_y_max; + int ts_y_fudge; + int ts_x_plate_ohm; + unsigned int esd_timeout_ms; + void (*set_reset)(bool enable); +}; + +#endif From patchwork Sun May 16 15:45:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99971 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkPwO025255 for ; Sun, 16 May 2010 15:46:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753405Ab0EPPqY (ORCPT ); Sun, 16 May 2010 11:46:24 -0400 Received: from mail-fx0-f46.google.com ([209.85.161.46]:51910 "EHLO mail-fx0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753268Ab0EPPqX (ORCPT ); Sun, 16 May 2010 11:46:23 -0400 Received: by fxm6 with SMTP id 6so2977823fxm.19 for ; Sun, 16 May 2010 08:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=7FGtAVM/IVIk3PMhUXMQdAtucp0Wi6hnYUlbYTRf7pY=; b=bCIoFuilQas6jFyqqx5jNiCuI2A7KzPsv3fSZDuJI30SEOGLZpNXoxh9y/aeGgjdl1 xi8esB9jxuzwj6tWHnOyyOyRnOn0v0LmtUiqJAedOmaiPJ3qjquvIye98oU1+t9WSAht LWMlJgh5Q11T3uuEFe6zLtvBWdrdJ/QmHAY+A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=LbGAPsJWhrSluEVikmr3FO+NdBB+wOmJeEDmdnjG2xBY0yA1o8CyZNk0KwBwWAlttX 3cov8esyLHQlXHAQ7T+2HCVeQW0rM4zA76dZZrfPMDygArjvIrfa9dMZu2Xa1pHMwJdH opTJ87rn6wGjeD+djHcWED7ysccvtGYQ3N7Sc= Received: by 10.87.13.6 with SMTP id q6mr1222926fgi.19.1274024782404; Sun, 16 May 2010 08:46:22 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id d8sm11666843fga.21.2010.05.16.08.46.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:21 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 07/14] dspbridge: deh: ensure only tlb #0 is enabled Date: Sun, 16 May 2010 18:45:58 +0300 Message-Id: <1274024765-21076-8-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:25 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 61e5e4e..f661aaf 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -235,6 +235,14 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); + /* + * Before acking the MMU fault, let's make sure MMU can only + * access entry #0. Then add a new entry so that the DSP OS + * can continue in order to dump the stack. + */ + hw_mmu_twl_disable(resources->dw_dmmu_base); + hw_mmu_tlb_flush_all(resources->dw_dmmu_base); + hw_mmu_tlb_add(resources->dw_dmmu_base, virt_to_phys(dummy_va_addr), fault_addr, HW_PAGE_SIZE4KB, 1, From patchwork Thu Jul 8 22:51:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110944 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsDAQ011187 for ; Thu, 8 Jul 2010 22:54:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758721Ab0GHWyJ (ORCPT ); Thu, 8 Jul 2010 18:54:09 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:39647 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758716Ab0GHWyI (ORCPT ); Thu, 8 Jul 2010 18:54:08 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms3DO001187 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:05 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaJ022017; Fri, 9 Jul 2010 04:24:00 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 09/10] OMAP: DMA: API's Clean up Date: Fri, 9 Jul 2010 04:21:21 +0530 Message-Id: <1278629482-32501-10-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:13 +0000 (UTC) This patch will clean up API's in plat-omap dma library The API's are cleaned up for eliminating cpu_is_xxxx checks and machine specific API/code is moved to corresponding mach-omap directories. Note: The code in plat-omap dma library will be removed in another patch. This is to avoid build break. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap1/dma.c | 253 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/dma.c | 296 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 548 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index fb5bf0d..dd03937 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -170,11 +170,149 @@ static struct omap_dma_reg_offset dma_reg_offset[] = { }; struct omap_dma_reg_offset *r = (struct omap_dma_reg_offset *)&dma_reg_offset; +static inline void enable_lnk(int lch); +static inline void disable_lnk(int lch); +static inline void omap_enable_channel_irq(int lch); +static irqreturn_t omap_dma_irq_handler(int irq, void *dev_id); static struct omap_dma_lch *omap1_dma_chan; static void __iomem *dma_base; static int enable_1510_mode; +static inline int get_gdma_dev(int req) +{ + u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; + int shift = ((req - 1) % 5) * 6; + + return ((omap_readl(reg) >> shift) & 0x3f) + 1; +} + +static inline void set_gdma_dev(int req, int dev) +{ + u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; + int shift = ((req - 1) % 5) * 6; + u32 l; + + l = omap_readl(reg); + l &= ~(0x3f << shift); + l |= (dev - 1) << shift; + omap_writel(l, reg); +} + +static void sync_device_set(int dev_id, int free_ch) +{ + u32 reg; + + reg = (r->lch_base * free_ch) + r->common_ch.ccr; + if (cpu_is_omap16xx()) { + /* If the sync device is set, configure it dynamically. */ + if (dev_id != 0) { + set_gdma_dev(free_ch + 1, dev_id); + dev_id = free_ch + 1; + } + /* + * Disable the 1510 compatibility mode and set the sync device + * id. + */ + omap1_dma_write(dev_id | (1 << 10), reg); + } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { + omap1_dma_write(dev_id, reg); + } +} + +static inline void omap_enable_channel_irq(int lch) +{ + u32 reg; + + /* Clear CSR */ + reg = (r->lch_base * lch) + r->common_ch.csr; + omap1_dma_read(reg); + + /* Enable some nice interrupts. */ + reg = (r->lch_base * lch) + r->common_ch.cicr; + omap1_dma_write(omap1_dma_chan[lch].enabled_irqs, reg); +} + +static inline void enable_lnk(int lch) +{ + u32 reg, l; + + reg = (r->lch_base * lch) + r->common_ch.clnk_ctrl; + l = omap1_dma_read(reg); + + if (omap1_dma_chan[lch].next_linked_ch != -1) + l = omap1_dma_chan[lch].next_linked_ch | (1 << 15); + + /* Set the ENABLE_LNK bits */ + if (omap1_dma_chan[lch].next_lch != -1) + l = omap1_dma_chan[lch].next_lch | (1 << 15); + + omap1_dma_write(l, reg); +} + +static inline void disable_lnk(int lch) +{ + u32 reg, l; + + reg = (r->lch_base * lch) + r->common_ch.clnk_ctrl; + l = omap1_dma_read(reg); + + /* Clear CSR */ + reg = (r->lch_base * lch) + r->common_ch.cicr; + omap1_dma_write(0, reg); + + /* Clear the ENABLE_LNK bit */ + l &= ~(1 << 15); + + reg = (r->lch_base * lch) + r->common_ch.clnk_ctrl; + omap1_dma_write(l, reg); + omap1_dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; +} + +static void clear_lch_regs(int lch) +{ + int reg_count; + u32 ch_reg_base, reg; + + ch_reg_base = r->lch_base * lch; + + for (reg_count = 0; reg_count < 0x2c; reg_count += 2) { + reg = ch_reg_base + reg_count; + omap1_dma_write(0, reg); + } +} + +static void clear_ccr_csr(int lch) +{ + u32 reg; + int l; + + reg = (r->lch_base * lch) + r->common_ch.ccr; + l = omap1_dma_read(reg); + l &= ~OMAP_DMA_CCR_EN; + omap1_dma_write(l, reg); + + /* Clear pending interrupts */ + reg = r->lch_base + r->common_ch.csr; + omap1_dma_read(reg); +} + +static int set_prio_lch(int lch, unsigned char read_prio, + unsigned char write_prio) +{ + u32 l = 0; + l |= ((read_prio & 0x1) << 6); + return l; +} + +static int dma_running(int dma_chan_count) +{ + if (omap_lcd_dma_running()) + return 1; + + return 0; +} + static int omap1_dma_handle_ch(int ch) { u32 csr; @@ -246,6 +384,121 @@ static int dma_irq_register(int dma_irq, int irq_count, return ret; } +void omap_set_dma_priority(int lch, int dst_port, int priority) +{ + unsigned long reg; + u32 l; + + switch (dst_port) { + case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ + reg = OMAP_TC_OCPT1_PRIOR; + break; + case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ + reg = OMAP_TC_OCPT2_PRIOR; + break; + case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ + reg = OMAP_TC_EMIFF_PRIOR; + break; + case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ + reg = OMAP_TC_EMIFS_PRIOR; + break; + default: + BUG(); + return; + } + l = omap_readl(reg); + l &= ~(0xf << 8); + l |= (priority & 0xf) << 8; + omap_writel(l, reg); +} +EXPORT_SYMBOL(omap_set_dma_priority); + +void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, + int frame_count, int sync_mode, + int dma_trigger, int src_or_dst_synch) +{ + u32 reg, l; + u16 ccr; + + reg = (r->lch_base * lch) + r->common_ch.csdp; + l = omap1_dma_read(reg); + l &= ~0x03; + l |= data_type; + omap1_dma_write(l, reg); + + reg = (r->lch_base * lch) + r->common_ch.ccr; + ccr = omap1_dma_read(reg); + ccr &= ~(1 << 5); + if (sync_mode == OMAP_DMA_SYNC_FRAME) + ccr |= 1 << 5; + omap1_dma_write(ccr, reg); + + reg = (r->lch_base * lch) + r->ch_specific.ccr2; + ccr = omap1_dma_read(reg); + ccr &= ~(1 << 2); + if (sync_mode == OMAP_DMA_SYNC_BLOCK) + ccr |= 1 << 2; + omap1_dma_write(ccr, reg); +} +EXPORT_SYMBOL(omap_set_dma_transfer_params); + +void set_dma_color_mode(int lch, + enum omap_dma_color_mode mode, u32 color) +{ + u32 reg; + u16 w; + + BUG_ON(enable_1510_mode); + + reg = (r->lch_base * lch) + r->ch_specific.ccr2; + w = omap1_dma_read(reg); + w &= ~0x03; + + switch (mode) { + case OMAP_DMA_CONSTANT_FILL: + w |= 0x01; + break; + case OMAP_DMA_TRANSPARENT_COPY: + w |= 0x02; + break; + case OMAP_DMA_COLOR_DIS: + break; + default: + BUG(); + } + omap1_dma_write(w, reg); + + reg = (r->lch_base * lch) + r->ch_specific.lch_ctrl; + w = omap1_dma_read(reg); + w &= ~0x0f; + /* Default is channel type 2D */ + if (mode) { + reg = (r->lch_base * lch) + r->ch_specific.color_l; + omap1_dma_write((u16)color, reg); + reg = (r->lch_base * lch) + r->ch_specific.color_u; + omap1_dma_write((u16)color >> 16, reg); + w |= 1; /* Channel type G */ + } + reg = (r->lch_base * lch) + r->ch_specific.lch_ctrl; + omap1_dma_write(w, reg); +} +EXPORT_SYMBOL(set_dma_color_mode); + +void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) +{ + u32 reg; + + if (!enable_1510_mode) { + u32 l; + reg = (r->lch_base * lch) + r->ch_specific.lch_ctrl; + l = omap1_dma_read(reg); + l &= ~0x7; + l |= mode; + omap1_dma_write(l, reg); + } +} +EXPORT_SYMBOL(omap_set_dma_channel_mode); + static int __init omap1_system_dma_init(void) { struct platform_device *pdev; diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 42a96cf..e315096 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -83,6 +83,12 @@ struct dma_link_info { }; +static struct omap_dma_global_context_registers { + u32 dma_irqenable_l0; + u32 dma_ocp_sysconfig; + u32 dma_gcr; +} omap_dma_global_context; + struct omap_device_pm_latency omap2_dma_latency[] = { { .deactivate_func = omap_device_idle_hwmods, @@ -129,11 +135,155 @@ struct omap_dma_reg_offset *r = (struct omap_dma_reg_offset *)&dma_reg_offset; struct omap_dma_dev_attr *d; -static struct omap_system_dma_plat_info *omap2_pdata; +static inline void omap_enable_lnk(int lch); +static inline void omap_disable_lnk(int lch); +static inline void omap_enable_channel_irq(int lch); +static inline void omap_disable_channel_irq(int lch); + +static struct omap_dma_lch *dma_chan; static void __iomem *dma_base; +static struct omap_system_dma_plat_info *omap2_pdata; static struct dma_link_info *dma_linked_lch; static u32 dma_chan_count; +static inline void omap_enable_channel_irq(int lch) +{ + u32 reg; + + /* Clear CSR */ + reg = (r->lch_base * lch) + r->common_ch.csr; + omap2_dma_write(OMAP2_DMA_CSR_CLEAR_MASK, reg); + + /* Enable interrupts. */ + reg = (r->lch_base * lch) + r->common_ch.cicr; + omap2_dma_write(dma_chan[lch].enabled_irqs, reg); +} + +static void omap_disable_channel_irq(int lch) +{ + u32 reg; + reg = (r->lch_base * lch) + r->common_ch.cicr; + omap2_dma_write(0, reg); +} + +static inline void omap_enable_lnk(int lch) +{ + u32 reg, l; + + reg = (r->lch_base * lch) + r->common_ch.clnk_ctrl; + l = omap2_dma_read(reg); + + /* Set the ENABLE_LNK bits */ + if (dma_chan[lch].next_lch != -1) + l = dma_chan[lch].next_lch | (1 << 15); + + if (dma_chan[lch].next_linked_ch != -1) + l = dma_chan[lch].next_linked_ch | (1 << 15); + + omap2_dma_write(l, reg); +} + +static inline void omap_disable_lnk(int lch) +{ + u32 reg, l; + + reg = (r->lch_base * lch) + r->common_ch.clnk_ctrl; + l = omap2_dma_read(reg); + + /* Disable interrupts */ + omap_disable_channel_irq(lch); + + /* Clear the ENABLE_LNK bit */ + l &= ~(1 << 15); + + omap2_dma_write(l, reg); + dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; +} + +static inline void enable_irq_lch(int lch) +{ + u32 reg, val; + + reg = r->irqreg.irq_enable_l0; + val = omap2_dma_read(reg); + val |= 1 << lch; + omap2_dma_write(val, reg); +} + +static inline void disable_irq_lch(int lch) +{ + u32 reg, val; + + reg = r->irqreg.irq_enable_l0; + + val = omap2_dma_read(reg); + val &= ~(1 << lch); + omap2_dma_write(val, reg); +} + +static int set_prio_lch(int l, unsigned char read_prio, + unsigned char write_prio) +{ + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) + l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); + else + l |= ((read_prio & 0x1) << 6); + + return l; +} + +static int dma_running(int dma_chan_count) +{ + u32 lch, reg = 0; + + for (lch = 0; lch < dma_chan_count; lch++) { + reg = (r->lch_base * lch) + r->common_ch.ccr; + if ((omap2_dma_read(reg)) & OMAP_DMA_CCR_EN) + return 1; + } + return 0; +} + +static void dma_ocpsysconfig_errata(int chain_id) +{ + int *channels; + u32 sys_cf; + u32 reg, l, i; + + /* + * DMA Errata: + * Special programming model needed to disable DMA before end of block + */ + sys_cf = omap2_dma_read(r->ocp_sysconfig); + l = sys_cf; + /* Middle mode reg set no Standby */ + l &= ~((1 << 12)|(1 << 13)); + omap2_dma_write(l, r->ocp_sysconfig); + + channels = dma_linked_lch[chain_id].linked_dmach_q; + + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { + + /* Stop the Channel transmission */ + reg = (r->lch_base * channels[i]) + r->common_ch.ccr; + l = omap2_dma_read(reg); + l &= ~(1 << 7); + omap2_dma_write(l, reg); + + /* Disable the link in all the channels */ + omap_disable_lnk(channels[i]); + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; + + } + dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED; + + /* Reset the Queue pointers */ + OMAP_DMA_CHAIN_QINIT(chain_id); + + /* Errata - put in the old value */ + omap2_dma_write(sys_cf, r->ocp_sysconfig); +} + static int omap2_dma_handle_ch(int ch) { u32 reg, ch_reg_base, status; @@ -283,6 +433,150 @@ static void create_dma_lch_chain(int lch_head, int lch_queue) omap2_dma_write(l, reg); } +void omap_dma_global_context_save(void) +{ + omap_dma_global_context.dma_irqenable_l0 = + omap2_dma_read(r->irqreg.irq_enable_l0); + omap_dma_global_context.dma_ocp_sysconfig = + omap2_dma_read(r->ocp_sysconfig); + omap_dma_global_context.dma_gcr = + omap2_dma_read(r->gcr); +} +EXPORT_SYMBOL(omap_dma_global_context_save); + +void omap_dma_global_context_restore(void) +{ + int ch; + + omap2_dma_write(omap_dma_global_context.dma_gcr, r->gcr); + omap2_dma_write(omap_dma_global_context.dma_ocp_sysconfig, + r->ocp_sysconfig); + omap2_dma_write(omap_dma_global_context.dma_irqenable_l0, + r->irqreg.irq_enable_l0); + + if (omap2_pdata->errata & DMA_IRQ_STATUS_ERRATA) + omap2_dma_write(0x3, r->irqreg.irq_status_l0); + + for (ch = 0; ch < dma_chan_count; ch++) + if (dma_chan[ch].dev_id != -1) + omap_clear_dma(ch); +} +EXPORT_SYMBOL(omap_dma_global_context_restore); + +void omap_set_dma_priority(int lch, int dst_port, int priority) +{ + u32 reg; + int ccr; + + reg = (r->lch_base * lch) + r->common_ch.ccr; + ccr = omap2_dma_read(reg); + + if (priority) + ccr |= (1 << 6); + else + ccr &= ~(1 << 6); + + omap2_dma_write(ccr, reg); +} +EXPORT_SYMBOL(omap_set_dma_priority); + + + +void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, + int frame_count, int sync_mode, + int dma_trigger, int src_or_dst_synch) +{ + u32 reg, ch_reg_base, l; + + ch_reg_base = r->lch_base * lch; + reg = ch_reg_base + r->common_ch.csdp; + l = omap2_dma_read(reg); + l &= ~0x03; + l |= data_type; + omap2_dma_write(l, reg); + + if (dma_trigger) { + u32 val; + + reg = ch_reg_base + r->common_ch.ccr; + val = omap2_dma_read(reg); + + /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ + val &= ~((3 << 19) | 0x1f); + val |= (dma_trigger & ~0x1f) << 14; + val |= dma_trigger & 0x1f; + + if (sync_mode & OMAP_DMA_SYNC_FRAME) + val |= 1 << 5; + else + val &= ~(1 << 5); + + if (sync_mode & OMAP_DMA_SYNC_BLOCK) + val |= 1 << 18; + else + val &= ~(1 << 18); + + if (src_or_dst_synch) + val |= 1 << 24; /* source synch */ + else + val &= ~(1 << 24); /* dest synch */ + + omap2_dma_write(val, reg); + } + + reg = ch_reg_base + r->common_ch.cen; + omap2_dma_write(elem_count, reg); + + reg = ch_reg_base + r->common_ch.cfn; + omap2_dma_write(frame_count, reg); +} +EXPORT_SYMBOL(omap_set_dma_transfer_params); + +void set_dma_color_mode(int lch, enum omap_dma_color_mode mode, + u32 color) +{ + u32 reg, ch_reg_base, val; + + ch_reg_base = r->lch_base * lch; + reg = ch_reg_base + r->common_ch.ccr; + + val = omap2_dma_read(reg); + val &= ~((1 << 17) | (1 << 16)); + + switch (mode) { + case OMAP_DMA_CONSTANT_FILL: + val |= 1 << 16; + break; + case OMAP_DMA_TRANSPARENT_COPY: + val |= 1 << 17; + break; + case OMAP_DMA_COLOR_DIS: + break; + default: + BUG(); + } + omap2_dma_write(val, reg); + + color &= 0xffffff; + reg = ch_reg_base + r->ch_specific.color; + omap2_dma_write(val, reg); +} +EXPORT_SYMBOL(set_dma_color_mode); + +void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) +{ + u32 reg, ch_reg_base, val; + + ch_reg_base = r->lch_base * lch; + + reg = ch_reg_base + r->common_ch.csdp; + val = omap2_dma_read(reg); + val &= ~(0x3 << 16); + val |= (mode << 16); + omap2_dma_write(val, reg); +} +EXPORT_SYMBOL(omap_set_dma_write_mode); + /** * @brief omap_request_dma_chain : Request a chain of DMA channels * From patchwork Thu Jul 8 22:51:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110945 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsFdO011203 for ; Thu, 8 Jul 2010 22:54:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758725Ab0GHWyN (ORCPT ); Thu, 8 Jul 2010 18:54:13 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:39652 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758716Ab0GHWyL (ORCPT ); Thu, 8 Jul 2010 18:54:11 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms3dj001192 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:06 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaK022017; Fri, 9 Jul 2010 04:24:01 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 10/10] OMAP: DMA: Cleanup DMA library and enable DMA platform driver Date: Fri, 9 Jul 2010 04:21:22 +0530 Message-Id: <1278629482-32501-11-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:15 +0000 (UTC) This patch will cleanup DMA library in plat-omap and converts the the same into platform driver and makes use of hwmod database and structures for DMA configuration. As a part of platform driver conversion and hwmod support, the API's are cleaned up so that cpu_is_xxxx checks are eliminated and corresponding API/source code is moved to machine specific directories. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap1/Makefile | 2 +- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/plat-omap/dma.c | 1968 +++++++-------------------------- arch/arm/plat-omap/include/plat/dma.h | 320 ++---- 4 files changed, 465 insertions(+), 1827 deletions(-) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index fd4df71..a159af4 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o +obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o obj-y += clock.o clock_data.o opp_data.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ae5f36f..3c5557a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o dma.o omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index f7f571e..418187a 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -39,402 +39,77 @@ #undef DEBUG -#ifndef CONFIG_ARCH_OMAP1 -enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, - DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED -}; - -enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; -#endif - -#define OMAP_DMA_ACTIVE 0x01 -#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe - -#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) - -static int enable_1510_mode; - -static struct omap_dma_global_context_registers { - u32 dma_irqenable_l0; - u32 dma_ocp_sysconfig; - u32 dma_gcr; -} omap_dma_global_context; - -struct omap_dma_lch { - int next_lch; - int dev_id; - u16 saved_csr; - u16 enabled_irqs; - const char *dev_name; - void (*callback)(int lch, u16 ch_status, void *data); - void *data; - -#ifndef CONFIG_ARCH_OMAP1 - /* required for Dynamic chaining */ - int prev_linked_ch; - int next_linked_ch; - int state; - int chain_id; - - int status; -#endif - long flags; -}; - -struct dma_link_info { - int *linked_dmach_q; - int no_of_lchs_linked; - - int q_count; - int q_tail; - int q_head; - - int chain_state; - int chain_mode; - -}; - -static struct dma_link_info *dma_linked_lch; - -#ifndef CONFIG_ARCH_OMAP1 - -/* Chain handling macros */ -#define OMAP_DMA_CHAIN_QINIT(chain_id) \ - do { \ - dma_linked_lch[chain_id].q_head = \ - dma_linked_lch[chain_id].q_tail = \ - dma_linked_lch[chain_id].q_count = 0; \ - } while (0) -#define OMAP_DMA_CHAIN_QFULL(chain_id) \ - (dma_linked_lch[chain_id].no_of_lchs_linked == \ - dma_linked_lch[chain_id].q_count) -#define OMAP_DMA_CHAIN_QLAST(chain_id) \ - do { \ - ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ - dma_linked_lch[chain_id].q_count) \ - } while (0) -#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ - (0 == dma_linked_lch[chain_id].q_count) -#define __OMAP_DMA_CHAIN_INCQ(end) \ - ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) -#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ - dma_linked_lch[chain_id].q_count--; \ - } while (0) - -#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ - dma_linked_lch[chain_id].q_count++; \ - } while (0) -#endif - -static int dma_lch_count; static int dma_chan_count; static int omap_dma_reserve_channels; static spinlock_t dma_chan_lock; static struct omap_dma_lch *dma_chan; -static void __iomem *omap_dma_base; - -static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = { - INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, - INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, - INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, - INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13, - INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD -}; -static inline void disable_lnk(int lch); -static void omap_disable_channel_irq(int lch); -static inline void omap_enable_channel_irq(int lch); +/* + * TODO : clean up usage of below variables since it contains + * device instance information. + */ +static void __iomem *omap_dma_base; +struct omap_system_dma_plat_info *p; +static struct omap_dma_reg_offset *r; +static struct omap_dma_dev_attr *d; -#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ - __func__); -#define dma_read(reg) \ +#define dma_read(reg) \ ({ \ u32 __val; \ - if (cpu_class_is_omap1()) \ - __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \ + \ + if (d->dma_dev_attr & IS_WORD_16) \ + __val = __raw_readw(omap_dma_base + reg); \ else \ - __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \ - __val; \ + __val = __raw_readl(omap_dma_base + reg); \ + __val; \ }) #define dma_write(val, reg) \ ({ \ - if (cpu_class_is_omap1()) \ - __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \ + if (d->dma_dev_attr & IS_WORD_16) \ + __raw_writew((u16)(val), omap_dma_base + reg); \ else \ - __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \ + __raw_writel((val), omap_dma_base + reg); \ }) -#ifdef CONFIG_ARCH_OMAP15XX -/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ -int omap_dma_in_1510_mode(void) -{ - return enable_1510_mode; -} -#else -#define omap_dma_in_1510_mode() 0 -#endif - -#ifdef CONFIG_ARCH_OMAP1 -static inline int get_gdma_dev(int req) -{ - u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; - int shift = ((req - 1) % 5) * 6; - - return ((omap_readl(reg) >> shift) & 0x3f) + 1; -} - -static inline void set_gdma_dev(int req, int dev) -{ - u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; - int shift = ((req - 1) % 5) * 6; - u32 l; - - l = omap_readl(reg); - l &= ~(0x3f << shift); - l |= (dev - 1) << shift; - omap_writel(l, reg); -} -#else -#define set_gdma_dev(req, dev) do {} while (0) -#endif - -/* Omap1 only */ -static void clear_lch_regs(int lch) -{ - int i; - void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch); - - for (i = 0; i < 0x2c; i += 2) - __raw_writew(0, lch_base + i); -} - -void omap_set_dma_priority(int lch, int dst_port, int priority) -{ - unsigned long reg; - u32 l; - - if (cpu_class_is_omap1()) { - switch (dst_port) { - case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ - reg = OMAP_TC_OCPT1_PRIOR; - break; - case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ - reg = OMAP_TC_OCPT2_PRIOR; - break; - case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ - reg = OMAP_TC_EMIFF_PRIOR; - break; - case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ - reg = OMAP_TC_EMIFS_PRIOR; - break; - default: - BUG(); - return; - } - l = omap_readl(reg); - l &= ~(0xf << 8); - l |= (priority & 0xf) << 8; - omap_writel(l, reg); - } - - if (cpu_class_is_omap2()) { - u32 ccr; - - ccr = dma_read(CCR(lch)); - if (priority) - ccr |= (1 << 6); - else - ccr &= ~(1 << 6); - dma_write(ccr, CCR(lch)); - } -} -EXPORT_SYMBOL(omap_set_dma_priority); - -void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, - int frame_count, int sync_mode, - int dma_trigger, int src_or_dst_synch) -{ - u32 l; - - l = dma_read(CSDP(lch)); - l &= ~0x03; - l |= data_type; - dma_write(l, CSDP(lch)); - - if (cpu_class_is_omap1()) { - u16 ccr; - - ccr = dma_read(CCR(lch)); - ccr &= ~(1 << 5); - if (sync_mode == OMAP_DMA_SYNC_FRAME) - ccr |= 1 << 5; - dma_write(ccr, CCR(lch)); - - ccr = dma_read(CCR2(lch)); - ccr &= ~(1 << 2); - if (sync_mode == OMAP_DMA_SYNC_BLOCK) - ccr |= 1 << 2; - dma_write(ccr, CCR2(lch)); - } - - if (cpu_class_is_omap2() && dma_trigger) { - u32 val; - - val = dma_read(CCR(lch)); - - /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ - val &= ~((3 << 19) | 0x1f); - val |= (dma_trigger & ~0x1f) << 14; - val |= dma_trigger & 0x1f; - - if (sync_mode & OMAP_DMA_SYNC_FRAME) - val |= 1 << 5; - else - val &= ~(1 << 5); - - if (sync_mode & OMAP_DMA_SYNC_BLOCK) - val |= 1 << 18; - else - val &= ~(1 << 18); - - if (src_or_dst_synch) - val |= 1 << 24; /* source synch */ - else - val &= ~(1 << 24); /* dest synch */ - - dma_write(val, CCR(lch)); - } - - dma_write(elem_count, CEN(lch)); - dma_write(frame_count, CFN(lch)); -} -EXPORT_SYMBOL(omap_set_dma_transfer_params); - -void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) -{ - BUG_ON(omap_dma_in_1510_mode()); - - if (cpu_class_is_omap1()) { - u16 w; - - w = dma_read(CCR2(lch)); - w &= ~0x03; - - switch (mode) { - case OMAP_DMA_CONSTANT_FILL: - w |= 0x01; - break; - case OMAP_DMA_TRANSPARENT_COPY: - w |= 0x02; - break; - case OMAP_DMA_COLOR_DIS: - break; - default: - BUG(); - } - dma_write(w, CCR2(lch)); - - w = dma_read(LCH_CTRL(lch)); - w &= ~0x0f; - /* Default is channel type 2D */ - if (mode) { - dma_write((u16)color, COLOR_L(lch)); - dma_write((u16)(color >> 16), COLOR_U(lch)); - w |= 1; /* Channel type G */ - } - dma_write(w, LCH_CTRL(lch)); - } - - if (cpu_class_is_omap2()) { - u32 val; - - val = dma_read(CCR(lch)); - val &= ~((1 << 17) | (1 << 16)); - - switch (mode) { - case OMAP_DMA_CONSTANT_FILL: - val |= 1 << 16; - break; - case OMAP_DMA_TRANSPARENT_COPY: - val |= 1 << 17; - break; - case OMAP_DMA_COLOR_DIS: - break; - default: - BUG(); - } - dma_write(val, CCR(lch)); - - color &= 0xffffff; - dma_write(color, COLOR(lch)); - } -} -EXPORT_SYMBOL(omap_set_dma_color_mode); - -void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) -{ - if (cpu_class_is_omap2()) { - u32 csdp; - - csdp = dma_read(CSDP(lch)); - csdp &= ~(0x3 << 16); - csdp |= (mode << 16); - dma_write(csdp, CSDP(lch)); - } -} -EXPORT_SYMBOL(omap_set_dma_write_mode); - -void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) -{ - if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { - u32 l; - - l = dma_read(LCH_CTRL(lch)); - l &= ~0x7; - l |= mode; - dma_write(l, LCH_CTRL(lch)); - } -} -EXPORT_SYMBOL(omap_set_dma_channel_mode); - -/* Note that src_port is only for omap1 */ void omap_set_dma_src_params(int lch, int src_port, int src_amode, unsigned long src_start, int src_ei, int src_fi) { - u32 l; + u32 l, reg = 0; - if (cpu_class_is_omap1()) { + if (d->dma_dev_attr & SRC_PORT) { u16 w; - - w = dma_read(CSDP(lch)); + reg = (r->lch_base * lch) + r->common_ch.csdp; + w = dma_read(reg); w &= ~(0x1f << 2); w |= src_port << 2; - dma_write(w, CSDP(lch)); + dma_write(w, reg); } - l = dma_read(CCR(lch)); + reg = (r->lch_base * lch) + r->common_ch.ccr; + l = dma_read(reg); l &= ~(0x03 << 12); l |= src_amode << 12; - dma_write(l, CCR(lch)); + dma_write(l, reg); - if (cpu_class_is_omap1()) { - dma_write(src_start >> 16, CSSA_U(lch)); - dma_write((u16)src_start, CSSA_L(lch)); + if (!(d->dma_dev_attr & IS_CSSA_32)) { + reg = (r->lch_base * lch) + r->ch_specific.cssa_u; + dma_write(src_start >> 16, reg); + reg = (r->lch_base * lch) + r->ch_specific.cssa_l; + dma_write((u16)src_start, reg); + } else { + reg = (r->lch_base * lch) + r->ch_specific.cssa; + dma_write(src_start, reg); + l = dma_read(reg); } - if (cpu_class_is_omap2()) - dma_write(src_start, CSSA(lch)); - - dma_write(src_ei, CSEI(lch)); - dma_write(src_fi, CSFI(lch)); + reg = (r->lch_base * lch) + r->common_ch.csei; + dma_write(src_ei, reg); + reg = (r->lch_base * lch) + r->common_ch.csfi; + dma_write(src_fi, reg); } EXPORT_SYMBOL(omap_set_dma_src_params); @@ -459,187 +134,171 @@ EXPORT_SYMBOL(omap_set_dma_params); void omap_set_dma_src_index(int lch, int eidx, int fidx) { - if (cpu_class_is_omap2()) - return; + u32 reg; - dma_write(eidx, CSEI(lch)); - dma_write(fidx, CSFI(lch)); + if (d->dma_dev_attr & SRC_INDEX) { + reg = (r->lch_base * lch) + r->common_ch.csei; + dma_write(eidx, reg); + reg = (r->lch_base * lch) + r->common_ch.csfi; + dma_write(fidx, reg); + } + return; } EXPORT_SYMBOL(omap_set_dma_src_index); void omap_set_dma_src_data_pack(int lch, int enable) { - u32 l; + u32 l, reg; - l = dma_read(CSDP(lch)); + reg = (r->lch_base * lch) + r->common_ch.csdp; + l = dma_read(reg); l &= ~(1 << 6); if (enable) l |= (1 << 6); - dma_write(l, CSDP(lch)); + dma_write(l, reg); } EXPORT_SYMBOL(omap_set_dma_src_data_pack); void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) { unsigned int burst = 0; - u32 l; + u32 l, reg; - l = dma_read(CSDP(lch)); + reg = (r->lch_base * lch) + r->common_ch.csdp; + l = dma_read(reg); l &= ~(0x03 << 7); switch (burst_mode) { case OMAP_DMA_DATA_BURST_DIS: break; case OMAP_DMA_DATA_BURST_4: - if (cpu_class_is_omap2()) - burst = 0x1; - else + if (d->dma_dev_attr & IS_BURST_ONLY4) burst = 0x2; + else + burst = 0x1; break; case OMAP_DMA_DATA_BURST_8: - if (cpu_class_is_omap2()) { + if (!(d->dma_dev_attr & IS_BURST_ONLY4)) { burst = 0x2; break; } - /* - * not supported by current hardware on OMAP1 - * w |= (0x03 << 7); - * fall through - */ case OMAP_DMA_DATA_BURST_16: - if (cpu_class_is_omap2()) { - burst = 0x3; + if (!(d->dma_dev_attr & IS_BURST_ONLY4)) { + burst = 0x2; break; } - /* - * OMAP1 don't support burst 16 - * fall through - */ default: BUG(); } l |= (burst << 7); - dma_write(l, CSDP(lch)); + dma_write(l, reg); } EXPORT_SYMBOL(omap_set_dma_src_burst_mode); -/* Note that dest_port is only for OMAP1 */ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, unsigned long dest_start, int dst_ei, int dst_fi) { - u32 l; + u32 l, reg; - if (cpu_class_is_omap1()) { - l = dma_read(CSDP(lch)); + reg = (r->lch_base * lch) + r->common_ch.csdp; + if (d->dma_dev_attr & DST_PORT) { + l = dma_read(reg); l &= ~(0x1f << 9); l |= dest_port << 9; - dma_write(l, CSDP(lch)); + dma_write(l, reg); } - l = dma_read(CCR(lch)); + reg = (r->lch_base * lch) + r->common_ch.ccr; + l = dma_read(reg); l &= ~(0x03 << 14); l |= dest_amode << 14; - dma_write(l, CCR(lch)); + dma_write(l, reg); - if (cpu_class_is_omap1()) { - dma_write(dest_start >> 16, CDSA_U(lch)); - dma_write(dest_start, CDSA_L(lch)); + if (!(d->dma_dev_attr & IS_CDSA_32)) { + reg = (r->lch_base * lch) + r->ch_specific.cdsa_u; + dma_write(dest_start >> 16, reg); + reg = (r->lch_base * lch) + r->ch_specific.cdsa_l; + dma_write(dest_start, reg); + } else { + reg = (r->lch_base * lch) + r->ch_specific.cdsa; + dma_write(dest_start, reg); } - if (cpu_class_is_omap2()) - dma_write(dest_start, CDSA(lch)); - - dma_write(dst_ei, CDEI(lch)); - dma_write(dst_fi, CDFI(lch)); + reg = (r->lch_base * lch) + r->common_ch.cdei; + dma_write(dst_ei, reg); + reg = (r->lch_base * lch) + r->common_ch.cdfi; + dma_write(dst_fi, reg); } EXPORT_SYMBOL(omap_set_dma_dest_params); void omap_set_dma_dest_index(int lch, int eidx, int fidx) { - if (cpu_class_is_omap2()) - return; + u32 reg; - dma_write(eidx, CDEI(lch)); - dma_write(fidx, CDFI(lch)); + if (d->dma_dev_attr & SRC_INDEX) { + reg = (r->lch_base * lch) + r->common_ch.cdei; + dma_write(eidx, reg); + reg = (r->lch_base * lch) + r->common_ch.cdfi; + dma_write(fidx, reg); + } + return; } EXPORT_SYMBOL(omap_set_dma_dest_index); void omap_set_dma_dest_data_pack(int lch, int enable) { - u32 l; + u32 l, reg; - l = dma_read(CSDP(lch)); + reg = (r->lch_base * lch) + r->common_ch.csdp; + l = dma_read(reg); l &= ~(1 << 13); if (enable) l |= 1 << 13; - dma_write(l, CSDP(lch)); + dma_write(l, reg); } EXPORT_SYMBOL(omap_set_dma_dest_data_pack); void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) { unsigned int burst = 0; - u32 l; + u32 l, reg; - l = dma_read(CSDP(lch)); + reg = (r->lch_base * lch) + r->common_ch.csdp; + l = dma_read(reg); l &= ~(0x03 << 14); switch (burst_mode) { case OMAP_DMA_DATA_BURST_DIS: break; case OMAP_DMA_DATA_BURST_4: - if (cpu_class_is_omap2()) - burst = 0x1; - else + if (d->dma_dev_attr & IS_BURST_ONLY4) burst = 0x2; + else + burst = 0x1; break; case OMAP_DMA_DATA_BURST_8: - if (cpu_class_is_omap2()) - burst = 0x2; - else + if (d->dma_dev_attr & IS_BURST_ONLY4) burst = 0x3; + else + burst = 0x2; break; case OMAP_DMA_DATA_BURST_16: - if (cpu_class_is_omap2()) { + if (!(d->dma_dev_attr & IS_BURST_ONLY4)) { burst = 0x3; break; } - /* - * OMAP1 don't support burst 16 - * fall through - */ default: printk(KERN_ERR "Invalid DMA burst mode\n"); BUG(); return; } l |= (burst << 14); - dma_write(l, CSDP(lch)); + dma_write(l, reg); } EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); -static inline void omap_enable_channel_irq(int lch) -{ - u32 status; - - /* Clear CSR */ - if (cpu_class_is_omap1()) - status = dma_read(CSR(lch)); - else if (cpu_class_is_omap2()) - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); - - /* Enable some nice interrupts. */ - dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); -} - -static void omap_disable_channel_irq(int lch) -{ - if (cpu_class_is_omap2()) - dma_write(0, CICR(lch)); -} - void omap_enable_dma_irq(int lch, u16 bits) { dma_chan[lch].enabled_irqs |= bits; @@ -652,88 +311,14 @@ void omap_disable_dma_irq(int lch, u16 bits) } EXPORT_SYMBOL(omap_disable_dma_irq); -static inline void enable_lnk(int lch) -{ - u32 l; - - l = dma_read(CLNK_CTRL(lch)); - - if (cpu_class_is_omap1()) - l &= ~(1 << 14); - - /* Set the ENABLE_LNK bits */ - if (dma_chan[lch].next_lch != -1) - l = dma_chan[lch].next_lch | (1 << 15); - -#ifndef CONFIG_ARCH_OMAP1 - if (cpu_class_is_omap2()) - if (dma_chan[lch].next_linked_ch != -1) - l = dma_chan[lch].next_linked_ch | (1 << 15); -#endif - - dma_write(l, CLNK_CTRL(lch)); -} - -static inline void disable_lnk(int lch) -{ - u32 l; - - l = dma_read(CLNK_CTRL(lch)); - - /* Disable interrupts */ - if (cpu_class_is_omap1()) { - dma_write(0, CICR(lch)); - /* Set the STOP_LNK bit */ - l |= 1 << 14; - } - - if (cpu_class_is_omap2()) { - omap_disable_channel_irq(lch); - /* Clear the ENABLE_LNK bit */ - l &= ~(1 << 15); - } - - dma_write(l, CLNK_CTRL(lch)); - dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; -} - -static inline void omap2_enable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (!cpu_class_is_omap2()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - val = dma_read(IRQENABLE_L0); - val |= 1 << lch; - dma_write(val, IRQENABLE_L0); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - -static inline void omap2_disable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (!cpu_class_is_omap2()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - val = dma_read(IRQENABLE_L0); - val &= ~(1 << lch); - dma_write(val, IRQENABLE_L0); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) { - int ch, free_ch = -1; unsigned long flags; struct omap_dma_lch *chan; + int ch, free_ch = -1; + u32 reg; spin_lock_irqsave(&dma_chan_lock, flags); for (ch = 0; ch < dma_chan_count; ch++) { @@ -750,10 +335,9 @@ int omap_request_dma(int dev_id, const char *dev_name, chan = dma_chan + free_ch; chan->dev_id = dev_id; - if (cpu_class_is_omap1()) - clear_lch_regs(free_ch); - - if (cpu_class_is_omap2()) + if (!d->dma_dev_attr & DMA_LINKED_LCH) + p->clear_lch_regs(free_ch); + else omap_clear_dma(free_ch); spin_unlock_irqrestore(&dma_chan_lock, flags); @@ -763,46 +347,34 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->data = data; chan->flags = 0; -#ifndef CONFIG_ARCH_OMAP1 - if (cpu_class_is_omap2()) { + if (d->dma_dev_attr & DMA_LINKED_LCH) { chan->chain_id = -1; chan->next_linked_ch = -1; } -#endif - chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; - if (cpu_class_is_omap1()) - chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; - else if (cpu_class_is_omap2()) + if (p->enable_irq_lch) chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ; + else + chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; - if (cpu_is_omap16xx()) { - /* If the sync device is set, configure it dynamically. */ - if (dev_id != 0) { - set_gdma_dev(free_ch + 1, dev_id); - dev_id = free_ch + 1; - } - /* - * Disable the 1510 compatibility mode and set the sync device - * id. - */ - dma_write(dev_id | (1 << 10), CCR(free_ch)); - } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { - dma_write(dev_id, CCR(free_ch)); - } + if (p->sync_device_set) + p->sync_device_set(dev_id, free_ch); + + if (p->enable_irq_lch) { + spin_lock_irqsave(&dma_chan_lock, flags); + p->enable_irq_lch(free_ch); + spin_unlock_irqrestore(&dma_chan_lock, flags); - if (cpu_class_is_omap2()) { - omap2_enable_irq_lch(free_ch); - omap_enable_channel_irq(free_ch); + p->enable_channel_irq(free_ch); /* Clear the CSR register and IRQ status register */ - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); - dma_write(1 << free_ch, IRQSTATUS_L0); + reg = (r->lch_base * free_ch) + r->common_ch.csr; + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, reg); + dma_write(1 << free_ch, r->irqreg.irq_status_l0); } *dma_ch_out = free_ch; - return 0; } EXPORT_SYMBOL(omap_request_dma); @@ -810,6 +382,7 @@ EXPORT_SYMBOL(omap_request_dma); void omap_free_dma(int lch) { unsigned long flags; + u32 reg; if (dma_chan[lch].dev_id == -1) { pr_err("omap_dma: trying to free unallocated DMA channel %d\n", @@ -817,26 +390,32 @@ void omap_free_dma(int lch) return; } - if (cpu_class_is_omap1()) { - /* Disable all DMA interrupts for the channel. */ - dma_write(0, CICR(lch)); - /* Make sure the DMA transfer is stopped. */ - dma_write(0, CCR(lch)); - } - - if (cpu_class_is_omap2()) { - omap2_disable_irq_lch(lch); + if (p->disable_irq_lch) { + unsigned long flags; + spin_lock_irqsave(&dma_chan_lock, flags); + p->disable_irq_lch(lch); + spin_unlock_irqrestore(&dma_chan_lock, flags); /* Clear the CSR register and IRQ status register */ - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); - dma_write(1 << lch, IRQSTATUS_L0); + reg = (r->lch_base * lch) + r->common_ch.csr; + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, reg); + dma_write(1 << lch, r->irqreg.irq_status_l0); /* Disable all DMA interrupts for the channel. */ - dma_write(0, CICR(lch)); + reg = (r->lch_base * lch) + r->common_ch.cicr; + dma_write(0, reg); /* Make sure the DMA transfer is stopped. */ - dma_write(0, CCR(lch)); + reg = (r->lch_base * lch) + r->common_ch.ccr; + dma_write(0, reg); omap_clear_dma(lch); + } else { + /* Disable all DMA interrupts for the channel. */ + reg = (r->lch_base * lch) + r->common_ch.cicr; + dma_write(0, reg); + /* Make sure the DMA transfer is stopped. */ + reg = (r->lch_base * lch) + r->common_ch.ccr; + dma_write(0, reg); } spin_lock_irqsave(&dma_chan_lock, flags); @@ -861,8 +440,7 @@ void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) { u32 reg; - - if (!cpu_class_is_omap2()) { + if (!d->dma_dev_attr & GLOBAL_PRIORITY) { printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); return; } @@ -876,7 +454,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) reg |= (0x3 & tparams) << 12; reg |= (arb_rate & 0xff) << 16; - dma_write(reg, GCR); + dma_write(reg, r->gcr); } EXPORT_SYMBOL(omap_dma_set_global_params); @@ -893,21 +471,20 @@ int omap_dma_set_prio_lch(int lch, unsigned char read_prio, unsigned char write_prio) { - u32 l; + u32 l, reg; - if (unlikely((lch < 0 || lch >= dma_lch_count))) { + if (unlikely((lch < 0 || lch >= d->dma_lch_count))) { printk(KERN_ERR "Invalid channel id\n"); return -EINVAL; } - l = dma_read(CCR(lch)); + reg = (r->lch_base * lch) + r->common_ch.ccr; + l = dma_read(reg); l &= ~((1 << 6) | (1 << 26)); - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) - l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); - else - l |= ((read_prio & 0x1) << 6); - dma_write(l, CCR(lch)); + if (p->set_prio_lch) + l = p->set_prio_lch(l, read_prio, write_prio); + dma_write(l, reg); return 0; } EXPORT_SYMBOL(omap_dma_set_prio_lch); @@ -922,22 +499,19 @@ void omap_clear_dma(int lch) local_irq_save(flags); - if (cpu_class_is_omap1()) { - u32 l; - - l = dma_read(CCR(lch)); - l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + /* OMAP1 only */ + if (!(d->dma_dev_attr & DMA_LINKED_LCH) && p->clear_ccr_csr) + p->clear_ccr_csr(lch); - /* Clear pending interrupts */ - l = dma_read(CSR(lch)); - } - - if (cpu_class_is_omap2()) { + /* OMAP2 only */ + if (d->dma_dev_attr & DMA_LINKED_LCH) { + u32 reg; int i; - void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch); - for (i = 0; i < 0x44; i += 4) - __raw_writel(0, lch_base + i); + reg = (r->lch_base * lch) + 0x80; + for (i = 0; i < 0x44; i += 4) { + reg = reg + i; + dma_write(0, reg); + } } local_irq_restore(flags); @@ -946,24 +520,28 @@ EXPORT_SYMBOL(omap_clear_dma); void omap_start_dma(int lch) { - u32 l; + u32 l, reg; /* * The CPC/CDAC register needs to be initialized to zero * before starting dma transfer. */ - if (cpu_is_omap15xx()) - dma_write(0, CPC(lch)); - else - dma_write(0, CDAC(lch)); + if (d->dma_dev_attr & ENABLE_1510_MODE) { + reg = (r->lch_base * lch) + r->common_ch.cpc; + dma_write(0, reg); + } else { + reg = (r->lch_base * lch) + r->common_ch.cdac; + dma_write(0, reg); + } - if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { + if ((!d->dma_dev_attr & ENABLE_1510_MODE) && + dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; - char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[d->dma_lch_count]; dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ - enable_lnk(lch); + p->enable_lnk(lch); memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); cur_lch = dma_chan[lch].next_lch; @@ -976,31 +554,28 @@ void omap_start_dma(int lch) /* Mark the current channel */ dma_chan_link_map[cur_lch] = 1; - enable_lnk(cur_lch); - omap_enable_channel_irq(cur_lch); + p->enable_lnk(cur_lch); + p->enable_channel_irq(cur_lch); cur_lch = next_lch; } while (next_lch != -1); - } else if (cpu_is_omap242x() || - (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) { + } - /* Errata: Need to write lch even if not using chaining */ - dma_write(lch, CLNK_CTRL(lch)); + if (p->errata & DMA_CHAINING_ERRATA) { + reg = (r->lch_base * lch) + r->common_ch.clnk_ctrl; + dma_write(lch, reg); } - omap_enable_channel_irq(lch); + p->enable_channel_irq(lch); - l = dma_read(CCR(lch)); + reg = (r->lch_base * lch) + r->common_ch.ccr; + l = dma_read(reg); - /* - * Errata: On ES2.0 BUFFERING disable must be set. - * This will always fail on ES1.0 - */ - if (cpu_is_omap24xx()) + if (p->errata & DMA_BUFF_DISABLE_ERRATA) l |= OMAP_DMA_CCR_EN; l |= OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + dma_write(l, reg); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } @@ -1008,19 +583,22 @@ EXPORT_SYMBOL(omap_start_dma); void omap_stop_dma(int lch) { - u32 l; + u32 l, reg; /* Disable all interrupts on the channel */ - if (cpu_class_is_omap1()) - dma_write(0, CICR(lch)); + reg = (r->lch_base * lch) + r->common_ch.cicr; + if (!p->disable_irq_lch) + dma_write(0, reg); - l = dma_read(CCR(lch)); + reg = (r->lch_base * lch) + r->common_ch.ccr; + l = dma_read(reg); l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + dma_write(l, reg); - if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { + if (!(d->dma_dev_attr & ENABLE_1510_MODE) && + dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; - char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[d->dma_lch_count]; memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); do { @@ -1030,7 +608,7 @@ void omap_stop_dma(int lch) /* Mark the current channel */ dma_chan_link_map[cur_lch] = 1; - disable_lnk(cur_lch); + p->disable_lnk(cur_lch); next_lch = dma_chan[cur_lch].next_lch; cur_lch = next_lch; @@ -1079,21 +657,30 @@ EXPORT_SYMBOL(omap_set_dma_callback); dma_addr_t omap_get_dma_src_pos(int lch) { dma_addr_t offset = 0; + u32 reg; - if (cpu_is_omap15xx()) - offset = dma_read(CPC(lch)); - else - offset = dma_read(CSAC(lch)); + if (d->dma_dev_attr & ENABLE_1510_MODE) { + reg = (r->lch_base * lch) + r->common_ch.cpc; + offset = dma_read(reg); + } else { + reg = (r->lch_base * lch) + r->common_ch.csac; + offset = dma_read(reg); + } /* * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is * read before the DMA controller finished disabling the channel. */ - if (!cpu_is_omap15xx() && offset == 0) - offset = dma_read(CSAC(lch)); - - if (cpu_class_is_omap1()) - offset |= (dma_read(CSSA_U(lch)) << 16); + if ((p->errata & OMAP3_3_ERRATUM) && !(d->dma_dev_attr & IS_WORD_16) + && (offset == 0)) { + reg = (r->lch_base * lch) + r->common_ch.csac; + offset = dma_read(reg); + } + if ((p->errata & OMAP3_3_ERRATUM) && (d->dma_dev_attr & IS_WORD_16) + && (offset == 0)) { + reg = (r->lch_base * lch) + r->ch_specific.cssa_u; + offset |= dma_read(reg) << 16; + } return offset; } @@ -1110,21 +697,30 @@ EXPORT_SYMBOL(omap_get_dma_src_pos); dma_addr_t omap_get_dma_dst_pos(int lch) { dma_addr_t offset = 0; + u32 reg; - if (cpu_is_omap15xx()) - offset = dma_read(CPC(lch)); - else - offset = dma_read(CDAC(lch)); + if (d->dma_dev_attr & ENABLE_1510_MODE) { + reg = (r->lch_base * lch) + r->common_ch.cpc; + offset = dma_read(reg); + } else { + reg = (r->lch_base * lch) + r->common_ch.cdac; + offset = dma_read(reg); + } /* * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is * read before the DMA controller finished disabling the channel. */ - if (!cpu_is_omap15xx() && offset == 0) - offset = dma_read(CDAC(lch)); - - if (cpu_class_is_omap1()) - offset |= (dma_read(CDSA_U(lch)) << 16); + if ((p->errata & OMAP3_3_ERRATUM) && !(d->dma_dev_attr & IS_WORD_16) + && (offset == 0)) { + reg = (r->lch_base * lch) + r->common_ch.cdac; + offset = dma_read(reg); + } + if ((p->errata & OMAP3_3_ERRATUM) && (d->dma_dev_attr & IS_WORD_16) + && (offset == 0)) { + reg = (r->lch_base * lch) + r->ch_specific.cdsa_u; + offset |= dma_read(reg) << 16; + } return offset; } @@ -1132,23 +728,18 @@ EXPORT_SYMBOL(omap_get_dma_dst_pos); int omap_get_dma_active_status(int lch) { - return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0; + u32 reg; + reg = (r->lch_base * lch) + r->common_ch.ccr; + return (dma_read(reg) & OMAP_DMA_CCR_EN) != 0; } EXPORT_SYMBOL(omap_get_dma_active_status); int omap_dma_running(void) { - int lch; - - if (cpu_class_is_omap1()) - if (omap_lcd_dma_running()) - return 1; + if (p->dma_running) + return p->dma_running(dma_chan_count); - for (lch = 0; lch < dma_chan_count; lch++) - if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) - return 1; - - return 0; + return -EPERM; } /* @@ -1158,10 +749,12 @@ int omap_dma_running(void) */ void omap_dma_link_lch(int lch_head, int lch_queue) { - if (omap_dma_in_1510_mode()) { + u32 reg; + + reg = (r->lch_base * lch_head) + r->common_ch.ccr; + if (d->dma_dev_attr & ENABLE_1510_MODE) { if (lch_head == lch_queue) { - dma_write(dma_read(CCR(lch_head)) | (3 << 8), - CCR(lch_head)); + dma_write((dma_read(reg) | (3 << 8)), reg); return; } printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); @@ -1172,7 +765,7 @@ void omap_dma_link_lch(int lch_head, int lch_queue) if ((dma_chan[lch_head].dev_id == -1) || (dma_chan[lch_queue].dev_id == -1)) { printk(KERN_ERR "omap_dma: trying to link " - "non requested channels\n"); + "non requested channels\n"); dump_stack(); } @@ -1185,10 +778,12 @@ EXPORT_SYMBOL(omap_dma_link_lch); */ void omap_dma_unlink_lch(int lch_head, int lch_queue) { - if (omap_dma_in_1510_mode()) { + u32 reg; + + reg = (r->lch_base * lch_head) + r->common_ch.ccr; + if (d->dma_dev_attr & ENABLE_1510_MODE) { if (lch_head == lch_queue) { - dma_write(dma_read(CCR(lch_head)) & ~(3 << 8), - CCR(lch_head)); + dma_write((dma_read(reg) & ~(3 << 8)), reg); return; } printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); @@ -1199,1004 +794,199 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) if (dma_chan[lch_head].next_lch != lch_queue || dma_chan[lch_head].next_lch == -1) { printk(KERN_ERR "omap_dma: trying to unlink " - "non linked channels\n"); + "non linked channels\n"); dump_stack(); } if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) { printk(KERN_ERR "omap_dma: You need to stop the DMA channels " - "before unlinking\n"); + "before unlinking\n"); dump_stack(); } - dma_chan[lch_head].next_lch = -1; } EXPORT_SYMBOL(omap_dma_unlink_lch); -/*----------------------------------------------------------------------------*/ - -#ifndef CONFIG_ARCH_OMAP1 -/* Create chain of DMA channesls */ -static void create_dma_lch_chain(int lch_head, int lch_queue) +static int __devinit omap_system_dma_probe(struct platform_device *pdev) { - u32 l; - - /* Check if this is the first link in chain */ - if (dma_chan[lch_head].next_linked_ch == -1) { - dma_chan[lch_head].next_linked_ch = lch_queue; - dma_chan[lch_head].prev_linked_ch = lch_queue; - dma_chan[lch_queue].next_linked_ch = lch_head; - dma_chan[lch_queue].prev_linked_ch = lch_head; - } - - /* a link exists, link the new channel in circular chain */ - else { - dma_chan[lch_queue].next_linked_ch = - dma_chan[lch_head].next_linked_ch; - dma_chan[lch_queue].prev_linked_ch = lch_head; - dma_chan[lch_head].next_linked_ch = lch_queue; - dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch = - lch_queue; - } - - l = dma_read(CLNK_CTRL(lch_head)); - l &= ~(0x1f); - l |= lch_queue; - dma_write(l, CLNK_CTRL(lch_head)); + struct omap_system_dma_plat_info *pdata = pdev->dev.platform_data; + struct resource *mem; + int irq_count, ret = 0; + int dma_irq; + char irq_name[14]; - l = dma_read(CLNK_CTRL(lch_queue)); - l &= ~(0x1f); - l |= (dma_chan[lch_queue].next_linked_ch); - dma_write(l, CLNK_CTRL(lch_queue)); -} - -/** - * @brief omap_request_dma_chain : Request a chain of DMA channels - * - * @param dev_id - Device id using the dma channel - * @param dev_name - Device name - * @param callback - Call back function - * @chain_id - - * @no_of_chans - Number of channels requested - * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN - * OMAP_DMA_DYNAMIC_CHAIN - * @params - Channel parameters - * - * @return - Success : 0 - * Failure: -EINVAL/-ENOMEM - */ -int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int lch, u16 ch_status, - void *data), - int *chain_id, int no_of_chans, int chain_mode, - struct omap_dma_channel_params params) -{ - int *channels; - int i, err; - - /* Is the chain mode valid ? */ - if (chain_mode != OMAP_DMA_STATIC_CHAIN - && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) { - printk(KERN_ERR "Invalid chain mode requested\n"); + if (!pdata) { + dev_err(&pdev->dev, "%s: System DMA initialized without" + "platform data\n", __func__); return -EINVAL; } - if (unlikely((no_of_chans < 1 - || no_of_chans > dma_lch_count))) { - printk(KERN_ERR "Invalid Number of channels requested\n"); - return -EINVAL; - } - - /* - * Allocate a queue to maintain the status of the channels - * in the chain - */ - channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); - if (channels == NULL) { - printk(KERN_ERR "omap_dma: No memory for channel queue\n"); - return -ENOMEM; - } - - /* request and reserve DMA channels for the chain */ - for (i = 0; i < no_of_chans; i++) { - err = omap_request_dma(dev_id, dev_name, - callback, NULL, &channels[i]); - if (err < 0) { - int j; - for (j = 0; j < i; j++) - omap_free_dma(channels[j]); - kfree(channels); - printk(KERN_ERR "omap_dma: Request failed %d\n", err); - return err; - } - dma_chan[channels[i]].prev_linked_ch = -1; - dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; - - /* - * Allowing client drivers to set common parameters now, - * so that later only relevant (src_start, dest_start - * and element count) can be set - */ - omap_set_dma_params(channels[i], ¶ms); - } - - *chain_id = channels[0]; - dma_linked_lch[*chain_id].linked_dmach_q = channels; - dma_linked_lch[*chain_id].chain_mode = chain_mode; - dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED; - dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans; - - for (i = 0; i < no_of_chans; i++) - dma_chan[channels[i]].chain_id = *chain_id; - - /* Reset the Queue pointers */ - OMAP_DMA_CHAIN_QINIT(*chain_id); - - /* Set up the chain */ - if (no_of_chans == 1) - create_dma_lch_chain(channels[0], channels[0]); - else { - for (i = 0; i < (no_of_chans - 1); i++) - create_dma_lch_chain(channels[i], channels[i + 1]); - } - - return 0; -} -EXPORT_SYMBOL(omap_request_dma_chain); - -/** - * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the - * params after setting it. Dont do this while dma is running!! - * - * @param chain_id - Chained logical channel id. - * @param params - * - * @return - Success : 0 - * Failure : -EINVAL - */ -int omap_modify_dma_chain_params(int chain_id, - struct omap_dma_channel_params params) -{ - int *channels; - u32 i; + p = pdata; + r = p->dma_reg_offset; + d = p->dma_attr; - /* Check for input params */ - if (unlikely((chain_id < 0 - || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "%s: no mem resource\n", __func__); return -EINVAL; } - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - channels = dma_linked_lch[chain_id].linked_dmach_q; - - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { - /* - * Allowing client drivers to set common parameters now, - * so that later only relevant (src_start, dest_start - * and element count) can be set - */ - omap_set_dma_params(channels[i], ¶ms); + omap_dma_base = ioremap(mem->start, resource_size(mem)); + if (!omap_dma_base) { + dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); + ret = -ENOMEM; + goto exit_release_region; } - return 0; -} -EXPORT_SYMBOL(omap_modify_dma_chain_params); + if ((d->dma_dev_attr & RESERVE_CHANNEL) && omap_dma_reserve_channels + && (omap_dma_reserve_channels <= (d->dma_lch_count))) + d->dma_lch_count = omap_dma_reserve_channels; -/** - * @brief omap_free_dma_chain - Free all the logical channels in a chain. - * - * @param chain_id - * - * @return - Success : 0 - * Failure : -EINVAL - */ -int omap_free_dma_chain(int chain_id) -{ - int *channels; - u32 i; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { - dma_chan[channels[i]].next_linked_ch = -1; - dma_chan[channels[i]].prev_linked_ch = -1; - dma_chan[channels[i]].chain_id = -1; - dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; - omap_free_dma(channels[i]); - } - - kfree(channels); - - dma_linked_lch[chain_id].linked_dmach_q = NULL; - dma_linked_lch[chain_id].chain_mode = -1; - dma_linked_lch[chain_id].chain_state = -1; - - return (0); -} -EXPORT_SYMBOL(omap_free_dma_chain); - -/** - * @brief omap_dma_chain_status - Check if the chain is in - * active / inactive state. - * @param chain_id - * - * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE - * Failure : -EINVAL - */ -int omap_dma_chain_status(int chain_id) -{ - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - pr_debug("CHAINID=%d, qcnt=%d\n", chain_id, - dma_linked_lch[chain_id].q_count); - - if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) - return OMAP_DMA_CHAIN_INACTIVE; - - return OMAP_DMA_CHAIN_ACTIVE; -} -EXPORT_SYMBOL(omap_dma_chain_status); - -/** - * @brief omap_dma_chain_a_transfer - Get a free channel from a chain, - * set the params and start the transfer. - * - * @param chain_id - * @param src_start - buffer start address - * @param dest_start - Dest address - * @param elem_count - * @param frame_count - * @param callbk_data - channel callback parameter data. - * - * @return - Success : 0 - * Failure: -EINVAL/-EBUSY - */ -int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, - int elem_count, int frame_count, void *callbk_data) -{ - int *channels; - u32 l, lch; - int start_dma = 0; - - /* - * if buffer size is less than 1 then there is - * no use of starting the chain - */ - if (elem_count < 1) { - printk(KERN_ERR "Invalid buffer size\n"); - return -EINVAL; - } - - /* Check for input params */ - if (unlikely((chain_id < 0 - || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exist\n"); - return -EINVAL; - } - - /* Check if all the channels in chain are in use */ - if (OMAP_DMA_CHAIN_QFULL(chain_id)) - return -EBUSY; - - /* Frame count may be negative in case of indexed transfers */ - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get a free channel */ - lch = channels[dma_linked_lch[chain_id].q_tail]; - - /* Store the callback data */ - dma_chan[lch].data = callbk_data; - - /* Increment the q_tail */ - OMAP_DMA_CHAIN_INCQTAIL(chain_id); - - /* Set the params to the free channel */ - if (src_start != 0) - dma_write(src_start, CSSA(lch)); - if (dest_start != 0) - dma_write(dest_start, CDSA(lch)); - - /* Write the buffer size */ - dma_write(elem_count, CEN(lch)); - dma_write(frame_count, CFN(lch)); - - /* - * If the chain is dynamically linked, - * then we may have to start the chain if its not active - */ - if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { - - /* - * In Dynamic chain, if the chain is not started, - * queue the channel - */ - if (dma_linked_lch[chain_id].chain_state == - DMA_CHAIN_NOTSTARTED) { - /* Enable the link in previous channel */ - if (dma_chan[dma_chan[lch].prev_linked_ch].state == - DMA_CH_QUEUED) - enable_lnk(dma_chan[lch].prev_linked_ch); - dma_chan[lch].state = DMA_CH_QUEUED; - } - - /* - * Chain is already started, make sure its active, - * if not then start the chain - */ - else { - start_dma = 1; - - if (dma_chan[dma_chan[lch].prev_linked_ch].state == - DMA_CH_STARTED) { - enable_lnk(dma_chan[lch].prev_linked_ch); - dma_chan[lch].state = DMA_CH_QUEUED; - start_dma = 0; - if (0 == ((1 << 7) & dma_read( - CCR(dma_chan[lch].prev_linked_ch)))) { - disable_lnk(dma_chan[lch]. - prev_linked_ch); - pr_debug("\n prev ch is stopped\n"); - start_dma = 1; - } - } - - else if (dma_chan[dma_chan[lch].prev_linked_ch].state - == DMA_CH_QUEUED) { - enable_lnk(dma_chan[lch].prev_linked_ch); - dma_chan[lch].state = DMA_CH_QUEUED; - start_dma = 0; - } - omap_enable_channel_irq(lch); - - l = dma_read(CCR(lch)); - - if ((0 == (l & (1 << 24)))) - l &= ~(1 << 25); - else - l |= (1 << 25); - if (start_dma == 1) { - if (0 == (l & (1 << 7))) { - l |= (1 << 7); - dma_chan[lch].state = DMA_CH_STARTED; - pr_debug("starting %d\n", lch); - dma_write(l, CCR(lch)); - } else - start_dma = 0; - } else { - if (0 == (l & (1 << 7))) - dma_write(l, CCR(lch)); - } - dma_chan[lch].flags |= OMAP_DMA_ACTIVE; - } - } - - return 0; -} -EXPORT_SYMBOL(omap_dma_chain_a_transfer); - -/** - * @brief omap_start_dma_chain_transfers - Start the chain - * - * @param chain_id - * - * @return - Success : 0 - * Failure : -EINVAL/-EBUSY - */ -int omap_start_dma_chain_transfers(int chain_id) -{ - int *channels; - u32 l, i; - - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) { - printk(KERN_ERR "Chain is already started\n"); - return -EBUSY; - } - - if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) { - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; - i++) { - enable_lnk(channels[i]); - omap_enable_channel_irq(channels[i]); - } - } else { - omap_enable_channel_irq(channels[0]); - } - - l = dma_read(CCR(channels[0])); - l |= (1 << 7); - dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; - dma_chan[channels[0]].state = DMA_CH_STARTED; - - if ((0 == (l & (1 << 24)))) - l &= ~(1 << 25); - else - l |= (1 << 25); - dma_write(l, CCR(channels[0])); - - dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; - - return 0; -} -EXPORT_SYMBOL(omap_start_dma_chain_transfers); - -/** - * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain. - * - * @param chain_id - * - * @return - Success : 0 - * Failure : EINVAL - */ -int omap_stop_dma_chain_transfers(int chain_id) -{ - int *channels; - u32 l, i; - u32 sys_cf; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* - * DMA Errata: - * Special programming model needed to disable DMA before end of block - */ - sys_cf = dma_read(OCP_SYSCONFIG); - l = sys_cf; - /* Middle mode reg set no Standby */ - l &= ~((1 << 12)|(1 << 13)); - dma_write(l, OCP_SYSCONFIG); - - for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { - - /* Stop the Channel transmission */ - l = dma_read(CCR(channels[i])); - l &= ~(1 << 7); - dma_write(l, CCR(channels[i])); - - /* Disable the link in all the channels */ - disable_lnk(channels[i]); - dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; - - } - dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED; - - /* Reset the Queue pointers */ - OMAP_DMA_CHAIN_QINIT(chain_id); - - /* Errata - put in the old value */ - dma_write(sys_cf, OCP_SYSCONFIG); - - return 0; -} -EXPORT_SYMBOL(omap_stop_dma_chain_transfers); - -/* Get the index of the ongoing DMA in chain */ -/** - * @brief omap_get_dma_chain_index - Get the element and frame index - * of the ongoing DMA in chain - * - * @param chain_id - * @param ei - Element index - * @param fi - Frame index - * - * @return - Success : 0 - * Failure : -EINVAL - */ -int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) -{ - int lch; - int *channels; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - if ((!ei) || (!fi)) - return -EINVAL; - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get the current channel */ - lch = channels[dma_linked_lch[chain_id].q_head]; - - *ei = dma_read(CCEN(lch)); - *fi = dma_read(CCFN(lch)); - - return 0; -} -EXPORT_SYMBOL(omap_get_dma_chain_index); - -/** - * @brief omap_get_dma_chain_dst_pos - Get the destination position of the - * ongoing DMA in chain - * - * @param chain_id - * - * @return - Success : Destination position - * Failure : -EINVAL - */ -int omap_get_dma_chain_dst_pos(int chain_id) -{ - int lch; - int *channels; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get the current channel */ - lch = channels[dma_linked_lch[chain_id].q_head]; - - return dma_read(CDAC(lch)); -} -EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); - -/** - * @brief omap_get_dma_chain_src_pos - Get the source position - * of the ongoing DMA in chain - * @param chain_id - * - * @return - Success : Destination position - * Failure : -EINVAL - */ -int omap_get_dma_chain_src_pos(int chain_id) -{ - int lch; - int *channels; - - /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { - printk(KERN_ERR "Invalid chain id\n"); - return -EINVAL; - } - - /* Check if the chain exists */ - if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { - printk(KERN_ERR "Chain doesn't exists\n"); - return -EINVAL; - } - - channels = dma_linked_lch[chain_id].linked_dmach_q; - - /* Get the current channel */ - lch = channels[dma_linked_lch[chain_id].q_head]; - - return dma_read(CSAC(lch)); -} -EXPORT_SYMBOL(omap_get_dma_chain_src_pos); -#endif /* ifndef CONFIG_ARCH_OMAP1 */ - -/*----------------------------------------------------------------------------*/ - -#ifdef CONFIG_ARCH_OMAP1 - -static int omap1_dma_handle_ch(int ch) -{ - u32 csr; - - if (enable_1510_mode && ch >= 6) { - csr = dma_chan[ch].saved_csr; - dma_chan[ch].saved_csr = 0; - } else - csr = dma_read(CSR(ch)); - if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { - dma_chan[ch + 6].saved_csr = csr >> 7; - csr &= 0x7f; - } - if ((csr & 0x3f) == 0) - return 0; - if (unlikely(dma_chan[ch].dev_id == -1)) { - printk(KERN_WARNING "Spurious interrupt from DMA channel " - "%d (CSR %04x)\n", ch, csr); - return 0; - } - if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) - printk(KERN_WARNING "DMA timeout with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(csr & OMAP_DMA_DROP_IRQ)) - printk(KERN_WARNING "DMA synchronization event drop occurred " - "with device %d\n", dma_chan[ch].dev_id); - if (likely(csr & OMAP_DMA_BLOCK_IRQ)) - dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; - if (likely(dma_chan[ch].callback != NULL)) - dma_chan[ch].callback(ch, csr, dma_chan[ch].data); - - return 1; -} - -static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) -{ - int ch = ((int) dev_id) - 1; - int handled = 0; - - for (;;) { - int handled_now = 0; - - handled_now += omap1_dma_handle_ch(ch); - if (enable_1510_mode && dma_chan[ch + 6].saved_csr) - handled_now += omap1_dma_handle_ch(ch + 6); - if (!handled_now) - break; - handled += handled_now; - } - - return handled ? IRQ_HANDLED : IRQ_NONE; -} - -#else -#define omap1_dma_irq_handler NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2PLUS - -static int omap2_dma_handle_ch(int ch) -{ - u32 status = dma_read(CSR(ch)); - - if (!status) { - if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", - ch); - dma_write(1 << ch, IRQSTATUS_L0); - return 0; - } - if (unlikely(dma_chan[ch].dev_id == -1)) { - if (printk_ratelimit()) - printk(KERN_WARNING "IRQ %04x for non-allocated DMA" - "channel %d\n", status, ch); - return 0; - } - if (unlikely(status & OMAP_DMA_DROP_IRQ)) - printk(KERN_INFO - "DMA synchronization event drop occurred with device " - "%d\n", dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { - printk(KERN_INFO "DMA transaction error with device %d\n", - dma_chan[ch].dev_id); - if (cpu_class_is_omap2()) { - /* - * Errata: sDMA Channel is not disabled - * after a transaction error. So we explicitely - * disable the channel - */ - u32 ccr; - - ccr = dma_read(CCR(ch)); - ccr &= ~OMAP_DMA_CCR_EN; - dma_write(ccr, CCR(ch)); - dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; - } - } - if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) - printk(KERN_INFO "DMA secure error with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) - printk(KERN_INFO "DMA misaligned error with device %d\n", - dma_chan[ch].dev_id); - - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch)); - dma_write(1 << ch, IRQSTATUS_L0); - - /* If the ch is not chained then chain_id will be -1 */ - if (dma_chan[ch].chain_id != -1) { - int chain_id = dma_chan[ch].chain_id; - dma_chan[ch].state = DMA_CH_NOTSTARTED; - if (dma_read(CLNK_CTRL(ch)) & (1 << 15)) - dma_chan[dma_chan[ch].next_linked_ch].state = - DMA_CH_STARTED; - if (dma_linked_lch[chain_id].chain_mode == - OMAP_DMA_DYNAMIC_CHAIN) - disable_lnk(ch); - - if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) - OMAP_DMA_CHAIN_INCQHEAD(chain_id); - - status = dma_read(CSR(ch)); - } - - dma_write(status, CSR(ch)); - - if (likely(dma_chan[ch].callback != NULL)) - dma_chan[ch].callback(ch, status, dma_chan[ch].data); - - return 0; -} - -/* STATUS register count is from 1-32 while our is 0-31 */ -static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) -{ - u32 val, enable_reg; - int i; - - val = dma_read(IRQSTATUS_L0); - if (val == 0) { - if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ\n"); - return IRQ_HANDLED; - } - enable_reg = dma_read(IRQENABLE_L0); - val &= enable_reg; /* Dispatch only relevant interrupts */ - for (i = 0; i < dma_lch_count && val != 0; i++) { - if (val & 1) - omap2_dma_handle_ch(i); - val >>= 1; - } - - return IRQ_HANDLED; -} - -static struct irqaction omap24xx_dma_irq = { - .name = "DMA", - .handler = omap2_dma_irq_handler, - .flags = IRQF_DISABLED -}; - -#else -static struct irqaction omap24xx_dma_irq; -#endif - -/*----------------------------------------------------------------------------*/ - -void omap_dma_global_context_save(void) -{ - omap_dma_global_context.dma_irqenable_l0 = - dma_read(IRQENABLE_L0); - omap_dma_global_context.dma_ocp_sysconfig = - dma_read(OCP_SYSCONFIG); - omap_dma_global_context.dma_gcr = dma_read(GCR); -} - -void omap_dma_global_context_restore(void) -{ - int ch; - - dma_write(omap_dma_global_context.dma_gcr, GCR); - dma_write(omap_dma_global_context.dma_ocp_sysconfig, - OCP_SYSCONFIG); - dma_write(omap_dma_global_context.dma_irqenable_l0, - IRQENABLE_L0); - - /* - * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared - * after secure sram context save and restore. Hence we need to - * manually clear those IRQs to avoid spurious interrupts. This - * affects only secure devices. - */ - if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) - dma_write(0x3 , IRQSTATUS_L0); - - for (ch = 0; ch < dma_chan_count; ch++) - if (dma_chan[ch].dev_id != -1) - omap_clear_dma(ch); -} - -/*----------------------------------------------------------------------------*/ - -static int __init omap_init_dma(void) -{ - unsigned long base; - int ch, r; - - if (cpu_class_is_omap1()) { - base = OMAP1_DMA_BASE; - dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap24xx()) { - base = OMAP24XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap34xx()) { - base = OMAP34XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap44xx()) { - base = OMAP44XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else { - pr_err("DMA init failed for unsupported omap\n"); - return -ENODEV; - } - - omap_dma_base = ioremap(base, SZ_4K); - BUG_ON(!omap_dma_base); - - if (cpu_class_is_omap2() && omap_dma_reserve_channels - && (omap_dma_reserve_channels <= dma_lch_count)) - dma_lch_count = omap_dma_reserve_channels; - - dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, + dma_chan = kzalloc(sizeof(struct omap_dma_lch) * (d->dma_lch_count), GFP_KERNEL); - if (!dma_chan) { - r = -ENOMEM; - goto out_unmap; - } - if (cpu_class_is_omap2()) { - dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * - dma_lch_count, GFP_KERNEL); - if (!dma_linked_lch) { - r = -ENOMEM; - goto out_free; - } + if (!dma_chan) { + ret = -ENOMEM; + goto exit_unmap; } - if (cpu_is_omap15xx()) { + if (d->dma_dev_attr & ENABLE_1510_MODE) { printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); dma_chan_count = 9; - enable_1510_mode = 1; - } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { + } else if (!(d->dma_dev_attr & ENABLE_1510_MODE) && + !(d->dma_dev_attr & DMA_LINKED_LCH)) { + u16 w; printk(KERN_INFO "OMAP DMA hardware version %d\n", - dma_read(HW_ID)); + dma_read(r->hw_id)); printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", - (dma_read(CAPS_0_U) << 16) | - dma_read(CAPS_0_L), - (dma_read(CAPS_1_U) << 16) | - dma_read(CAPS_1_L), - dma_read(CAPS_2), dma_read(CAPS_3), - dma_read(CAPS_4)); - if (!enable_1510_mode) { - u16 w; + (dma_read(r->reg_caps.caps_0u) << 16) | + dma_read(r->reg_caps.caps_0l), + (dma_read(r->reg_caps.caps_1u) << 16) | + dma_read(r->reg_caps.caps_1l), + dma_read(r->reg_caps.caps_2), + dma_read(r->reg_caps.caps_3), + dma_read(r->reg_caps.caps_4)); /* Disable OMAP 3.0/3.1 compatibility mode. */ - w = dma_read(GSCR); + w = dma_read(r->gscr); w |= 1 << 3; - dma_write(w, GSCR); + dma_write(w, r->gscr); dma_chan_count = 16; - } else - dma_chan_count = 9; - } else if (cpu_class_is_omap2()) { - u8 revision = dma_read(REVISION) & 0xff; + } else if (d->dma_dev_attr & DMA_LINKED_LCH) { + u8 revision = dma_read(r->rev) & 0xff; printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", revision >> 4, revision & 0xf); - dma_chan_count = dma_lch_count; + dma_chan_count = d->dma_lch_count; } else { dma_chan_count = 0; - return 0; } - spin_lock_init(&dma_chan_lock); - for (ch = 0; ch < dma_chan_count; ch++) { - omap_clear_dma(ch); - if (cpu_class_is_omap2()) - omap2_disable_irq_lch(ch); + for (irq_count = 0; irq_count < dma_chan_count ; irq_count++) { + omap_clear_dma(irq_count); + if (p->disable_irq_lch) { + unsigned long flags; + spin_lock_irqsave(&dma_chan_lock, flags); + p->disable_irq_lch(irq_count); + spin_unlock_irqrestore(&dma_chan_lock, flags); + } + + dma_chan[irq_count].dev_id = -1; + dma_chan[irq_count].next_lch = -1; - dma_chan[ch].dev_id = -1; - dma_chan[ch].next_lch = -1; + dma_irq = platform_get_irq_byname(pdev, irq_name); - if (ch >= 6 && enable_1510_mode) + if (((irq_count >= 7) && (d->dma_dev_attr & ENABLE_1510_MODE)) + || (d->dma_dev_attr & DMA_LINKED_LCH)) continue; - if (cpu_class_is_omap1()) { - /* - * request_irq() doesn't like dev_id (ie. ch) being - * zero, so we have to kludge around this. - */ - r = request_irq(omap1_dma_irq[ch], - omap1_dma_irq_handler, 0, "DMA", - (void *) (ch + 1)); - if (r != 0) { - int i; - - printk(KERN_ERR "unable to request IRQ %d " - "for DMA (error %d)\n", - omap1_dma_irq[ch], r); - for (i = 0; i < ch; i++) - free_irq(omap1_dma_irq[i], - (void *) (i + 1)); - goto out_free; + if (dma_irq < 0) { + dev_err(&pdev->dev, "%s:unable to get irq\n", __func__); + ret = dma_irq; + goto exit_unmap; + } + + if (p->dma_irq_register) + ret = p->dma_irq_register(dma_irq, irq_count, dma_chan); + + if (ret != 0) { + int irq_rel; + + printk(KERN_ERR "unable to request IRQ %d" + "for DMA (error %d)\n", dma_irq, ret); + for (irq_rel = 0; irq_rel < irq_count; irq_rel++) { + dma_irq = platform_get_irq(pdev, irq_rel); + free_irq(dma_irq, (void *) (irq_rel + 1)); + goto exit_dma_chan; } } } - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) + if ((d->dma_dev_attr & DMA_LINKED_LCH) && + p->dma_irq_register) { + strcpy(irq_name, "dma_0"); + dma_irq = platform_get_irq_byname(pdev, irq_name); + p->dma_irq_register(dma_irq, 0, dma_chan); + } + + if (d->dma_dev_attr & GLOBAL_PRIORITY) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); - if (cpu_class_is_omap2()) { - int irq; - if (cpu_is_omap44xx()) - irq = OMAP44XX_IRQ_SDMA_0; - else - irq = INT_24XX_SDMA_IRQ0; - setup_irq(irq, &omap24xx_dma_irq); - } - - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - /* Enable smartidle idlemodes and autoidle */ - u32 v = dma_read(OCP_SYSCONFIG); - v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | - DMA_SYSCONFIG_SIDLEMODE_MASK | - DMA_SYSCONFIG_AUTOIDLE); - v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | - DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | - DMA_SYSCONFIG_AUTOIDLE); - dma_write(v , OCP_SYSCONFIG); - /* reserve dma channels 0 and 1 in high security devices */ - if (cpu_is_omap34xx() && - (omap_type() != OMAP2_DEVICE_TYPE_GP)) { - printk(KERN_INFO "Reserving DMA channels 0 and 1 for " - "HS ROM code\n"); - dma_chan[0].dev_id = 0; - dma_chan[1].dev_id = 1; - } + /* reserve dma channels 0 and 1 in high security devices */ + if (d->dma_dev_attr & RESERVE_CHANNEL) { + printk(KERN_INFO "Reserving DMA channels 0 and 1 for " + "HS ROM code\n"); + dma_chan[0].dev_id = 0; + dma_chan[1].dev_id = 1; } + dev_info(&pdev->dev, "System DMA registered\n"); return 0; -out_free: +exit_dma_chan: kfree(dma_chan); +exit_unmap: + iounmap(omap_dma_base); +exit_release_region: + release_mem_region(mem->start, resource_size(mem)); + return ret; +} -out_unmap: +static int __devexit omap_system_dma_remove(struct platform_device *pdev) +{ + struct resource *mem; iounmap(omap_dma_base); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(mem->start, resource_size(mem)); + return 0; +} + +static struct platform_driver omap_system_dma_driver = { + .probe = omap_system_dma_probe, + .remove = omap_system_dma_remove, + .driver = { + .name = "dma" + }, +}; + +static int __init omap_system_dma_init(void) +{ + return platform_driver_register(&omap_system_dma_driver); +} - return r; +arch_initcall(omap_system_dma_init); + +static void __exit omap_system_dma_exit(void) +{ + platform_driver_unregister(&omap_system_dma_driver); } -arch_initcall(omap_init_dma); +MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_AUTHOR("Texas Instruments Inc"); /* * Reserve the omap SDMA channels using cmdline bootarg diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index fcc7d6e..ae372cb 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -26,139 +26,91 @@ /* Move omap4 specific defines to dma-44xx.h */ #include "dma-44xx.h" -/* Hardware registers for omap1 */ -#define OMAP1_DMA_BASE (0xfffed800) - -#define OMAP1_DMA_GCR 0x400 -#define OMAP1_DMA_GSCR 0x404 -#define OMAP1_DMA_GRST 0x408 -#define OMAP1_DMA_HW_ID 0x442 -#define OMAP1_DMA_PCH2_ID 0x444 -#define OMAP1_DMA_PCH0_ID 0x446 -#define OMAP1_DMA_PCH1_ID 0x448 -#define OMAP1_DMA_PCHG_ID 0x44a -#define OMAP1_DMA_PCHD_ID 0x44c -#define OMAP1_DMA_CAPS_0_U 0x44e -#define OMAP1_DMA_CAPS_0_L 0x450 -#define OMAP1_DMA_CAPS_1_U 0x452 -#define OMAP1_DMA_CAPS_1_L 0x454 -#define OMAP1_DMA_CAPS_2 0x456 -#define OMAP1_DMA_CAPS_3 0x458 -#define OMAP1_DMA_CAPS_4 0x45a -#define OMAP1_DMA_PCH2_SR 0x460 -#define OMAP1_DMA_PCH0_SR 0x480 -#define OMAP1_DMA_PCH1_SR 0x482 -#define OMAP1_DMA_PCHD_SR 0x4c0 - -/* Hardware registers for omap2 and omap3 */ -#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) -#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) -#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000) - -#define OMAP_DMA4_REVISION 0x00 -#define OMAP_DMA4_GCR 0x78 -#define OMAP_DMA4_IRQSTATUS_L0 0x08 -#define OMAP_DMA4_IRQSTATUS_L1 0x0c -#define OMAP_DMA4_IRQSTATUS_L2 0x10 -#define OMAP_DMA4_IRQSTATUS_L3 0x14 -#define OMAP_DMA4_IRQENABLE_L0 0x18 -#define OMAP_DMA4_IRQENABLE_L1 0x1c -#define OMAP_DMA4_IRQENABLE_L2 0x20 -#define OMAP_DMA4_IRQENABLE_L3 0x24 -#define OMAP_DMA4_SYSSTATUS 0x28 -#define OMAP_DMA4_OCP_SYSCONFIG 0x2c -#define OMAP_DMA4_CAPS_0 0x64 -#define OMAP_DMA4_CAPS_2 0x6c -#define OMAP_DMA4_CAPS_3 0x70 -#define OMAP_DMA4_CAPS_4 0x74 - -#define OMAP1_LOGICAL_DMA_CH_COUNT 17 -#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ - -/* Common channel specific registers for omap1 */ -#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) -#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) -#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) -#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) -#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) -#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) -#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) -#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) -#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) -#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ -#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) -#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) -#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) -#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) -#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) - -/* Common channel specific registers for omap2 */ -#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) -#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) -#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) -#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) -#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) -#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) -#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) -#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) -#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) -#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) -#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) -#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) -#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) -#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) - -/* Channel specific registers only on omap1 */ -#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) -#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) -#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) -#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) -#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) -#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) -#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) -#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ -#define OMAP1_DMA_CCEN(n) 0 -#define OMAP1_DMA_CCFN(n) 0 - -/* Channel specific registers only on omap2 */ -#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) -#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) -#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) -#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) -#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) - -/* Additional registers available on OMAP4 */ -#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0) -#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4) -#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8) - -/* Dummy defines to keep multi-omap compiles happy */ -#define OMAP1_DMA_REVISION 0 -#define OMAP1_DMA_IRQSTATUS_L0 0 -#define OMAP1_DMA_IRQENABLE_L0 0 -#define OMAP1_DMA_OCP_SYSCONFIG 0 -#define OMAP_DMA4_HW_ID 0 -#define OMAP_DMA4_CAPS_0_L 0 -#define OMAP_DMA4_CAPS_0_U 0 -#define OMAP_DMA4_CAPS_1_L 0 -#define OMAP_DMA4_CAPS_1_U 0 -#define OMAP_DMA4_GSCR 0 -#define OMAP_DMA4_CPC(n) 0 - -#define OMAP_DMA4_LCH_CTRL(n) 0 -#define OMAP_DMA4_COLOR_L(n) 0 -#define OMAP_DMA4_COLOR_U(n) 0 -#define OMAP_DMA4_CCR2(n) 0 -#define OMAP1_DMA_CSSA(n) 0 -#define OMAP1_DMA_CDSA(n) 0 -#define OMAP_DMA4_CSSA_L(n) 0 -#define OMAP_DMA4_CSSA_U(n) 0 -#define OMAP_DMA4_CDSA_L(n) 0 -#define OMAP_DMA4_CDSA_U(n) 0 -#define OMAP1_DMA_COLOR(n) 0 - -/*----------------------------------------------------------------------------*/ +#define OMAP1_DMA_TOUT_IRQ (1 << 0) +#define OMAP_DMA_DROP_IRQ (1 << 1) +#define OMAP_DMA_HALF_IRQ (1 << 2) +#define OMAP_DMA_FRAME_IRQ (1 << 3) +#define OMAP_DMA_LAST_IRQ (1 << 4) +#define OMAP_DMA_BLOCK_IRQ (1 << 5) +#define OMAP1_DMA_SYNC_IRQ (1 << 6) +#define OMAP2_DMA_PKT_IRQ (1 << 7) +#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) +#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) +#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) +#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) + +#define OMAP_DMA_CCR_EN (1 << 7) + +#define OMAP_DMA_DATA_TYPE_S8 0x00 +#define OMAP_DMA_DATA_TYPE_S16 0x01 +#define OMAP_DMA_DATA_TYPE_S32 0x02 + +#define OMAP_DMA_SYNC_ELEMENT 0x00 +#define OMAP_DMA_SYNC_FRAME 0x01 +#define OMAP_DMA_SYNC_BLOCK 0x02 +#define OMAP_DMA_SYNC_PACKET 0x03 + +#define OMAP_DMA_SRC_SYNC 0x01 +#define OMAP_DMA_DST_SYNC 0x00 + +#define OMAP_DMA_PORT_EMIFF 0x00 +#define OMAP_DMA_PORT_EMIFS 0x01 +#define OMAP_DMA_PORT_OCP_T1 0x02 +#define OMAP_DMA_PORT_TIPB 0x03 +#define OMAP_DMA_PORT_OCP_T2 0x04 +#define OMAP_DMA_PORT_MPUI 0x05 +#define OMAP_DMA_AMODE_CONSTANT 0x00 +#define OMAP_DMA_AMODE_POST_INC 0x01 +#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 +#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 + +#define DMA_DEFAULT_FIFO_DEPTH 0x10 +#define DMA_DEFAULT_ARB_RATE 0x01 +/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ +#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ +#define DMA_THREAD_RESERVE_ONET (0x01 << 12) +#define DMA_THREAD_RESERVE_TWOT (0x02 << 12) +#define DMA_THREAD_RESERVE_THREET (0x03 << 12) +#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ +#define DMA_THREAD_FIFO_75 (0x01 << 14) +#define DMA_THREAD_FIFO_25 (0x02 << 14) +#define DMA_THREAD_FIFO_50 (0x03 << 14) + +#define DMA_CH_PRIO_HIGH 0x1 +#define DMA_CH_PRIO_LOW 0x0 /* Def */ + +/* Attributes for OMAP DMA Contrllers */ +#define ENABLE_1510_MODE (1 << 0) +#define DMA_LINKED_LCH (1 << 1) +#define GLOBAL_PRIORITY (1 << 2) +#define RESERVE_CHANNEL (1 << 3) +#define SRC_PORT (2 << 3) +#define DST_PORT (2 << 4) +#define IS_CSSA_32 (2 << 5) +#define IS_CDSA_32 (2 << 6) +#define SRC_INDEX (4 << 6) +#define DST_INDEX (4 << 7) +#define IS_BURST_ONLY4 (4 << 8) +#define CLEAR_CSR_ON_READ (4 << 9) +#define IS_WORD_16 (8 << 9) + +/* Errata Definitions */ +#define DMA_CHAINING_ERRATA (1 << 0) +#define DMA_BUFF_DISABLE_ERRATA (1 << 1) +#define OMAP3_3_ERRATUM (1 << 2) +#define DMA_SYSCONFIG_ERRATA (1 << 3) +#define DMA_CH_DISABLE_ERRATA (1 << 4) +#define DMA_IRQ_STATUS_ERRATA (1 << 5) + +#define OMAP_DMA_ACTIVE 0x01 +#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe + +/* + * DMA request lines for omap1 and omap2. + * Should go to respective mach/dma.h files? + * DMA client drivers should fix these macros usage. + */ /* DMA channels for omap1 */ #define OMAP_DMA_NO_DEVICE 0 #define OMAP_DMA_MCSI1_TX 1 @@ -321,85 +273,6 @@ #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ -/*----------------------------------------------------------------------------*/ - -#define OMAP1_DMA_TOUT_IRQ (1 << 0) -#define OMAP_DMA_DROP_IRQ (1 << 1) -#define OMAP_DMA_HALF_IRQ (1 << 2) -#define OMAP_DMA_FRAME_IRQ (1 << 3) -#define OMAP_DMA_LAST_IRQ (1 << 4) -#define OMAP_DMA_BLOCK_IRQ (1 << 5) -#define OMAP1_DMA_SYNC_IRQ (1 << 6) -#define OMAP2_DMA_PKT_IRQ (1 << 7) -#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) -#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) -#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) -#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) - -#define OMAP_DMA_CCR_EN (1 << 7) - -#define OMAP_DMA_DATA_TYPE_S8 0x00 -#define OMAP_DMA_DATA_TYPE_S16 0x01 -#define OMAP_DMA_DATA_TYPE_S32 0x02 - -#define OMAP_DMA_SYNC_ELEMENT 0x00 -#define OMAP_DMA_SYNC_FRAME 0x01 -#define OMAP_DMA_SYNC_BLOCK 0x02 -#define OMAP_DMA_SYNC_PACKET 0x03 - -#define OMAP_DMA_SRC_SYNC 0x01 -#define OMAP_DMA_DST_SYNC 0x00 - -#define OMAP_DMA_PORT_EMIFF 0x00 -#define OMAP_DMA_PORT_EMIFS 0x01 -#define OMAP_DMA_PORT_OCP_T1 0x02 -#define OMAP_DMA_PORT_TIPB 0x03 -#define OMAP_DMA_PORT_OCP_T2 0x04 -#define OMAP_DMA_PORT_MPUI 0x05 - -#define OMAP_DMA_AMODE_CONSTANT 0x00 -#define OMAP_DMA_AMODE_POST_INC 0x01 -#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 -#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 - -#define DMA_DEFAULT_FIFO_DEPTH 0x10 -#define DMA_DEFAULT_ARB_RATE 0x01 -/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ -#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ -#define DMA_THREAD_RESERVE_ONET (0x01 << 12) -#define DMA_THREAD_RESERVE_TWOT (0x02 << 12) -#define DMA_THREAD_RESERVE_THREET (0x03 << 12) -#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ -#define DMA_THREAD_FIFO_75 (0x01 << 14) -#define DMA_THREAD_FIFO_25 (0x02 << 14) -#define DMA_THREAD_FIFO_50 (0x03 << 14) - -/* DMA4_OCP_SYSCONFIG bits */ -#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) -#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) -#define DMA_SYSCONFIG_EMUFREE (1 << 5) -#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) -#define DMA_SYSCONFIG_SOFTRESET (1 << 2) -#define DMA_SYSCONFIG_AUTOIDLE (1 << 0) - -#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) -#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) - -#define DMA_IDLEMODE_SMARTIDLE 0x2 -#define DMA_IDLEMODE_NO_IDLE 0x1 -#define DMA_IDLEMODE_FORCE_IDLE 0x0 - -/* Chaining modes*/ -#ifndef CONFIG_ARCH_OMAP1 -#define OMAP_DMA_STATIC_CHAIN 0x1 -#define OMAP_DMA_DYNAMIC_CHAIN 0x2 -#define OMAP_DMA_CHAIN_ACTIVE 0x1 -#define OMAP_DMA_CHAIN_INACTIVE 0x0 -#endif - -#define DMA_CH_PRIO_HIGH 0x1 -#define DMA_CH_PRIO_LOW 0x0 /* Def */ - enum omap_dma_burst_mode { OMAP_DMA_DATA_BURST_DIS = 0, OMAP_DMA_DATA_BURST_4, @@ -530,9 +403,7 @@ struct omap_dma_channel_params { unsigned char read_prio;/* read priority */ unsigned char write_prio;/* write priority */ -#ifndef CONFIG_ARCH_OMAP1 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ -#endif }; struct omap_dma_lch { @@ -643,29 +514,6 @@ void omap_dma_global_context_restore(void); extern void omap_dma_disable_irq(int lch); -/* Chaining APIs */ -#ifndef CONFIG_ARCH_OMAP1 -extern int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int lch, u16 ch_status, - void *data), - int *chain_id, int no_of_chans, - int chain_mode, - struct omap_dma_channel_params params); -extern int omap_free_dma_chain(int chain_id); -extern int omap_dma_chain_a_transfer(int chain_id, int src_start, - int dest_start, int elem_count, - int frame_count, void *callbk_data); -extern int omap_start_dma_chain_transfers(int chain_id); -extern int omap_stop_dma_chain_transfers(int chain_id); -extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); -extern int omap_get_dma_chain_dst_pos(int chain_id); -extern int omap_get_dma_chain_src_pos(int chain_id); - -extern int omap_modify_dma_chain_params(int chain_id, - struct omap_dma_channel_params params); -extern int omap_dma_chain_status(int chain_id); -#endif - #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP) #include #else From patchwork Thu Jul 8 22:51:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110946 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsHFk011213 for ; Thu, 8 Jul 2010 22:54:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758706Ab0GHWyP (ORCPT ); Thu, 8 Jul 2010 18:54:15 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59494 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758716Ab0GHWyO (ORCPT ); Thu, 8 Jul 2010 18:54:14 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms4ml002422 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:08 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaC022017; Fri, 9 Jul 2010 04:23:58 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 02/10] OMAP2430: DMA: HWMOD: Add hwmod data structures Date: Fri, 9 Jul 2010 04:21:14 +0530 Message-Id: <1278629482-32501-3-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:17 +0000 (UTC) This patch adds OMAP2430 DMA hwmod structures. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 93 +++++++++++++++++++++++++++- 1 files changed, 92 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c0f3311..30998c6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -12,10 +12,12 @@ * XXX these should be marked initdata for multi-OMAP kernels */ #include -#include #include #include +#include +#include + #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" @@ -32,6 +34,7 @@ static struct omap_hwmod omap2430_mpu_hwmod; static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; +static struct omap_hwmod omap2430_dma_system_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -137,12 +140,100 @@ static struct omap_hwmod omap2430_mpu_hwmod = { .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_dma_hwmod_class = { + .name = "dma", + .sysc = &omap2430_dma_sysc, +}; + +/* dma_system */ + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dma_dev_attr = DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT, +}; + +static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { + { .name = "dma_0", .irq = INT_24XX_SDMA_IRQ0 }, + { .name = "dma_1", .irq = INT_24XX_SDMA_IRQ1 }, + { .name = "dma_2", .irq = INT_24XX_SDMA_IRQ2 }, + { .name = "dma_3", .irq = INT_24XX_SDMA_IRQ3 }, +}; + +static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { + &omap2430_dma_system__l3, +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap2430_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { + &omap2430_l4_core__dma_system, +}; + +static struct omap_hwmod omap2430_dma_system_hwmod = { + .name = "dma", + .class = &omap2430_dma_hwmod_class, + .mpu_irqs = omap2430_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), + .main_clk = "l3_div_ck", + .prcm = { + .omap2 = { + /*.clkctrl_reg = NULL, */ + }, + }, + .slaves = omap2430_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), + .masters = omap2430_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, + &omap2430_dma_system_hwmod, NULL, }; From patchwork Thu Jul 8 22:51:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110947 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsJQS011226 for ; Thu, 8 Jul 2010 22:54:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932069Ab0GHWyR (ORCPT ); Thu, 8 Jul 2010 18:54:17 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:37477 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758720Ab0GHWyQ (ORCPT ); Thu, 8 Jul 2010 18:54:16 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms59P026349 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:14 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaG022017; Fri, 9 Jul 2010 04:24:00 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 06/10] OMAP2/3/4: DMA: HWMOD: Device registration Date: Fri, 9 Jul 2010 04:21:18 +0530 Message-Id: <1278629482-32501-7-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:19 +0000 (UTC) This patch converts omap2/3/4 dma driver into platform devices through using omap hwmod, omap device and runtime pm frameworks. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap2/dma.c | 200 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/include/mach/dma.h | 76 ++++++++++++ 2 files changed, 276 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-omap2/dma.c create mode 100644 arch/arm/mach-omap2/include/mach/dma.h diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c new file mode 100644 index 0000000..548321b --- /dev/null +++ b/arch/arm/mach-omap2/dma.c @@ -0,0 +1,200 @@ +/* + * dma.c - OMAP2 specific DMA code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Author: + * Manjunatha GK + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +struct omap_device_pm_latency omap2_dma_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +struct omap_dma_reg_offset dma_reg_offset[] = { + { + .lch_base = OMAP_DMA4_CH_BASE, + .gcr = OMAP_DMA4_GCR, + .ocp_sysconfig = OMAP_DMA4_OCP_SYSCONFIG, + .rev = OMAP_DMA4_REVISION, + .common_ch = { + .csdp = OMAP_DMA4_CSDP, + .ccr = OMAP_DMA4_CCR, + .cicr = OMAP_DMA4_CICR, + .csr = OMAP_DMA4_CSR, + .csfi = OMAP_DMA4_CSFI, + .csei = OMAP_DMA4_CSEI, + .cdac = OMAP_DMA4_CDAC, + .cdei = OMAP_DMA4_CDEI, + .cdfi = OMAP_DMA4_CDFI, + .clnk_ctrl = OMAP_DMA4_CLNK_CTRL, + .cen = OMAP_DMA4_CEN, + .cfn = OMAP_DMA4_CFN, + }, + .ch_specific = { + .cssa = OMAP_DMA4_CSSA, + .cdsa = OMAP_DMA4_CDSA, + }, + .irqreg = { + .irq_status_l0 = OMAP_DMA4_IRQSTATUS_L0, + .irq_enable_l0 = OMAP_DMA4_IRQENABLE_L0, + }, + + .reg_caps = { + .caps_0 = OMAP_DMA4_CAPS_0, + }, + }, +}; +struct omap_dma_reg_offset *r = (struct omap_dma_reg_offset *)&dma_reg_offset; + +struct omap_dma_dev_attr *d; + +static struct omap_system_dma_plat_info *omap2_pdata; +static void __iomem *dma_base; +static struct dma_link_info *dma_linked_lch; +static u32 dma_chan_count; + +/* One time initializations */ +static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *user) +{ + struct omap_device *od; + struct omap_system_dma_plat_info *pdata; + struct resource *mem; + char *name = "dma"; + + pdata = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); + if (!pdata) { + pr_err("%s: Unable to allocate pdata for %s:%s\n", + __func__, name, oh->name); + return -ENOMEM; + } + + + pdata->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; + + pdata->dma_reg_offset = r; + + pdata->disable_irq_lch = disable_irq_lch; + pdata->enable_irq_lch = enable_irq_lch; + pdata->dma_handle_ch = omap2_dma_handle_ch; + pdata->clear_lch_regs = NULL; + pdata->dma_running = dma_running; + pdata->set_prio_lch = set_prio_lch; + pdata->dma_irq_register = dma_irq_register; + pdata->enable_lnk = omap_enable_lnk; + pdata->disable_lnk = omap_disable_lnk; + pdata->enable_channel_irq = omap_enable_channel_irq; + pdata->disable_channel_irq = omap_disable_channel_irq; + pdata->clear_ccr_csr = NULL; + pdata->sync_device_set = NULL; + + /* Handling Errata's for all OMAP2PLUS processors */ + pdata->errata = 0; + + if (cpu_is_omap242x() || + (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) + pdata->errata = DMA_CHAINING_ERRATA; + + /* + * Errata: On ES2.0 BUFFERING disable must be set. + * This will always fail on ES1.0 + */ + if (cpu_is_omap24xx()) + pdata->errata |= DMA_BUFF_DISABLE_ERRATA; + + /* + * Errata: OMAP2: sDMA Channel is not disabled + * after a transaction error. So we explicitely + * disable the channel + */ + if (cpu_class_is_omap2()) + pdata->errata |= DMA_CH_DISABLE_ERRATA; + + /* Errata: OMAP3 : + * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared + * after secure sram context save and restore. Hence we need to + * manually clear those IRQs to avoid spurious interrupts. This + * affects only secure devices. + */ + if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + pdata->errata |= DMA_IRQ_STATUS_ERRATA; + + /* Errata3.3: Applicable for all omap2 plus */ + pdata->errata |= OMAP3_3_ERRATUM; + + od = omap_device_build(name, 0, oh, pdata, sizeof(*pdata), + omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); + + if (IS_ERR(od)) { + pr_err("%s: Cant build omap_device for %s:%s.\n", + __func__, name, oh->name); + kfree(pdata); + return 0; + } + + mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__); + return -EINVAL; + } + + dma_base = ioremap(mem->start, resource_size(mem)); + if (!dma_base) { + dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__); + return -ENOMEM; + } + + /* Get DMA device attributes from hwmod data base */ + d = (struct omap_dma_dev_attr *)oh->dev_attr; + + dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * + d->dma_lch_count, GFP_KERNEL); + if (!dma_linked_lch) { + int ret; + ret = -ENOMEM; + kfree(pdata); + return ret; + } + omap2_pdata = pdata; + + pm_runtime_enable(&(od->pdev.dev)); + return 0; +} + +static int __init omap2_system_dma_init(void) +{ + int ret; + + ret = omap_hwmod_for_each_by_class("dma", + omap2_system_dma_init_dev, NULL); + + return ret; +} +arch_initcall(omap2_system_dma_init); diff --git a/arch/arm/mach-omap2/include/mach/dma.h b/arch/arm/mach-omap2/include/mach/dma.h new file mode 100644 index 0000000..a8d8fee --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/dma.h @@ -0,0 +1,76 @@ +/* + * arch/arm/mach-omap2/include/mach/dma.h + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Author: Manjunatha GK + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP2_DMA_H +#define __ASM_ARCH_OMAP2_DMA_H +#include + +/* OMAP2 Plus register offset's */ +#define OMAP_DMA4_REVISION 0x00 +#define OMAP_DMA4_GCR 0x78 +#define OMAP_DMA4_IRQSTATUS_L0 0x08 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c +#define OMAP_DMA4_IRQSTATUS_L2 0x10 +#define OMAP_DMA4_IRQSTATUS_L3 0x14 +#define OMAP_DMA4_IRQENABLE_L0 0x18 +#define OMAP_DMA4_IRQENABLE_L1 0x1c +#define OMAP_DMA4_IRQENABLE_L2 0x20 +#define OMAP_DMA4_IRQENABLE_L3 0x24 +#define OMAP_DMA4_SYSSTATUS 0x28 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c +#define OMAP_DMA4_CAPS_0 0x64 +#define OMAP_DMA4_CAPS_2 0x6c +#define OMAP_DMA4_CAPS_3 0x70 +#define OMAP_DMA4_CAPS_4 0x74 + +/* Should be part of hwmod data base ? */ +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ + +/* Common channel specific registers for omap2 */ +#define OMAP_DMA4_CH_BASE (0x60) + +#define OMAP_DMA4_CCR (0x80) +#define OMAP_DMA4_CLNK_CTRL (0x84) +#define OMAP_DMA4_CICR (0x88) +#define OMAP_DMA4_CSR (0x8c) +#define OMAP_DMA4_CSDP (0x90) +#define OMAP_DMA4_CEN (0x94) +#define OMAP_DMA4_CFN (0x98) +#define OMAP_DMA4_CSEI (0xa4) +#define OMAP_DMA4_CSFI (0xa8) +#define OMAP_DMA4_CDEI (0xac) +#define OMAP_DMA4_CDFI (0xb0) +#define OMAP_DMA4_CSAC (0xb4) +#define OMAP_DMA4_CDAC (0xb8) + +/* Channel specific registers only on omap2 */ +#define OMAP_DMA4_CSSA (0x9c) +#define OMAP_DMA4_CDSA (0xa0) +#define OMAP_DMA4_CCEN (0xbc) +#define OMAP_DMA4_CCFN (0xc0) +#define OMAP_DMA4_COLOR (0xc4) + +/* Additional registers available on OMAP4 */ +#define OMAP_DMA4_CDP (0xd0) +#define OMAP_DMA4_CNDP (0xd4) +#define OMAP_DMA4_CCDN (0xd8) + +#endif /* __ASM_ARCH_OMAP2_DMA_H */ From patchwork Sun May 16 15:45:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99972 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkQEC025271 for ; Sun, 16 May 2010 15:46:27 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753456Ab0EPPq0 (ORCPT ); Sun, 16 May 2010 11:46:26 -0400 Received: from fg-out-1718.google.com ([72.14.220.157]:34390 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753444Ab0EPPqZ (ORCPT ); Sun, 16 May 2010 11:46:25 -0400 Received: by fg-out-1718.google.com with SMTP id 22so178499fge.1 for ; Sun, 16 May 2010 08:46:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=nkdLN/0SZ5ECDDaMjMfIA6wXXgWqsVAMXW5ZTb8rOyE=; b=q9kSv/26YbnPUWiJTEQNLhdcvXw/GaZ/ZbegdC5gk2g2KOUoV6Qbogg/Iz8h+quXO+ /KlxQn30j0jnEbR+rjlLGWP9J+sjGNH05hOvnnkvb7PMNQH6KH3DFLSNj8AF3y/UZmo6 f1osDLcXTLf+eKf+hHbNye/KjMmN0c4w6wBTI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=s7yL9mgD7aUytskHcf5nM5jy5qsZVQLEfbFYX22zJIcTtCOoiZqZUQbLRGMa8KImp1 77O0vWKPZ0sMNjcoBjqaHikzD7+FVSeaQvvd3w9i5iQBRIDw8CvcxHV6SUT7TNVeXh8D mmSVQJ7egcB8aVK0KqfZJzxD6///9ZAw8txLw= Received: by 10.87.35.9 with SMTP id n9mr6779747fgj.45.1274024784504; Sun, 16 May 2010 08:46:24 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id 3sm3767472fge.10.2010.05.16.08.46.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:46:24 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 08/14] dspbridge: deh: refactor in mmu_fault_print_stack() Date: Sun, 16 May 2010 18:45:59 +0300 Message-Id: <1274024765-21076-9-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:27 +0000 (UTC) diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index f661aaf..1d1b87b 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -189,9 +189,8 @@ static void wait_for_timer(void) omap_dm_timer_disable(timer); } -void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) +static void mmu_fault_print_stack(struct bridge_dev_context *dev_context) { - struct bridge_dev_context *dev_context; struct cfg_hostres *resources; struct hw_mmu_map_attrs_t map_attrs = { .endianism = HW_LITTLE_ENDIAN, @@ -200,12 +199,41 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) }; void *dummy_va_addr; + resources = dev_context->resources; + dummy_va_addr = (void*)__get_free_page(GFP_ATOMIC); + + /* + * Before acking the MMU fault, let's make sure MMU can only + * access entry #0. Then add a new entry so that the DSP OS + * can continue in order to dump the stack. + */ + hw_mmu_twl_disable(resources->dw_dmmu_base); + hw_mmu_tlb_flush_all(resources->dw_dmmu_base); + + hw_mmu_tlb_add(resources->dw_dmmu_base, + virt_to_phys(dummy_va_addr), fault_addr, + HW_PAGE_SIZE4KB, 1, + &map_attrs, HW_SET, HW_SET); + + wait_for_timer(); + /* Clear MMU interrupt */ + hw_mmu_event_ack(resources->dw_dmmu_base, + HW_MMU_TRANSLATION_FAULT); + dump_dsp_stack(dev_context); + + hw_mmu_disable(resources->dw_dmmu_base); + free_page((unsigned long)dummy_va_addr); +} + +void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) +{ + struct bridge_dev_context *dev_context; + if (!deh_mgr) return; dev_info(bridge, "%s: device exception\n", __func__); dev_context = deh_mgr->hbridge_context; - resources = dev_context->resources; switch (ulEventMask) { case DSP_SYSERROR: @@ -230,32 +258,10 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) (unsigned int) deh_mgr->err_info.dw_val1, (unsigned int) deh_mgr->err_info.dw_val2, (unsigned int) fault_addr); - dummy_va_addr = (void*)__get_free_page(GFP_ATOMIC); print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); - - /* - * Before acking the MMU fault, let's make sure MMU can only - * access entry #0. Then add a new entry so that the DSP OS - * can continue in order to dump the stack. - */ - hw_mmu_twl_disable(resources->dw_dmmu_base); - hw_mmu_tlb_flush_all(resources->dw_dmmu_base); - - hw_mmu_tlb_add(resources->dw_dmmu_base, - virt_to_phys(dummy_va_addr), fault_addr, - HW_PAGE_SIZE4KB, 1, - &map_attrs, HW_SET, HW_SET); - - wait_for_timer(); - /* Clear MMU interrupt */ - hw_mmu_event_ack(resources->dw_dmmu_base, - HW_MMU_TRANSLATION_FAULT); - dump_dsp_stack(dev_context); - - hw_mmu_disable(resources->dw_dmmu_base); - free_page((unsigned long)dummy_va_addr); + mmu_fault_print_stack(dev_context); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR case DSP_PWRERROR: From patchwork Thu Jul 8 22:51:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110943 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68Ms93i011157 for ; Thu, 8 Jul 2010 22:54:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758707Ab0GHWyH (ORCPT ); Thu, 8 Jul 2010 18:54:07 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:39640 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758670Ab0GHWyF (ORCPT ); Thu, 8 Jul 2010 18:54:05 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms0cR001185 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:02 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaB022017; Fri, 9 Jul 2010 04:23:58 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 01/10] OMAP2420: DMA: HWMOD: Add hwmod data structures Date: Fri, 9 Jul 2010 04:21:13 +0530 Message-Id: <1278629482-32501-2-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:10 +0000 (UTC) This patch adds OMAP2420 DMA hwmod structures. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 95 +++++++++++++++++++++++++++- 1 files changed, 93 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 8c90b27..294d5cc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -16,6 +16,9 @@ #include #include +#include +#include + #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" @@ -32,6 +35,7 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_dma_system_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -136,11 +140,100 @@ static struct omap_hwmod omap2420_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_dma_hwmod_class = { + .name = "dma", + .sysc = &omap2420_dma_sysc, +}; + +/* system dma */ + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dma_dev_attr = DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT, +}; + +static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { + { .name = "dma_0", .irq = INT_24XX_SDMA_IRQ0 }, + { .name = "dma_1", .irq = INT_24XX_SDMA_IRQ1 }, + { .name = "dma_2", .irq = INT_24XX_SDMA_IRQ2 }, + { .name = "dma_3", .irq = INT_24XX_SDMA_IRQ3 }, +}; + +static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { + .master = &omap2420_dma_system_hwmod, + .slave = &omap2420_l3_main_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { + &omap2420_dma_system__l3, +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap2420_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { + &omap2420_l4_core__dma_system, +}; + +static struct omap_hwmod omap2420_dma_system_hwmod = { + .name = "dma", + .class = &omap2420_dma_hwmod_class, + .mpu_irqs = omap2420_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs), + .main_clk = "l3_div_ck", + .prcm = { + .omap2 = { + /* .clkctrl_reg = NULL, */ + }, + }, + .slaves = omap2420_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), + .masters = omap2420_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, + &omap2420_dma_system_hwmod, NULL, }; @@ -148,5 +241,3 @@ int __init omap2420_hwmod_init(void) { return omap_hwmod_init(omap2420_hwmods); } - - From patchwork Sun May 16 15:46:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99973 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFkQED025271 for ; Sun, 16 May 2010 15:46:28 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753540Ab0EPPq2 (ORCPT ); Sun, 16 May 2010 11:46:28 -0400 Received: from fg-out-1718.google.com ([72.14.220.159]:5081 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753444Ab0EPPq1 (ORCPT ); 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Sun, 16 May 2010 08:46:26 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 09/14] dspbridge: deh: remove get_info Date: Sun, 16 May 2010 18:46:00 +0300 Message-Id: <1274024765-21076-10-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> References: <1274024765-21076-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:46:28 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/dspdefs.h b/arch/arm/plat-omap/include/dspbridge/dspdefs.h index 3dfe406..a5d410f 100644 --- a/arch/arm/plat-omap/include/dspbridge/dspdefs.h +++ b/arch/arm/plat-omap/include/dspbridge/dspdefs.h @@ -782,24 +782,6 @@ typedef dsp_status(*fxn_deh_registernotify) u32 event_mask, u32 notify_type, struct dsp_notification *hnotification); /* - * ======== bridge_deh_get_info ======== - * Purpose: - * Get DSP exception info. - * Parameters: - * phDehMgr: Location to store DEH manager on output. - * pErrInfo: Ptr to error info structure. - * Returns: - * DSP_SOK: Success. - * -EPERM: Creation failed. - * Requires: - * phDehMgr != NULL; - * pErrorInfo != NULL; - * Ensures: - */ -typedef dsp_status(*fxn_deh_getinfo) (struct deh_mgr *phDehMgr, - struct dsp_errorinfo *pErrInfo); - -/* * ======== bridge_io_create ======== * Purpose: * Create an object that manages I/O between CHNL and msg_ctrl. @@ -1089,7 +1071,6 @@ struct bridge_drv_interface { fxn_deh_notify pfn_deh_notify; /* Notify of DSP error */ /* register for deh notif. */ fxn_deh_registernotify pfn_deh_register_notify; - fxn_deh_getinfo pfn_deh_get_info; /* register for deh notif. */ fxn_io_create pfn_io_create; /* Create IO manager */ fxn_io_destroy pfn_io_destroy; /* Destroy IO manager */ fxn_io_onloaded pfn_io_on_loaded; /* Notify of program loaded */ diff --git a/arch/arm/plat-omap/include/dspbridge/dspdeh.h b/arch/arm/plat-omap/include/dspbridge/dspdeh.h index e263184..4c4d577 100644 --- a/arch/arm/plat-omap/include/dspbridge/dspdeh.h +++ b/arch/arm/plat-omap/include/dspbridge/dspdeh.h @@ -32,9 +32,6 @@ extern dsp_status bridge_deh_create(struct deh_mgr **ret_deh_mgr, extern dsp_status bridge_deh_destroy(struct deh_mgr *deh_mgr); -extern dsp_status bridge_deh_get_info(struct deh_mgr *deh_mgr, - struct dsp_errorinfo *pErrInfo); - extern dsp_status bridge_deh_register_notify(struct deh_mgr *deh_mgr, u32 event_mask, u32 notify_type, diff --git a/drivers/dsp/bridge/core/tiomap3430.c b/drivers/dsp/bridge/core/tiomap3430.c index d00eaaa..99bf966 100644 --- a/drivers/dsp/bridge/core/tiomap3430.c +++ b/drivers/dsp/bridge/core/tiomap3430.c @@ -197,7 +197,6 @@ static struct bridge_drv_interface drv_interface_fxns = { bridge_deh_destroy, bridge_deh_notify, bridge_deh_register_notify, - bridge_deh_get_info, /* The following IO functions are provided by chnl_io.lib: */ bridge_io_create, bridge_io_destroy, diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 1d1b87b..2388780 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -306,18 +306,3 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) */ dsp_wdt_enable(false); } - -dsp_status bridge_deh_get_info(struct deh_mgr *deh_mgr, - struct dsp_errorinfo *pErrInfo) -{ - if (!deh_mgr) - return -EFAULT; - - /* Copy DEH error info structure to PROC error info structure. */ - pErrInfo->dw_err_mask = deh_mgr->err_info.dw_err_mask; - pErrInfo->dw_val1 = deh_mgr->err_info.dw_val1; - pErrInfo->dw_val2 = deh_mgr->err_info.dw_val2; - pErrInfo->dw_val3 = deh_mgr->err_info.dw_val3; - - return 0; -} diff --git a/drivers/dsp/bridge/pmgr/dev.c b/drivers/dsp/bridge/pmgr/dev.c index c85a4fa..b1c8d8b 100644 --- a/drivers/dsp/bridge/pmgr/dev.c +++ b/drivers/dsp/bridge/pmgr/dev.c @@ -1121,7 +1121,6 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, STORE_FXN(fxn_deh_destroy, pfn_deh_destroy); STORE_FXN(fxn_deh_notify, pfn_deh_notify); STORE_FXN(fxn_deh_registernotify, pfn_deh_register_notify); - STORE_FXN(fxn_deh_getinfo, pfn_deh_get_info); STORE_FXN(fxn_io_create, pfn_io_create); STORE_FXN(fxn_io_destroy, pfn_io_destroy); STORE_FXN(fxn_io_onloaded, pfn_io_on_loaded); @@ -1162,7 +1161,6 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, DBC_ENSURE(intf_fxns->pfn_deh_destroy != NULL); DBC_ENSURE(intf_fxns->pfn_deh_notify != NULL); DBC_ENSURE(intf_fxns->pfn_deh_register_notify != NULL); - DBC_ENSURE(intf_fxns->pfn_deh_get_info != NULL); DBC_ENSURE(intf_fxns->pfn_io_create != NULL); DBC_ENSURE(intf_fxns->pfn_io_destroy != NULL); DBC_ENSURE(intf_fxns->pfn_io_on_loaded != NULL); diff --git a/drivers/dsp/bridge/rmgr/proc.c b/drivers/dsp/bridge/rmgr/proc.c index f9efe6a..f86958a 100644 --- a/drivers/dsp/bridge/rmgr/proc.c +++ b/drivers/dsp/bridge/rmgr/proc.c @@ -706,7 +706,6 @@ dsp_status proc_get_state(void *hprocessor, dsp_status status = DSP_SOK; struct proc_object *p_proc_object = (struct proc_object *)hprocessor; int brd_status; - struct deh_mgr *hdeh_mgr; DBC_REQUIRE(refs > 0); DBC_REQUIRE(proc_state_obj != NULL); @@ -739,11 +738,6 @@ dsp_status proc_get_state(void *hprocessor, break; } } - /* Next, retrieve error information, if any */ - status = dev_get_deh_mgr(p_proc_object->hdev_obj, &hdeh_mgr); - if (DSP_SUCCEEDED(status) && hdeh_mgr) - status = (*p_proc_object->intf_fxns->pfn_deh_get_info) - (hdeh_mgr, &(proc_state_obj->err_info)); } else { status = -EFAULT; } From patchwork Thu Jul 8 22:51:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 110948 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68MsJQT011226 for ; Thu, 8 Jul 2010 22:54:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932089Ab0GHWyS (ORCPT ); Thu, 8 Jul 2010 18:54:18 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:37476 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758716Ab0GHWyP (ORCPT ); Thu, 8 Jul 2010 18:54:15 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68Ms6oc026351 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 17:54:12 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68MrtaI022017; Fri, 9 Jul 2010 04:24:00 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Manjunatha GK , "Basak, Partha" , Benoit Cousson , Kevin Hilman , Paul Walmsley , Santosh Shilimkar , Rajendra Nayak Subject: [RFC PATCH 08/10] OMAP: DMA: Move IRQ handlers to mach-omap Date: Fri, 9 Jul 2010 04:21:20 +0530 Message-Id: <1278629482-32501-9-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1278629482-32501-1-git-send-email-manjugk@ti.com> References: <1278629482-32501-1-git-send-email-manjugk@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 22:54:19 +0000 (UTC) The DMA IRQ handling is completely differnet between omap1 and omap2 plus processors hence the IRQ handlers are moved to respective dma.c in mach-omap directories. Signed-off-by: Manjunatha GK Signed-off-by: Basak, Partha Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Rajendra Nayak --- arch/arm/mach-omap1/dma.c | 71 +++++++++++++++++++++++++++++ arch/arm/mach-omap2/dma.c | 111 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 57be4f5..fb5bf0d 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -175,6 +175,77 @@ static struct omap_dma_lch *omap1_dma_chan; static void __iomem *dma_base; static int enable_1510_mode; +static int omap1_dma_handle_ch(int ch) +{ + u32 csr; + u32 reg, ch_reg_base; + + ch_reg_base = r->lch_base * ch; + + if (enable_1510_mode && ch >= 6) { + csr = omap1_dma_chan[ch].saved_csr; + omap1_dma_chan[ch].saved_csr = 0; + } else { + reg = ch_reg_base + r->common_ch.csr; + csr = omap1_dma_read(reg); + } + if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { + omap1_dma_chan[ch + 6].saved_csr = csr >> 7; + csr &= 0x7f; + } + if ((csr & 0x3f) == 0) + return 0; + if (unlikely(omap1_dma_chan[ch].dev_id == -1)) { + printk(KERN_WARNING "Spurious interrupt from DMA channel " + "%d (CSR %04x)\n", ch, csr); + return 0; + } + if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) + printk(KERN_WARNING "DMA timeout with device %d\n", + omap1_dma_chan[ch].dev_id); + if (unlikely(csr & OMAP_DMA_DROP_IRQ)) + printk(KERN_WARNING "DMA synchronization event drop occurred " + "with device %d\n", omap1_dma_chan[ch].dev_id); + if (likely(csr & OMAP_DMA_BLOCK_IRQ)) + omap1_dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; + + if (likely(omap1_dma_chan[ch].callback != NULL)) + omap1_dma_chan[ch].callback(ch, csr, omap1_dma_chan[ch].data); + + return 1; +} + +static irqreturn_t omap_dma_irq_handler(int irq, void *dev_id) +{ + int ch = ((int) dev_id) - 1; + int handled = 0; + + for (;;) { + int handled_now = 0; + + handled_now += omap1_dma_handle_ch(ch); + + if (enable_1510_mode && + omap1_dma_chan[ch + 6].saved_csr) + handled_now += omap1_dma_handle_ch(ch + 6); + + if (!handled_now) + break; + handled += handled_now; + } + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static int dma_irq_register(int dma_irq, int irq_count, + void __iomem *omap_dma_base, struct omap_dma_lch *dma_chan) +{ + int ret = request_irq(dma_irq, omap_dma_irq_handler, 0, "DMA", + (void *) (irq_count+1)); + dma_base = omap_dma_base; + omap1_dma_chan = dma_chan; + return ret; +} + static int __init omap1_system_dma_init(void) { struct platform_device *pdev; diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index f5fe0f5..42a96cf 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -134,6 +134,117 @@ static void __iomem *dma_base; static struct dma_link_info *dma_linked_lch; static u32 dma_chan_count; +static int omap2_dma_handle_ch(int ch) +{ + u32 reg, ch_reg_base, status; + + ch_reg_base = (r->lch_base * ch); + reg = ch_reg_base + r->common_ch.csr; + status = omap2_dma_read(reg); + + if (!status) { + if (printk_ratelimit()) + printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", + ch); + omap2_dma_write(1 << ch, r->irqreg.irq_status_l0); + return 0; + } + if (unlikely(dma_chan[ch].dev_id == -1)) { + if (printk_ratelimit()) + printk(KERN_WARNING "IRQ %04x for non-allocated DMA" + "channel %d\n", status, ch); + return 0; + } + if (unlikely(status & OMAP_DMA_DROP_IRQ)) + printk(KERN_INFO + "DMA synchronization event drop occurred with device " + "%d\n", dma_chan[ch].dev_id); + if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { + printk(KERN_INFO "DMA transaction error with device %d\n", + dma_chan[ch].dev_id); + + if (omap2_pdata->errata & DMA_CH_DISABLE_ERRATA) { + u32 ccr; + + reg = ch_reg_base + r->common_ch.ccr; + ccr = omap2_dma_read(reg); + ccr &= ~OMAP_DMA_CCR_EN; + omap2_dma_write(ccr, reg); + dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; + } + } + if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) + printk(KERN_INFO "DMA secure error with device %d\n", + dma_chan[ch].dev_id); + if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) + printk(KERN_INFO "DMA misaligned error with device %d\n", + dma_chan[ch].dev_id); + + reg = ch_reg_base + r->common_ch.csr; + omap2_dma_write(OMAP2_DMA_CSR_CLEAR_MASK, reg); + omap2_dma_write(1 << ch, r->irqreg.irq_status_l0); + + /* If the ch is not chained then chain_id will be -1 */ + if (dma_chan[ch].chain_id != -1) { + int chain_id = dma_chan[ch].chain_id; + dma_chan[ch].state = DMA_CH_NOTSTARTED; + reg = ch_reg_base + r->common_ch.clnk_ctrl; + if (omap2_dma_read(reg) & (1 << 15)) + dma_chan[dma_chan[ch].next_linked_ch].state = + DMA_CH_STARTED; + if (dma_linked_lch[chain_id].chain_mode == + OMAP_DMA_DYNAMIC_CHAIN) + omap_disable_lnk(ch); + + if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) + OMAP_DMA_CHAIN_INCQHEAD(chain_id); + + status = omap2_dma_read(reg); + } + + omap2_dma_write(status, reg); + + if (likely(dma_chan[ch].callback != NULL)) + dma_chan[ch].callback(ch, status, dma_chan[ch].data); + + return 0; +} + +static irqreturn_t omap_dma_irq_handler(int irq, void *dev_id) +{ + u32 val, enable_reg, i; + + val = omap2_dma_read(r->irqreg.irq_status_l0); + if (val == 0) { + if (printk_ratelimit()) + printk(KERN_WARNING "Spurious DMA IRQ\n"); + return IRQ_HANDLED; + } + enable_reg = omap2_dma_read(r->irqreg.irq_enable_l0); + val &= enable_reg; /* Dispatch only relevant interrupts */ + for (i = 0; i < d->dma_lch_count && val != 0; i++) { + if (val & 1) + omap2_dma_handle_ch(i); + val >>= 1; + } + return IRQ_HANDLED; +} + +static struct irqaction omap24xx_dma_irq = { + .name = "DMA", + .handler = omap_dma_irq_handler, + .flags = IRQF_DISABLED, +}; + +static int dma_irq_register(int dma_irq, int irq_count, + struct omap_dma_lch *omap2_dma_chan) +{ + int ret; + ret = setup_irq(dma_irq, &omap24xx_dma_irq); + dma_chan = omap2_dma_chan; + return ret; +} + /* Create chain of DMA channesls */ static void create_dma_lch_chain(int lch_head, int lch_queue) { From patchwork Mon Jul 12 10:43:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Grinberg X-Patchwork-Id: 111410 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CAi1eU027074 for ; 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Mon, 12 Jul 2010 13:43:54 +0300 (IDT) Received: by grinberg-linux (sSMTP sendmail emulation); Mon, 12 Jul 2010 13:43:51 +0300 From: Igor Grinberg To: Tony Lindgren Cc: Tomi Valkeinen , linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, Igor Grinberg , Mike Rapoport Subject: [PATCH] [ARM] omap/board-cm-t35: fix visual artefacts Date: Mon, 12 Jul 2010 13:43:49 +0300 Message-Id: <1278931429-20018-1-git-send-email-grinberg@compulab.co.il> X-Mailer: git-send-email 1.7.1 X-ACL-Warn: { X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - compulab.site5.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - compulab.co.il X-Source: X-Source-Args: X-Source-Dir: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 10:44:02 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index e679a2c..015ebf8 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -349,6 +349,8 @@ static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) return -EINVAL; } + dssdev->panel.config |= OMAP_DSS_LCD_IPC | OMAP_DSS_LCD_ONOFF; + gpio_set_value(dvi_en_gpio, 0); dvi_enabled = 1; From patchwork Tue May 4 16:01:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kishore kadiyala X-Patchwork-Id: 96820 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o44G2GH5014327 for ; Tue, 4 May 2010 16:02:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932436Ab0EDQBw (ORCPT ); Tue, 4 May 2010 12:01:52 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:53354 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932084Ab0EDQBu (ORCPT ); Tue, 4 May 2010 12:01:50 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o44G1ela022393 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 4 May 2010 11:01:40 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o44G1Yl9011437; Tue, 4 May 2010 11:01:35 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099945); by dbdmail.itg.ti.com with HTTP; Tue, 4 May 2010 21:31:37 +0530 (IST) Message-ID: <35156.10.24.255.17.1272988897.squirrel@dbdmail.itg.ti.com> Date: Tue, 4 May 2010 21:31:37 +0530 (IST) Subject: [PATCH v2 3/5] OMAP4-HSMMC: Adding MMC-TWL regulator changes From: "kishore kadiyala" To: linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org Cc: tony@atomide.com, madhu.cr@ti.com, jarkko.lavinen@nokia.com, rmk@arm.linux.org.uk, paul@pwsan.com User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 04 May 2010 16:02:22 +0000 (UTC) diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index f5ca16c..a73f011 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ static u16 control_pbias_offset; static u16 control_devconf1_offset; +static u16 control_mmc1; #define HSMMC_NAME_LEN 9 @@ -43,7 +45,7 @@ static int hsmmc_get_context_loss(struct device *dev) #define hsmmc_get_context_loss NULL #endif -static void hsmmc1_before_set_reg(struct device *dev, int slot, +static void omap_hsmmc1_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg, prog_io; @@ -96,7 +98,7 @@ static void hsmmc1_before_set_reg(struct device *dev, int slot, } } -static void hsmmc1_after_set_reg(struct device *dev, int slot, +static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; @@ -120,6 +122,61 @@ static void hsmmc1_after_set_reg(struct device *dev, int slot, } } +static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, + int power_on, int vdd) +{ + u32 reg; + + /* + * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the + * card with Vcc regulator (from twl4030 or whatever). OMAP has both + * 1.8V and 3.0V modes, controlled by the PBIAS register. + * + * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which + * is most naturally TWL VSIM; those pins also use PBIAS. + * + * FIXME handle VMMC1A as needed ... + */ + if (power_on) { + reg = omap_ctrl_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); + } else { + reg = omap_ctrl_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); + } +} + +static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, + int power_on, int vdd) +{ + u32 reg; + + /* 100ms delay required for PBIAS configuration */ + msleep(100); + + if (power_on) { + reg = omap_ctrl_readl(control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; + if ((1 << vdd) <= MMC_VDD_165_195) { + reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | + OMAP4_MMC1_PWRDNZ); + } else { + reg |= (OMAP4_MMC1_PBIASLITE_VMODE | + OMAP4_MMC1_PBIASLITE_PWRDNZ | + OMAP4_MMC1_PWRDNZ); + } + omap_ctrl_writel(reg, control_pbias_offset); + } else { + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | + OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ); + omap_ctrl_writel(reg, control_pbias_offset); + } +} + static void hsmmc23_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { @@ -140,6 +197,24 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot, } } +static int mmc_twl_late_init(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + + if (cpu_is_omap44xx()) { + /* MMC1 Card detect Configuration */ + if (pdev->id == 0) { + ret = omap4_hsmmc1_card_detect_config(); + if (ret < 0) + pr_err("Unable to configure" + "Card detect for MMC1\n"); + } + } + return ret; +} + static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) @@ -147,13 +222,28 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info struct omap2_hsmmc_info *c; int nr_hsmmc = ARRAY_SIZE(hsmmc_data); int i; + u32 reg; - if (cpu_is_omap2430()) { - control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; + if (!cpu_is_omap44xx()) { + if (cpu_is_omap2430()) { + control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; + } else { + control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; + } } else { - control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; + control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; + control_mmc1 = OMAP44XX_CONTROL_MMC1; + reg = omap_ctrl_readl(control_mmc1); + reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); + reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | + OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); + reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | + OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); + omap_ctrl_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { @@ -186,6 +276,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) mmc->slots[0].wires = c->wires; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; + mmc->init = mmc_twl_late_init; mmc->get_context_loss_count = hsmmc_get_context_loss; @@ -220,10 +311,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info switch (c->mmc) { case 1: - /* on-chip level shifting via PBIAS0/PBIAS1 */ - mmc->slots[0].before_set_reg = hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = hsmmc1_after_set_reg; - + if (cpu_is_omap44xx()) { + /* on-chip level shifting via PBIAS0/PBIAS1 */ + mmc->slots[0].before_set_reg = + omap4_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap4_hsmmc1_after_set_reg; + } else { + mmc->slots[0].before_set_reg = + omap_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap_hsmmc1_after_set_reg; + } /* Omap3630 HSMMC1 supports only 4-bit */ if (cpu_is_omap3630() && c->wires > 4) { c->wires = 4; diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index a56deee..6d17a61 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -207,6 +207,9 @@ /* 44xx control status register offset */ #define OMAP44XX_CONTROL_STATUS 0x2c4 +/* 44xx-only CONTROL_GENERAL register offsets */ +#define OMAP44XX_CONTROL_MMC1 0x628 +#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -252,6 +255,20 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) +/* CONTROL_PBIAS_LITE bits for OMAP4 */ +#define OMAP4_MMC1_PWRDNZ (1 << 26) +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) +#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) + +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) +#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) +#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) +#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) +#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) + /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index eb198db..423a355 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -142,6 +142,13 @@ #define TWL6030_CHARGER_FAULT_INT_MASK 0x60 #define TWL6030_MMCCTRL 0xEE +#define VMMC_AUTO_OFF (0x1 << 3) +#define SW_FC (0x1 << 2) + +#define TWL6030_CFG_INPUT_PUPD3 0xF2 +#define MMC_PU (0x1 << 3) +#define MMC_PD (0x1 << 2) + #define TWL4030_CLASS_ID 0x4030 #define TWL6030_CLASS_ID 0x6030 @@ -174,11 +181,40 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); int twl6030_interrupt_mask(u8 bit_mask, u8 offset); -/* - * MMC1 Controller on OMAP4 uses Phoenix Irq for Card detect. - */ +/* MMC1 Controller on OMAP4 uses Phoenix Irq for Card detect */ int twl6030_mmc_card_detect(struct device *dev, int slot); +/* Configuring Card Detect for MMC1 */ +static inline int omap4_hsmmc1_card_detect_config(void) +{ + int res = -1; + u8 reg_val = 0; + + /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */ + if (twl_class_is_6030()) { + twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, + REG_INT_MSK_LINE_B); + twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, + REG_INT_MSK_STS_B); + } + + /* + * Intially Configuring MMC_CTRL for receving interrupts & + * Card status on TWL6030 for MMC1 + */ + reg_val |= (SW_FC & ~VMMC_AUTO_OFF); + twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL); + res = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, + TWL6030_CFG_INPUT_PUPD3); + if (res < 0) + return -EINVAL; + reg_val = 0; + reg_val &= ~(MMC_PU | MMC_PD); + twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, + TWL6030_CFG_INPUT_PUPD3); + return 0; +} + /*----------------------------------------------------------------------*/ /* From patchwork Fri Mar 19 10:46:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ranjith Lohithakshan X-Patchwork-Id: 86912 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2JAhxpY004451 for ; Fri, 19 Mar 2010 10:46:55 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751313Ab0CSKqy (ORCPT ); Fri, 19 Mar 2010 06:46:54 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50097 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750949Ab0CSKqy (ORCPT ); Fri, 19 Mar 2010 06:46:54 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2JAknMB029459 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 19 Mar 2010 05:46:52 -0500 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o2JAklHn003833; Fri, 19 Mar 2010 16:16:48 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id o2JAklRv032066; Fri, 19 Mar 2010 16:16:47 +0530 Received: (from a0876318@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id o2JAkkcE032061; Fri, 19 Mar 2010 16:16:46 +0530 From: Ranjith Lohithakshan To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, ranjithl@ti.com Subject: [PATCH] OMAP3: PM: Fix compilation error observed when cpufreq is disabled Date: Fri, 19 Mar 2010 16:16:46 +0530 Message-Id: <1268995606-32018-1-git-send-email-ranjithl@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 19 Mar 2010 10:46:55 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index a6d0b34..498cb5b 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -492,7 +492,11 @@ struct clk_functions omap2_clk_functions = { .clk_disable_unused = omap2_clk_disable_unused, #ifdef CONFIG_CPU_FREQ /* These will be removed when the OPP code is integrated */ +#ifdef CONFIG_ARCH_OMAP3 + .clk_init_cpufreq_table = omap3_clk_init_cpufreq_table, +#else .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, +#endif .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, #endif }; diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 57522de..d5153b6 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3560,8 +3560,6 @@ int __init omap3xxx_clk_init(void) else dpll4_dd = dpll4_dd_34xx; - omap2_clk_functions.clk_init_cpufreq_table = - omap3_clk_init_cpufreq_table; clk_init(&omap2_clk_functions); for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); From patchwork Thu Aug 5 22:21:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 117543 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o75MXYX5028323 for ; Thu, 5 Aug 2010 22:33:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756763Ab0HEWcH (ORCPT ); Thu, 5 Aug 2010 18:32:07 -0400 Received: from kroah.org ([198.145.64.141]:41373 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760809Ab0HEWcF (ORCPT ); Thu, 5 Aug 2010 18:32:05 -0400 Received: from localhost (c-24-16-163-131.hsd1.wa.comcast.net [24.16.163.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id B7445484FB; Thu, 5 Aug 2010 15:32:04 -0700 (PDT) From: Greg Kroah-Hartman To: devel@driverdev.osuosl.org Cc: Andy Shevchenko , Ohad Ben-Cohen , linux-omap@vger.kernel.org, Greg Kroah-Hartman Subject: [PATCH 288/524] staging: tidspbridge: gen: simplify and clean up Date: Thu, 5 Aug 2010 15:21:11 -0700 Message-Id: <1281047107-17649-288-git-send-email-gregkh@suse.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <20100805213308.GA13744@kroah.com> References: <20100805213308.GA13744@kroah.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 05 Aug 2010 22:33:35 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/gen/uuidutil.c b/drivers/staging/tidspbridge/gen/uuidutil.c index ce9319d..eb09bc3 100644 --- a/drivers/staging/tidspbridge/gen/uuidutil.c +++ b/drivers/staging/tidspbridge/gen/uuidutil.c @@ -54,61 +54,19 @@ void uuid_uuid_to_string(IN struct dsp_uuid *uuid_obj, OUT char *pszUuid, DBC_ENSURE(i != -1); } -/* - * ======== htoi ======== - * Purpose: - * Converts a hex value to a decimal integer. - */ - -static int htoi(char c) +static s32 uuid_hex_to_bin(char *buf, s32 len) { - switch (c) { - case '0': - return 0; - case '1': - return 1; - case '2': - return 2; - case '3': - return 3; - case '4': - return 4; - case '5': - return 5; - case '6': - return 6; - case '7': - return 7; - case '8': - return 8; - case '9': - return 9; - case 'A': - return 10; - case 'B': - return 11; - case 'C': - return 12; - case 'D': - return 13; - case 'E': - return 14; - case 'F': - return 15; - case 'a': - return 10; - case 'b': - return 11; - case 'c': - return 12; - case 'd': - return 13; - case 'e': - return 14; - case 'f': - return 15; + s32 i; + s32 result = 0; + + for (i = 0; i < len; i++) { + value = hex_to_bin(*buf++); + result *= 16; + if (value > 0) + result += value; } - return 0; + + return result; } /* @@ -118,106 +76,37 @@ static int htoi(char c) */ void uuid_uuid_from_string(IN char *pszUuid, OUT struct dsp_uuid *uuid_obj) { - char c; - s32 i, j; - s32 result; - char *temp = pszUuid; + s32 j; - result = 0; - for (i = 0; i < 8; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->ul_data1 = result; + uuid_obj->ul_data1 = uuid_hex_to_bin(pszUuid, 8); + pszUuid += 8; /* Step over underscore */ - temp++; + pszUuid++; - result = 0; - for (i = 0; i < 4; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->us_data2 = (u16) result; + uuid_obj->us_data2 = (u16) uuid_hex_to_bin(pszUuid, 4); + pszUuid += 4; /* Step over underscore */ - temp++; - - result = 0; - for (i = 0; i < 4; i++) { - /* Get first character in string */ - c = *temp; + pszUuid++; - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->us_data3 = (u16) result; + uuid_obj->us_data3 = (u16) uuid_hex_to_bin(pszUuid, 4); + pszUuid += 4; /* Step over underscore */ - temp++; - - result = 0; - for (i = 0; i < 2; i++) { - /* Get first character in string */ - c = *temp; + pszUuid++; - /* Increase the results by new value */ - result *= 16; - result += htoi(c); + uuid_obj->uc_data4 = (u8) uuid_hex_to_bin(pszUuid, 2); + pszUuid += 2; - /* Go to next character in string */ - temp++; - } - uuid_obj->uc_data4 = (u8) result; - - result = 0; - for (i = 0; i < 2; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->uc_data5 = (u8) result; + uuid_obj->uc_data5 = (u8) uuid_hex_to_bin(pszUuid, 2); + pszUuid += 2; /* Step over underscore */ - temp++; + pszUuid++; for (j = 0; j < 6; j++) { - result = 0; - for (i = 0; i < 2; i++) { - /* Get first character in string */ - c = *temp; - - /* Increase the results by new value */ - result *= 16; - result += htoi(c); - - /* Go to next character in string */ - temp++; - } - uuid_obj->uc_data6[j] = (u8) result; + uuid_obj->uc_data6[j] = (u8) uuid_hex_to_bin(pszUuid, 2); + pszUuid += 2; } } From patchwork Tue May 11 01:42:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abraham Arce X-Patchwork-Id: 98568 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B1gKrI004905 for ; Tue, 11 May 2010 01:42:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757533Ab0EKBm4 (ORCPT ); Mon, 10 May 2010 21:42:56 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:47364 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756794Ab0EKBm4 convert rfc822-to-8bit (ORCPT ); Mon, 10 May 2010 21:42:56 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B1gnZp005570 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 May 2010 20:42:49 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4B1gm4R027054; Mon, 10 May 2010 20:42:48 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B1gmnm025251; Mon, 10 May 2010 20:42:48 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dlee73.ent.ti.com ([157.170.170.88]) with mapi; Mon, 10 May 2010 20:42:48 -0500 From: "Arce, Abraham" To: "linux-omap@vger.kernel.org" , "spi-devel-general@lists.sourceforge.net" Date: Mon, 10 May 2010 20:42:47 -0500 Subject: [PATCH v3 2/3] OMAP4: Ethernet: KS8851 Board Support Thread-Topic: [PATCH v3 2/3] OMAP4: Ethernet: KS8851 Board Support Thread-Index: Acrwq0IQwKshY2VqRfq/SjZaR0PUdQ== Message-ID: <27F9C60D11D683428E133F85D2BB4A53043DFD52D8@dlee03.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 01:42:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index b88f28c..be7a786 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,75 @@ #include #include +#define ETH_KS8851_IRQ 34 +#define ETH_KS8851_POWER_ON 48 +#define ETH_KS8851_QUART 138 + +static struct spi_board_info sdp4430_spi_board_info[] __initdata = { + { + .modalias = "ks8851", + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 24000000, + .irq = ETH_KS8851_IRQ, + }, +}; + +static int omap_ethernet_init(void) +{ + int status; + + /* Request of GPIO lines */ + + status = gpio_request(ETH_KS8851_POWER_ON, "eth_power"); + if (status) { + pr_err("Cannot request GPIO %d\n", ETH_KS8851_POWER_ON); + return status; + } + + status = gpio_request(ETH_KS8851_QUART, "quart"); + if (status) { + pr_err("Cannot request GPIO %d\n", ETH_KS8851_QUART); + goto error1; + } + + status = gpio_request(ETH_KS8851_IRQ, "eth_irq"); + if (status) { + pr_err("Cannot request GPIO %d\n", ETH_KS8851_IRQ); + goto error2; + } + + /* Configuration of requested GPIO lines */ + + status = gpio_direction_output(ETH_KS8851_POWER_ON, 1); + if (status) { + pr_err("Cannot set output GPIO %d\n", ETH_KS8851_IRQ); + goto error3; + } + + status = gpio_direction_output(ETH_KS8851_QUART, 1); + if (status) { + pr_err("Cannot set output GPIO %d\n", ETH_KS8851_QUART); + goto error3; + } + + status = gpio_direction_input(ETH_KS8851_IRQ); + if (status) { + pr_err("Cannot set input GPIO %d\n", ETH_KS8851_IRQ); + goto error3; + } + + return 0; + +error3: + gpio_free(ETH_KS8851_IRQ); +error2: + gpio_free(ETH_KS8851_QUART); +error1: + gpio_free(ETH_KS8851_POWER_ON); + return status; +} + static struct platform_device sdp4430_lcd_device = { .name = "sdp4430_lcd", .id = -1, @@ -113,6 +183,8 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap_4430sdp_init(void) { + int status; + platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); /* OMAP4 SDP uses internal transceiver so register nop transceiver */ @@ -120,6 +192,15 @@ static void __init omap_4430sdp_init(void) /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ if (!cpu_is_omap44xx()) usb_musb_init(&musb_board_data); + + status = omap_ethernet_init(); + if (status) { + pr_err("Ethernet initialization failed: %d\n", status); + } else { + sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ); + spi_register_board_info(sdp4430_spi_board_info, + ARRAY_SIZE(sdp4430_spi_board_info)); + } } static void __init omap_4430sdp_map_io(void) From patchwork Tue May 11 01:43:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abraham Arce X-Patchwork-Id: 98569 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B1hQHU005112 for ; Tue, 11 May 2010 01:43:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757564Ab0EKBnZ (ORCPT ); Mon, 10 May 2010 21:43:25 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:46198 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756794Ab0EKBnY convert rfc822-to-8bit (ORCPT ); Mon, 10 May 2010 21:43:24 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B1hIAr012536 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 May 2010 20:43:18 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4B1hHDf027884; Mon, 10 May 2010 20:43:17 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B1hHB6025332; Mon, 10 May 2010 20:43:17 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dlee73.ent.ti.com ([157.170.170.88]) with mapi; Mon, 10 May 2010 20:43:17 -0500 From: "Arce, Abraham" To: "linux-omap@vger.kernel.org" , "spi-devel-general@lists.sourceforge.net" Date: Mon, 10 May 2010 20:43:16 -0500 Subject: [PATCH v3 3/3] OMAP4: Networking: Defconfig Support Thread-Topic: [PATCH v3 3/3] OMAP4: Networking: Defconfig Support Thread-Index: Acrwq1NWPG6rg8FWT+KZThkEQOJnig== Message-ID: <27F9C60D11D683428E133F85D2BB4A53043DFD52D9@dlee03.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 01:43:26 +0000 (UTC) diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index a96bca2..d87a349 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig @@ -343,7 +343,34 @@ CONFIG_BINFMT_MISC=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_NET is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_XFRM=y +CONFIG_INET=y +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_IPV6 is not set + +# +# Network testing +# +# CONFIG_WIRELESS is not set + # # Device Drivers @@ -386,6 +413,13 @@ CONFIG_HAVE_IDE=y # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_PHONE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_KS8851=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set # # Input device support @@ -457,7 +491,13 @@ CONFIG_HW_RANDOM=y # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set -# CONFIG_SPI is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_OMAP24XX=y # # PPS support @@ -634,6 +674,19 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y # # Partition Types From patchwork Thu Jun 17 14:09:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 106689 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HE9f83002417 for ; Thu, 17 Jun 2010 14:09:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760100Ab0FQOJi (ORCPT ); Thu, 17 Jun 2010 10:09:38 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:38266 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760063Ab0FQOJh convert rfc822-to-8bit (ORCPT ); Thu, 17 Jun 2010 10:09:37 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o5HE9Tbm014331 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 17 Jun 2010 09:09:31 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o5HE9QJO010482; Thu, 17 Jun 2010 19:39:27 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Thu, 17 Jun 2010 19:39:26 +0530 From: "Gupta, Ajay Kumar" To: Sergei Shtylyov CC: "linux-usb@vger.kernel.org" , "linux-omap@vger.kernel.org" , "felipe.balbi@nokia.com" , "gregkh@suse.de" Date: Thu, 17 Jun 2010 19:39:24 +0530 Subject: RE: [PATCH 3/8] musb: fix compilation warning in host only mode Thread-Topic: [PATCH 3/8] musb: fix compilation warning in host only mode Thread-Index: AcsOIJkIShfYJRfzR/CSbX4DcGXlKAABc1GQ Message-ID: <19F8576C6E063C45BE387C64729E7394044E91B88E@dbde02.ent.ti.com> References: <1276771242-5201-1-git-send-email-ajay.gupta@ti.com> <1276771242-5201-2-git-send-email-ajay.gupta@ti.com> <1276771242-5201-3-git-send-email-ajay.gupta@ti.com> <1276771242-5201-4-git-send-email-ajay.gupta@ti.com> <4C1A0499.9020802@ru.mvista.com> <19F8576C6E063C45BE387C64729E7394044E91B843@dbde02.ent.ti.com> <4C1A2220.7070502@mvista.com> In-Reply-To: <4C1A2220.7070502@mvista.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 14:09:41 +0000 (UTC) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index a8b0440..cfae447 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -704,7 +704,9 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, #ifdef CONFIG_USB_MUSB_HDRC_HCD if (int_usb & MUSB_INTR_CONNECT) { struct usb_hcd *hcd = musb_to_hcd(musb); +#ifdef CONFIG_USB_MUSB_OTG void __iomem *mbase = musb->mregs; +#endif handled = IRQ_HANDLED; musb->is_active = 1; From patchwork Tue May 11 01:42:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abraham Arce X-Patchwork-Id: 98566 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4B1gKrG004905 for ; Tue, 11 May 2010 01:42:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757422Ab0EKBmS (ORCPT ); Mon, 10 May 2010 21:42:18 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:38897 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756572Ab0EKBmS convert rfc822-to-8bit (ORCPT ); Mon, 10 May 2010 21:42:18 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4B1gBEC030225 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 May 2010 20:42:11 -0500 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B1gBO4010660; Mon, 10 May 2010 20:42:11 -0500 (CDT) Received: from dsbe71.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4B1gBTx025141; Mon, 10 May 2010 20:42:11 -0500 (CDT) Received: from dlee03.ent.ti.com ([157.170.170.18]) by dsbe71.ent.ti.com ([156.117.232.23]) with mapi; Mon, 10 May 2010 20:42:11 -0500 From: "Arce, Abraham" To: "linux-omap@vger.kernel.org" , "spi-devel-general@lists.sourceforge.net" Date: Mon, 10 May 2010 20:42:10 -0500 Subject: [PATCH v3 1/3] OMAP4: SPI: Fix Driver Kconfig Thread-Topic: [PATCH v3 1/3] OMAP4: SPI: Fix Driver Kconfig Thread-Index: Acrwqyv8d0GPNfxgSbSjupkfjIfCkQ== Message-ID: <27F9C60D11D683428E133F85D2BB4A53043DFD52D5@dlee03.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 01:42:20 +0000 (UTC) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a191fa2..f950b63 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -180,10 +180,10 @@ config SPI_OMAP_UWIRE This hooks up to the MicroWire controller on OMAP1 chips. config SPI_OMAP24XX - tristate "McSPI driver for OMAP24xx/OMAP34xx" - depends on ARCH_OMAP2 || ARCH_OMAP3 + tristate "McSPI driver for OMAP" + depends on ARCH_OMAP2PLUS help - SPI master controller for OMAP24xx/OMAP34xx Multichannel SPI + SPI master controller for OMAP24XX and later Multichannel SPI (McSPI) modules. config SPI_OMAP_100K From patchwork Mon May 3 06:18:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 96434 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o436JVMP009896 for ; Mon, 3 May 2010 06:19:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756494Ab0ECGTB (ORCPT ); Mon, 3 May 2010 02:19:01 -0400 Received: from smtp.nokia.com ([192.100.122.230]:34458 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755325Ab0ECGSy (ORCPT ); Mon, 3 May 2010 02:18:54 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o436ILWu019272; Mon, 3 May 2010 09:18:50 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:18:45 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 May 2010 09:18:45 +0300 Received: from localhost.localdomain (esdhcp04142.research.nokia.com [172.21.41.42]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o436Igob008122; Mon, 3 May 2010 09:18:44 +0300 From: Jani Nikula To: Tomi.Valkeinen@nokia.com, tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, ext-jani.1.nikula@nokia.com Subject: [PATCH v2 06/21] OMAP: DSS2: Taal: Fix request_irq() error handling Date: Mon, 3 May 2010 09:18:26 +0300 Message-Id: X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <7a01973540a3afa79701ee08a3d8732db4687d5b.1272621452.git.ext-jani.1.nikula@nokia.com> References: <1ef57e99d69aaf89b8e61074aa8ce2e5f6632d28.1272621452.git.ext-jani.1.nikula@nokia.com> <7a01973540a3afa79701ee08a3d8732db4687d5b.1272621452.git.ext-jani.1.nikula@nokia.com> In-Reply-To: References: X-OriginalArrivalTime: 03 May 2010 06:18:45.0212 (UTC) FILETIME=[7C1BA9C0:01CAEA88] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 06:19:31 +0000 (UTC) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 3729ec2..98f882a 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -601,7 +601,7 @@ static int taal_probe(struct omap_dss_device *dssdev) if (r) { dev_err(&dssdev->dev, "IRQ request failed\n"); gpio_free(gpio); - goto err3; + goto err4; } init_completion(&td->te_completion); @@ -612,18 +612,18 @@ static int taal_probe(struct omap_dss_device *dssdev) r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group); if (r) { dev_err(&dssdev->dev, "failed to create sysfs files\n"); - goto err4; + goto err5; } taal_hw_reset(dssdev); return 0; +err5: + if (td->use_ext_te) + free_irq(gpio_to_irq(dssdev->phy.dsi.ext_te_gpio), dssdev); err4: - if (td->use_ext_te) { - int gpio = dssdev->phy.dsi.ext_te_gpio; - free_irq(gpio_to_irq(gpio), dssdev); - gpio_free(gpio); - } + if (td->use_ext_te) + gpio_free(dssdev->phy.dsi.ext_te_gpio); err3: backlight_device_unregister(bldev); err2: From patchwork Fri May 21 11:29:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 101388 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4LBTwne003885 for ; Fri, 21 May 2010 11:29:59 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754211Ab0EUL3I (ORCPT ); Fri, 21 May 2010 07:29:08 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:40137 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753391Ab0EUL3F (ORCPT ); Fri, 21 May 2010 07:29:05 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4LBT3l6010379 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 21 May 2010 06:29:03 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4LBT0bn023809; Fri, 21 May 2010 06:29:01 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Fri, 21 May 2010 16:59:02 +0530 (IST) Message-ID: <28112.10.24.255.17.1274441342.squirrel@dbdmail.itg.ti.com> Date: Fri, 21 May 2010 16:59:02 +0530 (IST) Subject: [RFC] [PATCH] misc : ROHM BH1780GLI Ambient light sensor Driver From: "Hemanth V" To: linux-input@vger.kernel.org Cc: linux-omap@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 21 May 2010 11:29:59 +0000 (UTC) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0d0d625..0687a0c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -278,6 +278,17 @@ config SENSORS_TSL2550 This driver can also be built as a module. If so, the module will be called tsl2550. +config SENSORS_BH1780 + tristate "ROHM BH1780GLI ambient light sensor" + depends on I2C && SYSFS + help + If you say yes here you get support for the ROHM BH1780GLI + ambient light sensor. + + This driver can also be built as a module. If so, the module + will be called bh1780gli. + + config EP93XX_PWM tristate "EP93xx PWM support" depends on ARCH_EP93XX diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 7b6f7ee..c479d91 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/ obj-y += eeprom/ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmware_balloon.o +obj-$(CONFIG_SENSORS_BH1780) += bh1780gli.o diff --git a/drivers/misc/bh1780gli.c b/drivers/misc/bh1780gli.c new file mode 100644 index 0000000..9b4137d --- /dev/null +++ b/drivers/misc/bh1780gli.c @@ -0,0 +1,278 @@ +/* + * bh1780gli.c + * ROHM Ambient Light Sensor Driver + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +#include +#include +#include +#include +#include + +#define BH1780_REG_CONTROL 0x80 +#define BH1780_REG_PARTID 0x8A +#define BH1780_REG_MANFID 0x8B +#define BH1780_REG_DLOW 0x8C +#define BH1780_REG_DHIGH 0x8D + +#define BH1780_REVMASK (0xf) +#define BH1780_POWMASK (0x3) +#define BH1780_POFF (0x0) +#define BH1780_PON (0x3) + +/* power on settling time in ms */ +#define BH1780_PON_DELAY 2 + +struct bh1780_data { + struct i2c_client *client; + int power_state; + /* lock for sysfs operations */ + struct mutex lock; +}; + +int bh1780_write(struct bh1780_data *ddata, u8 reg, u8 val, char *msg) +{ + int ret = i2c_smbus_write_byte_data(ddata->client, reg, val); + if (ret < 0) + dev_err(&ddata->client->dev, + "i2c_smbus_write_byte_data failed error %d\ + Register (%s)\n", ret, msg); + return ret; +} + +int bh1780_read(struct bh1780_data *ddata, u8 reg, char *msg) +{ + int ret = i2c_smbus_read_byte_data(ddata->client, reg); + if (ret < 0) + dev_err(&ddata->client->dev, + "i2c_smbus_read_byte_data failed error %d\ + Register (%s)\n", ret, msg); + return ret; +} + +static ssize_t bh1780_show_lux(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + struct platform_device *pdev = to_platform_device(dev); + struct bh1780_data *ddata = platform_get_drvdata(pdev); + int lsb, msb; + + lsb = bh1780_read(ddata, BH1780_REG_DLOW, "DLOW"); + if (lsb < 0) + return lsb; + + msb = bh1780_read(ddata, BH1780_REG_DHIGH, "DHIGH"); + if (msb < 0) + return msb; + + return sprintf(buf, "%d\n", (msb << 8) | lsb); +} + +static ssize_t bh1780_show_power_state(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bh1780_data *ddata = platform_get_drvdata(pdev); + int state; + + state = bh1780_read(ddata, BH1780_REG_CONTROL, "CONTROL"); + if (state < 0) + return state; + + return sprintf(buf, "%d\n", state & BH1780_POWMASK); +} + +static ssize_t bh1780_store_power_state(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bh1780_data *ddata = platform_get_drvdata(pdev); + unsigned long val; + int error; + + error = strict_strtoul(buf, 0, &val); + if (error) + return error; + + if (val < BH1780_POFF || val > BH1780_PON) + return -EINVAL; + + mutex_lock(&ddata->lock); + + error = bh1780_write(ddata, BH1780_REG_CONTROL, val, "CONTROL"); + if (error < 0) { + mutex_unlock(&ddata->lock); + return error; + } + + msleep(BH1780_PON_DELAY); + ddata->power_state = val; + mutex_unlock(&ddata->lock); + return count; + +} + +static DEVICE_ATTR(lux, S_IRUGO, bh1780_show_lux, NULL); + +static DEVICE_ATTR(power_state, S_IWUSR | S_IRUGO, + bh1780_show_power_state, bh1780_store_power_state); + +static struct attribute *bh1780_attributes[] = { + &dev_attr_power_state.attr, + &dev_attr_lux.attr, + NULL +}; + +static const struct attribute_group bh1780_attr_group = { + .attrs = bh1780_attributes, +}; + +static int __devinit bh1780_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + struct bh1780_data *ddata = NULL; + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE)) { + ret = -EIO; + goto err_op_failed; + } + + ddata = kzalloc(sizeof(struct bh1780_data), GFP_KERNEL); + if (ddata == NULL) { + ret = -ENOMEM; + goto err_op_failed; + } + + ddata->client = client; + i2c_set_clientdata(client, ddata); + + ret = bh1780_read(ddata, BH1780_REG_PARTID, "PART ID"); + if (ret < 0) + goto err_op_failed; + + dev_info(&client->dev, "Ambient Light Sensor, Rev : %d\n", + (ret & BH1780_REVMASK)); + + mutex_init(&ddata->lock); + + ret = sysfs_create_group(&client->dev.kobj, &bh1780_attr_group); + if (ret) + goto err_op_failed; + + return 0; + +err_op_failed: + if (ddata != NULL) + kfree(ddata); + + return ret; +} + +static int __devexit bh1780_remove(struct i2c_client *client) +{ + struct bh1780_data *ddata; + + ddata = i2c_get_clientdata(client); + sysfs_remove_group(&client->dev.kobj, &bh1780_attr_group); + + if (ddata != NULL) { + i2c_set_clientdata(client, NULL); + kfree(ddata); + } + + return 0; +} + +#ifdef CONFIG_PM +static int bh1780_suspend(struct i2c_client *client, pm_message_t mesg) +{ + struct bh1780_data *ddata; + int state, ret; + + ddata = i2c_get_clientdata(client); + state = bh1780_read(ddata, BH1780_REG_CONTROL, "CONTROL"); + if (state < 0) + return state; + + ddata->power_state = state & BH1780_POWMASK; + + ret = bh1780_write(ddata, BH1780_REG_CONTROL, BH1780_POFF, + "CONTROL"); + + if (ret < 0) + return ret; + + return 0; +} + +static int bh1780_resume(struct i2c_client *client) +{ + struct bh1780_data *ddata; + int state, ret; + + ddata = i2c_get_clientdata(client); + state = ddata->power_state; + + ret = bh1780_write(ddata, BH1780_REG_CONTROL, state, + "CONTROL"); + + if (ret < 0) + return ret; + + return 0; +} +#endif + +static const struct i2c_device_id bh1780_id[] = { + { "bh1780", 0 }, + { }, +}; + +static struct i2c_driver bh1780_driver = { + .probe = bh1780_probe, + .remove = bh1780_remove, + .id_table = bh1780_id, +#ifdef CONFIG_PM + .suspend = bh1780_suspend, + .resume = bh1780_resume, +#endif + .driver = { + .name = "bh1780" + }, +}; + +static int __init bh1780_init(void) +{ + return i2c_add_driver(&bh1780_driver); +} + +static void __exit bh1780_exit(void) +{ + i2c_del_driver(&bh1780_driver); +} + +module_init(bh1780_init) +module_exit(bh1780_exit) + +MODULE_DESCRIPTION("BH1780GLI Ambient Light Sensor Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Hemanth V "); From patchwork Mon Mar 29 12:15:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 88960 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2TCFchk015800 for ; Mon, 29 Mar 2010 12:15:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751710Ab0C2MPp (ORCPT ); Mon, 29 Mar 2010 08:15:45 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:41061 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751045Ab0C2MPo (ORCPT ); Mon, 29 Mar 2010 08:15:44 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o2TCFeld002952 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 29 Mar 2010 07:15:40 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o2TCFbjI010840; Mon, 29 Mar 2010 07:15:39 -0500 (CDT) Received: from 10.24.255.17 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Mon, 29 Mar 2010 17:45:40 +0530 (IST) Message-ID: <49670.10.24.255.17.1269864940.squirrel@dbdmail.itg.ti.com> In-Reply-To: <33474.10.24.255.18.1269863733.squirrel@dbdmail.itg.ti.com> References: <19039.10.24.255.18.1269336516.squirrel@dbdmail.itg.ti.com> <20100326144415.GA1591@ucw.cz> <33474.10.24.255.18.1269863733.squirrel@dbdmail.itg.ti.com> Date: Mon, 29 Mar 2010 17:45:40 +0530 (IST) Subject: Re: Merge plans for Staging Synaptics Touchscreen Driver From: "Hemanth V" To: "Pavel Machek" Cc: linux-input@vger.kernel.org, linux-omap@vger.kernel.org User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 29 Mar 2010 12:15:46 +0000 (UTC) diff --git a/drivers/staging/dream/synaptics_i2c_rmi.c b/drivers/staging/dream/synaptics_i2c_rmi.c index 4de6bc9..f3bc7d6 100644 --- a/drivers/staging/dream/synaptics_i2c_rmi.c +++ b/drivers/staging/dream/synaptics_i2c_rmi.c @@ -108,9 +108,6 @@ static void decode_report(struct synaptics_ts_data *ts, u8 *buf) int f, a; int base = 2; int z = buf[1]; - int w = buf[0] >> 4; - int finger = buf[0] & 7; - int finger2_pressed; for (f = 0; f < 2; f++) { u32 flip_flag = SYNAPTICS_FLIP_X; @@ -150,14 +147,6 @@ static void decode_report(struct synaptics_ts_data *ts, u8 *buf) input_report_abs(ts->input_dev, ABS_Y, pos[0][1]); } input_report_abs(ts->input_dev, ABS_PRESSURE, z); - input_report_abs(ts->input_dev, ABS_TOOL_WIDTH, w); - input_report_key(ts->input_dev, BTN_TOUCH, finger); - finger2_pressed = finger > 1 && finger != 7; - input_report_key(ts->input_dev, BTN_2, finger2_pressed); - if (finger2_pressed) { - input_report_abs(ts->input_dev, ABS_HAT0X, pos[1][0]); - input_report_abs(ts->input_dev, ABS_HAT0Y, pos[1][1]); - } input_sync(ts->input_dev); } From patchwork Mon May 3 21:41:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 96570 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o43LfKMM016475 for ; Mon, 3 May 2010 21:41:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757076Ab0ECVlT (ORCPT ); Mon, 3 May 2010 17:41:19 -0400 Received: from mail-px0-f174.google.com ([209.85.212.174]:45892 "EHLO mail-px0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756680Ab0ECVlT (ORCPT ); Mon, 3 May 2010 17:41:19 -0400 Received: by mail-px0-f174.google.com with SMTP id 5so454018pxi.19 for ; Mon, 03 May 2010 14:41:18 -0700 (PDT) Received: by 10.143.24.29 with SMTP id b29mr9363234wfj.348.1272922878864; Mon, 03 May 2010 14:41:18 -0700 (PDT) Received: from localhost (deeprootsystems.com [216.254.16.51]) by mx.google.com with ESMTPS id 21sm4989029pzk.8.2010.05.03.14.41.17 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 03 May 2010 14:41:18 -0700 (PDT) From: Kevin Hilman To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] OMAP3: PRCM interrupt: only check and clear enabled PRCM IRQs Date: Mon, 3 May 2010 14:41:10 -0700 Message-Id: <1272922871-18847-3-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.7.0.2 In-Reply-To: <1272922871-18847-1-git-send-email-khilman@deeprootsystems.com> References: <1272922871-18847-1-git-send-email-khilman@deeprootsystems.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 21:41:21 +0000 (UTC) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index fee2efb..c38016b 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -266,13 +266,16 @@ static int _prcm_int_handle_wakeup(void) */ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) { - u32 irqstatus_mpu; + u32 irqenable_mpu, irqstatus_mpu; int c = 0; - do { - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + irqenable_mpu = prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQENABLE_MPU_OFFSET); + irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + irqstatus_mpu &= irqenable_mpu; + do { if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { c = _prcm_int_handle_wakeup(); @@ -291,7 +294,11 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) prm_write_mod_reg(irqstatus_mpu, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); + irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + irqstatus_mpu &= irqenable_mpu; + + } while (irqstatus_mpu); return IRQ_HANDLED; } From patchwork Tue Apr 20 23:02:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 93775 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3KN2Bl5003722 for ; Tue, 20 Apr 2010 23:02:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752525Ab0DTXCJ (ORCPT ); Tue, 20 Apr 2010 19:02:09 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:35612 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752004Ab0DTXCF (ORCPT ); Tue, 20 Apr 2010 19:02:05 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3KN22Gk016382 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 20 Apr 2010 18:02:02 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3KN22R9024339; Tue, 20 Apr 2010 18:02:02 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o3KN2068021769; Tue, 20 Apr 2010 18:02:01 -0500 (CDT) From: Ernesto Ramos To: linux-omap@vger.kernel.org Cc: felipe.contreras@nokia.com, ameya.palande@nokia.com, hiroshi.doyu@nokia.com, Ernesto Ramos Subject: [PATCH 3/5v3] DSPBRIDGE: Use processor handle from context instead of user's. Date: Tue, 20 Apr 2010 18:02:58 -0500 Message-Id: <1271804580-17072-3-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 In-Reply-To: <1271804580-17072-2-git-send-email-ernesto@ti.com> References: <1271804580-17072-1-git-send-email-ernesto@ti.com> <1271804580-17072-2-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 20 Apr 2010 23:02:28 +0000 (UTC) diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c index 692bfd9..e6e193d 100644 --- a/drivers/dsp/bridge/pmgr/wcd.c +++ b/drivers/dsp/bridge/pmgr/wcd.c @@ -613,6 +613,7 @@ u32 procwrap_ctrl(union Trapped_Args *args, void *pr_ctxt) args->args_proc_ctrl.pargs; u8 *pargs = NULL; dsp_status status = DSP_SOK; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (psize) { if (get_user(cb_data_size, psize)) { @@ -630,7 +631,7 @@ u32 procwrap_ctrl(union Trapped_Args *args, void *pr_ctxt) cb_data_size); } if (DSP_SUCCEEDED(status)) { - status = proc_ctrl(args->args_proc_ctrl.hprocessor, + status = proc_ctrl(hprocessor, args->args_proc_ctrl.dw_cmd, (struct dsp_cbdata *)pargs); } @@ -660,11 +661,12 @@ u32 procwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt) void *node_tab[MAX_NODES]; u32 num_nodes; u32 alloc_cnt; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (!args->args_proc_enumnode_info.node_tab_size) return DSP_ESIZE; - status = proc_enum_nodes(args->args_proc_enumnode_info.hprocessor, + status = proc_enum_nodes(hprocessor, node_tab, args->args_proc_enumnode_info.node_tab_size, &num_nodes, &alloc_cnt); @@ -683,12 +685,13 @@ u32 procwrap_enum_node_info(union Trapped_Args *args, void *pr_ctxt) u32 procwrap_flush_memory(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (args->args_proc_flushmemory.ul_flags > PROC_WRITEBACK_INVALIDATE_MEM) return DSP_EINVALIDARG; - status = proc_flush_memory(args->args_proc_flushmemory.hprocessor, + status = proc_flush_memory(hprocessor, args->args_proc_flushmemory.pmpu_addr, args->args_proc_flushmemory.ul_size, args->args_proc_flushmemory.ul_flags); @@ -701,9 +704,10 @@ u32 procwrap_flush_memory(union Trapped_Args *args, void *pr_ctxt) u32 procwrap_invalidate_memory(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; status = - proc_invalidate_memory(args->args_proc_invalidatememory.hprocessor, + proc_invalidate_memory(hprocessor, args->args_proc_invalidatememory.pmpu_addr, args->args_proc_invalidatememory.ul_size); return status; @@ -716,13 +720,14 @@ u32 procwrap_enum_resources(union Trapped_Args *args, void *pr_ctxt) { dsp_status status = DSP_SOK; struct dsp_resourceinfo resource_info; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (args->args_proc_enumresources.resource_info_size < sizeof(struct dsp_resourceinfo)) return DSP_ESIZE; status = - proc_get_resource_info(args->args_proc_enumresources.hprocessor, + proc_get_resource_info(hprocessor, args->args_proc_enumresources.resource_type, &resource_info, args->args_proc_enumresources. @@ -742,13 +747,13 @@ u32 procwrap_get_state(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; struct dsp_processorstate proc_state; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (args->args_proc_getstate.state_info_size < sizeof(struct dsp_processorstate)) return DSP_ESIZE; - status = - proc_get_state(args->args_proc_getstate.hprocessor, &proc_state, + status = proc_get_state(hprocessor, &proc_state, args->args_proc_getstate.state_info_size); CP_TO_USR(args->args_proc_getstate.proc_state_obj, &proc_state, status, 1); @@ -763,14 +768,14 @@ u32 procwrap_get_trace(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; u8 *pbuf; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (args->args_proc_gettrace.max_size > MAX_TRACEBUFLEN) return DSP_ESIZE; pbuf = mem_calloc(args->args_proc_gettrace.max_size, MEM_NONPAGED); if (pbuf != NULL) { - status = proc_get_trace(args->args_proc_gettrace.hprocessor, - pbuf, + status = proc_get_trace(hprocessor, pbuf, args->args_proc_gettrace.max_size); } else { status = DSP_EMEMORY; @@ -792,6 +797,7 @@ u32 procwrap_load(union Trapped_Args *args, void *pr_ctxt) char *temp; s32 count = args->args_proc_load.argc_index; u8 **argv = NULL, **envp = NULL; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (count <= 0 || count > MAX_LOADARGS) { status = DSP_EINVALIDARG; @@ -874,7 +880,7 @@ u32 procwrap_load(union Trapped_Args *args, void *pr_ctxt) } if (DSP_SUCCEEDED(status)) { - status = proc_load(args->args_proc_load.hprocessor, + status = proc_load(hprocessor, args->args_proc_load.argc_index, (CONST char **)argv, (CONST char **)envp); } @@ -905,6 +911,7 @@ u32 procwrap_map(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; void *map_addr; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if (!args->args_proc_mapmem.ul_size) return DSP_ESIZE; @@ -917,8 +924,7 @@ u32 procwrap_map(union Trapped_Args *args, void *pr_ctxt) if (DSP_SUCCEEDED(status)) { if (put_user(map_addr, args->args_proc_mapmem.pp_map_addr)) { status = DSP_EINVALIDARG; - proc_un_map(args->args_proc_mapmem.hprocessor, - map_addr, pr_ctxt); + proc_un_map(hprocessor, map_addr, pr_ctxt); } } @@ -932,13 +938,13 @@ u32 procwrap_register_notify(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; struct dsp_notification notification; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; /* Initialize the notification data structure */ notification.ps_name = NULL; notification.handle = NULL; - status = - proc_register_notify(args->args_proc_register_notify.hprocessor, + status = proc_register_notify(hprocessor, args->args_proc_register_notify.event_mask, args->args_proc_register_notify.notify_type, ¬ification); @@ -954,12 +960,13 @@ u32 procwrap_reserve_memory(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; void *prsv_addr; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; if ((args->args_proc_rsvmem.ul_size <= 0) || (args->args_proc_rsvmem.ul_size & (PG_SIZE4K - 1)) != 0) return DSP_ESIZE; - status = proc_reserve_memory(args->args_proc_rsvmem.hprocessor, + status = proc_reserve_memory(hprocessor, args->args_proc_rsvmem.ul_size, &prsv_addr, pr_ctxt); if (DSP_SUCCEEDED(status)) { @@ -979,7 +986,7 @@ u32 procwrap_start(union Trapped_Args *args, void *pr_ctxt) { u32 ret; - ret = proc_start(args->args_proc_start.hprocessor); + ret = proc_start(((struct process_context *)pr_ctxt)->hprocessor); return ret; } @@ -990,7 +997,7 @@ u32 procwrap_un_map(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; - status = proc_un_map(args->args_proc_unmapmem.hprocessor, + status = proc_un_map(((struct process_context *)pr_ctxt)->hprocessor, args->args_proc_unmapmem.map_addr, pr_ctxt); return status; } @@ -1001,8 +1008,9 @@ u32 procwrap_un_map(union Trapped_Args *args, void *pr_ctxt) u32 procwrap_un_reserve_memory(union Trapped_Args *args, void *pr_ctxt) { dsp_status status; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; - status = proc_un_reserve_memory(args->args_proc_unrsvmem.hprocessor, + status = proc_un_reserve_memory(hprocessor, args->args_proc_unrsvmem.prsv_addr, pr_ctxt); return status; @@ -1015,7 +1023,7 @@ u32 procwrap_stop(union Trapped_Args *args, void *pr_ctxt) { u32 ret; - ret = proc_stop(args->args_proc_stop.hprocessor); + ret = proc_stop(((struct process_context *)pr_ctxt)->hprocessor); return ret; } @@ -1047,6 +1055,7 @@ u32 nodewrap_allocate(union Trapped_Args *args, void *pr_ctxt) struct dsp_nodeattrin proc_attr_in, *attr_in = NULL; struct node_res_object *node_res; int nodeid; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; /* Optional argument */ if (psize) { @@ -1077,7 +1086,7 @@ u32 nodewrap_allocate(union Trapped_Args *args, void *pr_ctxt) } if (DSP_SUCCEEDED(status)) { - status = node_allocate(args->args_node_allocate.hprocessor, + status = node_allocate(hprocessor, &node_uuid, (struct dsp_cbdata *)pargs, attr_in, &node_res, pr_ctxt); } @@ -1462,6 +1471,7 @@ u32 nodewrap_get_uuid_props(union Trapped_Args *args, void *pr_ctxt) dsp_status status = DSP_SOK; struct dsp_uuid node_uuid; struct dsp_ndbprops *pnode_props = NULL; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; CP_FM_USR(&node_uuid, args->args_node_getuuidprops.node_id_ptr, status, 1); @@ -1470,8 +1480,7 @@ u32 nodewrap_get_uuid_props(union Trapped_Args *args, void *pr_ctxt) pnode_props = mem_alloc(sizeof(struct dsp_ndbprops), MEM_NONPAGED); if (pnode_props != NULL) { status = - node_get_uuid_props(args->args_node_getuuidprops.hprocessor, - &node_uuid, pnode_props); + node_get_uuid_props(hprocessor, &node_uuid, pnode_props); CP_TO_USR(args->args_node_getuuidprops.node_props, pnode_props, status, 1); } else @@ -1753,8 +1762,9 @@ u32 cmmwrap_get_handle(union Trapped_Args *args, void *pr_ctxt) { dsp_status status = DSP_SOK; struct cmm_object *hcmm_mgr; + void *hprocessor = ((struct process_context *)pr_ctxt)->hprocessor; - status = cmm_get_handle(args->args_cmm_gethandle.hprocessor, &hcmm_mgr); + status = cmm_get_handle(hprocessor, &hcmm_mgr); CP_TO_USR(args->args_cmm_gethandle.ph_cmm_mgr, &hcmm_mgr, status, 1); From patchwork Fri Jul 23 23:22:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Sin X-Patchwork-Id: 114024 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6NN74MV030334 for ; Fri, 23 Jul 2010 23:07:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759005Ab0GWXHD (ORCPT ); Fri, 23 Jul 2010 19:07:03 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:53197 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757523Ab0GWXHA (ORCPT ); Fri, 23 Jul 2010 19:07:00 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6NN6tXG012201 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 23 Jul 2010 18:06:55 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6NN6q0t017692; Fri, 23 Jul 2010 18:06:53 -0500 (CDT) Received: from localhost.localdomain (neo.am.dhcp.ti.com [128.247.75.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBDHgRP19228; Mon, 13 Dec 1915 12:42:27 -0500 (CDT) From: David Sin To: , , Tony Lindgren , Russell King Cc: Hari Kanigeri , Ohad Ben-Cohen , Vaibhav Hiremath , Santosh Shilimkar , Lajos Molnar , David Sin Subject: [RFC 7/8] TILER-DMM: Main TILER driver implementation. Date: Fri, 23 Jul 2010 18:22:27 -0500 Message-Id: <1279927348-21750-8-git-send-email-davidsin@ti.com> X-Mailer: git-send-email 1.6.6.2 In-Reply-To: <1279927348-21750-7-git-send-email-davidsin@ti.com> References: <1279927348-21750-1-git-send-email-davidsin@ti.com> <1279927348-21750-2-git-send-email-davidsin@ti.com> <1279927348-21750-3-git-send-email-davidsin@ti.com> <1279927348-21750-4-git-send-email-davidsin@ti.com> <1279927348-21750-5-git-send-email-davidsin@ti.com> <1279927348-21750-6-git-send-email-davidsin@ti.com> <1279927348-21750-7-git-send-email-davidsin@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Jul 2010 23:07:05 +0000 (UTC) diff --git a/drivers/media/video/tiler/Kconfig b/drivers/media/video/tiler/Kconfig new file mode 100644 index 0000000..2c61471 --- /dev/null +++ b/drivers/media/video/tiler/Kconfig @@ -0,0 +1,65 @@ +config HAVE_TI_TILER + bool + default y + depends on ARCH_OMAP4 + +menuconfig TI_TILER + tristate "TI TILER support" + default y + depends on HAVE_TI_TILER + help + TILER and TILER-DMM driver for TI chips. The TI TILER device + enables video rotation on certain TI chips such as OMAP4 or + Netra. Video rotation will be limited without TILER support. + +config TILER_GRANULARITY + int "Allocation granularity (2^n)" + range 1 4096 + default 128 + depends on TI_TILER + help + This option sets the default TILER allocation granularity. It can + be overriden by the tiler.grain boot argument. + + The allocation granularity is the smallest TILER block size (in + bytes) managed distinctly by the TILER driver. TILER blocks of any + size are managed in chunks of at least this size. + + Must be a 2^n in the range of 1 to 4096; however, the TILER driver + may use a larger supported granularity. + + Supported values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, + 2048, 4096. + +config TILER_ALIGNMENT + int "Allocation alignment (2^n)" + range 1 4096 + default 4096 + depends on TI_TILER + help + This option sets the default TILER allocation alignment. It can + be overriden by the tiler.align boot argument. + + Must be a 2^n in the range of 1 to 4096; however, it is naturally + aligned to the TILER granularity. + + Supported values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, + 2048, 4096. + +config TILER_CACHE_LIMIT + int "Memory limit to cache free pages in MBytes" + range 0 128 + default 40 + depends on TI_TILER + help + This option sets the minimum memory that TILER retains even if + there is less TILER allocated memory is use. The unused memory is + instead stored in a cache to speed up allocation and freeing of + physical pages. + + This option can be overriden by the tiler.cache boot argument. + + While initially TILER will use less memory than this limit (0), it + will not release any memory used until it reaches this limit. + Thereafter, TILER will release any unused memory immediately as + long as there it is above this threshold. diff --git a/drivers/media/video/tiler/Makefile b/drivers/media/video/tiler/Makefile new file mode 100644 index 0000000..4a6495e --- /dev/null +++ b/drivers/media/video/tiler/Makefile @@ -0,0 +1,7 @@ +obj-$(CONFIG_TI_TILER) += tcm/ + +obj-$(CONFIG_TI_TILER) += tiler.o +tiler-objs = tiler-geom.o tiler-main.o tiler-iface.o tmm-pat.o + +obj-$(CONFIG_TI_TILER) += tiler_dmm.o +tiler_dmm-objs = dmm.o diff --git a/drivers/media/video/tiler/tiler-iface.c b/drivers/media/video/tiler/tiler-iface.c new file mode 100644 index 0000000..0b10fae --- /dev/null +++ b/drivers/media/video/tiler/tiler-iface.c @@ -0,0 +1,106 @@ +/* + * tiler-iface.c + * + * TILER driver interace functions for TI TILER hardware block. + * + * Authors: Lajos Molnar + * David Sin + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include +#include /* kmalloc */ +#include +#include +#include /* for ioremap_page */ + +#include "_tiler.h" + +/* + * Memory-Map Kernel APIs + * ========================================================================== + */ + +s32 tiler_mmap_blk(struct tiler_block_t *blk, u32 offs, u32 size, + struct vm_area_struct *vma, u32 voffs) +{ + u32 v, p, len; + + /* don't allow mremap */ + vma->vm_flags |= VM_DONTEXPAND | VM_RESERVED; + + /* mapping must fit into vma */ + BUG_ON(vma->vm_start > vma->vm_start + voffs || + vma->vm_start + voffs > vma->vm_start + voffs + size || + vma->vm_start + voffs + size > vma->vm_end); + + /* mapping must fit into block */ + BUG_ON(offs > offs + size || offs + size > tiler_size(blk)); + + v = tiler_vstride(blk); + p = tiler_pstride(blk); + + /* remap block portion */ + len = v - (offs % v); /* initial area to map */ + while (size) { + /* restrict to size still needs mapping */ + if (len > size) + len = size; + + vma->vm_pgoff = (blk->phys + offs) >> PAGE_SHIFT; + if (remap_pfn_range(vma, vma->vm_start + voffs, vma->vm_pgoff, + len, vma->vm_page_prot)) + return -EAGAIN; + voffs += len; + offs += len + p - v; + size -= len; + len = v; /* subsequent area to map */ + } + return 0; +} +EXPORT_SYMBOL(tiler_mmap_blk); + +s32 tiler_ioremap_blk(struct tiler_block_t *blk, u32 offs, u32 size, + u32 addr, u32 mtype) +{ + u32 v, p; + u32 len; /* area to map */ + const struct mem_type *type = get_mem_type(mtype); + + /* mapping must fit into address space */ + BUG_ON(addr > addr + size); + + /* mapping must fit into block */ + BUG_ON(offs > offs + size || offs + size > tiler_size(blk)); + + v = tiler_vstride(blk); + p = tiler_pstride(blk); + + /* move offset and address to end */ + offs += blk->phys + size; + addr += size; + + len = v - (offs % v); /* initial area to map */ + while (size) { + while (len && size) { + if (ioremap_page(addr - size, offs - size, type)) + return -EAGAIN; + len -= PAGE_SIZE; + size -= PAGE_SIZE; + } + + offs += p - v; + len = v; /* subsequent area to map */ + } + return 0; +} +EXPORT_SYMBOL(tiler_ioremap_blk); diff --git a/drivers/media/video/tiler/tiler-main.c b/drivers/media/video/tiler/tiler-main.c new file mode 100644 index 0000000..cbd84d1 --- /dev/null +++ b/drivers/media/video/tiler/tiler-main.c @@ -0,0 +1,426 @@ +/* + * tiler-main.c + * + * TILER driver main support functions for TI TILER hardware block. + * + * Authors: Lajos Molnar + * David Sin + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include +#include +#include /* platform_device() */ +#include +#include +#include /* dma_alloc_coherent */ +#include /* page_cache_release() */ +#include + +#include +#include "tmm.h" +#include "_tiler.h" +#include "tcm/tcm-sita.h" /* TCM algorithm */ + +static uint default_align = CONFIG_TILER_ALIGNMENT; +static uint granularity = CONFIG_TILER_GRANULARITY; + +module_param_named(align, default_align, uint, 0444); +MODULE_PARM_DESC(align, "Default block ssptr alignment"); +module_param_named(grain, granularity, uint, 0444); +MODULE_PARM_DESC(grain, "Granularity (bytes)"); + +struct platform_driver tiler_driver_ldm = { + .driver = { + .owner = THIS_MODULE, + .name = "tiler", + }, + .probe = NULL, + .shutdown = NULL, + .remove = NULL, +}; + +static struct tiler_ops tiler; /* shared methods and variables */ + +static struct list_head blocks; /* all tiler blocks */ + +static struct mutex mtx; +static struct tcm *tcm[TILER_FORMATS]; +static struct tmm *tmm[TILER_FORMATS]; +static u32 *dmac_va; +static dma_addr_t dmac_pa; + +/* info for a block */ +struct mem_info { + struct list_head global; /* global blocks */ + struct tiler_block_t blk; /* block info */ + struct tcm_area area; + u32 *mem; /* list of alloced phys addresses */ +}; + +/* + * TMM connectors + * ========================================================================== + */ +/* wrapper around tmm_map */ +static s32 refill_pat(struct tmm *tmm, struct tcm_area *area, u32 *ptr) +{ + s32 res = 0; + struct pat_area p_area = {0}; + + p_area.x0 = area->p0.x; + p_area.y0 = area->p0.y; + p_area.x1 = area->p1.x; + p_area.y1 = area->p1.y; + + memcpy(dmac_va, ptr, sizeof(*ptr) * tcm_sizeof(*area)); + + if (tmm_map(tmm, p_area, dmac_pa)) + res = -EFAULT; + + return res; +} + +/* wrapper around tmm_clear */ +static void clear_pat(struct tmm *tmm, struct tcm_area *area) +{ + struct pat_area p_area = {0}; + + p_area.x0 = area->p0.x; + p_area.y0 = area->p0.y; + p_area.x1 = area->p1.x; + p_area.y1 = area->p1.y; + + tmm_clear(tmm, p_area); +} + +/* + * Area handling methods + * ========================================================================== + */ + +/* verify input params and calculate tiler container params for a block */ +static s32 __analize_area(enum tiler_fmt fmt, u32 width, u32 height, + u16 *x_area, u16 *y_area, u16 *align, u16 *offs) +{ + /* input: width, height is in pixels, *align, *offs in bytes */ + /* output: x_area, y_area, *align in slots */ + + /* slot width, height, and row size */ + u32 slot_row, min_align; + const struct tiler_geom *g; + + /* width and height must be positive, format must be 2D */ + if (!width || !height || fmt == TILFMT_PAGE) + return -EINVAL; + + /* align must be 2 power */ + if (*align & (*align - 1)) + return -EINVAL; + + /* format must be valid */ + g = tiler.geom(fmt); + if (!g) + return -EINVAL; + + /* get the # of bytes per row in 1 slot */ + slot_row = g->slot_w * g->bpp; + + /* minimum alignment is at least 1 slot. Use default if needed */ + min_align = max(slot_row, granularity); + *align = ALIGN(*align ? : default_align, min_align); + + /* offset must be multiple of bpp */ + if (*offs & (g->bpp - 1) || *offs >= *align) + return -EINVAL; + + /* round down the offset to the nearest slot size, and increase width + to allow space for having the correct offset */ + width += (*offs & (min_align - 1)) / g->bpp; + + /* expand width to block size */ + width = ALIGN(width, min_align / g->bpp); + + /* adjust to slots */ + *x_area = DIV_ROUND_UP(width, g->slot_w); + *y_area = DIV_ROUND_UP(height, g->slot_h); + *align /= slot_row; + + if (*x_area > tiler.width || *y_area > tiler.height) + return -ENOMEM; + return 0; +} + +/* allocate a mem_info structure and reserves a 2d container area */ +static struct mem_info *get_2d_area(u16 w, u16 h, u16 align, struct tcm *tcm) +{ + struct mem_info *mi = NULL; + + /* reserve a block struct */ + mi = kmalloc(sizeof(*mi), GFP_KERNEL); + if (!mi) + return mi; + memset(mi, 0, sizeof(*mi)); + + /* reserve an area */ + if (tcm_reserve_2d(tcm, w, h, align, &mi->area)) { + kfree(mi); + return NULL; + } + + return mi; +} + +/* + * Block operations + * ========================================================================== + */ + +/* free a block */ +static s32 free_block(struct mem_info *mi) +{ + /* release memory */ + if (mi->mem) + tmm_free(tmm[tiler_fmt(mi->blk.phys)], mi->mem); + clear_pat(tmm[tiler_fmt(mi->blk.phys)], &mi->area); + + /* unreserve area */ + tcm_free(&mi->area); + + /* have mutex */ + + /* safe deletion as list may not have been assigned */ + if (mi->global.next) + list_del(&mi->global); + + kfree(mi); + return 0; +} + +/* create an empty block with just an area and add it to the global list */ +static struct mem_info *get_area(enum tiler_fmt fmt, u32 width, u32 height, + u16 align, u16 offs) +{ + u16 x, y; + struct mem_info *mi = NULL; + const struct tiler_geom *g = tiler.geom(fmt); + + /* calculate dimensions and alignment in slots */ + if (__analize_area(fmt, width, height, &x, &y, &align, &offs)) + return NULL; + + mi = get_2d_area(x, y, align, tcm[fmt]); + if (!mi) + return NULL; + + /* have mutex */ + list_add(&mi->global, &blocks); + + mi->blk.phys = tiler.addr(fmt, + mi->area.p0.x * g->slot_w, mi->area.p0.y * g->slot_h) + + offs; + return mi; +} + +/* allocate a new tiler block */ +static s32 alloc_block(enum tiler_fmt fmt, u32 width, u32 height, + u32 align, u32 offs, struct mem_info **info) +{ + struct mem_info *mi = NULL; + + *info = NULL; + + /* only support up to page alignment */ + if (align > PAGE_SIZE || offs >= (align ? : default_align)) + return -EINVAL; + + mutex_lock(&mtx); + + /* reserve area in tiler container */ + mi = get_area(fmt, width, height, align, offs); + if (!mi) + goto nomem; + + mi->blk.width = width; + mi->blk.height = height; + + /* allocate and map if mapping is supported */ + if (tmm_can_map(tmm[fmt])) { + mi->mem = tmm_get(tmm[fmt], tcm_sizeof(mi->area)); + if (!mi->mem) + goto cleanup; + + /* Ensure the data reaches to main memory before PAT refill */ + wmb(); + + /* program PAT */ + if (refill_pat(tmm[fmt], &mi->area, mi->mem)) + goto cleanup; + } + *info = mi; + mutex_unlock(&mtx); + return 0; + +cleanup: + free_block(mi); +nomem: + mutex_unlock(&mtx); + return -ENOMEM; +} + +/* + * Driver code + * ========================================================================== + */ + +/* driver initialization */ +static s32 __init tiler_init(void) +{ + s32 r = -1; + struct tcm *sita = NULL; + struct tmm *tmm_pat = NULL; + + tiler_geom_init(&tiler); + + /* check module parameters for correctness */ + if (default_align > PAGE_SIZE || + default_align & (default_align - 1) || + granularity < 1 || granularity > PAGE_SIZE || + granularity & (granularity - 1)) + return -EINVAL; + + /* + * Array of physical pages for PAT programming, which must be a 16-byte + * aligned physical address. + */ + dmac_va = dma_alloc_coherent(NULL, tiler.width * tiler.height * + sizeof(*dmac_va), &dmac_pa, GFP_ATOMIC); + if (!dmac_va) + return -ENOMEM; + + /* Allocate tiler container manager (we share 1 on OMAP4) */ + sita = sita_init(tiler.width, tiler.height, NULL); + + tcm[TILFMT_8BIT] = sita; + tcm[TILFMT_16BIT] = sita; + tcm[TILFMT_32BIT] = sita; + + /* Allocate tiler memory manager (must have 1 unique TMM per TCM ) */ + tmm_pat = tmm_pat_init(0); + tmm[TILFMT_8BIT] = tmm_pat; + tmm[TILFMT_16BIT] = tmm_pat; + tmm[TILFMT_32BIT] = tmm_pat; + + if (!sita || !tmm_pat) { + r = -ENOMEM; + goto error; + } + + r = platform_driver_register(&tiler_driver_ldm); + + mutex_init(&mtx); + INIT_LIST_HEAD(&blocks); + +error: + if (r) { + tcm_deinit(sita); + tmm_deinit(tmm_pat); + dma_free_coherent(NULL, tiler.width * tiler.height * + sizeof(*dmac_va), dmac_va, dmac_pa); + } + + return r; +} + +/* driver cleanup */ +static void __exit tiler_exit(void) +{ + int i, j; + struct mem_info *mi, *mi_; + + mutex_lock(&mtx); + + /* free all blocks */ + list_for_each_entry_safe(mi, mi_, &blocks, global) + free_block(mi); + + /* all lists should have cleared */ + BUG_ON(!list_empty(&blocks)); + + mutex_unlock(&mtx); + + dma_free_coherent(NULL, tiler.width * tiler.height * sizeof(*dmac_va), + dmac_va, dmac_pa); + + /* close containers only once */ + for (i = TILFMT_MIN; i <= TILFMT_MAX; i++) { + /* remove identical containers (tmm is unique per tcm) */ + for (j = i + 1; j <= TILFMT_MAX; j++) + if (tcm[i] == tcm[j]) { + tcm[j] = NULL; + tmm[j] = NULL; + } + + tcm_deinit(tcm[i]); + tmm_deinit(tmm[i]); + } + + mutex_destroy(&mtx); + platform_driver_unregister(&tiler_driver_ldm); +} + +/* + * Block Kernel APIs + * ========================================================================== + */ + +s32 tiler_alloc(struct tiler_block_t *blk, enum tiler_fmt fmt, + u32 align, u32 offs) +{ + struct mem_info *mi; + s32 res; + + /* blk must be valid, and blk->phys must be 0 */ + BUG_ON(!blk || blk->phys); + + res = alloc_block(fmt, blk->width, blk->height, align, offs, &mi); + if (mi) + blk->phys = mi->blk.phys; + return res; +} +EXPORT_SYMBOL(tiler_alloc); + +void tiler_free(struct tiler_block_t *blk) +{ + struct mem_info *mi; + + mutex_lock(&mtx); + + /* find block */ + list_for_each_entry(mi, &blocks, global) { + if (mi->blk.phys == blk->phys) { + free_block(mi); + break; + } + } + + blk->phys = 0; + + mutex_unlock(&mtx); +} +EXPORT_SYMBOL(tiler_free); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Lajos Molnar "); +MODULE_AUTHOR("David Sin "); +module_init(tiler_init); +module_exit(tiler_exit); From patchwork Fri May 7 15:18:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlos Chinea X-Patchwork-Id: 97746 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o47FHhfZ016375 for ; Fri, 7 May 2010 15:18:22 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756416Ab0EGPR3 (ORCPT ); Fri, 7 May 2010 11:17:29 -0400 Received: from smtp.nokia.com ([192.100.105.134]:28484 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755971Ab0EGPPx (ORCPT ); Fri, 7 May 2010 11:15:53 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o47FFh6R001061; Fri, 7 May 2010 10:15:52 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 7 May 2010 18:15:48 +0300 Received: from mgw-da01.ext.nokia.com ([147.243.128.24]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 7 May 2010 18:15:46 +0300 Received: from localhost.localdomain (esdhcp0399.research.nokia.com [172.21.39.9]) by mgw-da01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o47FFg4I019001; Fri, 7 May 2010 18:15:44 +0300 From: Carlos Chinea To: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Subject: [RFC PATCHv2 1/7] HSI: Introducing HSI framework Date: Fri, 7 May 2010 18:18:31 +0300 Message-Id: <1273245517-30712-2-git-send-email-carlos.chinea@nokia.com> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1273245517-30712-1-git-send-email-carlos.chinea@nokia.com> References: <1273245517-30712-1-git-send-email-carlos.chinea@nokia.com> X-OriginalArrivalTime: 07 May 2010 15:15:47.0156 (UTC) FILETIME=[2B892140:01CAEDF8] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 07 May 2010 15:18:23 +0000 (UTC) diff --git a/drivers/Kconfig b/drivers/Kconfig index a2b902f..4fe39f9 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -50,6 +50,8 @@ source "drivers/i2c/Kconfig" source "drivers/spi/Kconfig" +source "drivers/hsi/Kconfig" + source "drivers/pps/Kconfig" source "drivers/gpio/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 2c4f277..24ca5bd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_SCSI) += scsi/ obj-$(CONFIG_ATA) += ata/ obj-$(CONFIG_MTD) += mtd/ obj-$(CONFIG_SPI) += spi/ +obj-$(CONFIG_HSI) += hsi/ obj-y += net/ obj-$(CONFIG_ATM) += atm/ obj-$(CONFIG_FUSION) += message/ diff --git a/drivers/hsi/Kconfig b/drivers/hsi/Kconfig new file mode 100644 index 0000000..5af62ce --- /dev/null +++ b/drivers/hsi/Kconfig @@ -0,0 +1,13 @@ +# +# HSI driver configuration +# +menuconfig HSI + bool "HSI support" + ---help--- + The "High speed synchronous Serial Interface" is + synchronous serial interface used mainly to connect + application engines and cellular modems. + +if HSI + +endif # HSI diff --git a/drivers/hsi/Makefile b/drivers/hsi/Makefile new file mode 100644 index 0000000..b42b6cf --- /dev/null +++ b/drivers/hsi/Makefile @@ -0,0 +1,4 @@ +# +# Makefile for HSI +# +obj-$(CONFIG_HSI) += hsi.o diff --git a/drivers/hsi/hsi.c b/drivers/hsi/hsi.c new file mode 100644 index 0000000..0e29f2c --- /dev/null +++ b/drivers/hsi/hsi.c @@ -0,0 +1,489 @@ +/* + * hsi.c + * + * HSI core. + * + * Copyright (C) 2010 Nokia Corporation. All rights reserved. + * + * Contact: Carlos Chinea + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include + +struct hsi_cl_info { + struct list_head list; + struct hsi_board_info info; +}; + +static LIST_HEAD(hsi_board_list); + +static struct device_type hsi_ctrl = { + .name = "hsi_controller", +}; + +static struct device_type hsi_cl = { + .name = "hsi_client", +}; + +static struct device_type hsi_port = { + .name = "hsi_port", +}; + +static ssize_t modalias_show(struct device *dev, struct device_attribute *a, + char *buf) +{ + return sprintf(buf, "hsi:%s\n", dev_name(dev)); +} + +static struct device_attribute hsi_bus_dev_attrs[] = { + __ATTR_RO(modalias), + __ATTR_NULL, +}; + +static int hsi_bus_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + add_uevent_var(env, "MODALIAS=hsi:%s", dev_name(dev)); + + return 0; +} + +static int hsi_bus_match(struct device *dev, struct device_driver *driver) +{ + return strcmp(dev_name(dev), driver->name) == 0; +} + +static struct bus_type hsi_bus_type = { + .name = "hsi", + .dev_attrs = hsi_bus_dev_attrs, + .match = hsi_bus_match, + .uevent = hsi_bus_uevent, +}; + +static void hsi_client_release(struct device *dev) +{ + kfree(to_hsi_client(dev)); +} + +static void hsi_new_client(struct hsi_port *port, struct hsi_board_info *info) +{ + struct hsi_client *cl; + + cl = kzalloc(sizeof(*cl), GFP_KERNEL); + if (!cl) + return; + cl->device.type = &hsi_cl; + cl->tx_cfg = info->tx_cfg; + cl->rx_cfg = info->rx_cfg; + cl->device.bus = &hsi_bus_type; + cl->device.parent = &port->device; + cl->device.release = hsi_client_release; + dev_set_name(&cl->device, info->name); + cl->device.platform_data = info->platform_data; + if (info->archdata) + cl->device.archdata = *info->archdata; + if (device_register(&cl->device) < 0) { + pr_err("hsi: failed to register client: %s\n", info->name); + kfree(cl); + } +} + +/** + * hsi_register_board_info - Register HSI clients information + * @info: Array of HSI clients on the board + * @len: Length of the array + * + * HSI clients are statically declared and registered on board files. + * + * HSI clients will be automatically registered to the HSI bus once the + * controller and the port where the clients wishes to attach are registered + * to it. + * + * Return -errno on failure, 0 on success. + */ +int __init hsi_register_board_info(struct hsi_board_info const *info, + unsigned int len) +{ + struct hsi_cl_info *cl_info; + + cl_info = kzalloc(sizeof(*cl_info) * len, GFP_KERNEL); + if (!cl_info) + return -ENOMEM; + + for (; len; len--, info++, cl_info++) { + cl_info->info = *info; + list_add_tail(&cl_info->list, &hsi_board_list); + } + + return 0; +} + +static void hsi_scan_board_info(struct hsi_controller *hsi) +{ + struct hsi_cl_info *cl_info; + struct hsi_port *p; + + list_for_each_entry(cl_info, &hsi_board_list, list) + if (cl_info->info.hsi_id == hsi->id) { + p = hsi_find_port_num(hsi, cl_info->info.port); + if (!p) + continue; + hsi_new_client(p, &cl_info->info); + } +} + +static int hsi_remove_client(struct device *dev, void *data) +{ + device_unregister(dev); + + return 0; +} + +static int hsi_remove_port(struct device *dev, void *data) +{ + device_for_each_child(dev, NULL, hsi_remove_client); + device_unregister(dev); + + return 0; +} + +static void hsi_controller_release(struct device *dev) +{ +} + +static void hsi_port_release(struct device *dev) +{ +} + +/** + * hsi_unregister_controller - Unregister an HSI controller + * @hsi: The HSI controller to register + */ +void hsi_unregister_controller(struct hsi_controller *hsi) +{ + device_for_each_child(&hsi->device, NULL, hsi_remove_port); + device_unregister(&hsi->device); +} +EXPORT_SYMBOL_GPL(hsi_unregister_controller); + +/** + * hsi_register_controller - Register an HSI controller and its ports + * @hsi: The HSI controller to register + * + * Returns -errno on failure, 0 on success. + */ +int hsi_register_controller(struct hsi_controller *hsi) +{ + unsigned int i; + int err; + + hsi->device.type = &hsi_ctrl; + hsi->device.bus = &hsi_bus_type; + hsi->device.release = hsi_controller_release; + err = device_register(&hsi->device); + if (err < 0) + return err; + for (i = 0; i < hsi->num_ports; i++) { + hsi->port[i].device.parent = &hsi->device; + hsi->port[i].device.bus = &hsi_bus_type; + hsi->port[i].device.release = hsi_port_release; + hsi->port[i].device.type = &hsi_port; + err = device_register(&hsi->port[i].device); + if (err < 0) + goto out; + } + /* Populate HSI bus with HSI clients */ + hsi_scan_board_info(hsi); + + return 0; +out: + hsi_unregister_controller(hsi); + + return err; +} +EXPORT_SYMBOL_GPL(hsi_register_controller); + +/** + * hsi_register_client_driver - Register an HSI client to the HSI bus + * @drv: HSI client driver to register + * + * Returns -errno on failure, 0 on success. + */ +int hsi_register_client_driver(struct hsi_client_driver *drv) +{ + drv->driver.bus = &hsi_bus_type; + + return driver_register(&drv->driver); +} +EXPORT_SYMBOL_GPL(hsi_register_client_driver); + +static inline int hsi_dummy_msg(struct hsi_msg *msg) +{ + return 0; +} + +static inline int hsi_dummy_cl(struct hsi_client *cl) +{ + return 0; +} + +/** + * hsi_alloc_controller - Allocate an HSI controller and its ports + * @n_ports: Number of ports on the HSI controller + * @flags: Kernel allocation flags + * + * Return NULL on failure or a pointer to an hsi_controller on success. + */ +struct hsi_controller *hsi_alloc_controller(unsigned int n_ports, gfp_t flags) +{ + struct hsi_controller *hsi; + struct hsi_port *port; + unsigned int i; + + if (!n_ports) + return NULL; + + port = kzalloc(sizeof(*port)*n_ports, flags); + if (!port) + return NULL; + hsi = kzalloc(sizeof(*hsi), flags); + if (!hsi) + goto out; + for (i = 0; i < n_ports; i++) { + dev_set_name(&port[i].device, "port%d", i); + port[i].num = i; + port[i].async = hsi_dummy_msg; + port[i].setup = hsi_dummy_cl; + port[i].flush = hsi_dummy_cl; + port[i].start_tx = hsi_dummy_cl; + port[i].stop_tx = hsi_dummy_cl; + port[i].release = hsi_dummy_cl; + mutex_init(&port[i].lock); + } + hsi->num_ports = n_ports; + hsi->port = port; + + return hsi; +out: + kfree(port); + + return NULL; +} +EXPORT_SYMBOL_GPL(hsi_alloc_controller); + +/** + * hsi_free_controller - Free an HSI controller + * @hsi: Pointer to HSI controller + */ +void hsi_free_controller(struct hsi_controller *hsi) +{ + if (!hsi) + return; + + kfree(hsi->port); + kfree(hsi); +} +EXPORT_SYMBOL_GPL(hsi_free_controller); + +/** + * hsi_free_msg - Free an HSI message + * @msg: Pointer to the HSI message + * + * Client is responsible to free the buffers pointed by the scatterlists. + */ +void hsi_free_msg(struct hsi_msg *msg) +{ + if (!msg) + return; + sg_free_table(&msg->sgt); + kfree(msg); +} +EXPORT_SYMBOL_GPL(hsi_free_msg); + +/** + * hsi_alloc_msg - Allocate an HSI message + * @nents: Number of memory entries + * @flags: Kernel allocation flags + * + * nents can be 0. This mainly makes sense for read transfer. + * In that case, HSI drivers will call the complete callback when + * there is data to be read without consuming it. + * + * Return NULL on failure or a pointer to an hsi_msg on success. + */ +struct hsi_msg *hsi_alloc_msg(unsigned int nents, gfp_t flags) +{ + struct hsi_msg *msg; + int err; + + msg = kzalloc(sizeof(*msg), flags); + if (!msg) + return NULL; + + if (!nents) + return msg; + + err = sg_alloc_table(&msg->sgt, nents, flags); + if (unlikely(err)) { + kfree(msg); + msg = NULL; + } + + return msg; +} +EXPORT_SYMBOL_GPL(hsi_alloc_msg); + +/** + * hsi_async - Submit an HSI transfer to the controller + * @cl: HSI client sending the transfer + * @msg: The HSI transfer passed to controller + * + * The HSI message must have the channel, ttype, complete and destructor + * fields set beforehand. If nents > 0 then the client has to initialize + * also the scatterlists to point to the buffers to write to or read from. + * + * HSI controllers relay on pre-allocated buffers from their clients and they + * do not allocate buffers on their own. + * + * Once the HSI message transfer finishes, the HSI controller calls the + * complete callback with the status and actual_len fields of the HSI message + * updated. The complete callback can be called before returning from + * hsi_async. + * + * Returns -errno on failure or 0 on success + */ +int hsi_async(struct hsi_client *cl, struct hsi_msg *msg) +{ + struct hsi_port *port = hsi_get_port(cl); + + if (!hsi_port_claimed(cl)) + return -EACCES; + + WARN_ON_ONCE(!msg->destructor || !msg->complete); + msg->cl = cl; + + return port->async(msg); +} +EXPORT_SYMBOL_GPL(hsi_async); + +/** + * hsi_claim_port - Claim the HSI client's port + * @cl: HSI client that wants to claim its port + * @share: Flag to indicate if the client wants to share the port or not. + * + * Returns -errno on failure, 0 on success. + */ +int hsi_claim_port(struct hsi_client *cl, unsigned int share) +{ + struct hsi_port *port = hsi_get_port(cl); + int err = 0; + + mutex_lock(&port->lock); + if ((port->claimed) && (!port->shared || !share)) { + err = -EBUSY; + goto out; + } + port->claimed++; + port->shared = !!share; + cl->pclaimed = 1; +out: + mutex_unlock(&port->lock); + + return err; +} +EXPORT_SYMBOL_GPL(hsi_claim_port); + +/** + * hsi_release_port - Release the HSI client's port + * @cl: HSI client which previously claimed its port + */ +void hsi_release_port(struct hsi_client *cl) +{ + struct hsi_port *port = hsi_get_port(cl); + + /* Allow HW driver to do some cleanup */ + port->release(cl); + mutex_lock(&port->lock); + if (cl->pclaimed) + port->claimed--; + BUG_ON(port->claimed < 0); + cl->pclaimed = 0; + if (!port->claimed) + port->shared = 0; + mutex_unlock(&port->lock); +} +EXPORT_SYMBOL_GPL(hsi_release_port); + +static int hsi_start_rx(struct device *dev, void *data) +{ + struct hsi_client *cl = to_hsi_client(dev); + + if (cl->hsi_start_rx) + (*cl->hsi_start_rx)(cl); + + return 0; +} + +static int hsi_stop_rx(struct device *dev, void *data) +{ + struct hsi_client *cl = to_hsi_client(dev); + + if (cl->hsi_stop_rx) + (*cl->hsi_stop_rx)(cl); + + return 0; +} + +/** + * hsi_event -Notifies clients about port events + * @port: Port where the event occurred + * @event: The event type + * + * Clients should not be concerned about wake line behavior. However, due + * to a race condition in HSI HW protocol, clients need to be notified + * about wake line changes, so they can implement a workaround for it. + * + * Events: + * HSI_EVENT_START_RX - Incoming wake line high + * HSI_EVENT_STOP_RX - Incoming wake line down + */ +void hsi_event(struct hsi_port *port, unsigned int event) +{ + int (*fn)(struct device *dev, void *data); + + switch (event) { + case HSI_EVENT_START_RX: + fn = hsi_start_rx; + break; + case HSI_EVENT_STOP_RX: + fn = hsi_stop_rx; + break; + default: + return; + } + device_for_each_child(&port->device, NULL, fn); +} +EXPORT_SYMBOL_GPL(hsi_event); + +static int __init hsi_init(void) +{ + return bus_register(&hsi_bus_type); +} +postcore_initcall(hsi_init); diff --git a/include/linux/hsi/hsi.h b/include/linux/hsi/hsi.h new file mode 100644 index 0000000..8f39c74 --- /dev/null +++ b/include/linux/hsi/hsi.h @@ -0,0 +1,369 @@ +/* + * hsi.h + * + * HSI core header file. + * + * Copyright (C) 2010 Nokia Corporation. All rights reserved. + * + * Contact: Carlos Chinea + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#ifndef __LINUX_HSI_H__ +#define __LINUX_HSI_H__ + +#include +#include +#include + +/* HSI message ttype */ +#define HSI_MSG_READ 0 +#define HSI_MSG_WRITE 1 + +/* HSI configuration values */ +#define HSI_MODE_STREAM 1 +#define HSI_MODE_FRAME 2 +#define HSI_FLOW_SYNC 0 /* Synchronized flow */ +#define HSI_FLOW_PIPE 1 /* Pipelined flow */ +#define HSI_ARB_RR 0 /* Round-robin arbitration */ +#define HSI_ARB_PRIO 1 /* Channel priority arbitration */ + +#define HSI_MAX_CHANNELS 16 + +/* HSI message status codes */ +enum { + HSI_STATUS_COMPLETED, /* Message transfer is completed */ + HSI_STATUS_PENDING, /* Message pending to be read/write (POLL) */ + HSI_STATUS_PROCEDING, /* Message transfer is ongoing */ + HSI_STATUS_QUEUED, /* Message waiting to be served */ + HSI_STATUS_ERROR, /* Error when message transfer was ongoing */ +}; + +/* HSI port event codes */ +enum { + HSI_EVENT_START_RX, + HSI_EVENT_STOP_RX, +}; + +/** + * struct hsi_config - Configuration for RX/TX HSI modules + * @mode: Bit transmission mode (STREAM or FRAME) + * @flow: Flow type (SYNCHRONIZED or PIPELINE) + * @channels: Number of channels to use [1..16] + * @speed: Max bit transmission speed (Kbit/s) + * @arb_mode: Arbitration mode for TX frame (Round robin, priority) + */ +struct hsi_config { + unsigned int mode; + unsigned int flow; + unsigned int channels; + unsigned int speed; + unsigned int arb_mode; /* TX only */ +}; + +/** + * struct hsi_board_info - HSI client board info + * @name: Name for the HSI device + * @hsi_id: HSI controller id where the client sits + * @port: Port number in the controller where the client sits + * @tx_cfg: HSI TX configuration + * @rx_cfg: HSI RX configuration + * @platform_data: Platform related data + * @archdata: Architecture-dependent device data + */ +struct hsi_board_info { + const char *name; + int hsi_id; + unsigned int port; + struct hsi_config tx_cfg; + struct hsi_config rx_cfg; + void *platform_data; + struct dev_archdata *archdata; +}; + +#ifdef CONFIG_HSI +extern int hsi_register_board_info(struct hsi_board_info const *info, + unsigned int len); +#else +static inline int hsi_register_board_info(struct hsi_board_info const *info, + unsigned int len) +{ + return 0; +} +#endif + +/** + * struct hsi_client - HSI client attached to an HSI port + * @device: Driver model representation of the device + * @tx_cfg: HSI TX configuration + * @rx_cfg: HSI RX configuration + * @hsi_start_rx: Called after incoming wake line goes high + * @hsi_stop_rx: Called after incoming wake line goes low + */ +struct hsi_client { + struct device device; + struct hsi_config tx_cfg; + struct hsi_config rx_cfg; + void (*hsi_start_rx)(struct hsi_client *cl); + void (*hsi_stop_rx)(struct hsi_client *cl); + /* private: */ + unsigned int pclaimed:1; +}; + +#define to_hsi_client(dev) container_of(dev, struct hsi_client, device) + +static inline void hsi_client_set_drvdata(struct hsi_client *cl, void *data) +{ + dev_set_drvdata(&cl->device, data); +} + +static inline void *hsi_client_drvdata(struct hsi_client *cl) +{ + return dev_get_drvdata(&cl->device); +} + +/** + * struct hsi_client_driver - Driver associated to an HSI client + * @driver: Driver model representation of the driver + */ +struct hsi_client_driver { + struct device_driver driver; +}; + +#define to_hsi_client_driver(drv) container_of(drv, struct hsi_client_driver,\ + driver) + +int hsi_register_client_driver(struct hsi_client_driver *drv); + +static inline void hsi_unregister_client_driver(struct hsi_client_driver *drv) +{ + driver_unregister(&drv->driver); +} + +/** + * struct hsi_msg - HSI message descriptor + * @link: Free to use by the current descriptor owner + * @cl: HSI device client that issues the transfer + * @sgt: Head of the scatterlist array + * @context: Client context data associated to the transfer + * @complete: Transfer completion callback + * @destructor: Destructor to free resources when flushing + * @status: Status of the transfer when completed + * @actual_len: Actual length of data transfered on completion + * @channel: Channel were to TX/RX the message + * @ttype: Transfer type (TX if set, RX otherwise) + * @break_frame: if true HSI will send/receive a break frame (FRAME MODE) + */ +struct hsi_msg { + struct list_head link; + struct hsi_client *cl; + struct sg_table sgt; + void *context; + + void (*complete)(struct hsi_msg *msg); + void (*destructor)(struct hsi_msg *msg); + + int status; + unsigned int actual_len; + unsigned int channel; + unsigned int ttype:1; + unsigned int break_frame:1; +}; + +struct hsi_msg *hsi_alloc_msg(unsigned int n_frag, gfp_t flags); +void hsi_free_msg(struct hsi_msg *msg); + +/** + * struct hsi_port - HSI port device + * @device: Driver model representation of the device + * @tx_cfg: Current TX path configuration + * @rx_cfg: Current RX path configuration + * @num: Port number + * @shared: Set when port can be shared by different clients + * @claimed: Reference count of clients which claimed the port + * @lock: Serialize port claim + * @async: Asynchronous transfer callback + * @setup: Callback to set the HSI client configuration + * @flush: Callback to clean the HW state and destroy all pending transfers + * @start_tx: Callback to inform that a client wants to TX data + * @stop_tx: Callback to inform that a client no longer wishes to TX data + * @release: Callback to inform that a client no longer uses the port + */ +struct hsi_port { + struct device device; + struct hsi_config tx_cfg; + struct hsi_config rx_cfg; + unsigned int num; + unsigned int shared:1; + int claimed; + struct mutex lock; + int (*async)(struct hsi_msg *msg); + int (*setup)(struct hsi_client *cl); + int (*flush)(struct hsi_client *cl); + int (*start_tx)(struct hsi_client *cl); + int (*stop_tx)(struct hsi_client *cl); + int (*release)(struct hsi_client *cl); +}; + +#define to_hsi_port(dev) container_of(dev, struct hsi_port, device) +#define hsi_get_port(cl) to_hsi_port((cl)->device.parent) + +void hsi_event(struct hsi_port *port, unsigned int event); +int hsi_claim_port(struct hsi_client *cl, unsigned int share); +void hsi_release_port(struct hsi_client *cl); + +static inline int hsi_port_claimed(struct hsi_client *cl) +{ + return cl->pclaimed; +} + +static inline void hsi_port_set_drvdata(struct hsi_port *port, void *data) +{ + dev_set_drvdata(&port->device, data); +} + +static inline void *hsi_port_drvdata(struct hsi_port *port) +{ + return dev_get_drvdata(&port->device); +} + +/** + * struct hsi_controller - HSI controller device + * @device: Driver model representation of the device + * @id: HSI controller ID + * @num_ports: Number of ports in the HSI controller + * @port: Array of HSI ports + */ +struct hsi_controller { + struct device device; + int id; + unsigned int num_ports; + struct hsi_port *port; +}; + +#define to_hsi_controller(dev) container_of(dev, struct hsi_controller, device) + +struct hsi_controller *hsi_alloc_controller(unsigned int n_ports, gfp_t flags); +void hsi_free_controller(struct hsi_controller *hsi); +int hsi_register_controller(struct hsi_controller *hsi); +void hsi_unregister_controller(struct hsi_controller *hsi); + +static inline void hsi_controller_set_drvdata(struct hsi_controller *hsi, + void *data) +{ + dev_set_drvdata(&hsi->device, data); +} + +static inline void *hsi_controller_drvdata(struct hsi_controller *hsi) +{ + return dev_get_drvdata(&hsi->device); +} + +static inline struct hsi_port *hsi_find_port_num(struct hsi_controller *hsi, + unsigned int num) +{ + return (num < hsi->num_ports) ? &hsi->port[num] : NULL; +} + +/* + * API for HSI clients + */ +int hsi_async(struct hsi_client *cl, struct hsi_msg *msg); + +/** + * hsi_setup - Configure the client's port + * @cl: Pointer to the HSI client + * + * When sharing ports, clients should either relay on a single + * client setup or have the same setup for all of them. + * + * Return -errno on failure, 0 on success + */ +static inline int hsi_setup(struct hsi_client *cl) +{ + if (!hsi_port_claimed(cl)) + return -EACCES; + return hsi_get_port(cl)->setup(cl); +} + +/** + * hsi_flush - Flush all pending transactions on the client's port + * @cl: Pointer to the HSI client + * + * This function will destroy all pending hsi_msg in the port and reset + * the HW port so it is ready to receive and transmit from a clean state. + * + * Return -errno on failure, 0 on success + */ +static inline int hsi_flush(struct hsi_client *cl) +{ + if (!hsi_port_claimed(cl)) + return -EACCES; + return hsi_get_port(cl)->flush(cl); +} + +/** + * hsi_async_read - Submit a read transfer + * @cl: Pointer to the HSI client + * @msg: HSI message descriptor of the transfer + * + * Return -errno on failure, 0 on success + */ +static inline int hsi_async_read(struct hsi_client *cl, struct hsi_msg *msg) +{ + msg->ttype = HSI_MSG_READ; + return hsi_async(cl, msg); +} + +/** + * hsi_async_write - Submit a write transfer + * @cl: Pointer to the HSI client + * @msg: HSI message descriptor of the transfer + * + * Return -errno on failure, 0 on success + */ +static inline int hsi_async_write(struct hsi_client *cl, struct hsi_msg *msg) +{ + msg->ttype = HSI_MSG_WRITE; + return hsi_async(cl, msg); +} + +/** + * hsi_start_tx - Signal the port that the client wants to start a TX + * @cl: Pointer to the HSI client + * + * Return -errno on failure, 0 on success + */ +static inline int hsi_start_tx(struct hsi_client *cl) +{ + if (!hsi_port_claimed(cl)) + return -EACCES; + return hsi_get_port(cl)->start_tx(cl); +} + +/** + * hsi_stop_tx - Signal the port that the client no longer wants to transmit + * @cl: Pointer to the HSI client + * + * Return -errno on failure, 0 on success + */ +static inline int hsi_stop_tx(struct hsi_client *cl) +{ + if (!hsi_port_claimed(cl)) + return -EACCES; + return hsi_get_port(cl)->stop_tx(cl); +} +#endif /* __LINUX_HSI_H__ */ From patchwork Tue May 11 14:15:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 98720 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4BEDnGl022508 for ; Tue, 11 May 2010 14:13:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758180Ab0EKOMp (ORCPT ); Tue, 11 May 2010 10:12:45 -0400 Received: from smtp.nokia.com ([192.100.122.233]:50760 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758104Ab0EKOMl (ORCPT ); Tue, 11 May 2010 10:12:41 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4BEC9nd013849; Tue, 11 May 2010 17:12:23 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 11 May 2010 17:12:09 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 11 May 2010 17:12:08 +0300 Received: from manganga.research.nokia.com (esdhcp04199.research.nokia.com [172.21.41.99]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4BEC3sQ027143; Tue, 11 May 2010 17:12:07 +0300 From: Eduardo Valentin To: LKML , linux-arm-kernel@lists.infradead.org, Linux-OMAP Cc: Russell King , Andrew Morton , ext Tony Lindgren , ext Kevin Hilman , Peter De-Schrijver , santosh.shilimkar@ti.com, Ambresh , felipe.balbi@nokia.com, Jouni Hogander , Paul Mundt , Eduardo Valentin Subject: [PATCHv5 2/3] OMAP: export OMAP info under /proc/socinfo Date: Tue, 11 May 2010 17:15:30 +0300 Message-Id: <1273587331-24604-3-git-send-email-eduardo.valentin@nokia.com> X-Mailer: git-send-email 1.7.0.4.361.g8b5fe.dirty In-Reply-To: <1273587331-24604-1-git-send-email-eduardo.valentin@nokia.com> References: <1273587331-24604-1-git-send-email-eduardo.valentin@nokia.com> X-OriginalArrivalTime: 11 May 2010 14:12:08.0954 (UTC) FILETIME=[F15CBDA0:01CAF113] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 11 May 2010 14:13:49 +0000 (UTC) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 92622eb..fbd3c50 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -326,6 +326,7 @@ config ARCH_EP93XX select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_HOLES_MEMORYMODEL + select PROC_SOC_INFO help This enables support for the Cirrus EP93xx series of CPUs. diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index a0e3560..ef3caf1 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #define OMAP_DIE_ID_0 0xfffe1800 @@ -118,9 +120,21 @@ static u8 __init omap_get_die_rev(void) return die_rev; } +#define SOCINFO_SZ 128 + +static int omap1_socinfo_show(struct seq_file *m, void *v) +{ + char *socinfo = v; + + seq_printf(m, "SoC\t: %s\n", socinfo); + + return 0; +} + void __init omap_check_revision(void) { - int i; + int i, sz; + char socinfo[SOCINFO_SZ]; u16 jtag_id; u8 die_rev; u32 omap_id; @@ -194,11 +208,14 @@ void __init omap_check_revision(void) printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type); } - printk(KERN_INFO "OMAP%04x", omap_revision >> 16); + sz = snprintf(socinfo, SOCINFO_SZ, "OMAP%04x", omap_revision >> 16); if ((omap_revision >> 8) & 0xff) - printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff); - printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n", - die_rev, omap_revision & 0xff, system_serial_low, - system_serial_high); + snprintf(socinfo + sz, SOCINFO_SZ - sz, "%x", + (omap_revision >> 8) & 0xff); + pr_info("%s revision %i handled as %02xxx id: %08x%08x\n", + socinfo, die_rev, omap_revision & 0xff, system_serial_low, + system_serial_high); + + /* register function to show SoC info under /proc/socinfo */ + register_socinfo_show(omap1_socinfo_show, kstrdup(socinfo, GFP_KERNEL)); } - diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a..b67486b 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include @@ -101,10 +103,12 @@ static struct omap_id omap_ids[] __initdata = { static void __iomem *tap_base; static u16 tap_prod_id; +#define SOCINFO_SZ 128 +static char socinfo[SOCINFO_SZ]; void __init omap24xx_check_revision(void) { - int i, j; + int i, j, sz; u32 idcode, prod_id; u16 hawkeye; u8 dev_type, rev; @@ -152,10 +156,11 @@ void __init omap24xx_check_revision(void) j = i; } - pr_info("OMAP%04x", omap_rev() >> 16); + sz = snprintf(socinfo, SOCINFO_SZ, "OMAP%04x", omap_rev() >> 16); if ((omap_rev() >> 8) & 0x0f) - pr_info("ES%x", (omap_rev() >> 12) & 0xf); - pr_info("\n"); + snprintf(socinfo + sz, SOCINFO_SZ - sz, "ES%x", + (omap_rev() >> 12) & 0xf); + pr_info("%s\n", socinfo); } #define OMAP3_CHECK_FEATURE(status,feat) \ @@ -286,7 +291,9 @@ void __init omap4_check_revision(void) if ((hawkeye == 0xb852) && (rev == 0x0)) { omap_revision = OMAP4430_REV_ES1_0; omap_chip.oc |= CHIP_IS_OMAP4430ES1; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); + snprintf(socinfo, SOCINFO_SZ, "OMAP%04x %s\n", + omap_rev() >> 16, rev_name); + pr_info("%s\n", socinfo); return; } @@ -356,7 +363,8 @@ void __init omap3_cpuinfo(void) } /* Print verbose information */ - pr_info("%s ES%s (", cpu_name, cpu_rev); + snprintf(socinfo, SOCINFO_SZ, "%s ES%s", cpu_name, cpu_rev); + pr_info("%s (", socinfo); OMAP3_SHOW_FEATURE(l2cache); OMAP3_SHOW_FEATURE(iva); @@ -368,6 +376,15 @@ void __init omap3_cpuinfo(void) printk(")\n"); } +static int omap_socinfo_show(struct seq_file *m, void *v) +{ + char *socinfop = v; + + seq_printf(m, "SoC\t: %s\n", socinfop); + + return 0; +} + /* * Try to detect the exact revision of the omap we're running on */ @@ -391,6 +408,9 @@ void __init omap2_check_revision(void) pr_err("OMAP revision unknown, please fix!\n"); } + /* also register call back to report SoC data under /proc/socinfo */ + register_socinfo_show(omap_socinfo_show, socinfo); + /* * OK, now we know the exact revision. Initialize omap_chip bits * for powerdowmain and clockdomain code. From patchwork Wed Jul 14 11:22:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 111934 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6EBP5V0015079 for ; Wed, 14 Jul 2010 11:25:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754787Ab0GNLZD (ORCPT ); Wed, 14 Jul 2010 07:25:03 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:41766 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753565Ab0GNLZB (ORCPT ); Wed, 14 Jul 2010 07:25:01 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6EBOndN010996 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 14 Jul 2010 06:24:51 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6EBOkaN013323; Wed, 14 Jul 2010 16:54:47 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Kevin Hilman Subject: [PATCH] OMAP1: PM: Fix OMAP1610 build Date: Wed, 14 Jul 2010 16:52:25 +0530 Message-Id: <1279106545-3018-1-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 14 Jul 2010 11:25:06 +0000 (UTC) diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index 29d651a..6c5ab40 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include @@ -23,6 +25,7 @@ int platform_pm_runtime_suspend(struct device *dev) { struct clk *iclk, *fclk; + int ret = 0; dev_dbg(dev, "%s\n", __func__); @@ -46,7 +49,7 @@ int platform_pm_runtime_suspend(struct device *dev) int platform_pm_runtime_resume(struct device *dev) { - int r, ret = 0; + int ret = 0; struct clk *iclk, *fclk; iclk = clk_get(dev, "ick"); @@ -69,6 +72,7 @@ int platform_pm_runtime_resume(struct device *dev) int platform_pm_runtime_idle(struct device *dev) { + int ret = 0; ret = pm_runtime_suspend(dev); dev_dbg(dev, "%s [%d]\n", __func__, ret); From patchwork Fri Jul 30 04:46:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 115394 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6U4mFZQ028714 for ; Fri, 30 Jul 2010 04:48:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751952Ab0G3EsP (ORCPT ); Fri, 30 Jul 2010 00:48:15 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:55223 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751742Ab0G3EsO (ORCPT ); Fri, 30 Jul 2010 00:48:14 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6U4m84u013604 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Jul 2010 23:48:10 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6U4m2ac001211; Fri, 30 Jul 2010 10:18:03 +0530 (IST) From: Manjunatha GK To: linux-omap@vger.kernel.org Cc: Venkatraman S , Benoit Cousson , Kevin Hilman , Paul Walmsley , Tony Lindgren , Anand Sawant , Santosh Shilimkar , Rajendra Nayak , Basak Partha , Charulatha V Subject: [PATCH resend 11/11] sDMA: descriptor autoloading feature Date: Fri, 30 Jul 2010 10:16:14 +0530 Message-Id: <1280465174-10928-1-git-send-email-manjugk@ti.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 30 Jul 2010 04:48:16 +0000 (UTC) diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index eadc160..1f10f62 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -304,6 +304,11 @@ void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) } EXPORT_SYMBOL(omap_dma_set_global_params); +void omap_clear_dma_sglist_mode(int lch) +{ + return; +} + static int __init omap1_system_dma_init(void) { struct platform_device *pdev; diff --git a/arch/arm/mach-omap1/include/mach/dma.h b/arch/arm/mach-omap1/include/mach/dma.h index 1eb0d31..afe486b 100644 --- a/arch/arm/mach-omap1/include/mach/dma.h +++ b/arch/arm/mach-omap1/include/mach/dma.h @@ -143,4 +143,6 @@ struct omap_dma_lch { long flags; }; +/* Dummy function */ +extern void omap_clear_dma_sglist_mode(int lch); #endif /* __ASM_ARCH_OMAP1_DMA_H */ diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 390c428..c24ed00 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -204,6 +204,77 @@ static void dma_ocpsysconfig_errata(u32 *sys_cf, bool flag) dma_write(*sys_cf, OCP_SYSCONFIG); } +static inline void omap_dma_list_set_ntype(struct omap_dma_sglist_node *node, + int value) +{ + node->num_of_elem |= ((value) << 29); +} + +static void omap_set_dma_sglist_pausebit( + struct omap_dma_list_config_params *lcfg, int nelem, int set) +{ + struct omap_dma_sglist_node *sgn = lcfg->sghead; + + if (nelem > 0 && nelem < lcfg->num_elem) { + lcfg->pausenode = nelem; + sgn += nelem; + + if (set) + sgn->next_desc_add_ptr |= DMA_LIST_DESC_PAUSE; + else + sgn->next_desc_add_ptr &= ~(DMA_LIST_DESC_PAUSE); + } +} + +static int dma_sglist_set_phy_params(struct omap_dma_sglist_node *sghead, + dma_addr_t phyaddr, int nelem) +{ + struct omap_dma_sglist_node *sgcurr, *sgprev; + dma_addr_t elem_paddr = phyaddr; + + for (sgprev = sghead; + sgprev < sghead + nelem; + sgprev++) { + + sgcurr = sgprev + 1; + sgprev->next = sgcurr; + elem_paddr += (int)sizeof(*sgcurr); + sgprev->next_desc_add_ptr = elem_paddr; + + switch (sgcurr->desc_type) { + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE1: + omap_dma_list_set_ntype(sgprev, 1); + break; + + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2a: + /* intentional no break */ + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2b: + omap_dma_list_set_ntype(sgprev, 2); + break; + + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3a: + /* intentional no break */ + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3b: + omap_dma_list_set_ntype(sgprev, 3); + break; + + default: + return -EINVAL; + + } + if (sgcurr->flags & OMAP_DMA_LIST_SRC_VALID) + sgprev->num_of_elem |= DMA_LIST_DESC_SRC_VALID; + if (sgcurr->flags & OMAP_DMA_LIST_DST_VALID) + sgprev->num_of_elem |= DMA_LIST_DESC_DST_VALID; + if (sgcurr->flags & OMAP_DMA_LIST_NOTIFY_BLOCK_END) + sgprev->num_of_elem |= DMA_LIST_DESC_BLK_END; + } + sgprev--; + sgprev->next_desc_add_ptr = OMAP_DMA_INVALID_DESCRIPTOR_POINTER; + return 0; +} + + void omap_dma_global_context_save(void) { omap_dma_global_context.dma_irqenable_l0 = @@ -861,6 +932,189 @@ void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) } EXPORT_SYMBOL(omap_set_dma_write_mode); +int omap_set_dma_sglist_mode(int lch, struct omap_dma_sglist_node *sgparams, + dma_addr_t padd, int nelem, struct omap_dma_channel_params *chparams) +{ + struct omap_dma_list_config_params *lcfg; + int l = DMA_LIST_CDP_LISTMODE; /* Enable Linked list mode in CDP */ + + if ((dma_caps0_status & DMA_CAPS_SGLIST_SUPPORT) == 0) { + printk(KERN_ERR "omap DMA: sglist feature not supported\n"); + return -EPERM; + } + if (dma_chan[lch].flags & OMAP_DMA_ACTIVE) { + printk(KERN_ERR "omap DMA: configuring active DMA channel\n"); + return -EPERM; + } + + if (padd == 0) { + printk(KERN_ERR "omap DMA: sglist invalid dma_addr\n"); + return -EINVAL; + } + lcfg = &dma_chan[lch].list_config; + + lcfg->sghead = sgparams; + lcfg->num_elem = nelem; + lcfg->sgheadphy = padd; + lcfg->pausenode = -1; + + + if (NULL == chparams) + l |= DMA_LIST_CDP_FASTMODE; + else + omap_set_dma_params(lch, chparams); + + dma_write(l, CDP(lch)); + dma_write(0, CCDN(lch)); /* Reset List index numbering */ + /* Initialize frame and element counters to invalid values */ + dma_write(OMAP_DMA_INVALID_FRAME_COUNT, CCFN(lch)); + dma_write(OMAP_DMA_INVALID_ELEM_COUNT, CCEN(lch)); + + return dma_sglist_set_phy_params(sgparams, lcfg->sgheadphy, nelem); + +} +EXPORT_SYMBOL(omap_set_dma_sglist_mode); + +void omap_clear_dma_sglist_mode(int lch) +{ + /* Clear entire CDP which is related to sglist handling */ + dma_write(0, CDP(lch)); + dma_write(0, CCDN(lch)); + /** + * Put back the original enabled irqs, which + * could have been overwritten by type 1 or type 2 + * descriptors + */ + dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); + return; +} +EXPORT_SYMBOL(omap_clear_dma_sglist_mode); + +int omap_start_dma_sglist_transfers(int lch, int pauseafter) +{ + struct omap_dma_list_config_params *lcfg; + struct omap_dma_sglist_node *sgn; + unsigned int l, type_id; + + lcfg = &dma_chan[lch].list_config; + sgn = lcfg->sghead; + + lcfg->pausenode = 0; + omap_set_dma_sglist_pausebit(lcfg, pauseafter, 1); + + /* Program the head descriptor's properties into CDP */ + switch (lcfg->sghead->desc_type) { + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE1: + type_id = DMA_LIST_CDP_TYPE1; + break; + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2a: + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2b: + type_id = DMA_LIST_CDP_TYPE2; + break; + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3a: + case OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3b: + type_id = DMA_LIST_CDP_TYPE3; + break; + default: + return -EINVAL; + } + + l = dma_read(CDP(lch)); + l |= type_id; + if (lcfg->sghead->flags & OMAP_DMA_LIST_SRC_VALID) + l |= DMA_LIST_CDP_SRC_VALID; + if (lcfg->sghead->flags & OMAP_DMA_LIST_DST_VALID) + l |= DMA_LIST_CDP_DST_VALID; + + dma_write(l, CDP(lch)); + dma_write((lcfg->sgheadphy), CNDP(lch)); + /** + * Barrier needed as writes to the + * descriptor memory needs to be flushed + * before it's used by DMA controller + */ + wmb(); + omap_start_dma(lch); + + return 0; +} +EXPORT_SYMBOL(omap_start_dma_sglist_transfers); + +int omap_resume_dma_sglist_transfers(int lch, int pauseafter) +{ + struct omap_dma_list_config_params *lcfg; + struct omap_dma_sglist_node *sgn; + int l, get_sysconfig; + + lcfg = &dma_chan[lch].list_config; + sgn = lcfg->sghead; + + /* Maintain the pause state in descriptor */ + omap_set_dma_sglist_pausebit(lcfg, lcfg->pausenode, 0); + omap_set_dma_sglist_pausebit(lcfg, pauseafter, 1); + + /** + * Barrier needed as writes to the + * descriptor memory needs to be flushed + * before it's used by DMA controller + */ + wmb(); + + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, false); + + /* Clear pause bit in CDP */ + l = dma_read(CDP(lch)); + l &= ~(DMA_LIST_CDP_PAUSEMODE); + dma_write(l, CDP(lch)); + + omap_start_dma(lch); + + if (p->errata & DMA_SYSCONFIG_ERRATA) + dma_ocpsysconfig_errata(&get_sysconfig, true); + + return 0; +} +EXPORT_SYMBOL(omap_resume_dma_sglist_transfers); + +void omap_release_dma_sglist(int lch) +{ + omap_clear_dma_sglist_mode(lch); + omap_free_dma(lch); + + return; +} +EXPORT_SYMBOL(omap_release_dma_sglist); + +int omap_get_completed_sglist_nodes(int lch) +{ + int list_count; + + list_count = dma_read(CCDN(lch)); + return list_count & 0xffff; /* only 16 LSB bits are valid */ +} +EXPORT_SYMBOL(omap_get_completed_sglist_nodes); + +int omap_dma_sglist_is_paused(int lch) +{ + int list_state; + list_state = dma_read(CDP(lch)); + return (list_state & DMA_LIST_CDP_PAUSEMODE) ? 1 : 0; +} +EXPORT_SYMBOL(omap_dma_sglist_is_paused); + +void omap_dma_set_sglist_fastmode(int lch, int fastmode) +{ + int l = dma_read(CDP(lch)); + + if (fastmode) + l |= DMA_LIST_CDP_FASTMODE; + else + l &= ~(DMA_LIST_CDP_FASTMODE); + dma_write(l, CDP(lch)); +} +EXPORT_SYMBOL(omap_dma_set_sglist_fastmode); + static int omap2_dma_handle_ch(int ch) { u32 status = dma_read(CSR(ch)); diff --git a/arch/arm/mach-omap2/include/mach/dma.h b/arch/arm/mach-omap2/include/mach/dma.h index f3e21d5..e039ea4 100644 --- a/arch/arm/mach-omap2/include/mach/dma.h +++ b/arch/arm/mach-omap2/include/mach/dma.h @@ -143,6 +143,112 @@ #define OMAP_DMA4_GSCR 0 #define OMAP1_DMA_REVISION 0 +/* CDP Register bitmaps */ +#define DMA_LIST_CDP_DST_VALID (BIT(0)) +#define DMA_LIST_CDP_SRC_VALID (BIT(2)) +#define DMA_LIST_CDP_TYPE1 (BIT(4)) +#define DMA_LIST_CDP_TYPE2 (BIT(5)) +#define DMA_LIST_CDP_TYPE3 (BIT(4) | BIT(5)) +#define DMA_LIST_CDP_PAUSEMODE (BIT(7)) +#define DMA_LIST_CDP_LISTMODE (BIT(8)) +#define DMA_LIST_CDP_FASTMODE (BIT(10)) +/* CAPS register bitmaps */ +#define DMA_CAPS_SGLIST_SUPPORT (BIT(20)) + +#define DMA_LIST_DESC_PAUSE (BIT(0)) +#define DMA_LIST_DESC_SRC_VALID (BIT(24)) +#define DMA_LIST_DESC_DST_VALID (BIT(26)) +#define DMA_LIST_DESC_BLK_END (BIT(28)) + +#define OMAP_DMA_INVALID_FRAME_COUNT (0xffff) +#define OMAP_DMA_INVALID_ELEM_COUNT (0xffffff) +#define OMAP_DMA_INVALID_DESCRIPTOR_POINTER (0xfffffffc) + +struct omap_dma_list_config_params { + unsigned int num_elem; + struct omap_dma_sglist_node *sghead; + dma_addr_t sgheadphy; + unsigned int pausenode; +}; + +struct omap_dma_sglist_type1_params { + u32 src_addr; + u32 dst_addr; + u16 cfn_fn; + u16 cicr; + u16 dst_elem_idx; + u16 src_elem_idx; + u32 dst_frame_idx_or_pkt_size; + u32 src_frame_idx_or_pkt_size; + u32 color; + u32 csdp; + u32 clnk_ctrl; + u32 ccr; +}; + +struct omap_dma_sglist_type2a_params { + u32 src_addr; + u32 dst_addr; + u16 cfn_fn; + u16 cicr; + u16 dst_elem_idx; + u16 src_elem_idx; + u32 dst_frame_idx_or_pkt_size; + u32 src_frame_idx_or_pkt_size; +}; + +struct omap_dma_sglist_type2b_params { + u32 src_or_dest_addr; + u16 cfn_fn; + u16 cicr; + u16 dst_elem_idx; + u16 src_elem_idx; + u32 dst_frame_idx_or_pkt_size; + u32 src_frame_idx_or_pkt_size; +}; + +struct omap_dma_sglist_type3a_params { + u32 src_addr; + u32 dst_addr; +}; + +struct omap_dma_sglist_type3b_params { + u32 src_or_dest_addr; +}; + +enum omap_dma_sglist_descriptor_select { + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE1, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2a, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE2b, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3a, + OMAP_DMA_SGLIST_DESCRIPTOR_TYPE3b, +}; + +union omap_dma_sglist_node_type{ + struct omap_dma_sglist_type1_params t1; + struct omap_dma_sglist_type2a_params t2a; + struct omap_dma_sglist_type2b_params t2b; + struct omap_dma_sglist_type3a_params t3a; + struct omap_dma_sglist_type3b_params t3b; +}; + +struct omap_dma_sglist_node { + + /* Common elements for all descriptors */ + dma_addr_t next_desc_add_ptr; + u32 num_of_elem; + /* Type specific elements */ + union omap_dma_sglist_node_type sg_node; + /* Control fields */ + unsigned short flags; + /* Fields that can be set in flags variable */ + #define OMAP_DMA_LIST_SRC_VALID BIT(0) + #define OMAP_DMA_LIST_DST_VALID BIT(1) + #define OMAP_DMA_LIST_NOTIFY_BLOCK_END BIT(2) + enum omap_dma_sglist_descriptor_select desc_type; + struct omap_dma_sglist_node *next; +}; + struct omap_dma_lch { int next_lch; int dev_id; @@ -158,8 +264,96 @@ struct omap_dma_lch { int state; int chain_id; int status; + struct omap_dma_list_config_params list_config; }; +/** + * omap_set_dma_sglist_mode() Switch channel to scatter gather mode + * @lch: Logical channel to switch to sglist mode + * @sghead: Contains the descriptor elements to be executed + * Should be allocated using dma_alloc_coherent + * @padd: The dma address of sghead, as returned by dma_alloc_coherent + * @nelem: Number of elements in sghead + * @chparams: DMA channel transfer parameters. Can be NULL + */ +extern int omap_set_dma_sglist_mode(int lch, + struct omap_dma_sglist_node *sghead, dma_addr_t padd, + int nelem, struct omap_dma_channel_params *chparams); + +/** + * omap_clear_dma_sglist_mode() Switch from scatter gather mode + * to normal mode + * @lch: The logical channel to be switched to normal mode + * + * Switches the requested logical channel to normal mode + * from scatter gather mode + */ +extern void omap_clear_dma_sglist_mode(int lch); + +/** + * omap_start_dma_sglist_transfers() Starts the sglist transfer + * @lch: logical channel on which sglist transfer to be started + * @pauseafter: index of the element on which to pause the transfer + * set to -1 if no pause is needed till end of transfer + * + * Start the dma transfer in list mode + * The index (in pauseafter) is absolute (from the head of the list) + * User should have previously called omap_set_dma_sglist_mode() + */ +extern int omap_start_dma_sglist_transfers(int lch, int pauseafter); + +/** + * omap_resume_dma_sglist_transfers() Resumes a previously paused + * sglist transfer + * @lch: The logical channel to be resumed + * @pauseafter: The index of sglist to be paused again + * set to -1 if no pause is needed till end of transfer + * + * Resume the previously paused transfer + * The index (in pauseafter) is absolute (from the head of the list) + */ +extern int omap_resume_dma_sglist_transfers(int lch, int pauseafter); + +/** + * omap_release_dma_sglist() Releases a previously requested + * DMA channel which is in sglist mode + * @lch: The logical channel to be released + */ +extern void omap_release_dma_sglist(int lch); + +/** + * omap_get_completed_sglist_nodes() Returns a list of completed + * sglist nodes + * @lch: The logical on which the query is to be made + * + * Returns the number of completed elements in the linked list + * The value is transient if the API is invoked for an ongoing transfer + */ +int omap_get_completed_sglist_nodes(int lch); + +/** + * omap_dma_sglist_is_paused() Query is the logical channel in + * sglist mode is paused or note + * @lch: The logical on which the query is to be made + * + * Returns non zero if the linked list is currently in pause state + */ +int omap_dma_sglist_is_paused(int lch); + +/** + * omap_dma_set_sglist_fastmode() Set the sglist transfer to fastmode + * @lch: The logical channel which is to be changed to fastmode + * @fastmode: Set or clear the fastmode status + * 1 = set fastmode + * 0 = clear fastmode + * + * In fastmode, DMA register settings are updated from the first element + * of the linked list, before initiating the tranfer. + * In non-fastmode, the first element is used only after completing the + * transfer as already configured in the registers + */ +void omap_dma_set_sglist_fastmode(int lch, int fastmode); + /* Chaining APIs */ extern int omap_request_dma_chain(int dev_id, const char *dev_name, void (*callback) (int lch, u16 ch_status, diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 643f538..daac49c 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -543,6 +543,7 @@ void omap_free_dma(int lch) /* Make sure the DMA transfer is stopped. */ dma_write(0, CCR(lch)); omap_clear_dma(lch); + omap_clear_dma_sglist_mode(lch); } spin_lock_irqsave(&dma_chan_lock, flags); From patchwork Sun May 2 15:58:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 96366 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o42Fx8FH004954 for ; Sun, 2 May 2010 15:59:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757235Ab0EBP7H (ORCPT ); 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Sun, 02 May 2010 08:58:59 -0700 (PDT) Received: by 10.204.60.78 with HTTP; Sun, 2 May 2010 08:58:59 -0700 (PDT) In-Reply-To: <0BA15D46-D494-4402-9EC8-574AD5D7BAE8@dominion.thruhere.net> References: <1271924622-21043-1-git-send-email-koen@dominion.thruhere.net> <0BA15D46-D494-4402-9EC8-574AD5D7BAE8@dominion.thruhere.net> Date: Sun, 2 May 2010 18:58:59 +0300 Message-ID: Subject: Re: [PATCH v9] board-omap3-beagle: add DSS2 support From: Felipe Contreras To: Koen Kooi Cc: "linux-omap@vger.kernel.org List" , Tomi Valkeinen , Tony Lindgren Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 02 May 2010 15:59:09 +0000 (UTC) --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -39,11 +39,11 @@ #include #include -#include #include #include #include #include +#include #include "mux.h" #include "mmc-twl4030.h" @@ -169,6 +169,10 @@ static void __init beagle_display_init(void) { int r; +#if 0 + /* is this really needed? */ + omap_mux_init_gpio(beagle_dvi_device.reset_gpio, OMAP_PIN_INPUT); +#endif r = gpio_request(beagle_dvi_device.reset_gpio, "DVI reset"); if (r < 0) { printk(KERN_ERR "Unable to get DVI reset GPIO\n"); @@ -279,6 +283,7 @@ static struct regulator_init_data beagle_vdac = { .constraints = { .min_uV = 1800000, .max_uV = 1800000, + .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE @@ -414,9 +419,9 @@ static void __init omap3_beagle_init_irq(void) } static struct platform_device *omap3_beagle_devices[] __initdata = { + &beagle_dss_device, &leds_gpio, &keys_gpio, - &beagle_dss_device, }; static void __init omap3beagle_flash_init(void) @@ -485,20 +490,14 @@ static void __init omap3_beagle_init(void) ARRAY_SIZE(omap3_beagle_devices)); omap_serial_init(); - omap_mux_init_gpio(170, OMAP_PIN_INPUT); - gpio_request(170, "DVI_nPD"); - /* REVISIT leave DVI powered down until it's needed ... */ - gpio_direction_output(170, true); - usb_musb_init(); usb_ehci_init(&ehci_pdata); omap3beagle_flash_init(); + beagle_display_init(); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); - - beagle_display_init(); } static void __init omap3_beagle_map_io(void) From patchwork Thu May 6 01:15:45 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Candelaria Villareal, Jorge" X-Patchwork-Id: 97251 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o461QdmG005057 for ; Thu, 6 May 2010 01:26:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753041Ab0EFB0i (ORCPT ); Wed, 5 May 2010 21:26:38 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:40771 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752131Ab0EFB0h (ORCPT ); Wed, 5 May 2010 21:26:37 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o461QaAT013509 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 5 May 2010 20:26:37 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o461QZLS018108; Wed, 5 May 2010 20:26:36 -0500 (CDT) Received: from localhost.localdomain (x0107209-ubuntu.sasken-mty.naucm.ext.ti.com [10.87.231.217]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o461QZVY018668; Wed, 5 May 2010 20:26:35 -0500 (CDT) From: Jorge Eduardo Candelaria To: linux-omap@vger.kernel.org Cc: Jorge Eduardo Candelaria Subject: [PATCH v2 1/2] ARM: McBSP: Fix request for irq in OMAP4 Date: Wed, 5 May 2010 20:15:45 -0500 Message-Id: <1273108546-2507-2-git-send-email-jorge.candelaria@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1273108546-2507-1-git-send-email-jorge.candelaria@ti.com> References: <1273108546-2507-1-git-send-email-jorge.candelaria@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 06 May 2010 01:26:42 +0000 (UTC) diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 2f3cad6..c293370 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -187,32 +187,28 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .phys_base = OMAP44XX_MCBSP1_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP1, .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP2, .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP3, .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + .tx_irq = OMAP44XX_IRQ_MCBSP4, .ops = &omap2_mcbsp_ops, }, }; diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e1d0440..6696eb6 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -724,14 +724,17 @@ int omap_mcbsp_request(unsigned int id) goto err_clk_disable; } - init_completion(&mcbsp->rx_irq_completion); - err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, + if (mcbsp->rx_irq) { + init_completion(&mcbsp->rx_irq_completion); + err = request_irq(mcbsp->rx_irq, + omap_mcbsp_rx_irq_handler, 0, "McBSP", (void *)mcbsp); - if (err != 0) { - dev_err(mcbsp->dev, "Unable to request RX IRQ %d " - "for McBSP%d\n", mcbsp->rx_irq, - mcbsp->id); - goto err_free_irq; + if (err != 0) { + dev_err(mcbsp->dev, "Unable to request RX IRQ %d " + "for McBSP%d\n", mcbsp->rx_irq, + mcbsp->id); + goto err_free_irq; + } } } @@ -781,7 +784,8 @@ void omap_mcbsp_free(unsigned int id) if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { /* Free IRQs */ - free_irq(mcbsp->rx_irq, (void *)mcbsp); + if (mcbsp->rx_irq) + free_irq(mcbsp->rx_irq, (void *)mcbsp); free_irq(mcbsp->tx_irq, (void *)mcbsp); } From patchwork Fri Jun 11 15:51:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 105608 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5BFqQMa023673 for ; Fri, 11 Jun 2010 15:52:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757482Ab0FKPwZ (ORCPT ); Fri, 11 Jun 2010 11:52:25 -0400 Received: from mail-wy0-f174.google.com ([74.125.82.174]:60624 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757565Ab0FKPwZ (ORCPT ); Fri, 11 Jun 2010 11:52:25 -0400 Received: by wyb40 with SMTP id 40so896647wyb.19 for ; Fri, 11 Jun 2010 08:52:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; 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Fri, 11 Jun 2010 15:52:27 +0000 (UTC) diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 379100c..462b59c 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -73,12 +73,10 @@ static inline void omap_init_rtc(void) {} # define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 #endif -#define OMAP1_MBOX_BASE OMAP16XX_MAILBOX_BASE - static struct resource mbox_resources[] = { { - .start = OMAP1_MBOX_BASE, - .end = OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE, + .start = OMAP16XX_MAILBOX_BASE, + .end = OMAP16XX_MAILBOX_BASE + OMAP1_MBOX_SIZE, .flags = IORESOURCE_MEM, }, { diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 4f5b3da..15bf2a2 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c @@ -83,7 +83,7 @@ static int omap1_mbox_fifo_full(struct omap_mbox *mbox) struct omap_mbox1_fifo *fifo = &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; - return (mbox_read_reg(fifo->flag)); + return mbox_read_reg(fifo->flag); } /* irq */ diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 763272c..8c1070c 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -131,7 +131,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) } l = mbox_read_reg(MAILBOX_REVISION); - pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); + pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); if (cpu_is_omap44xx()) l = OMAP4_SMARTIDLE; @@ -300,8 +300,6 @@ static struct omap_mbox2_priv omap2_mbox_dsp_priv = { .irqdisable = MAILBOX_IRQENABLE(0), }; - - /* OMAP4 specific data structure. Use the cpu_is_omap4xxx() to use this*/ static struct omap_mbox2_priv omap2_mbox_1_priv = { @@ -357,7 +355,6 @@ struct omap_mbox mbox_2_info = { }; EXPORT_SYMBOL(mbox_2_info); - #if defined(CONFIG_ARCH_OMAP2420) /* IVA */ static struct omap_mbox2_priv omap2_mbox_iva_priv = { .tx_fifo = { @@ -443,6 +440,11 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) #endif return 0; +#if defined(CONFIG_ARCH_OMAP2420) /* IVA */ +err_iva1: + omap_mbox_unregister(&mbox_dsp_info); +#endif + err_dsp: iounmap(mbox_base); return ret; From patchwork Mon Aug 2 15:29:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 116542 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FUFlP014434 for ; Mon, 2 Aug 2010 15:30:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751835Ab0HBPaN (ORCPT ); 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Mon, 02 Aug 2010 08:30:11 -0700 (PDT) Received: from localhost (97-126-99-222.tukw.qwest.net [97.126.99.222]) by mx.google.com with ESMTPS id n20sm5577530ibe.23.2010.08.02.08.30.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Aug 2010 08:30:05 -0700 (PDT) From: Cory Maccarrone To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Cory Maccarrone Subject: [PATCH 1/5] [OMAP] HTCHERALD: MMC, I2C, HTCPLD and related devices Date: Mon, 2 Aug 2010 08:29:32 -0700 Message-Id: <1280762976-17284-2-git-send-email-darkstar6262@gmail.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> References: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:30:15 +0000 (UTC) diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 3b02d3b..94d5b52 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -64,6 +64,8 @@ config MACH_OMAP_HTCWIZARD config MACH_HERALD bool "HTC Herald" depends on ARCH_OMAP850 + select OMAP_GPIO_EXTRA64 + select OMAP_IRQ_EXTRA64 help HTC Herald smartphone support (AKA T-Mobile Wing, ...) diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 311899f..2f0bb39 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -30,6 +30,11 @@ #include #include #include +#include +#include +#include +#include +#include #include #include @@ -39,6 +44,7 @@ #include #include #include +#include #include @@ -52,13 +58,121 @@ #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) #define OMAP_LCDC_STAT_DONE (1 << 0) -static struct omap_lcd_config htcherald_lcd_config __initdata = { - .ctrl_name = "internal", -}; +/* GPIO definitions for the power button and keyboard slide switch */ +#define HTCHERALD_GPIO_POWER 139 +#define HTCHERALD_GPIO_SLIDE 174 +#define HTCHERALD_GIRQ_BTNS 141 -static struct omap_board_config_kernel htcherald_config[] __initdata = { - { OMAP_TAG_LCD, &htcherald_lcd_config }, -}; +/* HTCPLD definitions */ + +/* + * CPLD Logic + * + +Chip 3 - 0x03 + +Function 7 6 5 4 3 2 1 0 +------------------------------------ +DPAD light x x x x x x x 1 +SoundDev x x x x 1 x x x +Screen white 1 x x x x x x x +MMC power on x x x x x 1 x x +Happy times (n) 0 x x x x 1 x x + +Chip 4 - 0x04 + +Function 7 6 5 4 3 2 1 0 +------------------------------------ +Keyboard light x x x x x x x 1 +LCD Bright (4) x x x x x 1 1 x +LCD Bright (3) x x x x x 0 1 x +LCD Bright (2) x x x x x 1 0 x +LCD Bright (1) x x x x x 0 0 x +LCD Off x x x x 0 x x x +LCD image (fb) 1 x x x x x x x +LCD image (white) 0 x x x x x x x +Caps lock LED x x 1 x x x x x + +Chip 5 - 0x05 + +Function 7 6 5 4 3 2 1 0 +------------------------------------ +Red (solid) x x x x x 1 x x +Red (flash) x x x x x x 1 x +Green (GSM flash) x x x x 1 x x x +Green (GSM solid) x x x 1 x x x x +Green (wifi flash) x x 1 x x x x x +Blue (bt flash) x 1 x x x x x x +DPAD Int Enable 1 x x x x x x 0 + +(Combinations of the above can be made for different colors.) +The direction pad interrupt enable must be set each time the +interrupt is handled. + +Chip 6 - 0x06 + +Function 7 6 5 4 3 2 1 0 +------------------------------------ +Vibrator x x x x 1 x x x +Alt LED x x x 1 x x x x +Screen white 1 x x x x x x x +Screen white x x 1 x x x x x +Screen white x 0 x x x x x x +Enable kbd dpad x x x x x x 0 x +Happy Times 0 1 0 x x x 0 x +*/ + +/* + * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account + * for the 16 MPUIO lines. + */ +#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16) +#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset)) +#define HTCPLD_BASE(chip, offset) \ + (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset)) + +#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) +#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) +#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) +#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) +#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) +#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3) +#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4) +#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5) +#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6) +#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3) +#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4) + +#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7) +#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6) +#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5) +#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4) + +#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7) +#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6) +#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5) +#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) +#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) + +/* + * The htcpld chip requires a gpio write to a specific line + * to re-enable interrupts after one has occurred. + */ +#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7) +#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0) + +/* Chip 5 */ +#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) +#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) +#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5) +#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4) + +/* Chip 6 */ +#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7) +#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6) +#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5) +#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4) +#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3) /* Keyboard definition */ @@ -140,6 +254,129 @@ static struct platform_device kp_device = { .resource = kp_resources, }; +/* GPIO buttons for keyboard slide and power button */ +static struct gpio_keys_button herald_gpio_keys_table[] = { + {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20}, + {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20}, + + {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20}, + {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20}, + {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20}, + {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20}, + + {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20}, + {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20}, + {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20}, + {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20}, + {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20}, +}; + +static struct gpio_keys_platform_data herald_gpio_keys_data = { + .buttons = herald_gpio_keys_table, + .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), + .rep = 1, +}; + +static struct platform_device herald_gpiokeys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &herald_gpio_keys_data, + }, +}; + +/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ +static struct gpio_led gpio_leds[] = { + {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, +}; + +static struct gpio_led_platform_data gpio_leds_data = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device gpio_leds_device = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &gpio_leds_data, + }, +}; + +/* HTC PLD chips */ + +static struct resource htcpld_resources[] = { + [0] = { + .start = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), + .end = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), + .flags = IORESOURCE_IRQ, + }, +}; + +struct htcpld_chip_platform_data htcpld_chips[] = { + [0] = { + .addr = 0x03, + .reset = 0x04, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(0, 0), + .gpio_in_base = HTCPLD_BASE(4, 0), + }, + [1] = { + .addr = 0x04, + .reset = 0x8e, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(1, 0), + .gpio_in_base = HTCPLD_BASE(5, 0), + }, + [2] = { + .addr = 0x05, + .reset = 0x80, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(2, 0), + .gpio_in_base = HTCPLD_BASE(6, 0), + .irq_base = HTCPLD_IRQ(0, 0), + .num_irqs = 8, + }, + [3] = { + .addr = 0x06, + .reset = 0x40, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(3, 0), + .gpio_in_base = HTCPLD_BASE(7, 0), + .irq_base = HTCPLD_IRQ(1, 0), + .num_irqs = 8, + }, +}; + +struct htcpld_core_platform_data htcpld_pfdata = { + .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, + .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, + .i2c_adapter_id = 1, + + .chip = htcpld_chips, + .num_chip = ARRAY_SIZE(htcpld_chips), +}; + +static struct platform_device htcpld_device = { + .name = "i2c-htcpld", + .id = -1, + .resource = htcpld_resources, + .num_resources = ARRAY_SIZE(htcpld_resources), + .dev = { + .platform_data = &htcpld_pfdata, + }, +}; + /* USB Device */ static struct omap_usb_config htcherald_usb_config __initdata = { .otg = 0, @@ -150,14 +387,45 @@ static struct omap_usb_config htcherald_usb_config __initdata = { }; /* LCD Device resources */ +static struct omap_lcd_config htcherald_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_board_config_kernel htcherald_config[] __initdata = { + { OMAP_TAG_LCD, &htcherald_lcd_config }, +}; + static struct platform_device lcd_device = { .name = "lcd_htcherald", .id = -1, }; +/* MMC Card */ +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) +static struct omap_mmc_platform_data htc_mmc1_data = { + .nr_slots = 1, + .switch_slot = NULL, + .slots[0] = { + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | + MMC_VDD_32_33 | MMC_VDD_33_34, + .name = "mmcblk", + .nomux = 1, + .wires = 4, + .switch_pin = -1, + }, +}; + +static struct omap_mmc_platform_data *htc_mmc_data[1]; +#endif + + +/* Platform devices for the Herald */ static struct platform_device *devices[] __initdata = { &kp_device, &lcd_device, + &htcpld_device, + &gpio_leds_device, + &herald_gpiokeys_device, }; /* @@ -278,6 +546,7 @@ static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); + /* Do board initialization before we register all the devices */ omap_gpio_init(); omap_board_config = htcherald_config; @@ -288,6 +557,13 @@ static void __init htcherald_init(void) htcherald_usb_enable(); omap1_usb_init(&htcherald_usb_config); + + omap_register_i2c_bus(1, 100, NULL, 0); + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + htc_mmc_data[0] = &htc_mmc1_data; + omap1_init_mmc(htc_mmc_data, 1); +#endif } static void __init htcherald_init_irq(void) From patchwork Mon Aug 2 15:29:33 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 116543 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FUOx7014464 for ; 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b=uasZ4jloMmMQNWqrslltlaLL4klrsDcJcf04tjCio9EDvwscmz63GLNu6OQEsTc/Ob pg9u5Ou3kwlsC/s6AGdHBhqUsFJkZC58BriIdtMlSaG8wtQB5LMSoPU1nWRZ1EtlFu1h GgZNJmju3/gEE2OhpH99X0564ig3mP5kGoK7c= Received: by 10.229.232.209 with SMTP id jv17mr193473qcb.63.1280763022576; Mon, 02 Aug 2010 08:30:22 -0700 (PDT) Received: from localhost (97-126-99-222.tukw.qwest.net [97.126.99.222]) by mx.google.com with ESMTPS id 34sm5581362ibi.12.2010.08.02.08.30.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Aug 2010 08:30:19 -0700 (PDT) From: Cory Maccarrone To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Cory Maccarrone Subject: [PATCH 2/5] [OMAP] htcherald: SPI register config, TSC2046 touchscreen Date: Mon, 2 Aug 2010 08:29:33 -0700 Message-Id: <1280762976-17284-3-git-send-email-darkstar6262@gmail.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> References: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:30:25 +0000 (UTC) diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 2f0bb39..1b12b75 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -35,6 +35,8 @@ #include #include #include +#include +#include #include #include @@ -63,6 +65,9 @@ #define HTCHERALD_GPIO_SLIDE 174 #define HTCHERALD_GIRQ_BTNS 141 +/* GPIO definitions for the touchscreen */ +#define HTCHERALD_GPIO_TS 76 + /* HTCPLD definitions */ /* @@ -429,6 +434,33 @@ static struct platform_device *devices[] __initdata = { }; /* + * Touchscreen + */ +static const struct ads7846_platform_data htcherald_ts_platform_data = { + .model = 7846, + .keep_vref_on = 1, + .x_plate_ohms = 496, + .gpio_pendown = HTCHERALD_GPIO_TS, + .pressure_max = 100000, + .pressure_min = 5000, + .x_min = 528, + .x_max = 3760, + .y_min = 624, + .y_max = 3760, +}; + +static struct spi_board_info __initdata htcherald_spi_board_info[] = { + { + .modalias = "ads7846", + .platform_data = &htcherald_ts_platform_data, + .irq = OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS), + .max_speed_hz = 2500000, + .bus_num = 2, + .chip_select = 1, + } +}; + +/* * Init functions from here on */ @@ -558,6 +590,9 @@ static void __init htcherald_init(void) htcherald_usb_enable(); omap1_usb_init(&htcherald_usb_config); + spi_register_board_info(htcherald_spi_board_info, + ARRAY_SIZE(htcherald_spi_board_info)); + omap_register_i2c_bus(1, 100, NULL, 0); #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) From patchwork Mon Aug 2 15:23:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 116540 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FOiXK013268 for ; Mon, 2 Aug 2010 15:24:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752093Ab0HBPYn (ORCPT ); Mon, 2 Aug 2010 11:24:43 -0400 Received: from mail-iw0-f174.google.com ([209.85.214.174]:40513 "EHLO mail-iw0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751726Ab0HBPYn (ORCPT ); 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Mon, 02 Aug 2010 08:24:38 -0700 (PDT) From: Cory Maccarrone To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.arm.linux.org.uk Cc: Cory Maccarrone Subject: [PATCH 4/5] [omap1] Bluetooth device code common to HTC smartphones Date: Mon, 2 Aug 2010 08:23:55 -0700 Message-Id: <1280762636-17206-5-git-send-email-darkstar6262@gmail.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1280762636-17206-1-git-send-email-darkstar6262@gmail.com> References: <1280762636-17206-1-git-send-email-darkstar6262@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:24:45 +0000 (UTC) diff --git a/arch/arm/mach-omap1/htc-bt.c b/arch/arm/mach-omap1/htc-bt.c new file mode 100644 index 0000000..aca7b97 --- /dev/null +++ b/arch/arm/mach-omap1/htc-bt.c @@ -0,0 +1,183 @@ +/* + * Bluetooth built-in chip control + * + * Copyright (c) 2010 Cory Maccarrone + * Based on tosa-bt.c copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +static struct clk *uart_ck; + +static void htc_bt_on(struct htc_bt_data *data) +{ + gpio_set_value(data->gpio_pwr, 1); + + if (uart_ck) + clk_enable(uart_ck); + + msleep(1000); + + if (data->gpio_enable) + gpio_set_value(data->gpio_enable, 1); +} + +static void htc_bt_off(struct htc_bt_data *data) +{ + gpio_set_value(data->gpio_pwr, 0); + + if (uart_ck) + clk_disable(uart_ck); + + msleep(1000); + + if (data->gpio_enable) + gpio_set_value(data->gpio_enable, 0); +} + +static int htc_bt_set_block(void *data, bool blocked) +{ + if (!blocked) + htc_bt_on(data); + else + htc_bt_off(data); + + return 0; +} + +static const struct rfkill_ops htc_bt_rfkill_ops = { + .set_block = htc_bt_set_block, +}; + +static int htc_bt_probe(struct platform_device *dev) +{ + int rc; + struct rfkill *rfk; + + struct htc_bt_data *data = dev->dev.platform_data; + + /* Configure the GPIOs */ + if (data->gpio_enable) { + rc = gpio_request(data->gpio_enable, "Bluetooth enable"); + if (rc) + goto err_enable; + rc = gpio_direction_output(data->gpio_enable, 0); + if (rc) + goto err_enable_dir; + } + + rc = gpio_request(data->gpio_pwr, "Bluetooth power"); + if (rc) + goto err_pwr; + rc = gpio_direction_output(data->gpio_pwr, 0); + if (rc) + goto err_pwr_dir; + + /* Get the clocks */ + if (data->uart_clock != NULL) { + uart_ck = clk_get(NULL, data->uart_clock); + if (IS_ERR(uart_ck)) { + pr_warn("htc-bt: Could not get uart clock\n"); + uart_ck = NULL; + } else + clk_disable(uart_ck); + } else + uart_ck = NULL; + + /* MUX pins for UART */ + omap_cfg_reg(UART_7XX_1); + omap_cfg_reg(UART_7XX_2); + + /* Configure RFKill */ + rfk = rfkill_alloc("htc-bt", &dev->dev, RFKILL_TYPE_BLUETOOTH, + &htc_bt_rfkill_ops, data); + if (!rfk) { + rc = -ENOMEM; + goto err_rfk_alloc; + } + + rfkill_set_led_trigger_name(rfk, "htc-bt"); + + rc = rfkill_register(rfk); + if (rc) + goto err_rfkill; + + platform_set_drvdata(dev, rfk); + + return 0; + +err_rfkill: + rfkill_destroy(rfk); +err_rfk_alloc: + htc_bt_off(data); +err_pwr_dir: + gpio_free(data->gpio_pwr); +err_pwr: +err_enable_dir: + if (data->gpio_enable) + gpio_free(data->gpio_enable); +err_enable: + return rc; +} + +static int __devexit htc_bt_remove(struct platform_device *dev) +{ + struct htc_bt_data *data = dev->dev.platform_data; + struct rfkill *rfk = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + + if (rfk) { + rfkill_unregister(rfk); + rfkill_destroy(rfk); + } + rfk = NULL; + + htc_bt_off(data); + + gpio_free(data->gpio_pwr); + if (data->gpio_enable) + gpio_free(data->gpio_enable); + + return 0; +} + +static struct platform_driver htc_bt_driver = { + .probe = htc_bt_probe, + .remove = __devexit_p(htc_bt_remove), + + .driver = { + .name = "htc-bt", + .owner = THIS_MODULE, + }, +}; + + +static int __init htc_bt_init(void) +{ + return platform_driver_register(&htc_bt_driver); +} + +static void __exit htc_bt_exit(void) +{ + platform_driver_unregister(&htc_bt_driver); +} + +late_initcall(htc_bt_init); +module_exit(htc_bt_exit); + diff --git a/arch/arm/mach-omap1/include/mach/htc-bt.h b/arch/arm/mach-omap1/include/mach/htc-bt.h new file mode 100644 index 0000000..843ec45 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/htc-bt.h @@ -0,0 +1,22 @@ +/* + * HTC bluetooth built-in chip control. + * + * Copyright (C) 2010 Cory Maccarrone + * Based on tosa_bt.h copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef HTC_BT_H +#define HTC_BT_H + +struct htc_bt_data { + const char *uart_clock; + int gpio_pwr; + int gpio_enable; +}; + +#endif + From patchwork Mon Aug 2 15:23:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 116541 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FOiXL013268 for ; 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b=lTjAELgpSaIS7u90eAj9A88GyQJ95dpL8oxXEuM2YJolhcY9rdW+pRY6dZxf1YtwtZ c8pez8cO3MSSZA8u5Qed99r99dM6yBBkC2JBsaYxVAQhS1KQrXQ9Z+X0fOiulMacMCRB 4/MpgC7vRtdaUIWkRQ5eg5WvL0x49/a4mx7tw= Received: by 10.90.92.6 with SMTP id p6mr4761313agb.66.1280762691072; Mon, 02 Aug 2010 08:24:51 -0700 (PDT) Received: from localhost (97-126-99-222.tukw.qwest.net [97.126.99.222]) by mx.google.com with ESMTPS id n20sm5574441ibe.17.2010.08.02.08.24.48 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Aug 2010 08:24:49 -0700 (PDT) From: Cory Maccarrone To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.arm.linux.org.uk Cc: Cory Maccarrone Subject: [PATCH 5/5] [htcherald] Add board support for UARTs, bluetooth Date: Mon, 2 Aug 2010 08:23:56 -0700 Message-Id: <1280762636-17206-6-git-send-email-darkstar6262@gmail.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1280762636-17206-1-git-send-email-darkstar6262@gmail.com> References: <1280762636-17206-1-git-send-email-darkstar6262@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:24:53 +0000 (UTC) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index facfaeb..0b8cb18 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -42,7 +42,7 @@ obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o -obj-$(CONFIG_MACH_HERALD) += board-htcherald.o +obj-$(CONFIG_MACH_HERALD) += board-htcherald.o htc-bt.o ifeq ($(CONFIG_ARCH_OMAP15XX),y) # Innovator-1510 FPGA diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 1b12b75..cf4b908 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -47,8 +47,10 @@ #include #include #include +#include #include +#include #include @@ -138,6 +140,7 @@ Happy Times 0 1 0 x x x 0 x #define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) #define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) +#define HTCPLD_GPIO_BT_POWER HTCPLD_BASE(1, 4) #define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) #define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) #define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) @@ -423,6 +426,22 @@ static struct omap_mmc_platform_data htc_mmc1_data = { static struct omap_mmc_platform_data *htc_mmc_data[1]; #endif +/* Bluetooth */ +#define HTCHERALD_GPIO_BT_ENABLE 125 + +static struct htc_bt_data htcherald_bt_data = { + .uart_clock = "uart1_ck", + .gpio_pwr = HTCPLD_GPIO_BT_POWER, + .gpio_enable = HTCHERALD_GPIO_BT_ENABLE, +}; + +static struct platform_device bt_device = { + .name = "htc-bt", + .id = -1, + .dev = { + .platform_data = &htcherald_bt_data, + }, +}; /* Platform devices for the Herald */ static struct platform_device *devices[] __initdata = { @@ -431,6 +450,7 @@ static struct platform_device *devices[] __initdata = { &htcpld_device, &gpio_leds_device, &herald_gpiokeys_device, + &bt_device, }; /* @@ -574,6 +594,7 @@ done: printk(KERN_INFO "USB setup complete.\n"); } + static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); @@ -595,6 +616,8 @@ static void __init htcherald_init(void) omap_register_i2c_bus(1, 100, NULL, 0); + omap_serial_init(); + #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) htc_mmc_data[0] = &htc_mmc1_data; omap1_init_mmc(htc_mmc_data, 1); From patchwork Wed Jul 28 16:50:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114863 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SGk7WV002568 for ; Wed, 28 Jul 2010 16:46:07 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754957Ab0G1QqF (ORCPT ); Wed, 28 Jul 2010 12:46:05 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:49243 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754246Ab0G1QqE (ORCPT ); Wed, 28 Jul 2010 12:46:04 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SGjqCp019523 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 11:45:52 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6SGjpRV011963; Wed, 28 Jul 2010 11:45:51 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SGjkDE026439; Wed, 28 Jul 2010 11:45:47 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH] staging:ti dspbridge: avoid possible NULL dereference panic Date: Wed, 28 Jul 2010 11:50:36 -0500 Message-Id: <1280335836-31801-1-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 16:46:07 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/pmgr/dspapi.c b/drivers/staging/tidspbridge/pmgr/dspapi.c index 1b0ab4a..da08dfc 100644 --- a/drivers/staging/tidspbridge/pmgr/dspapi.c +++ b/drivers/staging/tidspbridge/pmgr/dspapi.c @@ -539,7 +539,7 @@ func_end: */ u32 mgrwrap_wait_for_bridge_events(union trapped_args *args, void *pr_ctxt) { - int status = 0, real_status = 0; + int status = 0; struct dsp_notification *anotifications[MAX_EVENTS]; struct dsp_notification notifications[MAX_EVENTS]; u32 index, i; @@ -554,19 +554,21 @@ u32 mgrwrap_wait_for_bridge_events(union trapped_args *args, void *pr_ctxt) /* get the events */ for (i = 0; i < count; i++) { CP_FM_USR(¬ifications[i], anotifications[i], status, 1); - if (!status) { - /* set the array of pointers to kernel structures */ - anotifications[i] = ¬ifications[i]; + if (status || !notifications[i].handle) { + status = -EINVAL; + break; } + /* set the array of pointers to kernel structures */ + anotifications[i] = ¬ifications[i]; } if (!status) { - real_status = mgr_wait_for_bridge_events(anotifications, count, + status = mgr_wait_for_bridge_events(anotifications, count, &index, args->args_mgr_wait. utimeout); } CP_TO_USR(args->args_mgr_wait.pu_index, &index, status, 1); - return real_status; + return status; } /* From patchwork Mon Aug 2 15:29:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cory Maccarrone X-Patchwork-Id: 116545 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o72FUOx9014464 for ; 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b=LXHT8BSefF6GjgdzhJPN5RBGCtzFkqMrD3amLrVob4mdGhS27yFhw1FejhSR7c60sn tjodsDCGcpX438tMz5svkl8CyDyta2paEmin391j/cs8sBptVIBJ7b3VBaYWXd00rshU du3qENbTOeJ0gbuQQsReIMjLJbfb600oc4qXA= Received: by 10.150.162.3 with SMTP id k3mr7300577ybe.97.1280763045284; Mon, 02 Aug 2010 08:30:45 -0700 (PDT) Received: from localhost (97-126-99-222.tukw.qwest.net [97.126.99.222]) by mx.google.com with ESMTPS id h8sm5581363ibk.15.2010.08.02.08.30.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Aug 2010 08:30:42 -0700 (PDT) From: Cory Maccarrone To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Cory Maccarrone Subject: [PATCH 4/5] [omap1] Bluetooth device code common to HTC smartphones Date: Mon, 2 Aug 2010 08:29:35 -0700 Message-Id: <1280762976-17284-5-git-send-email-darkstar6262@gmail.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> References: <1280762976-17284-1-git-send-email-darkstar6262@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 02 Aug 2010 15:30:47 +0000 (UTC) diff --git a/arch/arm/mach-omap1/htc-bt.c b/arch/arm/mach-omap1/htc-bt.c new file mode 100644 index 0000000..aca7b97 --- /dev/null +++ b/arch/arm/mach-omap1/htc-bt.c @@ -0,0 +1,183 @@ +/* + * Bluetooth built-in chip control + * + * Copyright (c) 2010 Cory Maccarrone + * Based on tosa-bt.c copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +static struct clk *uart_ck; + +static void htc_bt_on(struct htc_bt_data *data) +{ + gpio_set_value(data->gpio_pwr, 1); + + if (uart_ck) + clk_enable(uart_ck); + + msleep(1000); + + if (data->gpio_enable) + gpio_set_value(data->gpio_enable, 1); +} + +static void htc_bt_off(struct htc_bt_data *data) +{ + gpio_set_value(data->gpio_pwr, 0); + + if (uart_ck) + clk_disable(uart_ck); + + msleep(1000); + + if (data->gpio_enable) + gpio_set_value(data->gpio_enable, 0); +} + +static int htc_bt_set_block(void *data, bool blocked) +{ + if (!blocked) + htc_bt_on(data); + else + htc_bt_off(data); + + return 0; +} + +static const struct rfkill_ops htc_bt_rfkill_ops = { + .set_block = htc_bt_set_block, +}; + +static int htc_bt_probe(struct platform_device *dev) +{ + int rc; + struct rfkill *rfk; + + struct htc_bt_data *data = dev->dev.platform_data; + + /* Configure the GPIOs */ + if (data->gpio_enable) { + rc = gpio_request(data->gpio_enable, "Bluetooth enable"); + if (rc) + goto err_enable; + rc = gpio_direction_output(data->gpio_enable, 0); + if (rc) + goto err_enable_dir; + } + + rc = gpio_request(data->gpio_pwr, "Bluetooth power"); + if (rc) + goto err_pwr; + rc = gpio_direction_output(data->gpio_pwr, 0); + if (rc) + goto err_pwr_dir; + + /* Get the clocks */ + if (data->uart_clock != NULL) { + uart_ck = clk_get(NULL, data->uart_clock); + if (IS_ERR(uart_ck)) { + pr_warn("htc-bt: Could not get uart clock\n"); + uart_ck = NULL; + } else + clk_disable(uart_ck); + } else + uart_ck = NULL; + + /* MUX pins for UART */ + omap_cfg_reg(UART_7XX_1); + omap_cfg_reg(UART_7XX_2); + + /* Configure RFKill */ + rfk = rfkill_alloc("htc-bt", &dev->dev, RFKILL_TYPE_BLUETOOTH, + &htc_bt_rfkill_ops, data); + if (!rfk) { + rc = -ENOMEM; + goto err_rfk_alloc; + } + + rfkill_set_led_trigger_name(rfk, "htc-bt"); + + rc = rfkill_register(rfk); + if (rc) + goto err_rfkill; + + platform_set_drvdata(dev, rfk); + + return 0; + +err_rfkill: + rfkill_destroy(rfk); +err_rfk_alloc: + htc_bt_off(data); +err_pwr_dir: + gpio_free(data->gpio_pwr); +err_pwr: +err_enable_dir: + if (data->gpio_enable) + gpio_free(data->gpio_enable); +err_enable: + return rc; +} + +static int __devexit htc_bt_remove(struct platform_device *dev) +{ + struct htc_bt_data *data = dev->dev.platform_data; + struct rfkill *rfk = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + + if (rfk) { + rfkill_unregister(rfk); + rfkill_destroy(rfk); + } + rfk = NULL; + + htc_bt_off(data); + + gpio_free(data->gpio_pwr); + if (data->gpio_enable) + gpio_free(data->gpio_enable); + + return 0; +} + +static struct platform_driver htc_bt_driver = { + .probe = htc_bt_probe, + .remove = __devexit_p(htc_bt_remove), + + .driver = { + .name = "htc-bt", + .owner = THIS_MODULE, + }, +}; + + +static int __init htc_bt_init(void) +{ + return platform_driver_register(&htc_bt_driver); +} + +static void __exit htc_bt_exit(void) +{ + platform_driver_unregister(&htc_bt_driver); +} + +late_initcall(htc_bt_init); +module_exit(htc_bt_exit); + diff --git a/arch/arm/mach-omap1/include/mach/htc-bt.h b/arch/arm/mach-omap1/include/mach/htc-bt.h new file mode 100644 index 0000000..843ec45 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/htc-bt.h @@ -0,0 +1,22 @@ +/* + * HTC bluetooth built-in chip control. + * + * Copyright (C) 2010 Cory Maccarrone + * Based on tosa_bt.h copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef HTC_BT_H +#define HTC_BT_H + +struct htc_bt_data { + const char *uart_clock; + int gpio_pwr; + int gpio_enable; +}; + +#endif + From patchwork Thu Apr 22 08:48:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 94054 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3M8mmKo029879 for ; Thu, 22 Apr 2010 08:48:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752862Ab0DVIsr (ORCPT ); Thu, 22 Apr 2010 04:48:47 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51964 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752841Ab0DVIsq (ORCPT ); Thu, 22 Apr 2010 04:48:46 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3M8mbwY028532 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 22 Apr 2010 03:48:40 -0500 Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3M8mXwW026271; Thu, 22 Apr 2010 14:18:34 +0530 (IST) Received: from linfarm488.india.ti.com (localhost [127.0.0.1]) by linfarm488.india.ti.com (8.12.11/8.12.11) with ESMTP id o3M8mXA7007726; Thu, 22 Apr 2010 14:18:33 +0530 Received: (from x0016154@localhost) by linfarm488.india.ti.com (8.12.11/8.12.11/Submit) id o3M8mW92007724; Thu, 22 Apr 2010 14:18:32 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak , Liam Girdwood , Samuel Ortiz , Mark Brown Subject: [PATCH] twl6030: regulator: Remove vsel tables and use formula for calculation Date: Thu, 22 Apr 2010 14:18:32 +0530 Message-Id: <1271926112-7700-1-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.5 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 22 Apr 2010 08:49:06 +0000 (UTC) diff --git a/drivers/regulator/twl-regulator.c b/drivers/regulator/twl-regulator.c index 9729d76..7e5892e 100644 --- a/drivers/regulator/twl-regulator.c +++ b/drivers/regulator/twl-regulator.c @@ -49,6 +49,7 @@ struct twlreg_info { /* chip constraints on regulator behavior */ u16 min_mV; + u16 max_mV; /* used by regulator core */ struct regulator_desc desc; @@ -318,31 +319,8 @@ static const u16 VIO_VSEL_table[] = { static const u16 VINTANA2_VSEL_table[] = { 2500, 2750, }; -static const u16 VAUX1_6030_VSEL_table[] = { - 1000, 1300, 1800, 2500, - 2800, 2900, 3000, 3000, -}; -static const u16 VAUX2_6030_VSEL_table[] = { - 1200, 1800, 2500, 2750, - 2800, 2800, 2800, 2800, -}; -static const u16 VAUX3_6030_VSEL_table[] = { - 1000, 1200, 1300, 1800, - 2500, 2800, 3000, 3000, -}; -static const u16 VMMC_VSEL_table[] = { - 1200, 1800, 2800, 2900, - 3000, 3000, 3000, 3000, -}; -static const u16 VPP_VSEL_table[] = { - 1800, 1900, 2000, 2100, - 2200, 2300, 2400, 2500, -}; -static const u16 VUSIM_VSEL_table[] = { - 1200, 1800, 2500, 2900, -}; -static int twlldo_list_voltage(struct regulator_dev *rdev, unsigned index) +static int twl4030ldo_list_voltage(struct regulator_dev *rdev, unsigned index) { struct twlreg_info *info = rdev_get_drvdata(rdev); int mV = info->table[index]; @@ -351,7 +329,7 @@ static int twlldo_list_voltage(struct regulator_dev *rdev, unsigned index) } static int -twlldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) +twl4030ldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct twlreg_info *info = rdev_get_drvdata(rdev); int vsel; @@ -375,7 +353,7 @@ twlldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) return -EDOM; } -static int twlldo_get_voltage(struct regulator_dev *rdev) +static int twl4030ldo_get_voltage(struct regulator_dev *rdev) { struct twlreg_info *info = rdev_get_drvdata(rdev); int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, @@ -388,11 +366,67 @@ static int twlldo_get_voltage(struct regulator_dev *rdev) return LDO_MV(info->table[vsel]) * 1000; } -static struct regulator_ops twlldo_ops = { - .list_voltage = twlldo_list_voltage, +static struct regulator_ops twl4030ldo_ops = { + .list_voltage = twl4030ldo_list_voltage, - .set_voltage = twlldo_set_voltage, - .get_voltage = twlldo_get_voltage, + .set_voltage = twl4030ldo_set_voltage, + .get_voltage = twl4030ldo_get_voltage, + + .enable = twlreg_enable, + .disable = twlreg_disable, + .is_enabled = twlreg_is_enabled, + + .set_mode = twlreg_set_mode, + + .get_status = twlreg_get_status, +}; + +static int twl6030ldo_list_voltage(struct regulator_dev *rdev, unsigned index) +{ + struct twlreg_info *info = rdev_get_drvdata(rdev); + + return ((info->min_mV + (index * 100)) * 1000); +} + +static int +twl6030ldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) +{ + struct twlreg_info *info = rdev_get_drvdata(rdev); + int vsel; + + if ((min_uV/1000 < info->min_mV) || (max_uV/1000 > info->max_mV)) + return -EDOM; + + /* + * Use the below formula to calculate vsel + * mV = 1000mv + 100mv * (vsel - 1) + */ + vsel = (min_uV/1000 - 1000)/100 + 1; + return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE, vsel); + +} + +static int twl6030ldo_get_voltage(struct regulator_dev *rdev) +{ + struct twlreg_info *info = rdev_get_drvdata(rdev); + int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, + VREG_VOLTAGE); + + if (vsel < 0) + return vsel; + + /* + * Use the below formula to calculate vsel + * mV = 1000mv + 100mv * (vsel - 1) + */ + return (1000 + (100 * (vsel - 1))) * 1000; +} + +static struct regulator_ops twl6030ldo_ops = { + .list_voltage = twl6030ldo_list_voltage, + + .set_voltage = twl6030ldo_set_voltage, + .get_voltage = twl6030ldo_get_voltage, .enable = twlreg_enable, .disable = twlreg_disable, @@ -438,24 +472,16 @@ static struct regulator_ops twlfixed_ops = { /*----------------------------------------------------------------------*/ -#define TWL4030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf) \ - TWL_ADJUSTABLE_LDO(label, offset, num, turnon_delay, \ - remap_conf, TWL4030) #define TWL4030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ remap_conf) \ TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ remap_conf, TWL4030) -#define TWL6030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, \ - remap_conf) \ - TWL_ADJUSTABLE_LDO(label, offset, num, turnon_delay, \ - remap_conf, TWL6030) #define TWL6030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ remap_conf) \ TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ remap_conf, TWL6030) -#define TWL_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf, \ - family) { \ +#define TWL4030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf) { \ .base = offset, \ .id = num, \ .table_len = ARRAY_SIZE(label##_VSEL_table), \ @@ -464,14 +490,32 @@ static struct regulator_ops twlfixed_ops = { .remap = remap_conf, \ .desc = { \ .name = #label, \ - .id = family##_REG_##label, \ + .id = TWL4030_REG_##label, \ .n_voltages = ARRAY_SIZE(label##_VSEL_table), \ - .ops = &twlldo_ops, \ + .ops = &twl4030ldo_ops, \ .type = REGULATOR_VOLTAGE, \ .owner = THIS_MODULE, \ }, \ } +#define TWL6030_ADJUSTABLE_LDO(label, offset, min_mVolts, max_mVolts, num, \ + remap_conf) { \ + .base = offset, \ + .id = num, \ + .min_mV = min_mVolts, \ + .max_mV = max_mVolts, \ + .remap = remap_conf, \ + .desc = { \ + .name = #label, \ + .id = TWL6030_REG_##label, \ + .n_voltages = (max_mVolts - min_mVolts)/100, \ + .ops = &twl6030ldo_ops, \ + .type = REGULATOR_VOLTAGE, \ + .owner = THIS_MODULE, \ + }, \ + } + + #define TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, remap_conf, \ family) { \ .base = offset, \ @@ -519,12 +563,12 @@ static struct twlreg_info twl_regs[] = { /* 6030 REG with base as PMC Slave Misc : 0x0030 */ /* Turnon-delay and remap configuration values for 6030 are not verified since the specification is not public */ - TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54, 1, 0, 0x21), - TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58, 2, 0, 0x21), - TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c, 3, 0, 0x21), - TWL6030_ADJUSTABLE_LDO(VMMC, 0x68, 4, 0, 0x21), - TWL6030_ADJUSTABLE_LDO(VPP, 0x6c, 5, 0, 0x21), - TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74, 7, 0, 0x21), + TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54, 1000, 3300, 1, 0x21), + TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58, 1000, 3300, 2, 0x21), + TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c, 1000, 3300, 3, 0x21), + TWL6030_ADJUSTABLE_LDO(VMMC, 0x68, 1000, 3300, 4, 0x21), + TWL6030_ADJUSTABLE_LDO(VPP, 0x6c, 1000, 3300, 5, 0x21), + TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74, 1000, 3300, 7, 0x21), TWL6030_FIXED_LDO(VANA, 0x50, 2100, 15, 0, 0x21), TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 16, 0, 0x21), TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 17, 0, 0x21), From patchwork Wed Jul 28 21:04:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramos Falcon, Ernesto" X-Patchwork-Id: 114906 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SL1BnS013193 for ; Wed, 28 Jul 2010 21:01:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756328Ab0G1VAr (ORCPT ); Wed, 28 Jul 2010 17:00:47 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:49163 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756234Ab0G1VAZ (ORCPT ); Wed, 28 Jul 2010 17:00:25 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6SL0AOr025275 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Jul 2010 16:00:10 -0500 Received: from emcc1.sasken-mty.naucm.ext.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6SL09Ek025577; Wed, 28 Jul 2010 16:00:09 -0500 (CDT) Received: from localhost.localdomain (x0076199-desktop.sasken-mty.naucm.ext.ti.com [10.87.230.107]) by emcc1.sasken-mty.naucm.ext.ti.com (8.13.8+Sun/8.13.8) with ESMTP id o6SL06xY017327; Wed, 28 Jul 2010 16:00:09 -0500 (CDT) From: Ernesto Ramos To: gregkh@suse.de Cc: omar.ramirez@ti.com, ohad@wizery.com, ameya.palande@nokia.com, felipe.contreras@nokia.com, fernando.lugo@ti.com, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, nm@ti.com, linux-omap@vger.kernel.org, Ernesto Ramos Subject: [PATCH] staging:ti dspbridge: use node id instead of kernel address Date: Wed, 28 Jul 2010 16:04:53 -0500 Message-Id: <1280351097-3346-2-git-send-email-ernesto@ti.com> X-Mailer: git-send-email 1.5.4.5 In-Reply-To: <1280351097-3346-1-git-send-email-ernesto@ti.com> References: <1280351097-3346-1-git-send-email-ernesto@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 21:01:11 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index 28541f7..0b36a11 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -24,6 +24,7 @@ #include #include +#include #define DRV_ASSIGN 1 #define DRV_RELEASE 0 @@ -81,7 +82,7 @@ struct node_res_object { s32 node_allocated; /* Node status */ s32 heap_allocated; /* Heap status */ s32 streams_allocated; /* Streams status */ - struct node_res_object *next; + int id; }; /* used to cache dma mapping information */ @@ -158,8 +159,7 @@ struct process_context { void *hprocessor; /* DSP Node resources */ - struct node_res_object *node_list; - struct mutex node_mutex; + struct idr *node_id; /* DMM mapped memory resources */ struct list_head dmm_map_list; diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index 61d2d9b..49ed5c1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -36,7 +36,7 @@ * pargs: Optional arguments to be passed to the node. * attr_in: Optional pointer to node attributes (priority, * timeout...) - * ph_node: Location to store node handle on output. + * noderes: Location to store node resource info. * Returns: * 0: Success. * -ENOMEM: Insufficient memory on GPP. @@ -50,17 +50,17 @@ * node_init(void) called. * hprocessor != NULL. * node_uuid != NULL. - * ph_node != NULL. + * noderes != NULL. * Ensures: * 0: IsValidNode(*ph_node). - * error: *ph_node == NULL. + * error: *noderes == NULL. */ extern int node_allocate(struct proc_object *hprocessor, const struct dsp_uuid *node_uuid, const struct dsp_cbdata *pargs, const struct dsp_nodeattrin *attr_in, - struct node_object **ph_node, + struct node_res_object **noderes, struct process_context *pr_ctxt); /* @@ -242,7 +242,9 @@ extern int node_create_mgr(struct node_mgr **node_man, * delete function. Loads the node's delete function if necessary. * GPP side resources are freed after node's delete function returns. * Parameters: - * hnode: Node handle returned from node_allocate(). + * noderes: Node resource info handle returned from + * node_allocate(). + * pr_ctxt: Poninter to process context data. * Returns: * 0: Success. * -EFAULT: Invalid hnode. @@ -254,7 +256,7 @@ extern int node_create_mgr(struct node_mgr **node_man, * Ensures: * 0: hnode is invalid. */ -extern int node_delete(struct node_object *hnode, +extern int node_delete(struct node_res_object *noderes, struct process_context *pr_ctxt); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h index 4e1b8a2..d17c7fb 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h +++ b/drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h @@ -34,17 +34,11 @@ extern int drv_remove_all_resources(void *process_ctxt); extern int drv_remove_proc_context(struct drv_object *driver_obj, void *pr_ctxt); -extern int drv_get_node_res_element(void *hnode, void *node_resource, - void *process_ctx); - extern int drv_insert_node_res_element(void *hnode, void *node_resource, void *process_ctxt); extern void drv_proc_node_update_heap_status(void *node_resource, s32 status); -extern int drv_remove_node_res_element(void *node_resource, - void *process_ctxt); - extern void drv_proc_node_update_status(void *node_resource, s32 status); extern int drv_proc_update_strm_res(u32 num_bufs, void *strm_resources); diff --git a/drivers/staging/tidspbridge/pmgr/dspapi.c b/drivers/staging/tidspbridge/pmgr/dspapi.c index da08dfc..6eda7c5 100644 --- a/drivers/staging/tidspbridge/pmgr/dspapi.c +++ b/drivers/staging/tidspbridge/pmgr/dspapi.c @@ -1052,6 +1052,20 @@ u32 procwrap_stop(union trapped_args *args, void *pr_ctxt) } /* + * ======== find_handle ========= + */ +inline void find_node_handle(struct node_res_object **noderes, + void *pr_ctxt, void *hnode) +{ + rcu_read_lock(); + *noderes = idr_find(((struct process_context *)pr_ctxt)->node_id, + (int)hnode); + rcu_read_unlock(); + return; +} + + +/* * ======== nodewrap_allocate ======== */ u32 nodewrap_allocate(union trapped_args *args, void *pr_ctxt) @@ -1062,7 +1076,7 @@ u32 nodewrap_allocate(union trapped_args *args, void *pr_ctxt) u32 __user *psize = (u32 __user *) args->args_node_allocate.pargs; u8 *pargs = NULL; struct dsp_nodeattrin proc_attr_in, *attr_in = NULL; - struct node_object *hnode; + struct node_res_object *node_res; /* Optional argument */ if (psize) { @@ -1095,13 +1109,14 @@ u32 nodewrap_allocate(union trapped_args *args, void *pr_ctxt) if (!status) { status = node_allocate(args->args_node_allocate.hprocessor, &node_uuid, (struct dsp_cbdata *)pargs, - attr_in, &hnode, pr_ctxt); + attr_in, &node_res, pr_ctxt); } if (!status) { - CP_TO_USR(args->args_node_allocate.ph_node, &hnode, status, 1); + CP_TO_USR(args->args_node_allocate.ph_node, &node_res->id, + status, 1); if (status) { status = -EFAULT; - node_delete(hnode, pr_ctxt); + node_delete(node_res, pr_ctxt); } } func_cont: @@ -1119,6 +1134,13 @@ u32 nodewrap_alloc_msg_buf(union trapped_args *args, void *pr_ctxt) struct dsp_bufferattr *pattr = NULL; struct dsp_bufferattr attr; u8 *pbuffer = NULL; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, + args->args_node_allocmsgbuf.hnode); + + if (!node_res) + return -EFAULT; if (!args->args_node_allocmsgbuf.usize) return -EINVAL; @@ -1132,7 +1154,7 @@ u32 nodewrap_alloc_msg_buf(union trapped_args *args, void *pr_ctxt) /* argument */ CP_FM_USR(&pbuffer, args->args_node_allocmsgbuf.pbuffer, status, 1); if (!status) { - status = node_alloc_msg_buf(args->args_node_allocmsgbuf.hnode, + status = node_alloc_msg_buf(node_res->hnode, args->args_node_allocmsgbuf.usize, pattr, &pbuffer); } @@ -1146,8 +1168,15 @@ u32 nodewrap_alloc_msg_buf(union trapped_args *args, void *pr_ctxt) u32 nodewrap_change_priority(union trapped_args *args, void *pr_ctxt) { u32 ret; + struct node_res_object *node_res; - ret = node_change_priority(args->args_node_changepriority.hnode, + find_node_handle(&node_res, pr_ctxt, + args->args_node_changepriority.hnode); + + if (!node_res) + return -EFAULT; + + ret = node_change_priority(node_res->hnode, args->args_node_changepriority.prio); return ret; @@ -1164,6 +1193,29 @@ u32 nodewrap_connect(union trapped_args *args, void *pr_ctxt) u32 cb_data_size; u32 __user *psize = (u32 __user *) args->args_node_connect.conn_param; u8 *pargs = NULL; + struct node_res_object *node_res1, *node_res2; + struct node_object *node1 = NULL, *node2 = NULL; + + if ((int)args->args_node_connect.hnode != DSP_HGPPNODE) { + find_node_handle(&node_res1, pr_ctxt, + args->args_node_connect.hnode); + if (node_res1) + node1 = node_res1->hnode; + } else { + node1 = args->args_node_connect.hnode; + } + + if ((int)args->args_node_connect.other_node != DSP_HGPPNODE) { + find_node_handle(&node_res2, pr_ctxt, + args->args_node_connect.other_node); + if (node_res2) + node2 = node_res2->hnode; + } else { + node2 = args->args_node_connect.other_node; + } + + if (!node1 || !node2) + return -EFAULT; /* Optional argument */ if (psize) { @@ -1191,9 +1243,9 @@ u32 nodewrap_connect(union trapped_args *args, void *pr_ctxt) } if (!status) { - status = node_connect(args->args_node_connect.hnode, + status = node_connect(node1, args->args_node_connect.stream_id, - args->args_node_connect.other_node, + node2, args->args_node_connect.other_stream, pattrs, (struct dsp_cbdata *)pargs); } @@ -1209,8 +1261,14 @@ func_cont: u32 nodewrap_create(union trapped_args *args, void *pr_ctxt) { u32 ret; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_node_create.hnode); - ret = node_create(args->args_node_create.hnode); + if (!node_res) + return -EFAULT; + + ret = node_create(node_res->hnode); return ret; } @@ -1221,8 +1279,14 @@ u32 nodewrap_create(union trapped_args *args, void *pr_ctxt) u32 nodewrap_delete(union trapped_args *args, void *pr_ctxt) { u32 ret; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_node_delete.hnode); + + if (!node_res) + return -EFAULT; - ret = node_delete(args->args_node_delete.hnode, pr_ctxt); + ret = node_delete(node_res, pr_ctxt); return ret; } @@ -1235,6 +1299,13 @@ u32 nodewrap_free_msg_buf(union trapped_args *args, void *pr_ctxt) int status = 0; struct dsp_bufferattr *pattr = NULL; struct dsp_bufferattr attr; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_node_freemsgbuf.hnode); + + if (!node_res) + return -EFAULT; + if (args->args_node_freemsgbuf.pattr) { /* Optional argument */ CP_FM_USR(&attr, args->args_node_freemsgbuf.pattr, status, 1); if (!status) @@ -1246,7 +1317,7 @@ u32 nodewrap_free_msg_buf(union trapped_args *args, void *pr_ctxt) return -EFAULT; if (!status) { - status = node_free_msg_buf(args->args_node_freemsgbuf.hnode, + status = node_free_msg_buf(node_res->hnode, args->args_node_freemsgbuf.pbuffer, pattr); } @@ -1261,8 +1332,14 @@ u32 nodewrap_get_attr(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_nodeattr attr; + struct node_res_object *node_res; - status = node_get_attr(args->args_node_getattr.hnode, &attr, + find_node_handle(&node_res, pr_ctxt, args->args_node_getattr.hnode); + + if (!node_res) + return -EFAULT; + + status = node_get_attr(node_res->hnode, &attr, args->args_node_getattr.attr_size); CP_TO_USR(args->args_node_getattr.pattr, &attr, status, 1); @@ -1276,8 +1353,14 @@ u32 nodewrap_get_message(union trapped_args *args, void *pr_ctxt) { int status; struct dsp_msg msg; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_node_getmessage.hnode); - status = node_get_message(args->args_node_getmessage.hnode, &msg, + if (!node_res) + return -EFAULT; + + status = node_get_message(node_res->hnode, &msg, args->args_node_getmessage.utimeout); CP_TO_USR(args->args_node_getmessage.message, &msg, status, 1); @@ -1291,8 +1374,14 @@ u32 nodewrap_get_message(union trapped_args *args, void *pr_ctxt) u32 nodewrap_pause(union trapped_args *args, void *pr_ctxt) { u32 ret; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_node_pause.hnode); + + if (!node_res) + return -EFAULT; - ret = node_pause(args->args_node_pause.hnode); + ret = node_pause(node_res->hnode); return ret; } @@ -1304,12 +1393,18 @@ u32 nodewrap_put_message(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_msg msg; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_node_putmessage.hnode); + + if (!node_res) + return -EFAULT; CP_FM_USR(&msg, args->args_node_putmessage.message, status, 1); if (!status) { status = - node_put_message(args->args_node_putmessage.hnode, &msg, + node_put_message(node_res->hnode, &msg, args->args_node_putmessage.utimeout); } @@ -1323,6 +1418,13 @@ u32 nodewrap_register_notify(union trapped_args *args, void *pr_ctxt) { int status = 0; struct dsp_notification notification; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, + args->args_node_registernotify.hnode); + + if (!node_res) + return -EFAULT; /* Initialize the notification data structure */ notification.ps_name = NULL; @@ -1333,7 +1435,7 @@ u32 nodewrap_register_notify(union trapped_args *args, void *pr_ctxt) args->args_proc_register_notify.hnotification, status, 1); - status = node_register_notify(args->args_node_registernotify.hnode, + status = node_register_notify(node_res->hnode, args->args_node_registernotify.event_mask, args->args_node_registernotify. notify_type, ¬ification); @@ -1348,8 +1450,14 @@ u32 nodewrap_register_notify(union trapped_args *args, void *pr_ctxt) u32 nodewrap_run(union trapped_args *args, void *pr_ctxt) { u32 ret; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_node_run.hnode); + + if (!node_res) + return -EFAULT; - ret = node_run(args->args_node_run.hnode); + ret = node_run(node_res->hnode); return ret; } @@ -1361,8 +1469,14 @@ u32 nodewrap_terminate(union trapped_args *args, void *pr_ctxt) { int status; int tempstatus; + struct node_res_object *node_res; - status = node_terminate(args->args_node_terminate.hnode, &tempstatus); + find_node_handle(&node_res, pr_ctxt, args->args_node_terminate.hnode); + + if (!node_res) + return -EFAULT; + + status = node_terminate(node_res->hnode, &tempstatus); CP_TO_USR(args->args_node_terminate.pstatus, &tempstatus, status, 1); @@ -1548,6 +1662,12 @@ u32 strmwrap_open(union trapped_args *args, void *pr_ctxt) struct strm_attr attr; struct strm_object *strm_obj; struct dsp_streamattrin strm_attr_in; + struct node_res_object *node_res; + + find_node_handle(&node_res, pr_ctxt, args->args_strm_open.hnode); + + if (!node_res) + return -EFAULT; CP_FM_USR(&attr, args->args_strm_open.attr_in, status, 1); @@ -1560,7 +1680,7 @@ u32 strmwrap_open(union trapped_args *args, void *pr_ctxt) } } - status = strm_open(args->args_strm_open.hnode, + status = strm_open(node_res->hnode, args->args_strm_open.direction, args->args_strm_open.index, &attr, &strm_obj, pr_ctxt); diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 12c270a..c8d9d25 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -73,7 +73,7 @@ static int request_bridge_resources(struct cfg_hostres *res); /* GPP PROCESS CLEANUP CODE */ -static int drv_proc_free_node_res(void *process_ctxt); +static int drv_proc_free_node_res(int id, void *p, void *data); /* Allocate and add a node resource element * This function is called from .Node_Allocate. */ @@ -84,88 +84,61 @@ int drv_insert_node_res_element(void *hnode, void *node_resource, (struct node_res_object **)node_resource; struct process_context *ctxt = (struct process_context *)process_ctxt; int status = 0; - struct node_res_object *temp_node_res = NULL; + int retval; *node_res_obj = kzalloc(sizeof(struct node_res_object), GFP_KERNEL); - if (*node_res_obj == NULL) - status = -EFAULT; + if (!*node_res_obj) { + status = -ENOMEM; + goto func_end; + } - if (!status) { - if (mutex_lock_interruptible(&ctxt->node_mutex)) { - kfree(*node_res_obj); - return -EPERM; + (*node_res_obj)->hnode = hnode; + retval = idr_get_new(ctxt->node_id, *node_res_obj, + &(*node_res_obj)->id); + if (retval == -EAGAIN) { + if (!idr_pre_get(ctxt->node_id, GFP_KERNEL)) { + pr_err("%s: OUT OF MEMORY\n", __func__); + status = -ENOMEM; + goto func_end; } - (*node_res_obj)->hnode = hnode; - if (ctxt->node_list != NULL) { - temp_node_res = ctxt->node_list; - while (temp_node_res->next != NULL) - temp_node_res = temp_node_res->next; - temp_node_res->next = *node_res_obj; - } else { - ctxt->node_list = *node_res_obj; - } - mutex_unlock(&ctxt->node_mutex); + retval = idr_get_new(ctxt->node_id, *node_res_obj, + &(*node_res_obj)->id); + } + if (retval) { + pr_err("%s: FAILED, IDR is FULL\n", __func__); + status = -EFAULT; } +func_end: + if (status) + kfree(*node_res_obj); return status; } /* Release all Node resources and its context -* This is called from .Node_Delete. */ -int drv_remove_node_res_element(void *node_resource, void *process_ctxt) + * Actual Node De-Allocation */ +static int drv_proc_free_node_res(int id, void *p, void *data) { - struct node_res_object *node_res_obj = - (struct node_res_object *)node_resource; - struct process_context *ctxt = (struct process_context *)process_ctxt; - struct node_res_object *temp_node; - int status = 0; - - if (mutex_lock_interruptible(&ctxt->node_mutex)) - return -EPERM; - temp_node = ctxt->node_list; - if (temp_node == node_res_obj) { - ctxt->node_list = node_res_obj->next; - } else { - while (temp_node && temp_node->next != node_res_obj) - temp_node = temp_node->next; - if (!temp_node) - status = -ENOENT; - else - temp_node->next = node_res_obj->next; - } - mutex_unlock(&ctxt->node_mutex); - kfree(node_res_obj); - return status; -} - -/* Actual Node De-Allocation */ -static int drv_proc_free_node_res(void *process_ctxt) -{ - struct process_context *ctxt = (struct process_context *)process_ctxt; - int status = 0; - struct node_res_object *node_list = NULL; - struct node_res_object *node_res_obj = NULL; + struct process_context *ctxt = data; + int status; + struct node_res_object *node_res_obj = p; u32 node_state; - node_list = ctxt->node_list; - while (node_list != NULL) { - node_res_obj = node_list; - node_list = node_list->next; - if (node_res_obj->node_allocated) { - node_state = node_get_state(node_res_obj->hnode); - if (node_state <= NODE_DELETING) { - if ((node_state == NODE_RUNNING) || - (node_state == NODE_PAUSED) || - (node_state == NODE_TERMINATING)) - status = node_terminate - (node_res_obj->hnode, &status); - - status = node_delete(node_res_obj->hnode, ctxt); - } + if (node_res_obj->node_allocated) { + node_state = node_get_state(node_res_obj->hnode); + if (node_state <= NODE_DELETING) { + if ((node_state == NODE_RUNNING) || + (node_state == NODE_PAUSED) || + (node_state == NODE_TERMINATING)) + node_terminate + (node_res_obj->hnode, &status); + + node_delete(node_res_obj, ctxt); } } - return status; + + return 0; } /* Release all Mapped and Reserved DMM resources */ @@ -220,50 +193,12 @@ void drv_proc_node_update_heap_status(void *node_resource, s32 status) */ int drv_remove_all_node_res_elements(void *process_ctxt) { - struct process_context *ctxt = (struct process_context *)process_ctxt; - int status = 0; - struct node_res_object *temp_node2 = NULL; - struct node_res_object *temp_node = NULL; - - drv_proc_free_node_res(ctxt); - temp_node = ctxt->node_list; - while (temp_node != NULL) { - temp_node2 = temp_node; - temp_node = temp_node->next; - kfree(temp_node2); - } - ctxt->node_list = NULL; - return status; -} + struct process_context *ctxt = process_ctxt; -/* Getting the node resource element */ -int drv_get_node_res_element(void *hnode, void *node_resource, - void *process_ctxt) -{ - struct node_res_object **node_res = - (struct node_res_object **)node_resource; - struct process_context *ctxt = (struct process_context *)process_ctxt; - int status = 0; - struct node_res_object *temp_node2 = NULL; - struct node_res_object *temp_node = NULL; - - if (mutex_lock_interruptible(&ctxt->node_mutex)) - return -EPERM; - - temp_node = ctxt->node_list; - while ((temp_node != NULL) && (temp_node->hnode != hnode)) { - temp_node2 = temp_node; - temp_node = temp_node->next; - } + idr_for_each(ctxt->node_id, drv_proc_free_node_res, ctxt); + idr_destroy(ctxt->node_id); - mutex_unlock(&ctxt->node_mutex); - - if (temp_node != NULL) - *node_res = temp_node; - else - status = -ENOENT; - - return status; + return 0; } /* Allocate the STRM resource element diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c b/drivers/staging/tidspbridge/rmgr/drv_interface.c index aec7cf7..900cdd3 100644 --- a/drivers/staging/tidspbridge/rmgr/drv_interface.c +++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c @@ -511,8 +511,13 @@ static int bridge_open(struct inode *ip, struct file *filp) INIT_LIST_HEAD(&pr_ctxt->dmm_map_list); spin_lock_init(&pr_ctxt->dmm_rsv_lock); INIT_LIST_HEAD(&pr_ctxt->dmm_rsv_list); - mutex_init(&pr_ctxt->node_mutex); mutex_init(&pr_ctxt->strm_mutex); + + pr_ctxt->node_id = kzalloc(sizeof(struct idr), GFP_KERNEL); + if (pr_ctxt->node_id) + idr_init(pr_ctxt->node_id); + else + status = -ENOMEM; } else { status = -ENOMEM; } diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index e2d02c4..6e9441e 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -291,11 +291,11 @@ enum node_state node_get_state(void *hnode) * Allocate GPP resources to manage a node on the DSP. */ int node_allocate(struct proc_object *hprocessor, - const struct dsp_uuid *node_uuid, - const struct dsp_cbdata *pargs, - const struct dsp_nodeattrin *attr_in, - struct node_object **ph_node, - struct process_context *pr_ctxt) + const struct dsp_uuid *node_uuid, + const struct dsp_cbdata *pargs, + const struct dsp_nodeattrin *attr_in, + struct node_res_object **noderes, + struct process_context *pr_ctxt) { struct node_mgr *hnode_mgr; struct dev_object *hdev_obj; @@ -327,10 +327,10 @@ int node_allocate(struct proc_object *hprocessor, DBC_REQUIRE(refs > 0); DBC_REQUIRE(hprocessor != NULL); - DBC_REQUIRE(ph_node != NULL); + DBC_REQUIRE(noderes != NULL); DBC_REQUIRE(node_uuid != NULL); - *ph_node = NULL; + *noderes = NULL; status = proc_get_processor_id(hprocessor, &proc_id); @@ -653,9 +653,6 @@ func_cont: * (for overlay and dll) */ pnode->phase_split = true; - if (!status) - *ph_node = pnode; - /* Notify all clients registered for DSP_NODESTATECHANGE. */ proc_notify_all_clients(hprocessor, DSP_NODESTATECHANGE); } else { @@ -666,16 +663,21 @@ func_cont: } if (!status) { - drv_insert_node_res_element(*ph_node, &node_res, pr_ctxt); + status = drv_insert_node_res_element(pnode, &node_res, pr_ctxt); + if (status) { + delete_node(pnode, pr_ctxt); + goto func_end; + } + + *noderes = (struct node_res_object *)node_res; drv_proc_node_update_heap_status(node_res, true); drv_proc_node_update_status(node_res, true); } - DBC_ENSURE((status && (*ph_node == NULL)) || - (!status && *ph_node)); + DBC_ENSURE((status && *noderes == NULL) || (!status && *noderes)); func_end: - dev_dbg(bridge, "%s: hprocessor: %p node_uuid: %p pargs: %p attr_in:" - " %p ph_node: %p status: 0x%x\n", __func__, hprocessor, - node_uuid, pargs, attr_in, ph_node, status); + dev_dbg(bridge, "%s: hprocessor: %p pNodeId: %p pargs: %p attr_in: %p " + "node_res: %p status: 0x%x\n", __func__, hprocessor, + node_uuid, pargs, attr_in, noderes, status); return status; } @@ -1433,10 +1435,10 @@ int node_create_mgr(struct node_mgr **node_man, * Loads the node's delete function if necessary. Free GPP side resources * after node's delete function returns. */ -int node_delete(struct node_object *hnode, +int node_delete(struct node_res_object *noderes, struct process_context *pr_ctxt) { - struct node_object *pnode = (struct node_object *)hnode; + struct node_object *pnode = noderes->hnode; struct node_mgr *hnode_mgr; struct proc_object *hprocessor; struct disp_object *disp_obj; @@ -1449,32 +1451,32 @@ int node_delete(struct node_object *hnode, u32 proc_id; struct bridge_drv_interface *intf_fxns; - void *node_res; + void *node_res = noderes; struct dsp_processorstate proc_state; DBC_REQUIRE(refs > 0); - if (!hnode) { + if (!pnode) { status = -EFAULT; goto func_end; } /* create struct dsp_cbdata struct for PWR call */ cb_data.cb_data = PWR_TIMEOUT; - hnode_mgr = hnode->hnode_mgr; - hprocessor = hnode->hprocessor; + hnode_mgr = pnode->hnode_mgr; + hprocessor = pnode->hprocessor; disp_obj = hnode_mgr->disp_obj; - node_type = node_get_type(hnode); + node_type = node_get_type(pnode); intf_fxns = hnode_mgr->intf_fxns; /* Enter critical section */ mutex_lock(&hnode_mgr->node_mgr_lock); - state = node_get_state(hnode); + state = node_get_state(pnode); /* Execute delete phase code for non-device node in all cases * except when the node was only allocated. Delete phase must be * executed even if create phase was executed, but failed. * If the node environment pointer is non-NULL, the delete phase * code must be executed. */ - if (!(state == NODE_ALLOCATED && hnode->node_env == (u32) NULL) && + if (!(state == NODE_ALLOCATED && pnode->node_env == (u32) NULL) && node_type != NODE_DEVICE) { status = proc_get_processor_id(pnode->hprocessor, &proc_id); if (status) @@ -1487,26 +1489,26 @@ int node_delete(struct node_object *hnode, * is now ok to unload it. If the node is running, we * will unload the execute phase only after deleting * the node. */ - if (state == NODE_PAUSED && hnode->loaded && - hnode->phase_split) { + if (state == NODE_PAUSED && pnode->loaded && + pnode->phase_split) { /* Ok to unload execute code as long as node * is not * running */ status1 = hnode_mgr->nldr_fxns. - pfn_unload(hnode->nldr_node_obj, + pfn_unload(pnode->nldr_node_obj, NLDR_EXECUTE); - hnode->loaded = false; - NODE_SET_STATE(hnode, NODE_DONE); + pnode->loaded = false; + NODE_SET_STATE(pnode, NODE_DONE); } /* Load delete phase code if not loaded or if haven't * * unloaded EXECUTE phase */ - if ((!(hnode->loaded) || (state == NODE_RUNNING)) && - hnode->phase_split) { + if ((!(pnode->loaded) || (state == NODE_RUNNING)) && + pnode->phase_split) { status = hnode_mgr->nldr_fxns. - pfn_load(hnode->nldr_node_obj, NLDR_DELETE); + pfn_load(pnode->nldr_node_obj, NLDR_DELETE); if (!status) - hnode->loaded = true; + pnode->loaded = true; else pr_err("%s: fail - load delete code:" " 0x%x\n", __func__, status); @@ -1515,14 +1517,14 @@ int node_delete(struct node_object *hnode, func_cont1: if (!status) { /* Unblock a thread trying to terminate the node */ - (void)sync_set_event(hnode->sync_done); + (void)sync_set_event(pnode->sync_done); if (proc_id == DSP_UNIT) { /* ul_delete_fxn = address of node's delete * function */ - status = get_fxn_address(hnode, &ul_delete_fxn, + status = get_fxn_address(pnode, &ul_delete_fxn, DELETEPHASE); } else if (proc_id == IVA_UNIT) - ul_delete_fxn = (u32) hnode->node_env; + ul_delete_fxn = (u32) pnode->node_env; if (!status) { status = proc_get_state(hprocessor, &proc_state, @@ -1530,22 +1532,22 @@ func_cont1: dsp_processorstate)); if (proc_state.proc_state != PROC_ERROR) { status = - disp_node_delete(disp_obj, hnode, + disp_node_delete(disp_obj, pnode, hnode_mgr-> ul_fxn_addrs [RMSDELETENODE], ul_delete_fxn, - hnode->node_env); + pnode->node_env); } else - NODE_SET_STATE(hnode, NODE_DONE); + NODE_SET_STATE(pnode, NODE_DONE); /* Unload execute, if not unloaded, and delete * function */ if (state == NODE_RUNNING && - hnode->phase_split) { + pnode->phase_split) { status1 = hnode_mgr->nldr_fxns. - pfn_unload(hnode->nldr_node_obj, + pfn_unload(pnode->nldr_node_obj, NLDR_EXECUTE); } if (status1) @@ -1553,10 +1555,10 @@ func_cont1: " 0x%x\n", __func__, status1); status1 = - hnode_mgr->nldr_fxns.pfn_unload(hnode-> + hnode_mgr->nldr_fxns.pfn_unload(pnode-> nldr_node_obj, NLDR_DELETE); - hnode->loaded = false; + pnode->loaded = false; if (status1) pr_err("%s: fail - unload delete code: " "0x%x\n", __func__, status1); @@ -1565,25 +1567,28 @@ func_cont1: } /* Free host side resources even if a failure occurred */ /* Remove node from hnode_mgr->node_list */ - lst_remove_elem(hnode_mgr->node_list, (struct list_head *)hnode); + lst_remove_elem(hnode_mgr->node_list, (struct list_head *)pnode); hnode_mgr->num_nodes--; /* Decrement count of nodes created on DSP */ if ((state != NODE_ALLOCATED) || ((state == NODE_ALLOCATED) && - (hnode->node_env != (u32) NULL))) + (pnode->node_env != (u32) NULL))) hnode_mgr->num_created--; /* Free host-side resources allocated by node_create() * delete_node() fails if SM buffers not freed by client! */ - if (drv_get_node_res_element(hnode, &node_res, pr_ctxt) != - -ENOENT) - drv_proc_node_update_status(node_res, false); - delete_node(hnode, pr_ctxt); + drv_proc_node_update_status(node_res, false); + delete_node(pnode, pr_ctxt); + + /* + * Release all Node resources and its context + */ + idr_remove(pr_ctxt->node_id, ((struct node_res_object *)node_res)->id); + kfree(node_res); - drv_remove_node_res_element(node_res, pr_ctxt); /* Exit critical section */ mutex_unlock(&hnode_mgr->node_mgr_lock); proc_notify_clients(hprocessor, DSP_NODESTATECHANGE); func_end: - dev_dbg(bridge, "%s: hnode: %p status 0x%x\n", __func__, hnode, status); + dev_dbg(bridge, "%s: pnode: %p status 0x%x\n", __func__, pnode, status); return status; } From patchwork Sun May 16 15:46:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 99980 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4GFlCUg025454 for ; Sun, 16 May 2010 15:47:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753998Ab0EPPrN (ORCPT ); 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Sun, 16 May 2010 08:47:10 -0700 (PDT) Received: from localhost (a91-153-253-80.elisa-laajakaista.fi [91.153.253.80]) by mx.google.com with ESMTPS id e3sm8343663fga.9.2010.05.16.08.47.09 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 08:47:10 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Omar Ramirez Luna , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH 2/5] dspbridge: rename BRIDGE to OMAP_DSP Date: Sun, 16 May 2010 18:46:58 +0300 Message-Id: <1274024821-21178-3-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274024821-21178-1-git-send-email-felipe.contreras@gmail.com> References: <1274024821-21178-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 16 May 2010 15:47:14 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 307f8b0..ac1e4ec 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -67,7 +67,7 @@ obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) -ifneq ($(CONFIG_MPU_BRIDGE),) +ifneq ($(CONFIG_OMAP_DSP),) obj-y += dspbridge.o endif diff --git a/arch/arm/mach-omap2/dspbridge.c b/arch/arm/mach-omap2/dspbridge.c index 8d6c122..2be88a7 100644 --- a/arch/arm/mach-omap2/dspbridge.c +++ b/arch/arm/mach-omap2/dspbridge.c @@ -14,7 +14,7 @@ #include #include "prm.h" #include "cm.h" -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS #include #endif @@ -23,7 +23,7 @@ static struct platform_device *dspbridge_pdev; static struct dspbridge_platform_data dspbridge_pdata __initdata = { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS .dsp_set_min_opp = omap_pm_dsp_set_min_opp, .dsp_get_opp = omap_pm_dsp_get_opp, .cpu_set_freq = omap_pm_cpu_set_freq, @@ -46,7 +46,7 @@ static int __init dspbridge_init(void) pdata->phys_mempool_base = dspbridge_get_mempool_base(); if (pdata->phys_mempool_base) { - pdata->phys_mempool_size = CONFIG_BRIDGE_MEMPOOL_SIZE; + pdata->phys_mempool_size = CONFIG_OMAP_DSP_MEMPOOL_SIZE; pr_info("%s: %x bytes @ %x\n", __func__, pdata->phys_mempool_size, pdata->phys_mempool_base); } diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c index fbbcb5c..0ab3b86 100644 --- a/arch/arm/mach-omap2/omap3-iommu.c +++ b/arch/arm/mach-omap2/omap3-iommu.c @@ -31,7 +31,7 @@ static struct iommu_device devices[] = { .clk_name = "cam_ick", }, }, -#if defined(CONFIG_MPU_BRIDGE_IOMMU) +#if defined(CONFIG_OMAP_DSP_IOMMU) { .base = 0x5d000000, .irq = 28, diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index b552976..95380cc 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -30,14 +30,14 @@ #include #include -#if defined(CONFIG_MPU_BRIDGE) || defined(CONFIG_MPU_BRIDGE_MODULE) +#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) static unsigned long dspbridge_phys_mempool_base; void dspbridge_reserve_sdram(void) { void *va; - unsigned long size = CONFIG_BRIDGE_MEMPOOL_SIZE; + unsigned long size = CONFIG_OMAP_DSP_MEMPOOL_SIZE; if (!size) return; diff --git a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h index 7a728b1..ddd4f43 100644 --- a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h @@ -99,7 +99,7 @@ struct shm { struct opp_rqst_struct opp_request; /* load monitor information structure */ struct load_mon_struct load_mon_info; -#ifdef CONFIG_BRIDGE_WDT3 +#ifdef CONFIG_OMAP_DSP_WDT3 /* Flag for WDT enable/disable F/I clocks */ u32 wdt_setclocks; u32 wdt_overflow; /* WDT overflow time */ diff --git a/arch/arm/plat-omap/include/dspbridge/dbc.h b/arch/arm/plat-omap/include/dspbridge/dbc.h index 76f049e..6277b03 100644 --- a/arch/arm/plat-omap/include/dspbridge/dbc.h +++ b/arch/arm/plat-omap/include/dspbridge/dbc.h @@ -26,7 +26,7 @@ #define DBC_ /* Assertion Macros: */ -#ifdef CONFIG_BRIDGE_DEBUG +#ifdef CONFIG_OMAP_DSP_DEBUG #define DBC_ASSERT(exp) \ if (!(exp)) \ diff --git a/arch/arm/plat-omap/include/dspbridge/drv.h b/arch/arm/plat-omap/include/dspbridge/drv.h index 7de3323..1d1ba98 100644 --- a/arch/arm/plat-omap/include/dspbridge/drv.h +++ b/arch/arm/plat-omap/include/dspbridge/drv.h @@ -402,7 +402,7 @@ extern dsp_status drv_release_resources(IN u32 dw_context, */ dsp_status drv_request_bridge_res_dsp(void **phost_resources); -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY void bridge_recover_schedule(void); #endif diff --git a/arch/arm/plat-omap/include/dspbridge/host_os.h b/arch/arm/plat-omap/include/dspbridge/host_os.h index 2834304..22886a3 100644 --- a/arch/arm/plat-omap/include/dspbridge/host_os.h +++ b/arch/arm/plat-omap/include/dspbridge/host_os.h @@ -77,12 +77,10 @@ struct dspbridge_platform_data { extern struct platform_device *omap_dspbridge_dev; extern struct device *bridge; -#if defined(CONFIG_MPU_BRIDGE) || defined(CONFIG_MPU_BRIDGE_MODULE) +#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) extern void dspbridge_reserve_sdram(void); #else -static inline void dspbridge_reserve_sdram(void) -{ -} +static inline void dspbridge_reserve_sdram(void) { } #endif extern unsigned long dspbridge_get_mempool_base(void); diff --git a/arch/arm/plat-omap/include/dspbridge/io_sm.h b/arch/arm/plat-omap/include/dspbridge/io_sm.h index ce87eb3..732aa4f 100644 --- a/arch/arm/plat-omap/include/dspbridge/io_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/io_sm.h @@ -41,7 +41,7 @@ #define IO_SET_LONG(pContext, type, base, field, value) (base->field = value) #define IO_GET_LONG(pContext, type, base, field) (base->field) -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS /* The maximum number of OPPs that are supported */ extern s32 dsp_max_opps; /* The Vdd1 opp table information */ diff --git a/drivers/Makefile b/drivers/Makefile index 1a40bfe..7074b57 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_CONNECTOR) += connector/ obj-$(CONFIG_FB_I810) += video/i810/ obj-$(CONFIG_FB_INTEL) += video/intelfb/ -obj-$(CONFIG_MPU_BRIDGE) += dsp/bridge/ +obj-$(CONFIG_OMAP_DSP) += dsp/bridge/ obj-y += serial/ obj-$(CONFIG_PARPORT) += parport/ diff --git a/drivers/dsp/bridge/Kconfig b/drivers/dsp/bridge/Kconfig index 6268f44..75c1a1c 100644 --- a/drivers/dsp/bridge/Kconfig +++ b/drivers/dsp/bridge/Kconfig @@ -2,7 +2,7 @@ # DSP Bridge Driver Support # -menuconfig MPU_BRIDGE +menuconfig OMAP_DSP tristate "DSP Bridge driver" default n select OMAP_MBOX_FWK @@ -14,9 +14,9 @@ menuconfig MPU_BRIDGE This driver depends on OMAP Mailbox (OMAP_MBOX_FWK). -config BRIDGE_DVFS +config OMAP_DSP_DVFS bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)" - depends on MPU_BRIDGE && OMAP_PM_SRF && CPU_FREQ + depends on OMAP_DSP && OMAP_PM_SRF && CPU_FREQ default n help DVFS allows DSP Bridge to initiate the operating point change to @@ -24,30 +24,30 @@ config BRIDGE_DVFS performance and power consumption to the current processing requirements. -config BRIDGE_MEMPOOL_SIZE +config OMAP_DSP_MEMPOOL_SIZE hex "Physical memory pool size (Byte)" - depends on MPU_BRIDGE + depends on OMAP_DSP default 0x600000 help Allocate specified size of memory at booting time to avoid allocation failure under heavy memory fragmentation after some use time. -config BRIDGE_DEBUG +config OMAP_DSP_DEBUG bool "DSP Bridge Debug Support" - depends on MPU_BRIDGE + depends on OMAP_DSP help Say Y to enable Bridge debugging capabilities -config BRIDGE_RECOVERY +config OMAP_DSP_RECOVERY bool "DSP Recovery Support" - depends on MPU_BRIDGE + depends on OMAP_DSP help In case of DSP fatal error, BRIDGE driver will try to recover itself. -config BRIDGE_CACHE_LINE_CHECK +config OMAP_DSP_CACHE_LINE_CHECK bool "Check buffers to be 128 byte aligned" - depends on MPU_BRIDGE + depends on OMAP_DSP default n help When the DSP processes data, the DSP cache controller loads 128-Byte @@ -59,29 +59,29 @@ config BRIDGE_CACHE_LINE_CHECK This can lead to heap corruption. Say Y, to enforce the check for 128 byte alignment, buffers failing this check will be rejected. -config BRIDGE_WDT3 +config OMAP_DSP_WDT3 bool "Enable WDT3 interruptions" - depends on MPU_BRIDGE + depends on OMAP_DSP default n help WTD3 is managed by DSP and once it is enabled, DSP side bridge is in charge of refreshing the timer before overflow, if the DSP hangs MPU will caught the interrupt and try to recover DSP. -config WDT_TIMEOUT +config OMAP_DSP_WDT_TIMEOUT int "DSP watchdog timer timeout (in secs)" - depends on BRIDGE_WDT3 + depends on OMAP_DSP_WDT3 default 5 help Watchdog timer timeout value, after that time if the watchdog timer counter is not reset the wdt overflow interrupt will be triggered comment "Bridge Notifications" - depends on MPU_BRIDGE + depends on OMAP_DSP -config BRIDGE_NTFY_PWRERR +config OMAP_DSP_NTFY_PWRERR bool "Notify DSP Power Error" - depends on MPU_BRIDGE + depends on OMAP_DSP help Enable notifications to registered clients on the event of power errror trying to suspend bridge driver. Say Y, to signal this event as a fatal diff --git a/drivers/dsp/bridge/Makefile b/drivers/dsp/bridge/Makefile index 39624d4..1a2b86f 100644 --- a/drivers/dsp/bridge/Makefile +++ b/drivers/dsp/bridge/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_MPU_BRIDGE) += bridgedriver.o +obj-$(CONFIG_OMAP_DSP) += bridgedriver.o libgen = gen/gb.o gen/gs.o gen/gh.o gen/uuidutil.o libservices = services/sync.o services/cfg.o \ diff --git a/drivers/dsp/bridge/core/io_sm.c b/drivers/dsp/bridge/core/io_sm.c index d6c1a98..161b598 100644 --- a/drivers/dsp/bridge/core/io_sm.c +++ b/drivers/dsp/bridge/core/io_sm.c @@ -1725,7 +1725,7 @@ void io_intr_dsp2(IN struct io_mgr *pio_mgr, IN u16 mb_val) */ dsp_status io_sh_msetting(struct io_mgr *hio_mgr, u8 desc, void *pargs) { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS u32 i; struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; diff --git a/drivers/dsp/bridge/core/tiomap3430_pwr.c b/drivers/dsp/bridge/core/tiomap3430_pwr.c index 1897c50..5c5565a 100644 --- a/drivers/dsp/bridge/core/tiomap3430_pwr.c +++ b/drivers/dsp/bridge/core/tiomap3430_pwr.c @@ -52,7 +52,7 @@ dsp_status handle_constraints_set(struct bridge_dev_context *dev_context, IN void *pargs) { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS u32 *constraint_val; struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; @@ -65,7 +65,7 @@ dsp_status handle_constraints_set(struct bridge_dev_context *dev_context, /* Set the new opp value */ if (pdata->dsp_set_min_opp) (*pdata->dsp_set_min_opp) ((u32) *(constraint_val + 1)); -#endif /* #ifdef CONFIG_BRIDGE_DVFS */ +#endif /* #ifdef CONFIG_OMAP_DSP_DVFS */ return DSP_SOK; } @@ -79,7 +79,7 @@ dsp_status handle_hibernation_from_dsp(struct bridge_dev_context *dev_context) #ifdef CONFIG_PM u16 timeout = PWRSTST_TIMEOUT / 10; u32 pwr_state; -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS u32 opplevel; struct io_mgr *hio_mgr; #endif @@ -115,7 +115,7 @@ dsp_status handle_hibernation_from_dsp(struct bridge_dev_context *dev_context) if (DSP_SUCCEEDED(status)) { /* Update the Bridger Driver state */ dev_context->dw_brd_state = BRD_DSP_HIBERNATION; -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr); if (DSP_FAILED(status)) @@ -129,7 +129,7 @@ dsp_status handle_hibernation_from_dsp(struct bridge_dev_context *dev_context) if (pdata->dsp_set_min_opp) (*pdata->dsp_set_min_opp) (VDD1_OPP1); status = DSP_SOK; -#endif /* CONFIG_BRIDGE_DVFS */ +#endif /* CONFIG_OMAP_DSP_DVFS */ } } #endif @@ -145,9 +145,9 @@ dsp_status sleep_dsp(struct bridge_dev_context *dev_context, IN u32 dw_cmd, { dsp_status status = DSP_SOK; #ifdef CONFIG_PM -#ifdef CONFIG_BRIDGE_NTFY_PWRERR +#ifdef CONFIG_OMAP_DSP_NTFY_PWRERR struct deh_mgr *hdeh_mgr; -#endif /* CONFIG_BRIDGE_NTFY_PWRERR */ +#endif /* CONFIG_OMAP_DSP_NTFY_PWRERR */ u16 timeout = PWRSTST_TIMEOUT / 10; u32 pwr_state, target_pwr_state; struct dspbridge_platform_data *pdata = @@ -209,10 +209,10 @@ dsp_status sleep_dsp(struct bridge_dev_context *dev_context, IN u32 dw_cmd, if (!timeout) { pr_err("%s: Timed out waiting for DSP off mode, state %x\n", __func__, pwr_state); -#ifdef CONFIG_BRIDGE_NTFY_PWRERR +#ifdef CONFIG_OMAP_DSP_NTFY_PWRERR dev_get_deh_mgr(dev_context->hdev_obj, &hdeh_mgr); bridge_deh_notify(hdeh_mgr, DSP_PWRERROR, 0); -#endif /* CONFIG_BRIDGE_NTFY_PWRERR */ +#endif /* CONFIG_OMAP_DSP_NTFY_PWRERR */ return -ETIMEDOUT; } else { /* Update the Bridger Driver state */ @@ -228,7 +228,7 @@ dsp_status sleep_dsp(struct bridge_dev_context *dev_context, IN u32 dw_cmd, status = dsp_clock_disable_all(dev_context->dsp_per_clks); if (DSP_FAILED(status)) return status; -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS else if (target_pwr_state == PWRDM_POWER_OFF) { /* * Set the OPP to low level before moving to OFF mode @@ -236,7 +236,7 @@ dsp_status sleep_dsp(struct bridge_dev_context *dev_context, IN u32 dw_cmd, if (pdata->dsp_set_min_opp) (*pdata->dsp_set_min_opp) (VDD1_OPP1); } -#endif /* CONFIG_BRIDGE_DVFS */ +#endif /* CONFIG_OMAP_DSP_DVFS */ } #endif /* CONFIG_PM */ return status; @@ -336,7 +336,7 @@ dsp_status dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context, */ dsp_status pre_scale_dsp(struct bridge_dev_context *dev_context, IN void *pargs) { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS u32 level; u32 voltage_domain; @@ -358,7 +358,7 @@ dsp_status pre_scale_dsp(struct bridge_dev_context *dev_context, IN void *pargs) } else { return -EPERM; } -#endif /* #ifdef CONFIG_BRIDGE_DVFS */ +#endif /* #ifdef CONFIG_OMAP_DSP_DVFS */ return DSP_SOK; } @@ -371,7 +371,7 @@ dsp_status post_scale_dsp(struct bridge_dev_context *dev_context, IN void *pargs) { dsp_status status = DSP_SOK; -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS u32 level; u32 voltage_domain; struct io_mgr *hio_mgr; @@ -401,7 +401,7 @@ dsp_status post_scale_dsp(struct bridge_dev_context *dev_context, } else { status = -EPERM; } -#endif /* #ifdef CONFIG_BRIDGE_DVFS */ +#endif /* #ifdef CONFIG_OMAP_DSP_DVFS */ return status; } diff --git a/drivers/dsp/bridge/core/tiomap_io.c b/drivers/dsp/bridge/core/tiomap_io.c index 00610df..1665003 100644 --- a/drivers/dsp/bridge/core/tiomap_io.c +++ b/drivers/dsp/bridge/core/tiomap_io.c @@ -389,7 +389,7 @@ dsp_status write_ext_dsp_data(struct bridge_dev_context *dev_context, dsp_status sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS u32 opplevel = 0; #endif struct dspbridge_platform_data *pdata = @@ -406,7 +406,7 @@ dsp_status sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION || dev_context->dw_brd_state == BRD_HIBERNATION) { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS if (pdata->dsp_get_opp) opplevel = (*pdata->dsp_get_opp) (); if (opplevel == VDD1_OPP1) { diff --git a/drivers/dsp/bridge/core/ue_deh.c b/drivers/dsp/bridge/core/ue_deh.c index 315672b..6611929 100644 --- a/drivers/dsp/bridge/core/ue_deh.c +++ b/drivers/dsp/bridge/core/ue_deh.c @@ -293,7 +293,7 @@ void bridge_deh_notify(struct deh_mgr *deh, int event, int info) /* Filter subsequent notifications when an error occurs */ if (dev_context->dw_brd_state != BRD_ERROR) { ntfy_notify(deh->ntfy_obj, event); -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY bridge_recover_schedule(); #endif } diff --git a/drivers/dsp/bridge/core/wdt.c b/drivers/dsp/bridge/core/wdt.c index 4637afb..d1c8105 100644 --- a/drivers/dsp/bridge/core/wdt.c +++ b/drivers/dsp/bridge/core/wdt.c @@ -25,8 +25,7 @@ #include #include - -#ifdef CONFIG_BRIDGE_WDT3 +#ifdef CONFIG_OMAP_DSP_WDT3 static struct dsp_wdt_setting dsp_wdt; void dsp_wdt_dpc(unsigned long data) @@ -82,7 +81,7 @@ int dsp_wdt_init(void) void dsp_wdt_sm_set(void *data) { dsp_wdt.sm_wdt = data; - dsp_wdt.sm_wdt->wdt_overflow = CONFIG_WDT_TIMEOUT; + dsp_wdt.sm_wdt->wdt_overflow = CONFIG_OMAP_DSP_WDT_TIMEOUT; } @@ -128,6 +127,7 @@ void dsp_wdt_enable(bool enable) } #else + void dsp_wdt_enable(bool enable) { } @@ -145,4 +145,3 @@ void dsp_wdt_exit(void) { } #endif - diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c index a8e711a..2ea8e91 100644 --- a/drivers/dsp/bridge/rmgr/drv.c +++ b/drivers/dsp/bridge/rmgr/drv.c @@ -524,7 +524,7 @@ dsp_status drv_get_dev_object(u32 index, struct drv_object *hdrv_obj, struct dev_object **phDevObject) { dsp_status status = DSP_SOK; -#ifdef CONFIG_BRIDGE_DEBUG +#ifdef CONFIG_OMAP_DSP_DEBUG /* used only for Assertions and debug messages */ struct drv_object *pdrv_obj = (struct drv_object *)hdrv_obj; #endif diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c index 00134e1..22ecfb3 100644 --- a/drivers/dsp/bridge/rmgr/drv_interface.c +++ b/drivers/dsp/bridge/rmgr/drv_interface.c @@ -63,7 +63,7 @@ #include #include -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS #include #endif @@ -89,7 +89,7 @@ static char *base_img; char *iva_img; static s32 shm_size = 0x500000; /* 5 MB */ static int tc_wordswapon; /* Default value is always false */ -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY #define REC_TIMEOUT 5000 /*recovery timeout in msecs */ static atomic_t bridge_cref; /* number of bridge open handles */ static struct workqueue_struct *bridge_rec_queue; @@ -149,13 +149,13 @@ static const struct file_operations bridge_fops = { #ifdef CONFIG_PM static u32 time_out = 1000; -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS s32 dsp_max_opps = VDD1_OPP5; #endif /* Maximum Opps that can be requested by IVA */ /*vdd1 rate table */ -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS const struct omap_opp vdd1_rate_table_bridge[] = { {0, 0, 0}, /*OPP1 */ @@ -188,7 +188,7 @@ u32 vdd1_dsp_freq[6][4] = { {0, 430000, 355000, 430000}, }; -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY static void bridge_recover(struct work_struct *work) { struct dev_object *dev; @@ -215,7 +215,7 @@ void bridge_recover_schedule(void) queue_work(bridge_rec_queue, &bridge_recovery_work); } #endif -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS static int dspbridge_scale_notification(struct notifier_block *op, unsigned long val, void *ptr) { @@ -240,7 +240,7 @@ static int __devinit omap34_xx_bridge_probe(struct platform_device *pdev) u32 init_status = DSP_SOK; dev_t dev = 0; int result; -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS int i = 0; #endif struct dspbridge_platform_data *pdata = pdev->dev.platform_data; @@ -321,7 +321,7 @@ static int __devinit omap34_xx_bridge_probe(struct platform_device *pdev) dev_dbg(bridge, "%s: TC Word Swap is enabled\n", __func__); if (DSP_SUCCEEDED(init_status)) { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS for (i = 0; i < 6; i++) pdata->mpu_speed[i] = vdd1_rate_table_bridge[i].rate; @@ -340,7 +340,7 @@ static int __devinit omap34_xx_bridge_probe(struct platform_device *pdev) } } -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY bridge_rec_queue = create_workqueue("bridge_rec_queue"); INIT_WORK(&bridge_recovery_work, bridge_recover); INIT_COMPLETION(bridge_comp); @@ -367,12 +367,12 @@ static int __devexit omap34_xx_bridge_remove(struct platform_device *pdev) if (DSP_FAILED(status)) goto func_cont; -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_OMAP_DSP_DVFS if (!cpufreq_unregister_notifier(&iva_clk_notifier, CPUFREQ_TRANSITION_NOTIFIER)) pr_err("%s: clk_notifier_unregister failed for iva2_ck\n", __func__); -#endif /* #ifdef CONFIG_BRIDGE_DVFS */ +#endif /* #ifdef CONFIG_OMAP_DSP_DVFS */ if (driver_context) { /* Put the DSP in reset state */ @@ -464,7 +464,7 @@ static int bridge_open(struct inode *ip, struct file *filp) * process context list. */ -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY if (recover) { if (filp->f_flags & O_NONBLOCK || wait_for_completion_interruptible(&bridge_open_comp)) @@ -485,7 +485,7 @@ static int bridge_open(struct inode *ip, struct file *filp) } filp->private_data = pr_ctxt; -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY if (!status) atomic_inc(&bridge_cref); #endif @@ -515,7 +515,7 @@ static int bridge_release(struct inode *ip, struct file *filp) filp->private_data = NULL; err: -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY if (!atomic_dec_return(&bridge_cref)) complete(&bridge_comp); #endif @@ -531,7 +531,7 @@ static long bridge_ioctl(struct file *filp, unsigned int code, union Trapped_Args buf_in; DBC_REQUIRE(filp != NULL); -#ifdef CONFIG_BRIDGE_RECOVERY +#ifdef CONFIG_OMAP_DSP_RECOVERY if (recover) { status = -EIO; goto err; diff --git a/drivers/dsp/bridge/rmgr/node.c b/drivers/dsp/bridge/rmgr/node.c index 23aed68..43f3890 100644 --- a/drivers/dsp/bridge/rmgr/node.c +++ b/drivers/dsp/bridge/rmgr/node.c @@ -1154,7 +1154,7 @@ dsp_status node_create(struct node_object *hnode) u32 proc_id = 255; struct dsp_processorstate proc_state; struct proc_object *hprocessor; -#if defined(CONFIG_BRIDGE_DVFS) && !defined(CONFIG_CPU_FREQ) +#if defined(CONFIG_OMAP_DSP_DVFS) && !defined(CONFIG_CPU_FREQ) struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; #endif @@ -1206,7 +1206,7 @@ dsp_status node_create(struct node_object *hnode) if (DSP_SUCCEEDED(status)) { /* If node's create function is not loaded, load it */ /* Boost the OPP level to max level that DSP can be requested */ -#if defined(CONFIG_BRIDGE_DVFS) && !defined(CONFIG_CPU_FREQ) +#if defined(CONFIG_OMAP_DSP_DVFS) && !defined(CONFIG_CPU_FREQ) if (pdata->cpu_set_freq) (*pdata->cpu_set_freq) (pdata->mpu_speed[VDD1_OPP3]); #endif @@ -1224,7 +1224,7 @@ dsp_status node_create(struct node_object *hnode) __func__, status); } /* Request the lowest OPP level */ -#if defined(CONFIG_BRIDGE_DVFS) && !defined(CONFIG_CPU_FREQ) +#if defined(CONFIG_OMAP_DSP_DVFS) && !defined(CONFIG_CPU_FREQ) if (pdata->cpu_set_freq) (*pdata->cpu_set_freq) (pdata->mpu_speed[VDD1_OPP1]); #endif diff --git a/drivers/dsp/bridge/rmgr/proc.c b/drivers/dsp/bridge/rmgr/proc.c index 1cccc89..7920f22 100644 --- a/drivers/dsp/bridge/rmgr/proc.c +++ b/drivers/dsp/bridge/rmgr/proc.c @@ -817,7 +817,7 @@ dsp_status proc_load(void *hprocessor, IN CONST s32 argc_index, struct timeval tv2; #endif -#if defined(CONFIG_BRIDGE_DVFS) && !defined(CONFIG_CPU_FREQ) +#if defined(CONFIG_OMAP_DSP_DVFS) && !defined(CONFIG_CPU_FREQ) struct dspbridge_platform_data *pdata = omap_dspbridge_dev->dev.platform_data; #endif @@ -952,7 +952,7 @@ dsp_status proc_load(void *hprocessor, IN CONST s32 argc_index, /* Now, attempt to load an exec: */ /* Boost the OPP level to Maximum level supported by baseport */ -#if defined(CONFIG_BRIDGE_DVFS) && !defined(CONFIG_CPU_FREQ) +#if defined(CONFIG_OMAP_DSP_DVFS) && !defined(CONFIG_CPU_FREQ) if (pdata->cpu_set_freq) (*pdata->cpu_set_freq) (pdata->mpu_speed[VDD1_OPP5]); #endif @@ -970,7 +970,7 @@ dsp_status proc_load(void *hprocessor, IN CONST s32 argc_index, } } /* Requesting the lowest opp supported */ -#if defined(CONFIG_BRIDGE_DVFS) && !defined(CONFIG_CPU_FREQ) +#if defined(CONFIG_OMAP_DSP_DVFS) && !defined(CONFIG_CPU_FREQ) if (pdata->cpu_set_freq) (*pdata->cpu_set_freq) (pdata->mpu_speed[VDD1_OPP1]); #endif @@ -1069,7 +1069,7 @@ dsp_status proc_map(void *hprocessor, void *pmpu_addr, u32 ul_size, struct proc_object *p_proc_object = (struct proc_object *)hprocessor; struct dmm_map_object *map_obj; -#ifdef CONFIG_BRIDGE_CACHE_LINE_CHECK +#ifdef CONFIG_OMAP_DSP_CACHE_LINE_CHECK if ((ul_map_attr & BUFMODE_MASK) != RBUF) { if (!IS_ALIGNED((u32)pmpu_addr, DSP_CACHE_LINE) || !IS_ALIGNED(ul_size, DSP_CACHE_LINE)) { From patchwork Mon Jul 12 22:56:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111569 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMk016827 for ; Mon, 12 Jul 2010 23:00:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756182Ab0GLW4r (ORCPT ); Mon, 12 Jul 2010 18:56:47 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:56985 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755980Ab0GLW4g (ORCPT ); Mon, 12 Jul 2010 18:56:36 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuRs3012361 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:27 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuRdP001625; Mon, 12 Jul 2010 17:56:27 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuQP07308; Mon, 12 Jul 2010 17:56:26 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id DE45CC23D; Mon, 12 Jul 2010 17:56:26 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH] staging: tidspbridge: fix build error for missing variable Date: Mon, 12 Jul 2010 17:56:25 -0500 Message-Id: <1278975385-7769-1-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:05 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/gen/uuidutil.c b/drivers/staging/tidspbridge/gen/uuidutil.c index eb09bc3..070761b 100644 --- a/drivers/staging/tidspbridge/gen/uuidutil.c +++ b/drivers/staging/tidspbridge/gen/uuidutil.c @@ -58,6 +58,7 @@ static s32 uuid_hex_to_bin(char *buf, s32 len) { s32 i; s32 result = 0; + int value; for (i = 0; i < len; i++) { value = hex_to_bin(*buf++); From patchwork Mon Jul 12 22:56:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111568 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMj016827 for ; Mon, 12 Jul 2010 23:00:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756130Ab0GLW4p (ORCPT ); Mon, 12 Jul 2010 18:56:45 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39468 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755963Ab0GLW41 (ORCPT ); Mon, 12 Jul 2010 18:56:27 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuEM2003028 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:14 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuDUv016493; Mon, 12 Jul 2010 17:56:13 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuCP07271; Mon, 12 Jul 2010 17:56:12 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 3FE7DC25B; Mon, 12 Jul 2010 17:56:10 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 07/11] staging: tidspbridge: replace CONST with c standard const Date: Mon, 12 Jul 2010 17:56:05 -0500 Message-Id: <1278975369-7687-8-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:04 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index b669bc0..25fe1a2 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -383,7 +383,7 @@ func_cont: */ int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, - IN CONST struct chnl_mgrattrs *pMgrAttrs) + IN const struct chnl_mgrattrs *pMgrAttrs) { int status = 0; struct chnl_mgr *chnl_mgr_obj = NULL; @@ -777,7 +777,7 @@ int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 dwTimeOut, */ int bridge_chnl_open(OUT struct chnl_object **phChnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, - u32 uChnlId, CONST IN struct chnl_attr *pattrs) + u32 uChnlId, const IN struct chnl_attr *pattrs) { int status = 0; struct chnl_mgr *chnl_mgr_obj = hchnl_mgr; diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 280b22d..73ba306 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -163,7 +163,7 @@ static int register_shm_segs(struct io_mgr *hio_mgr, */ int bridge_io_create(OUT struct io_mgr **phIOMgr, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs) + IN const struct io_attrs *pMgrAttrs) { int status = 0; struct io_mgr *pio_mgr = NULL; diff --git a/drivers/staging/tidspbridge/core/msg_sm.c b/drivers/staging/tidspbridge/core/msg_sm.c index 7b7a4be..576dac0 100644 --- a/drivers/staging/tidspbridge/core/msg_sm.c +++ b/drivers/staging/tidspbridge/core/msg_sm.c @@ -383,7 +383,7 @@ func_end: * Put a message onto a msg_ctrl queue. */ int bridge_msg_put(struct msg_queue *msg_queue_obj, - IN CONST struct dsp_msg *pmsg, u32 utimeout) + IN const struct dsp_msg *pmsg, u32 utimeout) { struct msg_frame *msg_frame_obj; struct msg_mgr *hmsg_mgr; diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 33fcef5..0a4b054 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -237,7 +237,7 @@ static void bad_page_dump(u32 pa, struct page *pg) * Bridge Driver entry point. */ void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, - IN CONST char *driver_file_name) + IN const char *driver_file_name) { DBC_REQUIRE(driver_file_name != NULL); diff --git a/drivers/staging/tidspbridge/include/dspbridge/chnl.h b/drivers/staging/tidspbridge/include/dspbridge/chnl.h index 89315dc..4e3d99e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/chnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/chnl.h @@ -79,7 +79,7 @@ extern int chnl_close(struct chnl_object *chnl_obj); */ extern int chnl_create(OUT struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, - IN CONST struct chnl_mgrattrs *pMgrAttrs); + IN const struct chnl_mgrattrs *pMgrAttrs); /* * ======== chnl_destroy ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index 493ff56..5b902c1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -87,7 +87,7 @@ extern void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, */ extern int cmm_create(OUT struct cmm_object **ph_cmm_mgr, struct dev_object *hdev_obj, - IN CONST struct cmm_mgrattrs *pMgrAttrs); + IN const struct cmm_mgrattrs *pMgrAttrs); /* * ======== cmm_destroy ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index 6914247..4edc6a1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -93,7 +93,7 @@ extern void cod_close(struct cod_libraryobj *lib); */ extern int cod_create(OUT struct cod_manager **phManager, char *pstrZLFile, - IN OPTIONAL CONST struct cod_attrs *attrs); + IN OPTIONAL const struct cod_attrs *attrs); /* * ======== cod_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index 434c128..126adaa 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -91,7 +91,7 @@ extern u32 dev_brd_write_fxn(void *pArb, */ extern int dev_create_device(OUT struct dev_object **phDevObject, - IN CONST char *driver_file_name, + IN const char *driver_file_name, struct cfg_devnode *dev_node_obj); /* @@ -126,8 +126,8 @@ extern int dev_create_device(OUT struct dev_object */ extern int dev_create_iva_device(OUT struct dev_object **phDevObject, - IN CONST char *driver_file_name, - IN CONST struct cfg_hostres + IN const char *driver_file_name, + IN const struct cfg_hostres *pHostConfig, struct cfg_devnode *dev_node_obj); @@ -490,7 +490,7 @@ extern int dev_get_node_manager(struct dev_object * 0: *pul_value contains the symbol value; */ extern int dev_get_symbol(struct dev_object *hdev_obj, - IN CONST char *pstrSym, OUT u32 * pul_value); + IN const char *pstrSym, OUT u32 * pul_value); /* * ======== dev_get_bridge_context ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/disp.h b/drivers/staging/tidspbridge/include/dspbridge/disp.h index 2fd14b0..421b260 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/disp.h +++ b/drivers/staging/tidspbridge/include/dspbridge/disp.h @@ -50,7 +50,7 @@ */ extern int disp_create(OUT struct disp_object **phDispObject, struct dev_object *hdev_obj, - IN CONST struct disp_attr *pDispAttrs); + IN const struct disp_attr *pDispAttrs); /* * ======== disp_delete ======== @@ -147,7 +147,7 @@ extern int disp_node_create(struct disp_object *hDispObject, struct node_object *hnode, u32 ul_fxn_addr, u32 ul_create_fxn, - IN CONST struct node_createargs + IN const struct node_createargs *pargs, OUT nodeenv *pNodeEnv); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/dmm.h b/drivers/staging/tidspbridge/include/dspbridge/dmm.h index 1ce1b65..1581ebb 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dmm.h @@ -59,7 +59,7 @@ extern int dmm_delete_tables(struct dmm_object *dmm_mgr); extern int dmm_create(OUT struct dmm_object **phDmmMgr, struct dev_object *hdev_obj, - IN CONST struct dmm_mgrattrs *pMgrAttrs); + IN const struct dmm_mgrattrs *pMgrAttrs); extern bool dmm_init(void); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h index 5661bca..0eb0d9d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h @@ -26,7 +26,7 @@ extern int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, - IN CONST struct chnl_mgrattrs + IN const struct chnl_mgrattrs *pMgrAttrs); extern int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr); @@ -35,7 +35,7 @@ extern int bridge_chnl_open(OUT struct chnl_object **phChnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, - CONST IN OPTIONAL struct chnl_attr + const IN OPTIONAL struct chnl_attr *pattrs); extern int bridge_chnl_close(struct chnl_object *chnl_obj); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 536816b..d92f82c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -326,7 +326,7 @@ typedef int(*fxn_chnl_create) (OUT struct chnl_mgr **phChnlMgr, struct dev_object * hdev_obj, - IN CONST struct + IN const struct chnl_mgrattrs * pMgrAttrs); /* @@ -411,7 +411,7 @@ typedef int(*fxn_chnl_open) (OUT struct chnl_object struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, - CONST IN OPTIONAL struct + const IN OPTIONAL struct chnl_attr * pattrs); /* @@ -745,7 +745,7 @@ typedef int(*fxn_dev_destroy) (struct bridge_dev_context *hDevContext); */ typedef int(*fxn_io_create) (OUT struct io_mgr **phIOMgr, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs); + IN const struct io_attrs *pMgrAttrs); /* * ======== bridge_io_destroy ======== @@ -915,7 +915,7 @@ typedef int(*fxn_msg_get) (struct msg_queue *msg_queue_obj, * Ensures: */ typedef int(*fxn_msg_put) (struct msg_queue *msg_queue_obj, - IN CONST struct dsp_msg *pmsg, u32 utimeout); + IN const struct dsp_msg *pmsg, u32 utimeout); /* * ======== bridge_msg_register_notify ======== @@ -1048,6 +1048,6 @@ struct bridge_drv_interface { * Called during the Device_Init phase. */ void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, - IN CONST char *driver_file_name); + IN const char *driver_file_name); #endif /* DSPDEFS_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspio.h b/drivers/staging/tidspbridge/include/dspbridge/dspio.h index 275697a..563b779 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspio.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspio.h @@ -28,7 +28,7 @@ extern int bridge_io_create(OUT struct io_mgr **phIOMgr, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs); + IN const struct io_attrs *pMgrAttrs); extern int bridge_io_destroy(struct io_mgr *hio_mgr); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h index a10634e..d01d756 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h @@ -42,7 +42,7 @@ extern int bridge_msg_get(struct msg_queue *msg_queue_obj, struct dsp_msg *pmsg, u32 utimeout); extern int bridge_msg_put(struct msg_queue *msg_queue_obj, - IN CONST struct dsp_msg *pmsg, u32 utimeout); + IN const struct dsp_msg *pmsg, u32 utimeout); extern int bridge_msg_register_notify(struct msg_queue *msg_queue_obj, u32 event_mask, diff --git a/drivers/staging/tidspbridge/include/dspbridge/io.h b/drivers/staging/tidspbridge/include/dspbridge/io.h index e1610f1..0a25829 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io.h @@ -51,7 +51,7 @@ */ extern int io_create(OUT struct io_mgr **phIOMgr, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs); + IN const struct io_attrs *pMgrAttrs); /* * ======== io_destroy ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldr.h b/drivers/staging/tidspbridge/include/dspbridge/nldr.h index b1dbccd..14bea86 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldr.h @@ -26,14 +26,14 @@ #define NLDR_ extern int nldr_allocate(struct nldr_object *nldr_obj, - void *priv_ref, IN CONST struct dcd_nodeprops + void *priv_ref, IN const struct dcd_nodeprops *node_props, OUT struct nldr_nodeobject **phNldrNode, IN bool *pf_phase_split); extern int nldr_create(OUT struct nldr_object **phNldr, struct dev_object *hdev_obj, - IN CONST struct nldr_attrs *pattrs); + IN const struct nldr_attrs *pattrs); extern void nldr_delete(struct nldr_object *nldr_obj); extern void nldr_exit(void); diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h index 9be0483..abe44a5 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h @@ -129,7 +129,7 @@ enum nldr_phase { */ typedef int(*nldr_allocatefxn) (struct nldr_object *nldr_obj, void *priv_ref, - IN CONST struct dcd_nodeprops + IN const struct dcd_nodeprops * node_props, OUT struct nldr_nodeobject **phNldrNode, @@ -158,7 +158,7 @@ typedef int(*nldr_allocatefxn) (struct nldr_object *nldr_obj, */ typedef int(*nldr_createfxn) (OUT struct nldr_object **phNldr, struct dev_object *hdev_obj, - IN CONST struct nldr_attrs *pattrs); + IN const struct nldr_attrs *pattrs); /* * ======== nldr_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index e9d8439..4c6c31b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -56,9 +56,9 @@ * error: *ph_node == NULL. */ extern int node_allocate(struct proc_object *hprocessor, - IN CONST struct dsp_uuid *pNodeId, - OPTIONAL IN CONST struct dsp_cbdata - *pargs, OPTIONAL IN CONST struct dsp_nodeattrin + IN const struct dsp_uuid *pNodeId, + OPTIONAL IN const struct dsp_cbdata + *pargs, OPTIONAL IN const struct dsp_nodeattrin *attr_in, OUT struct node_object **ph_node, struct process_context *pr_ctxt); @@ -470,7 +470,7 @@ extern int node_pause(struct node_object *hnode); * Ensures: */ extern int node_put_message(struct node_object *hnode, - IN CONST struct dsp_msg *pmsg, u32 utimeout); + IN const struct dsp_msg *pmsg, u32 utimeout); /* * ======== node_register_notify ======== @@ -554,7 +554,7 @@ extern int node_terminate(struct node_object *hnode, * */ extern int node_get_uuid_props(void *hprocessor, - IN CONST struct dsp_uuid *pNodeId, + IN const struct dsp_uuid *pNodeId, OUT struct dsp_ndbprops *node_props); diff --git a/drivers/staging/tidspbridge/include/dspbridge/proc.h b/drivers/staging/tidspbridge/include/dspbridge/proc.h index 230828c..9ad0934 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/proc.h +++ b/drivers/staging/tidspbridge/include/dspbridge/proc.h @@ -52,7 +52,7 @@ extern char *iva_img; * When attr_in is NULL, the default timeout value is 10 seconds. */ extern int proc_attach(u32 processor_id, - OPTIONAL CONST struct dsp_processorattrin + OPTIONAL const struct dsp_processorattrin *attr_in, void **ph_processor, struct process_context *pr_ctxt); @@ -329,8 +329,8 @@ extern int proc_get_trace(void *hprocessor, u8 * pbuf, u32 max_size); * can load the processor. */ extern int proc_load(void *hprocessor, - IN CONST s32 argc_index, IN CONST char **user_args, - IN CONST char **user_envp); + IN const s32 argc_index, IN const char **user_args, + IN const char **user_envp); /* * ======== proc_register_notify ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/pwr.h b/drivers/staging/tidspbridge/include/dspbridge/pwr.h index 63ccf8c..5fc85ea 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/pwr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/pwr.h @@ -45,7 +45,7 @@ * -EPERM: General failure, unable to send sleep command to * the DSP. */ -extern int pwr_sleep_dsp(IN CONST u32 sleepCode, IN CONST u32 timeout); +extern int pwr_sleep_dsp(IN const u32 sleepCode, IN const u32 timeout); /* * ======== pwr_wake_dsp ======== @@ -66,7 +66,7 @@ extern int pwr_sleep_dsp(IN CONST u32 sleepCode, IN CONST u32 timeout); * -EPERM: General failure, unable to send wake command to * the DSP. */ -extern int pwr_wake_dsp(IN CONST u32 timeout); +extern int pwr_wake_dsp(IN const u32 timeout); /* * ======== pwr_pm_pre_scale ======== diff --git a/drivers/staging/tidspbridge/pmgr/chnl.c b/drivers/staging/tidspbridge/pmgr/chnl.c index 9007bfd..d2c089c 100644 --- a/drivers/staging/tidspbridge/pmgr/chnl.c +++ b/drivers/staging/tidspbridge/pmgr/chnl.c @@ -53,7 +53,7 @@ static u32 refs; */ int chnl_create(OUT struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, - IN CONST struct chnl_mgrattrs *pMgrAttrs) + IN const struct chnl_mgrattrs *pMgrAttrs) { int status; struct chnl_mgr *hchnl_mgr; diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index 8300f97..160aa36 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -242,7 +242,7 @@ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize, */ int cmm_create(OUT struct cmm_object **ph_cmm_mgr, struct dev_object *hdev_obj, - IN CONST struct cmm_mgrattrs *pMgrAttrs) + IN const struct cmm_mgrattrs *pMgrAttrs) { struct cmm_object *cmm_obj = NULL; int status = 0; diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index d2c8e69..61bdaa9 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -110,7 +110,7 @@ static s32 cod_f_close(struct file *filp) return 0; } -static struct file *cod_f_open(CONST char *psz_file_name, CONST char *pszMode) +static struct file *cod_f_open(const char *psz_file_name, const char *pszMode) { mm_segment_t fs; struct file *filp; @@ -217,7 +217,7 @@ void cod_close(struct cod_libraryobj *lib) * */ int cod_create(OUT struct cod_manager **phMgr, char *pstrDummyFile, - IN OPTIONAL CONST struct cod_attrs *attrs) + IN OPTIONAL const struct cod_attrs *attrs) { struct cod_manager *mgr_new; struct dbll_attrs zl_attrs; diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index 4509468..d95167d 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -132,7 +132,7 @@ u32 dev_brd_write_fxn(void *pArb, u32 ulDspAddr, void *pHostBuf, * PM board (device). */ int dev_create_device(OUT struct dev_object **phDevObject, - IN CONST char *driver_file_name, + IN const char *driver_file_name, struct cfg_devnode *dev_node_obj) { struct cfg_hostres *host_res; @@ -691,7 +691,7 @@ int dev_get_node_manager(struct dev_object *hdev_obj, * ======== dev_get_symbol ======== */ int dev_get_symbol(struct dev_object *hdev_obj, - IN CONST char *pstrSym, OUT u32 * pul_value) + IN const char *pstrSym, OUT u32 * pul_value) { int status = 0; struct cod_manager *cod_mgr; diff --git a/drivers/staging/tidspbridge/pmgr/dmm.c b/drivers/staging/tidspbridge/pmgr/dmm.c index 11bd2b5..23c932c 100644 --- a/drivers/staging/tidspbridge/pmgr/dmm.c +++ b/drivers/staging/tidspbridge/pmgr/dmm.c @@ -119,7 +119,7 @@ int dmm_create_tables(struct dmm_object *dmm_mgr, u32 addr, u32 size) */ int dmm_create(OUT struct dmm_object **phDmmMgr, struct dev_object *hdev_obj, - IN CONST struct dmm_mgrattrs *pMgrAttrs) + IN const struct dmm_mgrattrs *pMgrAttrs) { struct dmm_object *dmm_obj = NULL; int status = 0; diff --git a/drivers/staging/tidspbridge/pmgr/dspapi.c b/drivers/staging/tidspbridge/pmgr/dspapi.c index 8555aad..4667507 100644 --- a/drivers/staging/tidspbridge/pmgr/dspapi.c +++ b/drivers/staging/tidspbridge/pmgr/dspapi.c @@ -905,7 +905,7 @@ u32 procwrap_load(union Trapped_Args *args, void *pr_ctxt) if (DSP_SUCCEEDED(status)) { status = proc_load(args->args_proc_load.hprocessor, args->args_proc_load.argc_index, - (CONST char **)argv, (CONST char **)envp); + (const char **)argv, (const char **)envp); } func_cont: if (envp) { diff --git a/drivers/staging/tidspbridge/pmgr/io.c b/drivers/staging/tidspbridge/pmgr/io.c index 9f687e0..83171f1 100644 --- a/drivers/staging/tidspbridge/pmgr/io.c +++ b/drivers/staging/tidspbridge/pmgr/io.c @@ -47,7 +47,7 @@ static u32 refs; * CHNL and msg_ctrl */ int io_create(OUT struct io_mgr **phIOMgr, struct dev_object *hdev_obj, - IN CONST struct io_attrs *pMgrAttrs) + IN const struct io_attrs *pMgrAttrs) { struct bridge_drv_interface *intf_fxns; struct io_mgr *hio_mgr = NULL; diff --git a/drivers/staging/tidspbridge/rmgr/disp.c b/drivers/staging/tidspbridge/rmgr/disp.c index eedf32a..a1defff 100644 --- a/drivers/staging/tidspbridge/rmgr/disp.c +++ b/drivers/staging/tidspbridge/rmgr/disp.c @@ -89,7 +89,7 @@ static int send_message(struct disp_object *disp_obj, u32 dwTimeout, */ int disp_create(OUT struct disp_object **phDispObject, struct dev_object *hdev_obj, - IN CONST struct disp_attr *pDispAttrs) + IN const struct disp_attr *pDispAttrs) { struct disp_object *disp_obj; struct bridge_drv_interface *intf_fxns; @@ -251,7 +251,7 @@ int disp_node_change_priority(struct disp_object *disp_obj, int disp_node_create(struct disp_object *disp_obj, struct node_object *hnode, u32 ulRMSFxn, u32 ul_create_fxn, - IN CONST struct node_createargs *pargs, + IN const struct node_createargs *pargs, OUT nodeenv *pNodeEnv) { struct node_msgargs node_msg_args; diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index f59a981..b4f7620 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -324,7 +324,7 @@ static u32 find_gcf(u32 a, u32 b); * ======== nldr_allocate ======== */ int nldr_allocate(struct nldr_object *nldr_obj, void *priv_ref, - IN CONST struct dcd_nodeprops *node_props, + IN const struct dcd_nodeprops *node_props, OUT struct nldr_nodeobject **phNldrNode, IN bool *pf_phase_split) { @@ -426,7 +426,7 @@ int nldr_allocate(struct nldr_object *nldr_obj, void *priv_ref, */ int nldr_create(OUT struct nldr_object **phNldr, struct dev_object *hdev_obj, - IN CONST struct nldr_attrs *pattrs) + IN const struct nldr_attrs *pattrs) { struct cod_manager *cod_mgr; /* COD manager */ char *psz_coff_buf = NULL; diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 4cc14fd..e5851bb 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -252,7 +252,7 @@ static int get_fxn_address(struct node_object *hnode, u32 * pulFxnAddr, u32 uPhase); static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, - CONST struct dsp_uuid *pNodeId, + const struct dsp_uuid *pNodeId, struct dcd_genericobj *pdcdProps); static int get_proc_props(struct node_mgr *hnode_mgr, struct dev_object *hdev_obj); @@ -291,9 +291,9 @@ enum node_state node_get_state(void *hnode) * Allocate GPP resources to manage a node on the DSP. */ int node_allocate(struct proc_object *hprocessor, - IN CONST struct dsp_uuid *pNodeId, - OPTIONAL IN CONST struct dsp_cbdata *pargs, - OPTIONAL IN CONST struct dsp_nodeattrin *attr_in, + IN const struct dsp_uuid *pNodeId, + OPTIONAL IN const struct dsp_cbdata *pargs, + OPTIONAL IN const struct dsp_nodeattrin *attr_in, OUT struct node_object **ph_node, struct process_context *pr_ctxt) { @@ -2094,7 +2094,7 @@ func_end: * message, or a timeout occurs. */ int node_put_message(struct node_object *hnode, - IN CONST struct dsp_msg *pmsg, u32 utimeout) + IN const struct dsp_msg *pmsg, u32 utimeout) { struct node_mgr *hnode_mgr = NULL; enum node_type node_type; @@ -2888,7 +2888,7 @@ void get_node_info(struct node_object *hnode, struct dsp_nodeinfo *pNodeInfo) */ static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, - CONST struct dsp_uuid *pNodeId, + const struct dsp_uuid *pNodeId, struct dcd_genericobj *pdcdProps) { u32 len; @@ -3004,7 +3004,7 @@ static int get_proc_props(struct node_mgr *hnode_mgr, * Fetch Node UUID properties from DCD/DOF file. */ int node_get_uuid_props(void *hprocessor, - IN CONST struct dsp_uuid *pNodeId, + IN const struct dsp_uuid *pNodeId, OUT struct dsp_ndbprops *node_props) { struct node_mgr *hnode_mgr = NULL; diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index c912572..8ca7852 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -272,7 +272,7 @@ static inline struct page *get_mapping_page(struct dmm_map_object *map_obj, */ int proc_attach(u32 processor_id, - OPTIONAL CONST struct dsp_processorattrin *attr_in, + OPTIONAL const struct dsp_processorattrin *attr_in, void **ph_processor, struct process_context *pr_ctxt) { int status = 0; @@ -469,7 +469,7 @@ int proc_auto_start(struct cfg_devnode *dev_node_obj, argv[0] = sz_exec_file; argv[1] = NULL; /* ...and try to load it: */ - status = proc_load(p_proc_object, 1, (CONST char **)argv, NULL); + status = proc_load(p_proc_object, 1, (const char **)argv, NULL); if (DSP_SUCCEEDED(status)) status = proc_start(p_proc_object); } @@ -1055,8 +1055,8 @@ bool proc_init(void) * This will be an OEM-only function, and not part of the DSP/BIOS Bridge * application developer's API. */ -int proc_load(void *hprocessor, IN CONST s32 argc_index, - IN CONST char **user_args, IN CONST char **user_envp) +int proc_load(void *hprocessor, IN const s32 argc_index, + IN const char **user_args, IN const char **user_envp) { int status = 0; struct proc_object *p_proc_object = (struct proc_object *)hprocessor; diff --git a/drivers/staging/tidspbridge/rmgr/pwr.c b/drivers/staging/tidspbridge/rmgr/pwr.c index ec6d181..4f5e498 100644 --- a/drivers/staging/tidspbridge/rmgr/pwr.c +++ b/drivers/staging/tidspbridge/rmgr/pwr.c @@ -36,7 +36,7 @@ * ======== pwr_sleep_dsp ======== * Send command to DSP to enter sleep state. */ -int pwr_sleep_dsp(IN CONST u32 sleepCode, IN CONST u32 timeout) +int pwr_sleep_dsp(IN const u32 sleepCode, IN const u32 timeout) { struct bridge_drv_interface *intf_fxns; struct bridge_dev_context *dw_context; @@ -79,7 +79,7 @@ int pwr_sleep_dsp(IN CONST u32 sleepCode, IN CONST u32 timeout) * ======== pwr_wake_dsp ======== * Send command to DSP to wake it from sleep. */ -int pwr_wake_dsp(IN CONST u32 timeout) +int pwr_wake_dsp(IN const u32 timeout) { struct bridge_drv_interface *intf_fxns; struct bridge_dev_context *dw_context; From patchwork Sun Jul 4 13:31:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110128 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64DW4sI003956 for ; Sun, 4 Jul 2010 13:32:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757573Ab0GDNb6 (ORCPT ); Sun, 4 Jul 2010 09:31:58 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:39559 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757524Ab0GDNb5 (ORCPT ); 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Sun, 04 Jul 2010 06:31:53 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Ohad Ben-Cohen , Omar Ramirez Luna , Greg KH , Felipe Contreras Subject: [PATCH] staging: ti dspbridge: remove contributor leftovers Date: Sun, 4 Jul 2010 16:31:47 +0300 Message-Id: <1278250307-16880-1-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 04 Jul 2010 13:32:05 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/Documentation/CONTRIBUTORS b/drivers/staging/tidspbridge/Documentation/CONTRIBUTORS index b40e7a6..86f5787 100644 --- a/drivers/staging/tidspbridge/Documentation/CONTRIBUTORS +++ b/drivers/staging/tidspbridge/Documentation/CONTRIBUTORS @@ -43,40 +43,3 @@ Please keep the following list in alphabetical order. Armando Uribe de Leon Nischal Varide Wenbiao Wang - - - -The following list was taken from file Revision History, if you recognize your -alias or did any contribution to the project please let us now, so we can -proper credit your work. - - ag - ap - cc - db - dh4 - dr - hp - jg - kc - kln - kw - ge - gv - map - mf - mk - mr - nn - rajesh - rg - rr - rt - sb - sg - sh - sp - srid - swa - vp - ww From patchwork Sun Jul 4 13:34:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Contreras X-Patchwork-Id: 110129 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o64DYlmk004340 for ; Sun, 4 Jul 2010 13:34:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757672Ab0GDNeq (ORCPT ); Sun, 4 Jul 2010 09:34:46 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:40955 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757665Ab0GDNep (ORCPT ); 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Sun, 04 Jul 2010 06:34:44 -0700 (PDT) From: Felipe Contreras To: linux-omap Cc: Ohad Ben-Cohen , Omar Ramirez Luna , Greg KH , Felipe Contreras Subject: [PATCH 01/13] staging: ti dspbridge: deh: trivial cleanups Date: Sun, 4 Jul 2010 16:34:27 +0300 Message-Id: <1278250479-16982-2-git-send-email-felipe.contreras@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> References: <1278250479-16982-1-git-send-email-felipe.contreras@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 04 Jul 2010 13:34:48 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/ue_deh.c b/drivers/staging/tidspbridge/core/ue_deh.c index 64e9366..ee2d23a 100644 --- a/drivers/staging/tidspbridge/core/ue_deh.c +++ b/drivers/staging/tidspbridge/core/ue_deh.c @@ -52,11 +52,6 @@ #include -static struct hw_mmu_map_attrs_t map_attrs = { HW_LITTLE_ENDIAN, - HW_ELEM_SIZE16BIT, - HW_MMU_CPUES -}; - static void *dummy_va_addr; int bridge_deh_create(struct deh_mgr **ret_deh_mgr, @@ -71,23 +66,20 @@ int bridge_deh_create(struct deh_mgr **ret_deh_mgr, * the base image. */ /* Get Bridge context info. */ dev_get_bridge_context(hdev_obj, &hbridge_context); - DBC_ASSERT(hbridge_context); - dummy_va_addr = NULL; /* Allocate IO manager object: */ deh_mgr = kzalloc(sizeof(struct deh_mgr), GFP_KERNEL); if (!deh_mgr) { status = -ENOMEM; - goto leave; + goto err; } /* Create an NTFY object to manage notifications */ deh_mgr->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL); - if (deh_mgr->ntfy_obj) { - ntfy_init(deh_mgr->ntfy_obj); - } else { + if (!deh_mgr->ntfy_obj) { status = -ENOMEM; goto err; } + ntfy_init(deh_mgr->ntfy_obj); /* Create a MMUfault DPC */ tasklet_init(&deh_mgr->dpc_tasklet, mmu_fault_dpc, (u32) deh_mgr); @@ -100,22 +92,17 @@ int bridge_deh_create(struct deh_mgr **ret_deh_mgr, deh_mgr->err_info.dw_val3 = 0L; /* Install ISR function for DSP MMU fault */ - if ((request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0, - "DspBridge\tiommu fault", - (void *)deh_mgr)) == 0) - status = 0; - else - status = -EPERM; + status = request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0, + "DspBridge\tiommu fault", deh_mgr); + if (status < 0) + goto err; -err: - if (DSP_FAILED(status)) { - /* If create failed, cleanup */ - bridge_deh_destroy(deh_mgr); - deh_mgr = NULL; - } -leave: *ret_deh_mgr = deh_mgr; + return 0; +err: + bridge_deh_destroy(deh_mgr); + *ret_deh_mgr = NULL; return status; } @@ -147,33 +134,32 @@ int bridge_deh_register_notify(struct deh_mgr *deh_mgr, u32 event_mask, u32 notify_type, struct dsp_notification *hnotification) { - int status = 0; - if (!deh_mgr) return -EFAULT; if (event_mask) - status = ntfy_register(deh_mgr->ntfy_obj, hnotification, - event_mask, notify_type); + return ntfy_register(deh_mgr->ntfy_obj, hnotification, + event_mask, notify_type); else - status = ntfy_unregister(deh_mgr->ntfy_obj, hnotification); - - return status; + return ntfy_unregister(deh_mgr->ntfy_obj, hnotification); } void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) { struct bridge_dev_context *dev_context; - int status = 0; u32 hw_mmu_max_tlb_count = 31; struct cfg_hostres *resources; - hw_status hw_status_obj; + struct hw_mmu_map_attrs_t map_attrs = { + .endianism = HW_LITTLE_ENDIAN, + .element_size = HW_ELEM_SIZE16BIT, + .mixed_size = HW_MMU_CPUES, + }; if (!deh_mgr) return; dev_info(bridge, "%s: device exception\n", __func__); - dev_context = (struct bridge_dev_context *)deh_mgr->hbridge_context; + dev_context = deh_mgr->hbridge_context; resources = dev_context->resources; switch (ulEventMask) { @@ -200,8 +186,6 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) (unsigned int) deh_mgr->err_info.dw_val2, (unsigned int) fault_addr); dummy_va_addr = (void*)__get_free_page(GFP_ATOMIC); - dev_context = (struct bridge_dev_context *) - deh_mgr->hbridge_context; print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); @@ -216,13 +200,10 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) dev_context->num_tlb_entries = dev_context->fixed_tlb_entries; } - if (DSP_SUCCEEDED(status)) { - hw_status_obj = - hw_mmu_tlb_add(resources->dw_dmmu_base, - virt_to_phys(dummy_va_addr), fault_addr, - HW_PAGE_SIZE4KB, 1, - &map_attrs, HW_SET, HW_SET); - } + hw_mmu_tlb_add(resources->dw_dmmu_base, + virt_to_phys(dummy_va_addr), fault_addr, + HW_PAGE_SIZE4KB, 1, + &map_attrs, HW_SET, HW_SET); dsp_clk_enable(DSP_CLK_GPT8); @@ -231,7 +212,7 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) /* Clear MMU interrupt */ hw_mmu_event_ack(resources->dw_dmmu_base, HW_MMU_TRANSLATION_FAULT); - dump_dsp_stack(deh_mgr->hbridge_context); + dump_dsp_stack(dev_context); dsp_clk_disable(DSP_CLK_GPT8); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR @@ -281,9 +262,6 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo) int bridge_deh_get_info(struct deh_mgr *deh_mgr, struct dsp_errorinfo *pErrInfo) { - DBC_REQUIRE(deh_mgr); - DBC_REQUIRE(pErrInfo); - if (!deh_mgr) return -EFAULT; From patchwork Thu Jul 8 10:28:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalliguddi, Hema" X-Patchwork-Id: 110818 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o68ASlIc013159 for ; Thu, 8 Jul 2010 10:28:47 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753513Ab0GHK2p (ORCPT ); Thu, 8 Jul 2010 06:28:45 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:50843 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752832Ab0GHK2o (ORCPT ); Thu, 8 Jul 2010 06:28:44 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o68ASbs7014584 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 05:28:39 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o68ASaa5024618; Thu, 8 Jul 2010 15:58:36 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id o68ASaZH021906; Thu, 8 Jul 2010 15:58:36 +0530 Received: (from a0876481@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id o68ASaDi021904; Thu, 8 Jul 2010 15:58:36 +0530 From: Hema HK To: linux-usb@vger.kernel.org, linux-omap@vger.kernel.org Cc: Hema HK , Maulik Mankad , Felipe Balbi , Tony Lindgren , Kevin Hilman Subject: [PATCH] usb: musb: Offmode fix for idle path Date: Thu, 8 Jul 2010 15:58:36 +0530 Message-Id: <1278584916-21288-1-git-send-email-hemahk@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Jul 2010 10:28:48 +0000 (UTC) Index: linux-omap-pm/arch/arm/mach-omap2/pm34xx.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/pm34xx.c +++ linux-omap-pm/arch/arm/mach-omap2/pm34xx.c @@ -431,6 +431,8 @@ void omap_sram_idle(void) if (core_next_state == PWRDM_POWER_OFF) { omap3_core_save_context(); omap3_prcm_save_context(); + /* Save MUSB context */ + musb_context_save_restore(1); } } @@ -479,6 +481,8 @@ void omap_sram_idle(void) omap3_prcm_restore_context(); omap3_sram_restore_context(); omap2_sms_restore_context(); + /* Restore MUSB context */ + musb_context_save_restore(0); /* * Errata 1.164 fix : OTG autoidle can prevent * sleep Index: linux-omap-pm/arch/arm/mach-omap2/usb-musb.c =================================================================== --- linux-omap-pm.orig/arch/arm/mach-omap2/usb-musb.c +++ linux-omap-pm/arch/arm/mach-omap2/usb-musb.c @@ -177,6 +177,21 @@ void __init usb_musb_init(struct omap_mu usb_musb_pm_init(); } +void musb_context_save_restore(int save) +{ + struct device *dev = &musb_device.dev; + struct device_driver *drv = dev->driver; + if (dev->driver) { + + const struct dev_pm_ops *pm = drv->pm; + + if (save) + pm->suspend(dev); + else + pm->resume_noirq(dev); + } +} + #else void __init usb_musb_init(struct omap_musb_board_data *board_data) { Index: linux-omap-pm/arch/arm/plat-omap/include/plat/usb.h =================================================================== --- linux-omap-pm.orig/arch/arm/plat-omap/include/plat/usb.h +++ linux-omap-pm/arch/arm/plat-omap/include/plat/usb.h @@ -82,6 +82,8 @@ extern void usb_ohci_init(const struct o /* This is needed for OMAP3 errata 1.164: enabled autoidle can prevent sleep */ extern void usb_musb_disable_autoidle(void); +/* For saving and restoring the musb context during off/wakeup*/ +extern void musb_context_save_restore(int save); #endif void omap_usb_init(struct omap_usb_config *pdata); Index: linux-omap-pm/drivers/usb/musb/musb_core.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/musb_core.c +++ linux-omap-pm/drivers/usb/musb/musb_core.c @@ -2430,11 +2430,6 @@ static int musb_suspend(struct device *d } musb_save_context(musb); - - if (musb->set_clock) - musb->set_clock(musb->clock, 0); - else - clk_disable(musb->clock); spin_unlock_irqrestore(&musb->lock, flags); return 0; } @@ -2446,12 +2441,6 @@ static int musb_resume_noirq(struct devi if (!musb->clock) return 0; - - if (musb->set_clock) - musb->set_clock(musb->clock, 1); - else - clk_enable(musb->clock); - musb_restore_context(musb); /* for static cmos like DaVinci, register values were preserved Index: linux-omap-pm/drivers/usb/musb/omap2430.c =================================================================== --- linux-omap-pm.orig/drivers/usb/musb/omap2430.c +++ linux-omap-pm/drivers/usb/musb/omap2430.c @@ -257,15 +257,39 @@ int __init musb_platform_init(struct mus void musb_platform_save_context(struct musb *musb, struct musb_context_registers *musb_context) { - musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG); - musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY); + /* + * As per the specification, configure it to forced standby + * and force idle mode when no activity on usb. + */ + void __iomem *musb_base = musb->mregs; + musb_writel(musb_base, OTG_FORCESTDBY, 0); + musb_writel(musb_base, OTG_SYSCONFIG, musb_readl(musb_base, + OTG_SYSCONFIG) & ~(NOSTDBY | SMARTSTDBY)); + + musb_writel(musb_base, OTG_SYSCONFIG, musb_readl(musb_base, + OTG_SYSCONFIG) & ~(AUTOIDLE)); + + musb_writel(musb_base, OTG_SYSCONFIG, musb_readl(musb_base, + OTG_SYSCONFIG) & ~(NOIDLE | SMARTIDLE)); + + musb_writel(musb_base, OTG_FORCESTDBY, 1); } void musb_platform_restore_context(struct musb *musb, struct musb_context_registers *musb_context) { - musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig); - musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby); + /* + * As per the specification, configure it smart standby + * and smart idle during operation. + */ + void __iomem *musb_base = musb->mregs; + musb_writel(musb_base, OTG_FORCESTDBY, 0); + + musb_writel(musb_base, OTG_SYSCONFIG, musb_readl(musb_base, + OTG_SYSCONFIG) | (SMARTSTDBY)); + + musb_writel(musb_base, OTG_SYSCONFIG, musb_readl(musb_base, + OTG_SYSCONFIG) | (SMARTIDLE)); } #endif From patchwork Thu May 13 10:10:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 99281 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4DABGK4006211 for ; Thu, 13 May 2010 10:11:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757255Ab0EMKLK (ORCPT ); Thu, 13 May 2010 06:11:10 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40437 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756708Ab0EMKLI convert rfc822-to-8bit (ORCPT ); Thu, 13 May 2010 06:11:08 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4DAB0a8018116 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 13 May 2010 05:11:02 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4DAAwUO002745; Thu, 13 May 2010 15:40:59 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Thu, 13 May 2010 15:40:59 +0530 From: "Gupta, Ajay Kumar" To: "Kalliguddi, Hema" , "Gadiyar, Anand" , "me@felipebalbi.com" CC: "linux-usb@vger.kernel.org" , "linux-omap@vger.kernel.org" Date: Thu, 13 May 2010 15:40:57 +0530 Subject: RE: [PATCH 2/5] musb: use system DMA to fix Inventra DMA issue on RTL-1.4 Thread-Topic: [PATCH 2/5] musb: use system DMA to fix Inventra DMA issue on RTL-1.4 Thread-Index: Acrx+6GRsyqYaxjlSS6DEU3V/M2zyAAAMjuxABWmlLAACY4UoAACuezg Message-ID: <19F8576C6E063C45BE387C64729E7394044E4052E6@dbde02.ent.ti.com> References: <1273664979-493-1-git-send-email-ajay.gupta@ti.com> <1273664979-493-2-git-send-email-ajay.gupta@ti.com>, <20100512175113.GA3285@gandalf> <5A47E75E594F054BAF48C5E4FC4B92AB03216237DA@dbde02.ent.ti.com> <19F8576C6E063C45BE387C64729E7394044E40516E@dbde02.ent.ti.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 13 May 2010 10:11:16 +0000 (UTC) diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c index fd842af..477a009 100644 --- a/drivers/usb/musb/musb_gadget.c +++ b/drivers/usb/musb/musb_gadget.c @@ -297,9 +297,13 @@ static void txstate(struct musb *musb, struct musb_request *req) csr); #ifndef CONFIG_MUSB_PIO_ONLY - if (is_dma_capable() && musb_ep->dma) { + + if (is_dma_capable() && musb->dma_controller) { struct dma_controller *c = musb->dma_controller; + if (!musb_ep->dma) + musb_ep->dma = c->channel_alloc(c, musb_ep->hw_ep, 1); + use_dma = (request->dma != DMA_ADDR_INVALID); /* MUSB_TXCSR_P_ISO is still set correctly */ @@ -433,6 +437,7 @@ void musb_g_tx(struct musb *musb, u8 epnum) u8 __iomem *mbase = musb->mregs; struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; void __iomem *epio = musb->endpoints[epnum].regs; + struct dma_controller *c = musb->dma_controller; struct dma_channel *dma; musb_ep_select(mbase, epnum); @@ -535,6 +540,10 @@ void musb_g_tx(struct musb *musb, u8 epnum) if (!request) { DBG(4, "%s idle now\n", musb_ep->end_point.name); + if (musb_ep->dma) { + c->channel_release(musb_ep->dma); + musb_ep->dma = NULL; + } return; } } @@ -585,6 +594,7 @@ static void rxstate(struct musb *musb, struct musb_request *req) struct usb_request *request = &req->request; struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; void __iomem *epio = musb->endpoints[epnum].regs; + struct dma_controller *c = musb->dma_controller; unsigned fifo_count = 0; u16 len = musb_ep->packet_sz; u16 csr = musb_readw(epio, MUSB_RXCSR); @@ -601,8 +611,10 @@ static void rxstate(struct musb *musb, struct musb_request *req) return; } + if (is_dma_capable() && musb->dma_controller && !musb_ep->dma) + musb_ep->dma = c->channel_alloc(c, musb_ep->hw_ep, 0); + if ((is_cppi_enabled() || is_cppi41_enabled()) && musb_ep->dma) { - struct dma_controller *c = musb->dma_controller; struct dma_channel *channel = musb_ep->dma; /* NOTE: CPPI won't actually stop advancing the DMA @@ -633,11 +645,9 @@ static void rxstate(struct musb *musb, struct musb_request *req) if (request->actual < request->length) { #ifdef CONFIG_USB_INVENTRA_DMA if (is_dma_capable() && musb_ep->dma) { - struct dma_controller *c; struct dma_channel *channel; int use_dma = 0; - c = musb->dma_controller; channel = musb_ep->dma; /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in @@ -719,7 +729,6 @@ static void rxstate(struct musb *musb, struct musb_request *req) #ifdef CONFIG_USB_TUSB_OMAP_DMA if (tusb_dma_omap() && musb_ep->dma) { - struct dma_controller *c = musb->dma_controller; struct dma_channel *channel = musb_ep->dma; u32 dma_addr = request->dma + request->actual; int ret; @@ -764,6 +773,7 @@ void musb_g_rx(struct musb *musb, u8 epnum) void __iomem *mbase = musb->mregs; struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; void __iomem *epio = musb->endpoints[epnum].regs; + struct dma_controller *c = musb->dma_controller; struct dma_channel *dma; musb_ep_select(mbase, epnum); @@ -838,8 +848,13 @@ void musb_g_rx(struct musb *musb, u8 epnum) musb_g_giveback(musb_ep, request, 0); request = next_request(musb_ep); - if (!request) + if (!request) { + if (musb_ep->dma) { + c->channel_release(musb_ep->dma); + musb_ep->dma = NULL; + } return; + } } /* analyze request if the ep is hot */ diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index 89c8c35..001a1d6 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -460,11 +460,21 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb, */ if (list_empty(&qh->hep->urb_list)) { struct list_head *head; + struct dma_controller *dma = musb->dma_controller; - if (is_in) + if (is_in) { ep->rx_reinit = 1; - else + if (ep->rx_channel) { + dma->channel_release(ep->rx_channel); + ep->rx_channel = NULL; + } + } else { ep->tx_reinit = 1; + if (ep->tx_channel) { + dma->channel_release(ep->tx_channel); + ep->tx_channel = NULL; + } + } /* Clobber old pointers to this qh */ musb_ep_set_qh(ep, is_in, NULL); From patchwork Mon Jul 12 22:56:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111561 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMb016827 for ; Mon, 12 Jul 2010 22:59:59 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755999Ab0GLW4i (ORCPT ); Mon, 12 Jul 2010 18:56:38 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39462 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755929Ab0GLW4X (ORCPT ); Mon, 12 Jul 2010 18:56:23 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuEPf003029 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:14 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuEra016501; Mon, 12 Jul 2010 17:56:14 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuDP07282; Mon, 12 Jul 2010 17:56:13 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 5DE94C23D; Mon, 12 Jul 2010 17:56:10 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 09/11] staging: tidspbridge: remove OPTIONAL Date: Mon, 12 Jul 2010 17:56:07 -0500 Message-Id: <1278975369-7687-10-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:00 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 25d2450..2189796 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -91,7 +91,7 @@ static int search_free_channel(struct chnl_mgr *chnl_mgr_obj, */ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *pHostBuf, u32 byte_size, u32 buf_size, - OPTIONAL u32 dw_dsp_addr, u32 dw_arg) + u32 dw_dsp_addr, u32 dw_arg) { int status = 0; struct chnl_object *pchnl = (struct chnl_object *)chnl_obj; diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index cb9b2c3..25817fc 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -93,7 +93,7 @@ extern void cod_close(struct cod_libraryobj *lib); */ extern int cod_create(OUT struct cod_manager **phManager, char *pstrZLFile, - OPTIONAL const struct cod_attrs *attrs); + const struct cod_attrs *attrs); /* * ======== cod_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h index ee71e9b..8b943cc 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h @@ -35,7 +35,7 @@ extern int bridge_chnl_open(OUT struct chnl_object **phChnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, - const OPTIONAL struct chnl_attr + const struct chnl_attr *pattrs); extern int bridge_chnl_close(struct chnl_object *chnl_obj); @@ -43,7 +43,7 @@ extern int bridge_chnl_close(struct chnl_object *chnl_obj); extern int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *pHostBuf, u32 byte_size, u32 buf_size, - OPTIONAL u32 dw_dsp_addr, u32 dw_arg); + u32 dw_dsp_addr, u32 dw_arg); extern int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 dwTimeOut, OUT struct chnl_ioc *pIOC); diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 7c86e7b..467ec8b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -411,7 +411,7 @@ typedef int(*fxn_chnl_open) (OUT struct chnl_object struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, - const OPTIONAL struct + const struct chnl_attr * pattrs); /* @@ -474,7 +474,7 @@ typedef int(*fxn_chnl_addioreq) (struct chnl_object void *pHostBuf, u32 byte_size, u32 buf_size, - OPTIONAL u32 dw_dsp_addr, u32 dw_arg); + u32 dw_dsp_addr, u32 dw_arg); /* * ======== bridge_chnl_get_ioc ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index 7f16f6f..7be6dda 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -57,8 +57,8 @@ */ extern int node_allocate(struct proc_object *hprocessor, const struct dsp_uuid *pNodeId, - OPTIONAL const struct dsp_cbdata - *pargs, OPTIONAL const struct dsp_nodeattrin + const struct dsp_cbdata + *pargs, const struct dsp_nodeattrin *attr_in, OUT struct node_object **ph_node, struct process_context *pr_ctxt); @@ -86,7 +86,7 @@ extern int node_allocate(struct proc_object *hprocessor, * Ensures: */ extern int node_alloc_msg_buf(struct node_object *hnode, - u32 usize, OPTIONAL struct dsp_bufferattr + u32 usize, struct dsp_bufferattr *pattr, OUT u8 **pbuffer); /* @@ -182,8 +182,8 @@ extern int node_connect(struct node_object *hNode1, u32 uStream1, struct node_object *hNode2, u32 uStream2, - OPTIONAL struct dsp_strmattr *pattrs, - OPTIONAL struct dsp_cbdata + struct dsp_strmattr *pattrs, + struct dsp_cbdata *conn_param); /* @@ -335,7 +335,7 @@ extern void node_exit(void); */ extern int node_free_msg_buf(struct node_object *hnode, u8 *pbuffer, - OPTIONAL struct dsp_bufferattr + struct dsp_bufferattr *pattr); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/proc.h b/drivers/staging/tidspbridge/include/dspbridge/proc.h index a06ddc4..12f2f2a 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/proc.h +++ b/drivers/staging/tidspbridge/include/dspbridge/proc.h @@ -52,7 +52,7 @@ extern char *iva_img; * When attr_in is NULL, the default timeout value is 10 seconds. */ extern int proc_attach(u32 processor_id, - OPTIONAL const struct dsp_processorattrin + const struct dsp_processorattrin *attr_in, void **ph_processor, struct process_context *pr_ctxt); diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index 859c2ff..2aed7a4 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -217,7 +217,7 @@ void cod_close(struct cod_libraryobj *lib) * */ int cod_create(OUT struct cod_manager **phMgr, char *pstrDummyFile, - OPTIONAL const struct cod_attrs *attrs) + const struct cod_attrs *attrs) { struct cod_manager *mgr_new; struct dbll_attrs zl_attrs; diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 61c47b0..81b91b8 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -70,9 +70,9 @@ static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size); static int get_dep_lib_info(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, OUT u16 *pNumLibs, - OPTIONAL OUT u16 *pNumPersLibs, - OPTIONAL OUT struct dsp_uuid *pDepLibUuids, - OPTIONAL OUT bool *pPersistentDepLibs, + OUT u16 *pNumPersLibs, + OUT struct dsp_uuid *pDepLibUuids, + OUT bool *pPersistentDepLibs, enum nldr_phase phase); /* @@ -1392,9 +1392,9 @@ static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size) static int get_dep_lib_info(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, OUT u16 *pNumLibs, - OPTIONAL OUT u16 *pNumPersLibs, - OPTIONAL OUT struct dsp_uuid *pDepLibUuids, - OPTIONAL OUT bool *pPersistentDepLibs, + OUT u16 *pNumPersLibs, + OUT struct dsp_uuid *pDepLibUuids, + OUT bool *pPersistentDepLibs, enum nldr_phase phase) { struct dcd_manager *dcd_mgr_obj = hdcd_mgr; diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index bad1b8f..aaaab67 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -306,8 +306,8 @@ static int load_lib(struct nldr_nodeobject *nldr_node_obj, static int load_ovly(struct nldr_nodeobject *nldr_node_obj, enum nldr_phase phase); static int remote_alloc(void **pRef, u16 mem_sect_type, u32 size, - u32 align, u32 *dspAddr, OPTIONAL s32 segmentId, - OPTIONAL s32 req, bool reserve); + u32 align, u32 *dspAddr, s32 segmentId, + s32 req, bool reserve); static int remote_free(void **pRef, u16 space, u32 dspAddr, u32 size, bool reserve); @@ -1625,7 +1625,7 @@ func_end: */ static int remote_alloc(void **pRef, u16 space, u32 size, u32 align, u32 *dspAddr, - OPTIONAL s32 segmentId, OPTIONAL s32 req, + s32 segmentId, s32 req, bool reserve) { struct nldr_nodeobject *hnode = (struct nldr_nodeobject *)pRef; diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index c19e1bf..1f975c6 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -292,8 +292,8 @@ enum node_state node_get_state(void *hnode) */ int node_allocate(struct proc_object *hprocessor, const struct dsp_uuid *pNodeId, - OPTIONAL const struct dsp_cbdata *pargs, - OPTIONAL const struct dsp_nodeattrin *attr_in, + const struct dsp_cbdata *pargs, + const struct dsp_nodeattrin *attr_in, OUT struct node_object **ph_node, struct process_context *pr_ctxt) { @@ -685,7 +685,7 @@ func_end: * Allocates buffer for zero copy messaging. */ DBAPI node_alloc_msg_buf(struct node_object *hnode, u32 usize, - OPTIONAL OUT struct dsp_bufferattr *pattr, + OUT struct dsp_bufferattr *pattr, OUT u8 **pbuffer) { struct node_object *pnode = (struct node_object *)hnode; @@ -833,8 +833,8 @@ func_end: */ int node_connect(struct node_object *hNode1, u32 uStream1, struct node_object *hNode2, - u32 uStream2, OPTIONAL struct dsp_strmattr *pattrs, - OPTIONAL struct dsp_cbdata *conn_param) + u32 uStream2, struct dsp_strmattr *pattrs, + struct dsp_cbdata *conn_param) { struct node_mgr *hnode_mgr; char *pstr_dev_name = NULL; @@ -1674,7 +1674,7 @@ void node_exit(void) * Frees the message buffer. */ int node_free_msg_buf(struct node_object *hnode, u8 * pbuffer, - OPTIONAL struct dsp_bufferattr *pattr) + struct dsp_bufferattr *pattr) { struct node_object *pnode = (struct node_object *)hnode; int status = 0; diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index e95d44c..1f450fe 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -272,7 +272,7 @@ static inline struct page *get_mapping_page(struct dmm_map_object *map_obj, */ int proc_attach(u32 processor_id, - OPTIONAL const struct dsp_processorattrin *attr_in, + const struct dsp_processorattrin *attr_in, void **ph_processor, struct process_context *pr_ctxt) { int status = 0; From patchwork Mon Jul 12 22:56:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111563 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMd016827 for ; Mon, 12 Jul 2010 23:00:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756053Ab0GLW4l (ORCPT ); Mon, 12 Jul 2010 18:56:41 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:56971 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755949Ab0GLW4X (ORCPT ); Mon, 12 Jul 2010 18:56:23 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuCLl012332 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:12 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuC4E016478; Mon, 12 Jul 2010 17:56:12 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuBP07247; Mon, 12 Jul 2010 17:56:11 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 00D38C25E; Mon, 12 Jul 2010 17:56:10 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 05/11] staging: tidspbridge: remove RET_OK RET_FAIL Date: Mon, 12 Jul 2010 17:56:03 -0500 Message-Id: <1278975369-7687-6-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:00 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 51e327f..33fcef5 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -1506,8 +1506,7 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, } paddr += HW_PAGE_SIZE4KB; } - if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size) - == RET_FAIL) { + if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) { status = -EPERM; goto EXIT_LOOP; } @@ -1524,9 +1523,8 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, /* * Clear the L1 PTE pointing to the L2 PT */ - if (hw_mmu_pte_clear(l1_base_va, va_curr_orig, - HW_MMU_COARSE_PAGE_SIZE) == - RET_OK) + if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig, + HW_MMU_COARSE_PAGE_SIZE)) status = 0; else { status = -EPERM; @@ -1571,7 +1569,7 @@ skip_coarse_page: } paddr += HW_PAGE_SIZE4KB; } - if (hw_mmu_pte_clear(l1_base_va, va_curr, pte_size) == RET_OK) { + if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) { status = 0; rem_bytes -= pte_size; va_curr += pte_size; diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index 4430daf..321b72d 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -22,6 +22,7 @@ #include #include #include +#include #define MMU_BASE_VAL_MASK 0xFC00 #define MMU_PAGE_MAX 3 @@ -59,7 +60,7 @@ enum hw_mmu_page_size_t { * RETURNS: * * Type : hw_status - * Description : RET_OK -- No errors occured + * Description : 0 -- No errors occured * RET_BAD_NULL_PARAM -- A Pointer * Paramater was set to NULL * @@ -102,7 +103,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address); * RETURNS: * * Type : hw_status - * Description : RET_OK -- No errors occured + * Description : 0 -- No errors occured * RET_BAD_NULL_PARAM -- A Pointer Paramater * was set to NULL * RET_PARAM_OUT_OF_RANGE -- Input Parameter out @@ -147,7 +148,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, * RETURNS: * * Type : hw_status - * Description : RET_OK -- No errors occured + * Description : 0 -- No errors occured * RET_BAD_NULL_PARAM -- A Pointer Paramater * was set to NULL * RET_PARAM_OUT_OF_RANGE -- Input Parameter @@ -167,7 +168,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address, hw_status hw_mmu_enable(const void __iomem *base_address) { - hw_status status = RET_OK; + hw_status status = 0; MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_SET); @@ -176,7 +177,7 @@ hw_status hw_mmu_enable(const void __iomem *base_address) hw_status hw_mmu_disable(const void __iomem *base_address) { - hw_status status = RET_OK; + hw_status status = 0; MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_CLEAR); @@ -186,7 +187,7 @@ hw_status hw_mmu_disable(const void __iomem *base_address) hw_status hw_mmu_num_locked_set(const void __iomem *base_address, u32 numLockedEntries) { - hw_status status = RET_OK; + hw_status status = 0; MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, numLockedEntries); @@ -196,7 +197,7 @@ hw_status hw_mmu_num_locked_set(const void __iomem *base_address, hw_status hw_mmu_victim_num_set(const void __iomem *base_address, u32 victimEntryNum) { - hw_status status = RET_OK; + hw_status status = 0; MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, victimEntryNum); @@ -205,7 +206,7 @@ hw_status hw_mmu_victim_num_set(const void __iomem *base_address, hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irqMask) { - hw_status status = RET_OK; + hw_status status = 0; MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irqMask); @@ -214,7 +215,7 @@ hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irqMask) hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irqMask) { - hw_status status = RET_OK; + hw_status status = 0; u32 irq_reg; irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address); @@ -226,7 +227,7 @@ hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irqMask) hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irqMask) { - hw_status status = RET_OK; + hw_status status = 0; u32 irq_reg; irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address); @@ -238,7 +239,7 @@ hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irqMask) hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irqMask) { - hw_status status = RET_OK; + hw_status status = 0; *irqMask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address); @@ -247,7 +248,7 @@ hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irqMask) hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr) { - hw_status status = RET_OK; + hw_status status = 0; /*Check the input Parameters */ CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM, @@ -261,7 +262,7 @@ hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr) hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 TTBPhysAddr) { - hw_status status = RET_OK; + hw_status status = 0; u32 load_ttb; /*Check the input Parameters */ @@ -277,7 +278,7 @@ hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 TTBPhysAddr) hw_status hw_mmu_twl_enable(const void __iomem *base_address) { - hw_status status = RET_OK; + hw_status status = 0; MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_SET); @@ -286,7 +287,7 @@ hw_status hw_mmu_twl_enable(const void __iomem *base_address) hw_status hw_mmu_twl_disable(const void __iomem *base_address) { - hw_status status = RET_OK; + hw_status status = 0; MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_CLEAR); @@ -296,7 +297,7 @@ hw_status hw_mmu_twl_disable(const void __iomem *base_address) hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, u32 pageSize) { - hw_status status = RET_OK; + hw_status status = 0; u32 virtual_addr_tag; enum hw_mmu_page_size_t pg_size_bits; @@ -318,7 +319,7 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtualAddr, break; default: - return RET_FAIL; + return -EINVAL; } /* Generate the 20-bit tag from virtual address */ @@ -339,7 +340,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, struct hw_mmu_map_attrs_t *map_attrs, s8 preservedBit, s8 validBit) { - hw_status status = RET_OK; + hw_status status = 0; u32 lock_reg; u32 virtual_addr_tag; enum hw_mmu_page_size_t mmu_pg_size; @@ -371,7 +372,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address, break; default: - return RET_FAIL; + return -EINVAL; } lock_reg = MMUMMU_LOCK_READ_REGISTER32(base_address); @@ -406,7 +407,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, u32 virtualAddr, u32 pageSize, struct hw_mmu_map_attrs_t *map_attrs) { - hw_status status = RET_OK; + hw_status status = 0; u32 pte_addr, pte_val; s32 num_entries = 1; @@ -466,7 +467,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, break; default: - return RET_FAIL; + return -EINVAL; } while (--num_entries >= 0) @@ -477,7 +478,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va, hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtualAddr, u32 page_size) { - hw_status status = RET_OK; + hw_status status = 0; u32 pte_addr; s32 num_entries = 1; @@ -510,7 +511,7 @@ hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtualAddr, u32 page_size) break; default: - return RET_FAIL; + return -EINVAL; } while (--num_entries >= 0) @@ -522,7 +523,7 @@ hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtualAddr, u32 page_size) /* mmu_flush_entry */ static hw_status mmu_flush_entry(const void __iomem *base_address) { - hw_status status = RET_OK; + hw_status status = 0; u32 flush_entry_data = 0x1; /*Check the input Parameters */ @@ -542,7 +543,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address, const u32 validBit, const u32 virtual_addr_tag) { - hw_status status = RET_OK; + hw_status status = 0; u32 mmu_cam_reg; /*Check the input Parameters */ @@ -566,7 +567,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address, enum hw_element_size_t element_size, enum hw_mmu_mixed_size_t mixed_size) { - hw_status status = RET_OK; + hw_status status = 0; u32 mmu_ram_reg; /*Check the input Parameters */ From patchwork Mon Jul 12 22:56:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111562 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMc016827 for ; Mon, 12 Jul 2010 23:00:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756040Ab0GLW4k (ORCPT ); Mon, 12 Jul 2010 18:56:40 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39461 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755911Ab0GLW4X (ORCPT ); Mon, 12 Jul 2010 18:56:23 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuEwb003025 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:14 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuEjt028793; Mon, 12 Jul 2010 17:56:14 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuDP07290; Mon, 12 Jul 2010 17:56:13 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 6373EC261; Mon, 12 Jul 2010 17:56:11 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 11/11] staging: tidspbridge: remove dbdefs.h Date: Mon, 12 Jul 2010 17:56:09 -0500 Message-Id: <1278975369-7687-12-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:00 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h index b408cad..ff0ba57 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h @@ -21,7 +21,6 @@ #include -#include /* GPP side type definitions */ #include /* Types shared between GPP and DSP */ #define PG_SIZE4K 4096 diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbtype.h b/drivers/staging/tidspbridge/include/dspbridge/dbtype.h deleted file mode 100644 index ca5eaf8..0000000 --- a/drivers/staging/tidspbridge/include/dspbridge/dbtype.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * dbtype.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * This header defines data types for DSP/BIOS Bridge APIs and device - * driver modules. It also defines the Hungarian prefix to use for each - * base type. - * - * Copyright (C) 2008 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef DBTYPE_ -#define DBTYPE_ - -/*===========================================================================*/ -/* Argument specification syntax */ -/*===========================================================================*/ - -#ifndef IN -#define IN /* Following parameter is for input. */ -#endif - -#ifndef OUT -#define OUT /* Following parameter is for output. */ -#endif - -#ifndef OPTIONAL -#define OPTIONAL /* Function may optionally use previous parameter. */ -#endif - -#ifndef CONST -#define CONST const -#endif - -/*===========================================================================*/ -/* NULL character (normally used for string termination) */ -/*===========================================================================*/ - -#ifndef NULL_CHAR -#define NULL_CHAR '\0' /* Null character. */ -#endif - -/*===========================================================================*/ -/* Basic Type definitions (with Prefixes for Hungarian notation) */ -/*===========================================================================*/ - -#ifndef OMAPBRIDGE_TYPES -#define OMAPBRIDGE_TYPES -typedef volatile unsigned short reg_uword16; -#endif - -#define TEXT(x) x - -#define DLLIMPORT -#define DLLEXPORT - -/* Define DSPAPIDLL correctly in dspapi.h */ -#define _DSPSYSDLL32_ - -#endif /* DBTYPE_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/host_os.h b/drivers/staging/tidspbridge/include/dspbridge/host_os.h index a91c136..6b4feb4 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/host_os.h +++ b/drivers/staging/tidspbridge/include/dspbridge/host_os.h @@ -42,7 +42,6 @@ #include #include #include -#include #include #include #include From patchwork Mon Jul 12 22:56:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111565 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMf016827 for ; Mon, 12 Jul 2010 23:00:01 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756096Ab0GLW4n (ORCPT ); Mon, 12 Jul 2010 18:56:43 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:56972 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755948Ab0GLW4X (ORCPT ); Mon, 12 Jul 2010 18:56:23 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuD78012338 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:13 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuDN8001520; Mon, 12 Jul 2010 17:56:13 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuCP07261; Mon, 12 Jul 2010 17:56:12 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 11B6CC260; Mon, 12 Jul 2010 17:56:10 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 04/11] staging: tidspbridge: remove custom typedef reg_uword32 Date: Mon, 12 Jul 2010 17:56:02 -0500 Message-Id: <1278975369-7687-5-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:01 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index d067de9..51e327f 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -555,24 +555,18 @@ static int bridge_brd_start(struct bridge_dev_context *hDevContext, dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg; /*PM_IVA2GRPSEL_PER = 0xC0;*/ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA8)); + temp = readl(resources->dw_per_pm_base + 0xA8); temp = (temp & 0xFFFFFF30) | 0xC0; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) = - (u32) temp; + writel(temp, resources->dw_per_pm_base + 0xA8); /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA4)); + temp = readl(resources->dw_per_pm_base + 0xA4); temp = (temp & 0xFFFFFF3F); - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) = - (u32) temp; + writel(temp, resources->dw_per_pm_base + 0xA4); /*CM_SLEEPDEP_PER |= 0x04; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_base) + 0x44)); + temp = readl(resources->dw_per_base + 0x44); temp = (temp & 0xFFFFFFFB) | 0x04; - *((reg_uword32 *) ((u32) (resources->dw_per_base) + 0x44)) = - (u32) temp; + writel(temp, resources->dw_per_base + 0x44); /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */ (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c index 2b3ce64..384b833 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c +++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c @@ -430,12 +430,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) switch (clock_id) { case BPWR_GP_TIMER5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK; @@ -443,18 +439,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER6: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK; @@ -462,18 +452,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER7: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK; @@ -481,18 +465,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER8: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK; @@ -500,18 +478,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP1: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK; @@ -519,18 +491,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4); break; case BPWR_MCBSP2: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK; @@ -538,18 +504,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP3: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK; @@ -557,18 +517,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP4: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK; @@ -576,18 +530,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK; @@ -595,10 +543,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; } } diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c index c5d39d8..ae165b1 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.c +++ b/drivers/staging/tidspbridge/core/tiomap_io.c @@ -439,7 +439,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) omap_mbox_restore_ctx(dev_context->mbox); /* Access MMU SYS CONFIG register to generate a short wakeup */ - temp = *(reg_uword32 *) (resources->dw_dmmu_base + 0x10); + temp = readl(resources->dw_dmmu_base + 0x10); dev_context->dw_brd_state = BRD_RUNNING; } else if (dev_context->dw_brd_state == BRD_RETENTION) { diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 928079e..4cc14fd 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -623,9 +623,7 @@ func_cont: ul_gpp_mem_base = (u32) host_res->dw_mem_base[1]; off_set = pul_value - dynext_base; ul_stack_seg_addr = ul_gpp_mem_base + off_set; - ul_stack_seg_val = (u32) *((reg_uword32 *) - ((u32) - (ul_stack_seg_addr))); + ul_stack_seg_val = readl(ul_stack_seg_addr); dev_dbg(bridge, "%s: StackSegVal = 0x%x, StackSegAddr =" " 0x%x\n", __func__, ul_stack_seg_val, From patchwork Mon Jul 12 22:56:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111564 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMe016827 for ; Mon, 12 Jul 2010 23:00:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756069Ab0GLW4m (ORCPT ); Mon, 12 Jul 2010 18:56:42 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39463 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755933Ab0GLW4X (ORCPT ); Mon, 12 Jul 2010 18:56:23 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuDd9003019 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:13 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6CMuCR7022639; Mon, 12 Jul 2010 17:56:12 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuCP07255; Mon, 12 Jul 2010 17:56:12 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 03AC9C25D; Mon, 12 Jul 2010 17:56:10 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 03/11] staging: tidspbridge: remove std.h Date: Mon, 12 Jul 2010 17:56:01 -0500 Message-Id: <1278975369-7687-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:01 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 714b6f7..b669bc0 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -42,11 +42,12 @@ * !LST_Empty(pchnl->pio_completions) ==> pchnl->sync_event is set. */ +#include + /* ----------------------------------- OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/core/dsp-clock.c b/drivers/staging/tidspbridge/core/dsp-clock.c index abaa595..6f9ea05 100644 --- a/drivers/staging/tidspbridge/core/dsp-clock.c +++ b/drivers/staging/tidspbridge/core/dsp-clock.c @@ -16,13 +16,14 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include + /* ----------------------------------- Host OS */ #include #include #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include #include #include diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 1503968..280b22d 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -23,13 +23,13 @@ * which may cause timeouts and/or failure of the sync_wait_on_event * function. */ +#include /* Host OS */ #include #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* Trace & Debug */ diff --git a/drivers/staging/tidspbridge/core/msg_sm.c b/drivers/staging/tidspbridge/core/msg_sm.c index 7c6d6cc..7b7a4be 100644 --- a/drivers/staging/tidspbridge/core/msg_sm.c +++ b/drivers/staging/tidspbridge/core/msg_sm.c @@ -15,9 +15,9 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 25c1271..d067de9 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -16,6 +16,7 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include #include @@ -23,7 +24,6 @@ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/core/wdt.c b/drivers/staging/tidspbridge/core/wdt.c index dd1afe7..2126f59 100644 --- a/drivers/staging/tidspbridge/core/wdt.c +++ b/drivers/staging/tidspbridge/core/wdt.c @@ -15,8 +15,8 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include -#include #include #include #include diff --git a/drivers/staging/tidspbridge/gen/gb.c b/drivers/staging/tidspbridge/gen/gb.c index d007233..06eb3d3 100644 --- a/drivers/staging/tidspbridge/gen/gb.c +++ b/drivers/staging/tidspbridge/gen/gb.c @@ -15,9 +15,9 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- This */ #include diff --git a/drivers/staging/tidspbridge/gen/gh.c b/drivers/staging/tidspbridge/gen/gh.c index 44fad88..f72d943 100644 --- a/drivers/staging/tidspbridge/gen/gh.c +++ b/drivers/staging/tidspbridge/gen/gh.c @@ -14,7 +14,7 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ -#include +#include #include diff --git a/drivers/staging/tidspbridge/gen/gs.c b/drivers/staging/tidspbridge/gen/gs.c index 3d091b9..9fc6144 100644 --- a/drivers/staging/tidspbridge/gen/gs.c +++ b/drivers/staging/tidspbridge/gen/gs.c @@ -16,8 +16,8 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include #include diff --git a/drivers/staging/tidspbridge/gen/uuidutil.c b/drivers/staging/tidspbridge/gen/uuidutil.c index 070761b..e2c005d 100644 --- a/drivers/staging/tidspbridge/gen/uuidutil.c +++ b/drivers/staging/tidspbridge/gen/uuidutil.c @@ -15,12 +15,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h index 9462a96..b408cad 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h @@ -22,7 +22,6 @@ #include #include /* GPP side type definitions */ -#include /* DSP/BIOS type definitions */ #include /* Types shared between GPP and DSP */ #define PG_SIZE4K 4096 diff --git a/drivers/staging/tidspbridge/include/dspbridge/rmstypes.h b/drivers/staging/tidspbridge/include/dspbridge/rmstypes.h index 3c31f5e..83c0f1d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/rmstypes.h +++ b/drivers/staging/tidspbridge/include/dspbridge/rmstypes.h @@ -19,10 +19,6 @@ #ifndef RMSTYPES_ #define RMSTYPES_ #include -/* - * DSP-side definitions. - */ -#include typedef u32 rms_word; #endif /* RMSTYPES_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/std.h b/drivers/staging/tidspbridge/include/dspbridge/std.h deleted file mode 100644 index ca2827d..0000000 --- a/drivers/staging/tidspbridge/include/dspbridge/std.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * std.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Copyright (C) 2008 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef STD_ -#define STD_ - -#include - -/* - * ======== _TI_ ======== - * _TI_ is defined for all TI targets - */ -#if defined(_29_) || defined(_30_) || defined(_40_) || defined(_50_) || \ - defined(_54_) || defined(_55_) || defined(_6x_) || defined(_80_) || \ - defined(_28_) || defined(_24_) -#define _TI_ 1 -#endif - -/* - * ======== _FLOAT_ ======== - * _FLOAT_ is defined for all targets that natively support floating point - */ -#if defined(_SUN_) || defined(_30_) || defined(_40_) || defined(_67_) || \ - defined(_80_) -#define _FLOAT_ 1 -#endif - -/* - * ======== _FIXED_ ======== - * _FIXED_ is defined for all fixed point target architectures - */ -#if defined(_29_) || defined(_50_) || defined(_54_) || defined(_55_) || \ - defined(_62_) || defined(_64_) || defined(_28_) -#define _FIXED_ 1 -#endif - -/* - * ======== _TARGET_ ======== - * _TARGET_ is defined for all target architectures (as opposed to - * host-side software) - */ -#if defined(_FIXED_) || defined(_FLOAT_) -#define _TARGET_ 1 -#endif - -/* - * 8, 16, 32-bit type definitions - * - * Sm* - 8-bit type - * Md* - 16-bit type - * Lg* - 32-bit type - * - * *s32 - signed type - * *u32 - unsigned type - * *Bits - unsigned type (bit-maps) - */ - -/* - * Aliases for standard C types - */ - -typedef s32(*fxn) (void); /* generic function type */ - -/* - * These macros are used to cast 'Arg' types to 's32' or 'Ptr'. - * These macros were added for the 55x since Arg is not the same - * size as s32 and Ptr in 55x large model. - */ -#if defined(_28l_) || defined(_55l_) -#define ARG_TO_INT(A) ((s32)((long)(A) & 0xffff)) -#define ARG_TO_PTR(A) ((Ptr)(A)) -#else -#define ARG_TO_INT(A) ((s32)(A)) -#define ARG_TO_PTR(A) ((Ptr)(A)) -#endif - -#endif /* STD_ */ diff --git a/drivers/staging/tidspbridge/pmgr/chnl.c b/drivers/staging/tidspbridge/pmgr/chnl.c index bc969d8..9007bfd 100644 --- a/drivers/staging/tidspbridge/pmgr/chnl.c +++ b/drivers/staging/tidspbridge/pmgr/chnl.c @@ -17,11 +17,11 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index 711d206..8300f97 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -29,9 +29,9 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index a9b0491..d2c8e69 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -20,13 +20,14 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include + /* ----------------------------------- Host OS */ #include #include #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/dbll.c b/drivers/staging/tidspbridge/pmgr/dbll.c index 3a50071..fccf369 100644 --- a/drivers/staging/tidspbridge/pmgr/dbll.c +++ b/drivers/staging/tidspbridge/pmgr/dbll.c @@ -13,12 +13,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index 2c31f31..4509468 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -15,12 +15,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/dmm.c b/drivers/staging/tidspbridge/pmgr/dmm.c index e211ec5..11bd2b5 100644 --- a/drivers/staging/tidspbridge/pmgr/dmm.c +++ b/drivers/staging/tidspbridge/pmgr/dmm.c @@ -20,12 +20,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/dspapi.c b/drivers/staging/tidspbridge/pmgr/dspapi.c index 7597210..8555aad 100644 --- a/drivers/staging/tidspbridge/pmgr/dspapi.c +++ b/drivers/staging/tidspbridge/pmgr/dspapi.c @@ -16,12 +16,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/io.c b/drivers/staging/tidspbridge/pmgr/io.c index c6ad203..9f687e0 100644 --- a/drivers/staging/tidspbridge/pmgr/io.c +++ b/drivers/staging/tidspbridge/pmgr/io.c @@ -15,12 +15,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/pmgr/msg.c b/drivers/staging/tidspbridge/pmgr/msg.c index 64f1cb4..7dec2ab 100644 --- a/drivers/staging/tidspbridge/pmgr/msg.c +++ b/drivers/staging/tidspbridge/pmgr/msg.c @@ -15,12 +15,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 4fe96bf..169bb15 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -22,12 +22,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ #include diff --git a/drivers/staging/tidspbridge/rmgr/disp.c b/drivers/staging/tidspbridge/rmgr/disp.c index 7195415..eedf32a 100644 --- a/drivers/staging/tidspbridge/rmgr/disp.c +++ b/drivers/staging/tidspbridge/rmgr/disp.c @@ -16,12 +16,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 72e2804..112ac87 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -15,12 +15,12 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c b/drivers/staging/tidspbridge/rmgr/drv_interface.c index 27db842..6dbac3b 100644 --- a/drivers/staging/tidspbridge/rmgr/drv_interface.c +++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c @@ -19,6 +19,7 @@ /* ----------------------------------- Host OS */ #include +#include #include #include @@ -32,7 +33,6 @@ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/dspdrv.c b/drivers/staging/tidspbridge/rmgr/dspdrv.c index 19a7471..2fddbbb 100644 --- a/drivers/staging/tidspbridge/rmgr/dspdrv.c +++ b/drivers/staging/tidspbridge/rmgr/dspdrv.c @@ -17,10 +17,10 @@ */ /* ----------------------------------- Host OS */ +#include #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/mgr.c b/drivers/staging/tidspbridge/rmgr/mgr.c index b1a68ac..a7bc93b 100644 --- a/drivers/staging/tidspbridge/rmgr/mgr.c +++ b/drivers/staging/tidspbridge/rmgr/mgr.c @@ -18,8 +18,9 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include + /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index 53fd371..f59a981 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -16,9 +16,10 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include + #include -#include #include #include diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 9a46edc..928079e 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -16,11 +16,11 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index d138d11..c912572 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -16,13 +16,13 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include /* ------------------------------------ Host OS */ #include #include #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/rmm.c b/drivers/staging/tidspbridge/rmgr/rmm.c index ff33080..042d32b 100644 --- a/drivers/staging/tidspbridge/rmgr/rmm.c +++ b/drivers/staging/tidspbridge/rmgr/rmm.c @@ -37,8 +37,9 @@ * been allocated, and not yet freed. */ +#include + /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/rmgr/strm.c b/drivers/staging/tidspbridge/rmgr/strm.c index e537ee8..d31422d 100644 --- a/drivers/staging/tidspbridge/rmgr/strm.c +++ b/drivers/staging/tidspbridge/rmgr/strm.c @@ -16,11 +16,12 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include + /* ----------------------------------- Host OS */ #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/services/cfg.c b/drivers/staging/tidspbridge/services/cfg.c index 8ae64f4..699792c 100644 --- a/drivers/staging/tidspbridge/services/cfg.c +++ b/drivers/staging/tidspbridge/services/cfg.c @@ -16,8 +16,9 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include + /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ diff --git a/drivers/staging/tidspbridge/services/services.c b/drivers/staging/tidspbridge/services/services.c index 23be95c..6a7dd6f 100644 --- a/drivers/staging/tidspbridge/services/services.c +++ b/drivers/staging/tidspbridge/services/services.c @@ -16,10 +16,11 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ +#include + #include /* ----------------------------------- DSP/BIOS Bridge */ -#include #include /* ----------------------------------- Trace & Debug */ From patchwork Mon Jul 12 22:56:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111567 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMi016827 for ; Mon, 12 Jul 2010 23:00:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756149Ab0GLW4p (ORCPT ); Mon, 12 Jul 2010 18:56:45 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:39124 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755548Ab0GLW4V (ORCPT ); Mon, 12 Jul 2010 18:56:21 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuFPY010836 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:15 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuDhx016498; Mon, 12 Jul 2010 17:56:14 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuDP07279; Mon, 12 Jul 2010 17:56:13 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 5ACA1C259; Mon, 12 Jul 2010 17:56:10 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 10/11] staging: tidspbridge: remove OUT define Date: Mon, 12 Jul 2010 17:56:08 -0500 Message-Id: <1278975369-7687-11-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:04 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c index 2189796..efc167a 100644 --- a/drivers/staging/tidspbridge/core/chnl_sm.c +++ b/drivers/staging/tidspbridge/core/chnl_sm.c @@ -81,7 +81,7 @@ static void free_chirp_list(struct lst_list *pList); static struct chnl_irp *make_new_chirp(void); static int search_free_channel(struct chnl_mgr *chnl_mgr_obj, - OUT u32 *pdwChnl); + u32 *pdwChnl); /* * ======== bridge_chnl_add_io_req ======== @@ -381,7 +381,7 @@ func_cont: * Create a channel manager object, responsible for opening new channels * and closing old ones for a given board. */ -int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, +int bridge_chnl_create(struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, const struct chnl_mgrattrs *pMgrAttrs) { @@ -534,7 +534,7 @@ int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 dwTimeOut) * Retrieve information related to a channel. */ int bridge_chnl_get_info(struct chnl_object *chnl_obj, - OUT struct chnl_info *pInfo) + struct chnl_info *pInfo) { int status = 0; struct chnl_object *pchnl = (struct chnl_object *)chnl_obj; @@ -568,7 +568,7 @@ int bridge_chnl_get_info(struct chnl_object *chnl_obj, * Note: Ensures Channel Invariant (see notes above). */ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 dwTimeOut, - OUT struct chnl_ioc *pIOC) + struct chnl_ioc *pIOC) { int status = 0; struct chnl_object *pchnl = (struct chnl_object *)chnl_obj; @@ -711,7 +711,7 @@ func_end: * Retrieve information related to the channel manager. */ int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 uChnlID, - OUT struct chnl_mgrinfo *pMgrInfo) + struct chnl_mgrinfo *pMgrInfo) { int status = 0; struct chnl_mgr *chnl_mgr_obj = (struct chnl_mgr *)hchnl_mgr; @@ -775,7 +775,7 @@ int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 dwTimeOut, * ======== bridge_chnl_open ======== * Open a new half-duplex channel to the DSP board. */ -int bridge_chnl_open(OUT struct chnl_object **phChnl, +int bridge_chnl_open(struct chnl_object **phChnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, const struct chnl_attr *pattrs) { @@ -997,7 +997,7 @@ static struct chnl_irp *make_new_chirp(void) * Search for a free channel slot in the array of channel pointers. */ static int search_free_channel(struct chnl_mgr *chnl_mgr_obj, - OUT u32 *pdwChnl) + u32 *pdwChnl) { int status = -ENOSR; u32 i; diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index 87e59ca..4552c3e 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -133,7 +133,7 @@ struct io_mgr { /* Function Prototypes */ static void io_dispatch_chnl(struct io_mgr *pio_mgr, - OUT struct chnl_object *pchnl, u8 iMode); + struct chnl_object *pchnl, u8 iMode); static void io_dispatch_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr); static void io_dispatch_pm(struct io_mgr *pio_mgr); @@ -161,7 +161,7 @@ static int register_shm_segs(struct io_mgr *hio_mgr, * ======== bridge_io_create ======== * Create an IO manager object. */ -int bridge_io_create(OUT struct io_mgr **phIOMgr, +int bridge_io_create(struct io_mgr **phIOMgr, struct dev_object *hdev_obj, const struct io_attrs *pMgrAttrs) { @@ -839,7 +839,7 @@ func_end: * Proc-copy chanl dispatch. */ static void io_dispatch_chnl(struct io_mgr *pio_mgr, - OUT struct chnl_object *pchnl, u8 iMode) + struct chnl_object *pchnl, u8 iMode) { if (!pio_mgr) goto func_end; @@ -919,7 +919,7 @@ static void io_dispatch_pm(struct io_mgr *pio_mgr) * out the dispatch of I/O as a non-preemptible event.It can only be * pre-empted by an ISR. */ -void io_dpc(OUT unsigned long pRefData) +void io_dpc(unsigned long pRefData) { struct io_mgr *pio_mgr = (struct io_mgr *)pRefData; struct chnl_mgr *chnl_mgr_obj; @@ -1014,7 +1014,7 @@ void io_mbox_msg(u32 msg) * interrupts the DSP. */ void io_request_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl, - u8 iMode, OUT u16 *pwMbVal) + u8 iMode, u16 *pwMbVal) { struct chnl_mgr *chnl_mgr_obj; struct shm *sm; @@ -1793,7 +1793,7 @@ int io_sh_msetting(struct io_mgr *hio_mgr, u8 desc, void *pargs) * Gets the Processor's Load information */ int bridge_io_get_proc_load(struct io_mgr *hio_mgr, - OUT struct dsp_procloadstat *pProcStat) + struct dsp_procloadstat *pProcStat) { pProcStat->curr_load = hio_mgr->shared_mem->load_mon_info.curr_dsp_load; pProcStat->predicted_load = diff --git a/drivers/staging/tidspbridge/core/msg_sm.c b/drivers/staging/tidspbridge/core/msg_sm.c index 7fd85ce..d9c2e76 100644 --- a/drivers/staging/tidspbridge/core/msg_sm.c +++ b/drivers/staging/tidspbridge/core/msg_sm.c @@ -48,7 +48,7 @@ static void free_msg_list(struct lst_list *msgList); * Create an object to manage message queues. Only one of these objects * can exist per device object. */ -int bridge_msg_create(OUT struct msg_mgr **phMsgMgr, +int bridge_msg_create(struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, msg_onexit msgCallback) { @@ -120,7 +120,7 @@ func_end: * on the DSP. */ int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, - OUT struct msg_queue **phMsgQueue, + struct msg_queue **phMsgQueue, u32 msgq_id, u32 max_msgs, void *arg) { u32 i; diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 3731fd0..aa94f3a 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -76,7 +76,7 @@ /* Forward Declarations: */ static int bridge_brd_monitor(struct bridge_dev_context *dev_context); static int bridge_brd_read(struct bridge_dev_context *dev_context, - OUT u8 *pbHostBuf, + u8 *pbHostBuf, u32 dwDSPAddr, u32 ul_num_bytes, u32 ulMemType); static int bridge_brd_start(struct bridge_dev_context *dev_context, @@ -102,12 +102,12 @@ static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext, struct page **mapped_pages); static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext, u32 ulVirtAddr, u32 ul_num_bytes); -static int bridge_dev_create(OUT struct bridge_dev_context +static int bridge_dev_create(struct bridge_dev_context **ppDevContext, struct dev_object *hdev_obj, struct cfg_hostres *pConfig); static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, - u32 dw_cmd, OUT void *pargs); + u32 dw_cmd, void *pargs); static int bridge_dev_destroy(struct bridge_dev_context *dev_context); static u32 user_va2_pa(struct mm_struct *mm, u32 address); static int pte_update(struct bridge_dev_context *hDevContext, u32 pa, @@ -236,7 +236,7 @@ static void bad_page_dump(u32 pa, struct page *pg) * purpose: * Bridge Driver entry point. */ -void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, +void bridge_drv_entry(struct bridge_drv_interface **ppDrvInterface, const char *driver_file_name) { @@ -304,7 +304,7 @@ static int bridge_brd_monitor(struct bridge_dev_context *hDevContext) * Reads buffers for DSP memory. */ static int bridge_brd_read(struct bridge_dev_context *hDevContext, - OUT u8 *pbHostBuf, u32 dwDSPAddr, + u8 *pbHostBuf, u32 dwDSPAddr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; @@ -785,7 +785,7 @@ static int bridge_brd_write(struct bridge_dev_context *hDevContext, * ======== bridge_dev_create ======== * Creates a driver object. Puts DSP in self loop. */ -static int bridge_dev_create(OUT struct bridge_dev_context +static int bridge_dev_create(struct bridge_dev_context **ppDevContext, struct dev_object *hdev_obj, struct cfg_hostres *pConfig) @@ -954,7 +954,7 @@ func_end: * Receives device specific commands. */ static int bridge_dev_ctrl(struct bridge_dev_context *dev_context, - u32 dw_cmd, OUT void *pargs) + u32 dw_cmd, void *pargs) { int status = 0; struct bridge_ioctl_extproc *pa_ext_proc = diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c index b2d516b..4a43927 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.c +++ b/drivers/staging/tidspbridge/core/tiomap_io.c @@ -51,7 +51,7 @@ bool symbols_reloaded = true; * Copies DSP external memory buffers to the host side buffers. */ int read_ext_dsp_data(struct bridge_dev_context *hDevContext, - OUT u8 *pbHostBuf, u32 dwDSPAddr, + u8 *pbHostBuf, u32 dwDSPAddr, u32 ul_num_bytes, u32 ulMemType) { int status = 0; diff --git a/drivers/staging/tidspbridge/core/tiomap_io.h b/drivers/staging/tidspbridge/core/tiomap_io.h index 243636d..eb08f1b 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.h +++ b/drivers/staging/tidspbridge/core/tiomap_io.h @@ -48,14 +48,14 @@ * is configured by the combination of DSP MMU and shm Memory manager in the CDB */ extern int read_ext_dsp_data(struct bridge_dev_context *dev_context, - OUT u8 *pbHostBuf, u32 dwDSPAddr, + u8 *pbHostBuf, u32 dwDSPAddr, u32 ul_num_bytes, u32 ulMemType); /* * ======== write_dsp_data ======== */ extern int write_dsp_data(struct bridge_dev_context *dev_context, - OUT u8 *pbHostBuf, u32 dwDSPAddr, + u8 *pbHostBuf, u32 dwDSPAddr, u32 ul_num_bytes, u32 ulMemType); /* diff --git a/drivers/staging/tidspbridge/gen/uuidutil.c b/drivers/staging/tidspbridge/gen/uuidutil.c index 17434b6..e13bbf2 100644 --- a/drivers/staging/tidspbridge/gen/uuidutil.c +++ b/drivers/staging/tidspbridge/gen/uuidutil.c @@ -36,7 +36,7 @@ * Note: snprintf format specifier is: * %[flags] [width] [.precision] [{h | l | I64 | L}]type */ -void uuid_uuid_to_string(struct dsp_uuid *uuid_obj, OUT char *pszUuid, +void uuid_uuid_to_string(struct dsp_uuid *uuid_obj, char *pszUuid, s32 size) { s32 i; /* return result from snprintf. */ @@ -75,7 +75,7 @@ static s32 uuid_hex_to_bin(char *buf, s32 len) * Purpose: * Converts a string to a struct dsp_uuid. */ -void uuid_uuid_from_string(char *pszUuid, OUT struct dsp_uuid *uuid_obj) +void uuid_uuid_from_string(char *pszUuid, struct dsp_uuid *uuid_obj) { s32 j; diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfg.h b/drivers/staging/tidspbridge/include/dspbridge/cfg.h index 0e7961d..bdf7b37 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cfg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cfg.h @@ -51,7 +51,7 @@ extern void cfg_exit(void); * 0: *pdwAutoStart contains autostart mask for this devnode. */ extern int cfg_get_auto_start(struct cfg_devnode *dev_node_obj, - OUT u32 *pdwAutoStart); + u32 *pdwAutoStart); /* * ======== cfg_get_cd_version ======== @@ -70,7 +70,7 @@ extern int cfg_get_auto_start(struct cfg_devnode *dev_node_obj, * 0: Success. * else: *pdwVersion is NULL. */ -extern int cfg_get_cd_version(OUT u32 *pdwVersion); +extern int cfg_get_cd_version(u32 *pdwVersion); /* * ======== cfg_get_dev_object ======== @@ -91,7 +91,7 @@ extern int cfg_get_cd_version(OUT u32 *pdwVersion); * else: *pdwValue is set to 0L. */ extern int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, - OUT u32 *pdwValue); + u32 *pdwValue); /* * ======== cfg_get_exec_file ======== @@ -113,7 +113,7 @@ extern int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, * devnode. */ extern int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, - u32 buf_size, OUT char *pstrExecFile); + u32 buf_size, char *pstrExecFile); /* * ======== cfg_get_object ======== @@ -130,7 +130,7 @@ extern int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, * 0: *pdwValue is set to the retrieved u32(non-Zero). * else: *pdwValue is set to 0L. */ -extern int cfg_get_object(OUT u32 *pdwValue, u8 dw_type); +extern int cfg_get_object(u32 *pdwValue, u8 dw_type); /* * ======== cfg_get_perf_value ======== @@ -146,7 +146,7 @@ extern int cfg_get_object(OUT u32 *pdwValue, u8 dw_type); * pfEnablePerf != NULL; * Ensures: */ -extern void cfg_get_perf_value(OUT bool *pfEnablePerf); +extern void cfg_get_perf_value(bool *pfEnablePerf); /* * ======== cfg_get_zl_file ======== @@ -168,7 +168,7 @@ extern void cfg_get_perf_value(OUT bool *pfEnablePerf); * for this devnode. */ extern int cfg_get_zl_file(struct cfg_devnode *dev_node_obj, - u32 buf_size, OUT char *pstrZLFileName); + u32 buf_size, char *pstrZLFileName); /* * ======== cfg_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/chnl.h b/drivers/staging/tidspbridge/include/dspbridge/chnl.h index aa6cd77..2b49b76 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/chnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/chnl.h @@ -77,7 +77,7 @@ extern int chnl_close(struct chnl_object *chnl_obj); * board without an intervening call to * chnl_destroy() will fail. */ -extern int chnl_create(OUT struct chnl_mgr **phChnlMgr, +extern int chnl_create(struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, const struct chnl_mgrattrs *pMgrAttrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmm.h b/drivers/staging/tidspbridge/include/dspbridge/cmm.h index 70e9dc5..8bae008 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cmm.h @@ -62,7 +62,7 @@ */ extern void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize, struct cmm_attrs *pattrs, - OUT void **pp_buf_va); + void **pp_buf_va); /* * ======== cmm_create ======== @@ -85,7 +85,7 @@ extern void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, * Ensures: * */ -extern int cmm_create(OUT struct cmm_object **ph_cmm_mgr, +extern int cmm_create(struct cmm_object **ph_cmm_mgr, struct dev_object *hdev_obj, const struct cmm_mgrattrs *pMgrAttrs); @@ -163,7 +163,7 @@ extern int cmm_free_buf(struct cmm_object *hcmm_mgr, * Ensures: */ extern int cmm_get_handle(void *hprocessor, - OUT struct cmm_object **ph_cmm_mgr); + struct cmm_object **ph_cmm_mgr); /* * ======== cmm_get_info ======== @@ -182,7 +182,7 @@ extern int cmm_get_handle(void *hprocessor, * */ extern int cmm_get_info(struct cmm_object *hcmm_mgr, - OUT struct cmm_info *cmm_info_obj); + struct cmm_info *cmm_info_obj); /* * ======== cmm_init ======== @@ -295,7 +295,7 @@ extern void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator, * Ensures: * */ -extern int cmm_xlator_create(OUT struct cmm_xlatorobject **phXlator, +extern int cmm_xlator_create(struct cmm_xlatorobject **phXlator, struct cmm_object *hcmm_mgr, struct cmm_xlatorattrs *pXlatorAttrs); @@ -359,7 +359,7 @@ extern int cmm_xlator_free_buf(struct cmm_xlatorobject *xlator, * */ extern int cmm_xlator_info(struct cmm_xlatorobject *xlator, - OUT u8 **paddr, + u8 **paddr, u32 ul_size, u32 uSegId, bool set_info); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/cod.h b/drivers/staging/tidspbridge/include/dspbridge/cod.h index 25817fc..3850de2 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cod.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cod.h @@ -91,7 +91,7 @@ extern void cod_close(struct cod_libraryobj *lib); * pstrZLFile != NULL * Ensures: */ -extern int cod_create(OUT struct cod_manager **phManager, +extern int cod_create(struct cod_manager **phManager, char *pstrZLFile, const struct cod_attrs *attrs); @@ -227,7 +227,7 @@ extern int cod_get_loader(struct cod_manager *cod_mgr_obj, */ extern int cod_get_section(struct cod_libraryobj *lib, char *pstrSect, - OUT u32 *puAddr, OUT u32 *puLen); + u32 *puAddr, u32 *puLen); /* * ======== cod_get_sym_value ======== @@ -251,7 +251,7 @@ extern int cod_get_section(struct cod_libraryobj *lib, * Ensures: */ extern int cod_get_sym_value(struct cod_manager *cod_mgr_obj, - char *pstrSym, OUT u32 * pul_value); + char *pstrSym, u32 * pul_value); /* * ======== cod_init ======== @@ -321,7 +321,7 @@ extern int cod_load_base(struct cod_manager *cod_mgr_obj, */ extern int cod_open(struct cod_manager *hmgr, char *pszCoffPath, - u32 flags, OUT struct cod_libraryobj **pLib); + u32 flags, struct cod_libraryobj **pLib); /* * ======== cod_open_base ======== @@ -364,6 +364,6 @@ extern int cod_open_base(struct cod_manager *hmgr, char *pszCoffPath, */ extern int cod_read_section(struct cod_libraryobj *lib, char *pstrSect, - OUT char *pstrContent, u32 content_size); + char *pstrContent, u32 content_size); #endif /* COD_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h index 6d32e02..61a01a6 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbdcd.h @@ -90,7 +90,7 @@ extern int dcd_auto_unregister(struct dcd_manager *hdcd_mgr, * A DCD manager handle is created. */ extern int dcd_create_manager(char *pszZlDllName, - OUT struct dcd_manager **phDcdMgr); + struct dcd_manager **phDcdMgr); /* * ======== dcd_destroy_manager ======== @@ -130,7 +130,7 @@ extern int dcd_destroy_manager(struct dcd_manager *hdcd_mgr); */ extern int dcd_enumerate_object(s32 index, enum dsp_dcdobjtype obj_type, - OUT struct dsp_uuid *uuid_obj); + struct dsp_uuid *uuid_obj); /* * ======== dcd_exit ======== @@ -172,8 +172,8 @@ extern void dcd_exit(void); extern int dcd_get_dep_libs(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, u16 numLibs, - OUT struct dsp_uuid *pDepLibUuids, - OUT bool *pPersistentDepLibs, + struct dsp_uuid *pDepLibUuids, + bool *pPersistentDepLibs, enum nldr_phase phase); /* @@ -201,8 +201,8 @@ extern int dcd_get_dep_libs(struct dcd_manager *hdcd_mgr, */ extern int dcd_get_num_dep_libs(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, - OUT u16 *pNumLibs, - OUT u16 *pNumPersLibs, + u16 *pNumLibs, + u16 *pNumPersLibs, enum nldr_phase phase); /* @@ -231,10 +231,10 @@ extern int dcd_get_num_dep_libs(struct dcd_manager *hdcd_mgr, */ extern int dcd_get_library_name(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, - OUT char *pstrLibName, - OUT u32 *pdwSize, + char *pstrLibName, + u32 *pdwSize, enum nldr_phase phase, - OUT bool *phase_split); + bool *phase_split); /* * ======== dcd_get_object_def ======== @@ -264,7 +264,7 @@ extern int dcd_get_library_name(struct dcd_manager *hdcd_mgr, extern int dcd_get_object_def(struct dcd_manager *hdcd_mgr, struct dsp_uuid *pObjUuid, enum dsp_dcdobjtype obj_type, - OUT struct dcd_genericobj *pObjDef); + struct dcd_genericobj *pObjDef); /* * ======== dcd_get_objects ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dev.h b/drivers/staging/tidspbridge/include/dspbridge/dev.h index 4c0658d..664f66b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dev.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dev.h @@ -89,7 +89,7 @@ extern u32 dev_brd_write_fxn(void *pArb, * Otherwise, does not create the device object, ensures the Bridge driver * module is unloaded, and sets *phDevObject to NULL. */ -extern int dev_create_device(OUT struct dev_object +extern int dev_create_device(struct dev_object **phDevObject, const char *driver_file_name, struct cfg_devnode *dev_node_obj); @@ -124,7 +124,7 @@ extern int dev_create_device(OUT struct dev_object * Otherwise, does not create the device object, ensures the Bridge driver * module is unloaded, and sets *phDevObject to NULL. */ -extern int dev_create_iva_device(OUT struct dev_object +extern int dev_create_iva_device(struct dev_object **phDevObject, const char *driver_file_name, const struct cfg_hostres @@ -208,7 +208,7 @@ extern int dev_destroy_device(struct dev_object * else: *phMgr is NULL. */ extern int dev_get_chnl_mgr(struct dev_object *hdev_obj, - OUT struct chnl_mgr **phMgr); + struct chnl_mgr **phMgr); /* * ======== dev_get_cmm_mgr ======== @@ -231,7 +231,7 @@ extern int dev_get_chnl_mgr(struct dev_object *hdev_obj, * else: *phMgr is NULL. */ extern int dev_get_cmm_mgr(struct dev_object *hdev_obj, - OUT struct cmm_object **phMgr); + struct cmm_object **phMgr); /* * ======== dev_get_dmm_mgr ======== @@ -254,7 +254,7 @@ extern int dev_get_cmm_mgr(struct dev_object *hdev_obj, * else: *phMgr is NULL. */ extern int dev_get_dmm_mgr(struct dev_object *hdev_obj, - OUT struct dmm_object **phMgr); + struct dmm_object **phMgr); /* * ======== dev_get_cod_mgr ======== @@ -275,7 +275,7 @@ extern int dev_get_dmm_mgr(struct dev_object *hdev_obj, * else: *phCodMgr is NULL. */ extern int dev_get_cod_mgr(struct dev_object *hdev_obj, - OUT struct cod_manager **phCodMgr); + struct cod_manager **phCodMgr); /* * ======== dev_get_deh_mgr ======== @@ -295,7 +295,7 @@ extern int dev_get_cod_mgr(struct dev_object *hdev_obj, * else: *phDehMgr is NULL. */ extern int dev_get_deh_mgr(struct dev_object *hdev_obj, - OUT struct deh_mgr **phDehMgr); + struct deh_mgr **phDehMgr); /* * ======== dev_get_dev_node ======== @@ -316,7 +316,7 @@ extern int dev_get_deh_mgr(struct dev_object *hdev_obj, * else: *phDevNode is NULL. */ extern int dev_get_dev_node(struct dev_object *hdev_obj, - OUT struct cfg_devnode **phDevNode); + struct cfg_devnode **phDevNode); /* * ======== dev_get_dev_type ======== @@ -380,7 +380,7 @@ extern struct dev_object *dev_get_first(void); * else: *ppIntfFxns is NULL. */ extern int dev_get_intf_fxns(struct dev_object *hdev_obj, - OUT struct bridge_drv_interface **ppIntfFxns); + struct bridge_drv_interface **ppIntfFxns); /* * ======== dev_get_io_mgr ======== @@ -401,7 +401,7 @@ extern int dev_get_intf_fxns(struct dev_object *hdev_obj, * else: *phMgr is NULL. */ extern int dev_get_io_mgr(struct dev_object *hdev_obj, - OUT struct io_mgr **phMgr); + struct io_mgr **phMgr); /* * ======== dev_get_next ======== @@ -443,7 +443,7 @@ extern struct dev_object *dev_get_next(struct dev_object * Ensures: */ extern void dev_get_msg_mgr(struct dev_object *hdev_obj, - OUT struct msg_mgr **phMsgMgr); + struct msg_mgr **phMsgMgr); /* * ========= dev_get_node_manager ======== @@ -466,7 +466,7 @@ extern void dev_get_msg_mgr(struct dev_object *hdev_obj, */ extern int dev_get_node_manager(struct dev_object *hdev_obj, - OUT struct node_mgr **phNodeMgr); + struct node_mgr **phNodeMgr); /* * ======== dev_get_symbol ======== @@ -490,7 +490,7 @@ extern int dev_get_node_manager(struct dev_object * 0: *pul_value contains the symbol value; */ extern int dev_get_symbol(struct dev_object *hdev_obj, - const char *pstrSym, OUT u32 * pul_value); + const char *pstrSym, u32 * pul_value); /* * ======== dev_get_bridge_context ======== @@ -511,7 +511,7 @@ extern int dev_get_symbol(struct dev_object *hdev_obj, * else: *phbridge_context is NULL; */ extern int dev_get_bridge_context(struct dev_object *hdev_obj, - OUT struct bridge_dev_context + struct bridge_dev_context **phbridge_context); /* @@ -585,7 +585,7 @@ extern int dev_is_locked(struct dev_object *hdev_obj); extern int dev_insert_proc_object(struct dev_object *hdev_obj, u32 proc_obj, - OUT bool *pbAlreadyAttached); + bool *pbAlreadyAttached); /* * ======== dev_remove_proc_object ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/disp.h b/drivers/staging/tidspbridge/include/dspbridge/disp.h index abadc79..5a12a88 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/disp.h +++ b/drivers/staging/tidspbridge/include/dspbridge/disp.h @@ -48,7 +48,7 @@ * 0: IS_VALID(*phDispObject). * error: *phDispObject == NULL. */ -extern int disp_create(OUT struct disp_object **phDispObject, +extern int disp_create(struct disp_object **phDispObject, struct dev_object *hdev_obj, const struct disp_attr *pDispAttrs); @@ -148,7 +148,7 @@ extern int disp_node_create(struct disp_object *hDispObject, u32 ul_fxn_addr, u32 ul_create_fxn, const struct node_createargs - *pargs, OUT nodeenv *pNodeEnv); + *pargs, nodeenv *pNodeEnv); /* * ======== disp_node_delete ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dmm.h b/drivers/staging/tidspbridge/include/dspbridge/dmm.h index 72882b7..b8739c1 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dmm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dmm.h @@ -39,7 +39,7 @@ struct dmm_mgrattrs { */ extern int dmm_get_handle(void *hprocessor, - OUT struct dmm_object **phDmmMgr); + struct dmm_object **phDmmMgr); extern int dmm_reserve_memory(struct dmm_object *dmm_mgr, u32 size, u32 *prsv_addr); @@ -57,7 +57,7 @@ extern int dmm_destroy(struct dmm_object *dmm_mgr); extern int dmm_delete_tables(struct dmm_object *dmm_mgr); -extern int dmm_create(OUT struct dmm_object **phDmmMgr, +extern int dmm_create(struct dmm_object **phDmmMgr, struct dev_object *hdev_obj, const struct dmm_mgrattrs *pMgrAttrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h b/drivers/staging/tidspbridge/include/dspbridge/drv.h index 753a317..1972e41 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/drv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h @@ -394,7 +394,7 @@ extern int drv_remove_dev_object(struct drv_object *hdrv_obj, * later used by the CFG module. */ extern int drv_request_resources(u32 dw_context, - OUT u32 *pDevNodeString); + u32 *pDevNodeString); /* * ======== drv_release_resources ======== @@ -463,7 +463,7 @@ extern void mem_ext_phys_pool_release(void); * location of memory. */ extern void *mem_alloc_phys_mem(u32 byte_size, - u32 ulAlign, OUT u32 *pPhysicalAddress); + u32 ulAlign, u32 *pPhysicalAddress); /* * ======== mem_free_phys_mem ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h b/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h index cc4e75b..2ad6089 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h @@ -339,7 +339,7 @@ union Trapped_Args { struct cmm_object *hcmm_mgr; u32 usize; struct cmm_attrs *pattrs; - OUT void **pp_buf_va; + void **pp_buf_va; } args_cmm_allocbuf; struct { diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h index 8b943cc..7c2447f 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspchnl.h @@ -24,14 +24,14 @@ #ifndef DSPCHNL_ #define DSPCHNL_ -extern int bridge_chnl_create(OUT struct chnl_mgr **phChnlMgr, +extern int bridge_chnl_create(struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, const struct chnl_mgrattrs *pMgrAttrs); extern int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr); -extern int bridge_chnl_open(OUT struct chnl_object **phChnl, +extern int bridge_chnl_open(struct chnl_object **phChnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, u32 uChnlId, @@ -46,7 +46,7 @@ extern int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, u32 dw_dsp_addr, u32 dw_arg); extern int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, - u32 dwTimeOut, OUT struct chnl_ioc *pIOC); + u32 dwTimeOut, struct chnl_ioc *pIOC); extern int bridge_chnl_cancel_io(struct chnl_object *chnl_obj); @@ -54,10 +54,10 @@ extern int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 dwTimeOut); extern int bridge_chnl_get_info(struct chnl_object *chnl_obj, - OUT struct chnl_info *pInfo); + struct chnl_info *pInfo); extern int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, - u32 uChnlID, OUT struct chnl_mgrinfo + u32 uChnlID, struct chnl_mgrinfo *pMgrInfo); extern int bridge_chnl_idle(struct chnl_object *chnl_obj, diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h index 467ec8b..b772c5d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h @@ -262,7 +262,7 @@ typedef int(*fxn_brd_status) (struct bridge_dev_context *hDevContext, * Will not write more than ul_num_bytes bytes into pHostBuf. */ typedef int(*fxn_brd_read) (struct bridge_dev_context *hDevContext, - OUT u8 *pHostBuf, + u8 *pHostBuf, u32 dwDSPAddr, u32 ul_num_bytes, u32 ulMemType); @@ -322,7 +322,7 @@ typedef int(*fxn_brd_write) (struct bridge_dev_context *hDevContext, * No channel manager exists for this board. * Ensures: */ -typedef int(*fxn_chnl_create) (OUT struct chnl_mgr +typedef int(*fxn_chnl_create) (struct chnl_mgr **phChnlMgr, struct dev_object * hdev_obj, @@ -406,7 +406,7 @@ typedef void (*fxn_deh_notify) (struct deh_mgr *hdeh_mgr, * 0: *phChnl is a valid channel. * else: *phChnl is set to NULL if (phChnl != NULL); */ -typedef int(*fxn_chnl_open) (OUT struct chnl_object +typedef int(*fxn_chnl_open) (struct chnl_object **phChnl, struct chnl_mgr *hchnl_mgr, s8 chnl_mode, @@ -502,7 +502,7 @@ typedef int(*fxn_chnl_addioreq) (struct chnl_object */ typedef int(*fxn_chnl_getioc) (struct chnl_object *chnl_obj, u32 dwTimeOut, - OUT struct chnl_ioc *pIOC); + struct chnl_ioc *pIOC); /* * ======== bridge_chnl_cancel_io ======== @@ -560,7 +560,7 @@ typedef int(*fxn_chnl_flushio) (struct chnl_object *chnl_obj, * if (pInfo != NULL). */ typedef int(*fxn_chnl_getinfo) (struct chnl_object *chnl_obj, - OUT struct chnl_info *pChnlInfo); + struct chnl_info *pChnlInfo); /* * ======== bridge_chnl_get_mgr_info ======== @@ -582,7 +582,7 @@ typedef int(*fxn_chnl_getinfo) (struct chnl_object *chnl_obj, typedef int(*fxn_chnl_getmgrinfo) (struct chnl_mgr * hchnl_mgr, u32 uChnlID, - OUT struct chnl_mgrinfo *pMgrInfo); + struct chnl_mgrinfo *pMgrInfo); /* * ======== bridge_chnl_idle ======== @@ -678,7 +678,7 @@ typedef int(*fxn_chnl_registernotify) * function returns, they must not be stored into the device context * structure. */ -typedef int(*fxn_dev_create) (OUT struct bridge_dev_context +typedef int(*fxn_dev_create) (struct bridge_dev_context **phDevContext, struct dev_object * hdev_obj, @@ -702,7 +702,7 @@ typedef int(*fxn_dev_create) (OUT struct bridge_dev_context * Ensures: */ typedef int(*fxn_dev_ctrl) (struct bridge_dev_context *hDevContext, - u32 dw_cmd, OUT void *pargs); + u32 dw_cmd, void *pargs); /* * ======== bridge_dev_destroy ======== @@ -743,7 +743,7 @@ typedef int(*fxn_dev_destroy) (struct bridge_dev_context *hDevContext); * phIOMgr != NULL; * Ensures: */ -typedef int(*fxn_io_create) (OUT struct io_mgr **phIOMgr, +typedef int(*fxn_io_create) (struct io_mgr **phIOMgr, struct dev_object *hdev_obj, const struct io_attrs *pMgrAttrs); @@ -817,7 +817,7 @@ typedef int(*fxn_io_getprocload) (struct io_mgr *hio_mgr, * Ensures: */ typedef int(*fxn_msg_create) - (OUT struct msg_mgr **phMsgMgr, + (struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, msg_onexit msgCallback); /* @@ -844,7 +844,7 @@ typedef int(*fxn_msg_create) */ typedef int(*fxn_msg_createqueue) (struct msg_mgr *hmsg_mgr, - OUT struct msg_queue **phMsgQueue, u32 msgq_id, u32 max_msgs, void *h); + struct msg_queue **phMsgQueue, u32 msgq_id, u32 max_msgs, void *h); /* * ======== bridge_msg_delete ======== @@ -1047,7 +1047,7 @@ struct bridge_drv_interface { * Details: * Called during the Device_Init phase. */ -void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface, +void bridge_drv_entry(struct bridge_drv_interface **ppDrvInterface, const char *driver_file_name); #endif /* DSPDEFS_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdrv.h b/drivers/staging/tidspbridge/include/dspbridge/dspdrv.h index 2dd4f8b..865f6fe 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspdrv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspdrv.h @@ -57,6 +57,6 @@ extern bool dsp_deinit(u32 dwDeviceContext); * Succeeded: device context > 0 * Failed: device Context = 0 */ -extern u32 dsp_init(OUT u32 *init_status); +extern u32 dsp_init(u32 *init_status); #endif diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspio.h b/drivers/staging/tidspbridge/include/dspbridge/dspio.h index f382f1a..22dc49c 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspio.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspio.h @@ -26,7 +26,7 @@ #include #include -extern int bridge_io_create(OUT struct io_mgr **phIOMgr, +extern int bridge_io_create(struct io_mgr **phIOMgr, struct dev_object *hdev_obj, const struct io_attrs *pMgrAttrs); @@ -36,6 +36,6 @@ extern int bridge_io_on_loaded(struct io_mgr *hio_mgr); extern int iva_io_on_loaded(struct io_mgr *hio_mgr); extern int bridge_io_get_proc_load(struct io_mgr *hio_mgr, - OUT struct dsp_procloadstat *pProcStat); + struct dsp_procloadstat *pProcStat); #endif /* DSPIO_ */ diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h index 3b9ca4e..7c31bdc 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dspmsg.h @@ -26,12 +26,12 @@ #include -extern int bridge_msg_create(OUT struct msg_mgr **phMsgMgr, +extern int bridge_msg_create(struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, msg_onexit msgCallback); extern int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, - OUT struct msg_queue **phMsgQueue, + struct msg_queue **phMsgQueue, u32 msgq_id, u32 max_msgs, void *h); extern void bridge_msg_delete(struct msg_mgr *hmsg_mgr); diff --git a/drivers/staging/tidspbridge/include/dspbridge/io.h b/drivers/staging/tidspbridge/include/dspbridge/io.h index 8241547..337c299 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io.h @@ -49,7 +49,7 @@ * pMgrAttrs != NULL. * Ensures: */ -extern int io_create(OUT struct io_mgr **phIOMgr, +extern int io_create(struct io_mgr **phIOMgr, struct dev_object *hdev_obj, const struct io_attrs *pMgrAttrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h index 64cb274..2ae2866 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/io_sm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/io_sm.h @@ -78,7 +78,7 @@ extern void io_cancel_chnl(struct io_mgr *hio_mgr, u32 ulChnl); * Ensures: * Non-preemptible (but interruptible). */ -extern void io_dpc(OUT unsigned long pRefData); +extern void io_dpc(unsigned long pRefData); /* * ======== io_mbox_msg ======== @@ -116,7 +116,7 @@ void io_mbox_msg(u32 msg); */ extern void io_request_chnl(struct io_mgr *hio_mgr, struct chnl_object *pchnl, - u8 iMode, OUT u16 *pwMbVal); + u8 iMode, u16 *pwMbVal); /* * ======== iosm_schedule ======== @@ -190,7 +190,7 @@ extern void io_ddma_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId); extern void io_ddma_request_chnl(struct io_mgr *hio_mgr, struct chnl_object *pchnl, struct chnl_irp *chnl_packet_obj, - OUT u16 *pwMbVal); + u16 *pwMbVal); /* * Zero-copy IO functions @@ -245,7 +245,7 @@ extern void io_ddzc_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uChnlId); extern void io_ddzc_request_chnl(struct io_mgr *hio_mgr, struct chnl_object *pchnl, struct chnl_irp *chnl_packet_obj, - OUT u16 *pwMbVal); + u16 *pwMbVal); /* * ======== io_sh_msetting ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/mgr.h b/drivers/staging/tidspbridge/include/dspbridge/mgr.h index adfd9b5..f24a7ba 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/mgr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/mgr.h @@ -40,7 +40,7 @@ int mgr_wait_for_bridge_events(struct dsp_notification **anotifications, - u32 count, OUT u32 *pu_index, + u32 count, u32 *pu_index, u32 utimeout); /* @@ -66,7 +66,7 @@ int mgr_wait_for_bridge_events(struct dsp_notification * Details: * DCD Dll is loaded and MGR Object stores the handle of the DLL. */ -extern int mgr_create(OUT struct mgr_object **hmgr_obj, +extern int mgr_create(struct mgr_object **hmgr_obj, struct cfg_devnode *dev_node_obj); /* @@ -119,9 +119,9 @@ extern int mgr_destroy(struct mgr_object *hmgr_obj); * Details: */ extern int mgr_enum_node_info(u32 node_id, - OUT struct dsp_ndbprops *pndb_props, + struct dsp_ndbprops *pndb_props, u32 undb_props_size, - OUT u32 *pu_num_nodes); + u32 *pu_num_nodes); /* * ======== mgr_enum_processor_info ======== @@ -150,10 +150,10 @@ extern int mgr_enum_node_info(u32 node_id, * Details: */ extern int mgr_enum_processor_info(u32 processor_id, - OUT struct dsp_processorinfo + struct dsp_processorinfo *processor_info, u32 processor_info_size, - OUT u8 *pu_num_procs); + u8 *pu_num_procs); /* * ======== mgr_exit ======== * Purpose: @@ -186,7 +186,7 @@ extern void mgr_exit(void); * -EPERM and *phDCDHandle == NULL */ extern int mgr_get_dcd_handle(struct mgr_object - *hMGRHandle, OUT u32 *phDCDHandle); + *hMGRHandle, u32 *phDCDHandle); /* * ======== mgr_init ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/msg.h b/drivers/staging/tidspbridge/include/dspbridge/msg.h index baac5f3..b849fc4 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/msg.h +++ b/drivers/staging/tidspbridge/include/dspbridge/msg.h @@ -40,7 +40,7 @@ * msgCallback != NULL. * Ensures: */ -extern int msg_create(OUT struct msg_mgr **phMsgMgr, +extern int msg_create(struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, msg_onexit msgCallback); diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldr.h b/drivers/staging/tidspbridge/include/dspbridge/nldr.h index d8c9688..a1b1996 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldr.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldr.h @@ -28,10 +28,10 @@ extern int nldr_allocate(struct nldr_object *nldr_obj, void *priv_ref, const struct dcd_nodeprops *node_props, - OUT struct nldr_nodeobject **phNldrNode, + struct nldr_nodeobject **phNldrNode, bool *pf_phase_split); -extern int nldr_create(OUT struct nldr_object **phNldr, +extern int nldr_create(struct nldr_object **phNldr, struct dev_object *hdev_obj, const struct nldr_attrs *pattrs); @@ -42,7 +42,7 @@ extern int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, char *pstrFxn, u32 * pulAddr); extern int nldr_get_rmm_manager(struct nldr_object *hNldrObject, - OUT struct rmm_target_obj **phRmmMgr); + struct rmm_target_obj **phRmmMgr); extern bool nldr_init(void); extern int nldr_load(struct nldr_nodeobject *nldr_node_obj, diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h index 2f9bea3..af5362e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h @@ -131,9 +131,9 @@ typedef int(*nldr_allocatefxn) (struct nldr_object *nldr_obj, void *priv_ref, const struct dcd_nodeprops * node_props, - OUT struct nldr_nodeobject + struct nldr_nodeobject **phNldrNode, - OUT bool *pf_phase_split); + bool *pf_phase_split); /* * ======== nldr_create ======== @@ -156,7 +156,7 @@ typedef int(*nldr_allocatefxn) (struct nldr_object *nldr_obj, * 0: Valid *phNldr. * error: *phNldr == NULL. */ -typedef int(*nldr_createfxn) (OUT struct nldr_object **phNldr, +typedef int(*nldr_createfxn) (struct nldr_object **phNldr, struct dev_object *hdev_obj, const struct nldr_attrs *pattrs); diff --git a/drivers/staging/tidspbridge/include/dspbridge/node.h b/drivers/staging/tidspbridge/include/dspbridge/node.h index 7be6dda..8ec348b 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/node.h +++ b/drivers/staging/tidspbridge/include/dspbridge/node.h @@ -60,7 +60,7 @@ extern int node_allocate(struct proc_object *hprocessor, const struct dsp_cbdata *pargs, const struct dsp_nodeattrin *attr_in, - OUT struct node_object **ph_node, + struct node_object **ph_node, struct process_context *pr_ctxt); /* @@ -87,7 +87,7 @@ extern int node_allocate(struct proc_object *hprocessor, */ extern int node_alloc_msg_buf(struct node_object *hnode, u32 usize, struct dsp_bufferattr - *pattr, OUT u8 **pbuffer); + *pattr, u8 **pbuffer); /* * ======== node_change_priority ======== @@ -231,7 +231,7 @@ extern int node_create(struct node_object *hnode); * 0: Valide *phNodeMgr. * error: *phNodeMgr == NULL. */ -extern int node_create_mgr(OUT struct node_mgr **phNodeMgr, +extern int node_create_mgr(struct node_mgr **phNodeMgr, struct dev_object *hdev_obj); /* @@ -299,8 +299,8 @@ extern int node_delete_mgr(struct node_mgr *hnode_mgr); extern int node_enum_nodes(struct node_mgr *hnode_mgr, void **node_tab, u32 node_tab_size, - OUT u32 *pu_num_nodes, - OUT u32 *pu_allocated); + u32 *pu_num_nodes, + u32 *pu_allocated); /* * ======== node_exit ======== @@ -358,7 +358,7 @@ extern int node_free_msg_buf(struct node_object *hnode, * 0: *pattrs contains the node's current attributes. */ extern int node_get_attr(struct node_object *hnode, - OUT struct dsp_nodeattr *pattr, u32 attr_size); + struct dsp_nodeattr *pattr, u32 attr_size); /* * ======== node_get_message ======== @@ -384,7 +384,7 @@ extern int node_get_attr(struct node_object *hnode, * Ensures: */ extern int node_get_message(struct node_object *hnode, - OUT struct dsp_msg *message, u32 utimeout); + struct dsp_msg *message, u32 utimeout); /* * ======== node_get_nldr_obj ======== @@ -399,7 +399,7 @@ extern int node_get_message(struct node_object *hnode, * Ensures: */ extern int node_get_nldr_obj(struct node_mgr *hnode_mgr, - OUT struct nldr_object **phNldrObj); + struct nldr_object **phNldrObj); /* * ======== node_init ======== @@ -544,7 +544,7 @@ extern int node_run(struct node_object *hnode); * Ensures: */ extern int node_terminate(struct node_object *hnode, - OUT int *pstatus); + int *pstatus); /* * ======== node_get_uuid_props ======== @@ -555,7 +555,7 @@ extern int node_terminate(struct node_object *hnode, */ extern int node_get_uuid_props(void *hprocessor, const struct dsp_uuid *pNodeId, - OUT struct dsp_ndbprops + struct dsp_ndbprops *node_props); #ifdef CONFIG_TIDSPBRIDGE_BACKTRACE diff --git a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h index 42e1a94..c6e1c09 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h +++ b/drivers/staging/tidspbridge/include/dspbridge/nodepriv.h @@ -102,7 +102,7 @@ struct node_createargs { * Ensures: */ extern int node_get_channel_id(struct node_object *hnode, - u32 dir, u32 index, OUT u32 *pulId); + u32 dir, u32 index, u32 *pulId); /* * ======== node_get_strm_mgr ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/proc.h b/drivers/staging/tidspbridge/include/dspbridge/proc.h index 12f2f2a..0c0a4ec 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/proc.h +++ b/drivers/staging/tidspbridge/include/dspbridge/proc.h @@ -153,8 +153,8 @@ extern int proc_detach(struct process_context *pr_ctxt); extern int proc_enum_nodes(void *hprocessor, void **node_tab, u32 node_tab_size, - OUT u32 *pu_num_nodes, - OUT u32 *pu_allocated); + u32 *pu_num_nodes, + u32 *pu_allocated); /* * ======== proc_get_resource_info ======== @@ -184,7 +184,7 @@ extern int proc_enum_nodes(void *hprocessor, */ extern int proc_get_resource_info(void *hprocessor, u32 resource_type, - OUT struct dsp_resourceinfo + struct dsp_resourceinfo *resource_info, u32 resource_info_size); @@ -256,7 +256,7 @@ extern bool proc_init(void); * Ensures: * Details: */ -extern int proc_get_state(void *hprocessor, OUT struct dsp_processorstate +extern int proc_get_state(void *hprocessor, struct dsp_processorstate *proc_state_obj, u32 state_info_size); /* diff --git a/drivers/staging/tidspbridge/include/dspbridge/strm.h b/drivers/staging/tidspbridge/include/dspbridge/strm.h index 7b7a243..e1b68d6 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/strm.h +++ b/drivers/staging/tidspbridge/include/dspbridge/strm.h @@ -46,7 +46,7 @@ */ extern int strm_allocate_buffer(struct strm_object *hStrm, u32 usize, - OUT u8 **ap_buffer, + u8 **ap_buffer, u32 num_bufs, struct process_context *pr_ctxt); @@ -90,7 +90,7 @@ extern int strm_close(struct strm_object *hStrm, * 0: Valid *phStrmMgr. * error: *phStrmMgr == NULL. */ -extern int strm_create(OUT struct strm_mgr **phStrmMgr, +extern int strm_create(struct strm_mgr **phStrmMgr, struct dev_object *dev_obj); /* @@ -158,7 +158,7 @@ extern int strm_free_buffer(struct strm_object *hStrm, * Ensures: */ extern int strm_get_event_handle(struct strm_object *hStrm, - OUT void **ph_event); + void **ph_event); /* * ======== strm_get_info ======== @@ -180,7 +180,7 @@ extern int strm_get_event_handle(struct strm_object *hStrm, * Ensures: */ extern int strm_get_info(struct strm_object *hStrm, - OUT struct stream_info *stream_info, + struct stream_info *stream_info, u32 stream_info_size); /* @@ -272,7 +272,7 @@ extern int strm_issue(struct strm_object *hStrm, u8 * pbuf, */ extern int strm_open(struct node_object *hnode, u32 dir, u32 index, struct strm_attr *pattr, - OUT struct strm_object **phStrm, + struct strm_object **phStrm, struct process_context *pr_ctxt); /* @@ -322,7 +322,7 @@ extern int strm_prepare_buffer(struct strm_object *hStrm, * Ensures: */ extern int strm_reclaim(struct strm_object *hStrm, - OUT u8 **buf_ptr, u32 * pulBytes, + u8 **buf_ptr, u32 * pulBytes, u32 *pulBufSize, u32 *pdw_arg); /* @@ -377,7 +377,7 @@ extern int strm_register_notify(struct strm_object *hStrm, * Error: *pmask == 0. */ extern int strm_select(struct strm_object **strm_tab, - u32 nStrms, OUT u32 *pmask, u32 utimeout); + u32 nStrms, u32 *pmask, u32 utimeout); /* * ======== strm_unprepare_buffer ======== diff --git a/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h b/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h index a7a64f2..db9dc1e 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h +++ b/drivers/staging/tidspbridge/include/dspbridge/uuidutil.h @@ -38,7 +38,7 @@ * Details: * UUID string limit currently set at MAXUUIDLEN. */ -void uuid_uuid_to_string(struct dsp_uuid *uuid_obj, OUT char *pszUuid, +void uuid_uuid_to_string(struct dsp_uuid *uuid_obj, char *pszUuid, s32 size); /* @@ -57,6 +57,6 @@ void uuid_uuid_to_string(struct dsp_uuid *uuid_obj, OUT char *pszUuid, * "12345678_1234_1234_1234_123456789abc". */ extern void uuid_uuid_from_string(char *pszUuid, - OUT struct dsp_uuid *uuid_obj); + struct dsp_uuid *uuid_obj); #endif /* UUIDUTIL_ */ diff --git a/drivers/staging/tidspbridge/pmgr/chnl.c b/drivers/staging/tidspbridge/pmgr/chnl.c index c9787fb..afb48a0 100644 --- a/drivers/staging/tidspbridge/pmgr/chnl.c +++ b/drivers/staging/tidspbridge/pmgr/chnl.c @@ -51,7 +51,7 @@ static u32 refs; * Create a channel manager object, responsible for opening new channels * and closing old ones for a given 'Bridge board. */ -int chnl_create(OUT struct chnl_mgr **phChnlMgr, +int chnl_create(struct chnl_mgr **phChnlMgr, struct dev_object *hdev_obj, const struct chnl_mgrattrs *pMgrAttrs) { diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c index 9f9b5c5..32e396a 100644 --- a/drivers/staging/tidspbridge/pmgr/cmm.c +++ b/drivers/staging/tidspbridge/pmgr/cmm.c @@ -164,7 +164,7 @@ static void un_register_gppsm_seg(struct cmm_allocator *psma); * inUseList. */ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize, - struct cmm_attrs *pattrs, OUT void **pp_buf_va) + struct cmm_attrs *pattrs, void **pp_buf_va) { struct cmm_object *cmm_mgr_obj = (struct cmm_object *)hcmm_mgr; void *buf_pa = NULL; @@ -240,7 +240,7 @@ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize, * Purpose: * Create a communication memory manager object. */ -int cmm_create(OUT struct cmm_object **ph_cmm_mgr, +int cmm_create(struct cmm_object **ph_cmm_mgr, struct dev_object *hdev_obj, const struct cmm_mgrattrs *pMgrAttrs) { @@ -429,7 +429,7 @@ int cmm_free_buf(struct cmm_object *hcmm_mgr, void *buf_pa, * Return the communication memory manager object for this device. * This is typically called from the client process. */ -int cmm_get_handle(void *hprocessor, OUT struct cmm_object ** ph_cmm_mgr) +int cmm_get_handle(void *hprocessor, struct cmm_object ** ph_cmm_mgr) { int status = 0; struct dev_object *hdev_obj; @@ -453,7 +453,7 @@ int cmm_get_handle(void *hprocessor, OUT struct cmm_object ** ph_cmm_mgr) * Return the current memory utilization information. */ int cmm_get_info(struct cmm_object *hcmm_mgr, - OUT struct cmm_info *cmm_info_obj) + struct cmm_info *cmm_info_obj) { struct cmm_object *cmm_mgr_obj = (struct cmm_object *)hcmm_mgr; u32 ul_seg; @@ -954,7 +954,7 @@ static struct cmm_allocator *get_allocator(struct cmm_object *cmm_mgr_obj, * Purpose: * Create an address translator object. */ -int cmm_xlator_create(OUT struct cmm_xlatorobject **phXlator, +int cmm_xlator_create(struct cmm_xlatorobject **phXlator, struct cmm_object *hcmm_mgr, struct cmm_xlatorattrs *pXlatorAttrs) { @@ -1075,7 +1075,7 @@ int cmm_xlator_free_buf(struct cmm_xlatorobject *xlator, void *pBufVa) * Purpose: * Set/Get translator info. */ -int cmm_xlator_info(struct cmm_xlatorobject *xlator, OUT u8 ** paddr, +int cmm_xlator_info(struct cmm_xlatorobject *xlator, u8 ** paddr, u32 ul_size, u32 uSegId, bool set_info) { struct cmm_xlator *xlator_obj = (struct cmm_xlator *)xlator; diff --git a/drivers/staging/tidspbridge/pmgr/cod.c b/drivers/staging/tidspbridge/pmgr/cod.c index 2aed7a4..0ab12f1 100644 --- a/drivers/staging/tidspbridge/pmgr/cod.c +++ b/drivers/staging/tidspbridge/pmgr/cod.c @@ -216,7 +216,7 @@ void cod_close(struct cod_libraryobj *lib) * dynamically loaded object files. * */ -int cod_create(OUT struct cod_manager **phMgr, char *pstrDummyFile, +int cod_create(struct cod_manager **phMgr, char *pstrDummyFile, const struct cod_attrs *attrs) { struct cod_manager *mgr_new; @@ -398,7 +398,7 @@ int cod_get_loader(struct cod_manager *cod_mgr_obj, * given the section name. */ int cod_get_section(struct cod_libraryobj *lib, char *pstrSect, - OUT u32 *puAddr, OUT u32 *puLen) + u32 *puAddr, u32 *puLen) { struct cod_manager *cod_mgr_obj; int status = 0; @@ -627,7 +627,7 @@ int cod_open_base(struct cod_manager *hmgr, char *pszCoffPath, * Retrieve the content of a code section given the section name. */ int cod_read_section(struct cod_libraryobj *lib, char *pstrSect, - OUT char *pstrContent, u32 content_size) + char *pstrContent, u32 content_size) { int status = 0; diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c index 4e4b20a..d05d366 100644 --- a/drivers/staging/tidspbridge/pmgr/dev.c +++ b/drivers/staging/tidspbridge/pmgr/dev.c @@ -92,7 +92,7 @@ static u32 refs; /* Module reference count */ static int fxn_not_implemented(int arg, ...); static int init_cod_mgr(struct dev_object *dev_obj); static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, - OUT struct bridge_drv_interface *intf_fxns); + struct bridge_drv_interface *intf_fxns); /* * ======== dev_brd_write_fxn ======== * Purpose: @@ -131,7 +131,7 @@ u32 dev_brd_write_fxn(void *pArb, u32 ulDspAddr, void *pHostBuf, * Called by the operating system to load the PM Bridge Driver for a * PM board (device). */ -int dev_create_device(OUT struct dev_object **phDevObject, +int dev_create_device(struct dev_object **phDevObject, const char *driver_file_name, struct cfg_devnode *dev_node_obj) { @@ -260,7 +260,7 @@ int dev_create_device(OUT struct dev_object **phDevObject, } leave: /* If all went well, return a handle to the dev object; - * else, cleanup and return NULL in the OUT parameter. */ + * else, cleanup and return NULL in the parameter. */ if (DSP_SUCCEEDED(status)) { *phDevObject = dev_obj; } else { @@ -420,7 +420,7 @@ int dev_destroy_device(struct dev_object *hdev_obj) * device. */ int dev_get_chnl_mgr(struct dev_object *hdev_obj, - OUT struct chnl_mgr **phMgr) + struct chnl_mgr **phMgr) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -447,7 +447,7 @@ int dev_get_chnl_mgr(struct dev_object *hdev_obj, * device. */ int dev_get_cmm_mgr(struct dev_object *hdev_obj, - OUT struct cmm_object **phMgr) + struct cmm_object **phMgr) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -474,7 +474,7 @@ int dev_get_cmm_mgr(struct dev_object *hdev_obj, * device. */ int dev_get_dmm_mgr(struct dev_object *hdev_obj, - OUT struct dmm_object **phMgr) + struct dmm_object **phMgr) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -500,7 +500,7 @@ int dev_get_dmm_mgr(struct dev_object *hdev_obj, * Retrieve the COD manager create for this device. */ int dev_get_cod_mgr(struct dev_object *hdev_obj, - OUT struct cod_manager **phCodMgr) + struct cod_manager **phCodMgr) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -524,7 +524,7 @@ int dev_get_cod_mgr(struct dev_object *hdev_obj, * ========= dev_get_deh_mgr ======== */ int dev_get_deh_mgr(struct dev_object *hdev_obj, - OUT struct deh_mgr **phDehMgr) + struct deh_mgr **phDehMgr) { int status = 0; @@ -546,7 +546,7 @@ int dev_get_deh_mgr(struct dev_object *hdev_obj, * Retrieve the platform specific device ID for this device. */ int dev_get_dev_node(struct dev_object *hdev_obj, - OUT struct cfg_devnode **phDevNode) + struct cfg_devnode **phDevNode) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -588,7 +588,7 @@ struct dev_object *dev_get_first(void) * ppIntfFxns != NULL. */ int dev_get_intf_fxns(struct dev_object *hdev_obj, - OUT struct bridge_drv_interface **ppIntfFxns) + struct bridge_drv_interface **ppIntfFxns) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -612,7 +612,7 @@ int dev_get_intf_fxns(struct dev_object *hdev_obj, * ========= dev_get_io_mgr ======== */ int dev_get_io_mgr(struct dev_object *hdev_obj, - OUT struct io_mgr **phIOMgr) + struct io_mgr **phIOMgr) { int status = 0; @@ -652,7 +652,7 @@ struct dev_object *dev_get_next(struct dev_object *hdev_obj) /* * ========= dev_get_msg_mgr ======== */ -void dev_get_msg_mgr(struct dev_object *hdev_obj, OUT struct msg_mgr **phMsgMgr) +void dev_get_msg_mgr(struct dev_object *hdev_obj, struct msg_mgr **phMsgMgr) { DBC_REQUIRE(refs > 0); DBC_REQUIRE(phMsgMgr != NULL); @@ -667,7 +667,7 @@ void dev_get_msg_mgr(struct dev_object *hdev_obj, OUT struct msg_mgr **phMsgMgr) * Retrieve the Node Manager Handle */ int dev_get_node_manager(struct dev_object *hdev_obj, - OUT struct node_mgr **phNodeMgr) + struct node_mgr **phNodeMgr) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -691,7 +691,7 @@ int dev_get_node_manager(struct dev_object *hdev_obj, * ======== dev_get_symbol ======== */ int dev_get_symbol(struct dev_object *hdev_obj, - const char *pstrSym, OUT u32 * pul_value) + const char *pstrSym, u32 * pul_value) { int status = 0; struct cod_manager *cod_mgr; @@ -718,7 +718,7 @@ int dev_get_symbol(struct dev_object *hdev_obj, * bridge_dev_create fxn. */ int dev_get_bridge_context(struct dev_object *hdev_obj, - OUT struct bridge_dev_context **phbridge_context) + struct bridge_dev_context **phbridge_context) { int status = 0; struct dev_object *dev_obj = hdev_obj; @@ -974,7 +974,7 @@ static int init_cod_mgr(struct dev_object *dev_obj) * 0 and List is not Empty. */ int dev_insert_proc_object(struct dev_object *hdev_obj, - u32 proc_obj, OUT bool *pbAlreadyAttached) + u32 proc_obj, bool *pbAlreadyAttached) { int status = 0; struct dev_object *dev_obj = (struct dev_object *)hdev_obj; @@ -1069,7 +1069,7 @@ int dev_get_dev_type(struct dev_object *hdevObject, u8 *dev_type) * All function pointers in the dev object's fxn interface are not NULL. */ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns, - OUT struct bridge_drv_interface *intf_fxns) + struct bridge_drv_interface *intf_fxns) { u32 bridge_version; diff --git a/drivers/staging/tidspbridge/pmgr/dmm.c b/drivers/staging/tidspbridge/pmgr/dmm.c index 633e77d..9599753 100644 --- a/drivers/staging/tidspbridge/pmgr/dmm.c +++ b/drivers/staging/tidspbridge/pmgr/dmm.c @@ -117,7 +117,7 @@ int dmm_create_tables(struct dmm_object *dmm_mgr, u32 addr, u32 size) * Purpose: * Create a dynamic memory manager object. */ -int dmm_create(OUT struct dmm_object **phDmmMgr, +int dmm_create(struct dmm_object **phDmmMgr, struct dev_object *hdev_obj, const struct dmm_mgrattrs *pMgrAttrs) { @@ -197,7 +197,7 @@ void dmm_exit(void) * Return the dynamic memory manager object for this device. * This is typically called from the client process. */ -int dmm_get_handle(void *hprocessor, OUT struct dmm_object **phDmmMgr) +int dmm_get_handle(void *hprocessor, struct dmm_object **phDmmMgr) { int status = 0; struct dev_object *hdev_obj; diff --git a/drivers/staging/tidspbridge/pmgr/dspapi.c b/drivers/staging/tidspbridge/pmgr/dspapi.c index 2d43031..bfaf88a 100644 --- a/drivers/staging/tidspbridge/pmgr/dspapi.c +++ b/drivers/staging/tidspbridge/pmgr/dspapi.c @@ -1127,7 +1127,7 @@ u32 nodewrap_alloc_msg_buf(union Trapped_Args *args, void *pr_ctxt) pattr = &attr; } - /* OUT argument */ + /* argument */ CP_FM_USR(&pbuffer, args->args_node_allocmsgbuf.pbuffer, status, 1); if (DSP_SUCCEEDED(status)) { status = node_alloc_msg_buf(args->args_node_allocmsgbuf.hnode, diff --git a/drivers/staging/tidspbridge/pmgr/io.c b/drivers/staging/tidspbridge/pmgr/io.c index e8f006a..b47786f 100644 --- a/drivers/staging/tidspbridge/pmgr/io.c +++ b/drivers/staging/tidspbridge/pmgr/io.c @@ -46,7 +46,7 @@ static u32 refs; * Create an IO manager object, responsible for managing IO between * CHNL and msg_ctrl */ -int io_create(OUT struct io_mgr **phIOMgr, struct dev_object *hdev_obj, +int io_create(struct io_mgr **phIOMgr, struct dev_object *hdev_obj, const struct io_attrs *pMgrAttrs) { struct bridge_drv_interface *intf_fxns; diff --git a/drivers/staging/tidspbridge/pmgr/msg.c b/drivers/staging/tidspbridge/pmgr/msg.c index 7dec2ab..3e2937c 100644 --- a/drivers/staging/tidspbridge/pmgr/msg.c +++ b/drivers/staging/tidspbridge/pmgr/msg.c @@ -45,7 +45,7 @@ static u32 refs; /* module reference count */ * Create an object to manage message queues. Only one of these objects * can exist per device object. */ -int msg_create(OUT struct msg_mgr **phMsgMgr, +int msg_create(struct msg_mgr **phMsgMgr, struct dev_object *hdev_obj, msg_onexit msgCallback) { struct bridge_drv_interface *intf_fxns; diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 81b91b8..026a6f6 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -69,10 +69,10 @@ static void compress_buf(char *psz_buf, u32 ul_buf_size, s32 char_size); static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size); static int get_dep_lib_info(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, - OUT u16 *pNumLibs, - OUT u16 *pNumPersLibs, - OUT struct dsp_uuid *pDepLibUuids, - OUT bool *pPersistentDepLibs, + u16 *pNumLibs, + u16 *pNumPersLibs, + struct dsp_uuid *pDepLibUuids, + bool *pPersistentDepLibs, enum nldr_phase phase); /* @@ -125,7 +125,7 @@ int dcd_auto_unregister(struct dcd_manager *hdcd_mgr, * Creates DCD manager. */ int dcd_create_manager(char *pszZlDllName, - OUT struct dcd_manager **phDcdMgr) + struct dcd_manager **phDcdMgr) { struct cod_manager *cod_mgr; /* COD manager handle */ struct dcd_manager *dcd_mgr_obj = NULL; /* DCD Manager pointer */ @@ -194,7 +194,7 @@ int dcd_destroy_manager(struct dcd_manager *hdcd_mgr) * Enumerates objects in the DCD. */ int dcd_enumerate_object(s32 index, enum dsp_dcdobjtype obj_type, - OUT struct dsp_uuid *uuid_obj) + struct dsp_uuid *uuid_obj) { int status = 0; char sz_reg_key[DCD_MAXPATHLENGTH]; @@ -327,8 +327,8 @@ void dcd_exit(void) */ int dcd_get_dep_libs(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, - u16 numLibs, OUT struct dsp_uuid *pDepLibUuids, - OUT bool *pPersistentDepLibs, + u16 numLibs, struct dsp_uuid *pDepLibUuids, + bool *pPersistentDepLibs, enum nldr_phase phase) { int status = 0; @@ -351,7 +351,7 @@ int dcd_get_dep_libs(struct dcd_manager *hdcd_mgr, */ int dcd_get_num_dep_libs(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, - OUT u16 *pNumLibs, OUT u16 *pNumPersLibs, + u16 *pNumLibs, u16 *pNumPersLibs, enum nldr_phase phase) { int status = 0; @@ -377,7 +377,7 @@ int dcd_get_num_dep_libs(struct dcd_manager *hdcd_mgr, int dcd_get_object_def(struct dcd_manager *hdcd_mgr, struct dsp_uuid *pObjUuid, enum dsp_dcdobjtype obj_type, - OUT struct dcd_genericobj *pObjDef) + struct dcd_genericobj *pObjDef) { struct dcd_manager *dcd_mgr_obj = hdcd_mgr; /* ptr to DCD mgr */ struct cod_libraryobj *lib = NULL; @@ -644,8 +644,8 @@ func_end: */ int dcd_get_library_name(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, - OUT char *pstrLibName, OUT u32 * pdwSize, - enum nldr_phase phase, OUT bool *phase_split) + char *pstrLibName, u32 * pdwSize, + enum nldr_phase phase, bool *phase_split) { char sz_reg_key[DCD_MAXPATHLENGTH]; char sz_uuid[MAXUUIDLEN]; @@ -1391,10 +1391,10 @@ static char dsp_char2_gpp_char(char *pWord, s32 dsp_char_size) */ static int get_dep_lib_info(struct dcd_manager *hdcd_mgr, struct dsp_uuid *uuid_obj, - OUT u16 *pNumLibs, - OUT u16 *pNumPersLibs, - OUT struct dsp_uuid *pDepLibUuids, - OUT bool *pPersistentDepLibs, + u16 *pNumLibs, + u16 *pNumPersLibs, + struct dsp_uuid *pDepLibUuids, + bool *pPersistentDepLibs, enum nldr_phase phase) { struct dcd_manager *dcd_mgr_obj = hdcd_mgr; diff --git a/drivers/staging/tidspbridge/rmgr/disp.c b/drivers/staging/tidspbridge/rmgr/disp.c index cb50077..bbd0d06 100644 --- a/drivers/staging/tidspbridge/rmgr/disp.c +++ b/drivers/staging/tidspbridge/rmgr/disp.c @@ -81,13 +81,13 @@ static int fill_stream_def(rms_word *pdw_buf, u32 *ptotal, u32 offset, struct node_strmdef strm_def, u32 max, u32 chars_in_rms_word); static int send_message(struct disp_object *disp_obj, u32 dwTimeout, - u32 ul_bytes, OUT u32 *pdw_arg); + u32 ul_bytes, u32 *pdw_arg); /* * ======== disp_create ======== * Create a NODE Dispatcher object. */ -int disp_create(OUT struct disp_object **phDispObject, +int disp_create(struct disp_object **phDispObject, struct dev_object *hdev_obj, const struct disp_attr *pDispAttrs) { @@ -252,7 +252,7 @@ int disp_node_create(struct disp_object *disp_obj, struct node_object *hnode, u32 ulRMSFxn, u32 ul_create_fxn, const struct node_createargs *pargs, - OUT nodeenv *pNodeEnv) + nodeenv *pNodeEnv) { struct node_msgargs node_msg_args; struct node_taskargs task_arg_obj; diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 112ac87..2777c43 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -421,7 +421,7 @@ int drv_proc_update_strm_res(u32 num_bufs, void *hstrm_res) * Purpose: * DRV Object gets created only once during Driver Loading. */ -int drv_create(OUT struct drv_object **phDRVObject) +int drv_create(struct drv_object **phDRVObject) { int status = 0; struct drv_object *pdrv_object = NULL; @@ -968,7 +968,7 @@ void mem_ext_phys_pool_release(void) * Allocate physically contiguous, uncached memory from external memory pool */ -static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * pPhysAddr) +static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, u32 * pPhysAddr) { u32 new_alloc_ptr; u32 offset; @@ -1011,7 +1011,7 @@ static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, OUT u32 * pPhysAddr) * Purpose: * Allocate physically contiguous, uncached memory */ -void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, OUT u32 * pPhysicalAddress) +void *mem_alloc_phys_mem(u32 byte_size, u32 ulAlign, u32 * pPhysicalAddress) { void *va_mem = NULL; dma_addr_t pa_mem; diff --git a/drivers/staging/tidspbridge/rmgr/dspdrv.c b/drivers/staging/tidspbridge/rmgr/dspdrv.c index 2fddbbb..5658cbc 100644 --- a/drivers/staging/tidspbridge/rmgr/dspdrv.c +++ b/drivers/staging/tidspbridge/rmgr/dspdrv.c @@ -44,7 +44,7 @@ * ======== dsp_init ======== * Allocates bridge resources. Loads a base image onto DSP, if specified. */ -u32 dsp_init(OUT u32 *init_status) +u32 dsp_init(u32 *init_status) { char dev_node[MAXREGPATHLENGTH] = "TIOMAP1510"; int status = -EPERM; diff --git a/drivers/staging/tidspbridge/rmgr/mgr.c b/drivers/staging/tidspbridge/rmgr/mgr.c index a7bc93b..1f8b929 100644 --- a/drivers/staging/tidspbridge/rmgr/mgr.c +++ b/drivers/staging/tidspbridge/rmgr/mgr.c @@ -53,7 +53,7 @@ static u32 refs; * Purpose: * MGR Object gets created only once during driver Loading. */ -int mgr_create(OUT struct mgr_object **phMgrObject, +int mgr_create(struct mgr_object **phMgrObject, struct cfg_devnode *dev_node_obj) { int status = 0; @@ -114,8 +114,8 @@ int mgr_destroy(struct mgr_object *hmgr_obj) * Enumerate and get configuration information about nodes configured * in the node database. */ -int mgr_enum_node_info(u32 node_id, OUT struct dsp_ndbprops *pndb_props, - u32 undb_props_size, OUT u32 *pu_num_nodes) +int mgr_enum_node_info(u32 node_id, struct dsp_ndbprops *pndb_props, + u32 undb_props_size, u32 *pu_num_nodes) { int status = 0; struct dsp_uuid node_uuid, temp_uuid; @@ -178,9 +178,9 @@ func_cont: * DSP processors. */ int mgr_enum_processor_info(u32 processor_id, - OUT struct dsp_processorinfo * + struct dsp_processorinfo * processor_info, u32 processor_info_size, - OUT u8 *pu_num_procs) + u8 *pu_num_procs) { int status = 0; int status1 = 0; @@ -305,7 +305,7 @@ void mgr_exit(void) * Retrieves the MGR handle. Accessor Function. */ int mgr_get_dcd_handle(struct mgr_object *hMGRHandle, - OUT u32 *phDCDHandle) + u32 *phDCDHandle) { int status = -EPERM; struct mgr_object *pmgr_obj = (struct mgr_object *)hMGRHandle; @@ -355,7 +355,7 @@ bool mgr_init(void) * Block on any Bridge event(s) */ int mgr_wait_for_bridge_events(struct dsp_notification **anotifications, - u32 count, OUT u32 *pu_index, + u32 count, u32 *pu_index, u32 utimeout) { int status; diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index aaaab67..8667216 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -325,7 +325,7 @@ static u32 find_gcf(u32 a, u32 b); */ int nldr_allocate(struct nldr_object *nldr_obj, void *priv_ref, const struct dcd_nodeprops *node_props, - OUT struct nldr_nodeobject **phNldrNode, + struct nldr_nodeobject **phNldrNode, bool *pf_phase_split) { struct nldr_nodeobject *nldr_node_obj = NULL; @@ -424,7 +424,7 @@ int nldr_allocate(struct nldr_object *nldr_obj, void *priv_ref, /* * ======== nldr_create ======== */ -int nldr_create(OUT struct nldr_object **phNldr, +int nldr_create(struct nldr_object **phNldr, struct dev_object *hdev_obj, const struct nldr_attrs *pattrs) { @@ -775,7 +775,7 @@ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, * Given a NLDR object, retrieve RMM Manager Handle */ int nldr_get_rmm_manager(struct nldr_object *hNldrObject, - OUT struct rmm_target_obj **phRmmMgr) + struct rmm_target_obj **phRmmMgr) { int status = 0; struct nldr_object *nldr_obj = hNldrObject; diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 1f975c6..6d24baf 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -294,7 +294,7 @@ int node_allocate(struct proc_object *hprocessor, const struct dsp_uuid *pNodeId, const struct dsp_cbdata *pargs, const struct dsp_nodeattrin *attr_in, - OUT struct node_object **ph_node, + struct node_object **ph_node, struct process_context *pr_ctxt) { struct node_mgr *hnode_mgr; @@ -685,8 +685,8 @@ func_end: * Allocates buffer for zero copy messaging. */ DBAPI node_alloc_msg_buf(struct node_object *hnode, u32 usize, - OUT struct dsp_bufferattr *pattr, - OUT u8 **pbuffer) + struct dsp_bufferattr *pattr, + u8 **pbuffer) { struct node_object *pnode = (struct node_object *)hnode; int status = 0; @@ -1300,7 +1300,7 @@ func_end: * Purpose: * Create a NODE Manager object. */ -int node_create_mgr(OUT struct node_mgr **phNodeMgr, +int node_create_mgr(struct node_mgr **phNodeMgr, struct dev_object *hdev_obj) { u32 i; @@ -1613,8 +1613,8 @@ int node_delete_mgr(struct node_mgr *hnode_mgr) * Enumerate currently allocated nodes. */ int node_enum_nodes(struct node_mgr *hnode_mgr, void **node_tab, - u32 node_tab_size, OUT u32 *pu_num_nodes, - OUT u32 *pu_allocated) + u32 node_tab_size, u32 *pu_num_nodes, + u32 *pu_allocated) { struct node_object *hnode; u32 i; @@ -1716,7 +1716,7 @@ func_end: * structure. */ int node_get_attr(struct node_object *hnode, - OUT struct dsp_nodeattr *pattr, u32 attr_size) + struct dsp_nodeattr *pattr, u32 attr_size) { struct node_mgr *hnode_mgr; int status = 0; @@ -1760,7 +1760,7 @@ int node_get_attr(struct node_object *hnode, * host and a node. */ int node_get_channel_id(struct node_object *hnode, u32 dir, u32 index, - OUT u32 *pulId) + u32 *pulId) { enum node_type node_type; int status = -EINVAL; @@ -1802,7 +1802,7 @@ int node_get_channel_id(struct node_object *hnode, u32 dir, u32 index, * Retrieve a message from a node on the DSP. */ int node_get_message(struct node_object *hnode, - OUT struct dsp_msg *pmsg, u32 utimeout) + struct dsp_msg *pmsg, u32 utimeout) { struct node_mgr *hnode_mgr; enum node_type node_type; @@ -2365,7 +2365,7 @@ func_end: * Signal a node running on the DSP that it should exit its execute phase * function. */ -int node_terminate(struct node_object *hnode, OUT int *pstatus) +int node_terminate(struct node_object *hnode, int *pstatus) { struct node_object *pnode = (struct node_object *)hnode; struct node_mgr *hnode_mgr = NULL; @@ -3005,7 +3005,7 @@ static int get_proc_props(struct node_mgr *hnode_mgr, */ int node_get_uuid_props(void *hprocessor, const struct dsp_uuid *pNodeId, - OUT struct dsp_ndbprops *node_props) + struct dsp_ndbprops *node_props) { struct node_mgr *hnode_mgr = NULL; struct dev_object *hdev_obj; diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c index 1f450fe..14de79a 100644 --- a/drivers/staging/tidspbridge/rmgr/proc.c +++ b/drivers/staging/tidspbridge/rmgr/proc.c @@ -582,8 +582,8 @@ int proc_detach(struct process_context *pr_ctxt) * on a DSP processor. */ int proc_enum_nodes(void *hprocessor, void **node_tab, - u32 node_tab_size, OUT u32 *pu_num_nodes, - OUT u32 *pu_allocated) + u32 node_tab_size, u32 *pu_num_nodes, + u32 *pu_allocated) { int status = -EPERM; struct proc_object *p_proc_object = (struct proc_object *)hprocessor; @@ -849,7 +849,7 @@ int proc_invalidate_memory(void *hprocessor, void *pmpu_addr, u32 size) * Enumerate the resources currently available on a processor. */ int proc_get_resource_info(void *hprocessor, u32 resource_type, - OUT struct dsp_resourceinfo *resource_info, + struct dsp_resourceinfo *resource_info, u32 resource_info_size) { int status = -EPERM; @@ -964,7 +964,7 @@ int proc_get_dev_object(void *hprocessor, * Report the state of the specified DSP processor. */ int proc_get_state(void *hprocessor, - OUT struct dsp_processorstate *proc_state_obj, + struct dsp_processorstate *proc_state_obj, u32 state_info_size) { int status = 0; diff --git a/drivers/staging/tidspbridge/rmgr/strm.c b/drivers/staging/tidspbridge/rmgr/strm.c index 46149da..6dfb6fe 100644 --- a/drivers/staging/tidspbridge/rmgr/strm.c +++ b/drivers/staging/tidspbridge/rmgr/strm.c @@ -98,7 +98,7 @@ static void delete_strm_mgr(struct strm_mgr *strm_mgr_obj); * Allocates buffers for a stream. */ int strm_allocate_buffer(struct strm_object *hStrm, u32 usize, - OUT u8 **ap_buffer, u32 num_bufs, + u8 **ap_buffer, u32 num_bufs, struct process_context *pr_ctxt) { int status = 0; @@ -200,7 +200,7 @@ func_end: * Purpose: * Create a STRM manager object. */ -int strm_create(OUT struct strm_mgr **phStrmMgr, +int strm_create(struct strm_mgr **phStrmMgr, struct dev_object *dev_obj) { struct strm_mgr *strm_mgr_obj; @@ -308,7 +308,7 @@ int strm_free_buffer(struct strm_object *hStrm, u8 ** ap_buffer, * Retrieves information about a stream. */ int strm_get_info(struct strm_object *hStrm, - OUT struct stream_info *stream_info, + struct stream_info *stream_info, u32 stream_info_size) { struct bridge_drv_interface *intf_fxns; @@ -465,7 +465,7 @@ int strm_issue(struct strm_object *hStrm, u8 *pbuf, u32 ul_bytes, */ int strm_open(struct node_object *hnode, u32 dir, u32 index, struct strm_attr *pattr, - OUT struct strm_object **phStrm, + struct strm_object **phStrm, struct process_context *pr_ctxt) { struct strm_mgr *strm_mgr_obj; @@ -615,7 +615,7 @@ func_cont: * Purpose: * Relcaims a buffer from a stream. */ -int strm_reclaim(struct strm_object *hStrm, OUT u8 ** buf_ptr, +int strm_reclaim(struct strm_object *hStrm, u8 ** buf_ptr, u32 *pulBytes, u32 *pulBufSize, u32 *pdw_arg) { struct bridge_drv_interface *intf_fxns; @@ -739,7 +739,7 @@ int strm_register_notify(struct strm_object *hStrm, u32 event_mask, * Selects a ready stream. */ int strm_select(struct strm_object **strm_tab, u32 nStrms, - OUT u32 *pmask, u32 utimeout) + u32 *pmask, u32 utimeout) { u32 index; struct chnl_info chnl_info_obj; diff --git a/drivers/staging/tidspbridge/services/cfg.c b/drivers/staging/tidspbridge/services/cfg.c index 699792c..95a2087 100644 --- a/drivers/staging/tidspbridge/services/cfg.c +++ b/drivers/staging/tidspbridge/services/cfg.c @@ -51,7 +51,7 @@ void cfg_exit(void) * Retreive the autostart mask, if any, for this board. */ int cfg_get_auto_start(struct cfg_devnode *dev_node_obj, - OUT u32 *pdwAutoStart) + u32 *pdwAutoStart) { int status = 0; u32 dw_buf_size; @@ -77,7 +77,7 @@ int cfg_get_auto_start(struct cfg_devnode *dev_node_obj, * Retrieve the Device Object handle for a given devnode. */ int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, - OUT u32 *pdwValue) + u32 *pdwValue) { int status = 0; u32 dw_buf_size; @@ -113,7 +113,7 @@ int cfg_get_dev_object(struct cfg_devnode *dev_node_obj, * Retreive the default executable, if any, for this board. */ int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, - OUT char *pstrExecFile) + char *pstrExecFile) { int status = 0; struct drv_data *drv_datap = dev_get_drvdata(bridge); @@ -143,7 +143,7 @@ int cfg_get_exec_file(struct cfg_devnode *dev_node_obj, u32 ul_buf_size, * Purpose: * Retrieve the Object handle from the Registry */ -int cfg_get_object(OUT u32 *pdwValue, u8 dw_type) +int cfg_get_object(u32 *pdwValue, u8 dw_type) { int status = -EINVAL; struct drv_data *drv_datap = dev_get_drvdata(bridge); From patchwork Mon Jul 12 22:56:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 111566 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6CMxxMg016827 for ; Mon, 12 Jul 2010 23:00:01 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756087Ab0GLW4n (ORCPT ); Mon, 12 Jul 2010 18:56:43 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:56970 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755939Ab0GLW4X (ORCPT ); Mon, 12 Jul 2010 18:56:23 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuEI3012341 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Jul 2010 17:56:14 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o6CMuDBf016489; Mon, 12 Jul 2010 17:56:13 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o6CMuDP07276; Mon, 12 Jul 2010 17:56:13 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 560F6C25F; Mon, 12 Jul 2010 17:56:10 -0500 (CDT) From: Nishanth Menon To: Greg Kroah-Hartman Cc: Omar Ramirez Luna , Ohad Ben-Cohen , Ameya Palande , Fernando Guzman Lugo , Felipe Contreras , Andy Shevchenko , lkml , linux-omap , Nishanth Menon Subject: [PATCH 02/11] staging: tidspbridge: no need for custom NULL Date: Mon, 12 Jul 2010 17:56:00 -0500 Message-Id: <1278975369-7687-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1278975369-7687-1-git-send-email-nm@ti.com> References: <1278975369-7687-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Jul 2010 23:00:01 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/dynload/header.h b/drivers/staging/tidspbridge/dynload/header.h index 04623f1..5b50a15 100644 --- a/drivers/staging/tidspbridge/dynload/header.h +++ b/drivers/staging/tidspbridge/dynload/header.h @@ -14,10 +14,6 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ -#ifndef NULL -#define NULL 0 -#endif - #include #define DL_STRCMP strcmp diff --git a/drivers/staging/tidspbridge/hw/GlobalTypes.h b/drivers/staging/tidspbridge/hw/GlobalTypes.h index ba045eb..2f8e69b 100644 --- a/drivers/staging/tidspbridge/hw/GlobalTypes.h +++ b/drivers/staging/tidspbridge/hw/GlobalTypes.h @@ -20,15 +20,6 @@ #define _GLOBALTYPES_H /* - * Definition: NULL - * - * DESCRIPTION: Invalid pointer - */ -#ifndef NULL -#define NULL (void *)0 -#endif - -/* * Definition: RET_CODE_BASE * * DESCRIPTION: Base value for return code offsets diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbtype.h b/drivers/staging/tidspbridge/include/dspbridge/dbtype.h index 0b2cb93..ca5eaf8 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/dbtype.h +++ b/drivers/staging/tidspbridge/include/dspbridge/dbtype.h @@ -42,14 +42,6 @@ #endif /*===========================================================================*/ -/* NULL (Definition is language specific) */ -/*===========================================================================*/ - -#ifndef NULL -#define NULL ((void *)0) /* Null pointer. */ -#endif - -/*===========================================================================*/ /* NULL character (normally used for string termination) */ /*===========================================================================*/ diff --git a/drivers/staging/tidspbridge/include/dspbridge/std.h b/drivers/staging/tidspbridge/include/dspbridge/std.h index 7e09fec..ca2827d 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/std.h +++ b/drivers/staging/tidspbridge/include/dspbridge/std.h @@ -74,10 +74,6 @@ typedef s32(*fxn) (void); /* generic function type */ -#ifndef NULL -#define NULL 0 -#endif - /* * These macros are used to cast 'Arg' types to 's32' or 'Ptr'. * These macros were added for the 55x since Arg is not the same From patchwork Fri May 7 09:07:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 97653 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4797P5Y009537 for ; Fri, 7 May 2010 09:07:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753536Ab0EGJHa (ORCPT ); Fri, 7 May 2010 05:07:30 -0400 Received: from mail.gmx.net ([213.165.64.20]:54960 "HELO mail.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1753398Ab0EGJH3 (ORCPT ); Fri, 7 May 2010 05:07:29 -0400 Received: (qmail invoked by alias); 07 May 2010 09:07:27 -0000 Received: from p57BD1BFA.dip0.t-ipconnect.de (EHLO axis700.grange) [87.189.27.250] by mail.gmx.net (mp018) with SMTP; 07 May 2010 11:07:27 +0200 X-Authenticated: #20450766 X-Provags-ID: V01U2FsdGVkX1+JtFEAuhuJwFPyCUtJtgZsBRVV591UEfuNMeeSbo 858o2ieANtMDyo Received: from lyakh (helo=localhost) by axis700.grange with local-esmtp (Exim 4.63) (envelope-from ) id 1OAJWp-0001a2-Hw; Fri, 07 May 2010 11:07:27 +0200 Date: Fri, 7 May 2010 11:07:27 +0200 (CEST) From: Guennadi Liakhovetski To: "linux-sh@vger.kernel.org" cc: Magnus Damm , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, Tomi Valkeinen Subject: [PATCH 3/4] ARM: add framebuffer support for ap4evb In-Reply-To: Message-ID: References: MIME-Version: 1.0 X-Y-GMX-Trusted: 0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 07 May 2010 09:07:42 +0000 (UTC) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 9003ea9..e216132 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -42,6 +42,7 @@ config MACH_AP4EVB bool "AP4EVB board" depends on ARCH_SH7372 select ARCH_REQUIRE_GPIOLIB + select SH_LCD_MIPI_DSI comment "SH-Mobile System Configuration" diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index d2bb7b0..e3f5375 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -17,6 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -32,8 +33,14 @@ #include #include #include + +#include