diff mbox

[v4,2/5] ARM: tegra: Add legacy interrupt controller nodes

Message ID 1409239879-12376-2-git-send-email-thierry.reding@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Thierry Reding Aug. 28, 2014, 3:31 p.m. UTC 
From: Thierry Reding <treding@nvidia.com>

Add device tree nodes for the legacy interrupt controller so that the
driver can get the register ranges from device tree rather than hard-
coding them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- bracket individual tuples in the "reg" property

Changes in v2:
- add chip-specific compatible string
- drop quinary controller on Tegra20

 arch/arm/boot/dts/tegra114.dtsi | 9 +++++++++
 arch/arm/boot/dts/tegra124.dtsi | 9 +++++++++
 arch/arm/boot/dts/tegra20.dtsi  | 8 ++++++++
 arch/arm/boot/dts/tegra30.dtsi  | 9 +++++++++
 4 files changed, 35 insertions(+)

Comments

Arnd Bergmann Aug. 28, 2014, 4:11 p.m. UTC | #1 
On Thursday 28 August 2014 17:31:16 Thierry Reding wrote:
> +       interrupt-controller@60004000 {
> +               compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
> +               reg = <0x60004000 0x40>, /* primary controller */
> +                     <0x60004100 0x40>, /* secondary controller */
> +                     <0x60004200 0x40>, /* tertiary controller */
> +                     <0x60004300 0x40>, /* quaternary controller */
> +                     <0x60004400 0x40>; /* quinary controller */
> +       };
> +
>         timer@60005000 {
>                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
> 

Don't you need an interrupt-parent and interrupts property here to point to
the GIC interrupts? I would assume this is a nested irqchip.

	Arnd
Peter De Schrijver Sept. 1, 2014, 8:16 a.m. UTC | #2 
On Thu, Aug 28, 2014 at 06:11:53PM +0200, Arnd Bergmann wrote:
> On Thursday 28 August 2014 17:31:16 Thierry Reding wrote:
> > +       interrupt-controller@60004000 {
> > +               compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
> > +               reg = <0x60004000 0x40>, /* primary controller */
> > +                     <0x60004100 0x40>, /* secondary controller */
> > +                     <0x60004200 0x40>, /* tertiary controller */
> > +                     <0x60004300 0x40>, /* quaternary controller */
> > +                     <0x60004400 0x40>; /* quinary controller */
> > +       };
> > +
> >         timer@60005000 {
> >                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
> > 
> 
> Don't you need an interrupt-parent and interrupts property here to point to
> the GIC interrupts? I would assume this is a nested irqchip.

No. It's not nested. All SoC interrupts are fed into both the LIC and the
GIC (as SPIs). The LIC also has an interface towards the flowcontroller which
allows waking up the CPU when an interrupt happens, even if the GIC is off. 
LIC can also route every interrupt it controls to the AVP.

See also section 3.4.1.4 Interrupt routing of the TRM.

Cheers,

Peter.
diff mbox

Patch

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index a147fa2bfdd2..9bfab8bb765a 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -141,6 +141,15 @@ 
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	interrupt-controller@60004000 {
+		compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>, /* quaternary controller */
+		      <0x60004400 0x40>; /* quinary controller */
+	};
+
 	timer@60005000 {
 		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 82dc48b530e6..8c7523225fd9 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -190,6 +190,15 @@ 
 		status = "disabled";
 	};
 
+	interrupt-controller@0,60004000 {
+		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
+		reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
+		      <0x0 0x60004100 0x0 0x40>, /* secondary controller */
+		      <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
+		      <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
+		      <0x0 0x60004400 0x0 0x40>; /* quinary controller */
+	};
+
 	timer@0,60005000 {
 		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 		reg = <0x0 0x60005000 0x0 0x400>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c6a2d078bdf4..fe2f57d19438 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -183,6 +183,14 @@ 
 		cache-level = <2>;
 	};
 
+	interrupt-controller@60004000 {
+		compatible = "nvidia,tegra20-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>; /* quaternary controller */
+	};
+
 	timer@60005000 {
 		compatible = "nvidia,tegra20-timer";
 		reg = <0x60005000 0x60>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index f4693c9c070e..e5da2d252220 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -262,6 +262,15 @@ 
 		cache-level = <2>;
 	};
 
+	interrupt-controller@60004000 {
+		compatible = "nvidia,tegra30-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>, /* quaternary controller */
+		      <0x60004400 0x40>; /* quinary controller */
+	};
+
 	timer@60005000 {
 		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;