| Message ID | 1409665033-3935-1-git-send-email-jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 02 Sep 2014, Jani Nikula <jani.nikula@intel.com> wrote: > How about throwing this at any eDP link parameter bugs and regressions? > Does it feel too much like giving up the battle? Fixes at least one bug... https://bugs.freedesktop.org/show_bug.cgi?id=79386#c15 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 24 +++++++----------------- > 1 file changed, 7 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index d7fc2c0e9ba8..f4248d7f64f9 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -889,23 +889,13 @@ intel_dp_compute_config(struct intel_encoder *encoder, > bpp = dev_priv->vbt.edp_bpp; > } > > - if (IS_BROADWELL(dev)) { > - /* Yes, it's an ugly hack. */ > - min_lane_count = max_lane_count; > - DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", > - min_lane_count); > - } else if (dev_priv->vbt.edp_lanes) { > - min_lane_count = min(dev_priv->vbt.edp_lanes, > - max_lane_count); > - DRM_DEBUG_KMS("using min %u lanes per VBT\n", > - min_lane_count); > - } > - > - if (dev_priv->vbt.edp_rate) { > - min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); > - DRM_DEBUG_KMS("using min %02x link bw per VBT\n", > - bws[min_clock]); > - } > + /* > + * Use the maximum clock and number of lanes the eDP panel > + * advertizes being capable of. Typically these values > + * correspond to the native resolution of the panel. > + */ > + min_lane_count = max_lane_count; > + min_clock = max_clock; > } > > for (; bpp >= 6*3; bpp -= 2*3) { > -- > 1.9.1 >
On Tue, 02 Sep 2014, Jani Nikula <jani.nikula@intel.com> wrote: > On Tue, 02 Sep 2014, Jani Nikula <jani.nikula@intel.com> wrote: >> How about throwing this at any eDP link parameter bugs and regressions? >> Does it feel too much like giving up the battle? > > Fixes at least one bug... > > https://bugs.freedesktop.org/show_bug.cgi?id=79386#c15 Another https://bugs.freedesktop.org/show_bug.cgi?id=81647#c6 > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/intel_dp.c | 24 +++++++----------------- >> 1 file changed, 7 insertions(+), 17 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index d7fc2c0e9ba8..f4248d7f64f9 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -889,23 +889,13 @@ intel_dp_compute_config(struct intel_encoder *encoder, >> bpp = dev_priv->vbt.edp_bpp; >> } >> >> - if (IS_BROADWELL(dev)) { >> - /* Yes, it's an ugly hack. */ >> - min_lane_count = max_lane_count; >> - DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", >> - min_lane_count); >> - } else if (dev_priv->vbt.edp_lanes) { >> - min_lane_count = min(dev_priv->vbt.edp_lanes, >> - max_lane_count); >> - DRM_DEBUG_KMS("using min %u lanes per VBT\n", >> - min_lane_count); >> - } >> - >> - if (dev_priv->vbt.edp_rate) { >> - min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); >> - DRM_DEBUG_KMS("using min %02x link bw per VBT\n", >> - bws[min_clock]); >> - } >> + /* >> + * Use the maximum clock and number of lanes the eDP panel >> + * advertizes being capable of. Typically these values >> + * correspond to the native resolution of the panel. >> + */ >> + min_lane_count = max_lane_count; >> + min_clock = max_clock; >> } >> >> for (; bpp >= 6*3; bpp -= 2*3) { >> -- >> 1.9.1 >> > > -- > Jani Nikula, Intel Open Source Technology Center
On Thu, 04 Sep 2014 10:53:44 +0300 Jani Nikula <jani.nikula@intel.com> wrote: > On Tue, 02 Sep 2014, Jani Nikula <jani.nikula@intel.com> wrote: > > On Tue, 02 Sep 2014, Jani Nikula <jani.nikula@intel.com> wrote: > >> How about throwing this at any eDP link parameter bugs and > >> regressions? Does it feel too much like giving up the battle? > > > > Fixes at least one bug... > > > > https://bugs.freedesktop.org/show_bug.cgi?id=79386#c15 > > Another > > https://bugs.freedesktop.org/show_bug.cgi?id=81647#c6 > > > > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > >> --- > >> drivers/gpu/drm/i915/intel_dp.c | 24 +++++++----------------- > >> 1 file changed, 7 insertions(+), 17 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_dp.c > >> b/drivers/gpu/drm/i915/intel_dp.c index d7fc2c0e9ba8..f4248d7f64f9 > >> 100644 --- a/drivers/gpu/drm/i915/intel_dp.c > >> +++ b/drivers/gpu/drm/i915/intel_dp.c > >> @@ -889,23 +889,13 @@ intel_dp_compute_config(struct intel_encoder > >> *encoder, bpp = dev_priv->vbt.edp_bpp; > >> } > >> > >> - if (IS_BROADWELL(dev)) { > >> - /* Yes, it's an ugly hack. */ > >> - min_lane_count = max_lane_count; > >> - DRM_DEBUG_KMS("forcing lane count to max > >> (%u) on BDW\n", > >> - min_lane_count); > >> - } else if (dev_priv->vbt.edp_lanes) { > >> - min_lane_count = > >> min(dev_priv->vbt.edp_lanes, > >> - max_lane_count); > >> - DRM_DEBUG_KMS("using min %u lanes per > >> VBT\n", > >> - min_lane_count); > >> - } > >> - > >> - if (dev_priv->vbt.edp_rate) { > >> - min_clock = min(dev_priv->vbt.edp_rate >> > >> 3, max_clock); > >> - DRM_DEBUG_KMS("using min %02x link bw per > >> VBT\n", > >> - bws[min_clock]); > >> - } > >> + /* > >> + * Use the maximum clock and number of lanes the > >> eDP panel > >> + * advertizes being capable of. Typically these > >> values > >> + * correspond to the native resolution of the > >> panel. > >> + */ > >> + min_lane_count = max_lane_count; > >> + min_clock = max_clock; > >> } > >> > >> for (; bpp >= 6*3; bpp -= 2*3) { > >> -- > >> 1.9.1 > >> > > > > -- > > Jani Nikula, Intel Open Source Technology Center > Then I'd say let's go for it. We can always whitelist systems where we can use fewer lanes (e.g. some Chromebooks). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
On Thu, 11 Sep 2014, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > Then I'd say let's go for it. We can always whitelist systems where we > can use fewer lanes (e.g. some Chromebooks). > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> You're late to the party! ;) commit 39fde1cdcc5df26bd65a2b9b765ae5b741ca6d13 Author: Jani Nikula <jani.nikula@intel.com> Date: Tue Sep 9 11:25:13 2014 +0300 drm/i915/edp: use lane count and link rate from DPCD for eDP
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index d7fc2c0e9ba8..f4248d7f64f9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -889,23 +889,13 @@ intel_dp_compute_config(struct intel_encoder *encoder, bpp = dev_priv->vbt.edp_bpp; } - if (IS_BROADWELL(dev)) { - /* Yes, it's an ugly hack. */ - min_lane_count = max_lane_count; - DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", - min_lane_count); - } else if (dev_priv->vbt.edp_lanes) { - min_lane_count = min(dev_priv->vbt.edp_lanes, - max_lane_count); - DRM_DEBUG_KMS("using min %u lanes per VBT\n", - min_lane_count); - } - - if (dev_priv->vbt.edp_rate) { - min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); - DRM_DEBUG_KMS("using min %02x link bw per VBT\n", - bws[min_clock]); - } + /* + * Use the maximum clock and number of lanes the eDP panel + * advertizes being capable of. Typically these values + * correspond to the native resolution of the panel. + */ + min_lane_count = max_lane_count; + min_clock = max_clock; } for (; bpp >= 6*3; bpp -= 2*3) {
How about throwing this at any eDP link parameter bugs and regressions? Does it feel too much like giving up the battle? Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-)