diff mbox

[v3,6/8] phy: miphy28lp: Add SSC support for PCIE

Message ID 1411721657-9924-7-git-send-email-gabriel.fernandez@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Gabriel FERNANDEZ Sept. 26, 2014, 8:54 a.m. UTC 
SSC is the technique of modulating the operating frequency of a signal
slightly to spread its radiated emissions over a range of frequencies.
This reduction in the maximum emission for a given frequency helps meet
radiated emission requirements.
These settings are applicable for PCIE with Internal clock.

Signed-off-by: Harsh Gupta <harsh.gupta@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
 drivers/phy/phy-miphy28lp.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

Comments

Valdis Klētnieks Sept. 29, 2014, 7:19 p.m. UTC | #1 
On Fri, 26 Sep 2014 10:54:15 +0200, Gabriel FERNANDEZ said:
> SSC is the technique of modulating the operating frequency of a signal
> slightly to spread its radiated emissions over a range of frequencies.
> This reduction in the maximum emission for a given frequency helps meet
> radiated emission requirements.
> These settings are applicable for PCIE with Internal clock.

> +		writeb_relaxed(0x69, miphy_phy->base + MIPHY_PLL_SBR_3);
> +		writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);
> +		writeb_relaxed(0x3c, miphy_phy->base + MIPHY_PLL_SBR_2);
> +		writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);
> +		writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);
> +		writeb_relaxed(0x02, miphy_phy->base + MIPHY_PLL_SBR_1);
> +		writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);

I'd feel a lot better about all these magic numbers (and the triple write
to SBR_1) if the Changelog or something referenced where they came from....
Gabriel Fernandez Oct. 13, 2014, 8:16 a.m. UTC | #2 
Hi Valdis,
Thanks for your remark.

Concerning multiple writing in MIPHY_PLL_SBR_1, the writing of the
first 0 it's to be sure there is no previous request.
Then we take account new setting by writing 0x02.
And then we make it 0 to make sure there is no other pending requests.

I added comments and macro to be more clear (see the code below).


Hi Kishon,

Do you want a new patch set (v4),  or i wait other remarks from you ?


    for (val = 0; val < 2; val++) {
        writeb_relaxed(val, miphy_phy->base + MIPHY_CONF);

        /* Validate Step component */
        writeb_relaxed(0x69, miphy_phy->base + MIPHY_PLL_SBR_3);
        writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);

        /* Validate Period component */
        writeb_relaxed(0x3c, miphy_phy->base + MIPHY_PLL_SBR_2);
        writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);

        /* Clear any previous request */
        writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);

        /* requests the PLL to take in account new parameters */
        writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);

        /* To be sure there is no other pending requests */
        writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);
    }


Best regards

Gabriel.


On 29 September 2014 21:19,  <Valdis.Kletnieks@vt.edu> wrote:
> On Fri, 26 Sep 2014 10:54:15 +0200, Gabriel FERNANDEZ said:
>> SSC is the technique of modulating the operating frequency of a signal
>> slightly to spread its radiated emissions over a range of frequencies.
>> This reduction in the maximum emission for a given frequency helps meet
>> radiated emission requirements.
>> These settings are applicable for PCIE with Internal clock.
>
>> +             writeb_relaxed(0x69, miphy_phy->base + MIPHY_PLL_SBR_3);
>> +             writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);
>> +             writeb_relaxed(0x3c, miphy_phy->base + MIPHY_PLL_SBR_2);
>> +             writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);
>> +             writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);
>> +             writeb_relaxed(0x02, miphy_phy->base + MIPHY_PLL_SBR_1);
>> +             writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);
>
> I'd feel a lot better about all these magic numbers (and the triple write
> to SBR_1) if the Changelog or something referenced where they came from....
Valdis Klētnieks Oct. 13, 2014, 4:12 p.m. UTC | #3 
On Mon, 13 Oct 2014 10:16:06 +0200, Gabriel Fernandez said:

> Concerning multiple writing in MIPHY_PLL_SBR_1, the writing of the
> first 0 it's to be sure there is no previous request.
> Then we take account new setting by writing 0x02.
> And then we make it 0 to make sure there is no other pending requests.
>
> I added comments and macro to be more clear (see the code below).

Thanks, that will be a lot clearer to some poor soul down the road who
has to delve in here (possibly to figure out if a new part can use the
same driver and/or what changes need to be made).
Kishon Vijay Abraham I Oct. 21, 2014, 11:49 a.m. UTC | #4 
Hi,

On Monday 13 October 2014 01:46 PM, Gabriel Fernandez wrote:
> Hi Valdis,
> Thanks for your remark.
> 
> Concerning multiple writing in MIPHY_PLL_SBR_1, the writing of the
> first 0 it's to be sure there is no previous request.
> Then we take account new setting by writing 0x02.
> And then we make it 0 to make sure there is no other pending requests.
> 
> I added comments and macro to be more clear (see the code below).
> 
> 
> Hi Kishon,
> 
> Do you want a new patch set (v4),  or i wait other remarks from you ?

Apart from my comment below and for adding a common dt header file, rest of it
looks fine.
> 
> 
>     for (val = 0; val < 2; val++) {

What is "2" here? Lets add a macro for it.

Thanks
Kishon
Gabriel Fernandez Oct. 21, 2014, 3:51 p.m. UTC | #5 
Hi Kishon

Okay, i will fix it.


Thanks.

Gabriel

On 21 October 2014 13:49, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> Hi,
>
> On Monday 13 October 2014 01:46 PM, Gabriel Fernandez wrote:
>> Hi Valdis,
>> Thanks for your remark.
>>
>> Concerning multiple writing in MIPHY_PLL_SBR_1, the writing of the
>> first 0 it's to be sure there is no previous request.
>> Then we take account new setting by writing 0x02.
>> And then we make it 0 to make sure there is no other pending requests.
>>
>> I added comments and macro to be more clear (see the code below).
>>
>>
>> Hi Kishon,
>>
>> Do you want a new patch set (v4),  or i wait other remarks from you ?
>
> Apart from my comment below and for adding a common dt header file, rest of it
> looks fine.
>>
>>
>>     for (val = 0; val < 2; val++) {
>
> What is "2" here? Lets add a macro for it.
>
> Thanks
> Kishon
diff mbox

Patch

diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index 7285543..b6574e8 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -579,6 +579,35 @@  static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
 	}
 }
 
+static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
+{
+	u8 val;
+
+	/* Compensate Tx impedance to avoid out of range values */
+	/*
+	 * Enable the SSC on PLL for all banks
+	 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
+	 */
+	val = readb_relaxed(miphy_phy->base + MIPHY_BOUNDARY_2);
+	val |= SSC_EN_SW;
+	writeb_relaxed(val, miphy_phy->base + MIPHY_BOUNDARY_2);
+
+	val = readb_relaxed(miphy_phy->base + MIPHY_BOUNDARY_SEL);
+	val |= SSC_SEL;
+	writeb_relaxed(val, miphy_phy->base + MIPHY_BOUNDARY_SEL);
+
+	for (val = 0; val < 2; val++) {
+		writeb_relaxed(val, miphy_phy->base + MIPHY_CONF);
+		writeb_relaxed(0x69, miphy_phy->base + MIPHY_PLL_SBR_3);
+		writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);
+		writeb_relaxed(0x3c, miphy_phy->base + MIPHY_PLL_SBR_2);
+		writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4);
+		writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);
+		writeb_relaxed(0x02, miphy_phy->base + MIPHY_PLL_SBR_1);
+		writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1);
+	}
+}
+
 static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
 {
 	void __iomem *base = miphy_phy->base;
@@ -647,6 +676,9 @@  static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
 	if (err)
 		return err;
 
+	if (miphy_phy->ssc)
+		miphy_pcie_tune_ssc(miphy_phy);
+
 	return 0;
 }