| Message ID | 1416865877-8347-1-git-send-email-suravee.suthikulpanit@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Suravee, Some comments below. On Mon, Nov 24, 2014 at 1:51 PM, <suravee.suthikulpanit@amd.com> wrote: > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > > Initial revision of device tree for AMD Seattle platform. > > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Marc Zyngier <marc.zyngier@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > Signed-off-by: Thomas Lendacky <Thomas.Lendacky@amd.com> > Signed-off-by: Joel Schopp <Joel.Schopp@amd.com> > --- > V4 Changes: > * Remove unnecessary smb layer and move motherbord to top level > * Move include dtsi to top level > * Remove apb_pclk from sata0 and i2c > * Fix GIC Virtual Maintanance Interrupt from PPI24 (8) to PPI25 (9) > * Add 40-bit dma-ranges for motherboard (simple-bus) > * Remove dma0 (pl330) entry for now since it only supports 32-bit DMA. > It is basically not used at the moment. It would also need SMMU > to allow dma remapping to 40-bit DMA range. > * Add phandle spi0 and spi1 > * Hook up gpio0 pin 7 with MMC Card Detection (CD) support. > * Changes in pcie0 entry: > - Add 40-bit dma-ranges > - Remove interrupts property > - Add interrupt-map/mask property > - Fix PCI I/O range > - Merge PCI 32-bit ranges > - Merge PCI 64-bit ranges > > NOTE: I am not add a new compatible ID for the sata0 as Rob Herring > suggested since there is no need at the momement, and I am trying > to avoid introducing ID unnecessarily. > > arch/arm64/Kconfig | 5 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/amd-seattle-periph.dtsi | 156 ++++++++++++++++++++++++++++ > arch/arm64/boot/dts/amd-seattle.dts | 89 ++++++++++++++++ > 4 files changed, 251 insertions(+) > create mode 100644 arch/arm64/boot/dts/amd-seattle-periph.dtsi > create mode 100644 arch/arm64/boot/dts/amd-seattle.dts > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..ddc0196 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -142,6 +142,11 @@ source "kernel/Kconfig.freezer" > > menu "Platform selection" > > +config ARCH_SEATTLE > + bool "AMD Seattle SoC Family" > + help > + This enables support for AMD Seattle SOC Family > + > config ARCH_THUNDER > bool "Cavium Inc. Thunder SoC Family" > help > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index f8001a6..604af09 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -1,3 +1,4 @@ > +dtb-$(CONFIG_ARCH_SEATTLE) += amd-seattle.dtb > dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb For 3.19, we're moving all device tree files on arm64 int per-vendor subdirectories. Can you please prepare this patch to go on top of linux-next (or arm-soc for-next) such that it adds this file in the same place? (Alternatively, we can move it when applying, it's not a huge deal). > dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb > diff --git a/arch/arm64/boot/dts/amd-seattle-periph.dtsi b/arch/arm64/boot/dts/amd-seattle-periph.dtsi > new file mode 100644 > index 0000000..77f565b > --- /dev/null > +++ b/arch/arm64/boot/dts/amd-seattle-periph.dtsi > @@ -0,0 +1,156 @@ > +/* > + * DTS file for AMD Seattle Peripheral > + * > + * Copyright (C) 2014 Advanced Micro Devices, Inc. > + */ > + > +/ { > + motherboard { > + compatible = "simple-bus"; I'm not sure I understand this abstraction. You have a motherboard device node, under which you have things like the pl011 UART and SATA -- while those blocks really are part of SoC, aren't they? After all, you have the pci-e controller as part of the dts file and not the dtsi. Unless you have some underlying motive, it would make more sense to keep these at the same toplevel since the "motherboard" doesn't seem to be part of the hardware topology as described. > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0xe0000000 0 0x01300000>; > + > + /* DDR range is 40-bit addressing */ > + dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>; > + > + adl3clk_100mhz: clk100mhz_0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "adl3clk_100mhz"; > + }; > + > + ccpclk_375mhz: clk375mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <375000000>; > + clock-output-names = "ccpclk_375mhz"; > + }; > + > + sataclk_333mhz: clk333mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <333000000>; > + clock-output-names = "sataclk_333mhz"; > + }; > + > + pcieclk_500mhz: clk500mhz_0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <500000000>; > + clock-output-names = "pcieclk_500mhz"; > + }; > + > + dmaclk_500mhz: clk500mhz_1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <500000000>; > + clock-output-names = "dmaclk_500mhz"; > + }; > + > + miscclk_250mhz: clk250mhz_4 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <250000000>; > + clock-output-names = "miscclk_250mhz"; > + }; > + > + uartspiclk_100mhz: clk100mhz_1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "uartspiclk_100mhz"; > + }; > + > + sata0: sata@00300000 { > + compatible = "snps,dwc-ahci"; > + reg = <0 0x300000 0 0x800>; > + interrupts = <0 355 4>; > + clocks = <&sataclk_333mhz>; > + dma-coherent; > + }; > + > + i2c@1000000 { > + compatible = "snps,designware-i2c"; > + reg = <0 0x01000000 0 0x1000>; > + interrupts = <0 357 4>; > + clocks = <&uartspiclk_100mhz>; > + }; > + > + serial0: serial@1010000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0 0x1010000 0 0x1000>; > + interrupts = <0 328 4>; > + clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; > + clock-names = "uartclk", "apb_pclk"; > + }; > + > + spi0: ssp@1020000 { > + compatible = "arm,pl022", "arm,primecell"; > + #gpio-cells = <2>; > + reg = <0 0x1020000 0 0x1000>; > + spi-controller; > + interrupts = <0 330 4>; > + clocks = <&uartspiclk_100mhz>; > + clock-names = "apb_pclk"; > + }; > + > + spi1: ssp@1030000 { > + compatible = "arm,pl022", "arm,primecell"; > + #gpio-cells = <2>; > + reg = <0 0x1030000 0 0x1000>; > + spi-controller; > + interrupts = <0 329 4>; > + clocks = <&uartspiclk_100mhz>; > + clock-names = "apb_pclk"; > + num-cs = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + sdcard@0 { > + compatible = "mmc-spi-slot"; > + reg = <0>; > + spi-max-frequency = <20000000>; > + voltage-ranges = <3200 3400>; > + gpios = <&gpio0 7 0>; > + interrupt-parent = <&gpio0>; > + interrupts = <7 3>; > + pl022,hierarchy = <0>; > + pl022,interface = <0>; > + pl022,com-mode = <0x0>; > + pl022,rx-level-trig = <0>; > + pl022,tx-level-trig = <0>; > + }; > + }; > + > + gpio0: gpio@1040000 { > + compatible = "arm,pl061", "arm,primecell"; > + #gpio-cells = <2>; > + reg = <0 0x1040000 0 0x1000>; > + gpio-controller; > + interrupts = <0 359 4>; > + interrupt-controller; > + #interrupt-cells = <2>; > + clocks = <&uartspiclk_100mhz>; > + clock-names = "apb_pclk"; > + }; > + > + gpio1: gpio@1050000 { > + compatible = "arm,pl061", "arm,primecell"; > + #gpio-cells = <2>; > + reg = <0 0x1050000 0 0x1000>; > + gpio-controller; > + interrupts = <0 358 4>; > + clocks = <&uartspiclk_100mhz>; > + clock-names = "apb_pclk"; > + }; > + > + ccp: ccp@00100000 { > + compatible = "amd,ccp-seattle-v1a"; > + reg = <0 0x00100000 0 0x10000>; > + interrupts = <0 3 4>; > + dma-coherent; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/amd-seattle.dts b/arch/arm64/boot/dts/amd-seattle.dts > new file mode 100644 > index 0000000..d5fc482 > --- /dev/null > +++ b/arch/arm64/boot/dts/amd-seattle.dts > @@ -0,0 +1,89 @@ > +/* > + * DTS file for AMD Seattle > + * > + * Copyright (C) 2014 Advanced Micro Devices, Inc. > + */ > + > +/dts-v1/; > + > +/include/ "amd-seattle-periph.dtsi" > + > +/ { > + compatible = "amd,seattle"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; So is this the dts for a specific board? Isn't Seattle the SoC? You might want to have a different topmost compatible here to identify the board. You should also have a "model" property here to describe what the hardware is. (I'm guessing it's really the development board for Seattle, correct?) > + > + chosen { > + stdout-path = &serial0; > + linux,pci-probe-only; > + }; > + > + gic: interrupt-controller@e1101000 { > + compatible = "arm,gic-400", "arm,cortex-a15-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + reg = <0x0 0xe1110000 0 0x1000>, > + <0x0 0xe112f000 0 0x2000>, > + <0x0 0xe1140000 0 0x10000>, > + <0x0 0xe1160000 0 0x10000>; > + interrupts = <1 9 0xf04>; > + ranges; > + v2m0: v2m@e1180000 { > + compatible = "arm,gic-v2m-frame"; > + msi-controller; > + arm,msi-base-spi = <64>; > + arm,msi-num-spis = <256>; > + reg = <0x0 0xe1180000 0 0x1000>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <1 13 0xff01>, > + <1 14 0xff01>, > + <1 11 0xff01>, > + <1 10 0xff01>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <0 7 4>, > + <0 8 4>, > + <0 9 4>, > + <0 10 4>, > + <0 11 4>, > + <0 12 4>, > + <0 13 4>, > + <0 14 4>; > + }; > + > + pcie0: pcie-controller { > + compatible = "pci-host-ecam-generic"; The controller itself should likely go in the SoC dtsi, and only per-board additional attributes should go here. It's also common to add a status = "disabled" in the dtsi, and overriding in the per-system dts with status = "okay" for those IP blocks that are actually useful on a particular platform. So, for example, if the SoC has SATA, but a particular board does not, then you wouldn't enable it in the dts. Also, if you use labels for the nodes in the dts, then you can do a flat-format dts where you don't have to exactly duplicate the same hierarchy of nodes to override a property (you're already using labels). I.e. in this case you could then do (for a board that does use sata): &sata0 { status = "okay"; }; in the dts (this would go at the top level of the file, not nested under other nodes). > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + device_type = "pci"; > + bus-range = <0 0xff>; > + reg = <0 0xf0000000 0 0x10000000>; > + msi-parent = <&v2m0>; > + > + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; > + interrupt-map = <0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x120 0x1>, > + <0x1000 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x121 0x1>, > + <0x1000 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x122 0x1>, > + <0x1000 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x123 0x1>; > + > + dma-coherent; > + dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>; > + ranges = > + /* I/O Memory (size=64K) */ > + <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, > + /* 32-bit MMIO (size=2G) */ > + <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>, > + /* 64-bit MMIO (size= 124G) */ > + <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; > + }; > +}; -Olof
Hi Olof, On 11/25/14, 06:09, "Olof Johansson" <olof@lixom.net> wrote: >Hi Suravee, > >Some comments below. > > >On Mon, Nov 24, 2014 at 1:51 PM, <suravee.suthikulpanit@amd.com> wrote: >> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> >> >>[...] >> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile >> index f8001a6..604af09 100644 >> --- a/arch/arm64/boot/dts/Makefile >> +++ b/arch/arm64/boot/dts/Makefile >> @@ -1,3 +1,4 @@ >> +dtb-$(CONFIG_ARCH_SEATTLE) += amd-seattle.dtb >> dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb >> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb > >For 3.19, we're moving all device tree files on arm64 int per-vendor >subdirectories. > >Can you please prepare this patch to go on top of linux-next (or >arm-soc for-next) such that it adds this file in the same place? > >(Alternatively, we can move it when applying, it's not a huge deal). No problem. I will provide V5 based with the new directory structure. > > >> dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb >> diff --git a/arch/arm64/boot/dts/amd-seattle-periph.dtsi >>b/arch/arm64/boot/dts/amd-seattle-periph.dtsi >> new file mode 100644 >> index 0000000..77f565b >> --- /dev/null >> +++ b/arch/arm64/boot/dts/amd-seattle-periph.dtsi >> @@ -0,0 +1,156 @@ >> +/* >> + * DTS file for AMD Seattle Peripheral >> + * >> + * Copyright (C) 2014 Advanced Micro Devices, Inc. >> + */ >> + >> +/ { >> + motherboard { >> + compatible = "simple-bus"; > >I'm not sure I understand this abstraction. You have a motherboard >device node, under which you have things like the pl011 UART and SATA >-- while those blocks really are part of SoC, aren't they? After all, >you have the pci-e controller as part of the dts file and not the >dtsi. Yes, they are parts of the SoC. I will rename the entry to smb, and I will move the pcie under the smb. > >Unless you have some underlying motive, it would make more sense to >keep these at the same toplevel since the "motherboard" doesn't seem >to be part of the hardware topology as described. I will restructure the DTS/DTSI and send out V5. >[..] >> diff --git a/arch/arm64/boot/dts/amd-seattle.dts >>b/arch/arm64/boot/dts/amd-seattle.dts >> new file mode 100644 >> index 0000000..d5fc482 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/amd-seattle.dts >> @@ -0,0 +1,89 @@ >> +/* >> + * DTS file for AMD Seattle >> + * >> + * Copyright (C) 2014 Advanced Micro Devices, Inc. >> + */ >> + >> +/dts-v1/; >> + >> +/include/ "amd-seattle-periph.dtsi" >> + >> +/ { >> + compatible = "amd,seattle"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; > >So is this the dts for a specific board? Isn't Seattle the SoC? You >might want to have a different topmost compatible here to identify the >board. You should also have a "model" property here to describe what >the hardware is. > >(I'm guessing it's really the development board for Seattle, correct?) Yes, Seattle is an SoC, and this DTS is meant for the Seattle development board. I will add the model property accordingly. >[..] >> + >> + pcie0: pcie-controller { >> + compatible = "pci-host-ecam-generic"; > >The controller itself should likely go in the SoC dtsi, and only >per-board additional attributes should go here. Ok, I will move it. > >It's also common to add a status = "disabled" in the dtsi, and >overriding in the per-system dts with status = "okay" for those IP >blocks that are actually useful on a particular platform. > >So, for example, if the SoC has SATA, but a particular board does not, >then you wouldn't enable it in the dts. > >Also, if you use labels for the nodes in the dts, then you can do a >flat-format dts where you don't have to exactly duplicate the same >hierarchy of nodes to override a property (you're already using >labels). I.e. in this case you could then do (for a board that does >use sata): > >&sata0 { > status = "okay"; >}; > >in the dts (this would go at the top level of the file, not nested >under other nodes). This is actually a great idea. Thank you for suggestions. I will adopt this approach in the V5. Thanks, Suravee
Hi Suravee, Just spotted a small issue below (looks like a recurring mistake in a number of DTs I've seem lately): On 24/11/14 21:51, suravee.suthikulpanit@amd.com wrote: > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > > Initial revision of device tree for AMD Seattle platform. > > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Marc Zyngier <marc.zyngier@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > Signed-off-by: Thomas Lendacky <Thomas.Lendacky@amd.com> > Signed-off-by: Joel Schopp <Joel.Schopp@amd.com> > --- > V4 Changes: > * Remove unnecessary smb layer and move motherbord to top level > * Move include dtsi to top level > * Remove apb_pclk from sata0 and i2c > * Fix GIC Virtual Maintanance Interrupt from PPI24 (8) to PPI25 (9) > * Add 40-bit dma-ranges for motherboard (simple-bus) > * Remove dma0 (pl330) entry for now since it only supports 32-bit DMA. > It is basically not used at the moment. It would also need SMMU > to allow dma remapping to 40-bit DMA range. > * Add phandle spi0 and spi1 > * Hook up gpio0 pin 7 with MMC Card Detection (CD) support. > * Changes in pcie0 entry: > - Add 40-bit dma-ranges > - Remove interrupts property > - Add interrupt-map/mask property > - Fix PCI I/O range > - Merge PCI 32-bit ranges > - Merge PCI 64-bit ranges > > NOTE: I am not add a new compatible ID for the sata0 as Rob Herring > suggested since there is no need at the momement, and I am trying > to avoid introducing ID unnecessarily. > > arch/arm64/Kconfig | 5 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/amd-seattle-periph.dtsi | 156 ++++++++++++++++++++++++++++ > arch/arm64/boot/dts/amd-seattle.dts | 89 ++++++++++++++++ > 4 files changed, 251 insertions(+) > create mode 100644 arch/arm64/boot/dts/amd-seattle-periph.dtsi > create mode 100644 arch/arm64/boot/dts/amd-seattle.dts > [...] > diff --git a/arch/arm64/boot/dts/amd-seattle.dts b/arch/arm64/boot/dts/amd-seattle.dts > new file mode 100644 > index 0000000..d5fc482 > --- /dev/null > +++ b/arch/arm64/boot/dts/amd-seattle.dts > @@ -0,0 +1,89 @@ > +/* > + * DTS file for AMD Seattle > + * > + * Copyright (C) 2014 Advanced Micro Devices, Inc. > + */ > + > +/dts-v1/; > + > +/include/ "amd-seattle-periph.dtsi" > + > +/ { > + compatible = "amd,seattle"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { > + stdout-path = &serial0; > + linux,pci-probe-only; > + }; > + > + gic: interrupt-controller@e1101000 { > + compatible = "arm,gic-400", "arm,cortex-a15-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + reg = <0x0 0xe1110000 0 0x1000>, > + <0x0 0xe112f000 0 0x2000>, > + <0x0 0xe1140000 0 0x10000>, > + <0x0 0xe1160000 0 0x10000>; > + interrupts = <1 9 0xf04>; > + ranges; > + v2m0: v2m@e1180000 { > + compatible = "arm,gic-v2m-frame"; > + msi-controller; > + arm,msi-base-spi = <64>; > + arm,msi-num-spis = <256>; > + reg = <0x0 0xe1180000 0 0x1000>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <1 13 0xff01>, > + <1 14 0xff01>, > + <1 11 0xff01>, > + <1 10 0xff01>; > + }; The Cortex-A57 TRM clearly states that these interrupts are level triggered. Thanks, M.
Hi Marc, On 11/25/14, 17:23, "Marc Zyngier" <marc.zyngier@arm.com> wrote: >Hi Suravee, > >Just spotted a small issue below (looks like a recurring mistake in a >number of DTs I've seem lately): > >On 24/11/14 21:51, suravee.suthikulpanit@amd.com wrote: >> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> >> >> Initial revision of device tree for AMD Seattle platform. >> >> Cc: Arnd Bergmann <arnd@arndb.de> >> Cc: Marc Zyngier <marc.zyngier@arm.com> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Will Deacon <will.deacon@arm.com> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> >> Signed-off-by: Thomas Lendacky <Thomas.Lendacky@amd.com> >> Signed-off-by: Joel Schopp <Joel.Schopp@amd.com> >> --- >> V4 Changes: >> * Remove unnecessary smb layer and move motherbord to top level >> * Move include dtsi to top level >> * Remove apb_pclk from sata0 and i2c >> * Fix GIC Virtual Maintanance Interrupt from PPI24 (8) to PPI25 (9) >> * Add 40-bit dma-ranges for motherboard (simple-bus) >> * Remove dma0 (pl330) entry for now since it only supports 32-bit >>DMA. >> It is basically not used at the moment. It would also need SMMU >> to allow dma remapping to 40-bit DMA range. >> * Add phandle spi0 and spi1 >> * Hook up gpio0 pin 7 with MMC Card Detection (CD) support. >> * Changes in pcie0 entry: >> - Add 40-bit dma-ranges >> - Remove interrupts property >> - Add interrupt-map/mask property >> - Fix PCI I/O range >> - Merge PCI 32-bit ranges >> - Merge PCI 64-bit ranges >> >> NOTE: I am not add a new compatible ID for the sata0 as Rob Herring >> suggested since there is no need at the momement, and I am trying >> to avoid introducing ID unnecessarily. >> >> arch/arm64/Kconfig | 5 + >> arch/arm64/boot/dts/Makefile | 1 + >> arch/arm64/boot/dts/amd-seattle-periph.dtsi | 156 >>++++++++++++++++++++++++++++ >> arch/arm64/boot/dts/amd-seattle.dts | 89 ++++++++++++++++ >> 4 files changed, 251 insertions(+) >> create mode 100644 arch/arm64/boot/dts/amd-seattle-periph.dtsi >> create mode 100644 arch/arm64/boot/dts/amd-seattle.dts >> > >[...] > >> diff --git a/arch/arm64/boot/dts/amd-seattle.dts >>b/arch/arm64/boot/dts/amd-seattle.dts >> new file mode 100644 >> index 0000000..d5fc482 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/amd-seattle.dts >> @@ -0,0 +1,89 @@ >> +/* >> + * DTS file for AMD Seattle >> + * >> + * Copyright (C) 2014 Advanced Micro Devices, Inc. >> + */ >> + >> +/dts-v1/; >> + [...] >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <1 13 0xff01>, >> + <1 14 0xff01>, >> + <1 11 0xff01>, >> + <1 10 0xff01>; >> + }; > >The Cortex-A57 TRM clearly states that these interrupts are level >triggered. Thanks for pointing this out. I¹ll fix this to <1 1X 0xff04> (4 for the Active-High) then. Suravee >
On Monday 24 November 2014 15:51:17 suravee.suthikulpanit@amd.com wrote: > > + gic: interrupt-controller@e1101000 { > + compatible = "arm,gic-400", "arm,cortex-a15-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + reg = <0x0 0xe1110000 0 0x1000>, > + <0x0 0xe112f000 0 0x2000>, > + <0x0 0xe1140000 0 0x10000>, > + <0x0 0xe1160000 0 0x10000>; > + interrupts = <1 9 0xf04>; > + ranges; > + v2m0: v2m@e1180000 { > + compatible = "arm,gic-v2m-frame"; > + msi-controller; > + arm,msi-base-spi = <64>; > + arm,msi-num-spis = <256>; > + reg = <0x0 0xe1180000 0 0x1000>; > + }; > + }; Having an empty ranges property in the gic seems strange, especially since the registers of the v2m seem to directly follow the gic's own registers. Could you limit the ranges to only the registers that are in the gic or its child devices itself? Arnd
On 11/25/14, 18:57, "Arnd Bergmann" <arnd@arndb.de> wrote: >On Monday 24 November 2014 15:51:17 suravee.suthikulpanit@amd.com wrote: >> >> + gic: interrupt-controller@e1101000 { >> + compatible = "arm,gic-400", "arm,cortex-a15-gic"; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + reg = <0x0 0xe1110000 0 0x1000>, >> + <0x0 0xe112f000 0 0x2000>, >> + <0x0 0xe1140000 0 0x10000>, >> + <0x0 0xe1160000 0 0x10000>; >> + interrupts = <1 9 0xf04>; >> + ranges; >> + v2m0: v2m@e1180000 { >> + compatible = "arm,gic-v2m-frame"; >> + msi-controller; >> + arm,msi-base-spi = <64>; >> + arm,msi-num-spis = <256>; >> + reg = <0x0 0xe1180000 0 0x1000>; >> + }; >> + }; > > >Having an empty ranges property in the gic seems strange, especially >since the registers of the v2m seem to directly follow the gic's own >registers. Could you limit the ranges to only the registers that >are in the gic or its child devices itself? > > Arnd Yes, I can change it to ranges = <0 0 0 0xe1100000 0 0x100000> to limit the range to just the GIC address range. Thanks, Suravee
On Tue, Nov 25, 2014 at 11:46:50AM +0000, Suthikulpanit, Suravee wrote: > Hi Marc, > > On 11/25/14, 17:23, "Marc Zyngier" <marc.zyngier@arm.com> wrote: > > >Hi Suravee, > > > >Just spotted a small issue below (looks like a recurring mistake in a > >number of DTs I've seem lately): > > > >On 24/11/14 21:51, suravee.suthikulpanit@amd.com wrote: > >> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > >> > >> Initial revision of device tree for AMD Seattle platform. > >> > >> Cc: Arnd Bergmann <arnd@arndb.de> > >> Cc: Marc Zyngier <marc.zyngier@arm.com> > >> Cc: Mark Rutland <mark.rutland@arm.com> > >> Cc: Will Deacon <will.deacon@arm.com> > >> Cc: Catalin Marinas <catalin.marinas@arm.com> > >> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > >> Signed-off-by: Thomas Lendacky <Thomas.Lendacky@amd.com> > >> Signed-off-by: Joel Schopp <Joel.Schopp@amd.com> > >> --- > >> V4 Changes: > >> * Remove unnecessary smb layer and move motherbord to top level > >> * Move include dtsi to top level > >> * Remove apb_pclk from sata0 and i2c > >> * Fix GIC Virtual Maintanance Interrupt from PPI24 (8) to PPI25 (9) > >> * Add 40-bit dma-ranges for motherboard (simple-bus) > >> * Remove dma0 (pl330) entry for now since it only supports 32-bit > >>DMA. > >> It is basically not used at the moment. It would also need SMMU > >> to allow dma remapping to 40-bit DMA range. > >> * Add phandle spi0 and spi1 > >> * Hook up gpio0 pin 7 with MMC Card Detection (CD) support. > >> * Changes in pcie0 entry: > >> - Add 40-bit dma-ranges > >> - Remove interrupts property > >> - Add interrupt-map/mask property > >> - Fix PCI I/O range > >> - Merge PCI 32-bit ranges > >> - Merge PCI 64-bit ranges > >> > >> NOTE: I am not add a new compatible ID for the sata0 as Rob Herring > >> suggested since there is no need at the momement, and I am trying > >> to avoid introducing ID unnecessarily. > >> > >> arch/arm64/Kconfig | 5 + > >> arch/arm64/boot/dts/Makefile | 1 + > >> arch/arm64/boot/dts/amd-seattle-periph.dtsi | 156 > >>++++++++++++++++++++++++++++ > >> arch/arm64/boot/dts/amd-seattle.dts | 89 ++++++++++++++++ > >> 4 files changed, 251 insertions(+) > >> create mode 100644 arch/arm64/boot/dts/amd-seattle-periph.dtsi > >> create mode 100644 arch/arm64/boot/dts/amd-seattle.dts > >> > > > >[...] > > > >> diff --git a/arch/arm64/boot/dts/amd-seattle.dts > >>b/arch/arm64/boot/dts/amd-seattle.dts > >> new file mode 100644 > >> index 0000000..d5fc482 > >> --- /dev/null > >> +++ b/arch/arm64/boot/dts/amd-seattle.dts > >> @@ -0,0 +1,89 @@ > >> +/* > >> + * DTS file for AMD Seattle > >> + * > >> + * Copyright (C) 2014 Advanced Micro Devices, Inc. > >> + */ > >> + > >> +/dts-v1/; > >> + > > [...] > > >> + > >> + timer { > >> + compatible = "arm,armv8-timer"; > >> + interrupts = <1 13 0xff01>, > >> + <1 14 0xff01>, > >> + <1 11 0xff01>, > >> + <1 10 0xff01>; > >> + }; > > > >The Cortex-A57 TRM clearly states that these interrupts are level > >triggered. > > Thanks for pointing this out. I¹ll fix this to <1 1X 0xff04> (4 for the > Active-High) then. Hi Suravee, Don't know what Seattle does, but the TRM says that the outputs are active-LOW. Best regards, Liviu > > Suravee > > > > >
On 27/11/14 14:28, Liviu Dudau wrote: > On Tue, Nov 25, 2014 at 11:46:50AM +0000, Suthikulpanit, Suravee wrote: >> Hi Marc, >> >> On 11/25/14, 17:23, "Marc Zyngier" <marc.zyngier@arm.com> wrote: >> >>> Hi Suravee, >>> >>> Just spotted a small issue below (looks like a recurring mistake in a >>> number of DTs I've seem lately): >>> >>> On 24/11/14 21:51, suravee.suthikulpanit@amd.com wrote: >>>> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> >>>> >>>> Initial revision of device tree for AMD Seattle platform. >>>> >>>> Cc: Arnd Bergmann <arnd@arndb.de> >>>> Cc: Marc Zyngier <marc.zyngier@arm.com> >>>> Cc: Mark Rutland <mark.rutland@arm.com> >>>> Cc: Will Deacon <will.deacon@arm.com> >>>> Cc: Catalin Marinas <catalin.marinas@arm.com> >>>> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> >>>> Signed-off-by: Thomas Lendacky <Thomas.Lendacky@amd.com> >>>> Signed-off-by: Joel Schopp <Joel.Schopp@amd.com> >>>> --- >>>> V4 Changes: >>>> * Remove unnecessary smb layer and move motherbord to top level >>>> * Move include dtsi to top level >>>> * Remove apb_pclk from sata0 and i2c >>>> * Fix GIC Virtual Maintanance Interrupt from PPI24 (8) to PPI25 (9) >>>> * Add 40-bit dma-ranges for motherboard (simple-bus) >>>> * Remove dma0 (pl330) entry for now since it only supports 32-bit >>>> DMA. >>>> It is basically not used at the moment. It would also need SMMU >>>> to allow dma remapping to 40-bit DMA range. >>>> * Add phandle spi0 and spi1 >>>> * Hook up gpio0 pin 7 with MMC Card Detection (CD) support. >>>> * Changes in pcie0 entry: >>>> - Add 40-bit dma-ranges >>>> - Remove interrupts property >>>> - Add interrupt-map/mask property >>>> - Fix PCI I/O range >>>> - Merge PCI 32-bit ranges >>>> - Merge PCI 64-bit ranges >>>> >>>> NOTE: I am not add a new compatible ID for the sata0 as Rob Herring >>>> suggested since there is no need at the momement, and I am trying >>>> to avoid introducing ID unnecessarily. >>>> >>>> arch/arm64/Kconfig | 5 + >>>> arch/arm64/boot/dts/Makefile | 1 + >>>> arch/arm64/boot/dts/amd-seattle-periph.dtsi | 156 >>>> ++++++++++++++++++++++++++++ >>>> arch/arm64/boot/dts/amd-seattle.dts | 89 ++++++++++++++++ >>>> 4 files changed, 251 insertions(+) >>>> create mode 100644 arch/arm64/boot/dts/amd-seattle-periph.dtsi >>>> create mode 100644 arch/arm64/boot/dts/amd-seattle.dts >>>> >>> >>> [...] >>> >>>> diff --git a/arch/arm64/boot/dts/amd-seattle.dts >>>> b/arch/arm64/boot/dts/amd-seattle.dts >>>> new file mode 100644 >>>> index 0000000..d5fc482 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/amd-seattle.dts >>>> @@ -0,0 +1,89 @@ >>>> +/* >>>> + * DTS file for AMD Seattle >>>> + * >>>> + * Copyright (C) 2014 Advanced Micro Devices, Inc. >>>> + */ >>>> + >>>> +/dts-v1/; >>>> + >> >> [...] >> >>>> + >>>> + timer { >>>> + compatible = "arm,armv8-timer"; >>>> + interrupts = <1 13 0xff01>, >>>> + <1 14 0xff01>, >>>> + <1 11 0xff01>, >>>> + <1 10 0xff01>; >>>> + }; >>> >>> The Cortex-A57 TRM clearly states that these interrupts are level >>> triggered. >> >> Thanks for pointing this out. I¹ll fix this to <1 1X 0xff04> (4 for the >> Active-High) then. > > Hi Suravee, > > Don't know what Seattle does, but the TRM says that the outputs are active-LOW. As I said in another thread, 0xff04 *is* the right value. This is an interrupt descriptor for the GIC, not a qualifier for the signal that comes out of the core. Thanks. M.
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..ddc0196 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -142,6 +142,11 @@ source "kernel/Kconfig.freezer" menu "Platform selection" +config ARCH_SEATTLE + bool "AMD Seattle SoC Family" + help + This enables support for AMD Seattle SOC Family + config ARCH_THUNDER bool "Cavium Inc. Thunder SoC Family" help diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f8001a6..604af09 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_SEATTLE) += amd-seattle.dtb dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb diff --git a/arch/arm64/boot/dts/amd-seattle-periph.dtsi b/arch/arm64/boot/dts/amd-seattle-periph.dtsi new file mode 100644 index 0000000..77f565b --- /dev/null +++ b/arch/arm64/boot/dts/amd-seattle-periph.dtsi @@ -0,0 +1,156 @@ +/* + * DTS file for AMD Seattle Peripheral + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + */ + +/ { + motherboard { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0xe0000000 0 0x01300000>; + + /* DDR range is 40-bit addressing */ + dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + + adl3clk_100mhz: clk100mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "adl3clk_100mhz"; + }; + + ccpclk_375mhz: clk375mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <375000000>; + clock-output-names = "ccpclk_375mhz"; + }; + + sataclk_333mhz: clk333mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333000000>; + clock-output-names = "sataclk_333mhz"; + }; + + pcieclk_500mhz: clk500mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + clock-output-names = "pcieclk_500mhz"; + }; + + dmaclk_500mhz: clk500mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + clock-output-names = "dmaclk_500mhz"; + }; + + miscclk_250mhz: clk250mhz_4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "miscclk_250mhz"; + }; + + uartspiclk_100mhz: clk100mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "uartspiclk_100mhz"; + }; + + sata0: sata@00300000 { + compatible = "snps,dwc-ahci"; + reg = <0 0x300000 0 0x800>; + interrupts = <0 355 4>; + clocks = <&sataclk_333mhz>; + dma-coherent; + }; + + i2c@1000000 { + compatible = "snps,designware-i2c"; + reg = <0 0x01000000 0 0x1000>; + interrupts = <0 357 4>; + clocks = <&uartspiclk_100mhz>; + }; + + serial0: serial@1010000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x1010000 0 0x1000>; + interrupts = <0 328 4>; + clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + spi0: ssp@1020000 { + compatible = "arm,pl022", "arm,primecell"; + #gpio-cells = <2>; + reg = <0 0x1020000 0 0x1000>; + spi-controller; + interrupts = <0 330 4>; + clocks = <&uartspiclk_100mhz>; + clock-names = "apb_pclk"; + }; + + spi1: ssp@1030000 { + compatible = "arm,pl022", "arm,primecell"; + #gpio-cells = <2>; + reg = <0 0x1030000 0 0x1000>; + spi-controller; + interrupts = <0 329 4>; + clocks = <&uartspiclk_100mhz>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + + sdcard@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3200 3400>; + gpios = <&gpio0 7 0>; + interrupt-parent = <&gpio0>; + interrupts = <7 3>; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,com-mode = <0x0>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + }; + }; + + gpio0: gpio@1040000 { + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <2>; + reg = <0 0x1040000 0 0x1000>; + gpio-controller; + interrupts = <0 359 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&uartspiclk_100mhz>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@1050000 { + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <2>; + reg = <0 0x1050000 0 0x1000>; + gpio-controller; + interrupts = <0 358 4>; + clocks = <&uartspiclk_100mhz>; + clock-names = "apb_pclk"; + }; + + ccp: ccp@00100000 { + compatible = "amd,ccp-seattle-v1a"; + reg = <0 0x00100000 0 0x10000>; + interrupts = <0 3 4>; + dma-coherent; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd-seattle.dts b/arch/arm64/boot/dts/amd-seattle.dts new file mode 100644 index 0000000..d5fc482 --- /dev/null +++ b/arch/arm64/boot/dts/amd-seattle.dts @@ -0,0 +1,89 @@ +/* + * DTS file for AMD Seattle + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +/include/ "amd-seattle-periph.dtsi" + +/ { + compatible = "amd,seattle"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = &serial0; + linux,pci-probe-only; + }; + + gic: interrupt-controller@e1101000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0xe1110000 0 0x1000>, + <0x0 0xe112f000 0 0x2000>, + <0x0 0xe1140000 0 0x10000>, + <0x0 0xe1160000 0 0x10000>; + interrupts = <1 9 0xf04>; + ranges; + v2m0: v2m@e1180000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + arm,msi-base-spi = <64>; + arm,msi-num-spis = <256>; + reg = <0x0 0xe1180000 0 0x1000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 7 4>, + <0 8 4>, + <0 9 4>, + <0 10 4>, + <0 11 4>, + <0 12 4>, + <0 13 4>, + <0 14 4>; + }; + + pcie0: pcie-controller { + compatible = "pci-host-ecam-generic"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + bus-range = <0 0xff>; + reg = <0 0xf0000000 0 0x10000000>; + msi-parent = <&v2m0>; + + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x120 0x1>, + <0x1000 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x121 0x1>, + <0x1000 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x122 0x1>, + <0x1000 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x123 0x1>; + + dma-coherent; + dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + ranges = + /* I/O Memory (size=64K) */ + <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, + /* 32-bit MMIO (size=2G) */ + <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>, + /* 64-bit MMIO (size= 124G) */ + <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; + }; +};