[7/8] drm/i915: Make intel_crtc->config a pointer

Message ID	1418301491-23020-8-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Dec 2014 14:38:10 +0200 Message-Id: <1418301491-23020-8-git-send-email-ander.conselvan.de.oliveira@intel.com> In-Reply-To: <1418301491-23020-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1418301491-23020-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>, shuang.he@linux.intel.com Subject: [Intel-gfx] [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

On Thu, Dec 11, 2014 at 02:38:10PM +0200, Ander Conselvan de Oliveira wrote: > To match the semantics of drm_crtc->state, which this will eventually > become. > > @@ struct intel_crtc *crtc; @@ > -&crtc->config > +crtc->config > @@ struct intel_crtc *crtc; identifier member; @@ > -crtc->config.member > +crtc->config->member > @@ struct drm_crtc *crtc; @@ > -&to_intel_crtc(crtc)->config > +to_intel_crtc(crtc)->config > @@ struct drm_crtc *crtc; identifier member; @@ > -to_intel_crtc(crtc)->config.member > +to_intel_crtc(crtc)->config->member Just to avoid confusion, you may want to indicate that there are a few changes beyond the coccinelle spatch listed here (allocation in intel_crtc_init, assignment with new intel_crtc_set_state, etc.). Also, I may be missing it happening somewhere else in the large patch, but do we need an intel_crtc_set_state(intel_crtc, NULL) in intel_crtc_destroy() to ensure that our final state doesn't leak when we rmmod? Matt > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 12 +- > drivers/gpu/drm/i915/i915_irq.c | 8 +- > drivers/gpu/drm/i915/intel_audio.c | 2 +- > drivers/gpu/drm/i915/intel_crt.c | 2 +- > drivers/gpu/drm/i915/intel_ddi.c | 52 +++---- > drivers/gpu/drm/i915/intel_display.c | 275 ++++++++++++++++++----------------- > drivers/gpu/drm/i915/intel_dp.c | 16 +- > drivers/gpu/drm/i915/intel_dp_mst.c | 7 +- > drivers/gpu/drm/i915/intel_drv.h | 2 +- > drivers/gpu/drm/i915/intel_dsi.c | 8 +- > drivers/gpu/drm/i915/intel_dvo.c | 8 +- > drivers/gpu/drm/i915/intel_fbdev.c | 10 +- > drivers/gpu/drm/i915/intel_hdmi.c | 36 ++--- > drivers/gpu/drm/i915/intel_lvds.c | 6 +- > drivers/gpu/drm/i915/intel_overlay.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 56 +++---- > drivers/gpu/drm/i915/intel_psr.c | 8 +- > drivers/gpu/drm/i915/intel_sdvo.c | 14 +- > drivers/gpu/drm/i915/intel_sprite.c | 2 +- > 19 files changed, 270 insertions(+), 256 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index d0e445e..a724e8c 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2572,7 +2572,7 @@ static int i915_display_info(struct seq_file *m, void *unused) > > seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", > crtc->base.base.id, pipe_name(crtc->pipe), > - yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); > + yesno(crtc->active), crtc->config->pipe_src_w, crtc->config->pipe_src_h); > if (crtc->active) { > intel_crtc_info(m, crtc); > > @@ -3280,9 +3280,9 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) > * relevant on hsw with pipe A when using the always-on power well > * routing. > */ > - if (crtc->config.cpu_transcoder == TRANSCODER_EDP && > - !crtc->config.pch_pfit.enabled) { > - crtc->config.pch_pfit.force_thru = true; > + if (crtc->config->cpu_transcoder == TRANSCODER_EDP && > + !crtc->config->pch_pfit.enabled) { > + crtc->config->pch_pfit.force_thru = true; > > intel_display_power_get(dev_priv, > POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); > @@ -3306,8 +3306,8 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) > * relevant on hsw with pipe A when using the always-on power well > * routing. > */ > - if (crtc->config.pch_pfit.force_thru) { > - crtc->config.pch_pfit.force_thru = false; > + if (crtc->config->pch_pfit.force_thru) { > + crtc->config->pch_pfit.force_thru = false; > > dev_priv->display.crtc_disable(&crtc->base); > dev_priv->display.crtc_enable(&crtc->base); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 11e209e..e55b275 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -567,7 +567,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) > struct intel_crtc *intel_crtc = > to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); > const struct drm_display_mode *mode = > - &intel_crtc->config.base.adjusted_mode; > + &intel_crtc->config->base.adjusted_mode; > > htotal = mode->crtc_htotal; > hsync_start = mode->crtc_hsync_start; > @@ -638,7 +638,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; > + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; > enum pipe pipe = crtc->pipe; > int position, vtotal; > > @@ -665,7 +665,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, > struct drm_i915_private *dev_priv = dev->dev_private; > struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode; > + const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; > int position; > int vbl_start, vbl_end, hsync_start, htotal, vtotal; > bool in_vbl = true; > @@ -823,7 +823,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, > return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, > vblank_time, flags, > crtc, > - &to_intel_crtc(crtc)->config.base.adjusted_mode); > + &to_intel_crtc(crtc)->config->base.adjusted_mode); > } > > static bool intel_hpd_irq_event(struct drm_device *dev, > diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c > index fe8c496..e84a798 100644 > --- a/drivers/gpu/drm/i915/intel_audio.c > +++ b/drivers/gpu/drm/i915/intel_audio.c > @@ -397,7 +397,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder) > { > struct drm_encoder *encoder = &intel_encoder->base; > struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); > - struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; > + struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; > struct drm_connector *connector; > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index e4f6d49..bb55368 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crt *crt = intel_encoder_to_crt(encoder); > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; > + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; > u32 adpa; > > if (INTEL_INFO(dev)->gen >= 5) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 970ca30..c409ccc 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -328,7 +328,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > /* Enable the PCH Receiver FDI PLL */ > rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | > FDI_RX_PLL_ENABLE | > - FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); > + FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); > I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); > POSTING_READ(_FDI_RXA_CTL); > udelay(220); > @@ -338,8 +338,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); > > /* Configure Port Clock Select */ > - I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); > - WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); > + I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); > + WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); > > /* Start the training iterating through available voltages and emphasis, > * testing each value twice. */ > @@ -357,7 +357,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > * port reversal bit */ > I915_WRITE(DDI_BUF_CTL(PORT_E), > DDI_BUF_CTL_ENABLE | > - ((intel_crtc->config.fdi_lanes - 1) << 1) | > + ((intel_crtc->config->fdi_lanes - 1) << 1) | > DDI_BUF_TRANS_SELECT(i / 2)); > POSTING_READ(DDI_BUF_CTL(PORT_E)); > > @@ -1186,13 +1186,13 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) > struct drm_i915_private *dev_priv = crtc->dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > int type = intel_encoder->type; > uint32_t temp; > > if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { > temp = TRANS_MSA_SYNC_CLK; > - switch (intel_crtc->config.pipe_bpp) { > + switch (intel_crtc->config->pipe_bpp) { > case 18: > temp |= TRANS_MSA_6_BPC; > break; > @@ -1217,7 +1217,7 @@ void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > uint32_t temp; > temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); > if (state == true) > @@ -1235,7 +1235,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > enum pipe pipe = intel_crtc->pipe; > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > enum port port = intel_ddi_get_encoder_port(intel_encoder); > int type = intel_encoder->type; > uint32_t temp; > @@ -1244,7 +1244,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) > temp = TRANS_DDI_FUNC_ENABLE; > temp |= TRANS_DDI_SELECT_PORT(port); > > - switch (intel_crtc->config.pipe_bpp) { > + switch (intel_crtc->config->pipe_bpp) { > case 18: > temp |= TRANS_DDI_BPC_6; > break; > @@ -1261,9 +1261,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) > BUG(); > } > > - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) > + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) > temp |= TRANS_DDI_PVSYNC; > - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) > + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) > temp |= TRANS_DDI_PHSYNC; > > if (cpu_transcoder == TRANSCODER_EDP) { > @@ -1274,8 +1274,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) > * using motion blur mitigation (which we don't > * support). */ > if (IS_HASWELL(dev) && > - (intel_crtc->config.pch_pfit.enabled || > - intel_crtc->config.pch_pfit.force_thru)) > + (intel_crtc->config->pch_pfit.enabled || > + intel_crtc->config->pch_pfit.force_thru)) > temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; > else > temp |= TRANS_DDI_EDP_INPUT_A_ON; > @@ -1293,14 +1293,14 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) > } > > if (type == INTEL_OUTPUT_HDMI) { > - if (intel_crtc->config.has_hdmi_sink) > + if (intel_crtc->config->has_hdmi_sink) > temp |= TRANS_DDI_MODE_SELECT_HDMI; > else > temp |= TRANS_DDI_MODE_SELECT_DVI; > > } else if (type == INTEL_OUTPUT_ANALOG) { > temp |= TRANS_DDI_MODE_SELECT_FDI; > - temp |= (intel_crtc->config.fdi_lanes - 1) << 1; > + temp |= (intel_crtc->config->fdi_lanes - 1) << 1; > > } else if (type == INTEL_OUTPUT_DISPLAYPORT || > type == INTEL_OUTPUT_EDP) { > @@ -1450,7 +1450,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) > struct drm_i915_private *dev_priv = crtc->dev->dev_private; > struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); > enum port port = intel_ddi_get_encoder_port(intel_encoder); > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > > if (cpu_transcoder != TRANSCODER_EDP) > I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), > @@ -1460,7 +1460,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) > void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) > { > struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > > if (cpu_transcoder != TRANSCODER_EDP) > I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), > @@ -1482,7 +1482,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > } > > if (IS_SKYLAKE(dev)) { > - uint32_t dpll = crtc->config.ddi_pll_sel; > + uint32_t dpll = crtc->config->ddi_pll_sel; > uint32_t val; > > /* > @@ -1497,7 +1497,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | > DPLL_CTRL1_SSC(dpll) | > DPLL_CRTL1_LINK_RATE_MASK(dpll)); > - val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6); > + val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); > > I915_WRITE(DPLL_CTRL1, val); > POSTING_READ(DPLL_CTRL1); > @@ -1514,8 +1514,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > I915_WRITE(DPLL_CTRL2, val); > > } else { > - WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); > - I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); > + WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); > + I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); > } > > if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { > @@ -1532,8 +1532,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); > > intel_hdmi->set_infoframes(encoder, > - crtc->config.has_hdmi_sink, > - &crtc->config.base.adjusted_mode); > + crtc->config->has_hdmi_sink, > + &crtc->config->base.adjusted_mode); > } > } > > @@ -1607,7 +1607,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) > intel_psr_enable(intel_dp); > } > > - if (intel_crtc->config.has_audio) { > + if (intel_crtc->config->has_audio) { > intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); > intel_audio_codec_enable(intel_encoder); > } > @@ -1622,7 +1622,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (intel_crtc->config.has_audio) { > + if (intel_crtc->config->has_audio) { > intel_audio_codec_disable(intel_encoder); > intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); > } > @@ -2031,7 +2031,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > struct intel_hdmi *intel_hdmi; > u32 temp, flags = 0; > struct drm_device *dev = dev_priv->dev; > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a032a1d..462f22a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -895,7 +895,7 @@ bool intel_crtc_active(struct drm_crtc *crtc) > * properly reconstruct framebuffers. > */ > return intel_crtc->active && crtc->primary->fb && > - intel_crtc->config.base.adjusted_mode.crtc_clock; > + intel_crtc->config->base.adjusted_mode.crtc_clock; > } > > enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, > @@ -904,7 +904,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, > struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > > - return intel_crtc->config.cpu_transcoder; > + return intel_crtc->config->cpu_transcoder; > } > > static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) > @@ -946,7 +946,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; > enum pipe pipe = crtc->pipe; > > if (INTEL_INFO(dev)->gen >= 4) { > @@ -1052,10 +1052,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc) > { > struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; > > - if (crtc->config.shared_dpll < 0) > + if (crtc->config->shared_dpll < 0) > return NULL; > > - return &dev_priv->shared_dplls[crtc->config.shared_dpll]; > + return &dev_priv->shared_dplls[crtc->config->shared_dpll]; > } > > /* For ILK+ */ > @@ -1599,7 +1599,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > int reg = DPLL(crtc->pipe); > - u32 dpll = crtc->config.dpll_hw_state.dpll; > + u32 dpll = crtc->config->dpll_hw_state.dpll; > > assert_pipe_disabled(dev_priv, crtc->pipe); > > @@ -1629,7 +1629,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > > if (INTEL_INFO(dev)->gen >= 4) { > I915_WRITE(DPLL_MD(crtc->pipe), > - crtc->config.dpll_hw_state.dpll_md); > + crtc->config->dpll_hw_state.dpll_md); > } else { > /* The pixel multiplier can only be updated once the > * DPLL is enabled and the clocks are stable. > @@ -2034,7 +2034,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > else > assert_pll_enabled(dev_priv, pipe); > else { > - if (crtc->config.has_pch_encoder) { > + if (crtc->config->has_pch_encoder) { > /* if driving the PCH, we need FDI enabled */ > assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); > assert_fdi_tx_pll_enabled(dev_priv, > @@ -2068,7 +2068,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > static void intel_disable_pipe(struct intel_crtc *crtc) > { > struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; > - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; > enum pipe pipe = crtc->pipe; > int reg; > u32 val; > @@ -2090,7 +2090,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) > * Double wide has implications for planes > * so best keep it disabled when not needed. > */ > - if (crtc->config.double_wide) > + if (crtc->config->double_wide) > val &= ~PIPECONF_DOUBLE_WIDE; > > /* Don't disable pipe or pipe PLLs if needed */ > @@ -2468,13 +2468,13 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, > * which should always be the user's requested size. > */ > I915_WRITE(DSPSIZE(plane), > - ((intel_crtc->config.pipe_src_h - 1) << 16) | > - (intel_crtc->config.pipe_src_w - 1)); > + ((intel_crtc->config->pipe_src_h - 1) << 16) | > + (intel_crtc->config->pipe_src_w - 1)); > I915_WRITE(DSPPOS(plane), 0); > } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { > I915_WRITE(PRIMSIZE(plane), > - ((intel_crtc->config.pipe_src_h - 1) << 16) | > - (intel_crtc->config.pipe_src_w - 1)); > + ((intel_crtc->config->pipe_src_h - 1) << 16) | > + (intel_crtc->config->pipe_src_w - 1)); > I915_WRITE(PRIMPOS(plane), 0); > I915_WRITE(PRIMCNSTALPHA(plane), 0); > } > @@ -2532,14 +2532,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, > if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { > dspcntr |= DISPPLANE_ROTATE_180; > > - x += (intel_crtc->config.pipe_src_w - 1); > - y += (intel_crtc->config.pipe_src_h - 1); > + x += (intel_crtc->config->pipe_src_w - 1); > + y += (intel_crtc->config->pipe_src_h - 1); > > /* Finding the last pixel of the last line of the display > data and adding to linear_offset*/ > linear_offset += > - (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + > - (intel_crtc->config.pipe_src_w - 1) * pixel_size; > + (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + > + (intel_crtc->config->pipe_src_w - 1) * pixel_size; > } > > I915_WRITE(reg, dspcntr); > @@ -2635,14 +2635,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, > dspcntr |= DISPPLANE_ROTATE_180; > > if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { > - x += (intel_crtc->config.pipe_src_w - 1); > - y += (intel_crtc->config.pipe_src_h - 1); > + x += (intel_crtc->config->pipe_src_w - 1); > + y += (intel_crtc->config->pipe_src_h - 1); > > /* Finding the last pixel of the last line of the display > data and adding to linear_offset*/ > linear_offset += > - (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + > - (intel_crtc->config.pipe_src_w - 1) * pixel_size; > + (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + > + (intel_crtc->config->pipe_src_w - 1) * pixel_size; > } > } > > @@ -2741,8 +2741,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, > I915_WRITE(PLANE_POS(pipe, 0), 0); > I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); > I915_WRITE(PLANE_SIZE(pipe, 0), > - (intel_crtc->config.pipe_src_h - 1) << 16 | > - (intel_crtc->config.pipe_src_w - 1)); > + (intel_crtc->config->pipe_src_h - 1) << 16 | > + (intel_crtc->config->pipe_src_w - 1)); > I915_WRITE(PLANE_STRIDE(pipe, 0), stride); > I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); > > @@ -2938,20 +2938,20 @@ static void intel_update_pipe_size(struct intel_crtc *crtc) > * then update the pipesrc and pfit state, even on the flip path. > */ > > - adjusted_mode = &crtc->config.base.adjusted_mode; > + adjusted_mode = &crtc->config->base.adjusted_mode; > > I915_WRITE(PIPESRC(crtc->pipe), > ((adjusted_mode->crtc_hdisplay - 1) << 16) | > (adjusted_mode->crtc_vdisplay - 1)); > - if (!crtc->config.pch_pfit.enabled && > + if (!crtc->config->pch_pfit.enabled && > (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || > intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { > I915_WRITE(PF_CTL(crtc->pipe), 0); > I915_WRITE(PF_WIN_POS(crtc->pipe), 0); > I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); > } > - crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; > - crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; > + crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; > + crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; > } > > static void intel_fdi_normal_train(struct drm_crtc *crtc) > @@ -2998,7 +2998,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) > static bool pipe_has_enabled_pch(struct intel_crtc *crtc) > { > return crtc->base.enabled && crtc->active && > - crtc->config.has_pch_encoder; > + crtc->config->has_pch_encoder; > } > > static void ivb_modeset_global_resources(struct drm_device *dev) > @@ -3053,7 +3053,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) > reg = FDI_TX_CTL(pipe); > temp = I915_READ(reg); > temp &= ~FDI_DP_PORT_WIDTH_MASK; > - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); > + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); > temp &= ~FDI_LINK_TRAIN_NONE; > temp |= FDI_LINK_TRAIN_PATTERN_1; > I915_WRITE(reg, temp | FDI_TX_ENABLE); > @@ -3151,7 +3151,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) > reg = FDI_TX_CTL(pipe); > temp = I915_READ(reg); > temp &= ~FDI_DP_PORT_WIDTH_MASK; > - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); > + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); > temp &= ~FDI_LINK_TRAIN_NONE; > temp |= FDI_LINK_TRAIN_PATTERN_1; > temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; > @@ -3302,7 +3302,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) > reg = FDI_TX_CTL(pipe); > temp = I915_READ(reg); > temp &= ~FDI_DP_PORT_WIDTH_MASK; > - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); > + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); > temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; > temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; > temp |= snb_b_fdi_train_param[j/2]; > @@ -3390,7 +3390,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) > reg = FDI_RX_CTL(pipe); > temp = I915_READ(reg); > temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); > - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); > + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); > temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; > I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); > > @@ -3574,7 +3574,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > - int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock; > + int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; > u32 divsel, phaseinc, auxdiv, phasedir = 0; > u32 temp; > > @@ -3663,7 +3663,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; > > I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), > I915_READ(HTOTAL(cpu_transcoder))); > @@ -3709,7 +3709,7 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) > case PIPE_A: > break; > case PIPE_B: > - if (intel_crtc->config.fdi_lanes > 2) > + if (intel_crtc->config->fdi_lanes > 2) > WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); > else > cpt_enable_fdi_bc_bifurcation(dev); > @@ -3761,7 +3761,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) > temp = I915_READ(PCH_DPLL_SEL); > temp |= TRANS_DPLL_ENABLE(pipe); > sel = TRANS_DPLLB_SEL(pipe); > - if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) > + if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) > temp |= sel; > else > temp &= ~sel; > @@ -3784,7 +3784,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) > intel_fdi_normal_train(crtc); > > /* For PCH DP, enable TRANS_DP_CTL */ > - if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) { > + if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { > u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; > reg = TRANS_DP_CTL(pipe); > temp = I915_READ(reg); > @@ -3825,7 +3825,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc) > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > > assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); > > @@ -3855,7 +3855,7 @@ void intel_put_shared_dpll(struct intel_crtc *crtc) > WARN_ON(pll->active); > } > > - crtc->config.shared_dpll = DPLL_ID_PRIVATE; > + crtc->config->shared_dpll = DPLL_ID_PRIVATE; > } > > struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, > @@ -4009,10 +4009,10 @@ static void skylake_pfit_enable(struct intel_crtc *crtc) > struct drm_i915_private *dev_priv = dev->dev_private; > int pipe = crtc->pipe; > > - if (crtc->config.pch_pfit.enabled) { > + if (crtc->config->pch_pfit.enabled) { > I915_WRITE(PS_CTL(pipe), PS_ENABLE); > - I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos); > - I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size); > + I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); > + I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); > } > } > > @@ -4022,7 +4022,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc) > struct drm_i915_private *dev_priv = dev->dev_private; > int pipe = crtc->pipe; > > - if (crtc->config.pch_pfit.enabled) { > + if (crtc->config->pch_pfit.enabled) { > /* Force use of hard-coded filter coefficients > * as some pre-programmed values are broken, > * e.g. x201. > @@ -4032,8 +4032,8 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc) > PF_PIPE_SEL_IVB(pipe)); > else > I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); > - I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); > - I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); > + I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); > + I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); > } > } > > @@ -4070,7 +4070,7 @@ void hsw_enable_ips(struct intel_crtc *crtc) > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (!crtc->config.ips_enabled) > + if (!crtc->config->ips_enabled) > return; > > /* We can only enable IPS after we enable a plane and wait for a vblank */ > @@ -4103,7 +4103,7 @@ void hsw_disable_ips(struct intel_crtc *crtc) > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (!crtc->config.ips_enabled) > + if (!crtc->config->ips_enabled) > return; > > assert_plane_enabled(dev_priv, crtc->plane); > @@ -4152,7 +4152,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) > /* Workaround : Do not read or write the pipe palette/gamma data while > * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. > */ > - if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && > + if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && > ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == > GAMMA_MODE_MODE_SPLIT)) { > hsw_disable_ips(intel_crtc); > @@ -4254,17 +4254,17 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) > if (intel_crtc->active) > return; > > - if (intel_crtc->config.has_pch_encoder) > + if (intel_crtc->config->has_pch_encoder) > intel_prepare_shared_dpll(intel_crtc); > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config->has_dp_encoder) > intel_dp_set_m_n(intel_crtc); > > intel_set_pipe_timings(intel_crtc); > > - if (intel_crtc->config.has_pch_encoder) { > + if (intel_crtc->config->has_pch_encoder) { > intel_cpu_transcoder_set_m_n(intel_crtc, > - &intel_crtc->config.fdi_m_n, NULL); > + &intel_crtc->config->fdi_m_n, NULL); > } > > ironlake_set_pipeconf(crtc); > @@ -4278,7 +4278,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) > if (encoder->pre_enable) > encoder->pre_enable(encoder); > > - if (intel_crtc->config.has_pch_encoder) { > + if (intel_crtc->config->has_pch_encoder) { > /* Note: FDI PLL enabling _must_ be done before we enable the > * cpu pipes, hence this is separate from all the other fdi/pch > * enabling. */ > @@ -4299,7 +4299,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) > intel_update_watermarks(crtc); > intel_enable_pipe(intel_crtc); > > - if (intel_crtc->config.has_pch_encoder) > + if (intel_crtc->config->has_pch_encoder) > ironlake_pch_enable(crtc); > > for_each_encoder_on_crtc(dev, crtc, encoder) > @@ -4365,19 +4365,19 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > if (intel_crtc_to_shared_dpll(intel_crtc)) > intel_enable_shared_dpll(intel_crtc); > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config->has_dp_encoder) > intel_dp_set_m_n(intel_crtc); > > intel_set_pipe_timings(intel_crtc); > > - if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { > - I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder), > - intel_crtc->config.pixel_multiplier - 1); > + if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { > + I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), > + intel_crtc->config->pixel_multiplier - 1); > } > > - if (intel_crtc->config.has_pch_encoder) { > + if (intel_crtc->config->has_pch_encoder) { > intel_cpu_transcoder_set_m_n(intel_crtc, > - &intel_crtc->config.fdi_m_n, NULL); > + &intel_crtc->config->fdi_m_n, NULL); > } > > haswell_set_pipeconf(crtc); > @@ -4391,7 +4391,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > if (encoder->pre_enable) > encoder->pre_enable(encoder); > > - if (intel_crtc->config.has_pch_encoder) { > + if (intel_crtc->config->has_pch_encoder) { > intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > true); > dev_priv->display.fdi_link_train(crtc); > @@ -4416,10 +4416,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > intel_update_watermarks(crtc); > intel_enable_pipe(intel_crtc); > > - if (intel_crtc->config.has_pch_encoder) > + if (intel_crtc->config->has_pch_encoder) > lpt_pch_enable(crtc); > > - if (intel_crtc->config.dp_encoder_is_mst) > + if (intel_crtc->config->dp_encoder_is_mst) > intel_ddi_set_vc_payload_alloc(crtc, true); > > for_each_encoder_on_crtc(dev, crtc, encoder) { > @@ -4444,7 +4444,7 @@ static void skylake_pfit_disable(struct intel_crtc *crtc) > > /* To avoid upsetting the power well on haswell only disable the pfit if > * it's in use. The hw state code will make sure we get this right. */ > - if (crtc->config.pch_pfit.enabled) { > + if (crtc->config->pch_pfit.enabled) { > I915_WRITE(PS_CTL(pipe), 0); > I915_WRITE(PS_WIN_POS(pipe), 0); > I915_WRITE(PS_WIN_SZ(pipe), 0); > @@ -4459,7 +4459,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc) > > /* To avoid upsetting the power well on haswell only disable the pfit if > * it's in use. The hw state code will make sure we get this right. */ > - if (crtc->config.pch_pfit.enabled) { > + if (crtc->config->pch_pfit.enabled) { > I915_WRITE(PF_CTL(pipe), 0); > I915_WRITE(PF_WIN_POS(pipe), 0); > I915_WRITE(PF_WIN_SZ(pipe), 0); > @@ -4486,7 +4486,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) > for_each_encoder_on_crtc(dev, crtc, encoder) > encoder->disable(encoder); > > - if (intel_crtc->config.has_pch_encoder) > + if (intel_crtc->config->has_pch_encoder) > intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); > > intel_disable_pipe(intel_crtc); > @@ -4497,7 +4497,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) > if (encoder->post_disable) > encoder->post_disable(encoder); > > - if (intel_crtc->config.has_pch_encoder) { > + if (intel_crtc->config->has_pch_encoder) { > ironlake_fdi_disable(crtc); > > ironlake_disable_pch_transcoder(dev_priv, pipe); > @@ -4537,7 +4537,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > struct intel_encoder *encoder; > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > > if (!intel_crtc->active) > return; > @@ -4552,12 +4552,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) > encoder->disable(encoder); > } > > - if (intel_crtc->config.has_pch_encoder) > + if (intel_crtc->config->has_pch_encoder) > intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > false); > intel_disable_pipe(intel_crtc); > > - if (intel_crtc->config.dp_encoder_is_mst) > + if (intel_crtc->config->dp_encoder_is_mst) > intel_ddi_set_vc_payload_alloc(crtc, false); > > intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); > @@ -4569,7 +4569,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) > > intel_ddi_disable_pipe_clock(intel_crtc); > > - if (intel_crtc->config.has_pch_encoder) { > + if (intel_crtc->config->has_pch_encoder) { > lpt_disable_pch_transcoder(dev_priv); > intel_ddi_fdi_disable(crtc); > } > @@ -4600,7 +4600,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > - struct intel_crtc_state *pipe_config = &crtc->config; > + struct intel_crtc_state *pipe_config = crtc->config; > > if (!pipe_config->gmch_pfit.control) > return; > @@ -4681,8 +4681,8 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) > > mask = BIT(POWER_DOMAIN_PIPE(pipe)); > mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); > - if (intel_crtc->config.pch_pfit.enabled || > - intel_crtc->config.pch_pfit.force_thru) > + if (intel_crtc->config->pch_pfit.enabled || > + intel_crtc->config->pch_pfit.force_thru) > mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); > > for_each_encoder_on_crtc(dev, crtc, intel_encoder) > @@ -4986,12 +4986,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) > > if (!is_dsi) { > if (IS_CHERRYVIEW(dev)) > - chv_prepare_pll(intel_crtc, &intel_crtc->config); > + chv_prepare_pll(intel_crtc, intel_crtc->config); > else > - vlv_prepare_pll(intel_crtc, &intel_crtc->config); > + vlv_prepare_pll(intel_crtc, intel_crtc->config); > } > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config->has_dp_encoder) > intel_dp_set_m_n(intel_crtc); > > intel_set_pipe_timings(intel_crtc); > @@ -5015,9 +5015,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) > > if (!is_dsi) { > if (IS_CHERRYVIEW(dev)) > - chv_enable_pll(intel_crtc, &intel_crtc->config); > + chv_enable_pll(intel_crtc, intel_crtc->config); > else > - vlv_enable_pll(intel_crtc, &intel_crtc->config); > + vlv_enable_pll(intel_crtc, intel_crtc->config); > } > > for_each_encoder_on_crtc(dev, crtc, encoder) > @@ -5048,8 +5048,8 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc) > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); > - I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); > + I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); > + I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); > } > > static void i9xx_crtc_enable(struct drm_crtc *crtc) > @@ -5067,7 +5067,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) > > i9xx_set_pll_dividers(intel_crtc); > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config->has_dp_encoder) > intel_dp_set_m_n(intel_crtc); > > intel_set_pipe_timings(intel_crtc); > @@ -5119,7 +5119,7 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc) > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (!crtc->config.gmch_pfit.control) > + if (!crtc->config->gmch_pfit.control) > return; > > assert_pipe_disabled(dev_priv, crtc->pipe); > @@ -5418,7 +5418,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, > return true; > case PIPE_C: > if (!pipe_has_enabled_pch(pipe_B_crtc) || > - pipe_B_crtc->config.fdi_lanes <= 2) { > + pipe_B_crtc->config->fdi_lanes <= 2) { > if (pipe_config->fdi_lanes > 2) { > DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", > pipe_name(pipe), pipe_config->fdi_lanes); > @@ -5816,7 +5816,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > int pipe = crtc->pipe; > - enum transcoder transcoder = crtc->config.cpu_transcoder; > + enum transcoder transcoder = crtc->config->cpu_transcoder; > > if (INTEL_INFO(dev)->gen >= 5) { > I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); > @@ -5828,7 +5828,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > * registers are not unnecessarily accessed). > */ > if (m2_n2 && INTEL_INFO(dev)->gen < 8 && > - crtc->config.has_drrs) { > + crtc->config->has_drrs) { > I915_WRITE(PIPE_DATA_M2(transcoder), > TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); > I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); > @@ -5845,11 +5845,11 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > > void intel_dp_set_m_n(struct intel_crtc *crtc) > { > - if (crtc->config.has_pch_encoder) > - intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); > + if (crtc->config->has_pch_encoder) > + intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); > else > - intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, > - &crtc->config.dp_m2_n2); > + intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n, > + &crtc->config->dp_m2_n2); > } > > static void vlv_update_pll(struct intel_crtc *crtc, > @@ -6217,9 +6217,9 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) > struct drm_device *dev = intel_crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > enum pipe pipe = intel_crtc->pipe; > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > struct drm_display_mode *adjusted_mode = > - &intel_crtc->config.base.adjusted_mode; > + &intel_crtc->config->base.adjusted_mode; > uint32_t crtc_vtotal, crtc_vblank_end; > int vsyncshift = 0; > > @@ -6277,8 +6277,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) > * always be the user's requested size. > */ > I915_WRITE(PIPESRC(pipe), > - ((intel_crtc->config.pipe_src_w - 1) << 16) | > - (intel_crtc->config.pipe_src_h - 1)); > + ((intel_crtc->config->pipe_src_w - 1) << 16) | > + (intel_crtc->config->pipe_src_h - 1)); > } > > static void intel_get_pipe_timings(struct intel_crtc *crtc, > @@ -6354,17 +6354,17 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) > (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) > pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; > > - if (intel_crtc->config.double_wide) > + if (intel_crtc->config->double_wide) > pipeconf |= PIPECONF_DOUBLE_WIDE; > > /* only g4x and later have fancy bpc/dither controls */ > if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { > /* Bspec claims that we can't use dithering for 30bpp pipes. */ > - if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) > + if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) > pipeconf |= PIPECONF_DITHER_EN | > PIPECONF_DITHER_TYPE_SP; > > - switch (intel_crtc->config.pipe_bpp) { > + switch (intel_crtc->config->pipe_bpp) { > case 18: > pipeconf |= PIPECONF_6BPC; > break; > @@ -6389,7 +6389,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) > } > } > > - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { > + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { > if (INTEL_INFO(dev)->gen < 4 || > intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) > pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; > @@ -6398,7 +6398,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) > } else > pipeconf |= PIPECONF_PROGRESSIVE; > > - if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) > + if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) > pipeconf |= PIPECONF_COLOR_RANGE_SELECT; > > I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); > @@ -7126,7 +7126,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc) > > val = 0; > > - switch (intel_crtc->config.pipe_bpp) { > + switch (intel_crtc->config->pipe_bpp) { > case 18: > val |= PIPECONF_6BPC; > break; > @@ -7144,15 +7144,15 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc) > BUG(); > } > > - if (intel_crtc->config.dither) > + if (intel_crtc->config->dither) > val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); > > - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) > + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) > val |= PIPECONF_INTERLACED_ILK; > else > val |= PIPECONF_PROGRESSIVE; > > - if (intel_crtc->config.limited_color_range) > + if (intel_crtc->config->limited_color_range) > val |= PIPECONF_COLOR_RANGE_SELECT; > > I915_WRITE(PIPECONF(pipe), val); > @@ -7181,7 +7181,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) > * consideration. > */ > > - if (intel_crtc->config.limited_color_range) > + if (intel_crtc->config->limited_color_range) > coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ > > /* > @@ -7205,7 +7205,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) > if (INTEL_INFO(dev)->gen > 6) { > uint16_t postoff = 0; > > - if (intel_crtc->config.limited_color_range) > + if (intel_crtc->config->limited_color_range) > postoff = (16 * (1 << 12) / 255) & 0x1fff; > > I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); > @@ -7216,7 +7216,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) > } else { > uint32_t mode = CSC_MODE_YUV_TO_RGB; > > - if (intel_crtc->config.limited_color_range) > + if (intel_crtc->config->limited_color_range) > mode |= CSC_BLACK_SCREEN_OFFSET; > > I915_WRITE(PIPE_CSC_MODE(pipe), mode); > @@ -7229,15 +7229,15 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > enum pipe pipe = intel_crtc->pipe; > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > uint32_t val; > > val = 0; > > - if (IS_HASWELL(dev) && intel_crtc->config.dither) > + if (IS_HASWELL(dev) && intel_crtc->config->dither) > val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); > > - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) > + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) > val |= PIPECONF_INTERLACED_ILK; > else > val |= PIPECONF_PROGRESSIVE; > @@ -7251,7 +7251,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) > if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { > val = 0; > > - switch (intel_crtc->config.pipe_bpp) { > + switch (intel_crtc->config->pipe_bpp) { > case 18: > val |= PIPEMISC_DITHER_6_BPC; > break; > @@ -7269,7 +7269,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) > BUG(); > } > > - if (intel_crtc->config.dither) > + if (intel_crtc->config->dither) > val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; > > I915_WRITE(PIPEMISC(pipe), val); > @@ -7530,7 +7530,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, > * registers are not unnecessarily read). > */ > if (m2_n2 && INTEL_INFO(dev)->gen < 8 && > - crtc->config.has_drrs) { > + crtc->config->has_drrs) { > m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); > m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); > m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) > @@ -8282,10 +8282,10 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, > if (on) > base = intel_crtc->cursor_addr; > > - if (x >= intel_crtc->config.pipe_src_w) > + if (x >= intel_crtc->config->pipe_src_w) > base = 0; > > - if (y >= intel_crtc->config.pipe_src_h) > + if (y >= intel_crtc->config->pipe_src_h) > base = 0; > > if (x < 0) { > @@ -8812,7 +8812,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, > { > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > struct drm_display_mode *mode; > struct intel_crtc_state pipe_config; > int htot = I915_READ(HTOTAL(cpu_transcoder)); > @@ -10769,11 +10769,11 @@ check_crtc_state(struct drm_device *dev) > "(expected %i, found %i)\n", crtc->active, active); > > if (active && > - !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { > + !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { > WARN(1, "pipe state doesn't match!\n"); > intel_dump_pipe_config(crtc, &pipe_config, > "[hw state]"); > - intel_dump_pipe_config(crtc, &crtc->config, > + intel_dump_pipe_config(crtc, crtc->config, > "[sw state]"); > } > } > @@ -10873,7 +10873,7 @@ static void update_scanline_offset(struct intel_crtc *crtc) > * one to the value. > */ > if (IS_GEN2(dev)) { > - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; > + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; > int vtotal; > > vtotal = mode->crtc_vtotal; > @@ -10921,6 +10921,13 @@ out: > return pipe_config; > } > > +static void intel_crtc_set_state(struct intel_crtc *crtc, > + struct intel_crtc_state *crtc_state) > +{ > + kfree(crtc->config); > + crtc->config = crtc_state; > +} > + > static int __intel_set_mode(struct drm_crtc *crtc, > struct drm_display_mode *mode, > int x, int y, struct drm_framebuffer *fb, > @@ -11000,7 +11007,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, > crtc->mode = *mode; > /* mode_set/enable/disable functions rely on a correct pipe > * config. */ > - to_intel_crtc(crtc)->config = *pipe_config; > + intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); > > /* > * Calculate and store various constants which > @@ -11044,7 +11051,6 @@ done: > if (ret && crtc->enabled) > crtc->mode = *saved_mode; > > - kfree(pipe_config); > kfree(saved_mode); > return ret; > } > @@ -11461,7 +11467,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set) > goto fail; > } else if (pipe_config) { > if (pipe_config->has_audio != > - to_intel_crtc(set->crtc)->config.has_audio) > + to_intel_crtc(set->crtc)->config->has_audio) > config->mode_changed = true; > > /* > @@ -11886,8 +11892,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, > > state.clip.x1 = 0; > state.clip.y1 = 0; > - state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; > - state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; > + state.clip.x2 = intel_crtc->active ? intel_crtc->config->pipe_src_w : 0; > + state.clip.y2 = intel_crtc->active ? intel_crtc->config->pipe_src_h : 0; > > state.orig_src = state.src; > state.orig_dst = state.dst; > @@ -12169,6 +12175,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > { > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc; > + struct intel_crtc_state *crtc_state = NULL; > struct drm_plane *primary = NULL; > struct drm_plane *cursor = NULL; > int i, ret; > @@ -12177,6 +12184,11 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > if (intel_crtc == NULL) > return; > > + crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); > + if (!crtc_state) > + goto fail; > + intel_crtc_set_state(intel_crtc, crtc_state); > + > primary = intel_primary_plane_create(dev, pipe); > if (!primary) > goto fail; > @@ -12229,6 +12241,7 @@ fail: > drm_plane_cleanup(primary); > if (cursor) > drm_plane_cleanup(cursor); > + kfree(crtc_state); > kfree(intel_crtc); > } > > @@ -13131,7 +13144,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) > u32 reg; > > /* Clear any frame start delays used for debugging left by the BIOS */ > - reg = PIPECONF(crtc->config.cpu_transcoder); > + reg = PIPECONF(crtc->config->cpu_transcoder); > I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); > > /* restore vblank interrupts to correct state */ > @@ -13335,12 +13348,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) > int i; > > for_each_intel_crtc(dev, crtc) { > - memset(&crtc->config, 0, sizeof(crtc->config)); > + memset(crtc->config, 0, sizeof(*crtc->config)); > > - crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; > + crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; > > crtc->active = dev_priv->display.get_pipe_config(crtc, > - &crtc->config); > + crtc->config); > > crtc->base.enabled = crtc->active; > crtc->primary_enabled = primary_get_hw_state(crtc); > @@ -13377,7 +13390,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) > if (encoder->get_hw_state(encoder, &pipe)) { > crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); > encoder->base.crtc = &crtc->base; > - encoder->get_config(encoder, &crtc->config); > + encoder->get_config(encoder, crtc->config); > } else { > encoder->base.crtc = NULL; > } > @@ -13427,7 +13440,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, > */ > for_each_intel_crtc(dev, crtc) { > if (crtc->active && i915.fastboot) { > - intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); > + intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); > DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", > crtc->base.base.id); > drm_mode_debug_printmodeline(&crtc->base.mode); > @@ -13442,7 +13455,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, > for_each_pipe(dev_priv, pipe) { > crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); > intel_sanitize_crtc(crtc); > - intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); > + intel_dump_pipe_config(crtc, crtc->config, "[setup_hw_state]"); > } > > for (i = 0; i < dev_priv->num_shared_dpll; i++) { > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 67cdbe8..d6f0d90 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1295,11 +1295,11 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) > struct drm_i915_private *dev_priv = dev->dev_private; > u32 dpa_ctl; > > - DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); > + DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config->port_clock); > dpa_ctl = I915_READ(DP_A); > dpa_ctl &= ~DP_PLL_FREQ_MASK; > > - if (crtc->config.port_clock == 162000) { > + if (crtc->config->port_clock == 162000) { > /* For a long time we've carried around a ILK-DevA w/a for the > * 160MHz clock. If we're really unlucky, it's still required. > */ > @@ -1324,7 +1324,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder) > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > enum port port = dp_to_dig_port(intel_dp)->port; > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; > + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; > > /* > * There are four kinds of DP registers: > @@ -1352,7 +1352,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder) > intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; > intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); > > - if (crtc->config.has_audio) > + if (crtc->config->has_audio) > intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; > > /* Split out the IBX/CPU vs CPT settings */ > @@ -2102,7 +2102,7 @@ static void intel_disable_dp(struct intel_encoder *encoder) > struct drm_device *dev = encoder->base.dev; > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > > - if (crtc->config.has_audio) > + if (crtc->config->has_audio) > intel_audio_codec_disable(encoder); > > if (HAS_PSR(dev) && !HAS_DDI(dev)) > @@ -2312,7 +2312,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) > intel_dp_complete_link_train(intel_dp); > intel_dp_stop_link_train(intel_dp); > > - if (crtc->config.has_audio) { > + if (crtc->config->has_audio) { > DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", > pipe_name(crtc->pipe)); > intel_audio_codec_enable(encoder); > @@ -4780,7 +4780,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > return; > } > > - config = &intel_crtc->config; > + config = intel_crtc->config; > > if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { > DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); > @@ -4802,7 +4802,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > } > > if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { > - reg = PIPECONF(intel_crtc->config.cpu_transcoder); > + reg = PIPECONF(intel_crtc->config->cpu_transcoder); > val = I915_READ(reg); > if (index > DRRS_HIGH_RR) { > val |= PIPECONF_EDP_RR_MODE_SWITCH; > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c > index 257aca1..28b6ee4 100644 > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > @@ -157,7 +157,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) > if (intel_dp->active_mst_links == 0) { > enum port port = intel_ddi_get_encoder_port(encoder); > > - I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config.ddi_pll_sel); > + I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config->ddi_pll_sel); > > intel_ddi_init_dp_buf_reg(&intel_dig_port->base); > > @@ -170,7 +170,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) > } > > ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, > - intel_mst->port, intel_crtc->config.pbn, &slots); > + intel_mst->port, intel_crtc->config->pbn, > + &slots); > if (ret == false) { > DRM_ERROR("failed to allocate vcpi\n"); > return; > @@ -223,7 +224,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > struct drm_device *dev = encoder->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; > + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; > u32 temp, flags = 0; > > pipe_config->has_dp_encoder = true; > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 175b853..01d6fa1 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -439,7 +439,7 @@ struct intel_crtc { > uint32_t cursor_base; > > struct intel_plane_config plane_config; > - struct intel_crtc_state config; > + struct intel_crtc_state *config; > bool new_enabled; > > /* reset counter value when the last flip was submitted */ > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 25291e9..5d9ec7b 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -232,7 +232,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) > I915_WRITE(DPLL(pipe), tmp); > > /* update the hw state for DPLL */ > - intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | > + intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | > DPLL_REFA_CLK_ENABLE_VLV; > > tmp = I915_READ(DSPCLK_GATE_D); > @@ -494,7 +494,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > enum port port; > - unsigned int bpp = intel_crtc->config.pipe_bpp; > + unsigned int bpp = intel_crtc->config->pipe_bpp; > unsigned int lane_count = intel_dsi->lane_count; > > u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; > @@ -549,9 +549,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > struct drm_display_mode *adjusted_mode = > - &intel_crtc->config.base.adjusted_mode; > + &intel_crtc->config->base.adjusted_mode; > enum port port; > - unsigned int bpp = intel_crtc->config.pipe_bpp; > + unsigned int bpp = intel_crtc->config->pipe_bpp; > u32 val, tmp; > u16 mode_hdisplay; > > diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c > index 108f058..706ab99 100644 > --- a/drivers/gpu/drm/i915/intel_dvo.c > +++ b/drivers/gpu/drm/i915/intel_dvo.c > @@ -186,8 +186,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder) > u32 temp = I915_READ(dvo_reg); > > intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, > - &crtc->config.base.mode, > - &crtc->config.base.adjusted_mode); > + &crtc->config->base.mode, > + &crtc->config->base.adjusted_mode); > > I915_WRITE(dvo_reg, temp | DVO_ENABLE); > I915_READ(dvo_reg); > @@ -221,7 +221,7 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode) > /* We call connector dpms manually below in case pipe dpms doesn't > * change due to cloning. */ > if (mode == DRM_MODE_DPMS_ON) { > - config = &to_intel_crtc(crtc)->config; > + config = to_intel_crtc(crtc)->config; > > intel_dvo->base.connectors_active = true; > > @@ -295,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder) > struct drm_device *dev = encoder->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; > + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; > struct intel_dvo *intel_dvo = enc_to_dvo(encoder); > int pipe = crtc->pipe; > u32 dvo_val; > diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c > index 1a9a727..f426e7c 100644 > --- a/drivers/gpu/drm/i915/intel_fbdev.c > +++ b/drivers/gpu/drm/i915/intel_fbdev.c > @@ -431,7 +431,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper, > DRM_DEBUG_KMS("looking for current mode on connector %s\n", > connector->name); > intel_mode_from_pipe_config(&encoder->crtc->hwmode, > - &to_intel_crtc(encoder->crtc)->config); > + to_intel_crtc(encoder->crtc)->config); > modes[i] = &encoder->crtc->hwmode; > } > crtcs[i] = new_crtc; > @@ -563,7 +563,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, > * pipe. Note we need to use the selected fb's pitch and bpp > * rather than the current pipe's, since they differ. > */ > - cur_size = intel_crtc->config.base.adjusted_mode.crtc_hdisplay; > + cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay; > cur_size = cur_size * fb->base.bits_per_pixel / 8; > if (fb->base.pitches[0] < cur_size) { > DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n", > @@ -574,13 +574,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, > break; > } > > - cur_size = intel_crtc->config.base.adjusted_mode.crtc_vdisplay; > + cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay; > cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1); > cur_size *= fb->base.pitches[0]; > DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n", > pipe_name(intel_crtc->pipe), > - intel_crtc->config.base.adjusted_mode.crtc_hdisplay, > - intel_crtc->config.base.adjusted_mode.crtc_vdisplay, > + intel_crtc->config->base.adjusted_mode.crtc_hdisplay, > + intel_crtc->config->base.adjusted_mode.crtc_vdisplay, > fb->base.bits_per_pixel, > cur_size); > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 02ff3e2..200a0e7 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -337,13 +337,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); > + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); > u32 data_reg; > int i; > u32 val = I915_READ(ctl_reg); > > data_reg = hsw_infoframe_data_reg(type, > - intel_crtc->config.cpu_transcoder, > + intel_crtc->config->cpu_transcoder, > dev_priv); > if (data_reg == 0) > return; > @@ -371,7 +371,7 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); > + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); > u32 val = I915_READ(ctl_reg); > > return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | > @@ -436,7 +436,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, > } > > if (intel_hdmi->rgb_quant_range_selectable) { > - if (intel_crtc->config.limited_color_range) > + if (intel_crtc->config->limited_color_range) > frame.avi.quantization_range = > HDMI_QUANTIZATION_RANGE_LIMITED; > else > @@ -672,7 +672,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder, > struct drm_i915_private *dev_priv = encoder->dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); > - u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); > + u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); > u32 val = I915_READ(reg); > > assert_hdmi_port_disabled(intel_hdmi); > @@ -700,7 +700,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); > - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; > + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; > u32 hdmi_val; > > hdmi_val = SDVO_ENCODING_HDMI; > @@ -711,12 +711,12 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder) > if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) > hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; > > - if (crtc->config.pipe_bpp > 24) > + if (crtc->config->pipe_bpp > 24) > hdmi_val |= HDMI_COLOR_FORMAT_12bpc; > else > hdmi_val |= SDVO_COLOR_FORMAT_8bpc; > > - if (crtc->config.has_hdmi_sink) > + if (crtc->config->has_hdmi_sink) > hdmi_val |= HDMI_MODE_SELECT_HDMI; > > if (HAS_PCH_CPT(dev)) > @@ -814,7 +814,7 @@ static void intel_enable_hdmi(struct intel_encoder *encoder) > u32 temp; > u32 enable_bits = SDVO_ENABLE; > > - if (intel_crtc->config.has_audio) > + if (intel_crtc->config->has_audio) > enable_bits |= SDVO_AUDIO_ENABLE; > > temp = I915_READ(intel_hdmi->hdmi_reg); > @@ -845,8 +845,8 @@ static void intel_enable_hdmi(struct intel_encoder *encoder) > POSTING_READ(intel_hdmi->hdmi_reg); > } > > - if (intel_crtc->config.has_audio) { > - WARN_ON(!intel_crtc->config.has_hdmi_sink); > + if (intel_crtc->config->has_audio) { > + WARN_ON(!intel_crtc->config->has_hdmi_sink); > DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", > pipe_name(intel_crtc->pipe)); > intel_audio_codec_enable(encoder); > @@ -866,7 +866,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) > u32 temp; > u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; > > - if (crtc->config.has_audio) > + if (crtc->config->has_audio) > intel_audio_codec_disable(encoder); > > temp = I915_READ(intel_hdmi->hdmi_reg); > @@ -1252,12 +1252,12 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder) > struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > struct drm_display_mode *adjusted_mode = > - &intel_crtc->config.base.adjusted_mode; > + &intel_crtc->config->base.adjusted_mode; > > intel_hdmi_prepare(encoder); > > intel_hdmi->set_infoframes(&encoder->base, > - intel_crtc->config.has_hdmi_sink, > + intel_crtc->config->has_hdmi_sink, > adjusted_mode); > } > > @@ -1270,7 +1270,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) > struct intel_crtc *intel_crtc = > to_intel_crtc(encoder->base.crtc); > struct drm_display_mode *adjusted_mode = > - &intel_crtc->config.base.adjusted_mode; > + &intel_crtc->config->base.adjusted_mode; > enum dpio_channel port = vlv_dport_to_channel(dport); > int pipe = intel_crtc->pipe; > u32 val; > @@ -1302,7 +1302,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) > mutex_unlock(&dev_priv->dpio_lock); > > intel_hdmi->set_infoframes(&encoder->base, > - intel_crtc->config.has_hdmi_sink, > + intel_crtc->config->has_hdmi_sink, > adjusted_mode); > > intel_enable_hdmi(encoder); > @@ -1467,7 +1467,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) > struct intel_crtc *intel_crtc = > to_intel_crtc(encoder->base.crtc); > struct drm_display_mode *adjusted_mode = > - &intel_crtc->config.base.adjusted_mode; > + &intel_crtc->config->base.adjusted_mode; > enum dpio_channel ch = vlv_dport_to_channel(dport); > int pipe = intel_crtc->pipe; > int data, i; > @@ -1593,7 +1593,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) > mutex_unlock(&dev_priv->dpio_lock); > > intel_hdmi->set_infoframes(&encoder->base, > - intel_crtc->config.has_hdmi_sink, > + intel_crtc->config->has_hdmi_sink, > adjusted_mode); > > intel_enable_hdmi(encoder); > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c > index 9d174cf..c7c6414 100644 > --- a/drivers/gpu/drm/i915/intel_lvds.c > +++ b/drivers/gpu/drm/i915/intel_lvds.c > @@ -139,7 +139,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > const struct drm_display_mode *adjusted_mode = > - &crtc->config.base.adjusted_mode; > + &crtc->config->base.adjusted_mode; > int pipe = crtc->pipe; > u32 temp; > > @@ -167,7 +167,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) > > /* set the corresponsding LVDS_BORDER bit */ > temp &= ~LVDS_BORDER_ENABLE; > - temp |= crtc->config.gmch_pfit.lvds_border_bits; > + temp |= crtc->config->gmch_pfit.lvds_border_bits; > /* Set the B0-B3 data pairs corresponding to whether we're going to > * set the DPLLs for dual-channel mode or not. > */ > @@ -190,7 +190,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) > if (INTEL_INFO(dev)->gen == 4) { > /* Bspec wording suggests that LVDS port dithering only exists > * for 18bpp panels. */ > - if (crtc->config.dither && crtc->config.pipe_bpp == 18) > + if (crtc->config->dither && crtc->config->pipe_bpp == 18) > temp |= LVDS_ENABLE_DITHER; > else > temp &= ~LVDS_ENABLE_DITHER; > diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c > index 973c9de..f93dfc1 100644 > --- a/drivers/gpu/drm/i915/intel_overlay.c > +++ b/drivers/gpu/drm/i915/intel_overlay.c > @@ -856,7 +856,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, > return -EINVAL; > > /* can't use the overlay with double wide pipe */ > - if (crtc->config.double_wide) > + if (crtc->config->double_wide) > return -EINVAL; > > return 0; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 47b23b7..22e49f4 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -574,7 +574,7 @@ void intel_update_fbc(struct drm_device *dev) > intel_crtc = to_intel_crtc(crtc); > fb = crtc->primary->fb; > obj = intel_fb_obj(fb); > - adjusted_mode = &intel_crtc->config.base.adjusted_mode; > + adjusted_mode = &intel_crtc->config->base.adjusted_mode; > > if (i915.enable_fbc < 0) { > if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) > @@ -604,8 +604,8 @@ void intel_update_fbc(struct drm_device *dev) > max_width = 2048; > max_height = 1536; > } > - if (intel_crtc->config.pipe_src_w > max_width || > - intel_crtc->config.pipe_src_h > max_height) { > + if (intel_crtc->config->pipe_src_w > max_width || > + intel_crtc->config->pipe_src_h > max_height) { > if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) > DRM_DEBUG_KMS("mode too large for compression, disabling\n"); > goto out_disable; > @@ -1157,7 +1157,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) > int pixel_size = crtc->primary->fb->bits_per_pixel / 8; > int clock; > > - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; > + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; > clock = adjusted_mode->crtc_clock; > > /* Display SR */ > @@ -1226,10 +1226,10 @@ static bool g4x_compute_wm0(struct drm_device *dev, > return false; > } > > - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; > + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; > clock = adjusted_mode->crtc_clock; > htotal = adjusted_mode->crtc_htotal; > - hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; > + hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; > pixel_size = crtc->primary->fb->bits_per_pixel / 8; > > /* Use the small buffer method to calculate plane watermark */ > @@ -1313,10 +1313,10 @@ static bool g4x_compute_srwm(struct drm_device *dev, > } > > crtc = intel_get_crtc_for_plane(dev, plane); > - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; > + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; > clock = adjusted_mode->crtc_clock; > htotal = adjusted_mode->crtc_htotal; > - hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; > + hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; > pixel_size = crtc->primary->fb->bits_per_pixel / 8; > > line_time_us = max(htotal * 1000 / clock, 1); > @@ -1347,7 +1347,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc, > { > struct drm_device *dev = crtc->dev; > int entries; > - int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock; > + int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; > > if (WARN(clock == 0, "Pixel clock is zero!\n")) > return false; > @@ -1677,10 +1677,10 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) > /* self-refresh has much higher latency */ > static const int sr_latency_ns = 12000; > const struct drm_display_mode *adjusted_mode = > - &to_intel_crtc(crtc)->config.base.adjusted_mode; > + &to_intel_crtc(crtc)->config->base.adjusted_mode; > int clock = adjusted_mode->crtc_clock; > int htotal = adjusted_mode->crtc_htotal; > - int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; > + int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; > int pixel_size = crtc->primary->fb->bits_per_pixel / 8; > unsigned long line_time_us; > int entries; > @@ -1762,7 +1762,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) > if (IS_GEN2(dev)) > cpp = 4; > > - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; > + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; > planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, > wm_info, fifo_size, cpp, > pessimal_latency_ns); > @@ -1784,7 +1784,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) > if (IS_GEN2(dev)) > cpp = 4; > > - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; > + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; > planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, > wm_info, fifo_size, cpp, > pessimal_latency_ns); > @@ -1823,10 +1823,10 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) > /* self-refresh has much higher latency */ > static const int sr_latency_ns = 6000; > const struct drm_display_mode *adjusted_mode = > - &to_intel_crtc(enabled)->config.base.adjusted_mode; > + &to_intel_crtc(enabled)->config->base.adjusted_mode; > int clock = adjusted_mode->crtc_clock; > int htotal = adjusted_mode->crtc_htotal; > - int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; > + int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; > int pixel_size = enabled->primary->fb->bits_per_pixel / 8; > unsigned long line_time_us; > int entries; > @@ -1879,7 +1879,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc) > if (crtc == NULL) > return; > > - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; > + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; > planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, > &i845_wm_info, > dev_priv->display.get_fifo_size(dev, 0), > @@ -1898,17 +1898,17 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > uint32_t pixel_rate; > > - pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock; > + pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock; > > /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to > * adjust the pixel_rate here. */ > > - if (intel_crtc->config.pch_pfit.enabled) { > + if (intel_crtc->config->pch_pfit.enabled) { > uint64_t pipe_w, pipe_h, pfit_w, pfit_h; > - uint32_t pfit_size = intel_crtc->config.pch_pfit.size; > + uint32_t pfit_size = intel_crtc->config->pch_pfit.size; > > - pipe_w = intel_crtc->config.pipe_src_w; > - pipe_h = intel_crtc->config.pipe_src_h; > + pipe_w = intel_crtc->config->pipe_src_w; > + pipe_h = intel_crtc->config->pipe_src_h; > pfit_w = (pfit_size >> 16) & 0xFFFF; > pfit_h = pfit_size & 0xFFFF; > if (pipe_w < pfit_w) > @@ -2261,7 +2261,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) > { > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode; > + struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; > u32 linetime, ips_linetime; > > if (!intel_crtc_active(crtc)) > @@ -2521,11 +2521,11 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc, > return; > > p->active = true; > - p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal; > + p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; > p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); > p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; > p->cur.bytes_per_pixel = 4; > - p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; > + p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; > p->cur.horiz_pixels = intel_crtc->cursor_width; > /* TODO: for now, assume primary and cursor planes are always enabled. */ > p->pri.enabled = true; > @@ -3265,8 +3265,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, > > p->active = intel_crtc_active(crtc); > if (p->active) { > - p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal; > - p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config); > + p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; > + p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); > > /* > * For now, assume primary and cursor planes are always enabled. > @@ -3274,8 +3274,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, > p->plane[0].enabled = true; > p->plane[0].bytes_per_pixel = > crtc->primary->fb->bits_per_pixel / 8; > - p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w; > - p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h; > + p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; > + p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; > > p->cursor.enabled = true; > p->cursor.bytes_per_pixel = 4; > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index b8713e4..494b132 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -79,8 +79,8 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp, > struct drm_device *dev = dig_port->base.base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); > - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); > - u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); > + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder); > + u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder); > uint32_t *data = (uint32_t *) vsc_psr; > unsigned int i; > > @@ -274,13 +274,13 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp) > if (IS_BROADWELL(dev)) > goto out; > > - if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & > + if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & > S3D_ENABLE) { > DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); > return false; > } > > - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { > + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); > return false; > } > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c > index e4d5da5..8c8d807 100644 > --- a/drivers/gpu/drm/i915/intel_sdvo.c > +++ b/drivers/gpu/drm/i915/intel_sdvo.c > @@ -1007,7 +1007,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, > } > > if (intel_sdvo->rgb_quant_range_selectable) { > - if (intel_crtc->config.limited_color_range) > + if (intel_crtc->config->limited_color_range) > frame.avi.quantization_range = > HDMI_QUANTIZATION_RANGE_LIMITED; > else > @@ -1181,8 +1181,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); > struct drm_display_mode *adjusted_mode = > - &crtc->config.base.adjusted_mode; > - struct drm_display_mode *mode = &crtc->config.base.mode; > + &crtc->config->base.adjusted_mode; > + struct drm_display_mode *mode = &crtc->config->base.mode; > struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); > u32 sdvox; > struct intel_sdvo_in_out_map in_out; > @@ -1224,7 +1224,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > if (!intel_sdvo_set_target_input(intel_sdvo)) > return; > > - if (crtc->config.has_hdmi_sink) { > + if (crtc->config->has_hdmi_sink) { > intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); > intel_sdvo_set_colorimetry(intel_sdvo, > SDVO_COLORIMETRY_RGB256); > @@ -1244,7 +1244,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > DRM_INFO("Setting input timings on %s failed\n", > SDVO_NAME(intel_sdvo)); > > - switch (crtc->config.pixel_multiplier) { > + switch (crtc->config->pixel_multiplier) { > default: > WARN(1, "unknown pixel mutlipler specified\n"); > case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; > @@ -1259,7 +1259,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > /* The real mode polarity is set by the SDVO commands, using > * struct intel_sdvo_dtd. */ > sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; > - if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range) > + if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) > sdvox |= HDMI_COLOR_RANGE_16_235; > if (INTEL_INFO(dev)->gen < 5) > sdvox |= SDVO_BORDER_ENABLE; > @@ -1289,7 +1289,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { > /* done in crtc_mode_set as it lives inside the dpll register */ > } else { > - sdvox |= (crtc->config.pixel_multiplier - 1) > + sdvox |= (crtc->config->pixel_multiplier - 1) > << SDVO_PORT_MULTIPLY_SHIFT; > } > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index 454b25d..937bd72 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -79,7 +79,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) > bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) > { > struct drm_device *dev = crtc->base.dev; > - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; > + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; > enum pipe pipe = crtc->pipe; > long timeout = msecs_to_jiffies_timeout(1); > int scanline, min, max, vblank_start; > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index d0e445e..a724e8c 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2572,7 +2572,7 @@ static int i915_display_info(struct seq_file *m, void *unused) seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", crtc->base.base.id, pipe_name(crtc->pipe), - yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); + yesno(crtc->active), crtc->config->pipe_src_w, crtc->config->pipe_src_h); if (crtc->active) { intel_crtc_info(m, crtc); @@ -3280,9 +3280,9 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) * relevant on hsw with pipe A when using the always-on power well * routing. */ - if (crtc->config.cpu_transcoder == TRANSCODER_EDP && - !crtc->config.pch_pfit.enabled) { - crtc->config.pch_pfit.force_thru = true; + if (crtc->config->cpu_transcoder == TRANSCODER_EDP && + !crtc->config->pch_pfit.enabled) { + crtc->config->pch_pfit.force_thru = true; intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); @@ -3306,8 +3306,8 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) * relevant on hsw with pipe A when using the always-on power well * routing. */ - if (crtc->config.pch_pfit.force_thru) { - crtc->config.pch_pfit.force_thru = false; + if (crtc->config->pch_pfit.force_thru) { + crtc->config->pch_pfit.force_thru = false; dev_priv->display.crtc_disable(&crtc->base); dev_priv->display.crtc_enable(&crtc->base); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 11e209e..e55b275 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -567,7 +567,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) struct intel_crtc *intel_crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); const struct drm_display_mode *mode = - &intel_crtc->config.base.adjusted_mode; + &intel_crtc->config->base.adjusted_mode; htotal = mode->crtc_htotal; hsync_start = mode->crtc_hsync_start; @@ -638,7 +638,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; enum pipe pipe = crtc->pipe; int position, vtotal; @@ -665,7 +665,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode; + const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; int position; int vbl_start, vbl_end, hsync_start, htotal, vtotal; bool in_vbl = true; @@ -823,7 +823,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, flags, crtc, - &to_intel_crtc(crtc)->config.base.adjusted_mode); + &to_intel_crtc(crtc)->config->base.adjusted_mode); } static bool intel_hpd_irq_event(struct drm_device *dev, diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index fe8c496..e84a798 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -397,7 +397,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder) { struct drm_encoder *encoder = &intel_encoder->base; struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); - struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; + struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; struct drm_connector *connector; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index e4f6d49..bb55368 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crt *crt = intel_encoder_to_crt(encoder); struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; u32 adpa; if (INTEL_INFO(dev)->gen >= 5) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 970ca30..c409ccc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -328,7 +328,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) /* Enable the PCH Receiver FDI PLL */ rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | FDI_RX_PLL_ENABLE | - FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); + FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); POSTING_READ(_FDI_RXA_CTL); udelay(220); @@ -338,8 +338,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); /* Configure Port Clock Select */ - I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); - WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); + I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); + WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ @@ -357,7 +357,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) * port reversal bit */ I915_WRITE(DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE | - ((intel_crtc->config.fdi_lanes - 1) << 1) | + ((intel_crtc->config->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); POSTING_READ(DDI_BUF_CTL(PORT_E)); @@ -1186,13 +1186,13 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; int type = intel_encoder->type; uint32_t temp; if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { temp = TRANS_MSA_SYNC_CLK; - switch (intel_crtc->config.pipe_bpp) { + switch (intel_crtc->config->pipe_bpp) { case 18: temp |= TRANS_MSA_6_BPC; break; @@ -1217,7 +1217,7 @@ void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; uint32_t temp; temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); if (state == true) @@ -1235,7 +1235,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe = intel_crtc->pipe; - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; enum port port = intel_ddi_get_encoder_port(intel_encoder); int type = intel_encoder->type; uint32_t temp; @@ -1244,7 +1244,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) temp = TRANS_DDI_FUNC_ENABLE; temp |= TRANS_DDI_SELECT_PORT(port); - switch (intel_crtc->config.pipe_bpp) { + switch (intel_crtc->config->pipe_bpp) { case 18: temp |= TRANS_DDI_BPC_6; break; @@ -1261,9 +1261,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) BUG(); } - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) temp |= TRANS_DDI_PVSYNC; - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) temp |= TRANS_DDI_PHSYNC; if (cpu_transcoder == TRANSCODER_EDP) { @@ -1274,8 +1274,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) * using motion blur mitigation (which we don't * support). */ if (IS_HASWELL(dev) && - (intel_crtc->config.pch_pfit.enabled || - intel_crtc->config.pch_pfit.force_thru)) + (intel_crtc->config->pch_pfit.enabled || + intel_crtc->config->pch_pfit.force_thru)) temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; else temp |= TRANS_DDI_EDP_INPUT_A_ON; @@ -1293,14 +1293,14 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) } if (type == INTEL_OUTPUT_HDMI) { - if (intel_crtc->config.has_hdmi_sink) + if (intel_crtc->config->has_hdmi_sink) temp |= TRANS_DDI_MODE_SELECT_HDMI; else temp |= TRANS_DDI_MODE_SELECT_DVI; } else if (type == INTEL_OUTPUT_ANALOG) { temp |= TRANS_DDI_MODE_SELECT_FDI; - temp |= (intel_crtc->config.fdi_lanes - 1) << 1; + temp |= (intel_crtc->config->fdi_lanes - 1) << 1; } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { @@ -1450,7 +1450,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); enum port port = intel_ddi_get_encoder_port(intel_encoder); - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; if (cpu_transcoder != TRANSCODER_EDP) I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), @@ -1460,7 +1460,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) { struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; if (cpu_transcoder != TRANSCODER_EDP) I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), @@ -1482,7 +1482,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) } if (IS_SKYLAKE(dev)) { - uint32_t dpll = crtc->config.ddi_pll_sel; + uint32_t dpll = crtc->config->ddi_pll_sel; uint32_t val; /* @@ -1497,7 +1497,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | DPLL_CRTL1_LINK_RATE_MASK(dpll)); - val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6); + val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); I915_WRITE(DPLL_CTRL1, val); POSTING_READ(DPLL_CTRL1); @@ -1514,8 +1514,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) I915_WRITE(DPLL_CTRL2, val); } else { - WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); - I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); + WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); + I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); } if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { @@ -1532,8 +1532,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); intel_hdmi->set_infoframes(encoder, - crtc->config.has_hdmi_sink, - &crtc->config.base.adjusted_mode); + crtc->config->has_hdmi_sink, + &crtc->config->base.adjusted_mode); } } @@ -1607,7 +1607,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) intel_psr_enable(intel_dp); } - if (intel_crtc->config.has_audio) { + if (intel_crtc->config->has_audio) { intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); intel_audio_codec_enable(intel_encoder); } @@ -1622,7 +1622,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (intel_crtc->config.has_audio) { + if (intel_crtc->config->has_audio) { intel_audio_codec_disable(intel_encoder); intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); } @@ -2031,7 +2031,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; struct intel_hdmi *intel_hdmi; u32 temp, flags = 0; struct drm_device *dev = dev_priv->dev; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a032a1d..462f22a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -895,7 +895,7 @@ bool intel_crtc_active(struct drm_crtc *crtc) * properly reconstruct framebuffers. */ return intel_crtc->active && crtc->primary->fb && - intel_crtc->config.base.adjusted_mode.crtc_clock; + intel_crtc->config->base.adjusted_mode.crtc_clock; } enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, @@ -904,7 +904,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - return intel_crtc->config.cpu_transcoder; + return intel_crtc->config->cpu_transcoder; } static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) @@ -946,7 +946,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; enum pipe pipe = crtc->pipe; if (INTEL_INFO(dev)->gen >= 4) { @@ -1052,10 +1052,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; - if (crtc->config.shared_dpll < 0) + if (crtc->config->shared_dpll < 0) return NULL; - return &dev_priv->shared_dplls[crtc->config.shared_dpll]; + return &dev_priv->shared_dplls[crtc->config->shared_dpll]; } /* For ILK+ */ @@ -1599,7 +1599,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; int reg = DPLL(crtc->pipe); - u32 dpll = crtc->config.dpll_hw_state.dpll; + u32 dpll = crtc->config->dpll_hw_state.dpll; assert_pipe_disabled(dev_priv, crtc->pipe); @@ -1629,7 +1629,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) if (INTEL_INFO(dev)->gen >= 4) { I915_WRITE(DPLL_MD(crtc->pipe), - crtc->config.dpll_hw_state.dpll_md); + crtc->config->dpll_hw_state.dpll_md); } else { /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. @@ -2034,7 +2034,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) else assert_pll_enabled(dev_priv, pipe); else { - if (crtc->config.has_pch_encoder) { + if (crtc->config->has_pch_encoder) { /* if driving the PCH, we need FDI enabled */ assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); assert_fdi_tx_pll_enabled(dev_priv, @@ -2068,7 +2068,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) static void intel_disable_pipe(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; enum pipe pipe = crtc->pipe; int reg; u32 val; @@ -2090,7 +2090,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) * Double wide has implications for planes * so best keep it disabled when not needed. */ - if (crtc->config.double_wide) + if (crtc->config->double_wide) val &= ~PIPECONF_DOUBLE_WIDE; /* Don't disable pipe or pipe PLLs if needed */ @@ -2468,13 +2468,13 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, * which should always be the user's requested size. */ I915_WRITE(DSPSIZE(plane), - ((intel_crtc->config.pipe_src_h - 1) << 16) | - (intel_crtc->config.pipe_src_w - 1)); + ((intel_crtc->config->pipe_src_h - 1) << 16) | + (intel_crtc->config->pipe_src_w - 1)); I915_WRITE(DSPPOS(plane), 0); } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { I915_WRITE(PRIMSIZE(plane), - ((intel_crtc->config.pipe_src_h - 1) << 16) | - (intel_crtc->config.pipe_src_w - 1)); + ((intel_crtc->config->pipe_src_h - 1) << 16) | + (intel_crtc->config->pipe_src_w - 1)); I915_WRITE(PRIMPOS(plane), 0); I915_WRITE(PRIMCNSTALPHA(plane), 0); } @@ -2532,14 +2532,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { dspcntr |= DISPPLANE_ROTATE_180; - x += (intel_crtc->config.pipe_src_w - 1); - y += (intel_crtc->config.pipe_src_h - 1); + x += (intel_crtc->config->pipe_src_w - 1); + y += (intel_crtc->config->pipe_src_h - 1); /* Finding the last pixel of the last line of the display data and adding to linear_offset*/ linear_offset += - (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + - (intel_crtc->config.pipe_src_w - 1) * pixel_size; + (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + + (intel_crtc->config->pipe_src_w - 1) * pixel_size; } I915_WRITE(reg, dspcntr); @@ -2635,14 +2635,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, dspcntr |= DISPPLANE_ROTATE_180; if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { - x += (intel_crtc->config.pipe_src_w - 1); - y += (intel_crtc->config.pipe_src_h - 1); + x += (intel_crtc->config->pipe_src_w - 1); + y += (intel_crtc->config->pipe_src_h - 1); /* Finding the last pixel of the last line of the display data and adding to linear_offset*/ linear_offset += - (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + - (intel_crtc->config.pipe_src_w - 1) * pixel_size; + (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + + (intel_crtc->config->pipe_src_w - 1) * pixel_size; } } @@ -2741,8 +2741,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, 0), 0); I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); I915_WRITE(PLANE_SIZE(pipe, 0), - (intel_crtc->config.pipe_src_h - 1) << 16 | - (intel_crtc->config.pipe_src_w - 1)); + (intel_crtc->config->pipe_src_h - 1) << 16 | + (intel_crtc->config->pipe_src_w - 1)); I915_WRITE(PLANE_STRIDE(pipe, 0), stride); I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); @@ -2938,20 +2938,20 @@ static void intel_update_pipe_size(struct intel_crtc *crtc) * then update the pipesrc and pfit state, even on the flip path. */ - adjusted_mode = &crtc->config.base.adjusted_mode; + adjusted_mode = &crtc->config->base.adjusted_mode; I915_WRITE(PIPESRC(crtc->pipe), ((adjusted_mode->crtc_hdisplay - 1) << 16) | (adjusted_mode->crtc_vdisplay - 1)); - if (!crtc->config.pch_pfit.enabled && + if (!crtc->config->pch_pfit.enabled && (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { I915_WRITE(PF_CTL(crtc->pipe), 0); I915_WRITE(PF_WIN_POS(crtc->pipe), 0); I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); } - crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; - crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; + crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; + crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; } static void intel_fdi_normal_train(struct drm_crtc *crtc) @@ -2998,7 +2998,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) static bool pipe_has_enabled_pch(struct intel_crtc *crtc) { return crtc->base.enabled && crtc->active && - crtc->config.has_pch_encoder; + crtc->config->has_pch_encoder; } static void ivb_modeset_global_resources(struct drm_device *dev) @@ -3053,7 +3053,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) reg = FDI_TX_CTL(pipe); temp = I915_READ(reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; I915_WRITE(reg, temp | FDI_TX_ENABLE); @@ -3151,7 +3151,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) reg = FDI_TX_CTL(pipe); temp = I915_READ(reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; @@ -3302,7 +3302,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) reg = FDI_TX_CTL(pipe); temp = I915_READ(reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[j/2]; @@ -3390,7 +3390,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) reg = FDI_RX_CTL(pipe); temp = I915_READ(reg); temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); @@ -3574,7 +3574,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; - int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock; + int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; u32 divsel, phaseinc, auxdiv, phasedir = 0; u32 temp; @@ -3663,7 +3663,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), I915_READ(HTOTAL(cpu_transcoder))); @@ -3709,7 +3709,7 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) case PIPE_A: break; case PIPE_B: - if (intel_crtc->config.fdi_lanes > 2) + if (intel_crtc->config->fdi_lanes > 2) WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); else cpt_enable_fdi_bc_bifurcation(dev); @@ -3761,7 +3761,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) temp = I915_READ(PCH_DPLL_SEL); temp |= TRANS_DPLL_ENABLE(pipe); sel = TRANS_DPLLB_SEL(pipe); - if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) + if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) temp |= sel; else temp &= ~sel; @@ -3784,7 +3784,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) intel_fdi_normal_train(crtc); /* For PCH DP, enable TRANS_DP_CTL */ - if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) { + if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; reg = TRANS_DP_CTL(pipe); temp = I915_READ(reg); @@ -3825,7 +3825,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); @@ -3855,7 +3855,7 @@ void intel_put_shared_dpll(struct intel_crtc *crtc) WARN_ON(pll->active); } - crtc->config.shared_dpll = DPLL_ID_PRIVATE; + crtc->config->shared_dpll = DPLL_ID_PRIVATE; } struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, @@ -4009,10 +4009,10 @@ static void skylake_pfit_enable(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = dev->dev_private; int pipe = crtc->pipe; - if (crtc->config.pch_pfit.enabled) { + if (crtc->config->pch_pfit.enabled) { I915_WRITE(PS_CTL(pipe), PS_ENABLE); - I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos); - I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size); + I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); + I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); } } @@ -4022,7 +4022,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = dev->dev_private; int pipe = crtc->pipe; - if (crtc->config.pch_pfit.enabled) { + if (crtc->config->pch_pfit.enabled) { /* Force use of hard-coded filter coefficients * as some pre-programmed values are broken, * e.g. x201. @@ -4032,8 +4032,8 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc) PF_PIPE_SEL_IVB(pipe)); else I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); - I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); - I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); + I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); + I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); } } @@ -4070,7 +4070,7 @@ void hsw_enable_ips(struct intel_crtc *crtc) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (!crtc->config.ips_enabled) + if (!crtc->config->ips_enabled) return; /* We can only enable IPS after we enable a plane and wait for a vblank */ @@ -4103,7 +4103,7 @@ void hsw_disable_ips(struct intel_crtc *crtc) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (!crtc->config.ips_enabled) + if (!crtc->config->ips_enabled) return; assert_plane_enabled(dev_priv, crtc->plane); @@ -4152,7 +4152,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) /* Workaround : Do not read or write the pipe palette/gamma data while * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. */ - if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && + if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == GAMMA_MODE_MODE_SPLIT)) { hsw_disable_ips(intel_crtc); @@ -4254,17 +4254,17 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) if (intel_crtc->active) return; - if (intel_crtc->config.has_pch_encoder) + if (intel_crtc->config->has_pch_encoder) intel_prepare_shared_dpll(intel_crtc); - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config->has_dp_encoder) intel_dp_set_m_n(intel_crtc); intel_set_pipe_timings(intel_crtc); - if (intel_crtc->config.has_pch_encoder) { + if (intel_crtc->config->has_pch_encoder) { intel_cpu_transcoder_set_m_n(intel_crtc, - &intel_crtc->config.fdi_m_n, NULL); + &intel_crtc->config->fdi_m_n, NULL); } ironlake_set_pipeconf(crtc); @@ -4278,7 +4278,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) if (encoder->pre_enable) encoder->pre_enable(encoder); - if (intel_crtc->config.has_pch_encoder) { + if (intel_crtc->config->has_pch_encoder) { /* Note: FDI PLL enabling _must_ be done before we enable the * cpu pipes, hence this is separate from all the other fdi/pch * enabling. */ @@ -4299,7 +4299,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(intel_crtc); - if (intel_crtc->config.has_pch_encoder) + if (intel_crtc->config->has_pch_encoder) ironlake_pch_enable(crtc); for_each_encoder_on_crtc(dev, crtc, encoder) @@ -4365,19 +4365,19 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (intel_crtc_to_shared_dpll(intel_crtc)) intel_enable_shared_dpll(intel_crtc); - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config->has_dp_encoder) intel_dp_set_m_n(intel_crtc); intel_set_pipe_timings(intel_crtc); - if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { - I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder), - intel_crtc->config.pixel_multiplier - 1); + if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { + I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), + intel_crtc->config->pixel_multiplier - 1); } - if (intel_crtc->config.has_pch_encoder) { + if (intel_crtc->config->has_pch_encoder) { intel_cpu_transcoder_set_m_n(intel_crtc, - &intel_crtc->config.fdi_m_n, NULL); + &intel_crtc->config->fdi_m_n, NULL); } haswell_set_pipeconf(crtc); @@ -4391,7 +4391,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (encoder->pre_enable) encoder->pre_enable(encoder); - if (intel_crtc->config.has_pch_encoder) { + if (intel_crtc->config->has_pch_encoder) { intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, true); dev_priv->display.fdi_link_train(crtc); @@ -4416,10 +4416,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(intel_crtc); - if (intel_crtc->config.has_pch_encoder) + if (intel_crtc->config->has_pch_encoder) lpt_pch_enable(crtc); - if (intel_crtc->config.dp_encoder_is_mst) + if (intel_crtc->config->dp_encoder_is_mst) intel_ddi_set_vc_payload_alloc(crtc, true); for_each_encoder_on_crtc(dev, crtc, encoder) { @@ -4444,7 +4444,7 @@ static void skylake_pfit_disable(struct intel_crtc *crtc) /* To avoid upsetting the power well on haswell only disable the pfit if * it's in use. The hw state code will make sure we get this right. */ - if (crtc->config.pch_pfit.enabled) { + if (crtc->config->pch_pfit.enabled) { I915_WRITE(PS_CTL(pipe), 0); I915_WRITE(PS_WIN_POS(pipe), 0); I915_WRITE(PS_WIN_SZ(pipe), 0); @@ -4459,7 +4459,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc) /* To avoid upsetting the power well on haswell only disable the pfit if * it's in use. The hw state code will make sure we get this right. */ - if (crtc->config.pch_pfit.enabled) { + if (crtc->config->pch_pfit.enabled) { I915_WRITE(PF_CTL(pipe), 0); I915_WRITE(PF_WIN_POS(pipe), 0); I915_WRITE(PF_WIN_SZ(pipe), 0); @@ -4486,7 +4486,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) for_each_encoder_on_crtc(dev, crtc, encoder) encoder->disable(encoder); - if (intel_crtc->config.has_pch_encoder) + if (intel_crtc->config->has_pch_encoder) intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); intel_disable_pipe(intel_crtc); @@ -4497,7 +4497,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) if (encoder->post_disable) encoder->post_disable(encoder); - if (intel_crtc->config.has_pch_encoder) { + if (intel_crtc->config->has_pch_encoder) { ironlake_fdi_disable(crtc); ironlake_disable_pch_transcoder(dev_priv, pipe); @@ -4537,7 +4537,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_encoder *encoder; - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; if (!intel_crtc->active) return; @@ -4552,12 +4552,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) encoder->disable(encoder); } - if (intel_crtc->config.has_pch_encoder) + if (intel_crtc->config->has_pch_encoder) intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, false); intel_disable_pipe(intel_crtc); - if (intel_crtc->config.dp_encoder_is_mst) + if (intel_crtc->config->dp_encoder_is_mst) intel_ddi_set_vc_payload_alloc(crtc, false); intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); @@ -4569,7 +4569,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_ddi_disable_pipe_clock(intel_crtc); - if (intel_crtc->config.has_pch_encoder) { + if (intel_crtc->config->has_pch_encoder) { lpt_disable_pch_transcoder(dev_priv); intel_ddi_fdi_disable(crtc); } @@ -4600,7 +4600,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc_state *pipe_config = &crtc->config; + struct intel_crtc_state *pipe_config = crtc->config; if (!pipe_config->gmch_pfit.control) return; @@ -4681,8 +4681,8 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) mask = BIT(POWER_DOMAIN_PIPE(pipe)); mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); - if (intel_crtc->config.pch_pfit.enabled || - intel_crtc->config.pch_pfit.force_thru) + if (intel_crtc->config->pch_pfit.enabled || + intel_crtc->config->pch_pfit.force_thru) mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); for_each_encoder_on_crtc(dev, crtc, intel_encoder) @@ -4986,12 +4986,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) if (!is_dsi) { if (IS_CHERRYVIEW(dev)) - chv_prepare_pll(intel_crtc, &intel_crtc->config); + chv_prepare_pll(intel_crtc, intel_crtc->config); else - vlv_prepare_pll(intel_crtc, &intel_crtc->config); + vlv_prepare_pll(intel_crtc, intel_crtc->config); } - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config->has_dp_encoder) intel_dp_set_m_n(intel_crtc); intel_set_pipe_timings(intel_crtc); @@ -5015,9 +5015,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) if (!is_dsi) { if (IS_CHERRYVIEW(dev)) - chv_enable_pll(intel_crtc, &intel_crtc->config); + chv_enable_pll(intel_crtc, intel_crtc->config); else - vlv_enable_pll(intel_crtc, &intel_crtc->config); + vlv_enable_pll(intel_crtc, intel_crtc->config); } for_each_encoder_on_crtc(dev, crtc, encoder) @@ -5048,8 +5048,8 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); - I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); + I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); + I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); } static void i9xx_crtc_enable(struct drm_crtc *crtc) @@ -5067,7 +5067,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) i9xx_set_pll_dividers(intel_crtc); - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config->has_dp_encoder) intel_dp_set_m_n(intel_crtc); intel_set_pipe_timings(intel_crtc); @@ -5119,7 +5119,7 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (!crtc->config.gmch_pfit.control) + if (!crtc->config->gmch_pfit.control) return; assert_pipe_disabled(dev_priv, crtc->pipe); @@ -5418,7 +5418,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, return true; case PIPE_C: if (!pipe_has_enabled_pch(pipe_B_crtc) || - pipe_B_crtc->config.fdi_lanes <= 2) { + pipe_B_crtc->config->fdi_lanes <= 2) { if (pipe_config->fdi_lanes > 2) { DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes); @@ -5816,7 +5816,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; int pipe = crtc->pipe; - enum transcoder transcoder = crtc->config.cpu_transcoder; + enum transcoder transcoder = crtc->config->cpu_transcoder; if (INTEL_INFO(dev)->gen >= 5) { I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); @@ -5828,7 +5828,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, * registers are not unnecessarily accessed). */ if (m2_n2 && INTEL_INFO(dev)->gen < 8 && - crtc->config.has_drrs) { + crtc->config->has_drrs) { I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); @@ -5845,11 +5845,11 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, void intel_dp_set_m_n(struct intel_crtc *crtc) { - if (crtc->config.has_pch_encoder) - intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); + if (crtc->config->has_pch_encoder) + intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); else - intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, - &crtc->config.dp_m2_n2); + intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n, + &crtc->config->dp_m2_n2); } static void vlv_update_pll(struct intel_crtc *crtc, @@ -6217,9 +6217,9 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe = intel_crtc->pipe; - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; struct drm_display_mode *adjusted_mode = - &intel_crtc->config.base.adjusted_mode; + &intel_crtc->config->base.adjusted_mode; uint32_t crtc_vtotal, crtc_vblank_end; int vsyncshift = 0; @@ -6277,8 +6277,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) * always be the user's requested size. */ I915_WRITE(PIPESRC(pipe), - ((intel_crtc->config.pipe_src_w - 1) << 16) | - (intel_crtc->config.pipe_src_h - 1)); + ((intel_crtc->config->pipe_src_w - 1) << 16) | + (intel_crtc->config->pipe_src_h - 1)); } static void intel_get_pipe_timings(struct intel_crtc *crtc, @@ -6354,17 +6354,17 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; - if (intel_crtc->config.double_wide) + if (intel_crtc->config->double_wide) pipeconf |= PIPECONF_DOUBLE_WIDE; /* only g4x and later have fancy bpc/dither controls */ if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { /* Bspec claims that we can't use dithering for 30bpp pipes. */ - if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) + if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) pipeconf |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; - switch (intel_crtc->config.pipe_bpp) { + switch (intel_crtc->config->pipe_bpp) { case 18: pipeconf |= PIPECONF_6BPC; break; @@ -6389,7 +6389,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) } } - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { if (INTEL_INFO(dev)->gen < 4 || intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; @@ -6398,7 +6398,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) } else pipeconf |= PIPECONF_PROGRESSIVE; - if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) + if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) pipeconf |= PIPECONF_COLOR_RANGE_SELECT; I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); @@ -7126,7 +7126,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc) val = 0; - switch (intel_crtc->config.pipe_bpp) { + switch (intel_crtc->config->pipe_bpp) { case 18: val |= PIPECONF_6BPC; break; @@ -7144,15 +7144,15 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc) BUG(); } - if (intel_crtc->config.dither) + if (intel_crtc->config->dither) val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) val |= PIPECONF_INTERLACED_ILK; else val |= PIPECONF_PROGRESSIVE; - if (intel_crtc->config.limited_color_range) + if (intel_crtc->config->limited_color_range) val |= PIPECONF_COLOR_RANGE_SELECT; I915_WRITE(PIPECONF(pipe), val); @@ -7181,7 +7181,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) * consideration. */ - if (intel_crtc->config.limited_color_range) + if (intel_crtc->config->limited_color_range) coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ /* @@ -7205,7 +7205,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) if (INTEL_INFO(dev)->gen > 6) { uint16_t postoff = 0; - if (intel_crtc->config.limited_color_range) + if (intel_crtc->config->limited_color_range) postoff = (16 * (1 << 12) / 255) & 0x1fff; I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); @@ -7216,7 +7216,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) } else { uint32_t mode = CSC_MODE_YUV_TO_RGB; - if (intel_crtc->config.limited_color_range) + if (intel_crtc->config->limited_color_range) mode |= CSC_BLACK_SCREEN_OFFSET; I915_WRITE(PIPE_CSC_MODE(pipe), mode); @@ -7229,15 +7229,15 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum pipe pipe = intel_crtc->pipe; - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; uint32_t val; val = 0; - if (IS_HASWELL(dev) && intel_crtc->config.dither) + if (IS_HASWELL(dev) && intel_crtc->config->dither) val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) val |= PIPECONF_INTERLACED_ILK; else val |= PIPECONF_PROGRESSIVE; @@ -7251,7 +7251,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { val = 0; - switch (intel_crtc->config.pipe_bpp) { + switch (intel_crtc->config->pipe_bpp) { case 18: val |= PIPEMISC_DITHER_6_BPC; break; @@ -7269,7 +7269,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) BUG(); } - if (intel_crtc->config.dither) + if (intel_crtc->config->dither) val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; I915_WRITE(PIPEMISC(pipe), val); @@ -7530,7 +7530,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, * registers are not unnecessarily read). */ if (m2_n2 && INTEL_INFO(dev)->gen < 8 && - crtc->config.has_drrs) { + crtc->config->has_drrs) { m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) @@ -8282,10 +8282,10 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, if (on) base = intel_crtc->cursor_addr; - if (x >= intel_crtc->config.pipe_src_w) + if (x >= intel_crtc->config->pipe_src_w) base = 0; - if (y >= intel_crtc->config.pipe_src_h) + if (y >= intel_crtc->config->pipe_src_h) base = 0; if (x < 0) { @@ -8812,7 +8812,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; struct drm_display_mode *mode; struct intel_crtc_state pipe_config; int htot = I915_READ(HTOTAL(cpu_transcoder)); @@ -10769,11 +10769,11 @@ check_crtc_state(struct drm_device *dev) "(expected %i, found %i)\n", crtc->active, active); if (active && - !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { + !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { WARN(1, "pipe state doesn't match!\n"); intel_dump_pipe_config(crtc, &pipe_config, "[hw state]"); - intel_dump_pipe_config(crtc, &crtc->config, + intel_dump_pipe_config(crtc, crtc->config, "[sw state]"); } } @@ -10873,7 +10873,7 @@ static void update_scanline_offset(struct intel_crtc *crtc) * one to the value. */ if (IS_GEN2(dev)) { - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; int vtotal; vtotal = mode->crtc_vtotal; @@ -10921,6 +10921,13 @@ out: return pipe_config; } +static void intel_crtc_set_state(struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state) +{ + kfree(crtc->config); + crtc->config = crtc_state; +} + static int __intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, int x, int y, struct drm_framebuffer *fb, @@ -11000,7 +11007,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, crtc->mode = *mode; /* mode_set/enable/disable functions rely on a correct pipe * config. */ - to_intel_crtc(crtc)->config = *pipe_config; + intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); /* * Calculate and store various constants which @@ -11044,7 +11051,6 @@ done: if (ret && crtc->enabled) crtc->mode = *saved_mode; - kfree(pipe_config); kfree(saved_mode); return ret; } @@ -11461,7 +11467,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set) goto fail; } else if (pipe_config) { if (pipe_config->has_audio != - to_intel_crtc(set->crtc)->config.has_audio) + to_intel_crtc(set->crtc)->config->has_audio) config->mode_changed = true; /* @@ -11886,8 +11892,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, state.clip.x1 = 0; state.clip.y1 = 0; - state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; - state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; + state.clip.x2 = intel_crtc->active ? intel_crtc->config->pipe_src_w : 0; + state.clip.y2 = intel_crtc->active ? intel_crtc->config->pipe_src_h : 0; state.orig_src = state.src; state.orig_dst = state.dst; @@ -12169,6 +12175,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc; + struct intel_crtc_state *crtc_state = NULL; struct drm_plane *primary = NULL; struct drm_plane *cursor = NULL; int i, ret; @@ -12177,6 +12184,11 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) if (intel_crtc == NULL) return; + crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); + if (!crtc_state) + goto fail; + intel_crtc_set_state(intel_crtc, crtc_state); + primary = intel_primary_plane_create(dev, pipe); if (!primary) goto fail; @@ -12229,6 +12241,7 @@ fail: drm_plane_cleanup(primary); if (cursor) drm_plane_cleanup(cursor); + kfree(crtc_state); kfree(intel_crtc); } @@ -13131,7 +13144,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) u32 reg; /* Clear any frame start delays used for debugging left by the BIOS */ - reg = PIPECONF(crtc->config.cpu_transcoder); + reg = PIPECONF(crtc->config->cpu_transcoder); I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); /* restore vblank interrupts to correct state */ @@ -13335,12 +13348,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) int i; for_each_intel_crtc(dev, crtc) { - memset(&crtc->config, 0, sizeof(crtc->config)); + memset(crtc->config, 0, sizeof(*crtc->config)); - crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; + crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; crtc->active = dev_priv->display.get_pipe_config(crtc, - &crtc->config); + crtc->config); crtc->base.enabled = crtc->active; crtc->primary_enabled = primary_get_hw_state(crtc); @@ -13377,7 +13390,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) if (encoder->get_hw_state(encoder, &pipe)) { crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); encoder->base.crtc = &crtc->base; - encoder->get_config(encoder, &crtc->config); + encoder->get_config(encoder, crtc->config); } else { encoder->base.crtc = NULL; } @@ -13427,7 +13440,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, */ for_each_intel_crtc(dev, crtc) { if (crtc->active && i915.fastboot) { - intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); + intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", crtc->base.base.id); drm_mode_debug_printmodeline(&crtc->base.mode); @@ -13442,7 +13455,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, for_each_pipe(dev_priv, pipe) { crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); intel_sanitize_crtc(crtc); - intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); + intel_dump_pipe_config(crtc, crtc->config, "[setup_hw_state]"); } for (i = 0; i < dev_priv->num_shared_dpll; i++) { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 67cdbe8..d6f0d90 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1295,11 +1295,11 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dev->dev_private; u32 dpa_ctl; - DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); + DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config->port_clock); dpa_ctl = I915_READ(DP_A); dpa_ctl &= ~DP_PLL_FREQ_MASK; - if (crtc->config.port_clock == 162000) { + if (crtc->config->port_clock == 162000) { /* For a long time we've carried around a ILK-DevA w/a for the * 160MHz clock. If we're really unlucky, it's still required. */ @@ -1324,7 +1324,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder) struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = dp_to_dig_port(intel_dp)->port; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; /* * There are four kinds of DP registers: @@ -1352,7 +1352,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder) intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); - if (crtc->config.has_audio) + if (crtc->config->has_audio) intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; /* Split out the IBX/CPU vs CPT settings */ @@ -2102,7 +2102,7 @@ static void intel_disable_dp(struct intel_encoder *encoder) struct drm_device *dev = encoder->base.dev; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); - if (crtc->config.has_audio) + if (crtc->config->has_audio) intel_audio_codec_disable(encoder); if (HAS_PSR(dev) && !HAS_DDI(dev)) @@ -2312,7 +2312,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) intel_dp_complete_link_train(intel_dp); intel_dp_stop_link_train(intel_dp); - if (crtc->config.has_audio) { + if (crtc->config->has_audio) { DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", pipe_name(crtc->pipe)); intel_audio_codec_enable(encoder); @@ -4780,7 +4780,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) return; } - config = &intel_crtc->config; + config = intel_crtc->config; if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); @@ -4802,7 +4802,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) } if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { - reg = PIPECONF(intel_crtc->config.cpu_transcoder); + reg = PIPECONF(intel_crtc->config->cpu_transcoder); val = I915_READ(reg); if (index > DRRS_HIGH_RR) { val |= PIPECONF_EDP_RR_MODE_SWITCH; diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 257aca1..28b6ee4 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -157,7 +157,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) if (intel_dp->active_mst_links == 0) { enum port port = intel_ddi_get_encoder_port(encoder); - I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config.ddi_pll_sel); + I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config->ddi_pll_sel); intel_ddi_init_dp_buf_reg(&intel_dig_port->base); @@ -170,7 +170,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) } ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, - intel_mst->port, intel_crtc->config.pbn, &slots); + intel_mst->port, intel_crtc->config->pbn, + &slots); if (ret == false) { DRM_ERROR("failed to allocate vcpi\n"); return; @@ -223,7 +224,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; u32 temp, flags = 0; pipe_config->has_dp_encoder = true; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 175b853..01d6fa1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -439,7 +439,7 @@ struct intel_crtc { uint32_t cursor_base; struct intel_plane_config plane_config; - struct intel_crtc_state config; + struct intel_crtc_state *config; bool new_enabled; /* reset counter value when the last flip was submitted */ diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 25291e9..5d9ec7b 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -232,7 +232,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) I915_WRITE(DPLL(pipe), tmp); /* update the hw state for DPLL */ - intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | + intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | DPLL_REFA_CLK_ENABLE_VLV; tmp = I915_READ(DSPCLK_GATE_D); @@ -494,7 +494,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; - unsigned int bpp = intel_crtc->config.pipe_bpp; + unsigned int bpp = intel_crtc->config->pipe_bpp; unsigned int lane_count = intel_dsi->lane_count; u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; @@ -549,9 +549,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct drm_display_mode *adjusted_mode = - &intel_crtc->config.base.adjusted_mode; + &intel_crtc->config->base.adjusted_mode; enum port port; - unsigned int bpp = intel_crtc->config.pipe_bpp; + unsigned int bpp = intel_crtc->config->pipe_bpp; u32 val, tmp; u16 mode_hdisplay; diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 108f058..706ab99 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -186,8 +186,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder) u32 temp = I915_READ(dvo_reg); intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, - &crtc->config.base.mode, - &crtc->config.base.adjusted_mode); + &crtc->config->base.mode, + &crtc->config->base.adjusted_mode); I915_WRITE(dvo_reg, temp | DVO_ENABLE); I915_READ(dvo_reg); @@ -221,7 +221,7 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode) /* We call connector dpms manually below in case pipe dpms doesn't * change due to cloning. */ if (mode == DRM_MODE_DPMS_ON) { - config = &to_intel_crtc(crtc)->config; + config = to_intel_crtc(crtc)->config; intel_dvo->base.connectors_active = true; @@ -295,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder) struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; struct intel_dvo *intel_dvo = enc_to_dvo(encoder); int pipe = crtc->pipe; u32 dvo_val; diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 1a9a727..f426e7c 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -431,7 +431,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper, DRM_DEBUG_KMS("looking for current mode on connector %s\n", connector->name); intel_mode_from_pipe_config(&encoder->crtc->hwmode, - &to_intel_crtc(encoder->crtc)->config); + to_intel_crtc(encoder->crtc)->config); modes[i] = &encoder->crtc->hwmode; } crtcs[i] = new_crtc; @@ -563,7 +563,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, * pipe. Note we need to use the selected fb's pitch and bpp * rather than the current pipe's, since they differ. */ - cur_size = intel_crtc->config.base.adjusted_mode.crtc_hdisplay; + cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay; cur_size = cur_size * fb->base.bits_per_pixel / 8; if (fb->base.pitches[0] < cur_size) { DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n", @@ -574,13 +574,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, break; } - cur_size = intel_crtc->config.base.adjusted_mode.crtc_vdisplay; + cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay; cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1); cur_size *= fb->base.pitches[0]; DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n", pipe_name(intel_crtc->pipe), - intel_crtc->config.base.adjusted_mode.crtc_hdisplay, - intel_crtc->config.base.adjusted_mode.crtc_vdisplay, + intel_crtc->config->base.adjusted_mode.crtc_hdisplay, + intel_crtc->config->base.adjusted_mode.crtc_vdisplay, fb->base.bits_per_pixel, cur_size); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 02ff3e2..200a0e7 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -337,13 +337,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); u32 data_reg; int i; u32 val = I915_READ(ctl_reg); data_reg = hsw_infoframe_data_reg(type, - intel_crtc->config.cpu_transcoder, + intel_crtc->config->cpu_transcoder, dev_priv); if (data_reg == 0) return; @@ -371,7 +371,7 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); u32 val = I915_READ(ctl_reg); return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | @@ -436,7 +436,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, } if (intel_hdmi->rgb_quant_range_selectable) { - if (intel_crtc->config.limited_color_range) + if (intel_crtc->config->limited_color_range) frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; else @@ -672,7 +672,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder, struct drm_i915_private *dev_priv = encoder->dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); + u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); u32 val = I915_READ(reg); assert_hdmi_port_disabled(intel_hdmi); @@ -700,7 +700,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode; + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; u32 hdmi_val; hdmi_val = SDVO_ENCODING_HDMI; @@ -711,12 +711,12 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder) if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; - if (crtc->config.pipe_bpp > 24) + if (crtc->config->pipe_bpp > 24) hdmi_val |= HDMI_COLOR_FORMAT_12bpc; else hdmi_val |= SDVO_COLOR_FORMAT_8bpc; - if (crtc->config.has_hdmi_sink) + if (crtc->config->has_hdmi_sink) hdmi_val |= HDMI_MODE_SELECT_HDMI; if (HAS_PCH_CPT(dev)) @@ -814,7 +814,7 @@ static void intel_enable_hdmi(struct intel_encoder *encoder) u32 temp; u32 enable_bits = SDVO_ENABLE; - if (intel_crtc->config.has_audio) + if (intel_crtc->config->has_audio) enable_bits |= SDVO_AUDIO_ENABLE; temp = I915_READ(intel_hdmi->hdmi_reg); @@ -845,8 +845,8 @@ static void intel_enable_hdmi(struct intel_encoder *encoder) POSTING_READ(intel_hdmi->hdmi_reg); } - if (intel_crtc->config.has_audio) { - WARN_ON(!intel_crtc->config.has_hdmi_sink); + if (intel_crtc->config->has_audio) { + WARN_ON(!intel_crtc->config->has_hdmi_sink); DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", pipe_name(intel_crtc->pipe)); intel_audio_codec_enable(encoder); @@ -866,7 +866,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) u32 temp; u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; - if (crtc->config.has_audio) + if (crtc->config->has_audio) intel_audio_codec_disable(encoder); temp = I915_READ(intel_hdmi->hdmi_reg); @@ -1252,12 +1252,12 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder) struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct drm_display_mode *adjusted_mode = - &intel_crtc->config.base.adjusted_mode; + &intel_crtc->config->base.adjusted_mode; intel_hdmi_prepare(encoder); intel_hdmi->set_infoframes(&encoder->base, - intel_crtc->config.has_hdmi_sink, + intel_crtc->config->has_hdmi_sink, adjusted_mode); } @@ -1270,7 +1270,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct drm_display_mode *adjusted_mode = - &intel_crtc->config.base.adjusted_mode; + &intel_crtc->config->base.adjusted_mode; enum dpio_channel port = vlv_dport_to_channel(dport); int pipe = intel_crtc->pipe; u32 val; @@ -1302,7 +1302,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) mutex_unlock(&dev_priv->dpio_lock); intel_hdmi->set_infoframes(&encoder->base, - intel_crtc->config.has_hdmi_sink, + intel_crtc->config->has_hdmi_sink, adjusted_mode); intel_enable_hdmi(encoder); @@ -1467,7 +1467,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct drm_display_mode *adjusted_mode = - &intel_crtc->config.base.adjusted_mode; + &intel_crtc->config->base.adjusted_mode; enum dpio_channel ch = vlv_dport_to_channel(dport); int pipe = intel_crtc->pipe; int data, i; @@ -1593,7 +1593,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) mutex_unlock(&dev_priv->dpio_lock); intel_hdmi->set_infoframes(&encoder->base, - intel_crtc->config.has_hdmi_sink, + intel_crtc->config->has_hdmi_sink, adjusted_mode); intel_enable_hdmi(encoder); diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 9d174cf..c7c6414 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -139,7 +139,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); const struct drm_display_mode *adjusted_mode = - &crtc->config.base.adjusted_mode; + &crtc->config->base.adjusted_mode; int pipe = crtc->pipe; u32 temp; @@ -167,7 +167,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) /* set the corresponsding LVDS_BORDER bit */ temp &= ~LVDS_BORDER_ENABLE; - temp |= crtc->config.gmch_pfit.lvds_border_bits; + temp |= crtc->config->gmch_pfit.lvds_border_bits; /* Set the B0-B3 data pairs corresponding to whether we're going to * set the DPLLs for dual-channel mode or not. */ @@ -190,7 +190,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) if (INTEL_INFO(dev)->gen == 4) { /* Bspec wording suggests that LVDS port dithering only exists * for 18bpp panels. */ - if (crtc->config.dither && crtc->config.pipe_bpp == 18) + if (crtc->config->dither && crtc->config->pipe_bpp == 18) temp |= LVDS_ENABLE_DITHER; else temp &= ~LVDS_ENABLE_DITHER; diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 973c9de..f93dfc1 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -856,7 +856,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, return -EINVAL; /* can't use the overlay with double wide pipe */ - if (crtc->config.double_wide) + if (crtc->config->double_wide) return -EINVAL; return 0; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 47b23b7..22e49f4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -574,7 +574,7 @@ void intel_update_fbc(struct drm_device *dev) intel_crtc = to_intel_crtc(crtc); fb = crtc->primary->fb; obj = intel_fb_obj(fb); - adjusted_mode = &intel_crtc->config.base.adjusted_mode; + adjusted_mode = &intel_crtc->config->base.adjusted_mode; if (i915.enable_fbc < 0) { if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) @@ -604,8 +604,8 @@ void intel_update_fbc(struct drm_device *dev) max_width = 2048; max_height = 1536; } - if (intel_crtc->config.pipe_src_w > max_width || - intel_crtc->config.pipe_src_h > max_height) { + if (intel_crtc->config->pipe_src_w > max_width || + intel_crtc->config->pipe_src_h > max_height) { if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) DRM_DEBUG_KMS("mode too large for compression, disabling\n"); goto out_disable; @@ -1157,7 +1157,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) int pixel_size = crtc->primary->fb->bits_per_pixel / 8; int clock; - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; clock = adjusted_mode->crtc_clock; /* Display SR */ @@ -1226,10 +1226,10 @@ static bool g4x_compute_wm0(struct drm_device *dev, return false; } - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; clock = adjusted_mode->crtc_clock; htotal = adjusted_mode->crtc_htotal; - hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; + hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* Use the small buffer method to calculate plane watermark */ @@ -1313,10 +1313,10 @@ static bool g4x_compute_srwm(struct drm_device *dev, } crtc = intel_get_crtc_for_plane(dev, plane); - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; clock = adjusted_mode->crtc_clock; htotal = adjusted_mode->crtc_htotal; - hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; + hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; pixel_size = crtc->primary->fb->bits_per_pixel / 8; line_time_us = max(htotal * 1000 / clock, 1); @@ -1347,7 +1347,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc, { struct drm_device *dev = crtc->dev; int entries; - int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock; + int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; if (WARN(clock == 0, "Pixel clock is zero!\n")) return false; @@ -1677,10 +1677,10 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) /* self-refresh has much higher latency */ static const int sr_latency_ns = 12000; const struct drm_display_mode *adjusted_mode = - &to_intel_crtc(crtc)->config.base.adjusted_mode; + &to_intel_crtc(crtc)->config->base.adjusted_mode; int clock = adjusted_mode->crtc_clock; int htotal = adjusted_mode->crtc_htotal; - int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; + int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; int pixel_size = crtc->primary->fb->bits_per_pixel / 8; unsigned long line_time_us; int entries; @@ -1762,7 +1762,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) if (IS_GEN2(dev)) cpp = 4; - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, pessimal_latency_ns); @@ -1784,7 +1784,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) if (IS_GEN2(dev)) cpp = 4; - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, pessimal_latency_ns); @@ -1823,10 +1823,10 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) /* self-refresh has much higher latency */ static const int sr_latency_ns = 6000; const struct drm_display_mode *adjusted_mode = - &to_intel_crtc(enabled)->config.base.adjusted_mode; + &to_intel_crtc(enabled)->config->base.adjusted_mode; int clock = adjusted_mode->crtc_clock; int htotal = adjusted_mode->crtc_htotal; - int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; + int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; int pixel_size = enabled->primary->fb->bits_per_pixel / 8; unsigned long line_time_us; int entries; @@ -1879,7 +1879,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc) if (crtc == NULL) return; - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, &i845_wm_info, dev_priv->display.get_fifo_size(dev, 0), @@ -1898,17 +1898,17 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); uint32_t pixel_rate; - pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock; + pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock; /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to * adjust the pixel_rate here. */ - if (intel_crtc->config.pch_pfit.enabled) { + if (intel_crtc->config->pch_pfit.enabled) { uint64_t pipe_w, pipe_h, pfit_w, pfit_h; - uint32_t pfit_size = intel_crtc->config.pch_pfit.size; + uint32_t pfit_size = intel_crtc->config->pch_pfit.size; - pipe_w = intel_crtc->config.pipe_src_w; - pipe_h = intel_crtc->config.pipe_src_h; + pipe_w = intel_crtc->config->pipe_src_w; + pipe_h = intel_crtc->config->pipe_src_h; pfit_w = (pfit_size >> 16) & 0xFFFF; pfit_h = pfit_size & 0xFFFF; if (pipe_w < pfit_w) @@ -2261,7 +2261,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode; + struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; u32 linetime, ips_linetime; if (!intel_crtc_active(crtc)) @@ -2521,11 +2521,11 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc, return; p->active = true; - p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal; + p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; p->cur.bytes_per_pixel = 4; - p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; + p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; p->cur.horiz_pixels = intel_crtc->cursor_width; /* TODO: for now, assume primary and cursor planes are always enabled. */ p->pri.enabled = true; @@ -3265,8 +3265,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, p->active = intel_crtc_active(crtc); if (p->active) { - p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal; - p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config); + p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; + p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); /* * For now, assume primary and cursor planes are always enabled. @@ -3274,8 +3274,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, p->plane[0].enabled = true; p->plane[0].bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; - p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w; - p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h; + p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; + p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; p->cursor.enabled = true; p->cursor.bytes_per_pixel = 4; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index b8713e4..494b132 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -79,8 +79,8 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp, struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); - u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder); + u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder); uint32_t *data = (uint32_t *) vsc_psr; unsigned int i; @@ -274,13 +274,13 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp) if (IS_BROADWELL(dev)) goto out; - if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & + if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & S3D_ENABLE) { DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); return false; } - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); return false; } diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index e4d5da5..8c8d807 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1007,7 +1007,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, } if (intel_sdvo->rgb_quant_range_selectable) { - if (intel_crtc->config.limited_color_range) + if (intel_crtc->config->limited_color_range) frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; else @@ -1181,8 +1181,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); struct drm_display_mode *adjusted_mode = - &crtc->config.base.adjusted_mode; - struct drm_display_mode *mode = &crtc->config.base.mode; + &crtc->config->base.adjusted_mode; + struct drm_display_mode *mode = &crtc->config->base.mode; struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); u32 sdvox; struct intel_sdvo_in_out_map in_out; @@ -1224,7 +1224,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) if (!intel_sdvo_set_target_input(intel_sdvo)) return; - if (crtc->config.has_hdmi_sink) { + if (crtc->config->has_hdmi_sink) { intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); intel_sdvo_set_colorimetry(intel_sdvo, SDVO_COLORIMETRY_RGB256); @@ -1244,7 +1244,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) DRM_INFO("Setting input timings on %s failed\n", SDVO_NAME(intel_sdvo)); - switch (crtc->config.pixel_multiplier) { + switch (crtc->config->pixel_multiplier) { default: WARN(1, "unknown pixel mutlipler specified\n"); case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; @@ -1259,7 +1259,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; - if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range) + if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) sdvox |= HDMI_COLOR_RANGE_16_235; if (INTEL_INFO(dev)->gen < 5) sdvox |= SDVO_BORDER_ENABLE; @@ -1289,7 +1289,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { /* done in crtc_mode_set as it lives inside the dpll register */ } else { - sdvox |= (crtc->config.pixel_multiplier - 1) + sdvox |= (crtc->config->pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; } diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 454b25d..937bd72 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -79,7 +79,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) { struct drm_device *dev = crtc->base.dev; - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode; + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; enum pipe pipe = crtc->pipe; long timeout = msecs_to_jiffies_timeout(1); int scanline, min, max, vblank_start;

[7/8] drm/i915: Make intel_crtc->config a pointer

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