| Message ID | 1418812486-12394-6-git-send-email-gabriel.fernandez@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 17 Dec 2014 11:34:46 +0100 Gabriel FERNANDEZ <gabriel.fernandez@st.com> wrote: > sti SoCs PCIe IPs are built around DesignWare IP Core. > But in these SoCs, PCIe IP doesn't support IO. > By default, when no IO space is provided, a default one is assigned. > > Add an empty IO resource to the bus, and disable IO by default. As a point of PCI pedantry I don't think this is quite sufficient. PCI has a weird corner case where I/O resources are implied rather than allocated. For IDE/SATA you may need to something like if (class == PCI_CLASS_STORAGE_IDE) { u8 progif; pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); progif |= 5; pci_write_config_byte(dev, PCI_CLASS_PROG, &progif); } so that any adapter is kicked out of legacy mode and doesn't get implied I/O resources and interrupts. I don't know if that case matters for your usage.
Hi, Yes, we don't really care about this corner case. Thanks for your reviewing. BR Gabriel On 17 December 2014 at 15:01, One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> wrote: > On Wed, 17 Dec 2014 11:34:46 +0100 > Gabriel FERNANDEZ <gabriel.fernandez@st.com> wrote: > >> sti SoCs PCIe IPs are built around DesignWare IP Core. >> But in these SoCs, PCIe IP doesn't support IO. >> By default, when no IO space is provided, a default one is assigned. >> >> Add an empty IO resource to the bus, and disable IO by default. > > As a point of PCI pedantry I don't think this is quite sufficient. PCI > has a weird corner case where I/O resources are implied rather than > allocated. > > For IDE/SATA you may need to something like > > if (class == PCI_CLASS_STORAGE_IDE) { > u8 progif; > pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); > progif |= 5; > pci_write_config_byte(dev, PCI_CLASS_PROG, &progif); > } > > so that any adapter is kicked out of legacy mode and doesn't get implied > I/O resources and interrupts. I don't know if that case matters for your > usage. > >
diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c index bd3d32d..c0d3895 100644 --- a/drivers/pci/host/pci-st.c +++ b/drivers/pci/host/pci-st.c @@ -357,9 +357,15 @@ static void st_pcie_board_reset(struct pcie_port *pp) static void st_pcie_hw_setup(struct pcie_port *pp) { struct st_pcie *pcie = to_st_pcie(pp); + u32 val; dw_pcie_setup_rc(pp); + /* Disable IO support */ + val = readl_relaxed(pp->dbi_base + PCI_COMMAND); + val &= ~PCI_COMMAND_IO; + writel_relaxed(val, pp->dbi_base + PCI_COMMAND); + /* Set up the config window to the top of the PCI address space */ writel_relaxed(pcie->config_window_start, pp->dbi_base + CFG_BASE_ADDRESS); @@ -445,11 +451,28 @@ static void st_pcie_host_init(struct pcie_port *pp) st_msi_init_one(pp); } +static void st_pcie_setup_bus(struct pcie_port *pp, struct pci_sys_data *sys) +{ + struct resource *res; + + /* This PCIe controller does not support IO, set an empty one. */ + res = devm_kzalloc(pp->dev, sizeof(*res), GFP_KERNEL); + if (!res) + return; + + res->start = 0; + res->end = 0; + res->name = "PCIe empty IO space"; + res->flags = IORESOURCE_IO; + pci_add_resource(&sys->resources, res); +} + static struct pcie_host_ops st_pcie_host_ops = { .rd_other_conf = st_pcie_rd_other_conf, .wr_other_conf = st_pcie_wr_other_conf, .link_up = st_pcie_link_up, .host_init = st_pcie_host_init, + .setup_bus = st_pcie_setup_bus, }; static int st_pcie_init(struct pcie_port *pp)
sti SoCs PCIe IPs are built around DesignWare IP Core. But in these SoCs, PCIe IP doesn't support IO. By default, when no IO space is provided, a default one is assigned. Add an empty IO resource to the bus, and disable IO by default. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> --- drivers/pci/host/pci-st.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)