| Message ID | 1590307.oZ7E5cNY8h@phil (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Dec 18, 2014 at 08:22:34PM +0100, Heiko Stübner wrote: > Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type > for armclk) didn't take into account that the divider used on rk3288 > are of the (n+1) type. > > The rk3066 and rk3188 socs use more complex divider types making it > necessary for the list-elements to be the real register-values to write. > > Therefore reduce divider values in the table accordingly so that they > really are the values that should be written to the registers. > > Reported-by: Sonny Rao <sonnyrao@chromium.org> > Fixes: 0e5bdb3f9fa5 The correct format for this is: Fixes: <12-digits-of-sha> ("<commit-comment>") where everything between and including the <> gets replaced. The () and "" stay. In other words: Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk") Thanks.
Heiko, On Thu, Dec 18, 2014 at 11:22 AM, Heiko Stübner <heiko@sntech.de> wrote: > Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type > for armclk) didn't take into account that the divider used on rk3288 > are of the (n+1) type. > > The rk3066 and rk3188 socs use more complex divider types making it > necessary for the list-elements to be the real register-values to write. > > Therefore reduce divider values in the table accordingly so that they > really are the values that should be written to the registers. > > Reported-by: Sonny Rao <sonnyrao@chromium.org> > Fixes: 0e5bdb3f9fa5 > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > Cc: stable@vger.kernel.org > --- > drivers/clk/rockchip/clk-rk3288.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) Looks right to me: Reviewed-by: Doug Anderson <dianders@chromium.org> I've done basic testing on this and saw no problems, but I haven't done stress testing yet...
Am Donnerstag, 18. Dezember 2014, 20:22:34 schrieb Heiko Stübner: > Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type > for armclk) didn't take into account that the divider used on rk3288 > are of the (n+1) type. > > The rk3066 and rk3188 socs use more complex divider types making it > necessary for the list-elements to be the real register-values to write. > > Therefore reduce divider values in the table accordingly so that they > really are the values that should be written to the registers. > > Reported-by: Sonny Rao <sonnyrao@chromium.org> > Fixes: 0e5bdb3f9fa5 > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > Cc: stable@vger.kernel.org applied to my clk-fixes branch with fixed "Fixes"-Tag and Doug's review
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index ac6be7c..11194b8 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -145,20 +145,20 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = { } static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = { - RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4), + RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3), }; static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers. Reported-by: Sonny Rao <sonnyrao@chromium.org> Fixes: 0e5bdb3f9fa5 Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: stable@vger.kernel.org --- drivers/clk/rockchip/clk-rk3288.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-)