diff mbox

drm/i915: Reset CSB read pointer when enabling contexts

Message ID 1420646970-4897-1-git-send-email-thomas.daniel@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Thomas Daniel Jan. 7, 2015, 4:09 p.m. UTC 
During a suspend/resume cycle the hardware Context Status Buffer write pointer
is reset.  However since recent changes to the init sequence the software CSB
read pointer is no longer reset.  This means that context status events are not
handled correctly and new contexts are not written to the ELSP, resulting in an
apparent GPU hang.

Pending further changes to the ring init code, just move the
ring->next_context_status_buffer initialization into i915_gem_context_enable to
fix this regression.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88097
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c |    1 +
 drivers/gpu/drm/i915/intel_lrc.c        |    1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

Comments

Daniel Vetter Jan. 7, 2015, 4:56 p.m. UTC | #1 
On Wed, Jan 07, 2015 at 04:09:30PM +0000, Thomas Daniel wrote:
> During a suspend/resume cycle the hardware Context Status Buffer write pointer
> is reset.  However since recent changes to the init sequence the software CSB
> read pointer is no longer reset.  This means that context status events are not
> handled correctly and new contexts are not written to the ELSP, resulting in an
> apparent GPU hang.
> 
> Pending further changes to the ring init code, just move the
> ring->next_context_status_buffer initialization into i915_gem_context_enable to
> fix this regression.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88097

Please cite the commit which introduced this regression (plus since it's
just the switch of defaults) also the commit which broke the execlist
code. And then add all the relevant ppl to the cc list of this patch.

> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c |    1 +
>  drivers/gpu/drm/i915/intel_lrc.c        |    1 -
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index bf9778e..cc100c9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -412,6 +412,7 @@ int i915_gem_context_enable(struct drm_i915_private *dev_priv)
>  
>  	if (i915.enable_execlists) {
>  		for_each_ring(ring, dev_priv, i) {
> +			ring->next_context_status_buffer = 0;

Hm, shouldn't we instead move this to the ring->init_hw callback instead?
That was the split which broke things here after all, and imo it makes
more sense. Otherwise someone might reorder the setup sequence a bit and
get confused when the engine is enabled already but the sw side still has
bogus state ...

Thanks, Daniel

>  			if (ring->init_context) {
>  				ret = ring->init_context(ring,
>  						ring->default_context);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 7670a0f..4580267 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1394,7 +1394,6 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
>  	INIT_LIST_HEAD(&ring->execlist_queue);
>  	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
>  	spin_lock_init(&ring->execlist_lock);
> -	ring->next_context_status_buffer = 0;
>  
>  	ret = i915_cmd_parser_init_ring(ring);
>  	if (ret)
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Shuang He Jan. 7, 2015, 8:39 p.m. UTC | #2 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -23              363/364              340/364
ILK                 -30              364/366              334/366
SNB              +4-56              443/450              391/450
IVB                 -36              496/498              460/498
BYT                                  288/289              288/289
HSW              +11-36              542/564              517/564
BDW                 -25              415/417              390/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(2, M23M25)PASS(1, M25)      NSPT(1, M25)
 ILK  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(2, M26)PASS(1, M37)      NSPT(1, M26)
 ILK  igt_kms_flip_nonexisting-fb      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_rcs-flip-vs-panning-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_render_direct-render      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_bcs-flip-vs-modeset-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_blocking-absolute-wf_vblank-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_busy-flip-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_flip-vs-dpms-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_flip-vs-panning      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_flip-vs-rmfb-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_plain-flip-fb-recreate-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_plain-flip-ts-check-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_rcs-flip-vs-dpms      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_rcs-flip-vs-modeset      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_rcs-flip-vs-panning      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_vblank-vs-hang      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_wf_vblank-ts-check      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_wf_vblank-vs-modeset-interruptible      DMESG_WARN(3, M26)PASS(1, M37)      DMESG_WARN(1, M26)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(2, M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_kms_cursor_crc_cursor-size-change      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(3, M35M22)PASS(2, M35M22)      PASS(1, M22)
 SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(2, M35M22)PASS(3, M35M22)      PASS(1, M22)
 SNB  igt_kms_flip_event_leak      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_kms_flip_modeset-vs-vblank-race      DMESG_WARN(4, M35M22)PASS(2, M35M22)      PASS(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_kms_plane_plane-position-hole-pipe-B-plane-1      DMESG_WARN(1, M35)PASS(6, M35M22)      PASS(1, M22)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_cursor      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_fences      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_fences-dpms      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-pread      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_i2c      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 SNB  igt_pm_rpm_rte      NSPT(2, M35M22)PASS(1, M35)      NSPT(1, M22)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(2, M21M34)PASS(1, M34)      NSPT(1, M34)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(2, M19M20)PASS(1, M40)      NSPT(1, M20)
 HSW  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(1, M40)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(2, M40)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_flip_flip-vs-dpms-off-vs-modeset      DMESG_WARN(1, M40)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible      DMESG_WARN(2, M40M19)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_flip_modeset-vs-vblank-race      DMESG_WARN(1, M40)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_flip_modeset-vs-vblank-race-interruptible      DMESG_WARN(1, M40)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible      DMESG_WARN(2, M40)PASS(3, M19M20)      PASS(1, M20)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-1      TIMEOUT(1, M40)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2      TIMEOUT(1, M40)PASS(2, M19M20)      PASS(1, M20)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1      TIMEOUT(3, M40)PASS(4, M19M40M20)      PASS(1, M20)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(2, M19)DMESG_WARN(1, M40)PASS(4, M40M20)      PASS(1, M20)
 BDW  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(2, M28M30)PASS(1, M30)      NSPT(1, M30)
*BDW  igt_gem_multi_bsd_sync_loop      PASS(3, M30M28)      DMESG_WARN(1, M30)
Note: You need to pay more attention to line start with '*'
Daniel Vetter Jan. 8, 2015, 8:01 a.m. UTC | #3 
On Wed, Jan 07, 2015 at 04:09:30PM +0000, Thomas Daniel wrote:
> During a suspend/resume cycle the hardware Context Status Buffer write pointer
> is reset.  However since recent changes to the init sequence the software CSB
> read pointer is no longer reset.  This means that context status events are not
> handled correctly and new contexts are not written to the ELSP, resulting in an
> apparent GPU hang.
> 
> Pending further changes to the ring init code, just move the
> ring->next_context_status_buffer initialization into i915_gem_context_enable to
> fix this regression.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88097
There's also

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88096

Can you please take a look at that one too?
-Daniel

> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c |    1 +
>  drivers/gpu/drm/i915/intel_lrc.c        |    1 -
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index bf9778e..cc100c9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -412,6 +412,7 @@ int i915_gem_context_enable(struct drm_i915_private *dev_priv)
>  
>  	if (i915.enable_execlists) {
>  		for_each_ring(ring, dev_priv, i) {
> +			ring->next_context_status_buffer = 0;
>  			if (ring->init_context) {
>  				ret = ring->init_context(ring,
>  						ring->default_context);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 7670a0f..4580267 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1394,7 +1394,6 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
>  	INIT_LIST_HEAD(&ring->execlist_queue);
>  	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
>  	spin_lock_init(&ring->execlist_lock);
> -	ring->next_context_status_buffer = 0;
>  
>  	ret = i915_cmd_parser_init_ring(ring);
>  	if (ret)
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index bf9778e..cc100c9 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -412,6 +412,7 @@  int i915_gem_context_enable(struct drm_i915_private *dev_priv)
 
 	if (i915.enable_execlists) {
 		for_each_ring(ring, dev_priv, i) {
+			ring->next_context_status_buffer = 0;
 			if (ring->init_context) {
 				ret = ring->init_context(ring,
 						ring->default_context);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7670a0f..4580267 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1394,7 +1394,6 @@  static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
 	INIT_LIST_HEAD(&ring->execlist_queue);
 	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
 	spin_lock_init(&ring->execlist_lock);
-	ring->next_context_status_buffer = 0;
 
 	ret = i915_cmd_parser_init_ring(ring);
 	if (ret)