| Message ID | 1421110105-15451-2-git-send-email-zhipeng.gong@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 354/354 354/354
ILK 354/354 354/354
SNB +1-1 401/424 401/424
IVB 488/488 488/488
BYT 278/278 278/278
HSW -42 529/529 487/529
BDW -1 405/405 404/405
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
SNB igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible NSPT(1, M35)PASS(7, M35M22) PASS(1, M35)
*SNB igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible PASS(8, M35M22) DMESG_WARN(1, M35)
HSW igt_kms_cursor_crc_cursor-size-change NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_kms_fence_pin_leak NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_kms_flip_event_leak NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_lpsp_non-edp NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_cursor NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_cursor-dpms NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_dpms-non-lpsp NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_drm-resources-equal NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_fences NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_fences-dpms NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_gem-execbuf NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_gem-mmap-cpu NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_gem-mmap-gtt NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_gem-pread NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_i2c NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_modeset-non-lpsp NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_pci-d3-state NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_pm_rpm_rte NSPT(4, M40M19)PASS(1, M20) NSPT(1, M40)
HSW igt_gem_concurrent_blit_gtt-bcs-early-read-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-bcs-early-read-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-bcs-overwrite-source-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-bcs-overwrite-source-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-rcs-early-read-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-rcs-gpu-read-after-write-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-rcs-gpu-read-after-write-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-rcs-overwrite-source-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gtt-rcs-overwrite-source-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-bcs-early-read-interruptible DMESG_WARN(3, M40)PASS(2, M20M19) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-bcs-overwrite-source-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-bcs-overwrite-source-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-rcs-early-read-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write-interruptible DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-rcs-overwrite-source-forked DMESG_WARN(4, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
HSW igt_gem_concurrent_blit_gttX-rcs-overwrite-source-interruptible DMESG_WARN(2, M40M19)PASS(1, M20) DMESG_WARN(1, M40)
*BDW igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible PASS(7, M30M28) DMESG_WARN(1, M30)
Note: You need to pay more attention to line start with '*'
for v2 as well: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> On Mon, Jan 12, 2015 at 4:48 PM, Zhipeng Gong <zhipeng.gong@intel.com> wrote: > This will let userland only try to use the new ring > when the appropriate kernel is present > > v2: change the number to be consistent with upstream (Zhipeng) > > Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> > Reviewed--by: Rodrigo Vivi <rodrigo.vivi@intel.com> (for v1) > --- > drivers/gpu/drm/i915/i915_dma.c | 3 +++ > include/uapi/drm/i915_drm.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 8cbff30..f0786d6 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -92,6 +92,9 @@ static int i915_getparam(struct drm_device *dev, void *data, > case I915_PARAM_HAS_VEBOX: > value = intel_ring_initialized(&dev_priv->ring[VECS]); > break; > + case I915_PARAM_HAS_BSD2: > + value = intel_ring_initialized(&dev_priv->ring[VCS2]); > + break; > case I915_PARAM_HAS_RELAXED_FENCING: > value = 1; > break; > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index dc84561..6eed16b 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -346,6 +346,7 @@ typedef struct drm_i915_irq_wait { > #define I915_PARAM_CMD_PARSER_VERSION 28 > #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 > #define I915_PARAM_MMAP_VERSION 30 > +#define I915_PARAM_HAS_BSD2 31 > > typedef struct drm_i915_getparam { > int param; > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 8cbff30..f0786d6 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -92,6 +92,9 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_VEBOX: value = intel_ring_initialized(&dev_priv->ring[VECS]); break; + case I915_PARAM_HAS_BSD2: + value = intel_ring_initialized(&dev_priv->ring[VCS2]); + break; case I915_PARAM_HAS_RELAXED_FENCING: value = 1; break; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index dc84561..6eed16b 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -346,6 +346,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_CMD_PARSER_VERSION 28 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 #define I915_PARAM_MMAP_VERSION 30 +#define I915_PARAM_HAS_BSD2 31 typedef struct drm_i915_getparam { int param;
This will let userland only try to use the new ring when the appropriate kernel is present v2: change the number to be consistent with upstream (Zhipeng) Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed--by: Rodrigo Vivi <rodrigo.vivi@intel.com> (for v1) --- drivers/gpu/drm/i915/i915_dma.c | 3 +++ include/uapi/drm/i915_drm.h | 1 + 2 files changed, 4 insertions(+)