diff mbox

[10/10] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS)

Message ID 1423133245-23953-11-git-send-email-nicholas.hoath@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Nick Hoath Feb. 5, 2015, 10:47 a.m. UTC 
From: "Hoath, Nicholas" <nicholas.hoath@intel.com>

Add:
WaEnableForceRestoreInCtxtDescForVCS

v1: Add stepping check.

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

Comments

Shuang He Feb. 5, 2015, 5:27 p.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5717
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  282/283              282/283
ILK              +1                 316/319              317/319
SNB              +22-4              322/346              340/346
IVB                 -3              382/384              379/384
BYT                                  296/296              296/296
HSW                 -1              425/428              424/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt_drv_suspend_forcewake      DMESG_WARN(3, M26)      PASS(1, M26)
 SNB  igt_kms_cursor_crc_cursor-size-change      NSPT(2, M22M35)PASS(2, M35)DMESG_FAIL(1, M35)      PASS(1, M35)
 SNB  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(1, M35)PASS(1, M22)      DMESG_WARN(1, M35)
 SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(2, M35)PASS(3, M22M35)      DMESG_WARN(1, M35)
 SNB  igt_kms_flip_event_leak      NSPT(2, M22M35)PASS(3, M35)      PASS(1, M35)
 SNB  igt_kms_flip_modeset-vs-vblank-race      DMESG_WARN(1, M35)PASS(2, M22M35)      DMESG_WARN(1, M35)
 SNB  igt_kms_flip_modeset-vs-vblank-race-interruptible      DMESG_WARN(1, M35)PASS(2, M22M35)      DMESG_WARN(1, M35)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_cursor      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_fences      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_fences-dpms      NSPT(1, M22)DMESG_WARN(1, M35)PASS(2, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_gem-pread      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_i2c      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 SNB  igt_pm_rpm_rte      NSPT(1, M22)PASS(3, M35)      PASS(1, M35)
 IVB  igt_gem_pwrite_pread_snooped-copy-performance      DMESG_WARN(1, M34)PASS(2, M21M34)      DMESG_WARN(1, M34)
 IVB  igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance      DMESG_WARN(2, M34)PASS(4, M21M34)      DMESG_WARN(1, M34)
 IVB  igt_gem_storedw_batches_loop_secure-dispatch      DMESG_WARN(1, M34)PASS(4, M21M34M4)      DMESG_WARN(1, M34)
*HSW  igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance      PASS(3, M20)      DMESG_WARN(1, M20)
Note: You need to pay more attention to line start with '*'
Lespiau, Damien Feb. 5, 2015, 6:17 p.m. UTC | #2 
On Thu, Feb 05, 2015 at 10:47:25AM +0000, Nick Hoath wrote:
> From: "Hoath, Nicholas" <nicholas.hoath@intel.com>
> 
> Add:
> WaEnableForceRestoreInCtxtDescForVCS
> 
> v1: Add stepping check.
> 
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index a94346f..cb7214f 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -254,8 +254,10 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
>  	return lrca >> 12;
>  }
>  
> -static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
> +static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
> +					 struct drm_i915_gem_object *ctx_obj)
>  {
> +	struct drm_device *dev = ring->dev;
>  	uint64_t desc;
>  	uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
>  
> @@ -272,6 +274,13 @@ static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
>  	 * signalling between Command Streamers */
>  	/* desc |= GEN8_CTX_FORCE_RESTORE; */
>  
> +	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
> +	if (IS_GEN9(dev) &&
> +			INTEL_REVID(dev) >= SKL_B0_REVID &&

Shouldn't it be <= SKL_B0_REVID?

> +			(ring->id == BCS || ring->id == VCS ||
> +			ring->id == VECS || ring->id == VCS2))

Usually, we indent with the opening brace.

> +		desc |= GEN8_CTX_FORCE_RESTORE;
> +
>  	return desc;
>  }
>  
> @@ -286,13 +295,13 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,
>  
>  	/* XXX: You must always write both descriptors in the order below. */
>  	if (ctx_obj1)
> -		temp = execlists_ctx_descriptor(ctx_obj1);
> +		temp = execlists_ctx_descriptor(ring, ctx_obj1);
>  	else
>  		temp = 0;
>  	desc[1] = (u32)(temp >> 32);
>  	desc[0] = (u32)temp;
>  
> -	temp = execlists_ctx_descriptor(ctx_obj0);
> +	temp = execlists_ctx_descriptor(ring, ctx_obj0);
>  	desc[3] = (u32)(temp >> 32);
>  	desc[2] = (u32)temp;
>  
> -- 
> 2.1.1
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a94346f..cb7214f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -254,8 +254,10 @@  u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 	return lrca >> 12;
 }
 
-static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
+static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
+					 struct drm_i915_gem_object *ctx_obj)
 {
+	struct drm_device *dev = ring->dev;
 	uint64_t desc;
 	uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 
@@ -272,6 +274,13 @@  static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
 	 * signalling between Command Streamers */
 	/* desc |= GEN8_CTX_FORCE_RESTORE; */
 
+	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
+	if (IS_GEN9(dev) &&
+			INTEL_REVID(dev) >= SKL_B0_REVID &&
+			(ring->id == BCS || ring->id == VCS ||
+			ring->id == VECS || ring->id == VCS2))
+		desc |= GEN8_CTX_FORCE_RESTORE;
+
 	return desc;
 }
 
@@ -286,13 +295,13 @@  static void execlists_elsp_write(struct intel_engine_cs *ring,
 
 	/* XXX: You must always write both descriptors in the order below. */
 	if (ctx_obj1)
-		temp = execlists_ctx_descriptor(ctx_obj1);
+		temp = execlists_ctx_descriptor(ring, ctx_obj1);
 	else
 		temp = 0;
 	desc[1] = (u32)(temp >> 32);
 	desc[0] = (u32)temp;
 
-	temp = execlists_ctx_descriptor(ctx_obj0);
+	temp = execlists_ctx_descriptor(ring, ctx_obj0);
 	desc[3] = (u32)(temp >> 32);
 	desc[2] = (u32)temp;