| Message ID | 1423136325-16532-1-git-send-email-shobhit.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5718
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -8 282/283 274/283
ILK +1 316/319 317/319
SNB 322/346 322/346
IVB -1 382/384 381/384
BYT 296/296 296/296
HSW 425/428 425/428
BDW 318/333 318/333
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_fence_thrash_bo-write-verify-y PASS(2, M23M7) FAIL(1, M7)
PNV igt_gem_userptr_blits_coherency-sync CRASH(2, M7)PASS(1, M23) CRASH(1, M7)
PNV igt_gem_userptr_blits_coherency-unsync CRASH(2, M7)PASS(1, M23) CRASH(1, M7)
*PNV igt_gem_userptr_blits_forked-sync-interruptible PASS(2, M23M7) DMESG_WARN(1, M7)
*PNV igt_gem_userptr_blits_forked-sync-multifd-interruptible PASS(2, M23M7) NO_RESULT(1, M7)
PNV igt_gen3_render_linear_blits FAIL(3, M7)CRASH(1, M23)PASS(4, M25M23) FAIL(1, M7)
PNV igt_gen3_render_mixed_blits FAIL(3, M7)PASS(1, M23) FAIL(1, M7)
PNV igt_gen3_render_tiledx_blits FAIL(2, M7)PASS(1, M23) FAIL(1, M7)
PNV igt_gem_tiled_pread_pwrite FAIL(2, M7)PASS(1, M23) FAIL(1, M7)
*ILK igt_drv_suspend_forcewake DMESG_WARN(5, M26M37) PASS(1, M26)
IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(2, M34)PASS(5, M21M34) DMESG_WARN(1, M21)
Note: You need to pay more attention to line start with '*'
On 02/06/2015 01:11 AM, shuang.he@intel.com wrote: > Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) > Task id: 5718 > -------------------------------------Summary------------------------------------- > Platform Delta drm-intel-nightly Series Applied > PNV -8 282/283 274/283 > ILK +1 316/319 317/319 > SNB 322/346 322/346 > IVB -1 382/384 381/384 > BYT 296/296 296/296 > HSW 425/428 425/428 > BDW 318/333 318/333 > -------------------------------------Detailed------------------------------------- > Platform Test drm-intel-nightly Series Applied > *PNV igt_gem_fence_thrash_bo-write-verify-y PASS(2, M23M7) FAIL(1, M7) > PNV igt_gem_userptr_blits_coherency-sync CRASH(2, M7)PASS(1, M23) CRASH(1, M7) > PNV igt_gem_userptr_blits_coherency-unsync CRASH(2, M7)PASS(1, M23) CRASH(1, M7) > *PNV igt_gem_userptr_blits_forked-sync-interruptible PASS(2, M23M7) DMESG_WARN(1, M7) > *PNV igt_gem_userptr_blits_forked-sync-multifd-interruptible PASS(2, M23M7) NO_RESULT(1, M7) > PNV igt_gen3_render_linear_blits FAIL(3, M7)CRASH(1, M23)PASS(4, M25M23) FAIL(1, M7) > PNV igt_gen3_render_mixed_blits FAIL(3, M7)PASS(1, M23) FAIL(1, M7) > PNV igt_gen3_render_tiledx_blits FAIL(2, M7)PASS(1, M23) FAIL(1, M7) > PNV igt_gem_tiled_pread_pwrite FAIL(2, M7)PASS(1, M23) FAIL(1, M7) > *ILK igt_drv_suspend_forcewake DMESG_WARN(5, M26M37) PASS(1, M26) > IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(2, M34)PASS(5, M21M34) DMESG_WARN(1, M21) > Note: You need to pay more attention to line start with '*' Not sure why this is giving issues for PNV and ILK. Patch is strictly for DSI. Are you expecting me to do anything about this ? Regards Shobhit > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >
On Mon, 09 Feb 2015, Shobhit Kumar <shobhit.kumar@linux.intel.com> wrote: > On 02/06/2015 01:11 AM, shuang.he@intel.com wrote: >> Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) >> Task id: 5718 >> -------------------------------------Summary------------------------------------- >> Platform Delta drm-intel-nightly Series Applied >> PNV -8 282/283 274/283 >> ILK +1 316/319 317/319 >> SNB 322/346 322/346 >> IVB -1 382/384 381/384 >> BYT 296/296 296/296 >> HSW 425/428 425/428 >> BDW 318/333 318/333 >> -------------------------------------Detailed------------------------------------- >> Platform Test drm-intel-nightly Series Applied >> *PNV igt_gem_fence_thrash_bo-write-verify-y PASS(2, M23M7) FAIL(1, M7) >> PNV igt_gem_userptr_blits_coherency-sync CRASH(2, M7)PASS(1, M23) CRASH(1, M7) >> PNV igt_gem_userptr_blits_coherency-unsync CRASH(2, M7)PASS(1, M23) CRASH(1, M7) >> *PNV igt_gem_userptr_blits_forked-sync-interruptible PASS(2, M23M7) DMESG_WARN(1, M7) >> *PNV igt_gem_userptr_blits_forked-sync-multifd-interruptible PASS(2, M23M7) NO_RESULT(1, M7) >> PNV igt_gen3_render_linear_blits FAIL(3, M7)CRASH(1, M23)PASS(4, M25M23) FAIL(1, M7) >> PNV igt_gen3_render_mixed_blits FAIL(3, M7)PASS(1, M23) FAIL(1, M7) >> PNV igt_gen3_render_tiledx_blits FAIL(2, M7)PASS(1, M23) FAIL(1, M7) >> PNV igt_gem_tiled_pread_pwrite FAIL(2, M7)PASS(1, M23) FAIL(1, M7) >> *ILK igt_drv_suspend_forcewake DMESG_WARN(5, M26M37) PASS(1, M26) >> IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(2, M34)PASS(5, M21M34) DMESG_WARN(1, M21) >> Note: You need to pay more attention to line start with '*' > > Not sure why this is giving issues for PNV and ILK. Patch is strictly > for DSI. Are you expecting me to do anything about this ? Yes - please ignore them! ;) BR, Jani. > > Regards > Shobhit > >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, 05 Feb 2015, Shobhit Kumar <shobhit.kumar@intel.com> wrote: > LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case > of dual link. In the dual link implementation, the bit is correctly set > or unset for hardcoded PORT_A, but for bit update the register base value > is read by using MIPI_PORT_CTRL(port) in a loop. The second iteration will > read base value from PORT_C and program for PORT_A. Mostly in case of dual > link all other bit values should be same, but logically we should read from > PORT_A. So hardcode to read initial value from PORT_A as well. > > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Pushed to drm-intel-next-fixes, thanks for the patch. BR, Jani. > --- > drivers/gpu/drm/i915/intel_dsi.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 6857d19..3fe8a1e 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -177,12 +177,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); > usleep_range(2500, 3000); > > - val = I915_READ(MIPI_PORT_CTRL(port)); > - > /* Enable MIPI PHY transparent latch > * Common bit for both MIPI Port A & MIPI Port C > * No similar bit in MIPI Port C reg > */ > + val = I915_READ(MIPI_PORT_CTRL(PORT_A)); > I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > @@ -360,10 +359,10 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) > == 0x00000), 30)) > DRM_ERROR("DSI LP not going Low\n"); > > - val = I915_READ(MIPI_PORT_CTRL(port)); > /* Disable MIPI PHY transparent latch > * Common bit for both MIPI Port A & MIPI Port C > */ > + val = I915_READ(MIPI_PORT_CTRL(PORT_A)); > I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > -- > 1.9.1 >
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 6857d19..3fe8a1e 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -177,12 +177,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); usleep_range(2500, 3000); - val = I915_READ(MIPI_PORT_CTRL(port)); - /* Enable MIPI PHY transparent latch * Common bit for both MIPI Port A & MIPI Port C * No similar bit in MIPI Port C reg */ + val = I915_READ(MIPI_PORT_CTRL(PORT_A)); I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); usleep_range(1000, 1500); @@ -360,10 +359,10 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) == 0x00000), 30)) DRM_ERROR("DSI LP not going Low\n"); - val = I915_READ(MIPI_PORT_CTRL(port)); /* Disable MIPI PHY transparent latch * Common bit for both MIPI Port A & MIPI Port C */ + val = I915_READ(MIPI_PORT_CTRL(PORT_A)); I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); usleep_range(1000, 1500);
LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case of dual link. In the dual link implementation, the bit is correctly set or unset for hardcoded PORT_A, but for bit update the register base value is read by using MIPI_PORT_CTRL(port) in a loop. The second iteration will read base value from PORT_C and program for PORT_A. Mostly in case of dual link all other bit values should be same, but logically we should read from PORT_A. So hardcode to read initial value from PORT_A as well. Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)