| Message ID | 1423840286-18377-10-git-send-email-tomi.valkeinen@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 13, 2015 at 9:11 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various > subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN > bits are used by the SW via syscon. > > For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a > clock related to DSS's HDCP. If that clock is off, DSS module does not > start at all, causing OCP errors. This means that the HWMOD code is not > able to reset and initialize DSS. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > --- > arch/arm/mach-omap2/io.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c > index a1bd6affb508..2206fb13f195 100644 > --- a/arch/arm/mach-omap2/io.c > +++ b/arch/arm/mach-omap2/io.c > @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void) > dra7xx_hwmod_init(); > omap_hwmod_init_postsetup(); > omap_clk_soc_init = dra7xx_dt_clk_init; > + > + if (soc_is_dra7xx()) { Umm.. this code will only be executed for dra7xx :) > + u32 v; > + const u16 ctrl_core_control_io_2 = 0x558; > + > + /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */ > + > + v = omap_ctrl_readl(ctrl_core_control_io_2); > + v |= 1; > + omap_ctrl_writel(v, ctrl_core_control_io_2); > + } > } > > void __init dra7xx_init_late(void) just my 2 cents. I would probably wait for control module to become syscon and probably model this as syscon clk - I thin we should be seeing a series sometime soon.
On 02/13/2015 05:25 PM, Nishanth Menon wrote: > On Fri, Feb 13, 2015 at 9:11 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: >> DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various >> subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN >> bits are used by the SW via syscon. >> >> For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a >> clock related to DSS's HDCP. If that clock is off, DSS module does not >> start at all, causing OCP errors. This means that the HWMOD code is not >> able to reset and initialize DSS. >> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> >> --- >> arch/arm/mach-omap2/io.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c >> index a1bd6affb508..2206fb13f195 100644 >> --- a/arch/arm/mach-omap2/io.c >> +++ b/arch/arm/mach-omap2/io.c >> @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void) >> dra7xx_hwmod_init(); >> omap_hwmod_init_postsetup(); >> omap_clk_soc_init = dra7xx_dt_clk_init; >> + >> + if (soc_is_dra7xx()) { > > Umm.. this code will only be executed for dra7xx :) > >> + u32 v; >> + const u16 ctrl_core_control_io_2 = 0x558; >> + >> + /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */ >> + >> + v = omap_ctrl_readl(ctrl_core_control_io_2); >> + v |= 1; >> + omap_ctrl_writel(v, ctrl_core_control_io_2); >> + } >> } >> >> void __init dra7xx_init_late(void) > just my 2 cents. > I would probably wait for control module to become syscon and probably > model this as syscon clk - I thin we should be seeing a series > sometime soon. Yeah, I will be posting a series in a bit, just running some final tests on it. -Tero
On 13/02/15 17:25, Nishanth Menon wrote: > On Fri, Feb 13, 2015 at 9:11 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: >> DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various >> subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN >> bits are used by the SW via syscon. >> >> For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a >> clock related to DSS's HDCP. If that clock is off, DSS module does not >> start at all, causing OCP errors. This means that the HWMOD code is not >> able to reset and initialize DSS. >> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> >> --- >> arch/arm/mach-omap2/io.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c >> index a1bd6affb508..2206fb13f195 100644 >> --- a/arch/arm/mach-omap2/io.c >> +++ b/arch/arm/mach-omap2/io.c >> @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void) >> dra7xx_hwmod_init(); >> omap_hwmod_init_postsetup(); >> omap_clk_soc_init = dra7xx_dt_clk_init; >> + >> + if (soc_is_dra7xx()) { > > Umm.. this code will only be executed for dra7xx :) Better safe than sorry! But you're right, I'll remove the if =). >> + u32 v; >> + const u16 ctrl_core_control_io_2 = 0x558; >> + >> + /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */ >> + >> + v = omap_ctrl_readl(ctrl_core_control_io_2); >> + v |= 1; >> + omap_ctrl_writel(v, ctrl_core_control_io_2); >> + } >> } >> >> void __init dra7xx_init_late(void) > just my 2 cents. > I would probably wait for control module to become syscon and probably > model this as syscon clk - I thin we should be seeing a series > sometime soon. Yep, I hope Tero's work will make this patch not needed. I wanted to include something in this series that makes the DSS usable. Tomi
On 13/02/15 17:42, Tero Kristo wrote: > On 02/13/2015 05:25 PM, Nishanth Menon wrote: >> I would probably wait for control module to become syscon and probably >> model this as syscon clk - I thin we should be seeing a series >> sometime soon. > > Yeah, I will be posting a series in a bit, just running some final tests > on it. I did the above with Tero's series. Adding the DES HDCP clock works ok. However, I'm not able to do this in HWMOD framework. To enable the DSS IP block I need to enable both the DSS func clock and the DES HDCP clock, but the HWMOD framework only allows one mainclock. I added the HDCP clock as an opt clock, but those are not enabled intially by the HWMOD framework, and the call in omap_hwmod.c:_enable() to soc_ops.wait_target_ready(oh) calls fails. So... Any ideas how to proceed? Tomi
On 02/20/2015 01:46 PM, Tomi Valkeinen wrote: > On 13/02/15 17:42, Tero Kristo wrote: >> On 02/13/2015 05:25 PM, Nishanth Menon wrote: > >>> I would probably wait for control module to become syscon and probably >>> model this as syscon clk - I thin we should be seeing a series >>> sometime soon. >> >> Yeah, I will be posting a series in a bit, just running some final tests >> on it. > > I did the above with Tero's series. Adding the DES HDCP clock works ok. > > However, I'm not able to do this in HWMOD framework. To enable the DSS > IP block I need to enable both the DSS func clock and the DES HDCP > clock, but the HWMOD framework only allows one mainclock. > > I added the HDCP clock as an opt clock, but those are not enabled > intially by the HWMOD framework, and the call in omap_hwmod.c:_enable() > to soc_ops.wait_target_ready(oh) calls fails. > > So... Any ideas how to proceed? Add the clock enable at the end of dra7xx_dt_clk_init()? You need to disable the clock at some point though. -Tero
On 20/02/15 14:59, Tero Kristo wrote: > On 02/20/2015 01:46 PM, Tomi Valkeinen wrote: >> On 13/02/15 17:42, Tero Kristo wrote: >>> On 02/13/2015 05:25 PM, Nishanth Menon wrote: >> >>>> I would probably wait for control module to become syscon and probably >>>> model this as syscon clk - I thin we should be seeing a series >>>> sometime soon. >>> >>> Yeah, I will be posting a series in a bit, just running some final tests >>> on it. >> >> I did the above with Tero's series. Adding the DES HDCP clock works ok. >> >> However, I'm not able to do this in HWMOD framework. To enable the DSS >> IP block I need to enable both the DSS func clock and the DES HDCP >> clock, but the HWMOD framework only allows one mainclock. >> >> I added the HDCP clock as an opt clock, but those are not enabled >> intially by the HWMOD framework, and the call in omap_hwmod.c:_enable() >> to soc_ops.wait_target_ready(oh) calls fails. >> >> So... Any ideas how to proceed? > > Add the clock enable at the end of dra7xx_dt_clk_init()? > > You need to disable the clock at some point though. Where would I disable it? And if the clock is disabled, doesn't this again fail when the dss driver tries to enable the IP block? The driver can enable the HDCP opt clock only later, when the IP block should be up already. Tomi
On 02/20/2015 03:48 PM, Tomi Valkeinen wrote: > On 20/02/15 14:59, Tero Kristo wrote: >> On 02/20/2015 01:46 PM, Tomi Valkeinen wrote: >>> On 13/02/15 17:42, Tero Kristo wrote: >>>> On 02/13/2015 05:25 PM, Nishanth Menon wrote: >>> >>>>> I would probably wait for control module to become syscon and probably >>>>> model this as syscon clk - I thin we should be seeing a series >>>>> sometime soon. >>>> >>>> Yeah, I will be posting a series in a bit, just running some final tests >>>> on it. >>> >>> I did the above with Tero's series. Adding the DES HDCP clock works ok. >>> >>> However, I'm not able to do this in HWMOD framework. To enable the DSS >>> IP block I need to enable both the DSS func clock and the DES HDCP >>> clock, but the HWMOD framework only allows one mainclock. >>> >>> I added the HDCP clock as an opt clock, but those are not enabled >>> intially by the HWMOD framework, and the call in omap_hwmod.c:_enable() >>> to soc_ops.wait_target_ready(oh) calls fails. >>> >>> So... Any ideas how to proceed? >> >> Add the clock enable at the end of dra7xx_dt_clk_init()? >> >> You need to disable the clock at some point though. > > Where would I disable it? And if the clock is disabled, doesn't this > again fail when the dss driver tries to enable the IP block? The driver > can enable the HDCP opt clock only later, when the IP block should be up > already. I guess in the display driver itself. -Tero
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a1bd6affb508..2206fb13f195 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void) dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dra7xx_dt_clk_init; + + if (soc_is_dra7xx()) { + u32 v; + const u16 ctrl_core_control_io_2 = 0x558; + + /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */ + + v = omap_ctrl_readl(ctrl_core_control_io_2); + v |= 1; + omap_ctrl_writel(v, ctrl_core_control_io_2); + } } void __init dra7xx_init_late(void)
DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN bits are used by the SW via syscon. For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a clock related to DSS's HDCP. If that clock is off, DSS module does not start at all, causing OCP errors. This means that the HWMOD code is not able to reset and initialize DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> --- arch/arm/mach-omap2/io.c | 11 +++++++++++ 1 file changed, 11 insertions(+)