diff mbox

[4/4] drm/i915/skl: Program PLL for edp1.4 intermediate frequencies

Message ID 1424497333-1393-5-git-send-email-sonika.jindal@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sonika.jindal@intel.com Feb. 21, 2015, 5:42 a.m. UTC 
v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
(Ville)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |   28 ++++++++++++++++++++++------
 1 file changed, 22 insertions(+), 6 deletions(-)

Comments

Shuang He Feb. 21, 2015, 8:23 a.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5802
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -5              277/277              272/277
ILK                                  313/313              313/313
SNB                                  309/309              309/309
IVB                                  382/382              382/382
BYT                                  296/296              296/296
HSW                                  425/425              425/425
BDW                 -1              318/318              317/318
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_fence_thrash_bo-write-verify-none      NRUN(1)PASS(6)      FAIL(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-x      PASS(7)      FAIL(1)NO_RESULT(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-y      NO_RESULT(1)PASS(7)      FAIL(1)NO_RESULT(1)
 PNV  igt_gem_userptr_blits_coherency-sync      NO_RESULT(1)CRASH(6)NRUN(1)PASS(6)      NO_RESULT(1)CRASH(1)
*PNV  igt_gem_userptr_blits_coherency-unsync      CRASH(4)NRUN(1)PASS(4)      NO_RESULT(1)CRASH(1)
*BDW  igt_gem_gtt_hog      PASS(19)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
Ville Syrjälä March 4, 2015, 11:25 a.m. UTC | #2 
On Sat, Feb 21, 2015 at 11:12:13AM +0530, Sonika Jindal wrote:
> v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
> (Ville)
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c |   28 ++++++++++++++++++++++------
>  1 file changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cf7a0f5..62bc6c1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1079,7 +1079,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
>  }
>  
>  static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
> +skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  {
>  	u32 ctrl1;
>  
> @@ -1088,19 +1088,35 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
>  	pipe_config->dpll_hw_state.cfgcr2 = 0;
>  
>  	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> -	switch (link_bw) {
> -	case DP_LINK_BW_1_62:
> +	switch (link_clock / 2) {
> +	case 81000:
>  		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
>  					      SKL_DPLL0);
>  		break;
> -	case DP_LINK_BW_2_7:
> +	case 135000:
>  		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
>  					      SKL_DPLL0);
>  		break;
> -	case DP_LINK_BW_5_4:
> +	case 270000:
>  		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
>  					      SKL_DPLL0);
>  		break;
> +	case 162000:
> +		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
> +					      SKL_DPLL0);
> +		break;
> +	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
> +	results in CDCLK change. Need to handle the change of CDCLK by
> +	disabling pipes and re-enabling them */
> +	case 108000:
> +		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
> +					      SKL_DPLL0);
> +		break;
> +	case 216000:
> +		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
> +					      SKL_DPLL0);
> +		break;
> +
>  	}
>  	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>  }
> @@ -1395,7 +1411,7 @@ found:
>  	}
>  
>  	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> -		skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
> +		skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
>  	else
> -- 
> 1.7.10.4
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cf7a0f5..62bc6c1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1079,7 +1079,7 @@  intel_dp_connector_unregister(struct intel_connector *intel_connector)
 }
 
 static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
+skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 {
 	u32 ctrl1;
 
@@ -1088,19 +1088,35 @@  skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
 	pipe_config->dpll_hw_state.cfgcr2 = 0;
 
 	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-	switch (link_bw) {
-	case DP_LINK_BW_1_62:
+	switch (link_clock / 2) {
+	case 81000:
 		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
 					      SKL_DPLL0);
 		break;
-	case DP_LINK_BW_2_7:
+	case 135000:
 		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
 					      SKL_DPLL0);
 		break;
-	case DP_LINK_BW_5_4:
+	case 270000:
 		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
 					      SKL_DPLL0);
 		break;
+	case 162000:
+		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
+					      SKL_DPLL0);
+		break;
+	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
+	results in CDCLK change. Need to handle the change of CDCLK by
+	disabling pipes and re-enabling them */
+	case 108000:
+		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
+					      SKL_DPLL0);
+		break;
+	case 216000:
+		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
+					      SKL_DPLL0);
+		break;
+
 	}
 	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
 }
@@ -1395,7 +1411,7 @@  found:
 	}
 
 	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
-		skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
+		skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 	else