| Message ID | 3082195.zNdUtZ8oMM@wasted.cogentembedded.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Sat, Feb 21, 2015 at 11:12 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe GPIO[0-6] controllers in the R8A7794 device tree. > > Based on original patch by Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-?by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sergei, Thank you for the patch. On Sunday 22 February 2015 01:12:31 Sergei Shtylyov wrote: > Describe GPIO[0-6] controllers in the R8A7794 device tree. > > Based on original patch by Hisashi Nakamura > <hisashi.nakamura.ak@renesas.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > --- > arch/arm/boot/dts/r8a7794.dtsi | 84 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 84 insertions(+) > > Index: renesas/arch/arm/boot/dts/r8a7794.dtsi > =================================================================== > --- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi > +++ renesas/arch/arm/boot/dts/r8a7794.dtsi > @@ -50,6 +50,90 @@ > interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > }; > > + gpio0: gpio@e6050000 { > + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > + reg = <0 0xe6050000 0 0x50>; > + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 0 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; > + }; > + > + gpio1: gpio@e6051000 { > + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > + reg = <0 0xe6051000 0 0x50>; > + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 32 32>; This GPIO block has 26 GPIOs only. > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; > + }; > + > + gpio2: gpio@e6052000 { > + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > + reg = <0 0xe6052000 0 0x50>; > + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 64 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; > + }; > + > + gpio3: gpio@e6053000 { > + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > + reg = <0 0xe6053000 0 0x50>; > + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 96 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; > + }; > + > + gpio4: gpio@e6054000 { > + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > + reg = <0 0xe6054000 0 0x50>; > + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 128 32>; > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; > + }; > + > + gpio5: gpio@e6055000 { > + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > + reg = <0 0xe6055000 0 0x50>; > + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 160 32>; This GPIO block has 28 GPIOs only. > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; > + }; > + > + gpio6: gpio@e6055400 { > + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > + reg = <0 0xe6055400 0 0x50>; > + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&pfc 0 192 32>; This GPIO block has 26 GPIOs only. > + #interrupt-cells = <2>; > + interrupt-controller; > + clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; > + }; > + > cmt0: timer@ffca0000 { > compatible = "renesas,cmt-48-gen2"; > reg = <0 0xffca0000 0 0x1004>;
Hi Laurent, On Wed, Feb 25, 2015 at 11:11 AM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: >> --- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi >> +++ renesas/arch/arm/boot/dts/r8a7794.dtsi >> @@ -50,6 +50,90 @@ >> + gpio1: gpio@e6051000 { >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; >> + reg = <0 0xe6051000 0 0x50>; >> + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; >> + #gpio-cells = <2>; >> + gpio-controller; >> + gpio-ranges = <&pfc 0 32 32>; > > This GPIO block has 26 GPIOs only. >> + gpio5: gpio@e6055000 { >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; >> + reg = <0 0xe6055000 0 0x50>; >> + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; >> + #gpio-cells = <2>; >> + gpio-controller; >> + gpio-ranges = <&pfc 0 160 32>; > > This GPIO block has 28 GPIOs only. >> + gpio6: gpio@e6055400 { >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; >> + reg = <0 0xe6055400 0 0x50>; >> + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; >> + #gpio-cells = <2>; >> + gpio-controller; >> + gpio-ranges = <&pfc 0 192 32>; > > This GPIO block has 26 GPIOs only. I guess you hear me coming... r8a779[01].dtsi need to be fixed, too. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello. On 2/25/2015 1:11 PM, Laurent Pinchart wrote: >> Describe GPIO[0-6] controllers in the R8A7794 device tree. >> Based on original patch by Hisashi Nakamura >> <hisashi.nakamura.ak@renesas.com>. >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> --- >> arch/arm/boot/dts/r8a7794.dtsi | 84 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 84 insertions(+) >> >> Index: renesas/arch/arm/boot/dts/r8a7794.dtsi >> =================================================================== >> --- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi >> +++ renesas/arch/arm/boot/dts/r8a7794.dtsi >> @@ -50,6 +50,90 @@ [...] >> + gpio1: gpio@e6051000 { >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; >> + reg = <0 0xe6051000 0 0x50>; >> + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; >> + #gpio-cells = <2>; >> + gpio-controller; >> + gpio-ranges = <&pfc 0 32 32>; > This GPIO block has 26 GPIOs only. [...] >> + gpio5: gpio@e6055000 { >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; >> + reg = <0 0xe6055000 0 0x50>; >> + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; >> + #gpio-cells = <2>; >> + gpio-controller; >> + gpio-ranges = <&pfc 0 160 32>; > This GPIO block has 28 GPIOs only. >> + #interrupt-cells = <2>; >> + interrupt-controller; >> + clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; >> + }; >> + >> + gpio6: gpio@e6055400 { >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; >> + reg = <0 0xe6055400 0 0x50>; >> + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; >> + #gpio-cells = <2>; >> + gpio-controller; >> + gpio-ranges = <&pfc 0 192 32>; > This GPIO block has 26 GPIOs only. Yes, I know; I just wasn't sure what to do with the "gpio-ranges" prop of the following GPIO node. Should I keep the base GPIO # or update it as well? WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sergei, On Wednesday 25 February 2015 17:04:53 Sergei Shtylyov wrote: > On 2/25/2015 1:11 PM, Laurent Pinchart wrote: > >> Describe GPIO[0-6] controllers in the R8A7794 device tree. > >> > >> Based on original patch by Hisashi Nakamura > >> <hisashi.nakamura.ak@renesas.com>. > >> > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > >> > >> --- > >> > >> arch/arm/boot/dts/r8a7794.dtsi | 84 +++++++++++++++++++++++++++++++++ > >> 1 file changed, 84 insertions(+) > >> > >> Index: renesas/arch/arm/boot/dts/r8a7794.dtsi > >> =================================================================== > >> --- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi > >> +++ renesas/arch/arm/boot/dts/r8a7794.dtsi > >> @@ -50,6 +50,90 @@ > > [...] > > >> + gpio1: gpio@e6051000 { > >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > >> + reg = <0 0xe6051000 0 0x50>; > >> + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; > >> + #gpio-cells = <2>; > >> + gpio-controller; > >> + gpio-ranges = <&pfc 0 32 32>; > > > > This GPIO block has 26 GPIOs only. > > [...] > > >> + gpio5: gpio@e6055000 { > >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > >> + reg = <0 0xe6055000 0 0x50>; > >> + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; > >> + #gpio-cells = <2>; > >> + gpio-controller; > >> + gpio-ranges = <&pfc 0 160 32>; > > > > This GPIO block has 28 GPIOs only. > > > >> + #interrupt-cells = <2>; > >> + interrupt-controller; > >> + clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; > >> + }; > >> + > >> + gpio6: gpio@e6055400 { > >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > >> + reg = <0 0xe6055400 0 0x50>; > >> + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; > >> + #gpio-cells = <2>; > >> + gpio-controller; > >> + gpio-ranges = <&pfc 0 192 32>; > > > > This GPIO block has 26 GPIOs only. > > Yes, I know; I just wasn't sure what to do with the "gpio-ranges" prop of > the following GPIO node. Should I keep the base GPIO # or update it as well? I think the base number should be kept as-is, as the pfc driver indexes GPIOs using 32 * bank + offset. There are thus holes in the pfc pins array, but that shouldn't be a big deal (of course if you can find an easy way to optimize that, it would be welcome :-)).
Hi Geert, On Wednesday 25 February 2015 11:27:37 Geert Uytterhoeven wrote: > On Wed, Feb 25, 2015 at 11:11 AM, Laurent Pinchart wrote: > >> --- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi > >> +++ renesas/arch/arm/boot/dts/r8a7794.dtsi > >> @@ -50,6 +50,90 @@ > >> > >> + gpio1: gpio@e6051000 { > >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > >> + reg = <0 0xe6051000 0 0x50>; > >> + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; > >> + #gpio-cells = <2>; > >> + gpio-controller; > >> + gpio-ranges = <&pfc 0 32 32>; > > > > This GPIO block has 26 GPIOs only. > > > >> + gpio5: gpio@e6055000 { > >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > >> + reg = <0 0xe6055000 0 0x50>; > >> + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; > >> + #gpio-cells = <2>; > >> + gpio-controller; > >> + gpio-ranges = <&pfc 0 160 32>; > > > > This GPIO block has 28 GPIOs only. > > > >> + gpio6: gpio@e6055400 { > >> + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; > >> + reg = <0 0xe6055400 0 0x50>; > >> + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; > >> + #gpio-cells = <2>; > >> + gpio-controller; > >> + gpio-ranges = <&pfc 0 192 32>; > > > > This GPIO block has 26 GPIOs only. > > I guess you hear me coming... r8a779[01].dtsi need to be fixed, too. Yes. We're first investigating issues in the pfc driver and/or pinctrl core due to holes in GPIO banks pins though.
Index: renesas/arch/arm/boot/dts/r8a7794.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi +++ renesas/arch/arm/boot/dts/r8a7794.dtsi @@ -50,6 +50,90 @@ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; + }; + cmt0: timer@ffca0000 { compatible = "renesas,cmt-48-gen2"; reg = <0 0xffca0000 0 0x1004>;
Describe GPIO[0-6] controllers in the R8A7794 device tree. Based on original patch by Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7794.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html