@@ -311,6 +311,7 @@ choice
config ARCH_MULTIPLATFORM
bool "Allow multiple platforms to be selected"
+ select ARCH_HAS_RESET_CONTROLLER
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
@@ -1,6 +1,5 @@
menuconfig ARCH_BERLIN
bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
- select ARCH_HAS_RESET_CONTROLLER
select ARCH_REQUIRE_GPIOLIB
select ARM_GIC
select DW_APB_ICTL
@@ -56,7 +56,6 @@ config HAVE_IMX_MMDC
config HAVE_IMX_SRC
def_bool y if SMP
- select ARCH_HAS_RESET_CONTROLLER
config IMX_HAVE_IOMUX_V1
bool
@@ -91,6 +91,7 @@ config MACH_MMP_DT
select PINCTRL_SINGLE
select COMMON_CLK
select ARCH_HAS_RESET_CONTROLLER
+ select RESET_CONTROLLER
select CPU_MOHAWK
help
Include support for Marvell MMP2 based platforms using
@@ -105,6 +106,7 @@ config MACH_MMP2_DT
select PINCTRL_SINGLE
select COMMON_CLK
select ARCH_HAS_RESET_CONTROLLER
+ select RESET_CONTROLLER
select CPU_PJ4
help
Include support for Marvell MMP2 based platforms using
@@ -1,6 +1,5 @@
menuconfig ARCH_SIRF
bool "CSR SiRF" if ARCH_MULTI_V7
- select ARCH_HAS_RESET_CONTROLLER
select ARCH_REQUIRE_GPIOLIB
select GENERIC_IRQ_CHIP
select NO_IOPORT_MAP
@@ -2,7 +2,6 @@ config ARCH_ROCKCHIP
bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
select PINCTRL
select PINCTRL_ROCKCHIP
- select ARCH_HAS_RESET_CONTROLLER
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_GIC
@@ -12,6 +11,7 @@ config ARCH_ROCKCHIP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
select REGULATOR if PM
+ select RESET_CONTROLLER
select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
@@ -5,7 +5,6 @@ menuconfig ARCH_STI
select PINCTRL
select PINCTRL_ST
select MFD_SYSCON
- select ARCH_HAS_RESET_CONTROLLER
select HAVE_ARM_SCU if SMP
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_754322
@@ -13,7 +12,6 @@ menuconfig ARCH_STI
select ARM_ERRATA_775420
select PL310_ERRATA_753970 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
- select RESET_CONTROLLER
help
Include support for STiH41x SOCs like STiH415/416 using the device tree
for discovery
@@ -1,13 +1,11 @@
menuconfig ARCH_SUNXI
bool "Allwinner SoCs" if ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB
- select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select PINCTRL
select RESET_CONTROLLER
select SUN4I_TIMER
- select RESET_CONTROLLER
if ARCH_SUNXI
@@ -44,7 +44,7 @@ extern void __init sun6i_reset_init(void);
static void __init sun6i_timer_init(void)
{
of_clk_init(NULL);
- if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+ if (IS_ENABLED(CONFIG_RESET_SUNXI))
sun6i_reset_init();
clocksource_of_init();
}
@@ -8,7 +8,6 @@ menuconfig ARCH_TEGRA
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PINCTRL
- select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
select SOC_BUS
select USB_ULPI if USB_PHY
@@ -403,7 +403,6 @@ config XILINX_VDMA
config DMA_SUN6I
tristate "Allwinner A31 SoCs DMA support"
depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST
- depends on RESET_CONTROLLER
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
@@ -1,7 +1,6 @@
config DRM_ROCKCHIP
tristate "DRM Support for Rockchip"
depends on DRM && ROCKCHIP_IOMMU
- depends on RESET_CONTROLLER
select DRM_KMS_HELPER
select DRM_KMS_FB_HELPER
select DRM_PANEL
@@ -1,7 +1,6 @@
config DRM_STI
tristate "DRM Support for STMicroelectronics SoC stiH41x Series"
depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM) && HAVE_DMA_ATTRS
- depends on RESET_CONTROLLER
select DRM_KMS_HELPER
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
@@ -3,7 +3,6 @@ config DRM_TEGRA
depends on ARCH_TEGRA || (ARM && COMPILE_TEST)
depends on COMMON_CLK
depends on DRM
- depends on RESET_CONTROLLER
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL
@@ -1,7 +1,6 @@
config IMX_IPUV3_CORE
tristate "IPUv3 core support"
depends on SOC_IMX5 || SOC_IMX6Q || ARCH_MULTIPLATFORM
- depends on RESET_CONTROLLER
select GENERIC_IRQ_CHIP
help
Choose this if you have a i.MX5/6 system and want to use the Image
@@ -829,7 +829,6 @@ config I2C_STU300
config I2C_SUN6I_P2WI
tristate "Allwinner sun6i internal P2WI controller"
- depends on RESET_CONTROLLER
depends on MACH_SUN6I || COMPILE_TEST
help
If you say yes to this option, support will be included for the
@@ -1,7 +1,6 @@
config STMMAC_ETH
tristate "STMicroelectronics 10/100/1000 Ethernet driver"
depends on HAS_IOMEM && HAS_DMA
- depends on RESET_CONTROLLER
select MII
select PHYLIB
select CRC32
@@ -17,7 +17,8 @@ config GENERIC_PHY
config PHY_BERLIN_USB
tristate "Marvell Berlin USB PHY Driver"
- depends on ARCH_BERLIN && RESET_CONTROLLER && HAS_IOMEM && OF
+ depends on ARCH_BERLIN || COMPILE_TEST
+ depends on HAS_IOMEM && OF
select GENERIC_PHY
help
Enable this to support the USB PHY on Marvell Berlin SoCs.
@@ -164,8 +165,8 @@ config PHY_HIX5HD2_SATA
config PHY_SUN4I_USB
tristate "Allwinner sunxi SoC USB PHY driver"
- depends on ARCH_SUNXI && HAS_IOMEM && OF
- depends on RESET_CONTROLLER
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on HAS_IOMEM && OF
select GENERIC_PHY
help
Enable this to support the transceiver that is part of Allwinner
@@ -269,7 +270,6 @@ config PHY_XGENE
config PHY_STIH407_USB
tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
- depends on RESET_CONTROLLER
depends on ARCH_STI || COMPILE_TEST
select GENERIC_PHY
help
@@ -27,7 +27,6 @@ config PINCTRL_SUN6I_A31S
config PINCTRL_SUN6I_A31_R
def_bool MACH_SUN6I
- depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
config PINCTRL_SUN7I_A20
@@ -40,7 +39,6 @@ config PINCTRL_SUN8I_A23
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
- depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
config PINCTRL_SUN9I_A80
@@ -1,15 +1,24 @@
-config ARCH_HAS_RESET_CONTROLLER
+config RESET_CONTROLLER
bool
-menuconfig RESET_CONTROLLER
- bool "Reset Controller Support"
- default y if ARCH_HAS_RESET_CONTROLLER
- help
- Generic Reset Controller support.
+menu "Reset Controller Support"
+ depends on ARCH_HAS_RESET_CONTROLLER || COMPILE_TEST
- This framework is designed to abstract reset handling of devices
- via GPIOs or SoC-internal reset controller modules.
+config RESET_SOCFPGA
+ bool "Altera SOCFPGA reset controller" if COMPILE_TEST
+ default ARCH_SOCFPGA
+ select RESET_CONTROLLER
- If unsure, say no.
+config RESET_BERLIN
+ bool "Marvell Berlin reset controller" if COMPILE_TEST
+ default ARCH_BERLIN
+ select RESET_CONTROLLER
+
+config RESET_SUNXI
+ bool "Allwinner reset controller" if COMPILE_TEST
+ default ARCH_SUNXI
+ select RESET_CONTROLLER
source "drivers/reset/sti/Kconfig"
+
+endmenu
@@ -1,5 +1,5 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
-obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
-obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
-obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
-obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
+obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_RESET_STI_SYSCFG) += sti/
@@ -1,19 +1,19 @@
-if ARCH_STI
+if ARCH_STI || COMPILE_TEST
-config STI_RESET_SYSCFG
+config RESET_STI_SYSCFG
bool
select RESET_CONTROLLER
-config STIH415_RESET
- bool
- select STI_RESET_SYSCFG
+config RESET_STIH415
+ bool "STmicroelectronics STiH415 reset controller" if COMPILE_TEST
+ select RESET_STI_SYSCFG
-config STIH416_RESET
- bool
- select STI_RESET_SYSCFG
+config RESET_STIH416
+ bool "STmicroelectronics STiH416 reset controller" if COMPILE_TEST
+ select RESET_STI_SYSCFG
-config STIH407_RESET
- bool
- select STI_RESET_SYSCFG
+config RESET_STIH407
+ bool "STmicroelectronics STiH407 reset controller" if COMPILE_TEST
+ select RESET_STI_SYSCFG
endif
@@ -1,5 +1,5 @@
-obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
+obj-$(CONFIG_RESET_STI_SYSCFG) += reset-syscfg.o
-obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
-obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
-obj-$(CONFIG_STIH407_RESET) += reset-stih407.o
+obj-$(CONFIG_RESET_STIH415) += reset-stih415.o
+obj-$(CONFIG_RESET_STIH416) += reset-stih416.o
+obj-$(CONFIG_RESET_STIH407) += reset-stih407.o
@@ -507,7 +507,6 @@ config SPI_SH_HSPI
config SPI_SIRF
tristate "CSR SiRFprimaII SPI controller"
depends on SIRF_DMA
- depends on RESET_CONTROLLER
select SPI_BITBANG
help
SPI driver for CSR SiRFprimaII SoCs
@@ -528,7 +527,6 @@ config SPI_SUN4I
config SPI_SUN6I
tristate "Allwinner A31 SPI controller"
depends on ARCH_SUNXI || COMPILE_TEST
- depends on RESET_CONTROLLER
help
This enables using the SPI controller on the Allwinner A31 SoCs.
@@ -542,7 +540,7 @@ config SPI_MXS
config SPI_TEGRA114
tristate "NVIDIA Tegra114 SPI Controller"
depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
- depends on RESET_CONTROLLER && HAS_DMA
+ depends on HAS_DMA
help
SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
is different than the older SoCs SPI controller and also register interface
@@ -551,7 +549,6 @@ config SPI_TEGRA114
config SPI_TEGRA20_SFLASH
tristate "Nvidia Tegra20 Serial flash Controller"
depends on ARCH_TEGRA || COMPILE_TEST
- depends on RESET_CONTROLLER
help
SPI driver for Nvidia Tegra20 Serial flash Controller interface.
The main usecase of this controller is to use spi flash as boot
@@ -560,7 +557,7 @@ config SPI_TEGRA20_SFLASH
config SPI_TEGRA20_SLINK
tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
- depends on RESET_CONTROLLER && HAS_DMA
+ depends on HAS_DMA
help
SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
@@ -157,8 +157,7 @@ config SPEAR_THERMAL
config ROCKCHIP_THERMAL
tristate "Rockchip thermal driver"
- depends on ARCH_ROCKCHIP
- depends on RESET_CONTROLLER
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
help
Rockchip thermal driver provides support for Temperature sensor
ADC (TS-ADC) found on Rockchip SoCs. It supports one critical
@@ -140,7 +140,6 @@ config USB_ISP1301
config USB_MSM_OTG
tristate "Qualcomm on-chip USB OTG controller support"
depends on (USB || USB_GADGET) && (ARCH_MSM || ARCH_QCOM || COMPILE_TEST)
- depends on RESET_CONTROLLER
select USB_PHY
help
Enable this to support the USB OTG transceiver on Qualcomm chips. It
@@ -40,50 +40,73 @@ struct reset_control *of_reset_control_get(struct device_node *node,
#else
+static inline struct reset_control *reset_control_get(struct device *dev, const char *id)
+{
+ return ERR_PTR(-ENOSYS);
+}
+
+static inline struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
+{
+ return ERR_PTR(-ENOSYS);
+}
+
+static inline int __must_check device_reset(struct device *dev)
+{
+ return -ENOSYS;
+}
+
static inline int reset_control_reset(struct reset_control *rstc)
{
- WARN_ON(1);
+ WARN_ON(rstc != NULL);
return 0;
}
static inline int reset_control_assert(struct reset_control *rstc)
{
- WARN_ON(1);
+ WARN_ON(rstc != NULL);
return 0;
}
static inline int reset_control_deassert(struct reset_control *rstc)
{
- WARN_ON(1);
+ WARN_ON(rstc != NULL);
return 0;
}
static inline int reset_control_status(struct reset_control *rstc)
{
- WARN_ON(1);
+ WARN_ON(rstc != NULL);
return 0;
}
static inline void reset_control_put(struct reset_control *rstc)
{
- WARN_ON(1);
+ WARN_ON(rstc != NULL);
}
static inline int device_reset_optional(struct device *dev)
{
- return -ENOSYS;
+ if (of_property_read_bool(dev->of_node, "resets"))
+ return -ENOSYS;
+
+ return 0;
}
+/*
+ * We intentionally return NULL here when no resets are specified
+ * or when building without DT, which is interpreted as 'success'
+ * if reset controller support is left out from the kernel.
+ */
static inline struct reset_control *reset_control_get_optional(
struct device *dev, const char *id)
{
- return ERR_PTR(-ENOSYS);
+ return ERR_PTR(device_reset_optional(dev));
}
static inline struct reset_control *devm_reset_control_get_optional(
struct device *dev, const char *id)
{
- return ERR_PTR(-ENOSYS);
+ return reset_control_get_optional(dev, id);
}
static inline struct reset_control *of_reset_control_get(
@@ -2,7 +2,6 @@ config SND_SOC_TEGRA
tristate "SoC Audio for the Tegra System-on-Chip"
depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
depends on COMMON_CLK
- depends on RESET_CONTROLLER
select REGMAP_MMIO
select SND_SOC_GENERIC_DMAENGINE_PCM
help