diff mbox

[3/8] drm/i915/skl: Updated the gen6_init_rps_frequencies function

Message ID 1424954986-24450-4-git-send-email-akash.goel@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

akash.goel@intel.com Feb. 26, 2015, 12:49 p.m. UTC
From: Akash Goel <akash.goel@intel.com>

On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual hardware unit.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Ville Syrjälä March 5, 2015, 10:14 a.m. UTC | #1
On Thu, Feb 26, 2015 at 06:19:39PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL the frequency is specified in units of 16.66 MHZ, barring the
> RP_STATE_CAP(0x5998) register, which still reports frequency in units
> of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
> function for SKL, to store the frequency values as per the actual hardware unit.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1b36d0e..9dcfca6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4032,6 +4032,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
>  	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
>  	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
>  	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
> +	if (IS_SKYLAKE(dev)) {
> +		/* Store the frequency values in 16.66 MHZ units, which is
> +		   the natural hardware unit for SKL */
> +		dev_priv->rps.rp0_freq /= GEN9_FREQ_SCALER;
> +		dev_priv->rps.rp1_freq /= GEN9_FREQ_SCALER;
> +		dev_priv->rps.min_freq /= GEN9_FREQ_SCALER;
> +	}

Shouldn't these be multiplied instead of divided?

>  	/* hw_max = RP0 until we check for overclocking */
>  	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
>  
> -- 
> 1.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
akash.goel@intel.com March 5, 2015, 10:26 a.m. UTC | #2
On Thu, 2015-03-05 at 12:14 +0200, Ville Syrjälä wrote:
> On Thu, Feb 26, 2015 at 06:19:39PM +0530, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > On SKL the frequency is specified in units of 16.66 MHZ, barring the
> > RP_STATE_CAP(0x5998) register, which still reports frequency in units
> > of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
> > function for SKL, to store the frequency values as per the actual hardware unit.
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 1b36d0e..9dcfca6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4032,6 +4032,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
> >  	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
> >  	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
> >  	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
> > +	if (IS_SKYLAKE(dev)) {
> > +		/* Store the frequency values in 16.66 MHZ units, which is
> > +		   the natural hardware unit for SKL */
> > +		dev_priv->rps.rp0_freq /= GEN9_FREQ_SCALER;
> > +		dev_priv->rps.rp1_freq /= GEN9_FREQ_SCALER;
> > +		dev_priv->rps.min_freq /= GEN9_FREQ_SCALER;
> > +	}
> 
> Shouldn't these be multiplied instead of divided?
So sorry for this blooper, thanks for spotting it.
Did it correctly in debugfs but faltered here. 
> 
> >  	/* hw_max = RP0 until we check for overclocking */
> >  	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
> >  
> > -- 
> > 1.9.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1b36d0e..9dcfca6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4032,6 +4032,13 @@  static void gen6_init_rps_frequencies(struct drm_device *dev)
 	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
 	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
 	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
+	if (IS_SKYLAKE(dev)) {
+		/* Store the frequency values in 16.66 MHZ units, which is
+		   the natural hardware unit for SKL */
+		dev_priv->rps.rp0_freq /= GEN9_FREQ_SCALER;
+		dev_priv->rps.rp1_freq /= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq /= GEN9_FREQ_SCALER;
+	}
 	/* hw_max = RP0 until we check for overclocking */
 	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;