diff mbox

drm/i915/skl: Read sink supported rates from edp panel

Message ID 1425530038-9712-1-git-send-email-sonika.jindal@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sonika.jindal@intel.com March 5, 2015, 4:33 a.m. UTC 
v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
v3: Reading dpcd's supported link rates tables based upon edp version in the
same patch.
v4: Move version check under is_edp (Satheesh)
v5: Using le16 for rates, some naming, and removing nested if block (Ville)
v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES
(Ville)
v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it
v8: Checking return value of intel_dp_dpcd_read_wake() (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |   38 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |    1 +
 2 files changed, 39 insertions(+)

Comments

Shuang He March 5, 2015, 1:11 p.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5892
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  280/280              280/280
ILK                                  308/308              308/308
SNB                 -21              328/328              307/328
IVB                                  379/379              379/379
BYT                                  294/294              294/294
HSW                                  387/387              387/387
BDW                 -1              316/316              315/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 SNB  igt_kms_cursor_crc_cursor-size-change      NSPT(1)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(2)DMESG_WARN(1)PASS(4)      NSPT(2)
 SNB  igt_pm_rpm_cursor      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_fences      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_fences-dpms      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-pread      NSPT(2)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_i2c      NSPT(2)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(2)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(2)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(2)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_rte      NSPT(2)DMESG_WARN(1)PASS(1)      NSPT(2)
*BDW  igt_gem_gtt_hog      PASS(6)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d1141d3..0ae8454 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1117,6 +1117,33 @@  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
 	}
 }
 
+static int
+intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	int i = 0;
+	uint16_t val;
+
+	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+		/*
+		 * Receiver supports only main-link rate selection by
+		 * link rate table method, so read link rates from
+		 * supported_link_rates
+		 */
+		for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
+			val = le16_to_cpu(intel_dp->supported_rates[i]);
+			if (val == 0)
+				break;
+
+			sink_rates[i] = val * 200;
+		}
+
+		if (i <= 0)
+			DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
+	}
+	return i;
+}
+
 static void
 intel_dp_set_clock(struct intel_encoder *encoder,
 		   struct intel_crtc_state *pipe_config, int link_bw)
@@ -3578,6 +3605,7 @@  intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint8_t rev;
 
 	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
 				    sizeof(intel_dp->dpcd)) < 0)
@@ -3609,6 +3637,16 @@  intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	} else
 		intel_dp->use_tps3 = false;
 
+	/* Intermediate frequency support */
+	if (is_edp(intel_dp) &&
+	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
+	    (rev >= 0x03)) { /* eDp v1.4 or higher */
+		intel_dp_dpcd_read_wake(&intel_dp->aux,
+				DP_SUPPORTED_LINK_RATES,
+				intel_dp->supported_rates,
+				sizeof(intel_dp->supported_rates));
+	}
 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 	      DP_DWN_STRM_PORT_PRESENT))
 		return true; /* native DP sink */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1fb1529..1f41a83 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -626,6 +626,7 @@  struct intel_dp {
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+	__le16 supported_rates[DP_MAX_SUPPORTED_RATES];
 	struct drm_dp_aux aux;
 	uint8_t train_set[4];
 	int panel_power_up_delay;