| Message ID | 1425302250-13446-3-git-send-email-b.michalska@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 02/03/15 14:17, Beata Michalska wrote: > Use assigned-clocks/assigned-clock-parents properties for > CMU clock controller DT node to secure proper clock setup: > switching the two muxes to root oscillator clock is not only > required for proper powering down the ISP power domain, > but it also reduces the risk of accessing the ISP CMU > registers while the ISP power domain remains turned off > (i.e. through the common clock framework by clk_summary) > > Signed-off-by: Beata Michalska <b.michalska@samsung.com> > Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Kukjin, please merge this patch for v4.1. I merged the exynos3250 CMU ISP driver patch and we will have regression if $subject patch is not applied, i.e. reading /sys/kernel/debug/clk/clk_summary would cause system hang on exynos3250. > --- > arch/arm/boot/dts/exynos3250.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi > index 277b48b..6d6118e 100644 > --- a/arch/arm/boot/dts/exynos3250.dtsi > +++ b/arch/arm/boot/dts/exynos3250.dtsi > @@ -172,6 +172,10 @@ > compatible = "samsung,exynos3250-cmu"; > reg = <0x10030000 0x20000>; > #clock-cells = <1>; > + assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, > + <&cmu CLK_MOUT_ACLK_266_SUB>; > + assigned-clock-parents = <&cmu CLK_FIN_PLL>, > + <&cmu CLK_FIN_PLL>; > }; > > cmu_dmc: clock-controller@105C0000 { > Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 03/17/15 19:53, Sylwester Nawrocki wrote: > On 02/03/15 14:17, Beata Michalska wrote: >> Use assigned-clocks/assigned-clock-parents properties for >> CMU clock controller DT node to secure proper clock setup: >> switching the two muxes to root oscillator clock is not only >> required for proper powering down the ISP power domain, >> but it also reduces the risk of accessing the ISP CMU >> registers while the ISP power domain remains turned off >> (i.e. through the common clock framework by clk_summary) >> >> Signed-off-by: Beata Michalska <b.michalska@samsung.com> >> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> > > Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > > Kukjin, please merge this patch for v4.1. I merged the exynos3250 > CMU ISP driver patch and we will have regression if $subject patch > is not applied, i.e. reading /sys/kernel/debug/clk/clk_summary > would cause system hang on exynos3250. > OK, applied. Thanks, Kukjin >> --- >> arch/arm/boot/dts/exynos3250.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi >> index 277b48b..6d6118e 100644 >> --- a/arch/arm/boot/dts/exynos3250.dtsi >> +++ b/arch/arm/boot/dts/exynos3250.dtsi >> @@ -172,6 +172,10 @@ >> compatible = "samsung,exynos3250-cmu"; >> reg = <0x10030000 0x20000>; >> #clock-cells = <1>; >> + assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, >> + <&cmu CLK_MOUT_ACLK_266_SUB>; >> + assigned-clock-parents = <&cmu CLK_FIN_PLL>, >> + <&cmu CLK_FIN_PLL>; >> }; >> >> cmu_dmc: clock-controller@105C0000 { >> > > Thanks, > Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 277b48b..6d6118e 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -172,6 +172,10 @@ compatible = "samsung,exynos3250-cmu"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, + <&cmu CLK_MOUT_ACLK_266_SUB>; + assigned-clock-parents = <&cmu CLK_FIN_PLL>, + <&cmu CLK_FIN_PLL>; }; cmu_dmc: clock-controller@105C0000 {