| Message ID | 1427412625-12377-1-git-send-email-jwerner@chromium.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 754ec43c0184aae48f5a8c917d8282449ab564a9 |
| Headers | show |
Julius, On Thu, Mar 26, 2015 at 4:30 PM, Julius Werner <jwerner@chromium.org> wrote: > The Rockchip SPI driver currently calculates its clock rate divisor by > integer dividing the parent rate by the target rate, and then rounding > the result up to the next even number (since the divisor must be > even). > > Clock rate divisors should always be rounded up, so that the resulting > frequency is lower or equal to the target. This is correctly done in the > second step here but not in the first, so we still have a risk of > exceeding the desired target frequency (e.g. setting spi-max-frequency > to 40000000 with a parent clock of 99000000 could lead to a divisor of > 99000000 / 40000000 == 2 (which is even) that then results in an > effective frequency of 99000000 / 2 == 49500000 (potentially exceeding > the flash chip's specifications). > > This patch changes the division to round up to fix this problem. > > Signed-off-by: Julius Werner <jwerner@chromium.org> > --- > drivers/spi/spi-rockchip.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Doug Anderson <dianders@chromium.org> -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Mar 26, 2015 at 04:30:24PM -0700, Julius Werner wrote: > The Rockchip SPI driver currently calculates its clock rate divisor by > integer dividing the parent rate by the target rate, and then rounding > the result up to the next even number (since the divisor must be > even). Applied both, thanks.
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 1a777dc..5e4e52c 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -519,7 +519,7 @@ static void rockchip_spi_config(struct rockchip_spi *rs) } /* div doesn't support odd number */ - div = max_t(u32, rs->max_freq / rs->speed, 1); + div = DIV_ROUND_UP(rs->max_freq, rs->speed); div = (div + 1) & 0xfffe; writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
The Rockchip SPI driver currently calculates its clock rate divisor by integer dividing the parent rate by the target rate, and then rounding the result up to the next even number (since the divisor must be even). Clock rate divisors should always be rounded up, so that the resulting frequency is lower or equal to the target. This is correctly done in the second step here but not in the first, so we still have a risk of exceeding the desired target frequency (e.g. setting spi-max-frequency to 40000000 with a parent clock of 99000000 could lead to a divisor of 99000000 / 40000000 == 2 (which is even) that then results in an effective frequency of 99000000 / 2 == 49500000 (potentially exceeding the flash chip's specifications). This patch changes the division to round up to fix this problem. Signed-off-by: Julius Werner <jwerner@chromium.org> --- drivers/spi/spi-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)