| Message ID | 1429707494-2732-3-git-send-email-jszhang@marvell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
Hi Jisheng, On 04/22/2015 02:58 PM, Jisheng Zhang wrote: > Most transactions' type are cfg0 and MEM, so the Current iATU usage is not > balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors > the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation > ideas comes from Minghuan Lian<Minghuan.Lian@freescale.com>: > > http://www.spinics.net/lists/linux-pci/msg40440.html > > Signed-off-by: Jisheng Zhang<jszhang@marvell.com> > --- > drivers/pci/host/pcie-designware.c | 83 +++++++++++++++++++++----------------- > 1 file changed, 47 insertions(+), 36 deletions(-) > > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index 1da1446..bb81c8ad 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c > @@ -508,6 +508,13 @@ int dw_pcie_host_init(struct pcie_port *pp) > if (pp->ops->host_init) > pp->ops->host_init(pp); > > + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, > + PCIE_ATU_TYPE_IO, pp->io_mod_base, > + pp->io_bus_addr, pp->io_size); > + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, > + PCIE_ATU_TYPE_MEM, pp->mem_mod_base, > + pp->mem_bus_addr, pp->mem_size); > + Some platforms doesn't have support for ATU. I think this is the reason to have rd_other_conf / wr_other_conf ops in the driver. IMO, this is not suitable to have this in the initialization routine for all platforms. Regards, Fabrice -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Fabrice, On Thu, 23 Apr 2015 00:35:10 -0700 Fabrice Gasnier <fabrice.gasnier@st.com> wrote: > Hi Jisheng, > > On 04/22/2015 02:58 PM, Jisheng Zhang wrote: > > Most transactions' type are cfg0 and MEM, so the Current iATU usage is not > > balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors > > the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation > > ideas comes from Minghuan Lian<Minghuan.Lian@freescale.com>: > > > > http://www.spinics.net/lists/linux-pci/msg40440.html > > > > Signed-off-by: Jisheng Zhang<jszhang@marvell.com> > > --- > > drivers/pci/host/pcie-designware.c | 83 +++++++++++++++++++++----------------- > > 1 file changed, 47 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > > index 1da1446..bb81c8ad 100644 > > --- a/drivers/pci/host/pcie-designware.c > > +++ b/drivers/pci/host/pcie-designware.c > > @@ -508,6 +508,13 @@ int dw_pcie_host_init(struct pcie_port *pp) > > if (pp->ops->host_init) > > pp->ops->host_init(pp); > > > > + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, > > + PCIE_ATU_TYPE_IO, pp->io_mod_base, > > + pp->io_bus_addr, pp->io_size); > > + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, > > + PCIE_ATU_TYPE_MEM, pp->mem_mod_base, > > + pp->mem_bus_addr, pp->mem_size); > > + > Some platforms doesn't have support for ATU. I think this is the reason > to have > rd_other_conf / wr_other_conf ops in the driver. oops. Thanks for the information. So what about something like: if (!pp->ops->rd_other_conf) { dw_pcie_prog_outbound_atu(...); dw_pcie_prog_outbound_atu(...); } Thanks, Jisheng > IMO, this is not suitable to have this in the initialization routine for > all platforms. > > Regards, > Fabrice -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 1da1446..bb81c8ad 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -508,6 +508,13 @@ int dw_pcie_host_init(struct pcie_port *pp) if (pp->ops->host_init) pp->ops->host_init(pp); + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_IO, pp->io_mod_base, + pp->io_bus_addr, pp->io_size); + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_MEM, pp->mem_mod_base, + pp->mem_bus_addr, pp->mem_size); + dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); /* program correct class for RC */ @@ -533,66 +540,70 @@ int dw_pcie_host_init(struct pcie_port *pp) static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - int ret = PCIBIOS_SUCCESSFUL; - u32 address, busdev; + int ret, type; + u32 address, busdev, cfg_size; + u64 cpu_addr; + void __iomem *va_cfg_base; busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | PCIE_ATU_FUNC(PCI_FUNC(devfn)); address = where & ~0x3; if (bus->parent->number == pp->root_bus_nr) { - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base, - busdev, pp->cfg0_size); - ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, - val); - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_MEM, pp->mem_mod_base, - pp->mem_bus_addr, pp->mem_size); + type = PCIE_ATU_TYPE_CFG0; + cpu_addr = pp->cfg0_mod_base; + cfg_size = pp->cfg0_size; + va_cfg_base = pp->va_cfg0_base; } else { - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base, - busdev, pp->cfg1_size); - ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, - val); - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_IO, pp->io_mod_base, - pp->io_bus_addr, pp->io_size); + type = PCIE_ATU_TYPE_CFG1; + cpu_addr = pp->cfg1_mod_base; + cfg_size = pp->cfg1_size; + va_cfg_base = pp->va_cfg1_base; } + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, + type, cpu_addr, + busdev, cfg_size); + ret = dw_pcie_cfg_read(va_cfg_base + address, where, size, val); + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_IO, pp->io_mod_base, + pp->io_bus_addr, pp->io_size); + return ret; } static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - int ret = PCIBIOS_SUCCESSFUL; - u32 address, busdev; + int ret, type; + u32 address, busdev, cfg_size; + u64 cpu_addr; + void __iomem *va_cfg_base; busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | PCIE_ATU_FUNC(PCI_FUNC(devfn)); address = where & ~0x3; if (bus->parent->number == pp->root_bus_nr) { - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base, - busdev, pp->cfg0_size); - ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, - val); - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_MEM, pp->mem_mod_base, - pp->mem_bus_addr, pp->mem_size); + type = PCIE_ATU_TYPE_CFG0; + cpu_addr = pp->cfg0_mod_base; + cfg_size = pp->cfg0_size; + va_cfg_base = pp->va_cfg0_base; } else { - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base, - busdev, pp->cfg1_size); - ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, - val); - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_IO, pp->io_mod_base, - pp->io_bus_addr, pp->io_size); + type = PCIE_ATU_TYPE_CFG1; + cpu_addr = pp->cfg1_mod_base; + cfg_size = pp->cfg1_size; + va_cfg_base = pp->va_cfg1_base; } + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, + type, cpu_addr, + busdev, cfg_size); + ret = dw_pcie_cfg_write(va_cfg_base + address, where, size, val); + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_IO, pp->io_mod_base, + pp->io_bus_addr, pp->io_size); + return ret; }
Most transactions' type are cfg0 and MEM, so the Current iATU usage is not balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation ideas comes from Minghuan Lian <Minghuan.Lian@freescale.com>: http://www.spinics.net/lists/linux-pci/msg40440.html Signed-off-by: Jisheng Zhang <jszhang@marvell.com> --- drivers/pci/host/pcie-designware.c | 83 +++++++++++++++++++++----------------- 1 file changed, 47 insertions(+), 36 deletions(-)