| Message ID | 1430408363-20905-5-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Apr 30, 2015 at 04:39:19PM +0100, Damien Lespiau wrote: > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Patches 2,3,4 satisfy my brain's visual pattern matcher. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 880290d..6d428a5 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6642,6 +6642,11 @@ enum skl_disp_power_wells { > #define GEN6_PCODE_READ_RC6VIDS 0x5 > #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) > #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) > +#define GEN9_PCODE_READ_MEM_LATENCY 0x6 > +#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF > +#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 > +#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 > +#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 > #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 > #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 > #define GEN6_READ_OC_PARAMS 0xc > @@ -6655,12 +6660,6 @@ enum skl_disp_power_wells { > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 > #define GEN6_PCODE_DATA1 0x13812C > > -#define GEN9_PCODE_READ_MEM_LATENCY 0x6 > -#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF > -#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 > -#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 > -#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 > - > #define GEN6_GT_CORE_STATUS 0x138060 > #define GEN6_CORE_CPD_STATE_MASK (7<<4) > #define GEN6_RCn_MASK 7 > -- > 2.1.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 880290d..6d428a5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6642,6 +6642,11 @@ enum skl_disp_power_wells { #define GEN6_PCODE_READ_RC6VIDS 0x5 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) +#define GEN9_PCODE_READ_MEM_LATENCY 0x6 +#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF +#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 +#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 +#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_READ_OC_PARAMS 0xc @@ -6655,12 +6660,6 @@ enum skl_disp_power_wells { #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 #define GEN6_PCODE_DATA1 0x13812C -#define GEN9_PCODE_READ_MEM_LATENCY 0x6 -#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF -#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 -#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 -#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 - #define GEN6_GT_CORE_STATUS 0x138060 #define GEN6_CORE_CPD_STATE_MASK (7<<4) #define GEN6_RCn_MASK 7
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)