| Message ID | 1432739754-19511-1-git-send-email-chanho61.park@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Chanho, On 05/28/2015 12:15 AM, Chanho Park wrote: > The odroid-xu3 board which is based on exynos5422 not exynos5800 is > booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order > is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are > cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi > and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and > cpu4-7 are cortex-a15. The exynos5422 SoC can boot using cortex-a15 cpu depending on gpio GPG2CON[1], i think this is just Odroid-XU3 board problem. Is it possible to overwrite cpus information directly from exynos5422-odroidxu3.dts? -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, > -----Original Message----- > From: Joonyoung Shim [mailto:jy0922.shim@samsung.com] > Sent: Thursday, May 28, 2015 10:59 AM > To: Chanho Park; kgene@kernel.org; k.kozlowski@samsung.com > Cc: cw00.choi@samsung.com; linux-samsung-soc@vger.kernel.org; > javier.martinez@collabora.co.uk; khilman@linaro.org; > sjoerd.simons@collabora.co.uk; heesub.shin@samsung.com > Subject: Re: [PATCH] ARM: dts: add exynos5422.dtsi to correct cpu order > > Hi Chanho, > > On 05/28/2015 12:15 AM, Chanho Park wrote: > > The odroid-xu3 board which is based on exynos5422 not exynos5800 is > > booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu > order > > is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are > > cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi > > and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 > and > > cpu4-7 are cortex-a15. > > The exynos5422 SoC can boot using cortex-a15 cpu depending on gpio > GPG2CON[1], Yes, But, the pin is not controllable because it's checked in the iROM area. > i think this is just Odroid-XU3 board problem. Is it > possible to overwrite cpus information directly from > exynos5422-odroidxu3.dts? It's possible to override the info in the odroidxu3.dts. As you know, however, a new exynos5422 board will be added soon. The board also has same configuration of the gpio pin and booted cpu0 from a cortex-a7 core. BTW, booting of secondary cpus are still broken. Is there any progress of the patch[1]? This patch is also generated top of the patch with some fixes. [1]. http://www.spinics.net/lists/linux-samsung-soc/msg39523.html Best Regards, Chanho Park -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
+Cc Bartlomiej On 28.05.2015 13:00, Chanho Park wrote: > Hi, > >> -----Original Message----- >> From: Joonyoung Shim [mailto:jy0922.shim@samsung.com] >> Sent: Thursday, May 28, 2015 10:59 AM >> To: Chanho Park; kgene@kernel.org; k.kozlowski@samsung.com >> Cc: cw00.choi@samsung.com; linux-samsung-soc@vger.kernel.org; >> javier.martinez@collabora.co.uk; khilman@linaro.org; >> sjoerd.simons@collabora.co.uk; heesub.shin@samsung.com >> Subject: Re: [PATCH] ARM: dts: add exynos5422.dtsi to correct cpu order >> >> Hi Chanho, >> >> On 05/28/2015 12:15 AM, Chanho Park wrote: >>> The odroid-xu3 board which is based on exynos5422 not exynos5800 is >>> booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu >> order >>> is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are >>> cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi >>> and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 >> and >>> cpu4-7 are cortex-a15. >> >> The exynos5422 SoC can boot using cortex-a15 cpu depending on gpio >> GPG2CON[1], > > Yes, But, the pin is not controllable because it's checked in the iROM > area. After looking at schematics I think the pin on Odroid XU3 seems to be hard-wired to VDDQ_JTAG so this means that board will always boot to A7. However this is a board-specific property. > >> i think this is just Odroid-XU3 board problem. Is it >> possible to overwrite cpus information directly from >> exynos5422-odroidxu3.dts? > > It's possible to override the info in the odroidxu3.dts. As you know, > however, a new exynos5422 board will be added soon. The board also has same > configuration of the gpio pin and booted cpu0 from a cortex-a7 core. When adding new 5422 board we can split out CPU configuration to separate DTSI file. I already posted patches for Odroid XU3-family common DTSI file for XU3 Lite board: http://www.spinics.net/lists/linux-samsung-soc/msg44868.html > BTW, booting of secondary cpus are still broken. Is there any progress of > the patch[1]? > This patch is also generated top of the patch with some fixes. > > [1]. http://www.spinics.net/lists/linux-samsung-soc/msg39523.html No progress so far. Apparently nobody knows why this works and what to do with it. I would suspect booted CPUs stuck somewhere in BL1 or BL2 and writing to PMU_SPARE2 kicks them. However this is just a guess. Kukjin which could be the closest person to the real knowledge (LSI) did not gave his feedback. We have a lot of such hacks and undocumented interfaces between kernel and bootloaders. IMHO it would be good to start documenting them. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, > When adding new 5422 board we can split out CPU configuration to > separate DTSI file. I already posted patches for Odroid XU3-family > common DTSI file for XU3 Lite board: > http://www.spinics.net/lists/linux-samsung-soc/msg44868.html IMHO, all of the exynos5422 boards will be same cpu configurations. That's why I added new exynos5422.dtsi. > > > BTW, booting of secondary cpus are still broken. Is there any progress > of > > the patch[1]? > > This patch is also generated top of the patch with some fixes. > > > > [1]. http://www.spinics.net/lists/linux-samsung-soc/msg39523.html > > No progress so far. Apparently nobody knows why this works and what to > do with it. I would suspect booted CPUs stuck somewhere in BL1 or BL2 > and writing to PMU_SPARE2 kicks them. However this is just a guess. > > Kukjin which could be the closest person to the real knowledge (LSI) did > not gave his feedback. > > We have a lot of such hacks and undocumented interfaces between kernel > and bootloaders. IMHO it would be good to start documenting them. Good. But, who can do it? Best Regards, Chanho Park -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello, On 2015-05-28 06:00, Chanho Park wrote: >> -----Original Message----- >> From: Joonyoung Shim [mailto:jy0922.shim@samsung.com] >> Sent: Thursday, May 28, 2015 10:59 AM >> To: Chanho Park; kgene@kernel.org; k.kozlowski@samsung.com >> Cc: cw00.choi@samsung.com; linux-samsung-soc@vger.kernel.org; >> javier.martinez@collabora.co.uk; khilman@linaro.org; >> sjoerd.simons@collabora.co.uk; heesub.shin@samsung.com >> Subject: Re: [PATCH] ARM: dts: add exynos5422.dtsi to correct cpu order >> >> Hi Chanho, >> >> On 05/28/2015 12:15 AM, Chanho Park wrote: >>> The odroid-xu3 board which is based on exynos5422 not exynos5800 is >>> booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu >> order >>> is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are >>> cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi >>> and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 >> and >>> cpu4-7 are cortex-a15. >> The exynos5422 SoC can boot using cortex-a15 cpu depending on gpio >> GPG2CON[1], > Yes, But, the pin is not controllable because it's checked in the iROM > area. > >> i think this is just Odroid-XU3 board problem. Is it >> possible to overwrite cpus information directly from >> exynos5422-odroidxu3.dts? > It's possible to override the info in the odroidxu3.dts. As you know, > however, a new exynos5422 board will be added soon. The board also has same > configuration of the gpio pin and booted cpu0 from a cortex-a7 core. > > BTW, booting of secondary cpus are still broken. Is there any progress of > the patch[1]? > This patch is also generated top of the patch with some fixes. Przemyslaw is checking how to solve this issue in the bootloader like it has been solved for Exynos 5800 based Chromebooks. The plan is to use the same SPL code as mentioned here: https://www.mail-archive.com/u-boot@lists.denx.de/msg159960.html Best regards
Marek Szyprowski <m.szyprowski@samsung.com> writes: > Hello, > > On 2015-05-28 06:00, Chanho Park wrote: >>> -----Original Message----- >>> From: Joonyoung Shim [mailto:jy0922.shim@samsung.com] >>> Sent: Thursday, May 28, 2015 10:59 AM >>> To: Chanho Park; kgene@kernel.org; k.kozlowski@samsung.com >>> Cc: cw00.choi@samsung.com; linux-samsung-soc@vger.kernel.org; >>> javier.martinez@collabora.co.uk; khilman@linaro.org; >>> sjoerd.simons@collabora.co.uk; heesub.shin@samsung.com >>> Subject: Re: [PATCH] ARM: dts: add exynos5422.dtsi to correct cpu order >>> >>> Hi Chanho, >>> >>> On 05/28/2015 12:15 AM, Chanho Park wrote: >>>> The odroid-xu3 board which is based on exynos5422 not exynos5800 is >>>> booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu >>> order >>>> is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are >>>> cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi >>>> and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 >>> and >>>> cpu4-7 are cortex-a15. >>> The exynos5422 SoC can boot using cortex-a15 cpu depending on gpio >>> GPG2CON[1], >> Yes, But, the pin is not controllable because it's checked in the iROM >> area. >> >>> i think this is just Odroid-XU3 board problem. Is it >>> possible to overwrite cpus information directly from >>> exynos5422-odroidxu3.dts? >> It's possible to override the info in the odroidxu3.dts. As you know, >> however, a new exynos5422 board will be added soon. The board also has same >> configuration of the gpio pin and booted cpu0 from a cortex-a7 core. >> >> BTW, booting of secondary cpus are still broken. Is there any progress of >> the patch[1]? >> This patch is also generated top of the patch with some fixes. Note that even with that hack/patch from me, all cores may boot, but you cannot let them hit deeper idle states with CPUidle. This is because the firmware appears to have configured CCI in secure mode, which mean that the kernel cannot control CCI, which essentially breaks MCPM and everthing built on it (idle, suspend, etc.) > Przemyslaw is checking how to solve this issue in the bootloader like it has > been solved for Exynos 5800 based Chromebooks. The plan is to use the same > SPL code as mentioned here: > https://www.mail-archive.com/u-boot@lists.denx.de/msg159960.html This is good news! I'd be happy to test any work in progress on this. We really need the other exynos platforms to follow the bootloader of the chromebooks which includes a working CCI and thus kernel MCPM functionality. Kevin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
2015-05-28 17:43 GMT+09:00 Chanho Park <chanho61.park@samsung.com>: > Hi, > >> When adding new 5422 board we can split out CPU configuration to >> separate DTSI file. I already posted patches for Odroid XU3-family >> common DTSI file for XU3 Lite board: >> http://www.spinics.net/lists/linux-samsung-soc/msg44868.html > > IMHO, all of the exynos5422 boards will be same cpu configurations. That's > why I added new exynos5422.dtsi. Maybe all of boards will have same configuration... maybe not. You cannot predict the future, right? It is however strictly related to the board configuration. The SoC supports both boot modes depending on the GPIO pin. I do not oppose against the idea of correcting order of CPUs. It is nice to have them ordered in a more natural way. However I think this should be a DTSI related to the CPU-nodes, not a DTSI for SoC. Especially that inclusion order gets quite complicated: 1. Odroid includes 5422.dtsi. 2. 5422 includes 5800. 3. 5800 includes 5420. Can you make it as a DTSI specific for CPU nodes configuration and then include it only in boards DTS? > >> >> > BTW, booting of secondary cpus are still broken. Is there any progress >> of >> > the patch[1]? >> > This patch is also generated top of the patch with some fixes. >> > >> > [1]. http://www.spinics.net/lists/linux-samsung-soc/msg39523.html >> >> No progress so far. Apparently nobody knows why this works and what to >> do with it. I would suspect booted CPUs stuck somewhere in BL1 or BL2 >> and writing to PMU_SPARE2 kicks them. However this is just a guess. >> >> Kukjin which could be the closest person to the real knowledge (LSI) did >> not gave his feedback. >> >> We have a lot of such hacks and undocumented interfaces between kernel >> and bootloaders. IMHO it would be good to start documenting them. > > Good. But, who can do it? Anyone can do it! The information is there (spread in arch/arm/mach-exynos and in u-boot code) so we just need a volunteer! :) BR, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index edc25cf..0f0784b 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -11,11 +11,12 @@ */ /dts-v1/; -#include "exynos5800.dtsi" +#include "exynos5422.dtsi" / { model = "Hardkernel Odroid XU3"; - compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; + compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", + "samsung,exynos5422", "samsung,exynos5"; memory { reg = <0x40000000 0x7EA00000>; diff --git a/arch/arm/boot/dts/exynos5422.dtsi b/arch/arm/boot/dts/exynos5422.dtsi new file mode 100644 index 0000000..3ac12bc --- /dev/null +++ b/arch/arm/boot/dts/exynos5422.dtsi @@ -0,0 +1,88 @@ +/* + * SAMSUNG EXYNOS5422 SoC device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The + * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting + * from Cortex-A15 core. + * + * EXYNOS5422 based board files can include this file and provide + * values for board specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "exynos5800.dtsi" + +/ { + compatible = "samsung,exynos5800", "samsung,exynos5422", + "samsung,exynos5"; +}; + +&cpu0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu4 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu5 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu6 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu7 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +};
The odroid-xu3 board which is based on exynos5422 not exynos5800 is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15. Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 5 +- arch/arm/boot/dts/exynos5422.dtsi | 88 ++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/exynos5422.dtsi