diff mbox

[PATCHv3] ARM: dts: add exynos5422-cpus.dtsi to correct cpu order

Message ID 1433161459-10901-1-git-send-email-chanho61.park@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chanho Park June 1, 2015, 12:24 p.m. UTC
The odroid-xu3 board which is based on exynos5422 not exynos5800 is
booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order
is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are
cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi
and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and
cpu4-7 are cortex-a15.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
Change from v2:
 - drop inclusion of exynos5420.dtsi from exynos5422-cpus.dtsi
 - drop compatibles from exynos5422-cpus.dtsi

Changes from v1:
 - rename exynos5422.dtsi to exynos5422-cpus.dtsi
 - include the dtsi file top of the exynos5422-odroidxu3.dts

 arch/arm/boot/dts/exynos5422-cpus.dtsi     | 81 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos5422-odroidxu3.dts |  4 +-
 2 files changed, 84 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi

Comments

Krzysztof Kozlowski June 1, 2015, 11:55 p.m. UTC | #1
On 01.06.2015 21:24, Chanho Park wrote:
> The odroid-xu3 board which is based on exynos5422 not exynos5800 is
> booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order
> is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are
> cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi
> and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and
> cpu4-7 are cortex-a15.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> Change from v2:
>  - drop inclusion of exynos5420.dtsi from exynos5422-cpus.dtsi
>  - drop compatibles from exynos5422-cpus.dtsi
> 
> Changes from v1:
>  - rename exynos5422.dtsi to exynos5422-cpus.dtsi
>  - include the dtsi file top of the exynos5422-odroidxu3.dts
> 
>  arch/arm/boot/dts/exynos5422-cpus.dtsi     | 81 ++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3.dts |  4 +-
>  2 files changed, 84 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi


Looks good,
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

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Peter Chubb June 2, 2015, 3:29 a.m. UTC | #2
>>>>> "Chanho" == Chanho Park <parkch98@gmail.com> writes:

Chanho> The odroid-xu3 board which is based on exynos5422 not
Chanho> exynos5800 is booted from cortex-a7 core unlike
Chanho> exynos5800. The odroid-xu3's cpu order is quite strange. cpu0
Chanho> and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15
Chanho> cores. To correct this mis-odering, I added exynos5422.dtsi
Chanho> and reversing cpu orders from exynos5420. Now, cpu0-3 are
Chanho> cortex-a7 and cpu4-7 are cortex-a15.

Does this patch make any difference?  CPUs are numbered in the kernel
in the order they're enumerated; with this patch or using the old dts
I see the CPUs numbered the same after boot.  And only 5 of the 8 come
up: processor 0 is an A7; processors 1 through 4 are A15.

Peter C
Krzysztof Kozlowski June 2, 2015, 12:02 p.m. UTC | #3
W dniu 02.06.2015 o 12:29, Peter Chubb pisze:
>>>>>> "Chanho" == Chanho Park <parkch98@gmail.com> writes:
> 
> Chanho> The odroid-xu3 board which is based on exynos5422 not
> Chanho> exynos5800 is booted from cortex-a7 core unlike
> Chanho> exynos5800. The odroid-xu3's cpu order is quite strange. cpu0
> Chanho> and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15
> Chanho> cores. To correct this mis-odering, I added exynos5422.dtsi
> Chanho> and reversing cpu orders from exynos5420. Now, cpu0-3 are
> Chanho> cortex-a7 and cpu4-7 are cortex-a15.
> 
> Does this patch make any difference?  CPUs are numbered in the kernel
> in the order they're enumerated; with this patch or using the old dts
> I see the CPUs numbered the same after boot.  And only 5 of the 8 come
> up: processor 0 is an A7; processors 1 through 4 are A15.

In my case (Odroid XU3 Lite, next-20150529) the patch makes difference.
The A7 is 0-3 and A15 is 4-7 so the patch changes the order.

Best regards,
Krzysztof
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Chanho Park June 2, 2015, 12:49 p.m. UTC | #4
Hi Peter,

On Tue, Jun 2, 2015 at 12:29 PM, Peter Chubb <peter.chubb@nicta.com.au> wrote:
>>>>>> "Chanho" == Chanho Park <parkch98@gmail.com> writes:
>
> Chanho> The odroid-xu3 board which is based on exynos5422 not
> Chanho> exynos5800 is booted from cortex-a7 core unlike
> Chanho> exynos5800. The odroid-xu3's cpu order is quite strange. cpu0
> Chanho> and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15
> Chanho> cores. To correct this mis-odering, I added exynos5422.dtsi
> Chanho> and reversing cpu orders from exynos5420. Now, cpu0-3 are
> Chanho> cortex-a7 and cpu4-7 are cortex-a15.
>
> Does this patch make any difference?  CPUs are numbered in the kernel
> in the order they're enumerated; with this patch or using the old dts
> I see the CPUs numbered the same after boot.  And only 5 of the 8 come
> up: processor 0 is an A7; processors 1 through 4 are A15.

My patch is just reordering cpu order not fix previous Little core problem.
You'll need below patch from previous mail thread[1].

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c

index a825bca..e803ec5 100644

--- a/arch/arm/mach-exynos/platsmp.c

+++ b/arch/arm/mach-exynos/platsmp.c

@@ -124,6 +124,7 @@ void exynos_cpu_power_up(int cpu)

        if (soc_is_exynos3250())

                core_conf |= S5P_CORE_AUTOWAKEUP_EN;



+       pmu_raw_writel(1, S5P_PMU_SPARE2);

        pmu_raw_writel(core_conf,

                        EXYNOS_ARM_CORE_CONFIGURATION(cpu));

 }

[1]: https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg44023.html
Chanho Park July 1, 2015, 1:35 p.m. UTC | #5
Hi,

On Tue, Jun 2, 2015 at 8:55 AM, Krzysztof Kozlowski
<k.kozlowski@samsung.com> wrote:
> On 01.06.2015 21:24, Chanho Park wrote:
>> The odroid-xu3 board which is based on exynos5422 not exynos5800 is
>> booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order
>> is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are
>> cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi
>> and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and
>> cpu4-7 are cortex-a15.
>>
>> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>> ---
>> Change from v2:
>>  - drop inclusion of exynos5420.dtsi from exynos5422-cpus.dtsi
>>  - drop compatibles from exynos5422-cpus.dtsi
>>
>> Changes from v1:
>>  - rename exynos5422.dtsi to exynos5422-cpus.dtsi
>>  - include the dtsi file top of the exynos5422-odroidxu3.dts
>>
>>  arch/arm/boot/dts/exynos5422-cpus.dtsi     | 81 ++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/exynos5422-odroidxu3.dts |  4 +-
>>  2 files changed, 84 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi
>
>
> Looks good,
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> Best regards,
> Krzysztof
>

Could you pick up this patch or should I request it to Kukjin?
Krzysztof Kozlowski July 1, 2015, 11:50 p.m. UTC | #6
On 01.07.2015 22:35, Chanho Park wrote:
> Hi,
> 
> On Tue, Jun 2, 2015 at 8:55 AM, Krzysztof Kozlowski
> <k.kozlowski@samsung.com> wrote:
>> On 01.06.2015 21:24, Chanho Park wrote:
>>> The odroid-xu3 board which is based on exynos5422 not exynos5800 is
>>> booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order
>>> is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are
>>> cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi
>>> and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and
>>> cpu4-7 are cortex-a15.
>>>
>>> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>>> ---
>>> Change from v2:
>>>  - drop inclusion of exynos5420.dtsi from exynos5422-cpus.dtsi
>>>  - drop compatibles from exynos5422-cpus.dtsi
>>>
>>> Changes from v1:
>>>  - rename exynos5422.dtsi to exynos5422-cpus.dtsi
>>>  - include the dtsi file top of the exynos5422-odroidxu3.dts
>>>
>>>  arch/arm/boot/dts/exynos5422-cpus.dtsi     | 81 ++++++++++++++++++++++++++++++
>>>  arch/arm/boot/dts/exynos5422-odroidxu3.dts |  4 +-
>>>  2 files changed, 84 insertions(+), 1 deletion(-)
>>>  create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi
>>
>>
>> Looks good,
>> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>
>> Best regards,
>> Krzysztof
>>
> 
> Could you pick up this patch or should I request it to Kukjin?

I reviewed it already so Kukjin should pick it up with my tag.

Anyway it does not apply, probably because of changes in Odroid XU3 DTS
(a common DTSI was added).

Best regards,
Krzysztof


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diff mbox

Patch

diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
new file mode 100644
index 0000000..b7f60c8
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -0,0 +1,81 @@ 
+/*
+ * SAMSUNG EXYNOS5422 SoC cpu device tree source
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The
+ * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting
+ * from Cortex-A15 core.
+ *
+ * EXYNOS5422 based board files can include this file to provide cpu ordering
+ * which could boot a cortex-a7 from cpu0.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&cpu0 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a7";
+	reg = <0x100>;
+	clock-frequency = <1000000000>;
+	cci-control-port = <&cci_control0>;
+};
+
+&cpu1 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a7";
+	reg = <0x101>;
+	clock-frequency = <1000000000>;
+	cci-control-port = <&cci_control0>;
+};
+
+&cpu2 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a7";
+	reg = <0x102>;
+	clock-frequency = <1000000000>;
+	cci-control-port = <&cci_control0>;
+};
+
+&cpu3 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a7";
+	reg = <0x103>;
+	clock-frequency = <1000000000>;
+	cci-control-port = <&cci_control0>;
+};
+
+&cpu4 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a15";
+	reg = <0x0>;
+	clock-frequency = <1800000000>;
+	cci-control-port = <&cci_control1>;
+};
+
+&cpu5 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a15";
+	reg = <0x1>;
+	clock-frequency = <1800000000>;
+	cci-control-port = <&cci_control1>;
+};
+
+&cpu6 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a15";
+	reg = <0x2>;
+	clock-frequency = <1800000000>;
+	cci-control-port = <&cci_control1>;
+};
+
+&cpu7 {
+	device_type = "cpu";
+	compatible = "arm,cortex-a15";
+	reg = <0x3>;
+	clock-frequency = <1800000000>;
+	cci-control-port = <&cci_control1>;
+};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index edc25cf..00f45c9 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -12,10 +12,12 @@ 
 
 /dts-v1/;
 #include "exynos5800.dtsi"
+#include "exynos5422-cpus.dtsi"
 
 / {
 	model = "Hardkernel Odroid XU3";
-	compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
+	compatible = "hardkernel,odroid-xu3", "samsung,exynos5800",
+		     "samsung,exynos5422", "samsung,exynos5";
 
 	memory {
 		reg = <0x40000000 0x7EA00000>;