| Message ID | 1436533300-6364-1-git-send-email-praveen.paneri@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6773
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 303/303 303/303
SNB +3 309/316 312/316
IVB 343/343 343/343
BYT 285/285 285/285
HSW +13 367/381 380/381
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*SNB igt@kms_mmio_vs_cs_flip@setcrtc_vs_cs_flip DMESG_WARN(1) PASS(1)
*SNB igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(1) PASS(1)
*SNB igt@pm_rpm@cursor DMESG_WARN(1) PASS(1)
*SNB igt@pm_rpm@cursor-dpms DMESG_FAIL(1) FAIL(1)
*HSW igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(1) PASS(1)
*HSW igt@pm_lpsp@non-edp DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@debugfs-read DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@gem-idle DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@gem-mmap-gtt DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@gem-pread DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@i2c DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@modeset-non-lpsp DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@modeset-non-lpsp-stress-no-wait DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@pci-d3-state DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@reg-read-ioctl DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@rte DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@sysfs-read DMESG_WARN(1) PASS(1)
Note: You need to pay more attention to line start with '*'
On Fri, Jul 10, 2015 at 06:31:40PM +0530, Praveen Paneri wrote: > From: Deepak S <deepak.s@intel.com> > > Currently we update the freq before masking the interrupts, which can > allow new interrupts to occur before the frequency has changed. These > extra interrupts might waste some cpu cycles. This patch corrects > this by masking interrupts prior to updating the frequency. Well it won't waste CPU cycles as the interrupt is also masked by the threshold limits, but there should be no harm at all in reordering the patch so, and it does make a certain amount of sense. > Signed-off-by: Deepak S <deepak.s@intel.com> > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com> Quibbling over the language in the changelog aside, Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
On Sat, Jul 11, 2015 at 05:46:37PM +0100, Chris Wilson wrote: > On Fri, Jul 10, 2015 at 06:31:40PM +0530, Praveen Paneri wrote: > > From: Deepak S <deepak.s@intel.com> > > > > Currently we update the freq before masking the interrupts, which can > > allow new interrupts to occur before the frequency has changed. These > > extra interrupts might waste some cpu cycles. This patch corrects > > this by masking interrupts prior to updating the frequency. > > Well it won't waste CPU cycles as the interrupt is also masked by the > threshold limits, but there should be no harm at all in reordering the > patch so, and it does make a certain amount of sense. Added and ... > > > Signed-off-by: Deepak S <deepak.s@intel.com> > > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com> > > Quibbling over the language in the changelog aside, > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4e24d2b..1082123 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4482,14 +4482,14 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) "Odd GPU freq value\n")) val &= ~1; + I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); + if (val != dev_priv->rps.cur_freq) { vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); if (!IS_CHERRYVIEW(dev_priv)) gen6_set_rps_thresholds(dev_priv, val); } - I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); - dev_priv->rps.cur_freq = val; trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); }