| Message ID | 1439456813-4918-1-git-send-email-aballier@gentoo.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
W dniu 13.08.2015 o 18:06, Alexis Ballier pisze: > SPI1 is available on IO Port #2 (as depicted on their website) in > PCB Revision 0.5 of Hardkernel Odroid U3 board. > The shield connects a 256KiB spi-nor flash on that bus. > > Signed-off-by: Alexis Ballier <aballier@gentoo.org> > > --- > > Changes in v2: Use GPIO_ACTIVE_HIGH (Krzysztof Kozlowski) > > arch/arm/boot/dts/exynos4412-odroidu3.dts | 8 ++++++++ > 1 file changed, 8 insertions(+) Thanks for fixing, looks good: Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Krzysztof Kozlowski wrote: > > W dniu 13.08.2015 o 18:06, Alexis Ballier pisze: > > SPI1 is available on IO Port #2 (as depicted on their website) in > > PCB Revision 0.5 of Hardkernel Odroid U3 board. > > The shield connects a 256KiB spi-nor flash on that bus. > > > > Signed-off-by: Alexis Ballier <aballier@gentoo.org> > > > > --- > > > > Changes in v2: Use GPIO_ACTIVE_HIGH (Krzysztof Kozlowski) > > > > arch/arm/boot/dts/exynos4412-odroidu3.dts | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > Thanks for fixing, looks good: > > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Applied, thanks. - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 44684e5..8632f35 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -13,6 +13,7 @@ /dts-v1/; #include "exynos4412-odroid-common.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Hardkernel ODROID-U3 board based on Exynos4412"; @@ -61,3 +62,10 @@ "Speakers", "SPKL", "Speakers", "SPKR"; }; + +&spi_1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +};
SPI1 is available on IO Port #2 (as depicted on their website) in PCB Revision 0.5 of Hardkernel Odroid U3 board. The shield connects a 256KiB spi-nor flash on that bus. Signed-off-by: Alexis Ballier <aballier@gentoo.org> --- Changes in v2: Use GPIO_ACTIVE_HIGH (Krzysztof Kozlowski) arch/arm/boot/dts/exynos4412-odroidu3.dts | 8 ++++++++ 1 file changed, 8 insertions(+)