diff mbox

[11/15] drm/i915: Enable DPIO SUS clock gating on CHV

Message ID 1436388361-11130-12-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä July 8, 2015, 8:45 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has supports some form of automagic clock gating for the
DPIO SUS clock. We can simply enable the magic bits and the
hardware should take care of the rest.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

Comments

deepak.s@linux.intel.com Aug. 19, 2015, 1:09 p.m. UTC | #1 
On 07/09/2015 02:15 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV has supports some form of automagic clock gating for the
> DPIO SUS clock. We can simply enable the magic bits and the
> hardware should take care of the rest.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
>   drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
>   2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcfcbb62..8010200 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1133,6 +1133,10 @@ enum skl_disp_power_wells {
>   #define CHV_CMN_DW28			0x8170
>   #define   DPIO_CL1POWERDOWNEN		(1 << 23)
>   #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
> +#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
> +#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
> +#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
> +#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
>   
>   #define CHV_CMN_DW30			0x8178
>   #define   DPIO_LRC_BYPASS		(1 << 3)
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 551cf08..37e4375 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -972,7 +972,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
>   
>   	/* Enable dynamic power down */
>   	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
> -	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN;
> +	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
> +		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
>   	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
>   
>   	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
Changes looks fine as per Bspec.
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcfcbb62..8010200 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1133,6 +1133,10 @@  enum skl_disp_power_wells {
 #define CHV_CMN_DW28			0x8170
 #define   DPIO_CL1POWERDOWNEN		(1 << 23)
 #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
+#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
+#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
+#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
+#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
 
 #define CHV_CMN_DW30			0x8178
 #define   DPIO_LRC_BYPASS		(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 551cf08..37e4375 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -972,7 +972,8 @@  static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 
 	/* Enable dynamic power down */
 	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
-	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN;
+	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
+		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
 
 	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {