| Message ID | 1440382692-3855-2-git-send-email-yamada.masahiro@socionext.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, 2015-08-24 at 11:18 +0900, Masahiro Yamada wrote: > This commit adds support for UniPhier outer cache controller. > All the UniPhier SoCs are equipped with the L2 cache, while the L3 > cache is currently only integrated on PH1-Pro5 SoC. style trivia: You might add and use #define pr_fmt(fmt) "uniphier: " fmt before any other #include so all of the pr_<level> uses are automatically prefixed. > diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c [] > +static int __init __uniphier_cache_init(void) > +{ [] > + if (uniphier_outer_levels == 0) { > + ret = ret ?: -ENODEV; > + pr_err("uniphier: failed to initialize outer cache\n"); So this becomes: pr_err("failed to initialize outer cache\n"); > +int __init uniphier_cache_init(void) > +{ [] > + pr_info("uniphier: enabled outer cache (%s)\n", > + uniphier_outer_levels >= 2 ? "L2 and L3" : "L2"); pr_info("enabled outer cache (%s)\n", uniphier_outer_levels >= 2 ? "L2 and L3" : "L2"); etc...
Hi Joe, 2015-08-24 11:29 GMT+09:00 Joe Perches <joe@perches.com>: > On Mon, 2015-08-24 at 11:18 +0900, Masahiro Yamada wrote: >> This commit adds support for UniPhier outer cache controller. >> All the UniPhier SoCs are equipped with the L2 cache, while the L3 >> cache is currently only integrated on PH1-Pro5 SoC. > > style trivia: > > You might add and use > #define pr_fmt(fmt) "uniphier: " fmt > before any other #include so all of the pr_<level> > uses are automatically prefixed. I did not know that. Thanks! I will do so for the whole series in v2.
On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote: > diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt > new file mode 100644 > index 0000000..6428289 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt > @@ -0,0 +1,30 @@ > +UniPhier outer cache controller > + > +UniPhier SoCs are integrated with a level 2 cache controller that resides > +outside of the ARM cores, some of them also have a level 3 cache controller. > + > +Required properties: > +- compatible: should be one of the followings: > + "socionext,uniphier-l2-cache" (L2 cache) > + "socionext,uniphier-l3-cache" (L3 cache) > +- reg: offsets and lengths of the register sets for the device. It should > + contain 3 regions: control registers, revision registers, operation > + registers, in this order. > + > +The L2 cache must exist to use the L3 cache; adding only an L3 cache device > +node to the device tree causes the initialization failure of the whole outer > +cache system. > How much does this outer cache have in common with the l2x0/pl310 cache controller model? Would it make sense to at least share the common entry point at l2x0_of_init() so you don't need to call it from the platform file? Arnd
Hi Arnd, 2015-08-25 4:59 GMT+09:00 Arnd Bergmann <arnd@arndb.de>: > On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote: >> diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt >> new file mode 100644 >> index 0000000..6428289 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt >> @@ -0,0 +1,30 @@ >> +UniPhier outer cache controller >> + >> +UniPhier SoCs are integrated with a level 2 cache controller that resides >> +outside of the ARM cores, some of them also have a level 3 cache controller. >> + >> +Required properties: >> +- compatible: should be one of the followings: >> + "socionext,uniphier-l2-cache" (L2 cache) >> + "socionext,uniphier-l3-cache" (L3 cache) >> +- reg: offsets and lengths of the register sets for the device. It should >> + contain 3 regions: control registers, revision registers, operation >> + registers, in this order. >> + >> +The L2 cache must exist to use the L3 cache; adding only an L3 cache device >> +node to the device tree causes the initialization failure of the whole outer >> +cache system. >> > > How much does this outer cache have in common with the l2x0/pl310 cache > controller model? Nothing. This outer cache is not a variant of l2x0/pl310. It was designed only for our SoCs from scratch. > Would it make sense to at least share the > common entry point at l2x0_of_init() so you don't need to call it from > the platform file? I do not think so. l2x0_of_init() checks L2X0_AUX_CTRL register, but the cache-uniphier does not have such register, so the boot code crashes. BTW, what makes l2x0_of_init() so special? Only L2x0/L310 and variants can be initialized directly from init_IRQ(). Moreover, outer-cache init seems to be unrelated to IRQ init.
On Wednesday 26 August 2015 10:38:59 Masahiro Yamada wrote: > > 2015-08-25 4:59 GMT+09:00 Arnd Bergmann <arnd@arndb.de>: > > On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote: > Nothing. > > This outer cache is not a variant of l2x0/pl310. > It was designed only for our SoCs from scratch. Ok, I see. > > Would it make sense to at least share the > > common entry point at l2x0_of_init() so you don't need to call it from > > the platform file? > > I do not think so. > > > l2x0_of_init() checks L2X0_AUX_CTRL register, > but the cache-uniphier does not have such register, > so the boot code crashes. > > > > BTW, what makes l2x0_of_init() so special? > > Only L2x0/L310 and variants can be initialized > directly from init_IRQ(). The only thing that is special about it is that almost everyone uses it because it is often licensed together with the Cortex-A cores from ARM. There are a few variants that are closely related (tauros3 and aurora, both from Marvell. All other outer_cache implementations (feroceon, xscale, tauros2) are for older Marvell (or Intel) cores that have since been replaced with Cortex-A cores in newer products. > Moreover, outer-cache init seems to be unrelated to > IRQ init. Agreed, this is also just a historic artifact, as we don't really have a place to put cache controller initialization, and the irq init callback was already there at the time when people added code to init their outer caches. It often does not matter much where you call it, but doing it early speeds up the boot time. It would be nice to unify the cache initialization a bit further, apparently only a few older platforms still call the l2x0 init manually and we can probably all convert them to the implicit configuration in one way or another. As we now have three kinds of cache controllers (l2x0, tauros2 and uniphier) that we need to support using DT, it would be nice for generalize that init sequence a bit more. A first step would be to add the tauros2 and uniphier outer cache init to the init_IRQ() function, and then have another patch that moves all the outercache initialization into a new place like arch/arm/mm/outercache.c so we don't clutter up irq.c with unrelated stuff. Russell probably also has some ideas on this topic, in doubt just do what he suggests. Arnd
On Mon, Aug 24, 2015 at 4:18 AM, Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > This commit adds support for UniPhier outer cache controller. > All the UniPhier SoCs are equipped with the L2 cache, while the L3 > cache is currently only integrated on PH1-Pro5 SoC. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Wow it is really a custom L2$ controller. Wow. Just wow. That's really brave, given all the problems we've seen in l2x0. > +UniPhier SoCs are integrated with a level 2 cache controller that resides > +outside of the ARM cores, some of them also have a level 3 cache controller. > + > +Required properties: > +- compatible: should be one of the followings: > + "socionext,uniphier-l2-cache" (L2 cache) > + "socionext,uniphier-l3-cache" (L3 cache) Refer to and use the 3.7.3 ePAPR v1.1 specification too: https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf cache-unified and cache-level are *not* optional and should be required. So: > +The L2 cache must exist to use the L3 cache; adding only an L3 cache device > +node to the device tree causes the initialization failure of the whole outer > +cache system. > + > +Example: > + l2-cache@500c0000 { > + compatible = "socionext,uniphier-l2-cache"; > + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > + <0x506c0000 0x400>; cache-unified; cache-level = <2>; > + /* Not all of UniPhier SoCs have L3 cache */ > + l3-cache@500c8000 { > + compatible = "socionext,uniphier-l3-cache"; > + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, > + <0x506c8000 0x400>; cache-unified; cache-level = <3>; (I'm just assuming this cache is unified, anything else would be baffling.) Further the ePAPR spec optionally supports specifying things like the cache size, number of sets, block size and line size, unless this can be hard coded. Yours, Linus Walleij
Hi Arnd, Russell, 2015-08-26 21:52 GMT+09:00 Arnd Bergmann <arnd@arndb.de>: > On Wednesday 26 August 2015 10:38:59 Masahiro Yamada wrote: >> >> 2015-08-25 4:59 GMT+09:00 Arnd Bergmann <arnd@arndb.de>: >> > On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote: > >> Nothing. >> >> This outer cache is not a variant of l2x0/pl310. >> It was designed only for our SoCs from scratch. > > Ok, I see. > >> > Would it make sense to at least share the >> > common entry point at l2x0_of_init() so you don't need to call it from >> > the platform file? >> >> I do not think so. >> >> >> l2x0_of_init() checks L2X0_AUX_CTRL register, >> but the cache-uniphier does not have such register, >> so the boot code crashes. >> >> >> >> BTW, what makes l2x0_of_init() so special? >> >> Only L2x0/L310 and variants can be initialized >> directly from init_IRQ(). > > The only thing that is special about it is that almost everyone > uses it because it is often licensed together with the Cortex-A > cores from ARM. There are a few variants that are closely related > (tauros3 and aurora, both from Marvell. All other outer_cache > implementations (feroceon, xscale, tauros2) are for older > Marvell (or Intel) cores that have since been replaced with > Cortex-A cores in newer products. > >> Moreover, outer-cache init seems to be unrelated to >> IRQ init. > > Agreed, this is also just a historic artifact, as we don't really > have a place to put cache controller initialization, and the > irq init callback was already there at the time when people > added code to init their outer caches. It often does not matter > much where you call it, but doing it early speeds up the boot > time. > > It would be nice to unify the cache initialization a bit further, > apparently only a few older platforms still call the l2x0 init > manually and we can probably all convert them to the implicit > configuration in one way or another. > > As we now have three kinds of cache controllers (l2x0, tauros2 > and uniphier) that we need to support using DT, it would be nice > for generalize that init sequence a bit more. > > A first step would be to add the tauros2 and uniphier outer cache > init to the init_IRQ() function, and then have another patch > that moves all the outercache initialization into a new place > like arch/arm/mm/outercache.c so we don't clutter up irq.c > with unrelated stuff. > > Russell probably also has some ideas on this topic, in doubt > just do what he suggests. In my v1 patch, the outer cache init is called from .init_machine as some other SoCs do, but if moving my cache_init to init_IRQ() is acceptable, that would be better for faster boot. I will follow Arnd's suggestion in v2 unless Russell is opposed to it. Thanks!
On Wed, Aug 26, 2015 at 02:52:45PM +0200, Arnd Bergmann wrote: > On Wednesday 26 August 2015 10:38:59 Masahiro Yamada wrote: > > Moreover, outer-cache init seems to be unrelated to > > IRQ init. > > Agreed, this is also just a historic artifact, as we don't really > have a place to put cache controller initialization, and the Arnd, I'm afraid you're completely wrong there. It's not a historic artifact by any of the kind. I explicitly placed the L2 cache initialisation there based upon which callbacks into architecture code were available from init/main.c and where in the initialisation sequence I wanted the L2 cache to be initialised _for_ _everyone_. That being, before SMP is brought up, preferably before the delay loop calibration (so we don't calibrate the loop without the L2 cache, and then invalidate that calibration when we enable the cache), but sufficiently late that various services that the L2 cache code wants (like kmalloc) have been initialised. That rules out setup_arch(), leaving trap_init(), init_IRQ(), time_init() and late_time_init(). I chose init_IRQ() out of that lot because it seemed to be a sensible point to initialise it, though trap_init() looks like it could have been another good site. All L2 caches should be initialised at a similar point IMHO - not only does this give us a more consistent initialisation sequence, but it avoids issues such as the one I mention above with delay loop calibration being wrong. > A first step would be to add the tauros2 and uniphier outer cache > init to the init_IRQ() function, and then have another patch > that moves all the outercache initialization into a new place > like arch/arm/mm/outercache.c so we don't clutter up irq.c arch/arm/mm/l2c-common.c > with unrelated stuff.
Hi Linus, 2015-08-26 22:39 GMT+09:00 Linus Walleij <linus.walleij@linaro.org>: > On Mon, Aug 24, 2015 at 4:18 AM, Masahiro Yamada > <yamada.masahiro@socionext.com> wrote: >> This commit adds support for UniPhier outer cache controller. >> All the UniPhier SoCs are equipped with the L2 cache, while the L3 >> cache is currently only integrated on PH1-Pro5 SoC. >> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > > Wow it is really a custom L2$ controller. Wow. Just wow. That's > really brave, given all the problems we've seen in l2x0. Looks like my company is crazy... ARM Ltd. people said we are the only vendor that still uses a custom outer cache. >> +UniPhier SoCs are integrated with a level 2 cache controller that resides >> +outside of the ARM cores, some of them also have a level 3 cache controller. >> + >> +Required properties: >> +- compatible: should be one of the followings: >> + "socionext,uniphier-l2-cache" (L2 cache) >> + "socionext,uniphier-l3-cache" (L3 cache) > > Refer to and use the 3.7.3 ePAPR v1.1 specification too: > https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf I've checked it out. Thanks, but I had some doubts. > cache-unified and cache-level are *not* optional and should be required. "cache-unified" is mentioned in "3.7.3 Internal (L1) Cache Properties" (Table 3-8), but it is not in "3.8 Multi-level and Shared Caches" (Table 3-9) Are the rules in Table 3-8 also applied for L2? > So: > >> +The L2 cache must exist to use the L3 cache; adding only an L3 cache device >> +node to the device tree causes the initialization failure of the whole outer >> +cache system. >> + >> +Example: >> + l2-cache@500c0000 { >> + compatible = "socionext,uniphier-l2-cache"; >> + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, >> + <0x506c0000 0x400>; > > cache-unified; > cache-level = <2>; > >> + /* Not all of UniPhier SoCs have L3 cache */ >> + l3-cache@500c8000 { >> + compatible = "socionext,uniphier-l3-cache"; >> + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, >> + <0x506c8000 0x400>; > > cache-unified; > cache-level = <3>; > > (I'm just assuming this cache is unified, anything else would be baffling.) In fact, unified/harvard is configurable thru a register of this cache controller. It is usually used as a unified cached, though. > Further the ePAPR spec optionally supports specifying things like the > cache size, number of sets, block size and line size, unless this can > be hard coded. > > Yours, > Linus Walleij > Given that cache-level specifies the level and next-level-cache specifies the topology, I think "socionext,uniphier-l*-cache" gives redundant information. The L2 and L3 cache controller look the same; they have the same register maps. The differences between them are register-base, cache-size, cache-sets, line-size, which are specified by properties. So,I am planning to use the same compatible for L2 and L3, like this: l2-cache@500c0000 { compatible = "socionext,uniphier-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; cache-unified; cache-level = <2>; next-level-cache = <&L2>; cache-size = <0x200000>; cache-sets = <256>; cache-line-size = <128>; }; /* Not all of UniPhier SoCs have L3 cache */ l3-cache@500c8000 { compatible = "socionext,uniphier-cache"; reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; cache-unified; cache-level = <3>; cache-size = <0x400000>; cache-sets = <256>; cache-line-size = <256>; }; The Table 3-9 in ePAPR v1.1 says the compatible should be "cache", but I do not think it makes sense here.
On Fri, Aug 28, 2015 at 12:24 PM, Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > 2015-08-26 22:39 GMT+09:00 Linus Walleij <linus.walleij@linaro.org>: >> cache-unified and cache-level are *not* optional and should be required. > > "cache-unified" is mentioned in "3.7.3 Internal (L1) Cache Properties" > (Table 3-8), > but it is not in "3.8 Multi-level and Shared Caches" (Table 3-9) > > Are the rules in Table 3-8 also applied for L2? Your guess is as good as mine unless someone involved in actually writing that spec says something :/ >> (I'm just assuming this cache is unified, anything else would be baffling.) > > In fact, unified/harvard is configurable thru a register of this cache > controller. Jesus Christ. > It is usually used as a unified cached, though. I would, too. > So,I am planning to use the same compatible for L2 and L3, like this: > > > l2-cache@500c0000 { > compatible = "socionext,uniphier-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > <0x506c0000 0x400>; > cache-unified; > cache-level = <2>; > next-level-cache = <&L2>; > cache-size = <0x200000>; > cache-sets = <256>; > cache-line-size = <128>; > }; > > /* Not all of UniPhier SoCs have L3 cache */ > l3-cache@500c8000 { > compatible = "socionext,uniphier-cache"; > reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, > <0x506c8000 0x400>; > cache-unified; > cache-level = <3>; > cache-size = <0x400000>; > cache-sets = <256>; > cache-line-size = <256>; > }; This LooksGoodToMe. > The Table 3-9 in ePAPR v1.1 says > the compatible should be "cache", but I do not think it makes sense here. Agree. Yours, Linus Walleij
On 09/08/2015 08:09 AM, Linus Walleij wrote: > On Fri, Aug 28, 2015 at 12:24 PM, Masahiro Yamada > <yamada.masahiro@socionext.com> wrote: >> 2015-08-26 22:39 GMT+09:00 Linus Walleij <linus.walleij@linaro.org>: > >>> cache-unified and cache-level are *not* optional and should be required. >> >> "cache-unified" is mentioned in "3.7.3 Internal (L1) Cache Properties" >> (Table 3-8), >> but it is not in "3.8 Multi-level and Shared Caches" (Table 3-9) >> >> Are the rules in Table 3-8 also applied for L2? > > Your guess is as good as mine unless someone involved in > actually writing that spec says something :/ Maybe you'd have to be crazy to have Harvard cache for 2nd+ level. I've got no clue. Doesn't hurt to have it. > >>> (I'm just assuming this cache is unified, anything else would be baffling.) >> >> In fact, unified/harvard is configurable thru a register of this cache >> controller. > > Jesus Christ. Hardware designers either hate software folks or ensure our job security. > >> It is usually used as a unified cached, though. > > I would, too. > >> So,I am planning to use the same compatible for L2 and L3, like this: >> >> >> l2-cache@500c0000 { >> compatible = "socionext,uniphier-cache"; >> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, >> <0x506c0000 0x400>; >> cache-unified; >> cache-level = <2>; >> next-level-cache = <&L2>; Next level of the L2 is the L2? >> cache-size = <0x200000>; >> cache-sets = <256>; >> cache-line-size = <128>; >> }; >> >> /* Not all of UniPhier SoCs have L3 cache */ >> l3-cache@500c8000 { >> compatible = "socionext,uniphier-cache"; >> reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, >> <0x506c8000 0x400>; >> cache-unified; >> cache-level = <3>; >> cache-size = <0x400000>; >> cache-sets = <256>; >> cache-line-size = <256>; >> }; > > This LooksGoodToMe. > >> The Table 3-9 in ePAPR v1.1 says >> the compatible should be "cache", but I do not think it makes sense here. > > Agree. It could be useful for finding all cache nodes, but we've generally failed to use it, so at this point it doesn't matter. Rob
diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt new file mode 100644 index 0000000..6428289 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt @@ -0,0 +1,30 @@ +UniPhier outer cache controller + +UniPhier SoCs are integrated with a level 2 cache controller that resides +outside of the ARM cores, some of them also have a level 3 cache controller. + +Required properties: +- compatible: should be one of the followings: + "socionext,uniphier-l2-cache" (L2 cache) + "socionext,uniphier-l3-cache" (L3 cache) +- reg: offsets and lengths of the register sets for the device. It should + contain 3 regions: control registers, revision registers, operation + registers, in this order. + +The L2 cache must exist to use the L3 cache; adding only an L3 cache device +node to the device tree causes the initialization failure of the whole outer +cache system. + +Example: + l2-cache@500c0000 { + compatible = "socionext,uniphier-l2-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + }; + + /* Not all of UniPhier SoCs have L3 cache */ + l3-cache@500c8000 { + compatible = "socionext,uniphier-l3-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a4fbfc8..62e0784 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1578,7 +1578,9 @@ M: Masahiro Yamada <yamada.masahiro@socionext.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/uniphier* +F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ +F: arch/arm/mm/cache-uniphier.c F: drivers/pinctrl/uniphier/ F: drivers/tty/serial/8250/8250_uniphier.c N: uniphier diff --git a/arch/arm/include/asm/hardware/cache-uniphier.h b/arch/arm/include/asm/hardware/cache-uniphier.h new file mode 100644 index 0000000..641d32f --- /dev/null +++ b/arch/arm/include/asm/hardware/cache-uniphier.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CACHE_UNIPHIER_H +#define __CACHE_UNIPHIER_H + +#ifdef CONFIG_CACHE_UNIPHIER +int uniphier_cache_init(void); +int uniphier_cache_init_locked(void); +void uniphier_cache_touch_range(unsigned long start, unsigned long end); +#else +static inline int uniphier_cache_init(void) +{ + return -ENODEV; +} + +static inline int uniphier_cache_init_locked(void) +{ + return -ENODEV; +} + +static inline void uniphier_cache_touch_range(unsigned long start, + unsigned long end) +{ +} + +#endif + +#endif /* __CACHE_UNIPHIER_H */ diff --git a/arch/arm/mach-uniphier/uniphier.c b/arch/arm/mach-uniphier/uniphier.c index 9be10ef..6aed136 100644 --- a/arch/arm/mach-uniphier/uniphier.c +++ b/arch/arm/mach-uniphier/uniphier.c @@ -12,6 +12,8 @@ * GNU General Public License for more details. */ +#include <linux/of_platform.h> +#include <asm/hardware/cache-uniphier.h> #include <asm/mach/arch.h> static const char * const uniphier_dt_compat[] __initconst = { @@ -25,6 +27,15 @@ static const char * const uniphier_dt_compat[] __initconst = { NULL, }; +static void __init uniphier_init_machine(void) +{ + if (uniphier_cache_init()) + pr_warn("outer cache was not enabled"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + DT_MACHINE_START(UNIPHIER, "Socionext UniPhier") .dt_compat = uniphier_dt_compat, + .init_machine = uniphier_init_machine, MACHINE_END diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7c6b976..7b33ff3 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -985,6 +985,16 @@ config CACHE_TAUROS2 This option enables the Tauros2 L2 cache controller (as found on PJ1/PJ4). +config CACHE_UNIPHIER + bool "Enable the UniPhier outer cache controller" + depends on ARCH_UNIPHIER + default y + select OUTER_CACHE + select OUTER_CACHE_SYNC + help + This option enables the UniPhier outer cache (system cache) + controller. + config CACHE_XSC3L2 bool "Enable the L2 cache on XScale3" depends on CPU_XSC3 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 57c8df5..7f76d96 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -103,3 +103,4 @@ obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o l2c-l2x0-resume.o obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o +obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c new file mode 100644 index 0000000..9eb0665 --- /dev/null +++ b/arch/arm/mm/cache-uniphier.c @@ -0,0 +1,518 @@ +/* + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of_address.h> +#include <asm/hardware/cache-uniphier.h> +#include <asm/outercache.h> + +/* control registers */ +#define UNIPHIER_SSCC 0x0 /* Control Register */ +#define UNIPHIER_SSCC_BST BIT(20) /* UCWG burst read */ +#define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */ +#define UNIPHIER_SSCC_WTG BIT(18) /* WT gathering on */ +#define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */ +#define UNIPHIER_SSCC_ON BIT(0) /* enable cache */ +#define UNIPHIER_SSCLPDAWCR 0x30 /* Unified/Data Active Way Control */ +#define UNIPHIER_SSCLPIAWCR 0x34 /* Instruction Active Way Control */ + +/* revision registers */ +#define UNIPHIER_SSCID 0x0 /* ID Register */ + +/* operation registers */ +#define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */ +#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */ +#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */ +#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */ +#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */ +#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */ +#define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */ +#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21) +#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21) +#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21) +#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21) +#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17) +#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17) +#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17) +#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17) +#define UNIPHIER_SSCOQM_CE BIT(15) /* notify completion */ +#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */ +#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */ +#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */ +#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */ +#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */ +#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */ +#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */ +#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */ +#define UNIPHIER_SSCOQAD 0x24c /* Cache Operation Queue Address */ +#define UNIPHIER_SSCOQSZ 0x250 /* Cache Operation Queue Size */ +#define UNIPHIER_SSCOQMASK 0x254 /* Cache Operation Queue Address Mask */ +#define UNIPHIER_SSCOQWN 0x258 /* Cache Operation Queue Way Number */ +#define UNIPHIER_SSCOPPQSEF 0x25c /* Cache Operation Queue Set Complete*/ +#define UNIPHIER_SSCOPPQSEF_FE BIT(1) +#define UNIPHIER_SSCOPPQSEF_OE BIT(0) +#define UNIPHIER_SSCOLPQS 0x260 /* Cache Operation Queue Status */ +#define UNIPHIER_SSCOLPQS_EF BIT(2) +#define UNIPHIER_SSCOLPQS_EST BIT(1) +#define UNIPHIER_SSCOLPQS_QST BIT(0) + +/* Is the touch/pre-fetch destination specified by ways? */ +#define UNIPHIER_SSCOQM_TID_IS_WAY(op) \ + ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY) +/* Is the operation region specified by address range? */ +#define UNIPHIER_SSCOQM_S_IS_RANGE(op) \ + ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE) +/* Is the operation region specified by ways? */ +#define UNIPHIER_SSCOQM_S_IS_WAY(op) \ + ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_WAY) + +#define UNIPHIER_L2_CACHE_LINE_SIZE 128 +#define UNIPHIER_L3_CACHE_LINE_SIZE 256 + +/** + * uniphier_cache_data - UniPhier outer cache specific data + * + * @ctrl_base: virtual base address of control registers + * @rev_base: virtual base address of revision registers + * @op_base: virtual base address of operation registers + * @line_size: line size, which range operations must be aligned to + * @range_op_max_size: max data size for a single range operation can handle + */ +static struct uniphier_cache_data { + void __iomem *ctrl_base; + void __iomem *rev_base; + void __iomem *op_base; + unsigned int line_size; + unsigned long range_op_max_size; +} uniphier_cache_data[]; + +/* the number of detected outer cache levels (0: none, 1: L2, 2: L2&L3) */ +static int uniphier_outer_levels; + +/** + * __uniphier_cache_sync - perform a sync point for a particular cache level + * + * @data: cache controller specific data + */ +static void __uniphier_cache_sync(struct uniphier_cache_data *data) +{ + /* This sequence need not be atomic. Do not disable IRQ. */ + writel_relaxed(UNIPHIER_SSCOPE_CM_SYNC, + data->op_base + UNIPHIER_SSCOPE); + /* need a read back to confirm */ + readl_relaxed(data->op_base + UNIPHIER_SSCOPE); +} + +/** + * __uniphier_cache_maint_common - run a queue operation for a particular level + * + * @data: cache controller specific data + * @start: start address of range operation (don't care for "all" operation) + * @size: data size of range operation (don't care for "all" operation) + * @operation: flags to specify the desired cache operation + */ +static void __uniphier_cache_maint_common(struct uniphier_cache_data *data, + unsigned long start, + unsigned long size, + u32 operation) +{ + unsigned long flags; + + /* + * The IRQ must be disable during this sequence because the accessor + * holds the access right of the operation queue registers. + * Restore the IRQ after releasing the register access right. + */ + local_irq_save(flags); + + /* clear the complete notification flag */ + writel_relaxed(UNIPHIER_SSCOLPQS_EF, data->op_base + UNIPHIER_SSCOLPQS); + + /* + * We do not need a spin lock here because the hardware guarantees + * this sequence is atomic, i.e. the write access is arbitrated + * and only the winner's write accesses take effect. + * After register settings, we need to check the UNIPHIER_SSCOPPQSEF to + * see if we won the arbitration or not. + * If the command was not successfully set, just try again. + */ + do { + /* set cache operation */ + writel_relaxed(UNIPHIER_SSCOQM_CE | operation, + data->op_base + UNIPHIER_SSCOQM); + + /* set address range if needed */ + if (likely(UNIPHIER_SSCOQM_S_IS_RANGE(operation))) { + writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD); + writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ); + } + + /* set target ways if needed */ + if (unlikely(UNIPHIER_SSCOQM_S_IS_WAY(operation) || + UNIPHIER_SSCOQM_TID_IS_WAY(operation))) + /* set all the locked ways as destination */ + writel_relaxed(~readl_relaxed(data->ctrl_base + + UNIPHIER_SSCLPDAWCR), + data->op_base + UNIPHIER_SSCOQWN); + } while (unlikely(readl_relaxed(data->op_base + UNIPHIER_SSCOPPQSEF) & + (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE))); + + /* wait until the operation is completed */ + while (likely(readl_relaxed(data->op_base + UNIPHIER_SSCOLPQS) != + UNIPHIER_SSCOLPQS_EF)) + cpu_relax(); + + local_irq_restore(flags); +} + +static void __uniphier_cache_maint_all(struct uniphier_cache_data *data, + u32 operation) +{ + __uniphier_cache_maint_common(data, 0, 0, + UNIPHIER_SSCOQM_S_ALL | operation); + + __uniphier_cache_sync(data); +} + +static void __uniphier_cache_maint_range(struct uniphier_cache_data *data, + unsigned long start, unsigned long end, + u32 operation) +{ + unsigned long size; + + /* + * If the start address is not aligned, + * perform a cache operation for the first cache-line + */ + start = start & ~(data->line_size - 1); + + size = end - start; + + if (unlikely(size >= (unsigned long)(-data->line_size))) { + /* this means cache operation for all range */ + __uniphier_cache_maint_all(data, operation); + return; + } + + /* + * If the end address is not aligned, + * perform a cache operation for the last cache-line + */ + size = ALIGN(size, data->line_size); + + while (size) { + u32 chunk_size = min(size, data->range_op_max_size); + + __uniphier_cache_maint_common(data, start, chunk_size, + UNIPHIER_SSCOQM_S_RANGE | operation); + + start += chunk_size; + size -= chunk_size; + } + + __uniphier_cache_sync(data); +} + +static void __uniphier_cache_enable(struct uniphier_cache_data *data, bool on) +{ + u32 val = 0; + + if (on) + val = UNIPHIER_SSCC_WTG | UNIPHIER_SSCC_PRD | UNIPHIER_SSCC_ON; + + writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC); +} + +static void __uniphier_cache_set_active_ways(struct uniphier_cache_data *data, + u32 ways) +{ + writel_relaxed(ways, data->ctrl_base + UNIPHIER_SSCLPDAWCR); +} + +static void uniphier_cache_maint_all(u32 operation) +{ + int i; + + for (i = 0; i < uniphier_outer_levels; i++) + __uniphier_cache_maint_all(&uniphier_cache_data[i], operation); +} + +static void uniphier_cache_maint_range(unsigned long start, unsigned long end, + u32 operation) +{ + int i; + + for (i = 0; i < uniphier_outer_levels; i++) + __uniphier_cache_maint_range(&uniphier_cache_data[i], + start, end, operation); +} + +static void uniphier_cache_inv_range(unsigned long start, unsigned long end) +{ + uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV); +} + +static void uniphier_cache_clean_range(unsigned long start, unsigned long end) +{ + uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_CLEAN); +} + +static void uniphier_cache_flush_range(unsigned long start, unsigned long end) +{ + uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH); +} + +void __init uniphier_cache_touch_range(unsigned long start, unsigned long end) +{ + uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_TID_WAY | + UNIPHIER_SSCOQM_CM_TOUCH); +} + +static void __init uniphier_cache_inv_all(void) +{ + uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV); +} + +static void uniphier_cache_flush_all(void) +{ + uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH); +} + +static void uniphier_cache_disable(void) +{ + int i; + + for (i = uniphier_outer_levels - 1; i >= 0; i--) + __uniphier_cache_enable(&uniphier_cache_data[i], false); + + uniphier_cache_flush_all(); +} + +static void __init uniphier_cache_enable(void) +{ + int i; + + uniphier_cache_inv_all(); + + for (i = 0; i < uniphier_outer_levels; i++) + __uniphier_cache_enable(&uniphier_cache_data[i], true); +} + +static void uniphier_cache_sync(void) +{ + int i; + + for (i = 0; i < uniphier_outer_levels; i++) + __uniphier_cache_sync(&uniphier_cache_data[i]); +} + +static void __init uniphier_cache_set_active_ways(u32 ways) +{ + int i; + + for (i = 0; i < uniphier_outer_levels; i++) + __uniphier_cache_set_active_ways(&uniphier_cache_data[i], + ways); +} + +static int __init uniphier_cache_common_init(struct device_node *np, + struct uniphier_cache_data *data) +{ + data->ctrl_base = of_iomap(np, 0); + if (!data->ctrl_base) + return -ENOMEM; + + data->rev_base = of_iomap(np, 1); + if (!data->rev_base) + goto err; + + data->op_base = of_iomap(np, 2); + if (!data->op_base) + goto err; + + return 0; +err: + iounmap(data->rev_base); + iounmap(data->ctrl_base); + + return -ENOMEM; +} + +static int __init uniphier_l2_cache_init(struct device_node *np, + struct uniphier_cache_data *data) +{ + int ret; + u32 revision; + + ret = uniphier_cache_common_init(np, data); + if (ret) + return ret; + + data->line_size = UNIPHIER_L2_CACHE_LINE_SIZE; + + revision = readl(data->rev_base + UNIPHIER_SSCID); + + if (revision >= 0x17) /* PH1-Pro5 or later */ + data->range_op_max_size = (u32)-data->line_size; + else + data->range_op_max_size = (1UL << 22) - data->line_size; + + writel_relaxed(0, data->ctrl_base + UNIPHIER_SSCC); + + return 0; +} + +static int __init uniphier_l3_cache_init(struct device_node *np, + struct uniphier_cache_data *data) +{ + int ret; + + ret = uniphier_cache_common_init(np, data); + if (ret) + return ret; + + data->line_size = UNIPHIER_L3_CACHE_LINE_SIZE; + + data->range_op_max_size = (u32)-data->line_size; + + return 0; +} + +static const struct of_device_id uniphier_l2_cache_match[] __initconst = { + { + .compatible = "socionext,uniphier-l2-cache", + .data = uniphier_l2_cache_init, + }, + { /* sentinel */ } +}; + +static const struct of_device_id uniphier_l3_cache_match[] __initconst = { + { + .compatible = "socionext,uniphier-l3-cache", + .data = uniphier_l3_cache_init, + }, + { /* sentinel */ } +}; + +static const struct of_device_id *const uniphier_cache_matches[] __initconst = { + uniphier_l2_cache_match, + uniphier_l3_cache_match, +}; + +#define UNIPHIER_CACHE_LEVELS (ARRAY_SIZE(uniphier_cache_matches)) + +static struct uniphier_cache_data uniphier_cache_data[UNIPHIER_CACHE_LEVELS]; + +static int __init __uniphier_cache_init(void) +{ + int (*initf)(struct device_node *np, struct uniphier_cache_data *data); + static int done; + static int ret; + struct device_node *np; + const struct of_device_id *match; + int i; + + if (done) + return ret; + + for (i = 0; ARRAY_SIZE(uniphier_cache_matches); i++) { + np = of_find_matching_node_and_match(NULL, + uniphier_cache_matches[i], + &match); + if (!np) { + ret = -ENODEV; + break; + } + + initf = match->data; + ret = initf(np, &uniphier_cache_data[i]); + if (ret) + break; + } + + uniphier_outer_levels = i; + + /* + * Error out iif L2 initialization fails. + * Continue with any error on L3 because it is optional. + */ + if (uniphier_outer_levels == 0) { + ret = ret ?: -ENODEV; + pr_err("uniphier: failed to initialize outer cache\n"); + goto out; + } else { + ret = 0; + } + + outer_cache.inv_range = uniphier_cache_inv_range; + outer_cache.clean_range = uniphier_cache_clean_range; + outer_cache.flush_range = uniphier_cache_flush_range; + outer_cache.flush_all = uniphier_cache_flush_all; + outer_cache.disable = uniphier_cache_disable; + outer_cache.sync = uniphier_cache_sync; + + uniphier_cache_enable(); + +out: + done = 1; + + return ret; +} + +/** + * uniphier_cache_init - initialize outer cache and set all the ways active + * + * This enables the outer cache for the normal operation. + */ +int __init uniphier_cache_init(void) +{ + int ret; + + ret = __uniphier_cache_init(); + if (ret) + return ret; + + uniphier_cache_set_active_ways(U32_MAX); + + pr_info("uniphier: enabled outer cache (%s)\n", + uniphier_outer_levels >= 2 ? "L2 and L3" : "L2"); + + return 0; +} + +/** + * uniphier_cache_init_locked - initialize outer cache and lock all the ways + * + * This enables the outer cache, but never performs the refill operations. + * If the data at the accessed address is found in the cache (cache-hit), the + * data is transferred to the CPU. If not (cache-miss), the desired data is + * fetched from the main memory, but the contents in the cache are _not_ + * replaced. This is generally used to keep particular data in the cache. + */ +int __init uniphier_cache_init_locked(void) +{ + int ret; + + ret = __uniphier_cache_init(); + if (ret) + return ret; + + uniphier_cache_set_active_ways(0); + + pr_info("uniphier: set up outer cache (%s) as locked cache\n", + uniphier_outer_levels >= 2 ? "L2 and L3" : "L2"); + + return 0; +}
This commit adds support for UniPhier outer cache controller. All the UniPhier SoCs are equipped with the L2 cache, while the L3 cache is currently only integrated on PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- .../bindings/arm/uniphier/cache-uniphier.txt | 30 ++ MAINTAINERS | 2 + arch/arm/include/asm/hardware/cache-uniphier.h | 40 ++ arch/arm/mach-uniphier/uniphier.c | 11 + arch/arm/mm/Kconfig | 10 + arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-uniphier.c | 518 +++++++++++++++++++++ 7 files changed, 612 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt create mode 100644 arch/arm/include/asm/hardware/cache-uniphier.h create mode 100644 arch/arm/mm/cache-uniphier.c