| Message ID | 1442485969-1733-1-git-send-email-zhengxing@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Donnerstag, 17. September 2015, 18:32:49 schrieb Xing Zheng: > Add the devicetree binding for the cru on the rk3036 which quite similar > structured as previous clock controllers. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > --- > > Changes in v2: None > > .../bindings/clock/rockchip,rk3036-cru.txt | 60 > ++++++++++++++++++++ 1 file changed, 60 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt > b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file > mode 100644 > index 0000000..ac3037a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt > @@ -0,0 +1,60 @@ > +* Rockchip RK3036 Clock and Reset Unit > + > +The RK3036 clock controller generates and supplies clock to various > +controllers within the SoC and also implements a reset controller for SoC > +peripherals. > + > +Required Properties: > + > +- compatible: should be "rockchip,rk3036-cru" > +- reg: physical base address of the controller and length of memory mapped > + region. > +- #clock-cells: should be 1. > +- #reset-cells: should be 1. > + > +Optional Properties: > + > +- rockchip,grf: phandle to the syscon managing the "general register files" > + If missing pll rates are not changable, due to the missing pll lock > status. + > +Each clock is assigned an identifier and client nodes can use this > identifier +to specify the clock which they consume. All available clocks > are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h > headers and can be +used in device tree sources. Similar macros exist for > the reset sources in +these files. > + > +External clocks: > + > +There are several clocks that are generated outside the SoC. It is expected > +that they are defined using standard clock bindings with following > +clock-output-names: > + - "xin24m" - crystal input - required, > + - "xin32k" - rtc clock - optional, The rk3036 does not seem to use a rtc clock, so this should probably go away > + - "ext_i2s" - external I2S clock - optional, > + - "ext_hsadc" - external HSADC clock - optional, > + - "ext_vip" - external VIP clock - optional, > + - "ext_isp" - external ISP clock - optional, > + - "ext_jtag" - external JTAG clock - optional There do not seem to exist external clock sources for hsadc, vip, isp and jtag in your clock tree? missing here: - ext_gmac > + > +Example: Clock controller node: > + > + cru: cru@20000000 { > + compatible = "rockchip,rk3036-cru"; > + reg = <0x20000000 0x1000>; > + rockchip,grf = <&grf>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > +Example: UART controller node that consumes the clock generated by the > clock + controller: > + > + uart0: serial@20060000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x20060000 0x100>; > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&cru SCLK_UART0>; > + };
On 2015?09?17? 23:09, Heiko Stübner wrote: > Am Donnerstag, 17. September 2015, 18:32:49 schrieb Xing Zheng: >> Add the devicetree binding for the cru on the rk3036 which quite similar >> structured as previous clock controllers. >> >> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com> >> --- >> >> Changes in v2: None >> >> .../bindings/clock/rockchip,rk3036-cru.txt | 60 >> ++++++++++++++++++++ 1 file changed, 60 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt >> b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file >> mode 100644 >> index 0000000..ac3037a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt >> @@ -0,0 +1,60 @@ >> +* Rockchip RK3036 Clock and Reset Unit >> + >> +The RK3036 clock controller generates and supplies clock to various >> +controllers within the SoC and also implements a reset controller for SoC >> +peripherals. >> + >> +Required Properties: >> + >> +- compatible: should be "rockchip,rk3036-cru" >> +- reg: physical base address of the controller and length of memory mapped >> + region. >> +- #clock-cells: should be 1. >> +- #reset-cells: should be 1. >> + >> +Optional Properties: >> + >> +- rockchip,grf: phandle to the syscon managing the "general register files" >> + If missing pll rates are not changable, due to the missing pll lock >> status. + >> +Each clock is assigned an identifier and client nodes can use this >> identifier +to specify the clock which they consume. All available clocks >> are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h >> headers and can be +used in device tree sources. Similar macros exist for >> the reset sources in +these files. >> + >> +External clocks: >> + >> +There are several clocks that are generated outside the SoC. It is expected >> +that they are defined using standard clock bindings with following >> +clock-output-names: >> + - "xin24m" - crystal input - required, >> + - "xin32k" - rtc clock - optional, > The rk3036 does not seem to use a rtc clock, so this should probably go away Done. >> + - "ext_i2s" - external I2S clock - optional, >> + - "ext_hsadc" - external HSADC clock - optional, >> + - "ext_vip" - external VIP clock - optional, >> + - "ext_isp" - external ISP clock - optional, >> + - "ext_jtag" - external JTAG clock - optional > There do not seem to exist external clock sources for hsadc, vip, isp and jtag > in your clock tree? > > missing here: > - ext_gmac Yes, done. >> + >> +Example: Clock controller node: >> + >> + cru: cru@20000000 { >> + compatible = "rockchip,rk3036-cru"; >> + reg =<0x20000000 0x1000>; >> + rockchip,grf =<&grf>; >> + >> + #clock-cells =<1>; >> + #reset-cells =<1>; >> + }; >> + >> +Example: UART controller node that consumes the clock generated by the >> clock + controller: >> + >> + uart0: serial@20060000 { >> + compatible = "snps,dw-apb-uart"; >> + reg =<0x20060000 0x100>; >> + interrupts =<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + clocks =<&cru SCLK_UART0>; >> + }; Thanks.
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file mode 100644 index 0000000..ac3037a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt @@ -0,0 +1,60 @@ +* Rockchip RK3036 Clock and Reset Unit + +The RK3036 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3036-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "ext_i2s" - external I2S clock - optional, + - "ext_hsadc" - external HSADC clock - optional, + - "ext_vip" - external VIP clock - optional, + - "ext_isp" - external ISP clock - optional, + - "ext_jtag" - external JTAG clock - optional + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@20060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + };
Add the devicetree binding for the cru on the rk3036 which quite similar structured as previous clock controllers. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- Changes in v2: None .../bindings/clock/rockchip,rk3036-cru.txt | 60 ++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt