diff mbox

[3/3] drm/i915/chv: remove pre-production hardware workarounds

Message ID 1444205866-5355-3-git-send-email-jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jani Nikula Oct. 7, 2015, 8:17 a.m. UTC 
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++------------------------
 1 file changed, 22 insertions(+), 33 deletions(-)

Comments

kernel test robot Oct. 7, 2015, 8:31 a.m. UTC | #1 
Hi Jani,

[auto build test WARNING on v4.3-rc4 -- if it's inappropriate base, please ignore]

config: x86_64-randconfig-x006-201540 (attached as .config)
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_pm.c: In function 'cherryview_rps_guar_freq':
>> drivers/gpu/drm/i915/intel_pm.c:5187:21: warning: unused variable 'dev' [-Wunused-variable]
     struct drm_device *dev = dev_priv->dev;
                        ^

vim +/dev +5187 drivers/gpu/drm/i915/intel_pm.c

965cb130 Jani Nikula 2015-10-07  5171  
2b6b3a09 Deepak S    2014-05-27  5172  	return rp0;
2b6b3a09 Deepak S    2014-05-27  5173  }
2b6b3a09 Deepak S    2014-05-27  5174  
2b6b3a09 Deepak S    2014-05-27  5175  static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2b6b3a09 Deepak S    2014-05-27  5176  {
2b6b3a09 Deepak S    2014-05-27  5177  	u32 val, rpe;
2b6b3a09 Deepak S    2014-05-27  5178  
2b6b3a09 Deepak S    2014-05-27  5179  	val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
2b6b3a09 Deepak S    2014-05-27  5180  	rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
2b6b3a09 Deepak S    2014-05-27  5181  
2b6b3a09 Deepak S    2014-05-27  5182  	return rpe;
2b6b3a09 Deepak S    2014-05-27  5183  }
2b6b3a09 Deepak S    2014-05-27  5184  
7707df4a Deepak S    2014-07-12  5185  static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
7707df4a Deepak S    2014-07-12  5186  {
095acd5f Deepak S    2015-01-17 @5187  	struct drm_device *dev = dev_priv->dev;
7707df4a Deepak S    2014-07-12  5188  	u32 val, rp1;
7707df4a Deepak S    2014-07-12  5189  
095acd5f Deepak S    2015-01-17  5190  	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
095acd5f Deepak S    2015-01-17  5191  	rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
965cb130 Jani Nikula 2015-10-07  5192  
7707df4a Deepak S    2014-07-12  5193  	return rp1;
7707df4a Deepak S    2014-07-12  5194  }
7707df4a Deepak S    2014-07-12  5195  

:::::: The code at line 5187 was first introduced by commit
:::::: 095acd5f8739aa8322820d460e617898baf092df drm/i915: New offset for reading frequencies on CHV.

:::::: TO: Deepak S <deepak.s@linux.intel.com>
:::::: CC: Daniel Vetter <daniel.vetter@ffwll.ch>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Ville Syrjälä Oct. 7, 2015, 1:28 p.m. UTC | #2 
On Wed, Oct 07, 2015 at 11:17:46AM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++------------------------
>  1 file changed, 22 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 60d120c472ab..598ee4c8d86e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5061,32 +5061,27 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>  	struct drm_device *dev = dev_priv->dev;
>  	u32 val, rp0;
>  
> -	if (dev->pdev->revision >= 0x20) {

Yep. C0 is the first production stepping.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> -		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> +	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
>  
> -		switch (INTEL_INFO(dev)->eu_total) {
> -		case 8:
> -				/* (2 * 4) config */
> -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> -				break;
> -		case 12:
> -				/* (2 * 6) config */
> -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
> -				break;
> -		case 16:
> -				/* (2 * 8) config */
> -		default:
> -				/* Setting (2 * 8) Min RP0 for any other combination */
> -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
> -				break;
> -		}
> -		rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
> -	} else {
> -		/* For pre-production hardware */
> -		val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> -		rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> -		       PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> +	switch (INTEL_INFO(dev)->eu_total) {
> +	case 8:
> +		/* (2 * 4) config */
> +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> +		break;
> +	case 12:
> +		/* (2 * 6) config */
> +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
> +		break;
> +	case 16:
> +		/* (2 * 8) config */
> +	default:
> +		/* Setting (2 * 8) Min RP0 for any other combination */
> +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
> +		break;
>  	}
> +
> +	rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
> +
>  	return rp0;
>  }
>  
> @@ -5105,15 +5100,9 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
>  	struct drm_device *dev = dev_priv->dev;
>  	u32 val, rp1;
>  
> -	if (dev->pdev->revision >= 0x20) {
> -		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> -		rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
> -	} else {
> -		/* For pre-production hardware */
> -		val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -		rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> -		       PUNIT_GPU_STATUS_MAX_FREQ_MASK);
> -	}
> +	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> +	rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
> +
>  	return rp1;
>  }
>  
> -- 
> 2.1.4
Daniel Vetter Oct. 7, 2015, 2:32 p.m. UTC | #3 
On Wed, Oct 07, 2015 at 04:28:48PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 11:17:46AM +0300, Jani Nikula wrote:
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++------------------------
> >  1 file changed, 22 insertions(+), 33 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 60d120c472ab..598ee4c8d86e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5061,32 +5061,27 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> >  	struct drm_device *dev = dev_priv->dev;
> >  	u32 val, rp0;
> >  
> > -	if (dev->pdev->revision >= 0x20) {
> 
> Yep. C0 is the first production stepping.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Applied both patch 1&3 from this series, with gcc appeased on this patch
here.

Thanks, Daniel
> 
> > -		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> > +	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> >  
> > -		switch (INTEL_INFO(dev)->eu_total) {
> > -		case 8:
> > -				/* (2 * 4) config */
> > -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> > -				break;
> > -		case 12:
> > -				/* (2 * 6) config */
> > -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
> > -				break;
> > -		case 16:
> > -				/* (2 * 8) config */
> > -		default:
> > -				/* Setting (2 * 8) Min RP0 for any other combination */
> > -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
> > -				break;
> > -		}
> > -		rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
> > -	} else {
> > -		/* For pre-production hardware */
> > -		val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> > -		rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> > -		       PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> > +	switch (INTEL_INFO(dev)->eu_total) {
> > +	case 8:
> > +		/* (2 * 4) config */
> > +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> > +		break;
> > +	case 12:
> > +		/* (2 * 6) config */
> > +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
> > +		break;
> > +	case 16:
> > +		/* (2 * 8) config */
> > +	default:
> > +		/* Setting (2 * 8) Min RP0 for any other combination */
> > +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
> > +		break;
> >  	}
> > +
> > +	rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
> > +
> >  	return rp0;
> >  }
> >  
> > @@ -5105,15 +5100,9 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
> >  	struct drm_device *dev = dev_priv->dev;
> >  	u32 val, rp1;
> >  
> > -	if (dev->pdev->revision >= 0x20) {
> > -		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> > -		rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
> > -	} else {
> > -		/* For pre-production hardware */
> > -		val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > -		rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> > -		       PUNIT_GPU_STATUS_MAX_FREQ_MASK);
> > -	}
> > +	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> > +	rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
> > +
> >  	return rp1;
> >  }
> >  
> > -- 
> > 2.1.4
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 60d120c472ab..598ee4c8d86e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5061,32 +5061,27 @@  static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	u32 val, rp0;
 
-	if (dev->pdev->revision >= 0x20) {
-		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
 
-		switch (INTEL_INFO(dev)->eu_total) {
-		case 8:
-				/* (2 * 4) config */
-				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
-				break;
-		case 12:
-				/* (2 * 6) config */
-				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
-				break;
-		case 16:
-				/* (2 * 8) config */
-		default:
-				/* Setting (2 * 8) Min RP0 for any other combination */
-				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
-				break;
-		}
-		rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
-	} else {
-		/* For pre-production hardware */
-		val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
-		rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
-		       PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+	switch (INTEL_INFO(dev)->eu_total) {
+	case 8:
+		/* (2 * 4) config */
+		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
+		break;
+	case 12:
+		/* (2 * 6) config */
+		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
+		break;
+	case 16:
+		/* (2 * 8) config */
+	default:
+		/* Setting (2 * 8) Min RP0 for any other combination */
+		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
+		break;
 	}
+
+	rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
+
 	return rp0;
 }
 
@@ -5105,15 +5100,9 @@  static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	u32 val, rp1;
 
-	if (dev->pdev->revision >= 0x20) {
-		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
-		rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
-	} else {
-		/* For pre-production hardware */
-		val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-		rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
-		       PUNIT_GPU_STATUS_MAX_FREQ_MASK);
-	}
+	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+	rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
+
 	return rp1;
 }