| Message ID | 1444578364-1384-3-git-send-email-linux.amoon@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 12.10.2015 00:46, Anand Moon wrote: > Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) This description is not entirely correct. The MMC driver already supports these UHS speeds (you did not any code) so you rather enabled it (description of bindings says "is supported"). You mentioned DDR50 but I don't see respective property below. How do you know that these modes are really supported? I don't know. Can you convince me? > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > --- > Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch > > Changes Fixed the UHS-I bus speed detedtion on cold boot. I don't get what is exactly fixed here. What was the error? What is the outcome of this fix? The log below is before or after? Best regards, Krzysztof > > [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) > [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa > [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 2.461743] mmcblk0: p1 p2 > --- > arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > index 58c06d3..ba4a87b 100644 > --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > @@ -364,6 +364,10 @@ > pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; > bus-width = <4>; > cap-sd-highspeed; > + sd-uhs-sdr12; > + sd-uhs-sdr25; > + sd-uhs-sdr50; > + sd-uhs-sdr104; > }; > > &pinctrl_0 { > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Krzysztof, On 12 October 2015 at 11:14, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 12.10.2015 00:46, Anand Moon wrote: >> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) > > This description is not entirely correct. The MMC driver already > supports these UHS speeds (you did not any code) so you rather enabled > it (description of bindings says "is supported"). > > You mentioned DDR50 but I don't see respective property below. Looks like I missed it, I will add this in the next patch, > > How do you know that these modes are really supported? I don't know. Can > you convince me? > >> >> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >> >> --- >> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >> >> Changes Fixed the UHS-I bus speed detedtion on cold boot. > > I don't get what is exactly fixed here. What was the error? What is the > outcome of this fix? The log below is before or after? > > Best regards, > Krzysztof > >> >> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 2.461743] mmcblk0: p1 p2 > >> --- >> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> index 58c06d3..ba4a87b 100644 >> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> @@ -364,6 +364,10 @@ >> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >> bus-width = <4>; >> cap-sd-highspeed; >> + sd-uhs-sdr12; >> + sd-uhs-sdr25; >> + sd-uhs-sdr50; >> + sd-uhs-sdr104; >> }; >> >> &pinctrl_0 { >> > Changes were made to support Sandisk Ultra UHS-I class 10 card support. OdroidXU3/XU4 board would not boot up using this card. Depending on the capability of the UHS-I card, the speed of the card is selected. I have just added the enhance capability feature to support them. On warm boot: i.e reboot of the board. [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.657555] mmc1: new high speed SDHC card at address aaaa [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.669206] mmcblk0: p1 p2 On cold boot:: ie: power on the board. [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.650293] IRQ56 no longer affine to CPU7 [ 4.650581] CPU7: shutdown [ 4.658293] mmcblk0: p1 p2 Note: Their is need to reset the PMIC S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers to support this feature consistently on every reboot. -Anand Moon -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/12/2015 07:46 PM, Anand Moon wrote: > Hi Krzysztof, > > On 12 October 2015 at 11:14, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> On 12.10.2015 00:46, Anand Moon wrote: >>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >> >> This description is not entirely correct. The MMC driver already >> supports these UHS speeds (you did not any code) so you rather enabled >> it (description of bindings says "is supported"). >> >> You mentioned DDR50 but I don't see respective property below. > Looks like I missed it, I will add this in the next patch, >> >> How do you know that these modes are really supported? I don't know. Can >> you convince me? >> > >>> >>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>> >>> --- >>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>> >>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >> >> I don't get what is exactly fixed here. What was the error? What is the >> outcome of this fix? The log below is before or after? >> >> Best regards, >> Krzysztof >> >>> >>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>> [ 2.461743] mmcblk0: p1 p2 >> >>> --- >>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> index 58c06d3..ba4a87b 100644 >>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> @@ -364,6 +364,10 @@ >>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>> bus-width = <4>; >>> cap-sd-highspeed; >>> + sd-uhs-sdr12; >>> + sd-uhs-sdr25; >>> + sd-uhs-sdr50; >>> + sd-uhs-sdr104; >>> }; >>> >>> &pinctrl_0 { >>> >> > > Changes were made to support Sandisk Ultra UHS-I class 10 card support. > OdroidXU3/XU4 board would not boot up using this card. > > Depending on the capability of the UHS-I card, the speed of the card > is selected. > I have just added the enhance capability feature to support them. > > On warm boot: i.e reboot of the board. > [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > req 50000000Hz, actual 50000000HZ div = 0) > [ 4.657555] mmc1: new high speed SDHC card at address aaaa > [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 4.669206] mmcblk0: p1 p2 > > On cold boot:: ie: power on the board. > > [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot > req 100000000Hz, actual 100000000HZ div = 0) > [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa > [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 4.650293] IRQ56 no longer affine to CPU7 > [ 4.650581] CPU7: shutdown > [ 4.658293] mmcblk0: p1 p2 > > Note: Their is need to reset the PMIC > S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers > to support this feature consistently on every reboot. I don't understand...why needs to reset? I know it needs to switch the voltage, doesn't it? Best Regards, Jaehoon Chung > > -Anand Moon > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Jaehoon Chung On 12 October 2015 at 16:21, Jaehoon Chung <jh80.chung@samsung.com> wrote: > On 10/12/2015 07:46 PM, Anand Moon wrote: >> Hi Krzysztof, >> >> On 12 October 2015 at 11:14, Krzysztof Kozlowski >> <k.kozlowski@samsung.com> wrote: >>> On 12.10.2015 00:46, Anand Moon wrote: >>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>> >>> This description is not entirely correct. The MMC driver already >>> supports these UHS speeds (you did not any code) so you rather enabled >>> it (description of bindings says "is supported"). >>> >>> You mentioned DDR50 but I don't see respective property below. >> Looks like I missed it, I will add this in the next patch, >>> >>> How do you know that these modes are really supported? I don't know. Can >>> you convince me? >>> >> >>>> >>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>>> >>>> --- >>>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>>> >>>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >>> >>> I don't get what is exactly fixed here. What was the error? What is the >>> outcome of this fix? The log below is before or after? >>> >>> Best regards, >>> Krzysztof >>> >>>> >>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 2.461743] mmcblk0: p1 p2 >>> >>>> --- >>>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>> index 58c06d3..ba4a87b 100644 >>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>> @@ -364,6 +364,10 @@ >>>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>>> bus-width = <4>; >>>> cap-sd-highspeed; >>>> + sd-uhs-sdr12; >>>> + sd-uhs-sdr25; >>>> + sd-uhs-sdr50; >>>> + sd-uhs-sdr104; >>>> }; >>>> >>>> &pinctrl_0 { >>>> >>> >> >> Changes were made to support Sandisk Ultra UHS-I class 10 card support. >> OdroidXU3/XU4 board would not boot up using this card. >> >> Depending on the capability of the UHS-I card, the speed of the card >> is selected. >> I have just added the enhance capability feature to support them. >> >> On warm boot: i.e reboot of the board. >> [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.657555] mmc1: new high speed SDHC card at address aaaa >> [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.669206] mmcblk0: p1 p2 >> >> On cold boot:: ie: power on the board. >> >> [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >> req 100000000Hz, actual 100000000HZ div = 0) >> [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.650293] IRQ56 no longer affine to CPU7 >> [ 4.650581] CPU7: shutdown >> [ 4.658293] mmcblk0: p1 p2 >> >> Note: Their is need to reset the PMIC >> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers >> to support this feature consistently on every reboot. > > I don't understand...why needs to reset? > I know it needs to switch the voltage, doesn't it? > I was referring to this code. https://github.com/hardkernel/linux/blob/odroidxu3-3.10.y/drivers/regulator/s2mps11.c#L451 I am not sure if this need to fixed in u-boot of hardkernel or shutdown function. -Anand Moon > Best Regards, > Jaehoon Chung > >> >> -Anand Moon >> > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
W dniu 12.10.2015 o 19:46, Anand Moon pisze: > Hi Krzysztof, > > On 12 October 2015 at 11:14, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> On 12.10.2015 00:46, Anand Moon wrote: >>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >> >> This description is not entirely correct. The MMC driver already >> supports these UHS speeds (you did not any code) so you rather enabled >> it (description of bindings says "is supported"). >> >> You mentioned DDR50 but I don't see respective property below. > Looks like I missed it, I will add this in the next patch, >> >> How do you know that these modes are really supported? I don't know. Can >> you convince me? That part was not answered... >> > >>> >>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>> >>> --- >>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>> >>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >> >> I don't get what is exactly fixed here. What was the error? What is the >> outcome of this fix? The log below is before or after? >> >> Best regards, >> Krzysztof >> >>> >>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>> [ 2.461743] mmcblk0: p1 p2 >> >>> --- >>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> index 58c06d3..ba4a87b 100644 >>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> @@ -364,6 +364,10 @@ >>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>> bus-width = <4>; >>> cap-sd-highspeed; >>> + sd-uhs-sdr12; >>> + sd-uhs-sdr25; >>> + sd-uhs-sdr50; >>> + sd-uhs-sdr104; >>> }; >>> >>> &pinctrl_0 { >>> >> > > Changes were made to support Sandisk Ultra UHS-I class 10 card support. > OdroidXU3/XU4 board would not boot up using this card. > > Depending on the capability of the UHS-I card, the speed of the card > is selected. > I have just added the enhance capability feature to support them. So without these capabilities mentioned microSD card cannot be used? So I have a UHS-I card, that one exactly: http://www.samsung.com/us/support/owners/product/MB-MP32D/APC It works: [ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.693296] mmc1: new high speed SDHC card at address 0001 [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB [ 2.708406] mmcblk0: p1 p2 This is just HS mode. In the same time isn't UHS-I backward compatible? Your report seems surprising. Best regards, Krzysztof > > On warm boot: i.e reboot of the board. > [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > req 50000000Hz, actual 50000000HZ div = 0) > [ 4.657555] mmc1: new high speed SDHC card at address aaaa > [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 4.669206] mmcblk0: p1 p2 > > On cold boot:: ie: power on the board. > > [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot > req 100000000Hz, actual 100000000HZ div = 0) > [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa > [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 4.650293] IRQ56 no longer affine to CPU7 > [ 4.650581] CPU7: shutdown > [ 4.658293] mmcblk0: p1 p2 > > Note: Their is need to reset the PMIC > S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers > to support this feature consistently on every reboot. > > -Anand Moon > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote: > W dniu 12.10.2015 o 19:46, Anand Moon pisze: >> Hi Krzysztof, >> >> On 12 October 2015 at 11:14, Krzysztof Kozlowski >> <k.kozlowski@samsung.com> wrote: >>> On 12.10.2015 00:46, Anand Moon wrote: >>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>> >>> This description is not entirely correct. The MMC driver already >>> supports these UHS speeds (you did not any code) so you rather enabled >>> it (description of bindings says "is supported"). >>> >>> You mentioned DDR50 but I don't see respective property below. >> Looks like I missed it, I will add this in the next patch, >>> >>> How do you know that these modes are really supported? I don't know. Can >>> you convince me? > > That part was not answered... In my experiment, it needs two requirements. One is that Host controller supported UHS-I mode or others, other is SD-card. In Anand's commit message, there is no information for this. And 50MB/s or 104MB/s is not real performance. (Just theoretical values) It seems that can get those performances. > >>> >> >>>> >>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>>> >>>> --- >>>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>>> >>>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >>> >>> I don't get what is exactly fixed here. What was the error? What is the >>> outcome of this fix? The log below is before or after? >>> >>> Best regards, >>> Krzysztof >>> >>>> >>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 2.461743] mmcblk0: p1 p2 >>> >>>> --- >>>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>> index 58c06d3..ba4a87b 100644 >>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>> @@ -364,6 +364,10 @@ >>>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>>> bus-width = <4>; >>>> cap-sd-highspeed; >>>> + sd-uhs-sdr12; >>>> + sd-uhs-sdr25; >>>> + sd-uhs-sdr50; >>>> + sd-uhs-sdr104; >>>> }; >>>> >>>> &pinctrl_0 { >>>> >>> >> >> Changes were made to support Sandisk Ultra UHS-I class 10 card support. >> OdroidXU3/XU4 board would not boot up using this card. >> >> Depending on the capability of the UHS-I card, the speed of the card >> is selected. >> I have just added the enhance capability feature to support them. > > So without these capabilities mentioned microSD card cannot be used? So > I have a UHS-I card, that one exactly: > http://www.samsung.com/us/support/owners/product/MB-MP32D/APC > > It works: > [ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req > 50000000Hz, actual 50000000HZ div = 0) > [ 2.693296] mmc1: new high speed SDHC card at address 0001 > [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB > [ 2.708406] mmcblk0: p1 p2 > > This is just HS mode. > > In the same time isn't UHS-I backward compatible? Your report seems > surprising. Right. it's not issue. just working as lower mode than its capability. Best Regards, Jaehoon Chung > > Best regards, > Krzysztof > >> >> On warm boot: i.e reboot of the board. >> [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.657555] mmc1: new high speed SDHC card at address aaaa >> [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.669206] mmcblk0: p1 p2 >> >> On cold boot:: ie: power on the board. >> >> [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >> req 100000000Hz, actual 100000000HZ div = 0) >> [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.650293] IRQ56 no longer affine to CPU7 >> [ 4.650581] CPU7: shutdown >> [ 4.658293] mmcblk0: p1 p2 >> >> Note: Their is need to reset the PMIC >> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers >> to support this feature consistently on every reboot. >> >> -Anand Moon >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html >> Please read the FAQ at http://www.tux.org/lkml/ >> > > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze: > On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote: >> W dniu 12.10.2015 o 19:46, Anand Moon pisze: >>> Hi Krzysztof, >>> >>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>> <k.kozlowski@samsung.com> wrote: >>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>> >>>> This description is not entirely correct. The MMC driver already >>>> supports these UHS speeds (you did not any code) so you rather enabled >>>> it (description of bindings says "is supported"). >>>> >>>> You mentioned DDR50 but I don't see respective property below. >>> Looks like I missed it, I will add this in the next patch, >>>> >>>> How do you know that these modes are really supported? I don't know. Can >>>> you convince me? >> >> That part was not answered... > > In my experiment, it needs two requirements. > One is that Host controller supported UHS-I mode or others, other is SD-card. > In Anand's commit message, there is no information for this. > > And 50MB/s or 104MB/s is not real performance. (Just theoretical values) > It seems that can get those performances. Right. But do you know if the host actually supports these? > >> >>>> >>> >>>>> >>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>>>> >>>>> --- >>>>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>>>> >>>>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >>>> >>>> I don't get what is exactly fixed here. What was the error? What is the >>>> outcome of this fix? The log below is before or after? >>>> >>>> Best regards, >>>> Krzysztof >>>> >>>>> >>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>> [ 2.461743] mmcblk0: p1 p2 >>>> >>>>> --- >>>>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>>>> 1 file changed, 4 insertions(+) >>>>> >>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>> index 58c06d3..ba4a87b 100644 >>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>> @@ -364,6 +364,10 @@ >>>>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>>>> bus-width = <4>; >>>>> cap-sd-highspeed; >>>>> + sd-uhs-sdr12; >>>>> + sd-uhs-sdr25; >>>>> + sd-uhs-sdr50; >>>>> + sd-uhs-sdr104; >>>>> }; >>>>> >>>>> &pinctrl_0 { >>>>> >>>> >>> >>> Changes were made to support Sandisk Ultra UHS-I class 10 card support. >>> OdroidXU3/XU4 board would not boot up using this card. >>> >>> Depending on the capability of the UHS-I card, the speed of the card >>> is selected. >>> I have just added the enhance capability feature to support them. >> >> So without these capabilities mentioned microSD card cannot be used? So >> I have a UHS-I card, that one exactly: >> http://www.samsung.com/us/support/owners/product/MB-MP32D/APC >> >> It works: >> [ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req >> 50000000Hz, actual 50000000HZ div = 0) >> [ 2.693296] mmc1: new high speed SDHC card at address 0001 >> [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB >> [ 2.708406] mmcblk0: p1 p2 >> >> This is just HS mode. >> >> In the same time isn't UHS-I backward compatible? Your report seems >> surprising. > > Right. it's not issue. just working as lower mode than its capability. Anand's report mentions "board would not boot up" which seems quite drastic. :) Thanks Jaehoon for help in reviewing this patch. Dear Anand, Could you describe in more details observable issues, what is fixed or what feature is added? Best regards, Krzysztof > > Best Regards, > Jaehoon Chung > >> >> Best regards, >> Krzysztof >> >>> >>> On warm boot: i.e reboot of the board. >>> [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>> req 50000000Hz, actual 50000000HZ div = 0) >>> [ 4.657555] mmc1: new high speed SDHC card at address aaaa >>> [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>> [ 4.669206] mmcblk0: p1 p2 >>> >>> On cold boot:: ie: power on the board. >>> >>> [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >>> req 100000000Hz, actual 100000000HZ div = 0) >>> [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>> [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>> [ 4.650293] IRQ56 no longer affine to CPU7 >>> [ 4.650581] CPU7: shutdown >>> [ 4.658293] mmcblk0: p1 p2 >>> >>> Note: Their is need to reset the PMIC >>> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers >>> to support this feature consistently on every reboot. >>> >>> -Anand Moon >>> -- >>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >>> the body of a message to majordomo@vger.kernel.org >>> More majordomo info at http://vger.kernel.org/majordomo-info.html >>> Please read the FAQ at http://www.tux.org/lkml/ >>> >> >> > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Krzysztof, On 12 October 2015 at 11:14, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 12.10.2015 00:46, Anand Moon wrote: >> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) > > This description is not entirely correct. The MMC driver already > supports these UHS speeds (you did not any code) so you rather enabled > it (description of bindings says "is supported"). > > You mentioned DDR50 but I don't see respective property below. > > How do you know that these modes are really supported? I don't know. Can > you convince me? Setting this DDR50 capability give me this error. That's the reason to drop this capability. Sep 24 09:37:04 odroidxu4 kernel: [ 4.138418] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) Sep 24 09:37:04 odroidxu4 kernel: [ 4.138546] mmc1: new ultra high speed DDR50 SDHC card at address aaaa Sep 24 09:37:04 odroidxu4 kernel: [ 4.141585] mmcblk0: mmc1:aaaa SL32G 29.7 GiB Sep 24 09:37:04 odroidxu4 kernel: [ 4.146477] mmcblk0: error -110 sending status command, retrying Sep 24 09:37:04 odroidxu4 kernel: [ 4.146577] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 Sep 24 09:37:04 odroidxu4 kernel: [ 4.146581] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 >> >> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >> >> --- >> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >> >> Changes Fixed the UHS-I bus speed detedtion on cold boot. > > I don't get what is exactly fixed here. What was the error? What is the > outcome of this fix? The log below is before or after? > > Best regards, > Krzysztof > >> >> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 2.461743] mmcblk0: p1 p2 > >> --- >> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> index 58c06d3..ba4a87b 100644 >> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> @@ -364,6 +364,10 @@ >> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >> bus-width = <4>; >> cap-sd-highspeed; >> + sd-uhs-sdr12; >> + sd-uhs-sdr25; >> + sd-uhs-sdr50; >> + sd-uhs-sdr104; >> }; >> >> &pinctrl_0 { >> > -Anand Moon -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 13.10.2015 00:32, Anand Moon wrote: > Hi Krzysztof, > > On 12 October 2015 at 11:14, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> On 12.10.2015 00:46, Anand Moon wrote: >>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >> >> This description is not entirely correct. The MMC driver already >> supports these UHS speeds (you did not any code) so you rather enabled >> it (description of bindings says "is supported"). >> >> You mentioned DDR50 but I don't see respective property below. >> >> How do you know that these modes are really supported? I don't know. Can >> you convince me? > > Setting this DDR50 capability give me this error. That's the reason to > drop this capability. But you mentioned it in commit message! "Added support for UHS-I ... (DDR50)" In the same time dropping DDR50 is not an sufficient proof that "SDR50 and SDR104 are really supported". Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/12/2015 10:16 PM, Krzysztof Kozlowski wrote: > W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze: >> On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote: >>> W dniu 12.10.2015 o 19:46, Anand Moon pisze: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> <k.kozlowski@samsung.com> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>> Looks like I missed it, I will add this in the next patch, >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>> >>> That part was not answered... >> >> In my experiment, it needs two requirements. >> One is that Host controller supported UHS-I mode or others, other is SD-card. >> In Anand's commit message, there is no information for this. >> >> And 50MB/s or 104MB/s is not real performance. (Just theoretical values) >> It seems that can get those performances. > > Right. But do you know if the host actually supports these? Actually, it needs to check the User Manual for SoC. If i can't check the User manual, i can't also know whether it supports or not. Especially, there is no register that can be known which SD specification version at dw-mmc controller. Well, if i miss something, let me know. I will also check more. Best Regards, Jaehoon Chung > >> >>> >>>>> >>>> >>>>>> >>>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>>>>> >>>>>> --- >>>>>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>>>>> >>>>>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >>>>> >>>>> I don't get what is exactly fixed here. What was the error? What is the >>>>> outcome of this fix? The log below is before or after? >>>>> >>>>> Best regards, >>>>> Krzysztof >>>>> >>>>>> >>>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>>> [ 2.461743] mmcblk0: p1 p2 >>>>> >>>>>> --- >>>>>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>>>>> 1 file changed, 4 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> index 58c06d3..ba4a87b 100644 >>>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> @@ -364,6 +364,10 @@ >>>>>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>>>>> bus-width = <4>; >>>>>> cap-sd-highspeed; >>>>>> + sd-uhs-sdr12; >>>>>> + sd-uhs-sdr25; >>>>>> + sd-uhs-sdr50; >>>>>> + sd-uhs-sdr104; >>>>>> }; >>>>>> >>>>>> &pinctrl_0 { >>>>>> >>>>> >>>> >>>> Changes were made to support Sandisk Ultra UHS-I class 10 card support. >>>> OdroidXU3/XU4 board would not boot up using this card. >>>> >>>> Depending on the capability of the UHS-I card, the speed of the card >>>> is selected. >>>> I have just added the enhance capability feature to support them. >>> >>> So without these capabilities mentioned microSD card cannot be used? So >>> I have a UHS-I card, that one exactly: >>> http://www.samsung.com/us/support/owners/product/MB-MP32D/APC >>> >>> It works: >>> [ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req >>> 50000000Hz, actual 50000000HZ div = 0) >>> [ 2.693296] mmc1: new high speed SDHC card at address 0001 >>> [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB >>> [ 2.708406] mmcblk0: p1 p2 >>> >>> This is just HS mode. >>> >>> In the same time isn't UHS-I backward compatible? Your report seems >>> surprising. >> >> Right. it's not issue. just working as lower mode than its capability. > > Anand's report mentions "board would not boot up" which seems quite > drastic. :) > > Thanks Jaehoon for help in reviewing this patch. > > > Dear Anand, > > Could you describe in more details observable issues, what is fixed or > what feature is added? > > Best regards, > Krzysztof > >> >> Best Regards, >> Jaehoon Chung >> >>> >>> Best regards, >>> Krzysztof >>> >>>> >>>> On warm boot: i.e reboot of the board. >>>> [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.657555] mmc1: new high speed SDHC card at address aaaa >>>> [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.669206] mmcblk0: p1 p2 >>>> >>>> On cold boot:: ie: power on the board. >>>> >>>> [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >>>> req 100000000Hz, actual 100000000HZ div = 0) >>>> [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.650293] IRQ56 no longer affine to CPU7 >>>> [ 4.650581] CPU7: shutdown >>>> [ 4.658293] mmcblk0: p1 p2 >>>> >>>> Note: Their is need to reset the PMIC >>>> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers >>>> to support this feature consistently on every reboot. >>>> >>>> -Anand Moon >>>> -- >>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >>>> the body of a message to majordomo@vger.kernel.org >>>> More majordomo info at http://vger.kernel.org/majordomo-info.html >>>> Please read the FAQ at http://www.tux.org/lkml/ >>>> >>> >>> >> > > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Krzysztof, On 13 October 2015 at 05:44, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 13.10.2015 00:32, Anand Moon wrote: >> Hi Krzysztof, >> >> On 12 October 2015 at 11:14, Krzysztof Kozlowski >> <k.kozlowski@samsung.com> wrote: >>> On 12.10.2015 00:46, Anand Moon wrote: >>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>> >>> This description is not entirely correct. The MMC driver already >>> supports these UHS speeds (you did not any code) so you rather enabled >>> it (description of bindings says "is supported"). >>> >>> You mentioned DDR50 but I don't see respective property below. >>> >>> How do you know that these modes are really supported? I don't know. Can >>> you convince me? >> >> Setting this DDR50 capability give me this error. That's the reason to >> drop this capability. > > But you mentioned it in commit message! "Added support for UHS-I ... > (DDR50)" > > In the same time dropping DDR50 is not an sufficient proof that "SDR50 > and SDR104 are really supported". > These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card. When the card select the capability for DDR50 --------------------------------------------------- [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 4.009179] mmcblk0: error -110 sending status command, retrying [ 4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) [ 4.067770] Console: switching to colour frame buffer device 274x77 [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 4.099692] mmc1: tried to reset card [ 4.101332] mmcblk0: p1 p2 When the card select the capability for SDR50 --------------------------------------------------------------------------------- [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2 Which will relate to better read/write speed. -Anand Moon > Best regards, > Krzysztof > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 13.10.2015 12:08, Anand Moon wrote: > Hi Krzysztof, > > On 13 October 2015 at 05:44, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> On 13.10.2015 00:32, Anand Moon wrote: >>> Hi Krzysztof, >>> >>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>> <k.kozlowski@samsung.com> wrote: >>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>> >>>> This description is not entirely correct. The MMC driver already >>>> supports these UHS speeds (you did not any code) so you rather enabled >>>> it (description of bindings says "is supported"). >>>> >>>> You mentioned DDR50 but I don't see respective property below. >>>> >>>> How do you know that these modes are really supported? I don't know. Can >>>> you convince me? >>> >>> Setting this DDR50 capability give me this error. That's the reason to >>> drop this capability. >> >> But you mentioned it in commit message! "Added support for UHS-I ... >> (DDR50)" >> >> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >> and SDR104 are really supported". >> > > These changes are related to the microSD card capabilities. > So SDR50 have better frequency over DDR50. On the same Sandisk card. > > When the card select the capability for DDR50 > --------------------------------------------------- > [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > req 50000000Hz, actual 50000000HZ div = 0) > [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa > [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 4.009179] mmcblk0: error -110 sending status command, retrying > [ 4.009271] mmcblk0: error -115 sending stop command, original cmd > response 0x900, card status 0x900 > [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, > cmd response 0x900, card status 0x0 > [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > req 400000Hz, actual 396825HZ div = 63) > [ 4.067770] Console: switching to colour frame buffer device 274x77 > [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > req 50000000Hz, actual 50000000HZ div = 0) > [ 4.099692] mmc1: tried to reset card > [ 4.101332] mmcblk0: p1 p2 > > > When the card select the capability for SDR50 > --------------------------------------------------------------------------------- > [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req > 100000000Hz, actual 100000000HZ div = 0) > [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa > [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 2.461743] mmcblk0: p1 p2 > > Which will relate to better read/write speed. Which is not an answer to my question. To none of my previous questions. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Krzysztof, On 13 October 2015 at 09:13, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 13.10.2015 12:08, Anand Moon wrote: >> Hi Krzysztof, >> >> On 13 October 2015 at 05:44, Krzysztof Kozlowski >> <k.kozlowski@samsung.com> wrote: >>> On 13.10.2015 00:32, Anand Moon wrote: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> <k.kozlowski@samsung.com> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>>> >>>> Setting this DDR50 capability give me this error. That's the reason to >>>> drop this capability. >>> >>> But you mentioned it in commit message! "Added support for UHS-I ... >>> (DDR50)" >>> >>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>> and SDR104 are really supported". >>> >> >> These changes are related to the microSD card capabilities. >> So SDR50 have better frequency over DDR50. On the same Sandisk card. >> >> When the card select the capability for DDR50 >> --------------------------------------------------- >> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.009179] mmcblk0: error -110 sending status command, retrying >> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >> response 0x900, card status 0x900 >> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >> cmd response 0x900, card status 0x0 >> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 400000Hz, actual 396825HZ div = 63) >> [ 4.067770] Console: switching to colour frame buffer device 274x77 >> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.099692] mmc1: tried to reset card >> [ 4.101332] mmcblk0: p1 p2 >> >> >> When the card select the capability for SDR50 >> --------------------------------------------------------------------------------- >> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >> 100000000Hz, actual 100000000HZ div = 0) >> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 2.461743] mmcblk0: p1 p2 >> >> Which will relate to better read/write speed. > > Which is not an answer to my question. To none of my previous questions. OK, you are correct.Just ignore these changes. -Anand Moon > > Best regards, > Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Krzysztof, On 13 October 2015 at 09:13, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > > On 13.10.2015 12:08, Anand Moon wrote: > > Hi Krzysztof, > > > > On 13 October 2015 at 05:44, Krzysztof Kozlowski > > <k.kozlowski@samsung.com> wrote: > >> On 13.10.2015 00:32, Anand Moon wrote: > >>> Hi Krzysztof, > >>> > >>> On 12 October 2015 at 11:14, Krzysztof Kozlowski > >>> <k.kozlowski@samsung.com> wrote: > >>>> On 12.10.2015 00:46, Anand Moon wrote: > >>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) > >>>> > >>>> This description is not entirely correct. The MMC driver already > >>>> supports these UHS speeds (you did not any code) so you rather enabled > >>>> it (description of bindings says "is supported"). > >>>> > >>>> You mentioned DDR50 but I don't see respective property below. > >>>> > >>>> How do you know that these modes are really supported? I don't know. Can > >>>> you convince me? > >>> > >>> Setting this DDR50 capability give me this error. That's the reason to > >>> drop this capability. > >> > >> But you mentioned it in commit message! "Added support for UHS-I ... > >> (DDR50)" > >> > >> In the same time dropping DDR50 is not an sufficient proof that "SDR50 > >> and SDR104 are really supported". > >> > > > > These changes are related to the microSD card capabilities. > > So SDR50 have better frequency over DDR50. On the same Sandisk card. > > > > When the card select the capability for DDR50 > > --------------------------------------------------- > > [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > > req 50000000Hz, actual 50000000HZ div = 0) > > [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa > > [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > > [ 4.009179] mmcblk0: error -110 sending status command, retrying > > [ 4.009271] mmcblk0: error -115 sending stop command, original cmd > > response 0x900, card status 0x900 > > [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, > > cmd response 0x900, card status 0x0 > > [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > > req 400000Hz, actual 396825HZ div = 63) > > [ 4.067770] Console: switching to colour frame buffer device 274x77 > > [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > > req 50000000Hz, actual 50000000HZ div = 0) > > [ 4.099692] mmc1: tried to reset card > > [ 4.101332] mmcblk0: p1 p2 > > > > > > When the card select the capability for SDR50 > > --------------------------------------------------------------------------------- > > [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req > > 100000000Hz, actual 100000000HZ div = 0) > > [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa > > [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > > [ 2.461743] mmcblk0: p1 p2 > > > > Which will relate to better read/write speed. > > Which is not an answer to my question. To none of my previous questions. > Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, sd-uhs-sdr104) help tune speed supported for mmc I have tired to compare the speed on high speed UHS-I vs ultra high speed UHS-I using izone utility. [ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) [ 2.572609] mmc1: new high speed SDHC card at address aaaa Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls Output is in kBytes/sec Time Resolution = 0.000001 seconds. Processor cache size set to 32 kBytes. Processor cache line size set to 64 bytes. File stride size set to 17 * record size. random random bkwd record stride kB reclen write rewrite read reread read write read rewrite read fwrite frewrite fread freread 10240 4 1631 0 6556 0 5538 982 10240 64 8828 0 18897 0 17994 303 10240 128 6269 0 20670 0 20128 1096 --------------------------------------------------------------------------------------------------------- [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaa Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls Output is in kBytes/sec Time Resolution = 0.000001 seconds. Processor cache size set to 32 kBytes. Processor cache line size set to 64 bytes. File stride size set to 17 * record size. random random bkwd record stride kB reclen write rewrite read reread read write read rewrite read fwrite frewrite fread freread 10240 4 1809 0 7507 0 5233 859 10240 64 11622 0 31250 0 28072 516 10240 128 4320 0 34417 0 32509 1148 My observation is that their slight increase in read/write operation. Hope I have tried to answer you query. If I am wrong please let me know. -Anand Moon > > Best regards, > Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 14.10.2015 01:27, Anand Moon wrote: > Hi Krzysztof, > > On 13 October 2015 at 09:13, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> >> On 13.10.2015 12:08, Anand Moon wrote: >>> Hi Krzysztof, >>> >>> On 13 October 2015 at 05:44, Krzysztof Kozlowski >>> <k.kozlowski@samsung.com> wrote: >>>> On 13.10.2015 00:32, Anand Moon wrote: >>>>> Hi Krzysztof, >>>>> >>>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>>> <k.kozlowski@samsung.com> wrote: >>>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>>> >>>>>> This description is not entirely correct. The MMC driver already >>>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>>> it (description of bindings says "is supported"). >>>>>> >>>>>> You mentioned DDR50 but I don't see respective property below. >>>>>> >>>>>> How do you know that these modes are really supported? I don't know. Can >>>>>> you convince me? >>>>> >>>>> Setting this DDR50 capability give me this error. That's the reason to >>>>> drop this capability. >>>> >>>> But you mentioned it in commit message! "Added support for UHS-I ... >>>> (DDR50)" >>>> >>>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>>> and SDR104 are really supported". >>>> >>> >>> These changes are related to the microSD card capabilities. >>> So SDR50 have better frequency over DDR50. On the same Sandisk card. >>> >>> When the card select the capability for DDR50 >>> --------------------------------------------------- >>> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>> req 50000000Hz, actual 50000000HZ div = 0) >>> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >>> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>> [ 4.009179] mmcblk0: error -110 sending status command, retrying >>> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >>> response 0x900, card status 0x900 >>> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >>> cmd response 0x900, card status 0x0 >>> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>> req 400000Hz, actual 396825HZ div = 63) >>> [ 4.067770] Console: switching to colour frame buffer device 274x77 >>> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>> req 50000000Hz, actual 50000000HZ div = 0) >>> [ 4.099692] mmc1: tried to reset card >>> [ 4.101332] mmcblk0: p1 p2 >>> >>> >>> When the card select the capability for SDR50 >>> --------------------------------------------------------------------------------- >>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >>> 100000000Hz, actual 100000000HZ div = 0) >>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>> [ 2.461743] mmcblk0: p1 p2 >>> >>> Which will relate to better read/write speed. >> >> Which is not an answer to my question. To none of my previous questions. >> > > Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, > sd-uhs-sdr104) help tune speed supported for mmc > > I have tired to compare the speed on high speed UHS-I vs ultra high > speed UHS-I using izone utility. > > [ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > req 50000000Hz, actual 50000000HZ div = 0) > [ 2.572609] mmc1: new high speed SDHC card at address aaaa > > Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k > -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls > Output is in kBytes/sec > Time Resolution = 0.000001 seconds. > Processor cache size set to 32 kBytes. > Processor cache line size set to 64 bytes. > File stride size set to 17 * record size. > random > random bkwd record stride > kB reclen write rewrite read reread read > write read rewrite read fwrite frewrite fread > freread > 10240 4 1631 0 6556 0 5538 982 > 10240 64 8828 0 18897 0 17994 303 > 10240 128 6269 0 20670 0 20128 1096 > --------------------------------------------------------------------------------------------------------- > [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot > req 100000000Hz, actual 100000000HZ div = 0) > [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaa > > Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k > -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls > Output is in kBytes/sec > Time Resolution = 0.000001 seconds. > Processor cache size set to 32 kBytes. > Processor cache line size set to 64 bytes. > File stride size set to 17 * record size. > random > random bkwd record stride > kB reclen write rewrite read reread read > write read rewrite read fwrite frewrite fread > freread > 10240 4 1809 0 7507 0 5233 859 > 10240 64 11622 0 31250 0 28072 516 > 10240 128 4320 0 34417 0 32509 1148 > > My observation is that their slight increase in read/write operation. > > Hope I have tried to answer you query. If I am wrong please let me know. Nope, that did not answer my query. You gave some performance benchmarks but my question was not about the speed of anything. The question is (once again): How do you know that these modes are really supported? You are marking the *host* as supporting these modes. Please provide information that host supports them *really*, not by experimenting "oh, it seems to work now, maybe it will work always". Usually vendors, if their products implement some kind of specification/protocol, they mark the products as "compatible with XYZ" etc. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
+Doug Hello, AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 and SDR104 modes. [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this. Have not checked it recently, so not sure if this got broken somehow. Regards, Alim On Wed, Oct 14, 2015 at 5:29 AM, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 14.10.2015 01:27, Anand Moon wrote: >> Hi Krzysztof, >> >> On 13 October 2015 at 09:13, Krzysztof Kozlowski >> <k.kozlowski@samsung.com> wrote: >>> >>> On 13.10.2015 12:08, Anand Moon wrote: >>>> Hi Krzysztof, >>>> >>>> On 13 October 2015 at 05:44, Krzysztof Kozlowski >>>> <k.kozlowski@samsung.com> wrote: >>>>> On 13.10.2015 00:32, Anand Moon wrote: >>>>>> Hi Krzysztof, >>>>>> >>>>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>>>> <k.kozlowski@samsung.com> wrote: >>>>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>>>> >>>>>>> This description is not entirely correct. The MMC driver already >>>>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>>>> it (description of bindings says "is supported"). >>>>>>> >>>>>>> You mentioned DDR50 but I don't see respective property below. >>>>>>> >>>>>>> How do you know that these modes are really supported? I don't know. Can >>>>>>> you convince me? >>>>>> >>>>>> Setting this DDR50 capability give me this error. That's the reason to >>>>>> drop this capability. >>>>> >>>>> But you mentioned it in commit message! "Added support for UHS-I ... >>>>> (DDR50)" >>>>> >>>>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>>>> and SDR104 are really supported". >>>>> >>>> >>>> These changes are related to the microSD card capabilities. >>>> So SDR50 have better frequency over DDR50. On the same Sandisk card. >>>> >>>> When the card select the capability for DDR50 >>>> --------------------------------------------------- >>>> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >>>> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.009179] mmcblk0: error -110 sending status command, retrying >>>> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >>>> response 0x900, card status 0x900 >>>> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >>>> cmd response 0x900, card status 0x0 >>>> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 400000Hz, actual 396825HZ div = 63) >>>> [ 4.067770] Console: switching to colour frame buffer device 274x77 >>>> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.099692] mmc1: tried to reset card >>>> [ 4.101332] mmcblk0: p1 p2 >>>> >>>> >>>> When the card select the capability for SDR50 >>>> --------------------------------------------------------------------------------- >>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >>>> 100000000Hz, actual 100000000HZ div = 0) >>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 2.461743] mmcblk0: p1 p2 >>>> >>>> Which will relate to better read/write speed. >>> >>> Which is not an answer to my question. To none of my previous questions. >>> >> >> Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, >> sd-uhs-sdr104) help tune speed supported for mmc >> >> I have tired to compare the speed on high speed UHS-I vs ultra high >> speed UHS-I using izone utility. >> >> [ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 2.572609] mmc1: new high speed SDHC card at address aaaa >> >> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >> Output is in kBytes/sec >> Time Resolution = 0.000001 seconds. >> Processor cache size set to 32 kBytes. >> Processor cache line size set to 64 bytes. >> File stride size set to 17 * record size. >> random >> random bkwd record stride >> kB reclen write rewrite read reread read >> write read rewrite read fwrite frewrite fread >> freread >> 10240 4 1631 0 6556 0 5538 982 >> 10240 64 8828 0 18897 0 17994 303 >> 10240 128 6269 0 20670 0 20128 1096 >> --------------------------------------------------------------------------------------------------------- >> [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >> req 100000000Hz, actual 100000000HZ div = 0) >> [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> >> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >> Output is in kBytes/sec >> Time Resolution = 0.000001 seconds. >> Processor cache size set to 32 kBytes. >> Processor cache line size set to 64 bytes. >> File stride size set to 17 * record size. >> random >> random bkwd record stride >> kB reclen write rewrite read reread read >> write read rewrite read fwrite frewrite fread >> freread >> 10240 4 1809 0 7507 0 5233 859 >> 10240 64 11622 0 31250 0 28072 516 >> 10240 128 4320 0 34417 0 32509 1148 >> >> My observation is that their slight increase in read/write operation. >> >> Hope I have tried to answer you query. If I am wrong please let me know. > > Nope, that did not answer my query. You gave some performance benchmarks > but my question was not about the speed of anything. The question is > (once again): > How do you know that these modes are really supported? > > You are marking the *host* as supporting these modes. Please provide > information that host supports them *really*, not by experimenting "oh, > it seems to work now, maybe it will work always". > > Usually vendors, if their products implement some kind of > specification/protocol, they mark the products as "compatible with XYZ" etc. > > Best regards, > Krzysztof > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
On 14.10.2015 10:06, Alim Akhtar wrote: > +Doug > Hello, > AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 > and SDR104 modes. > > [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html > > What I remember is, one need to set "broken-cd" property also in order > to make it work because of the vqmmc and vmmc connection on board. I > didn't find the link right now, but you can search on the web, there > was a long discussion about handling this. > Have not checked it recently, so not sure if this got broken somehow. > Please, don't top post. I am not a SD/MMC specialist (I do not feel enough confident in its internals) but the datasheet for 5422 does not mention UHS. However it mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This does not look like UHS... https://www.sdcard.org/developers/overview/bus_speed/ This of course is not a definite proof that 5422 does not support UHS. I am just saying that I couldn't find any information that *it does*. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/14/2015 10:15 AM, Krzysztof Kozlowski wrote: > On 14.10.2015 10:06, Alim Akhtar wrote: >> +Doug >> Hello, >> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >> and SDR104 modes. >> >> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >> >> What I remember is, one need to set "broken-cd" property also in order >> to make it work because of the vqmmc and vmmc connection on board. I >> didn't find the link right now, but you can search on the web, there >> was a long discussion about handling this. >> Have not checked it recently, so not sure if this got broken somehow. >> > > Please, don't top post. > > I am not a SD/MMC specialist (I do not feel enough confident in its > internals) but the datasheet for 5422 does not mention UHS. However it > mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This > does not look like UHS... You're right. It's not UHS mode. it mentions eMMC's HS400 mode. UHS and HS400 are difference mode. eMMC mode are supported > https://www.sdcard.org/developers/overview/bus_speed/ > This of course is not a definite proof that 5422 does not support UHS. I > am just saying that I couldn't find any information that *it does*. Well, I think you want to know whether it supported or not. Then you can find the information at User manual. In mobile storage part of User manual, it described the overview. Mobile storage host supports these specification: - Secure Digital memory (SD memory version 3.0) - Secure Digital I/O SDIO (SDIO version 3.0) - etc... SD3.0 is supported UHS-I mode. If user manual of exynos5422 is mentioned this specification, it should be supported UHS-I mode. If my understanding is wrong, let me know, plz. Best Regards, Jaehoon Chung > > Best regards, > Krzysztof > > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 14.10.2015 10:40, Jaehoon Chung wrote: > On 10/14/2015 10:15 AM, Krzysztof Kozlowski wrote: >> On 14.10.2015 10:06, Alim Akhtar wrote: >>> +Doug >>> Hello, >>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >>> and SDR104 modes. >>> >>> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >>> >>> What I remember is, one need to set "broken-cd" property also in order >>> to make it work because of the vqmmc and vmmc connection on board. I >>> didn't find the link right now, but you can search on the web, there >>> was a long discussion about handling this. >>> Have not checked it recently, so not sure if this got broken somehow. >>> >> >> Please, don't top post. >> >> I am not a SD/MMC specialist (I do not feel enough confident in its >> internals) but the datasheet for 5422 does not mention UHS. However it >> mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This >> does not look like UHS... > > You're right. It's not UHS mode. it mentions eMMC's HS400 mode. > UHS and HS400 are difference mode. > > eMMC mode are supported > >> https://www.sdcard.org/developers/overview/bus_speed/ >> This of course is not a definite proof that 5422 does not support UHS. I >> am just saying that I couldn't find any information that *it does*. > > Well, I think you want to know whether it supported or not. > Then you can find the information at User manual. > In mobile storage part of User manual, it described the overview. > Mobile storage host supports these specification: > - Secure Digital memory (SD memory version 3.0) > - Secure Digital I/O SDIO (SDIO version 3.0) > - etc... > > SD3.0 is supported UHS-I mode. > If user manual of exynos5422 is mentioned this specification, it should be supported UHS-I mode. Thanks! Indeed datasheet mentions that supported SD and SDIO is version 3.0 (not 3.01... which seems irrelevant because 3.0 introduced UHS-I, right?). Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Oct 14, 2015 at 7:22 AM, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 14.10.2015 10:40, Jaehoon Chung wrote: >> On 10/14/2015 10:15 AM, Krzysztof Kozlowski wrote: >>> On 14.10.2015 10:06, Alim Akhtar wrote: >>>> +Doug >>>> Hello, >>>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >>>> and SDR104 modes. >>>> >>>> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >>>> >>>> What I remember is, one need to set "broken-cd" property also in order >>>> to make it work because of the vqmmc and vmmc connection on board. I >>>> didn't find the link right now, but you can search on the web, there >>>> was a long discussion about handling this. >>>> Have not checked it recently, so not sure if this got broken somehow. >>>> >>> >>> Please, don't top post. >>> >>> I am not a SD/MMC specialist (I do not feel enough confident in its >>> internals) but the datasheet for 5422 does not mention UHS. However it >>> mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This >>> does not look like UHS... >> >> You're right. It's not UHS mode. it mentions eMMC's HS400 mode. >> UHS and HS400 are difference mode. >> >> eMMC mode are supported >> >>> https://www.sdcard.org/developers/overview/bus_speed/ >>> This of course is not a definite proof that 5422 does not support UHS. I >>> am just saying that I couldn't find any information that *it does*. >> >> Well, I think you want to know whether it supported or not. >> Then you can find the information at User manual. >> In mobile storage part of User manual, it described the overview. >> Mobile storage host supports these specification: >> - Secure Digital memory (SD memory version 3.0) >> - Secure Digital I/O SDIO (SDIO version 3.0) >> - etc... >> >> SD3.0 is supported UHS-I mode. >> If user manual of exynos5422 is mentioned this specification, it should be supported UHS-I mode. > > Thanks! Indeed datasheet mentions that supported SD and SDIO is version > 3.0 (not 3.01... which seems irrelevant because 3.0 introduced UHS-I, > right?). > Yes, your understanding is right. SD3.0 does includes UHS-I. > Best regards, > Krzysztof
On Wed, Oct 14, 2015 at 6:45 AM, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 14.10.2015 10:06, Alim Akhtar wrote: >> +Doug >> Hello, >> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >> and SDR104 modes. >> >> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >> >> What I remember is, one need to set "broken-cd" property also in order >> to make it work because of the vqmmc and vmmc connection on board. I >> didn't find the link right now, but you can search on the web, there >> was a long discussion about handling this. >> Have not checked it recently, so not sure if this got broken somehow. >> > > Please, don't top post. > I am sorry, but I didn't get this, what is the guide line here??? > I am not a SD/MMC specialist (I do not feel enough confident in its > internals) but the datasheet for 5422 does not mention UHS. However it > mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This > does not look like UHS... > https://www.sdcard.org/developers/overview/bus_speed/ > This of course is not a definite proof that 5422 does not support UHS. I > am just saying that I couldn't find any information that *it does*. > > Best regards, > Krzysztof >
On 14.10.2015 11:13, Alim Akhtar wrote: > On Wed, Oct 14, 2015 at 6:45 AM, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> On 14.10.2015 10:06, Alim Akhtar wrote: >>> +Doug >>> Hello, >>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >>> and SDR104 modes. >>> >>> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >>> >>> What I remember is, one need to set "broken-cd" property also in order >>> to make it work because of the vqmmc and vmmc connection on board. I >>> didn't find the link right now, but you can search on the web, there >>> was a long discussion about handling this. >>> Have not checked it recently, so not sure if this got broken somehow. >>> >> >> Please, don't top post. >> > I am sorry, but I didn't get this, what is the guide line here??? I mean reply inline, under the other person's quote, not above it. And some old, really old joke: A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing in e-mail? :) Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Oct 14, 2015 at 7:50 AM, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 14.10.2015 11:13, Alim Akhtar wrote: >> On Wed, Oct 14, 2015 at 6:45 AM, Krzysztof Kozlowski >> <k.kozlowski@samsung.com> wrote: >>> On 14.10.2015 10:06, Alim Akhtar wrote: >>>> +Doug >>>> Hello, >>>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >>>> and SDR104 modes. >>>> >>>> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >>>> >>>> What I remember is, one need to set "broken-cd" property also in order >>>> to make it work because of the vqmmc and vmmc connection on board. I >>>> didn't find the link right now, but you can search on the web, there >>>> was a long discussion about handling this. >>>> Have not checked it recently, so not sure if this got broken somehow. >>>> >>> >>> Please, don't top post. >>> >> I am sorry, but I didn't get this, what is the guide line here??? > > I mean reply inline, under the other person's quote, not above it. > > And some old, really old joke: > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing in e-mail? > > :) > I see..got it..thanks for clarification. > Best regards, > Krzysztof >
hi Krzysztof, On 14 October 2015 at 05:29, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 14.10.2015 01:27, Anand Moon wrote: >> Hi Krzysztof, >> >> On 13 October 2015 at 09:13, Krzysztof Kozlowski >> <k.kozlowski@samsung.com> wrote: >>> >>> On 13.10.2015 12:08, Anand Moon wrote: >>>> Hi Krzysztof, >>>> >>>> On 13 October 2015 at 05:44, Krzysztof Kozlowski >>>> <k.kozlowski@samsung.com> wrote: >>>>> On 13.10.2015 00:32, Anand Moon wrote: >>>>>> Hi Krzysztof, >>>>>> >>>>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>>>> <k.kozlowski@samsung.com> wrote: >>>>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>>>> >>>>>>> This description is not entirely correct. The MMC driver already >>>>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>>>> it (description of bindings says "is supported"). >>>>>>> >>>>>>> You mentioned DDR50 but I don't see respective property below. >>>>>>> >>>>>>> How do you know that these modes are really supported? I don't know. Can >>>>>>> you convince me? >>>>>> >>>>>> Setting this DDR50 capability give me this error. That's the reason to >>>>>> drop this capability. >>>>> >>>>> But you mentioned it in commit message! "Added support for UHS-I ... >>>>> (DDR50)" >>>>> >>>>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>>>> and SDR104 are really supported". >>>>> >>>> >>>> These changes are related to the microSD card capabilities. >>>> So SDR50 have better frequency over DDR50. On the same Sandisk card. >>>> >>>> When the card select the capability for DDR50 >>>> --------------------------------------------------- >>>> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >>>> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.009179] mmcblk0: error -110 sending status command, retrying >>>> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >>>> response 0x900, card status 0x900 >>>> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >>>> cmd response 0x900, card status 0x0 >>>> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 400000Hz, actual 396825HZ div = 63) >>>> [ 4.067770] Console: switching to colour frame buffer device 274x77 >>>> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.099692] mmc1: tried to reset card >>>> [ 4.101332] mmcblk0: p1 p2 >>>> >>>> >>>> When the card select the capability for SDR50 >>>> --------------------------------------------------------------------------------- >>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >>>> 100000000Hz, actual 100000000HZ div = 0) >>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 2.461743] mmcblk0: p1 p2 >>>> >>>> Which will relate to better read/write speed. >>> >>> Which is not an answer to my question. To none of my previous questions. >>> >> >> Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, >> sd-uhs-sdr104) help tune speed supported for mmc >> >> I have tired to compare the speed on high speed UHS-I vs ultra high >> speed UHS-I using izone utility. >> >> [ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 2.572609] mmc1: new high speed SDHC card at address aaaa >> >> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >> Output is in kBytes/sec >> Time Resolution = 0.000001 seconds. >> Processor cache size set to 32 kBytes. >> Processor cache line size set to 64 bytes. >> File stride size set to 17 * record size. >> random >> random bkwd record stride >> kB reclen write rewrite read reread read >> write read rewrite read fwrite frewrite fread >> freread >> 10240 4 1631 0 6556 0 5538 982 >> 10240 64 8828 0 18897 0 17994 303 >> 10240 128 6269 0 20670 0 20128 1096 >> --------------------------------------------------------------------------------------------------------- >> [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >> req 100000000Hz, actual 100000000HZ div = 0) >> [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> >> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >> Output is in kBytes/sec >> Time Resolution = 0.000001 seconds. >> Processor cache size set to 32 kBytes. >> Processor cache line size set to 64 bytes. >> File stride size set to 17 * record size. >> random >> random bkwd record stride >> kB reclen write rewrite read reread read >> write read rewrite read fwrite frewrite fread >> freread >> 10240 4 1809 0 7507 0 5233 859 >> 10240 64 11622 0 31250 0 28072 516 >> 10240 128 4320 0 34417 0 32509 1148 >> >> My observation is that their slight increase in read/write operation. >> >> Hope I have tried to answer you query. If I am wrong please let me know. > > Nope, that did not answer my query. You gave some performance benchmarks > but my question was not about the speed of anything. The question is > (once again): > How do you know that these modes are really supported? > > You are marking the *host* as supporting these modes. Please provide > information that host supports them *really*, not by experimenting "oh, > it seems to work now, maybe it will work always". > > Usually vendors, if their products implement some kind of > specification/protocol, they mark the products as "compatible with XYZ" etc. I found this link from hardkernel website which specify the interface support http://www.hardkernel.com/main/products/prdt_info.php?g_code=G141578491347 Manufacturer Part Number : Sandisk SDSDQAD-016G Interface : UHS-1 SDR50 I don't know much internal specification of the Odroid XU3/XU4 Boards. I am not sure if it will support host will sd-uhs-sdr104, but it will be compatible for sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50. -Anand Moon > > Best regards, > Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 14.10.2015 12:58, Anand Moon wrote: > hi Krzysztof, > > On 14 October 2015 at 05:29, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> On 14.10.2015 01:27, Anand Moon wrote: >>> Hi Krzysztof, >>> >>> On 13 October 2015 at 09:13, Krzysztof Kozlowski >>> <k.kozlowski@samsung.com> wrote: >>>> >>>> On 13.10.2015 12:08, Anand Moon wrote: >>>>> Hi Krzysztof, >>>>> >>>>> On 13 October 2015 at 05:44, Krzysztof Kozlowski >>>>> <k.kozlowski@samsung.com> wrote: >>>>>> On 13.10.2015 00:32, Anand Moon wrote: >>>>>>> Hi Krzysztof, >>>>>>> >>>>>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>>>>> <k.kozlowski@samsung.com> wrote: >>>>>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>>>>> >>>>>>>> This description is not entirely correct. The MMC driver already >>>>>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>>>>> it (description of bindings says "is supported"). >>>>>>>> >>>>>>>> You mentioned DDR50 but I don't see respective property below. >>>>>>>> >>>>>>>> How do you know that these modes are really supported? I don't know. Can >>>>>>>> you convince me? >>>>>>> >>>>>>> Setting this DDR50 capability give me this error. That's the reason to >>>>>>> drop this capability. >>>>>> >>>>>> But you mentioned it in commit message! "Added support for UHS-I ... >>>>>> (DDR50)" >>>>>> >>>>>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>>>>> and SDR104 are really supported". >>>>>> >>>>> >>>>> These changes are related to the microSD card capabilities. >>>>> So SDR50 have better frequency over DDR50. On the same Sandisk card. >>>>> >>>>> When the card select the capability for DDR50 >>>>> --------------------------------------------------- >>>>> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>>> req 50000000Hz, actual 50000000HZ div = 0) >>>>> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >>>>> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>> [ 4.009179] mmcblk0: error -110 sending status command, retrying >>>>> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >>>>> response 0x900, card status 0x900 >>>>> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >>>>> cmd response 0x900, card status 0x0 >>>>> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>>> req 400000Hz, actual 396825HZ div = 63) >>>>> [ 4.067770] Console: switching to colour frame buffer device 274x77 >>>>> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>>> req 50000000Hz, actual 50000000HZ div = 0) >>>>> [ 4.099692] mmc1: tried to reset card >>>>> [ 4.101332] mmcblk0: p1 p2 >>>>> >>>>> >>>>> When the card select the capability for SDR50 >>>>> --------------------------------------------------------------------------------- >>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >>>>> 100000000Hz, actual 100000000HZ div = 0) >>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>> [ 2.461743] mmcblk0: p1 p2 >>>>> >>>>> Which will relate to better read/write speed. >>>> >>>> Which is not an answer to my question. To none of my previous questions. >>>> >>> >>> Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, >>> sd-uhs-sdr104) help tune speed supported for mmc >>> >>> I have tired to compare the speed on high speed UHS-I vs ultra high >>> speed UHS-I using izone utility. >>> >>> [ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>> req 50000000Hz, actual 50000000HZ div = 0) >>> [ 2.572609] mmc1: new high speed SDHC card at address aaaa >>> >>> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >>> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >>> Output is in kBytes/sec >>> Time Resolution = 0.000001 seconds. >>> Processor cache size set to 32 kBytes. >>> Processor cache line size set to 64 bytes. >>> File stride size set to 17 * record size. >>> random >>> random bkwd record stride >>> kB reclen write rewrite read reread read >>> write read rewrite read fwrite frewrite fread >>> freread >>> 10240 4 1631 0 6556 0 5538 982 >>> 10240 64 8828 0 18897 0 17994 303 >>> 10240 128 6269 0 20670 0 20128 1096 >>> --------------------------------------------------------------------------------------------------------- >>> [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >>> req 100000000Hz, actual 100000000HZ div = 0) >>> [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>> >>> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >>> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >>> Output is in kBytes/sec >>> Time Resolution = 0.000001 seconds. >>> Processor cache size set to 32 kBytes. >>> Processor cache line size set to 64 bytes. >>> File stride size set to 17 * record size. >>> random >>> random bkwd record stride >>> kB reclen write rewrite read reread read >>> write read rewrite read fwrite frewrite fread >>> freread >>> 10240 4 1809 0 7507 0 5233 859 >>> 10240 64 11622 0 31250 0 28072 516 >>> 10240 128 4320 0 34417 0 32509 1148 >>> >>> My observation is that their slight increase in read/write operation. >>> >>> Hope I have tried to answer you query. If I am wrong please let me know. >> >> Nope, that did not answer my query. You gave some performance benchmarks >> but my question was not about the speed of anything. The question is >> (once again): >> How do you know that these modes are really supported? >> >> You are marking the *host* as supporting these modes. Please provide >> information that host supports them *really*, not by experimenting "oh, >> it seems to work now, maybe it will work always". >> >> Usually vendors, if their products implement some kind of >> specification/protocol, they mark the products as "compatible with XYZ" etc. > > I found this link from hardkernel website which specify the interface support > > http://www.hardkernel.com/main/products/prdt_info.php?g_code=G141578491347 > > Manufacturer Part Number : Sandisk SDSDQAD-016G > Interface : UHS-1 SDR50 > > I don't know much internal specification of the Odroid XU3/XU4 Boards. > > I am not sure if it will support host will sd-uhs-sdr104, but it will > be compatible for sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50. I can't find how this proofs anything. You can sell an UHS-II card labelled "for ODROID-XU3 and XU4" and it will work fine on Odroid-XU3. Does it mean that Odroid-XU3 supports UHS-II? That UHS-II card will work even on 10-year camera! Of course not in UHS mode... Does it mean that this 10-year old camera supports UHS-II? Of course not because it will work in some HS mode (or even pre-HS). You can label any SD card as "for Odroid XU3" because any card will work... Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Tue, Oct 13, 2015 at 6:06 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote: > +Doug > Hello, > AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 > and SDR104 modes. > > [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html > > What I remember is, one need to set "broken-cd" property also in order > to make it work because of the vqmmc and vmmc connection on board. I > didn't find the link right now, but you can search on the web, there > was a long discussion about handling this. > Have not checked it recently, so not sure if this got broken somehow. Right. It _shouldn't_ be possible to add "vmmc/vqmmc" supplies to your DTS (which you do in patch 2/3) and also to use the "gpc2-2" pin for card detect (even if you configure it as a GPIO). Once you add "vmmc/vqmmc" then Linux ought to be turning these regulators off when no card is plugged in. Presumably the "vqmmc" regulator is hooked up to the "VDDQ_MMC2". If you look in the user manual for 5422 you can see that "GPC2[2]/SD_2_CDn" has power domain "VDDQ_MMC2". Thus you really shouldn't be using that pin when vqmmc is off. I think at some point someone claimed that it still worked for them, but nobody could ever explain why. Full discussion at <https://patchwork.kernel.org/patch/4763881/> --- In case it matters, comments on stuff from earlier in the thread: * As people pointed out, exynos5422 certainly supports all these modes (including DDR50) in the SoC. * Just because the SoC supports these modes doesn't mean that the boards do, which is why the SoC .dtsi doesn't include them. Thus, this patch is "right" in that it changes a board-specific file. * As Krzysztof points out this board doesn't "add" support but rather "enables" support. The distinction is subtle. * You might be able to get DDR50 working, but probably better to just start with SDR modes. Previously I never attempted to get DDR50 cards working, so possibly the software needs extra work? -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Doug/ Krzysztof , On 15 October 2015 at 04:10, Doug Anderson <dianders@chromium.org> wrote: > Hi, > > On Tue, Oct 13, 2015 at 6:06 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote: >> +Doug >> Hello, >> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >> and SDR104 modes. >> >> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >> >> What I remember is, one need to set "broken-cd" property also in order >> to make it work because of the vqmmc and vmmc connection on board. I >> didn't find the link right now, but you can search on the web, there >> was a long discussion about handling this. >> Have not checked it recently, so not sure if this got broken somehow. > > Right. It _shouldn't_ be possible to add "vmmc/vqmmc" supplies to > your DTS (which you do in patch 2/3) and also to use the "gpc2-2" pin > for card detect (even if you configure it as a GPIO). Once you add > "vmmc/vqmmc" then Linux ought to be turning these regulators off when > no card is plugged in. Presumably the "vqmmc" regulator is hooked up > to the "VDDQ_MMC2". If you look in the user manual for 5422 you can > see that "GPC2[2]/SD_2_CDn" has power domain "VDDQ_MMC2". Thus you > really shouldn't be using that pin when vqmmc is off. I think at some > point someone claimed that it still worked for them, but nobody could > ever explain why. Full discussion at > <https://patchwork.kernel.org/patch/4763881/> > > --- > > In case it matters, comments on stuff from earlier in the thread: > > * As people pointed out, exynos5422 certainly supports all these modes > (including DDR50) in the SoC. > > * Just because the SoC supports these modes doesn't mean that the > boards do, which is why the SoC .dtsi doesn't include them. Thus, > this patch is "right" in that it changes a board-specific file. > > * As Krzysztof points out this board doesn't "add" support but rather > "enables" support. The distinction is subtle. > > * You might be able to get DDR50 working, but probably better to just > start with SDR modes. Previously I never attempted to get DDR50 cards > working, so possibly the software needs extra work? > Thanks for clarifying all the background details on the mmc changes. Here is what I would conclude from the previous mail chain's. 1 Drop the cd-gpios changes. pinctrl-0 changes. 2 Fix the regulator changes for vmmc/vqmmc with disable of regulator-always-on; 3 Drop this UHS-I changes as if now. Is this ok with you. -Anand Moon > > -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
W dniu 19.10.2015 o 19:11, Anand Moon pisze: > Hi Doug/ Krzysztof , > > > Thanks for clarifying all the background details on the mmc changes. > > Here is what I would conclude from the previous mail chain's. > > 1 Drop the cd-gpios changes. pinctrl-0 changes. OK > > 2 Fix the regulator changes for vmmc/vqmmc with disable of regulator-always-on; Just fix all the comments for patch 2. > > 3 Drop this UHS-I changes as if now. > > Is this ok with you. It's okay. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Mon, Oct 19, 2015 at 3:11 AM, Anand Moon <linux.amoon@gmail.com> wrote: > 1 Drop the cd-gpios changes. pinctrl-0 changes. Right. > 2 Fix the regulator changes for vmmc/vqmmc with disable of regulator-always-on; I'm not totally sure I understand. You should need to keep vmmc and vqmmc always on because otherwise you can't do card detection (unless you poll for card detect). > 3 Drop this UHS-I changes as if now. Sounds right. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, Anand. On 10/14/2015 12:58 PM, Anand Moon wrote: > hi Krzysztof, > > On 14 October 2015 at 05:29, Krzysztof Kozlowski > <k.kozlowski@samsung.com> wrote: >> On 14.10.2015 01:27, Anand Moon wrote: >>> Hi Krzysztof, >>> >>> On 13 October 2015 at 09:13, Krzysztof Kozlowski >>> <k.kozlowski@samsung.com> wrote: >>>> >>>> On 13.10.2015 12:08, Anand Moon wrote: >>>>> Hi Krzysztof, >>>>> >>>>> On 13 October 2015 at 05:44, Krzysztof Kozlowski >>>>> <k.kozlowski@samsung.com> wrote: >>>>>> On 13.10.2015 00:32, Anand Moon wrote: >>>>>>> Hi Krzysztof, >>>>>>> >>>>>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>>>>> <k.kozlowski@samsung.com> wrote: >>>>>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>>>>> >>>>>>>> This description is not entirely correct. The MMC driver already >>>>>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>>>>> it (description of bindings says "is supported"). >>>>>>>> >>>>>>>> You mentioned DDR50 but I don't see respective property below. >>>>>>>> >>>>>>>> How do you know that these modes are really supported? I don't know. Can >>>>>>>> you convince me? >>>>>>> >>>>>>> Setting this DDR50 capability give me this error. That's the reason to >>>>>>> drop this capability. >>>>>> >>>>>> But you mentioned it in commit message! "Added support for UHS-I ... >>>>>> (DDR50)" >>>>>> >>>>>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>>>>> and SDR104 are really supported". >>>>>> >>>>> >>>>> These changes are related to the microSD card capabilities. >>>>> So SDR50 have better frequency over DDR50. On the same Sandisk card. >>>>> >>>>> When the card select the capability for DDR50 >>>>> --------------------------------------------------- >>>>> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>>> req 50000000Hz, actual 50000000HZ div = 0) >>>>> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >>>>> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>> [ 4.009179] mmcblk0: error -110 sending status command, retrying >>>>> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >>>>> response 0x900, card status 0x900 >>>>> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >>>>> cmd response 0x900, card status 0x0 >>>>> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>>> req 400000Hz, actual 396825HZ div = 63) >>>>> [ 4.067770] Console: switching to colour frame buffer device 274x77 >>>>> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>>> req 50000000Hz, actual 50000000HZ div = 0) >>>>> [ 4.099692] mmc1: tried to reset card >>>>> [ 4.101332] mmcblk0: p1 p2 I found this issue that produced on your board. I will send the patch and test DDR50 on your board. Best Regards, Jaehoon Chung >>>>> >>>>> >>>>> When the card select the capability for SDR50 >>>>> --------------------------------------------------------------------------------- >>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >>>>> 100000000Hz, actual 100000000HZ div = 0) >>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>> [ 2.461743] mmcblk0: p1 p2 >>>>> >>>>> Which will relate to better read/write speed. >>>> >>>> Which is not an answer to my question. To none of my previous questions. >>>> >>> >>> Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, >>> sd-uhs-sdr104) help tune speed supported for mmc >>> >>> I have tired to compare the speed on high speed UHS-I vs ultra high >>> speed UHS-I using izone utility. >>> >>> [ 2.572469] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>> req 50000000Hz, actual 50000000HZ div = 0) >>> [ 2.572609] mmc1: new high speed SDHC card at address aaaa >>> >>> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >>> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >>> Output is in kBytes/sec >>> Time Resolution = 0.000001 seconds. >>> Processor cache size set to 32 kBytes. >>> Processor cache line size set to 64 bytes. >>> File stride size set to 17 * record size. >>> random >>> random bkwd record stride >>> kB reclen write rewrite read reread read >>> write read rewrite read fwrite frewrite fread >>> freread >>> 10240 4 1631 0 6556 0 5538 982 >>> 10240 64 8828 0 18897 0 17994 303 >>> 10240 128 6269 0 20670 0 20128 1096 >>> --------------------------------------------------------------------------------------------------------- >>> [ 2.613761] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >>> req 100000000Hz, actual 100000000HZ div = 0) >>> [ 2.623573] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>> >>> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >>> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >>> Output is in kBytes/sec >>> Time Resolution = 0.000001 seconds. >>> Processor cache size set to 32 kBytes. >>> Processor cache line size set to 64 bytes. >>> File stride size set to 17 * record size. >>> random >>> random bkwd record stride >>> kB reclen write rewrite read reread read >>> write read rewrite read fwrite frewrite fread >>> freread >>> 10240 4 1809 0 7507 0 5233 859 >>> 10240 64 11622 0 31250 0 28072 516 >>> 10240 128 4320 0 34417 0 32509 1148 >>> >>> My observation is that their slight increase in read/write operation. >>> >>> Hope I have tried to answer you query. If I am wrong please let me know. >> >> Nope, that did not answer my query. You gave some performance benchmarks >> but my question was not about the speed of anything. The question is >> (once again): >> How do you know that these modes are really supported? >> >> You are marking the *host* as supporting these modes. Please provide >> information that host supports them *really*, not by experimenting "oh, >> it seems to work now, maybe it will work always". >> >> Usually vendors, if their products implement some kind of >> specification/protocol, they mark the products as "compatible with XYZ" etc. > > I found this link from hardkernel website which specify the interface support > > http://www.hardkernel.com/main/products/prdt_info.php?g_code=G141578491347 > > Manufacturer Part Number : Sandisk SDSDQAD-016G > Interface : UHS-1 SDR50 > > I don't know much internal specification of the Odroid XU3/XU4 Boards. > > I am not sure if it will support host will sd-uhs-sdr104, but it will > be compatible for sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50. > > -Anand Moon > >> >> Best regards, >> Krzysztof > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 58c06d3..ba4a87b 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -364,6 +364,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; }; &pinctrl_0 {
Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch Changes Fixed the UHS-I bus speed detedtion on cold boot. [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2 --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+)