Message ID | 1443798319-45744-4-git-send-email-yingjoe.chen@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Hi Daniel,
[auto build test results on v4.3-rc3 -- if it's inappropriate base, please ignore]
config: arm64-allyesconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All error/warnings (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/mediatek/mt8173.dtsi:246.24-25 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
On 02/10/15 17:05, Yingjoe Chen wrote: > From: Daniel Kurtz <djkurtz@chromium.org> > > Add device node to enable GPT timer. > > Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> > Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> > Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > --- I reapplied this on v4.4-next/arm64 > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index d18ee42..d763803 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -238,6 +238,15 @@ > reg = <0 0x10007000 0 0x100>; > }; > > + timer: timer@10008000 { > + compatible = "mediatek,mt8173-timer", > + "mediatek,mt6577-timer"; > + reg = <0 0x10008000 0 0x1000>; > + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_CLK_13M>, > + <&topckgen CLK_TOP_RTC_SEL>; > + }; > + > pwrap: pwrap@1000d000 { > compatible = "mediatek,mt8173-pwrap"; > reg = <0 0x1000d000 0 0x1000>; >
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d18ee42..d763803 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -238,6 +238,15 @@ reg = <0 0x10007000 0 0x100>; }; + timer: timer@10008000 { + compatible = "mediatek,mt8173-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_CLK_13M>, + <&topckgen CLK_TOP_RTC_SEL>; + }; + pwrap: pwrap@1000d000 { compatible = "mediatek,mt8173-pwrap"; reg = <0 0x1000d000 0 0x1000>;