diff mbox

[v4,2/5,RFC] clk: shmobile: Add r8a7795 CPG Core Clock Definitions

Message ID 1444999760-15750-3-git-send-email-geert+renesas@glider.be (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show

Commit Message

Geert Uytterhoeven Oct. 16, 2015, 12:49 p.m. UTC 
Add all R-Car H3 CPG Core Clock Outputs defined in the datasheet.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
  - Add all clocks instead of just the ones used by the current DTS.

v3:
  - New.
---
 include/dt-bindings/clock/r8a7795-cpg-mssr.h | 63 ++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7795-cpg-mssr.h

Comments

Geert Uytterhoeven Oct. 20, 2015, 10:09 a.m. UTC | #1 
On Fri, Oct 16, 2015 at 2:49 PM, Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> Add all R-Car H3 CPG Core Clock Outputs defined in the datasheet.

Cfr. Table 8.2a ("List of Clocks [R-Car H3]").

> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7795 CPG Core Clocks */
> +#define R8A7795_CLK_Z                  0
> +#define R8A7795_CLK_Z2                 1
> +#define R8A7795_CLK_ZR                 2
> +#define R8A7795_CLK_ZG                 3
> +#define R8A7795_CLK_ZTR                        4
> +#define R8A7795_CLK_ZTRD2              5
> +#define R8A7795_CLK_ZT                 6
> +#define R8A7795_CLK_ZX                 7
> +#define R8A7795_CLK_S0D1               8
> +#define R8A7795_CLK_S0D4               9
> +#define R8A7795_CLK_S1D1               10
> +#define R8A7795_CLK_S1D2               11
> +#define R8A7795_CLK_S1D4               12
> +#define R8A7795_CLK_S2D1               13
> +#define R8A7795_CLK_S2D2               14
> +#define R8A7795_CLK_S2D4               15
> +#define R8A7795_CLK_S3D1               16
> +#define R8A7795_CLK_S3D2               17
> +#define R8A7795_CLK_S3D4               18

Please note that I deliberately left out S[0-3], as they're used as
internal clock
sources only.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Magnus Damm Oct. 20, 2015, 4:21 p.m. UTC | #2 
On Tue, Oct 20, 2015 at 7:09 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Fri, Oct 16, 2015 at 2:49 PM, Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
>> Add all R-Car H3 CPG Core Clock Outputs defined in the datasheet.
>
> Cfr. Table 8.2a ("List of Clocks [R-Car H3]").

Thanks for this additional information. Would it be possible to add
that table pointer together with data sheet revision to the commit
message or a comment in the code so we know which version of the
documentation this file is based on?

>> --- /dev/null
>> +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
>> @@ -0,0 +1,63 @@
>> +/*
>> + * Copyright (C) 2015 Renesas Electronics Corp.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
>> +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
>> +
>> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
>> +
>> +/* r8a7795 CPG Core Clocks */
>> +#define R8A7795_CLK_Z                  0
>> +#define R8A7795_CLK_Z2                 1
>> +#define R8A7795_CLK_ZR                 2
>> +#define R8A7795_CLK_ZG                 3
>> +#define R8A7795_CLK_ZTR                        4
>> +#define R8A7795_CLK_ZTRD2              5
>> +#define R8A7795_CLK_ZT                 6
>> +#define R8A7795_CLK_ZX                 7
>> +#define R8A7795_CLK_S0D1               8
>> +#define R8A7795_CLK_S0D4               9
>> +#define R8A7795_CLK_S1D1               10
>> +#define R8A7795_CLK_S1D2               11
>> +#define R8A7795_CLK_S1D4               12
>> +#define R8A7795_CLK_S2D1               13
>> +#define R8A7795_CLK_S2D2               14
>> +#define R8A7795_CLK_S2D4               15
>> +#define R8A7795_CLK_S3D1               16
>> +#define R8A7795_CLK_S3D2               17
>> +#define R8A7795_CLK_S3D4               18
>
> Please note that I deliberately left out S[0-3], as they're used as
> internal clock
> sources only.

Omitting internal clock sources sounds sane to me. If you're going to
update the commit message they may I suggest that you list the
intentionally omitted clocks there?

Reviewed-by: Magnus Damm <damm+renesas@opensource.se>

Thanks for your help!

Best,

/ magnus
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Laurent Pinchart Oct. 23, 2015, 11:21 a.m. UTC | #3 
Hi Geert,

Thank you for the patch.

On Friday 16 October 2015 14:49:17 Geert Uytterhoeven wrote:
> Add all R-Car H3 CPG Core Clock Outputs defined in the datasheet.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4:
>   - Add all clocks instead of just the ones used by the current DTS.
> 
> v3:
>   - New.
> ---
>  include/dt-bindings/clock/r8a7795-cpg-mssr.h | 63 +++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a7795-cpg-mssr.h
> 
> diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> b/include/dt-bindings/clock/r8a7795-cpg-mssr.h new file mode 100644
> index 0000000000000000..e864aae0a2561c4b
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7795 CPG Core Clocks */
> +#define R8A7795_CLK_Z			0
> +#define R8A7795_CLK_Z2			1
> +#define R8A7795_CLK_ZR			2
> +#define R8A7795_CLK_ZG			3
> +#define R8A7795_CLK_ZTR			4
> +#define R8A7795_CLK_ZTRD2		5
> +#define R8A7795_CLK_ZT			6
> +#define R8A7795_CLK_ZX			7
> +#define R8A7795_CLK_S0D1		8
> +#define R8A7795_CLK_S0D4		9
> +#define R8A7795_CLK_S1D1		10
> +#define R8A7795_CLK_S1D2		11
> +#define R8A7795_CLK_S1D4		12
> +#define R8A7795_CLK_S2D1		13
> +#define R8A7795_CLK_S2D2		14
> +#define R8A7795_CLK_S2D4		15
> +#define R8A7795_CLK_S3D1		16
> +#define R8A7795_CLK_S3D2		17
> +#define R8A7795_CLK_S3D4		18
> +#define R8A7795_CLK_LB			19
> +#define R8A7795_CLK_CL			20
> +#define R8A7795_CLK_ZB3			21
> +#define R8A7795_CLK_ZB3D2		22
> +#define R8A7795_CLK_CR			23
> +#define R8A7795_CLK_CRD2		24
> +#define R8A7795_CLK_SD0H		25
> +#define R8A7795_CLK_SD0			26
> +#define R8A7795_CLK_SD1H		27
> +#define R8A7795_CLK_SD1			28
> +#define R8A7795_CLK_SD2H		29
> +#define R8A7795_CLK_SD2			30
> +#define R8A7795_CLK_SD3H		31
> +#define R8A7795_CLK_SD3			32
> +#define R8A7795_CLK_SSP2		33
> +#define R8A7795_CLK_SSP1		34
> +#define R8A7795_CLK_SSPRS		35
> +#define R8A7795_CLK_RPC			36
> +#define R8A7795_CLK_RPCD2		37
> +#define R8A7795_CLK_MSO			38
> +#define R8A7795_CLK_CANFD		39
> +#define R8A7795_CLK_HDMI		40
> +#define R8A7795_CLK_CSI0		41
> +#define R8A7795_CLK_CSIREF		42
> +#define R8A7795_CLK_CP			43
> +#define R8A7795_CLK_CPEX		44
> +#define R8A7795_CLK_R			45
> +#define R8A7795_CLK_OSC			46

Those two clocks are called RCLK and OSCCLK in the datasheet, shouldn't we use 
those names ?

Apart from that,

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> +#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
Geert Uytterhoeven Oct. 23, 2015, 11:25 a.m. UTC | #4 
Hi Laurent,

On Fri, Oct 23, 2015 at 1:21 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>> +#define R8A7795_CLK_R                        45
>> +#define R8A7795_CLK_OSC                      46
>
> Those two clocks are called RCLK and OSCCLK in the datasheet, shouldn't we use
> those names ?

..._CLK_RCLK and ..._CLK_OSCCLK sound a bit heavy to me.

Besides, all other clocks in the datasheet have a "?" suffix, which also
means "CLK", and which we don't retain.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
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diff mbox

Patch

diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
new file mode 100644
index 0000000000000000..e864aae0a2561c4b
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
@@ -0,0 +1,63 @@ 
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7795 CPG Core Clocks */
+#define R8A7795_CLK_Z			0
+#define R8A7795_CLK_Z2			1
+#define R8A7795_CLK_ZR			2
+#define R8A7795_CLK_ZG			3
+#define R8A7795_CLK_ZTR			4
+#define R8A7795_CLK_ZTRD2		5
+#define R8A7795_CLK_ZT			6
+#define R8A7795_CLK_ZX			7
+#define R8A7795_CLK_S0D1		8
+#define R8A7795_CLK_S0D4		9
+#define R8A7795_CLK_S1D1		10
+#define R8A7795_CLK_S1D2		11
+#define R8A7795_CLK_S1D4		12
+#define R8A7795_CLK_S2D1		13
+#define R8A7795_CLK_S2D2		14
+#define R8A7795_CLK_S2D4		15
+#define R8A7795_CLK_S3D1		16
+#define R8A7795_CLK_S3D2		17
+#define R8A7795_CLK_S3D4		18
+#define R8A7795_CLK_LB			19
+#define R8A7795_CLK_CL			20
+#define R8A7795_CLK_ZB3			21
+#define R8A7795_CLK_ZB3D2		22
+#define R8A7795_CLK_CR			23
+#define R8A7795_CLK_CRD2		24
+#define R8A7795_CLK_SD0H		25
+#define R8A7795_CLK_SD0			26
+#define R8A7795_CLK_SD1H		27
+#define R8A7795_CLK_SD1			28
+#define R8A7795_CLK_SD2H		29
+#define R8A7795_CLK_SD2			30
+#define R8A7795_CLK_SD3H		31
+#define R8A7795_CLK_SD3			32
+#define R8A7795_CLK_SSP2		33
+#define R8A7795_CLK_SSP1		34
+#define R8A7795_CLK_SSPRS		35
+#define R8A7795_CLK_RPC			36
+#define R8A7795_CLK_RPCD2		37
+#define R8A7795_CLK_MSO			38
+#define R8A7795_CLK_CANFD		39
+#define R8A7795_CLK_HDMI		40
+#define R8A7795_CLK_CSI0		41
+#define R8A7795_CLK_CSIREF		42
+#define R8A7795_CLK_CP			43
+#define R8A7795_CLK_CPEX		44
+#define R8A7795_CLK_R			45
+#define R8A7795_CLK_OSC			46
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */