| Message ID | 1446514438-13922-2-git-send-email-wxt@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Nov 03, 2015 at 09:33:54AM +0800, Caesar Wang wrote: > In order to support more sample rates, add the divider clock api. > > As the input source clock to the module is MCLK_I2S, > and by the divider of the module, the clock generator generates > SCLK and LRCK to transmitter and receiver. Same thing as your other very similar patch: why does this feature require set_clkdiv()?
On Thu, Nov 05, 2015 at 01:56:39PM +0800, Caesar Wang wrote: > ? 2015?11?04? 22:34, Mark Brown ??: > >Same thing as your other very similar patch: why does this feature > >require set_clkdiv()? > Okay, you said " > Why is this a requirement? The clock to use as a source should normally > be specified via set_sysclk() and any internal dividers calculated > automatically by the driver. > " > I think we should divider settings for these different sample rates. Sure, the question is how these things get set. > If the codec is master mode, we are *not* need this operate. > If the codec is slave mode, we are need to divider the MCLK to setting the different sample rates. > (for example, the sample rates (8k, 48k) the clock is MCLK, the clock should be divider cpu ip ) > "dividers calculated automatically by the driver", that should be occured by codec(max98090 > ) driver, but the divider clocks (LRCK, SCLK) should need to set for cpu internal side. So the CPU knows what rates it needs to set and what clocks it's getting in, why can't it set the dividers autonomously.
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index b936102..23c867f 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -286,6 +286,32 @@ static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, return ret; } +static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, + int div_id, int div) +{ + struct rk_i2s_dev *i2s = to_info(cpu_dai); + unsigned int val = 0; + + switch (div_id) { + case ROCKCHIP_DIV_BCLK: + val |= I2S_CKR_TSD(div); + val |= I2S_CKR_RSD(div); + regmap_update_bits(i2s->regmap, I2S_CKR, + I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK, + val); + break; + case ROCKCHIP_DIV_MCLK: + val |= I2S_CKR_MDIV(div); + regmap_update_bits(i2s->regmap, I2S_CKR, + I2S_CKR_MDIV_MASK, val); + break; + default: + return -EINVAL; + } + + return 0; +} + static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int dir) { @@ -311,6 +337,7 @@ static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { .hw_params = rockchip_i2s_hw_params, + .set_clkdiv = rockchip_i2s_set_clkdiv, .set_sysclk = rockchip_i2s_set_sysclk, .set_fmt = rockchip_i2s_set_fmt, .trigger = rockchip_i2s_trigger,
In order to support more sample rates, add the divider clock api. As the input source clock to the module is MCLK_I2S, and by the divider of the module, the clock generator generates SCLK and LRCK to transmitter and receiver. Signed-off-by: Caesar Wang <wxt@rock-chips.com> --- Changes in v1: - change the subject and commit. - remove the print message dev_dbg(). sound/soc/rockchip/rockchip_i2s.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)