| Message ID | 1449634091-1842-13-git-send-email-cw00.choi@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 09.12.2015 13:08, Chanwoo Choi wrote: > This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. > Exynos3250 has following AXI buses to translate data between > DRAM and sub-blocks. > > Following list specifies the detailed relation between DRAM and sub-blocks: > - ACLK400 clock for MCUISP > - ACLK266 clock for ISP > - ACLK200 clock for FSYS > - ACLK160 clock for LCD0 > - ACLK100 clock for PERIL > - GDL clock for LEFTBUS > - GDR clock for RIGHTBUS > - SCLK_MFC clock for MFC > > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > --- > arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 160 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi > index 7214c5e42150..46dee1951ec1 100644 > --- a/arch/arm/boot/dts/exynos3250.dtsi > +++ b/arch/arm/boot/dts/exynos3250.dtsi > @@ -721,6 +721,166 @@ > opp-microvolt = <875000>; > }; > }; > + > + bus_leftbus: bus_leftbus { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_GDL>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_rightbus: bus_rightbus { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_GDR>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_lcd0: bus_lcd0 { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_160>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_fsys: bus_fsys { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_200>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_mcuisp: bus_mcuisp { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_mcuisp_opp_table>; > + status = "disabled"; > + }; > + > + bus_isp: bus_isp { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_266>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_isp_opp_table>; > + status = "disabled"; > + }; > + > + bus_peril: bus_peril { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_100>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_peril_opp_table>; > + status = "disabled"; > + }; > + > + bus_mfc: bus_mfc { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_SCLK_MFC>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_leftbus_opp_table: opp_table2 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = /bits/ 64 <50000000>; > + opp-microvolt = <900000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <80000000>; > + opp-microvolt = <900000>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <100000000>; > + opp-microvolt = <1000000>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <134000000>; > + opp-microvolt = <1000000>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <200000000>; > + opp-microvolt = <1000000>; > + }; > + }; > + > + bus_mcuisp_opp_table: opp_table3 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = /bits/ 64 <50000000>; > + opp-microvolt = <900000>; The voltages for all these INT-block tables have exactly the same value which of course makes sense because this is the same regulator. However the opp-microvolt property is an optional property. Do you have to provide it in each OPP? Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 2015? 12? 10? 11:09, Krzysztof Kozlowski wrote: > On 09.12.2015 13:08, Chanwoo Choi wrote: >> This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. >> Exynos3250 has following AXI buses to translate data between >> DRAM and sub-blocks. >> >> Following list specifies the detailed relation between DRAM and sub-blocks: >> - ACLK400 clock for MCUISP >> - ACLK266 clock for ISP >> - ACLK200 clock for FSYS >> - ACLK160 clock for LCD0 >> - ACLK100 clock for PERIL >> - GDL clock for LEFTBUS >> - GDR clock for RIGHTBUS >> - SCLK_MFC clock for MFC >> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> --- >> arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 160 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi >> index 7214c5e42150..46dee1951ec1 100644 >> --- a/arch/arm/boot/dts/exynos3250.dtsi >> +++ b/arch/arm/boot/dts/exynos3250.dtsi >> @@ -721,6 +721,166 @@ >> opp-microvolt = <875000>; >> }; >> }; >> + >> + bus_leftbus: bus_leftbus { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_DIV_GDL>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_leftbus_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_rightbus: bus_rightbus { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_DIV_GDR>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_leftbus_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_lcd0: bus_lcd0 { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_DIV_ACLK_160>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_leftbus_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_fsys: bus_fsys { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_DIV_ACLK_200>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_leftbus_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_mcuisp: bus_mcuisp { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_mcuisp_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_isp: bus_isp { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_DIV_ACLK_266>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_isp_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_peril: bus_peril { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_DIV_ACLK_100>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_peril_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_mfc: bus_mfc { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&cmu CLK_SCLK_MFC>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_leftbus_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_leftbus_opp_table: opp_table2 { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp00 { >> + opp-hz = /bits/ 64 <50000000>; >> + opp-microvolt = <900000>; >> + }; >> + opp01 { >> + opp-hz = /bits/ 64 <80000000>; >> + opp-microvolt = <900000>; >> + }; >> + opp02 { >> + opp-hz = /bits/ 64 <100000000>; >> + opp-microvolt = <1000000>; >> + }; >> + opp03 { >> + opp-hz = /bits/ 64 <134000000>; >> + opp-microvolt = <1000000>; >> + }; >> + opp04 { >> + opp-hz = /bits/ 64 <200000000>; >> + opp-microvolt = <1000000>; >> + }; >> + }; >> + >> + bus_mcuisp_opp_table: opp_table3 { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp00 { >> + opp-hz = /bits/ 64 <50000000>; >> + opp-microvolt = <900000>; > > The voltages for all these INT-block tables have exactly the same value > which of course makes sense because this is the same regulator. However > the opp-microvolt property is an optional property. Do you have to > provide it in each OPP? I couldn't check whether opp-microvolt property is optional or not. You're right. Except for the opp-microvolt property of parent device, I'll remove it on dts file. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 7214c5e42150..46dee1951ec1 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -721,6 +721,166 @@ opp-microvolt = <875000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_isp_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_peril_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + }; }; };
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+)