diff mbox

drm/i915: Add Backlight Control using DPCD for eDP connectors (v3)

Message ID 1447698547-9027-1-git-send-email-yetundex.adebisi@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Yetunde Adebisi Nov. 16, 2015, 6:29 p.m. UTC
This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/intel_dp.c               |  16 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 177 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |   6 +
 drivers/gpu/drm/i915/intel_panel.c            |   4 +
 5 files changed, 198 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

Comments

Jani Nikula Nov. 20, 2015, 3:04 p.m. UTC | #1
On Mon, 16 Nov 2015, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote:
> This patch adds support for eDP backlight control using DPCD registers to
> backlight hooks in intel_panel.
>
> It checks for backlight control over AUX channel capability and sets up
> function pointers to get and set the backlight brightness level if
> supported.
>
> v2: Moved backlight functions from intel_dp.c into a new file
> intel_dp_aux_backlight.c. Also moved reading of eDP display control
> registers to intel_dp_get_dpcd
>
> v3: Correct some formatting mistakes
>
> This patch depends on http://patchwork.freedesktop.org/patch/64253/
>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  drivers/gpu/drm/i915/intel_dp.c               |  16 ++-
>  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 177 ++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h              |   6 +
>  drivers/gpu/drm/i915/intel_panel.c            |   4 +
>  5 files changed, 198 insertions(+), 6 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0851de07..7a1db3d 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
>  	  dvo_tfp410.o \
>  	  intel_crt.o \
>  	  intel_ddi.o \
> +	  intel_dp_aux_backlight.o\

Space before \ please.

>  	  intel_dp_link_training.o \
>  	  intel_dp_mst.o \
>  	  intel_dp.o \
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8071247..22e0241 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3156,7 +3156,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
>   * Sinks are *supposed* to come up within 1ms from an off state, but we're also
>   * supposed to retry 3 times per the spec.
>   */
> -static ssize_t
> +ssize_t
>  intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
>  			void *buffer, size_t size)
>  {
> @@ -3823,7 +3823,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint8_t rev;
>  
>  	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
>  				    sizeof(intel_dp->dpcd)) < 0)
> @@ -3859,6 +3858,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  			DRM_DEBUG_KMS("PSR2 %s on sink",
>  				dev_priv->psr.psr2_support ? "supported" : "not supported");
>  		}
> +
> +		/* Read the eDP Display control capabilities registers */

You need to clear intel_dp->dpcd_edp here.

> +		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> +				(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
> +						intel_dp->dpcd_edp, sizeof(intel_dp->dpcd_edp)) ==
> +								sizeof(intel_dp->dpcd_edp)))
> +			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->dpcd_edp),
> +					intel_dp->dpcd_edp);
>  	}
>  
>  	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
> @@ -3866,10 +3873,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
>  
>  	/* Intermediate frequency support */
> -	if (is_edp(intel_dp) &&
> -	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> -	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
> -	    (rev >= 0x03)) { /* eDp v1.4 or higher */
> +	if (is_edp(intel_dp) && (intel_dp->dpcd_edp[0] >= 0x03)) { /* eDp v1.4 or higher */
>  		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
>  		int i;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> new file mode 100644
> index 0000000..190c5d9
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -0,0 +1,177 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "intel_drv.h"
> +
> +static bool is_aux_backlight_enabled(struct drm_dp_aux *aux)
> +{
> +	uint8_t read_val = 0;
> +
> +	if (intel_dp_dpcd_read_wake(aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
> +			&read_val, sizeof(read_val)) < 0)
> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> +				DP_EDP_DISPLAY_CONTROL_REGISTER);
> +
> +	return read_val & DP_EDP_BACKLIGHT_ENABLE;
> +}
> +
> +static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
> +{
> +	uint8_t reg_val = 0;
> +
> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
> +				DP_EDP_DISPLAY_CONTROL_REGISTER,
> +				&reg_val, sizeof(reg_val)) < 0) {
> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> +				DP_EDP_DISPLAY_CONTROL_REGISTER);
> +		return;
> +	}
> +	if (enable)
> +		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> +	else
> +		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> +
> +	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
> +			reg_val) < 0) {
> +		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
> +				enable ? "enable" : "disable");
> +	}
> +}
> +
> +/*
> + * Read the current backlight value from DPCD register(s) based
> + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
> + */
> +static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t read_val[2] = { 0x0 };
> +	uint16_t level = 0;
> +
> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
> +			DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> +			&read_val, sizeof(read_val)) < 0) {
> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> +				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
> +		return 0;
> +	}
> +	level = read_val[0];
> +	if (intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> +		level = (read_val[0] << 8 | read_val[1]);
> +
> +	return level;
> +}
> +
> +/*
> + * Sends the current backlight level over the aux channel, checking if its using
> + * 8-bit or 16 bit value (MSB and LSB)
> + */
> +static void
> +intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t vals[2] = { 0x0 };
> +
> +	DRM_DEBUG_KMS("Level 0x%x\n", level);

The caller of the hook does debug logging already.

> +	vals[0] = level;
> +
> +	/* Write the MSB and/or LSB */
> +	 if (intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
> +		vals[0] = (level & 0xFF00) >> 8;
> +		vals[1] = (level & 0xFF);
> +	}
> +	if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> +			vals, sizeof(vals)) < 0) {
> +		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
> +		return;
> +	}
> +}
> +
> +static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
> +{
> +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), true);
> +}
> +
> +static void intel_dp_aux_disable_backlight(struct intel_connector *connector)
> +{
> +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), false);
> +}
> +
> +static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
> +			enum pipe pipe)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	struct intel_panel *panel = &connector->panel;
> +
> +	if (intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> +		panel->backlight.max = 0xFFFF;
> +	else
> +		panel->backlight.max = 0xFF;
> +
> +	panel->backlight.min = 0;
> +
> +	panel->backlight.level = intel_dp_aux_get_backlight(connector);
> +	panel->backlight.enabled = is_aux_backlight_enabled(&intel_dp->aux);
> +
> +	return 0;
> +}
> +
> +static bool intel_dp_aux_display_control_capable(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t dpcd_buf = 0;
> +
> +	/* Check the  eDP Display control capabilities registers to determine if
> +	 * the panel can support backlight control over the aux channel*/
> +
> +	if (intel_dp->dpcd_edp[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> +			(intel_dp->dpcd_edp[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> +			(intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
> +			((intel_dp_dpcd_read_wake(&intel_dp->aux,
> +					DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&
> +					((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> +							DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD))) {

The DP_EDP_BACKLIGHT_MODE_SET_REGISTER is a read/write register for
configuration. You can also *set* the control method. Apparently this
now trusts the BIOS to have written the right value here. I am not sure
this is the right way to go.

How about checking that aux control is possible *and* pwm control is not
possible, and then setting the mode accordingly?

Also, the power-on default for the mode is
DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET, which means a power cycle will fix
the brightness to a preset level and the brightness adjustment will
cease to work. Did you test this? I think you should write the mode in
backlight enable.

> +
> +		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
> +
> +		return true;
> +	}
> +	return false;
> +}
> +
> +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
> +{
> +	struct intel_panel *panel = &intel_connector->panel;
> +
> +	if (!intel_dp_aux_display_control_capable(intel_connector))
> +		return -ENODEV;
> +
> +	panel->backlight.setup = intel_dp_aux_setup_backlight;
> +	panel->backlight.enable = intel_dp_aux_enable_backlight;
> +	panel->backlight.disable = intel_dp_aux_disable_backlight;
> +	panel->backlight.set = intel_dp_aux_set_backlight;
> +	panel->backlight.get = intel_dp_aux_get_backlight;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ad17288..095df8d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -758,6 +758,7 @@ struct intel_dp {
>  	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>  	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>  	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> +	uint8_t dpcd_edp[EDP_DISPLAY_CTL_CAP_SIZE];
>  	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
>  	uint8_t num_sink_rates;
>  	int sink_rates[DP_MAX_SUPPORTED_RATES];
> @@ -1279,6 +1280,11 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
>  bool
>  intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
> +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
> +		void *buffer, size_t size);
> +
> +/* intel_dp_aux_backlight.c */
> +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
>  
>  /* intel_dp_mst.c */
>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index a24df35..7da49b5 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1744,6 +1744,10 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
>  	struct drm_device *dev = intel_connector->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> +	if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
> +			intel_dp_aux_init_backlight_funcs(intel_connector) == 0)
> +		return;
> +
>  	if (IS_BROXTON(dev)) {
>  		panel->backlight.setup = bxt_setup_backlight;
>  		panel->backlight.enable = bxt_enable_backlight;
Yetunde Adebisi Dec. 10, 2015, 11:13 a.m. UTC | #2
Hi Jani,

I have a question below.

> -----Original Message-----

> From: Nikula, Jani

> Sent: Friday, November 20, 2015 3:04 PM

> To: Adebisi, YetundeX; intel-gfx@lists.freedesktop.org

> Cc: Adebisi, YetundeX; Paauwe, Bob J

> Subject: Re: [PATCH] drm/i915: Add Backlight Control using DPCD for eDP

> connectors (v3)

> 

> On Mon, 16 Nov 2015, Yetunde Adebisi <yetundex.adebisi@intel.com>

> wrote:

> > This patch adds support for eDP backlight control using DPCD registers to

> > backlight hooks in intel_panel.

> >

> > It checks for backlight control over AUX channel capability and sets up

> > function pointers to get and set the backlight brightness level if

> > supported.

> >

> > v2: Moved backlight functions from intel_dp.c into a new file

> > intel_dp_aux_backlight.c. Also moved reading of eDP display control

> > registers to intel_dp_get_dpcd

> >

> > v3: Correct some formatting mistakes

> >

> > This patch depends on http://patchwork.freedesktop.org/patch/64253/

> >

> > Cc: Bob Paauwe <bob.j.paauwe@intel.com>

> > Cc: Jani Nikula <jani.nikula@intel.com>

> > Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

> > Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>

> > ---

> >  drivers/gpu/drm/i915/Makefile                 |   1 +

> >  drivers/gpu/drm/i915/intel_dp.c               |  16 ++-

> >  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 177

> ++++++++++++++++++++++++++

> >  drivers/gpu/drm/i915/intel_drv.h              |   6 +

> >  drivers/gpu/drm/i915/intel_panel.c            |   4 +

> >  5 files changed, 198 insertions(+), 6 deletions(-)

> >  create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

> >

> > diff --git a/drivers/gpu/drm/i915/Makefile

> b/drivers/gpu/drm/i915/Makefile

> > index 0851de07..7a1db3d 100644

> > --- a/drivers/gpu/drm/i915/Makefile

> > +++ b/drivers/gpu/drm/i915/Makefile

> > @@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \

> >  	  dvo_tfp410.o \

> >  	  intel_crt.o \

> >  	  intel_ddi.o \

> > +	  intel_dp_aux_backlight.o\

> 

> Space before \ please.

> 

> >  	  intel_dp_link_training.o \

> >  	  intel_dp_mst.o \

> >  	  intel_dp.o \

> > diff --git a/drivers/gpu/drm/i915/intel_dp.c

> b/drivers/gpu/drm/i915/intel_dp.c

> > index 8071247..22e0241 100644

> > --- a/drivers/gpu/drm/i915/intel_dp.c

> > +++ b/drivers/gpu/drm/i915/intel_dp.c

> > @@ -3156,7 +3156,7 @@ static void chv_dp_post_pll_disable(struct

> intel_encoder *encoder)

> >   * Sinks are *supposed* to come up within 1ms from an off state, but

> we're also

> >   * supposed to retry 3 times per the spec.

> >   */

> > -static ssize_t

> > +ssize_t

> >  intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,

> >  			void *buffer, size_t size)

> >  {

> > @@ -3823,7 +3823,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)

> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

> >  	struct drm_device *dev = dig_port->base.base.dev;

> >  	struct drm_i915_private *dev_priv = dev->dev_private;

> > -	uint8_t rev;

> >

> >  	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp-

> >dpcd,

> >  				    sizeof(intel_dp->dpcd)) < 0)

> > @@ -3859,6 +3858,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)

> >  			DRM_DEBUG_KMS("PSR2 %s on sink",

> >  				dev_priv->psr.psr2_support ? "supported" :

> "not supported");

> >  		}

> > +

> > +		/* Read the eDP Display control capabilities registers */

> 

> You need to clear intel_dp->dpcd_edp here.

> 

> > +		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &

> DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&

> > +				(intel_dp_dpcd_read_wake(&intel_dp->aux,

> DP_EDP_DPCD_REV,

> > +						intel_dp->dpcd_edp,

> sizeof(intel_dp->dpcd_edp)) ==

> > +

> 	sizeof(intel_dp->dpcd_edp)))

> > +			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int)

> sizeof(intel_dp->dpcd_edp),

> > +					intel_dp->dpcd_edp);

> >  	}

> >

> >  	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink

> %s\n",

> > @@ -3866,10 +3873,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)

> >  		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));

> >

> >  	/* Intermediate frequency support */

> > -	if (is_edp(intel_dp) &&

> > -	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &

> 	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&

> > -	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,

> &rev, 1) == 1) &&

> > -	    (rev >= 0x03)) { /* eDp v1.4 or higher */

> > +	if (is_edp(intel_dp) && (intel_dp->dpcd_edp[0] >= 0x03)) { /* eDp

> v1.4 or higher */

> >  		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];

> >  		int i;

> >

> > diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c

> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c

> > new file mode 100644

> > index 0000000..190c5d9

> > --- /dev/null

> > +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c

> > @@ -0,0 +1,177 @@

> > +/*

> > + * Copyright © 2015 Intel Corporation

> > + *

> > + * Permission is hereby granted, free of charge, to any person obtaining a

> > + * copy of this software and associated documentation files (the

> "Software"),

> > + * to deal in the Software without restriction, including without limitation

> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,

> > + * and/or sell copies of the Software, and to permit persons to whom the

> > + * Software is furnished to do so, subject to the following conditions:

> > + *

> > + * The above copyright notice and this permission notice (including the

> next

> > + * paragraph) shall be included in all copies or substantial portions of the

> > + * Software.

> > + *

> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY

> KIND, EXPRESS OR

> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

> MERCHANTABILITY,

> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN

> NO EVENT SHALL

> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,

> DAMAGES OR OTHER

> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR

> OTHERWISE, ARISING

> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE

> OR OTHER DEALINGS

> > + * IN THE SOFTWARE.

> > + *

> > + */

> > +

> > +#include "intel_drv.h"

> > +

> > +static bool is_aux_backlight_enabled(struct drm_dp_aux *aux)

> > +{

> > +	uint8_t read_val = 0;

> > +

> > +	if (intel_dp_dpcd_read_wake(aux,

> DP_EDP_DISPLAY_CONTROL_REGISTER,

> > +			&read_val, sizeof(read_val)) < 0)

> > +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",

> > +				DP_EDP_DISPLAY_CONTROL_REGISTER);

> > +

> > +	return read_val & DP_EDP_BACKLIGHT_ENABLE;

> > +}

> > +

> > +static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool

> enable)

> > +{

> > +	uint8_t reg_val = 0;

> > +

> > +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,

> > +				DP_EDP_DISPLAY_CONTROL_REGISTER,

> > +				&reg_val, sizeof(reg_val)) < 0) {

> > +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",

> > +				DP_EDP_DISPLAY_CONTROL_REGISTER);

> > +		return;

> > +	}

> > +	if (enable)

> > +		reg_val |= DP_EDP_BACKLIGHT_ENABLE;

> > +	else

> > +		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);

> > +

> > +	if (drm_dp_dpcd_writeb(&intel_dp->aux,

> DP_EDP_DISPLAY_CONTROL_REGISTER,

> > +			reg_val) < 0) {

> > +		DRM_DEBUG_KMS("Failed to %s aux backlight\n",

> > +				enable ? "enable" : "disable");

> > +	}

> > +}

> > +

> > +/*

> > + * Read the current backlight value from DPCD register(s) based

> > + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported

> > + */

> > +static uint32_t intel_dp_aux_get_backlight(struct intel_connector

> *connector)

> > +{

> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-

> >base);

> > +	uint8_t read_val[2] = { 0x0 };

> > +	uint16_t level = 0;

> > +

> > +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,

> > +			DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,

> > +			&read_val, sizeof(read_val)) < 0) {

> > +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",

> > +				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);

> > +		return 0;

> > +	}

> > +	level = read_val[0];

> > +	if (intel_dp->dpcd_edp[2] &

> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)

> > +		level = (read_val[0] << 8 | read_val[1]);

> > +

> > +	return level;

> > +}

> > +

> > +/*

> > + * Sends the current backlight level over the aux channel, checking if its

> using

> > + * 8-bit or 16 bit value (MSB and LSB)

> > + */

> > +static void

> > +intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)

> > +{

> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-

> >base);

> > +	uint8_t vals[2] = { 0x0 };

> > +

> > +	DRM_DEBUG_KMS("Level 0x%x\n", level);

> 

> The caller of the hook does debug logging already.

> 

> > +	vals[0] = level;

> > +

> > +	/* Write the MSB and/or LSB */

> > +	 if (intel_dp->dpcd_edp[2] &

> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {

> > +		vals[0] = (level & 0xFF00) >> 8;

> > +		vals[1] = (level & 0xFF);

> > +	}

> > +	if (drm_dp_dpcd_write(&intel_dp->aux,

> DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,

> > +			vals, sizeof(vals)) < 0) {

> > +		DRM_DEBUG_KMS("Failed to write aux backlight level\n");

> > +		return;

> > +	}

> > +}

> > +

> > +static void intel_dp_aux_enable_backlight(struct intel_connector

> *connector)

> > +{

> > +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder-

> >base), true);

> > +}

> > +

> > +static void intel_dp_aux_disable_backlight(struct intel_connector

> *connector)

> > +{

> > +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder-

> >base), false);

> > +}

> > +

> > +static int intel_dp_aux_setup_backlight(struct intel_connector

> *connector,

> > +			enum pipe pipe)

> > +{

> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-

> >base);

> > +	struct intel_panel *panel = &connector->panel;

> > +

> > +	if (intel_dp->dpcd_edp[2] &

> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)

> > +		panel->backlight.max = 0xFFFF;

> > +	else

> > +		panel->backlight.max = 0xFF;

> > +

> > +	panel->backlight.min = 0;

> > +

> > +	panel->backlight.level = intel_dp_aux_get_backlight(connector);

> > +	panel->backlight.enabled = is_aux_backlight_enabled(&intel_dp-

> >aux);

> > +

> > +	return 0;

> > +}

> > +

> > +static bool intel_dp_aux_display_control_capable(struct intel_connector

> *connector)

> > +{

> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-

> >base);

> > +	uint8_t dpcd_buf = 0;

> > +

> > +	/* Check the  eDP Display control capabilities registers to determine if

> > +	 * the panel can support backlight control over the aux channel*/

> > +

> > +	if (intel_dp->dpcd_edp[1] &

> DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&

> > +			(intel_dp->dpcd_edp[1] &

> DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&

> > +			(intel_dp->dpcd_edp[2] &

> DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&

> > +			((intel_dp_dpcd_read_wake(&intel_dp->aux,

> > +

> 	DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&

> > +					((dpcd_buf &

> DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==

> > +

> 	DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD))) {

> 

> The DP_EDP_BACKLIGHT_MODE_SET_REGISTER is a read/write register for

> configuration. You can also *set* the control method. Apparently this

> now trusts the BIOS to have written the right value here. I am not sure

> this is the right way to go.

> 

> How about checking that aux control is possible *and* pwm control is not

> possible, and then setting the mode accordingly?

> 

> Also, the power-on default for the mode is

> DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET, which means a power cycle

> will fix

> the brightness to a preset level and the brightness adjustment will

> cease to work. Did you test this? I think you should write the mode in

> backlight enable.


I am not sure what you mean by writing the mode in backlight enable. 
The panel I am testing with doesn’t  have the mode set to CONTROL_MODE_PRESET after a power cycle.

I have changed the code to look like this, is this what you mean?

static bool intel_dp_aux_display_control_capable(struct intel_connector *connector)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
	uint8_t dpcd_buf = 0;

	/* Check the  eDP Display control capabilities registers to determine if
	 * the panel can support backlight control over the aux channel*/

	if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
			(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
			!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP) &&
			(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) ) {

		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
		set_aux_backlight_enable(intel_dp, true);
		if ((intel_dp_dpcd_read_wake(&intel_dp->aux,
			DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&
			((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
					DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET))
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
				(dpcd_buf | DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD));

		return true;
	}
	return false;
}


> 

> > +

> > +		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");

> > +

> > +		return true;

> > +	}

> > +	return false;

> > +}

> > +

> > +int intel_dp_aux_init_backlight_funcs(struct intel_connector

> *intel_connector)

> > +{

> > +	struct intel_panel *panel = &intel_connector->panel;

> > +

> > +	if (!intel_dp_aux_display_control_capable(intel_connector))

> > +		return -ENODEV;

> > +

> > +	panel->backlight.setup = intel_dp_aux_setup_backlight;

> > +	panel->backlight.enable = intel_dp_aux_enable_backlight;

> > +	panel->backlight.disable = intel_dp_aux_disable_backlight;

> > +	panel->backlight.set = intel_dp_aux_set_backlight;

> > +	panel->backlight.get = intel_dp_aux_get_backlight;

> > +

> > +	return 0;

> > +}

> > diff --git a/drivers/gpu/drm/i915/intel_drv.h

> b/drivers/gpu/drm/i915/intel_drv.h

> > index ad17288..095df8d 100644

> > --- a/drivers/gpu/drm/i915/intel_drv.h

> > +++ b/drivers/gpu/drm/i915/intel_drv.h

> > @@ -758,6 +758,7 @@ struct intel_dp {

> >  	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];

> >  	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

> >  	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

> > +	uint8_t dpcd_edp[EDP_DISPLAY_CTL_CAP_SIZE];

> >  	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */

> >  	uint8_t num_sink_rates;

> >  	int sink_rates[DP_MAX_SUPPORTED_RATES];

> > @@ -1279,6 +1280,11 @@ void intel_dp_compute_rate(struct intel_dp

> *intel_dp, int port_clock,

> >  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);

> >  bool

> >  intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t

> link_status[DP_LINK_STATUS_SIZE]);

> > +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int

> offset,

> > +		void *buffer, size_t size);

> > +

> > +/* intel_dp_aux_backlight.c */

> > +int intel_dp_aux_init_backlight_funcs(struct intel_connector

> *intel_connector);

> >

> >  /* intel_dp_mst.c */

> >  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int

> conn_id);

> > diff --git a/drivers/gpu/drm/i915/intel_panel.c

> b/drivers/gpu/drm/i915/intel_panel.c

> > index a24df35..7da49b5 100644

> > --- a/drivers/gpu/drm/i915/intel_panel.c

> > +++ b/drivers/gpu/drm/i915/intel_panel.c

> > @@ -1744,6 +1744,10 @@ intel_panel_init_backlight_funcs(struct

> intel_panel *panel)

> >  	struct drm_device *dev = intel_connector->base.dev;

> >  	struct drm_i915_private *dev_priv = dev->dev_private;

> >

> > +	if (intel_connector->base.connector_type ==

> DRM_MODE_CONNECTOR_eDP &&

> > +			intel_dp_aux_init_backlight_funcs(intel_connector)

> == 0)

> > +		return;

> > +

> >  	if (IS_BROXTON(dev)) {

> >  		panel->backlight.setup = bxt_setup_backlight;

> >  		panel->backlight.enable = bxt_enable_backlight;

> 

> --

> Jani Nikula, Intel Open Source Technology Center
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..7a1db3d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@  i915-y += dvo_ch7017.o \
 	  dvo_tfp410.o \
 	  intel_crt.o \
 	  intel_ddi.o \
+	  intel_dp_aux_backlight.o\
 	  intel_dp_link_training.o \
 	  intel_dp_mst.o \
 	  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8071247..22e0241 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3156,7 +3156,7 @@  static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
 			void *buffer, size_t size)
 {
@@ -3823,7 +3823,6 @@  intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint8_t rev;
 
 	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
 				    sizeof(intel_dp->dpcd)) < 0)
@@ -3859,6 +3858,14 @@  intel_dp_get_dpcd(struct intel_dp *intel_dp)
 			DRM_DEBUG_KMS("PSR2 %s on sink",
 				dev_priv->psr.psr2_support ? "supported" : "not supported");
 		}
+
+		/* Read the eDP Display control capabilities registers */
+		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+				(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
+						intel_dp->dpcd_edp, sizeof(intel_dp->dpcd_edp)) ==
+								sizeof(intel_dp->dpcd_edp)))
+			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->dpcd_edp),
+					intel_dp->dpcd_edp);
 	}
 
 	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3866,10 +3873,7 @@  intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
 	/* Intermediate frequency support */
-	if (is_edp(intel_dp) &&
-	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
-	    (rev >= 0x03)) { /* eDp v1.4 or higher */
+	if (is_edp(intel_dp) && (intel_dp->dpcd_edp[0] >= 0x03)) { /* eDp v1.4 or higher */
 		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 		int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 0000000..190c5d9
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,177 @@ 
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+static bool is_aux_backlight_enabled(struct drm_dp_aux *aux)
+{
+	uint8_t read_val = 0;
+
+	if (intel_dp_dpcd_read_wake(aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			&read_val, sizeof(read_val)) < 0)
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				DP_EDP_DISPLAY_CONTROL_REGISTER);
+
+	return read_val & DP_EDP_BACKLIGHT_ENABLE;
+}
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+	uint8_t reg_val = 0;
+
+	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
+				DP_EDP_DISPLAY_CONTROL_REGISTER,
+				&reg_val, sizeof(reg_val)) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				DP_EDP_DISPLAY_CONTROL_REGISTER);
+		return;
+	}
+	if (enable)
+		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+	else
+		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			reg_val) < 0) {
+		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
+				enable ? "enable" : "disable");
+	}
+}
+
+/*
+ * Read the current backlight value from DPCD register(s) based
+ * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
+ */
+static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t read_val[2] = { 0x0 };
+	uint16_t level = 0;
+
+	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
+			DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			&read_val, sizeof(read_val)) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+		return 0;
+	}
+	level = read_val[0];
+	if (intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		level = (read_val[0] << 8 | read_val[1]);
+
+	return level;
+}
+
+/*
+ * Sends the current backlight level over the aux channel, checking if its using
+ * 8-bit or 16 bit value (MSB and LSB)
+ */
+static void
+intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t vals[2] = { 0x0 };
+
+	DRM_DEBUG_KMS("Level 0x%x\n", level);
+	vals[0] = level;
+
+	/* Write the MSB and/or LSB */
+	 if (intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+		vals[0] = (level & 0xFF00) >> 8;
+		vals[1] = (level & 0xFF);
+	}
+	if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			vals, sizeof(vals)) < 0) {
+		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
+		return;
+	}
+}
+
+static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
+{
+	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), true);
+}
+
+static void intel_dp_aux_disable_backlight(struct intel_connector *connector)
+{
+	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), false);
+}
+
+static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
+			enum pipe pipe)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	struct intel_panel *panel = &connector->panel;
+
+	if (intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		panel->backlight.max = 0xFFFF;
+	else
+		panel->backlight.max = 0xFF;
+
+	panel->backlight.min = 0;
+
+	panel->backlight.level = intel_dp_aux_get_backlight(connector);
+	panel->backlight.enabled = is_aux_backlight_enabled(&intel_dp->aux);
+
+	return 0;
+}
+
+static bool intel_dp_aux_display_control_capable(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t dpcd_buf = 0;
+
+	/* Check the  eDP Display control capabilities registers to determine if
+	 * the panel can support backlight control over the aux channel*/
+
+	if (intel_dp->dpcd_edp[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
+			(intel_dp->dpcd_edp[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+			(intel_dp->dpcd_edp[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
+			((intel_dp_dpcd_read_wake(&intel_dp->aux,
+					DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&
+					((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
+							DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD))) {
+
+		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
+
+		return true;
+	}
+	return false;
+}
+
+int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
+{
+	struct intel_panel *panel = &intel_connector->panel;
+
+	if (!intel_dp_aux_display_control_capable(intel_connector))
+		return -ENODEV;
+
+	panel->backlight.setup = intel_dp_aux_setup_backlight;
+	panel->backlight.enable = intel_dp_aux_enable_backlight;
+	panel->backlight.disable = intel_dp_aux_disable_backlight;
+	panel->backlight.set = intel_dp_aux_set_backlight;
+	panel->backlight.get = intel_dp_aux_get_backlight;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ad17288..095df8d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -758,6 +758,7 @@  struct intel_dp {
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+	uint8_t dpcd_edp[EDP_DISPLAY_CTL_CAP_SIZE];
 	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 	uint8_t num_sink_rates;
 	int sink_rates[DP_MAX_SUPPORTED_RATES];
@@ -1279,6 +1280,11 @@  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
 bool
 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
+ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
+		void *buffer, size_t size);
+
+/* intel_dp_aux_backlight.c */
+int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index a24df35..7da49b5 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1744,6 +1744,10 @@  intel_panel_init_backlight_funcs(struct intel_panel *panel)
 	struct drm_device *dev = intel_connector->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
+			intel_dp_aux_init_backlight_funcs(intel_connector) == 0)
+		return;
+
 	if (IS_BROXTON(dev)) {
 		panel->backlight.setup = bxt_setup_backlight;
 		panel->backlight.enable = bxt_enable_backlight;