| Message ID | 1449789132-18976-1-git-send-email-Frank.Li@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 2015-12-10 15:12, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > add cortex a7 arch timer. > uboot v2016.01-rc2 supported psci basic support. > smp can be supported by psci This sounds a bit overly simplified log message. I am not very into this PSCI topic, is this a prerequisit for the ARM arch timers? Maybe you could elaborate that a bit more. Also, I would prefer full sentences and commonly used spellings such as Cortex-A7, U-Boot etc... -- Stefan > > Signed-off-by: Frank Li <Frank.Li@freescale.com> > --- > arch/arm/boot/dts/imx7d.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi > index 489604a..a621af6 100644 > --- a/arch/arm/boot/dts/imx7d.dtsi > +++ b/arch/arm/boot/dts/imx7d.dtsi > @@ -119,6 +119,15 @@ > clock-output-names = "osc"; > }; > > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + interrupt-parent = <&intc>; > + }; > + > etr@30086000 { > compatible = "arm,coresight-tmc", "arm,primecell"; > reg = <0x30086000 0x1000>;
On Thu, Dec 17, 2015 at 2:45 PM, Stefan Agner <stefan@agner.ch> wrote: > On 2015-12-10 15:12, Frank.Li@freescale.com wrote: >> From: Frank Li <Frank.Li@freescale.com> >> >> add cortex a7 arch timer. >> uboot v2016.01-rc2 supported psci basic support. >> smp can be supported by psci > > This sounds a bit overly simplified log message. I am not very into this > PSCI topic, is this a prerequisit for the ARM arch timers? Maybe you > could elaborate that a bit more. No. But according to previous discussion. Shawn want us to use psci to enable second core. We need enable arch timer if second core enabled. > > Also, I would prefer full sentences and commonly used spellings such as > Cortex-A7, U-Boot etc... > > -- > Stefan > >> >> Signed-off-by: Frank Li <Frank.Li@freescale.com> >> --- >> arch/arm/boot/dts/imx7d.dtsi | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi >> index 489604a..a621af6 100644 >> --- a/arch/arm/boot/dts/imx7d.dtsi >> +++ b/arch/arm/boot/dts/imx7d.dtsi >> @@ -119,6 +119,15 @@ >> clock-output-names = "osc"; >> }; >> >> + timer { >> + compatible = "arm,armv7-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; >> + interrupt-parent = <&intc>; >> + }; >> + >> etr@30086000 { >> compatible = "arm,coresight-tmc", "arm,primecell"; >> reg = <0x30086000 0x1000>;
On Thu, Dec 17, 2015 at 03:23:59PM -0600, Zhi Li wrote: > On Thu, Dec 17, 2015 at 2:45 PM, Stefan Agner <stefan@agner.ch> wrote: > > On 2015-12-10 15:12, Frank.Li@freescale.com wrote: > >> From: Frank Li <Frank.Li@freescale.com> > >> > >> add cortex a7 arch timer. > >> uboot v2016.01-rc2 supported psci basic support. > >> smp can be supported by psci > > > > This sounds a bit overly simplified log message. I am not very into this > > PSCI topic, is this a prerequisit for the ARM arch timers? Maybe you > > could elaborate that a bit more. > > No. > But according to previous discussion. Shawn want us to use psci to enable > second core. We need enable arch timer if second core enabled. I guess you can make the commit log a bit better by commenting the relationship between the arch timer and secondary core. Shawn
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 489604a..a621af6 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -119,6 +119,15 @@ clock-output-names = "osc"; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&intc>; + }; + etr@30086000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x30086000 0x1000>;