| Message ID | 1454203266-4450-5-git-send-email-vishnupatekar0510@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote: > AHB1 on A83T is similar to ahb1 on A31, except parents are different. > clock index 0b1x is PLL6. > > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + Acked-by: Rob Herring <robh@kernel.org> > drivers/clk/sunxi/clk-sunxi.c | 75 +++++++++++++++++++++++ > 2 files changed, 76 insertions(+)
On Mon, Feb 1, 2016 at 10:49 PM, Rob Herring <robh@kernel.org> wrote: > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote: >> AHB1 on A83T is similar to ahb1 on A31, except parents are different. >> clock index 0b1x is PLL6. >> >> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> >> --- >> Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > > Acked-by: Rob Herring <robh@kernel.org> > >> drivers/clk/sunxi/clk-sunxi.c | 75 +++++++++++++++++++++++ >> 2 files changed, 76 insertions(+) Acked-by: Chen-Yu Tsai <wens@csie.org>
Hi, On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote: > AHB1 on A83T is similar to ahb1 on A31, except parents are different. > clock index 0b1x is PLL6. > > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> If the clock is the same but the parents are different, then we don't need to duplicate all the logic. Simply add the number of parents to mux_data, and you're all set. Maxime
Hello Maxime, On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi, > > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote: >> AHB1 on A83T is similar to ahb1 on A31, except parents are different. >> clock index 0b1x is PLL6. >> >> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > > If the clock is the same but the parents are different, then we don't > need to duplicate all the logic. Simply add the number of parents to > mux_data, and you're all set. Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div. 0b10 and 0b11 is pll6/pre_div. So, just adding number of parents to mux_data will not solve problem. Regards, Vishnu > > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com
On Thu, Feb 04, 2016 at 02:06:45PM +0800, Vishnu Patekar wrote: > Hello Maxime, > > > On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > Hi, > > > > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote: > >> AHB1 on A83T is similar to ahb1 on A31, except parents are different. > >> clock index 0b1x is PLL6. > >> > >> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > > > > If the clock is the same but the parents are different, then we don't > > need to duplicate all the logic. Simply add the number of parents to > > mux_data, and you're all set. > > Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div. > 0b10 and 0b11 is pll6/pre_div. > So, just adding number of parents to mux_data will not solve problem. Is anyone using 0b11 ? Can't we just ignore it? Maxime
Hello Maxime, On Thu, Feb 4, 2016 at 4:01 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Thu, Feb 04, 2016 at 02:06:45PM +0800, Vishnu Patekar wrote: >> Hello Maxime, >> >> >> On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard >> <maxime.ripard@free-electrons.com> wrote: >> > Hi, >> > >> > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote: >> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different. >> >> clock index 0b1x is PLL6. >> >> >> >> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> >> > >> > If the clock is the same but the parents are different, then we don't >> > need to duplicate all the logic. Simply add the number of parents to >> > mux_data, and you're all set. >> >> Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div. >> 0b10 and 0b11 is pll6/pre_div. >> So, just adding number of parents to mux_data will not solve problem. > > Is anyone using 0b11 ? Can't we just ignore it? Yes, it's used, 0b11 is pll6 parent in case of A31. > > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 4514d77..bfd82f1 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -29,6 +29,7 @@ Required properties: "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index e460a6b..02bbdf6 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req) req->rate >>= req->p; } + +#define SUN8I_A83T_AHB1_PARENT_PLL6 2 +/** + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB + * AHB rate is calculated as follows + * rate = parent_rate >> p + * + * if parent is pll6, then + * parent_rate = pll6 rate / (m + 1) + */ + +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req) +{ + u8 div, calcp, calcm = 1; + + /* + * clock can only divide, so we will never be able to achieve + * frequencies higher than the parent frequency + */ + if (req->parent_rate && req->rate > req->parent_rate) + req->rate = req->parent_rate; + + div = DIV_ROUND_UP(req->parent_rate, req->rate); + + /* calculate pre-divider if parent is pll6 */ + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) { + if (div < 4) + calcp = 0; + else if (div / 2 < 4) + calcp = 1; + else if (div / 4 < 4) + calcp = 2; + else + calcp = 3; + + calcm = DIV_ROUND_UP(div, 1 << calcp); + } else { + calcp = __roundup_pow_of_two(div); + calcp = calcp > 3 ? 3 : calcp; + } + + req->rate = (req->parent_rate / calcm) >> calcp; + req->p = calcp; + req->m = calcm - 1; +} + +/** + * sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and + * parent index + */ +static void sun8i_a83t_ahb1_recalc(struct factors_request *req) +{ + req->rate = req->parent_rate; + + /* apply pre-divider first if parent is pll6 */ + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6) + req->rate /= req->m + 1; + + /* clk divider */ + req->rate >>= req->p; +} /** * sun4i_get_apb1_factors() - calculates m, p factors for APB1 * APB1 rate is calculated as follows @@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data __initconst = { .recalc = sun6i_ahb1_recalc, }; +static const struct factors_data sun8i_a83t_ahb1_data __initconst = { + .mux = 12, + .muxmask = BIT(1) | BIT(0), + .table = &sun6i_ahb1_config, + .getter = sun8i_a83t_get_ahb1_factors, + .recalc = sun8i_a83t_ahb1_recalc, +}; + static const struct factors_data sun4i_apb1_data __initconst = { .mux = 24, .muxmask = BIT(1) | BIT(0), @@ -592,6 +661,12 @@ static void __init sun6i_ahb1_clk_setup(struct device_node *node) CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup); +static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node) +{ + sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data); +} +CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk", + sun8i_a83t_ahb1_clk_setup); /** * sunxi_mux_clk_setup() - Setup function for muxes
AHB1 on A83T is similar to ahb1 on A31, except parents are different. clock index 0b1x is PLL6. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 75 +++++++++++++++++++++++ 2 files changed, 76 insertions(+)