| Message ID | 1454448113-18810-3-git-send-email-k@japko.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote: > APB0 is bearly mentioned in H3 User Manual and it is only setup in the > Allwinners kernel dump for CIR. I have verified experimentally that the > gate for R_PIO exists and works, though. There are probably other gates > there but I don't know their order right now and I don't have access to > their peripherals on my board to test them. > > Signed-off-by: Krzysztof Adamski <k@japko.eu> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > index 1524130e..ce35e93 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -276,6 +276,32 @@ > clocks = <&osc24M>, <&pll6 1>, <&pll5>; > clock-output-names = "mbus"; > }; > + > + ahb0: ahb0_clk { > + compatible = "fixed-factor-clock"; > + #clock-cells = <0>; > + clock-div = <1>; > + clock-mult = <1>; > + clocks = <&osc24M>, <&osc32k>; > + clock-output-names = "ahb0"; > + }; I'm not sure what you mean there. The fixed factor clocks only take a single parent, and you provided two. Maxime
On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote: >Hi, > >On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote: >> APB0 is bearly mentioned in H3 User Manual and it is only setup in the >> Allwinners kernel dump for CIR. I have verified experimentally that the >> gate for R_PIO exists and works, though. There are probably other gates >> there but I don't know their order right now and I don't have access to >> their peripherals on my board to test them. >> >> Signed-off-by: Krzysztof Adamski <k@japko.eu> >> --- >> arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >> index 1524130e..ce35e93 100644 >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -276,6 +276,32 @@ >> clocks = <&osc24M>, <&pll6 1>, <&pll5>; >> clock-output-names = "mbus"; >> }; >> + >> + ahb0: ahb0_clk { >> + compatible = "fixed-factor-clock"; >> + #clock-cells = <0>; >> + clock-div = <1>; >> + clock-mult = <1>; >> + clocks = <&osc24M>, <&osc32k>; >> + clock-output-names = "ahb0"; >> + }; > >I'm not sure what you mean there. The fixed factor clocks only take a >single parent, and you provided two. True, I that's actually some stupid leftover. As mentioned in the commit message I didn't really know how the clock tree looks like here so I wanted to just pretend it's connectet to osc24M. After some experiments I think that 0x01f0140c register does not exist on H3 and I was finally (hopefully) able to understand how this clock is set up in Allwinner's code. So I changed the clock to factors clock with possible osc32k and osc24M parrents. Will send it in v3.
On Wed, Feb 03, 2016 at 11:21:17PM +0100, Krzysztof Adamski wrote: >On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote: >>Hi, >> >>I'm not sure what you mean there. The fixed factor clocks only take a >>single parent, and you provided two. > >True, I that's actually some stupid leftover. As mentioned in the >commit message I didn't really know how the clock tree looks like here >so I wanted to just pretend it's connectet to osc24M. After some >experiments I think that 0x01f0140c register does not exist on H3 and >I was finally (hopefully) able to understand how this clock is set up >in Allwinner's code. So I changed the clock to factors clock with >possible osc32k and osc24M parrents. Will send it in v3. I've changed my mind about using factors clock. The clock I was thinking about is only setup for CIR peripheral and I have no information on how r_pio is clocked other than the fact it works by default so I assume it's clocked from 24M oscillator. New patchset send, let me know what you think.
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 1524130e..ce35e93 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -276,6 +276,32 @@ clocks = <&osc24M>, <&pll6 1>, <&pll5>; clock-output-names = "mbus"; }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>, <&osc32k>; + clock-output-names = "ahb0"; + }; + + apb0: clk@01f0140c { + compatible = "allwinner,sun8i-a23-apb0-clk"; + reg = <0x01f0140c 0x4>; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: clk@01f01428 { + compatible = "allwinner,sun8i-h3-abp0-gates-clk"; + reg = <0x01f01428 0x4>; + #clock-cells = <1>; + clocks = <&apb0>; + clock-indices = <0>, <1>; + clock-output-names = "apb0_pio", "apb0_ir"; + }; }; soc { @@ -493,5 +519,11 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + + apb0_reset: reset@01f014b0 { + reg = <0x01f014b0 0x4>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; }; };
APB0 is bearly mentioned in H3 User Manual and it is only setup in the Allwinners kernel dump for CIR. I have verified experimentally that the gate for R_PIO exists and works, though. There are probably other gates there but I don't know their order right now and I don't have access to their peripherals on my board to test them. Signed-off-by: Krzysztof Adamski <k@japko.eu> --- arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)