| Message ID | 1454448113-18810-6-git-send-email-k@japko.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On Wed, Feb 3, 2016 at 5:21 AM, Krzysztof Adamski <k@japko.eu> wrote: > sunxi_pmx_set accepts pin number and then calculates offset by > subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, > gets offset so we have to convert it to pin number so we won't get > negative value in sunxi_pmx_set. > > This was only used on A10 so far, where there is only one GPIO chip with > pin_base set to 0 so it didn't matter. However H3 also requires this > workaround but have two pinmux sections, triggering problem for PL port. > > Signed-off-by: Krzysztof Adamski <k@japko.eu> > --- > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > index 7a2465f..9e5bac9 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -460,14 +460,17 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) > u32 set_mux = pctl->desc->irq_read_needs_mux && > test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags); > u32 val; > + u32 pin; > > - if (set_mux) > - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT); > + if (set_mux) { > + pin = offset + pctl->desc->pin_base; You can use chip->base directly. It's value is set to pin_base in the init function. You could also move this out of the if block, and not add the braces. Otherwise this looks good. ChenYu > + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); > + } > > val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; > > if (set_mux) > - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ); > + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); > > return !!val; > } > -- > 2.1.4 >
On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: > sunxi_pmx_set accepts pin number and then calculates offset by > subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, > gets offset so we have to convert it to pin number so we won't get > negative value in sunxi_pmx_set. > > This was only used on A10 so far, where there is only one GPIO chip with > pin_base set to 0 so it didn't matter. However H3 also requires this > workaround but have two pinmux sections, triggering problem for PL port. > > Signed-off-by: Krzysztof Adamski <k@japko.eu> Waiting for Maxime to review this. I guess this patch can be merged independently of the other patches? Yours, Linus Walleij
On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote: >On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: > >> sunxi_pmx_set accepts pin number and then calculates offset by >> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, >> gets offset so we have to convert it to pin number so we won't get >> negative value in sunxi_pmx_set. >> >> This was only used on A10 so far, where there is only one GPIO chip with >> pin_base set to 0 so it didn't matter. However H3 also requires this >> workaround but have two pinmux sections, triggering problem for PL port. >> >> Signed-off-by: Krzysztof Adamski <k@japko.eu> > >Waiting for Maxime to review this. I guess this patch can be merged >independently of the other patches? Yes it can but it won't have any effect, as stated in the commit message, since other SoCs either don't use this flag or have only one port so theri pin_base=0. Best regards, Krzysztof Adamski
Hi, On Thu, Feb 11, 2016 at 9:17 PM, Linus Walleij <linus.walleij@linaro.org> wrote: > On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: > >> sunxi_pmx_set accepts pin number and then calculates offset by >> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, >> gets offset so we have to convert it to pin number so we won't get >> negative value in sunxi_pmx_set. >> >> This was only used on A10 so far, where there is only one GPIO chip with >> pin_base set to 0 so it didn't matter. However H3 also requires this >> workaround but have two pinmux sections, triggering problem for PL port. >> >> Signed-off-by: Krzysztof Adamski <k@japko.eu> > > Waiting for Maxime to review this. I guess this patch can be merged > independently of the other patches? FYI there's a v4 of this patch that both Maxime and I acked. ChenYu
On Thu, Feb 11, 2016 at 2:20 PM, Krzysztof Adamski <k@japko.eu> wrote: > On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote: >> >> On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: >> >>> sunxi_pmx_set accepts pin number and then calculates offset by >>> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, >>> gets offset so we have to convert it to pin number so we won't get >>> negative value in sunxi_pmx_set. >>> >>> This was only used on A10 so far, where there is only one GPIO chip with >>> pin_base set to 0 so it didn't matter. However H3 also requires this >>> workaround but have two pinmux sections, triggering problem for PL port. >>> >>> Signed-off-by: Krzysztof Adamski <k@japko.eu> >> >> >> Waiting for Maxime to review this. I guess this patch can be merged >> independently of the other patches? > > Yes it can but it won't have any effect, as stated in the commit message, > since other SoCs either don't use this flag or have only one port so theri > pin_base=0. Who cares as long as it will be used eventually. Merged v4 as stated earlier. Yours, Linus Walleij
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 7a2465f..9e5bac9 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -460,14 +460,17 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) u32 set_mux = pctl->desc->irq_read_needs_mux && test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags); u32 val; + u32 pin; - if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT); + if (set_mux) { + pin = offset + pctl->desc->pin_base; + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); + } val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ); + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); return !!val; }
sunxi_pmx_set accepts pin number and then calculates offset by subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, gets offset so we have to convert it to pin number so we won't get negative value in sunxi_pmx_set. This was only used on A10 so far, where there is only one GPIO chip with pin_base set to 0 so it didn't matter. However H3 also requires this workaround but have two pinmux sections, triggering problem for PL port. Signed-off-by: Krzysztof Adamski <k@japko.eu> --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)