| Message ID | 1455772383-20598-1-git-send-email-k.kozlowski@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On 18-02-16, 14:13, Krzysztof Kozlowski wrote: > On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and > 12 steps for big core (700-1800 MHz). Add respective cooling cells. > > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > > --- > > Changes since v1: > 1. Add cooling properties to all CPUs (suggested by Viresh). > --- > arch/arm/boot/dts/exynos5420-cpus.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Hi Krzysztof, Krzysztof Kozlowski <k.kozlowski@samsung.com> writes: > On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and > 12 steps for big core (700-1800 MHz). Add respective cooling cells. > > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > > --- > > Changes since v1: > 1. Add cooling properties to all CPUs (suggested by Viresh). > --- > arch/arm/boot/dts/exynos5420-cpus.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi > index 261d25173f61..5c052d7ff554 100644 > --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi > +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi > @@ -33,6 +33,9 @@ > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > operating-points-v2 = <&cluster_a15_opp_table>; > + cooling-min-level = <0>; > + cooling-max-level = <11>; Although the above two properties are defined they aren't parsed in the kernel. Setting min / max extents for cooling devices via cooling maps does work though. [...] -- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 19.02.2016 02:58, Punit Agrawal wrote: > Hi Krzysztof, > > Krzysztof Kozlowski <k.kozlowski@samsung.com> writes: > >> On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and >> 12 steps for big core (700-1800 MHz). Add respective cooling cells. >> >> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> >> >> --- >> >> Changes since v1: >> 1. Add cooling properties to all CPUs (suggested by Viresh). >> --- >> arch/arm/boot/dts/exynos5420-cpus.dtsi | 24 ++++++++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi >> index 261d25173f61..5c052d7ff554 100644 >> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi >> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi >> @@ -33,6 +33,9 @@ >> clock-frequency = <1800000000>; >> cci-control-port = <&cci_control1>; >> operating-points-v2 = <&cluster_a15_opp_table>; >> + cooling-min-level = <0>; >> + cooling-max-level = <11>; > > Although the above two properties are defined they aren't parsed in the > kernel. > > Setting min / max extents for cooling devices via cooling maps does work > though. It is described as optional property in Documentation/devicetree/bindings/thermal/thermal.txt ... but indeed it is totally ignored. So what is the recommendation? Get rid of it from DTS and documentation or leave it because it will be implemented someday? Thanks for feedback! Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Krzysztof Kozlowski <k.kozlowski@samsung.com> writes: > On 19.02.2016 02:58, Punit Agrawal wrote: >> Hi Krzysztof, >> >> Krzysztof Kozlowski <k.kozlowski@samsung.com> writes: >> >>> On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and >>> 12 steps for big core (700-1800 MHz). Add respective cooling cells. >>> >>> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> >>> >>> --- >>> >>> Changes since v1: >>> 1. Add cooling properties to all CPUs (suggested by Viresh). >>> --- >>> arch/arm/boot/dts/exynos5420-cpus.dtsi | 24 ++++++++++++++++++++++++ >>> 1 file changed, 24 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi >>> index 261d25173f61..5c052d7ff554 100644 >>> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi >>> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi >>> @@ -33,6 +33,9 @@ >>> clock-frequency = <1800000000>; >>> cci-control-port = <&cci_control1>; >>> operating-points-v2 = <&cluster_a15_opp_table>; >>> + cooling-min-level = <0>; >>> + cooling-max-level = <11>; >> >> Although the above two properties are defined they aren't parsed in the >> kernel. >> >> Setting min / max extents for cooling devices via cooling maps does work >> though. > > It is described as optional property in > Documentation/devicetree/bindings/thermal/thermal.txt ... but indeed it > is totally ignored. > > So what is the recommendation? Get rid of it from DTS and documentation > or leave it because it will be implemented someday? As long as you are not expecting any particular behaviour arising from that property today I think it should be fine to leave it in. Eduardo, do you agree? > > Thanks for feedback! > > Best regards, > Krzysztof > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 261d25173f61..5c052d7ff554 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -33,6 +33,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@1 { @@ -42,6 +45,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu2: cpu@2 { @@ -51,6 +57,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu3: cpu@3 { @@ -60,6 +69,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu4: cpu@100 { @@ -70,6 +82,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu5: cpu@101 { @@ -79,6 +94,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu6: cpu@102 { @@ -88,6 +106,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu7: cpu@103 { @@ -97,6 +118,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; }; };
On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and 12 steps for big core (700-1800 MHz). Add respective cooling cells. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- Changes since v1: 1. Add cooling properties to all CPUs (suggested by Viresh). --- arch/arm/boot/dts/exynos5420-cpus.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)