| Message ID | 1455242450-24493-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Simon Horman |
| Headers | show |
On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> wrote: > The parent clock isn't documented in the datasheet, use S2D1 as a best > guess for now. Looks like a good guess... I assume the driver doesn't depend on the clock rate? > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Monday 15 February 2016 10:22:22 Geert Uytterhoeven wrote: > On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart wrote: > > The parent clock isn't documented in the datasheet, use S2D1 as a best > > guess for now. > > Looks like a good guess... > I assume the driver doesn't depend on the clock rate? Correct. > > Signed-off-by: Laurent Pinchart > > <laurent.pinchart+renesas@ideasonboard.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thank you.
Hi Morimoto-san, On Friday 12 February 2016 04:00:42 Laurent Pinchart wrote: > The parent clock isn't documented in the datasheet, use S2D1 as a best > guess for now. Would you be able to find out what the parent clock is for the FCP and LVDS (patch 2/9) clocks ? Feel free to tell the documentation team that your life would be easier if the information was included in the datasheets ;-) > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > --- > drivers/clk/shmobile/r8a7795-cpg-mssr.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c > b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index 13e994772dfd..ae5004ee7bdd > 100644 > --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c > +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > @@ -130,6 +130,21 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] > __initconst = { DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), > DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), > DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), > + DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), > + DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), > + DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), > + DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), > + DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), > + DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), > + DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), > + DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), > DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), > DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), > DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
Hi Laurent > > The parent clock isn't documented in the datasheet, use S2D1 as a best > > guess for now. > > Would you be able to find out what the parent clock is for the FCP and LVDS > (patch 2/9) clocks ? Thanks ! I asked it to HW team > Feel free to tell the documentation team that your life would be easier if the > information was included in the datasheets ;-) Hehe :) OK, will try Best regards --- Kuninori Morimoto
Hi Laurent > > > The parent clock isn't documented in the datasheet, use S2D1 as a best > > > guess for now. > > > > Would you be able to find out what the parent clock is for the FCP and LVDS > > (patch 2/9) clocks ? It seems FCP clock is based on each SoC In H3 ES1 case, it is using - s2d2 (for 200MHz) - s2d1 (for 400MHz)
Hi Morimoto-san, On Thursday 03 March 2016 00:17:54 Kuninori Morimoto wrote: > Hi Laurent > > >>> The parent clock isn't documented in the datasheet, use S2D1 as a best > >>> guess for now. > >> > >> Would you be able to find out what the parent clock is for the FCP and > >> LVDS (patch 2/9) clocks ? > > It seems FCP clock is based on each SoC > In H3 ES1 case, it is using > - s2d2 (for 200MHz) > - s2d1 (for 400MHz) Thank you for the information. Do you mean that different FCP instances use different clocks ? If so, could you tell us which clock is used by each instance in th H3 ES1 ?
Hi Laurent > > It seems FCP clock is based on each SoC > > In H3 ES1 case, it is using > > - s2d2 (for 200MHz) > > - s2d1 (for 400MHz) > > Thank you for the information. Do you mean that different FCP instances use > different clocks ? If so, could you tell us which clock is used by each > instance in th H3 ES1 ? Sorry for my confusable mail. All FCP on H3 ES1 is using above, but, M3 or E3 will use different clock. Is this more clear ?
Hi Morimoto-sa, On Thursday 03 March 2016 07:19:20 Kuninori Morimoto wrote: > Hi Laurent > > >> It seems FCP clock is based on each SoC > >> In H3 ES1 case, it is using > >> > >> - s2d2 (for 200MHz) > >> - s2d1 (for 400MHz) > > > > Thank you for the information. Do you mean that different FCP instances > > use different clocks ? If so, could you tell us which clock is used by > > each instance in th H3 ES1 ? > > Sorry for my confusable mail. > All FCP on H3 ES1 is using above, > but, M3 or E3 will use different clock. > > Is this more clear ? Does it mean that every FCP instance uses both the S2D2 and the S2D1 clocks as functional clocks on H3 ES1 ?
Hi Laurent > > >> - s2d2 (for 200MHz) > > >> - s2d1 (for 400MHz) > > > > > > Thank you for the information. Do you mean that different FCP instances > > > use different clocks ? If so, could you tell us which clock is used by > > > each instance in th H3 ES1 ? > > > > Sorry for my confusable mail. > > All FCP on H3 ES1 is using above, > > but, M3 or E3 will use different clock. > > > > Is this more clear ? > > Does it mean that every FCP instance uses both the S2D2 and the S2D1 clocks as > functional clocks on H3 ES1 ? - s2d2 (200MHz) is for APB-IF, - s2d1 (400MHz) is for AXI-IF, and internal Is this clear answer ?
Hi Morimoto-san, On Thursday 03 March 2016 08:37:02 Kuninori Morimoto wrote: > Hi Laurent > > >>>> - s2d2 (for 200MHz) > >>>> - s2d1 (for 400MHz) > >>> > >>> Thank you for the information. Do you mean that different FCP instances > >>> use different clocks ? If so, could you tell us which clock is used by > >>> each instance in th H3 ES1 ? > >> > >> Sorry for my confusable mail. > >> All FCP on H3 ES1 is using above, > >> but, M3 or E3 will use different clock. > >> > >> Is this more clear ? > > > > Does it mean that every FCP instance uses both the S2D2 and the S2D1 > > clocks as functional clocks on H3 ES1 ? > > - s2d2 (200MHz) is for APB-IF, > - s2d1 (400MHz) is for AXI-IF, and internal > > Is this clear answer ? It is, thank you very much for putting up with my slow mind ;-) Geert, deciding what clock to use as a parent for the MSTP clock becomes interesting, As S2D2 clocks the control interface I propose picking it. This shows the limits of the MSTP clock model though, MSTP is really a module stop bit, not a clock.
Hi Laurent, On Thu, Mar 3, 2016 at 11:49 AM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Thursday 03 March 2016 08:37:02 Kuninori Morimoto wrote: >> >>>> - s2d2 (for 200MHz) >> >>>> - s2d1 (for 400MHz) >> >>> >> >>> Thank you for the information. Do you mean that different FCP instances >> >>> use different clocks ? If so, could you tell us which clock is used by >> >>> each instance in th H3 ES1 ? >> >> >> >> Sorry for my confusable mail. >> >> All FCP on H3 ES1 is using above, >> >> but, M3 or E3 will use different clock. >> >> >> >> Is this more clear ? >> > >> > Does it mean that every FCP instance uses both the S2D2 and the S2D1 >> > clocks as functional clocks on H3 ES1 ? >> >> - s2d2 (200MHz) is for APB-IF, >> - s2d1 (400MHz) is for AXI-IF, and internal >> >> Is this clear answer ? > > It is, thank you very much for putting up with my slow mind ;-) > > Geert, deciding what clock to use as a parent for the MSTP clock becomes > interesting, As S2D2 clocks the control interface I propose picking it. This > shows the limits of the MSTP clock model though, MSTP is really a module stop > bit, not a clock. Quoting R-Car Gen3 rev. 0.5E: "Under software control, the CPG is capable of turning the supply of clock signals to individual modules on or off and of resetting individual modules." So it is a clock signal, or better (or worse): clock signals (plural). Hence MSTP gates one or more clocks. Sigh... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Thursday 03 March 2016 12:56:29 Geert Uytterhoeven wrote: > On Thu, Mar 3, 2016 at 11:49 AM, Laurent Pinchart wrote: > > On Thursday 03 March 2016 08:37:02 Kuninori Morimoto wrote: > >>>>>> - s2d2 (for 200MHz) > >>>>>> - s2d1 (for 400MHz) > >>>>> > >>>>> Thank you for the information. Do you mean that different FCP > >>>>> instances use different clocks ? If so, could you tell us which clock > >>>>> is used by each instance in th H3 ES1 ? > >>>> > >>>> Sorry for my confusable mail. > >>>> All FCP on H3 ES1 is using above, > >>>> but, M3 or E3 will use different clock. > >>>> > >>>> Is this more clear ? > >>> > >>> Does it mean that every FCP instance uses both the S2D2 and the S2D1 > >>> clocks as functional clocks on H3 ES1 ? > >> > >> - s2d2 (200MHz) is for APB-IF, > >> - s2d1 (400MHz) is for AXI-IF, and internal > >> > >> Is this clear answer ? > > > > It is, thank you very much for putting up with my slow mind ;-) > > > > Geert, deciding what clock to use as a parent for the MSTP clock becomes > > interesting, As S2D2 clocks the control interface I propose picking it. > > This shows the limits of the MSTP clock model though, MSTP is really a > > module stop bit, not a clock. > > Quoting R-Car Gen3 rev. 0.5E: > "Under software control, the CPG is capable of turning the supply of clock > signals to individual modules on or off and of resetting individual > modules." > > So it is a clock signal, or better (or worse): clock signals (plural). I certainly believe that the module clock(s) is (are) gated when the module is stopped through its MSTP bit. My point was that MSTP in itself is not a clock, it's a module stop feature that uses clock and possibly other means to stop modules and lower power consumption. > Hence MSTP gates one or more clocks. Sigh... The question is whether we really need to model that, and the answer can be given in a case-by-case basis. In this case, given that S2D1 and S2D2 are both children of the S2 clock and are not individually gate-able (the S2 clock itself isn't either as far as I can tell) then it doesn't matter too much from a functional point of view. The FCP MSTP clock doesn't have to be modeled in the CPG driver as having multiple parents.
Hi Laurent > > > The parent clock isn't documented in the datasheet, use S2D1 as a best > > > guess for now. > > > > Would you be able to find out what the parent clock is for the FCP and LVDS > > (patch 2/9) clocks ? > > Thanks ! > I asked it to HW team It is too late information for you LVDS (APB) is using S0D4 (200MHz)
diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index 13e994772dfd..ae5004ee7bdd 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -130,6 +130,21 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), + DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), + DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), + DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), + DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), + DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), + DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), + DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), + DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), + DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), + DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), + DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), + DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), + DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), + DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), + DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
The parent clock isn't documented in the datasheet, use S2D1 as a best guess for now. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> --- drivers/clk/shmobile/r8a7795-cpg-mssr.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)