| Message ID | 1458587984-6313-4-git-send-email-wsa@the-dreams.de (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Wolfram, On Mon, Mar 21, 2016 at 8:19 PM, Wolfram Sang <wsa@the-dreams.de> wrote: > From: Wolfram Sang <wsa+renesas@sang-engineering.com> > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > drivers/clk/shmobile/r8a7795-cpg-mssr.c | 3 +++ > include/dt-bindings/clock/r8a7795-cpg-mssr.h | 5 +++-- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > index a9f933055663cb..4dda7f2ed0bcb6 100644 > --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c > +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > @@ -116,6 +116,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { > DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), > DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), > DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), > + > + DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, 0x0240, 8), > + DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, 0x0240, 32), Ah, so you use the same register for both. However, the notes for Table 8.2a say there are _2_ possible values: "The initial value depend on MD14, MD13. When MD14=L and MD13 = H, RCLK = 32.89 (kHz) In the other setting, RCLK = 32.55 (kHz) The initial value depend on MD14, MD13. When MD14=L and MD13 = H, OSCCLK = 131.57 (kHz). In the other setting, OSCCLK = 130.20 (kHz)" While the register documentation says there are _4_ possible values, and it doesn't document the relation behind these values and the "dividers": "MD14=0, MD13=0: 6’B00_1111 MD14=0, MD13=1: 6’B01_0010 MD14=1, MD13=0: 6’B01_0111 MD14=1, MD13=1: 6’B01_1111" I also cannot see how you get to the RCLK/OSCCLK values by using EXTAL (33.33333 MHz on final boards) and the dividers above. What am I missing (ah, morning coffee)? > --- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h > +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h > @@ -57,7 +57,8 @@ > #define R8A7795_CLK_CSIREF 42 > #define R8A7795_CLK_CP 43 > #define R8A7795_CLK_CPEX 44 > -#define R8A7795_CLK_R 45 > -#define R8A7795_CLK_OSC 46 > +#define R8A7795_CLK_RINT 45 > +#define R8A7795_CLK_R 46 > +#define R8A7795_CLK_OSC 47 This list of values is append-only, as it's part of the stable DT ABI. Please add new values at the end. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, > > + DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, 0x0240, 8), > > + DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, 0x0240, 32), Yes, we should ask the HW team if this is safe. I got the assumption from Figure 8.1a. In the middle, after EXTAL divider, OSCCLK and internal RCLK seem to have the same origin. (Note that in the diagram the 1/4 divider should have been placed to the internal RCLK). > However, the notes for Table 8.2a say there are _2_ possible values: > > "The initial value depend on MD14, MD13. > When MD14=L and MD13 = H, RCLK = 32.89 (kHz) > In the other setting, RCLK = 32.55 (kHz) Well, to be precise, it says the are two resulting frequencies, but for that, 4 values are needed as you found out. > While the register documentation says there are _4_ possible values, and it > doesn't document the relation behind these values and the "dividers": > > "MD14=0, MD13=0: 6’B00_1111 > MD14=0, MD13=1: 6’B01_0010 > MD14=1, MD13=0: 6’B01_0111 > MD14=1, MD13=1: 6’B01_1111" > > I also cannot see how you get to the RCLK/OSCCLK values by using EXTAL > (33.33333 MHz on final boards) and the dividers above. See figure 8.1a. OSCCLK is EXTAL_divider / 8. Internal RCLK is EXTAL_divider / 8 / 4. So, now assume the lower 6 bits of the RCKCR register are a standard DIV6 divider where the divisor is the value of these bits + 1. So, with EXTAL = 33.333MHz and MD14=MD13=1, the register value becomes 0x1f and divisor = 32. So for internal RCLK: 33333333 / 32 (fixed prescaler) / 32 (DIV6) = 32552.1 According to the Salvator-X manual, section 2.1.1.9: When EXTAL = 20MHz, and MD14=0 and MD13=1, then regval = 0x12, divisor = 19: So for internal RCLK: 20000000 / 32 (fixed prescaler) / 19 (DIV6) = 32894.7 I tried all the combinations and they match the datasheet precisely. > > +#define R8A7795_CLK_RINT 45 > > +#define R8A7795_CLK_R 46 > > +#define R8A7795_CLK_OSC 47 > > This list of values is append-only, as it's part of the stable DT ABI. > Please add new values at the end. Uh, okay. Then I'll introduce a special define for the end of that list, since there is one place where R8A7795_CLK_OSC is hardcoded. Thanks, Wolfram
Hi Wolfram, On Tue, Mar 22, 2016 at 5:26 PM, Wolfram Sang <wsa@the-dreams.de> wrote: >> However, the notes for Table 8.2a say there are _2_ possible values: >> >> "The initial value depend on MD14, MD13. >> When MD14=L and MD13 = H, RCLK = 32.89 (kHz) >> In the other setting, RCLK = 32.55 (kHz) > > Well, to be precise, it says the are two resulting frequencies, but for > that, 4 values are needed as you found out. > > >> While the register documentation says there are _4_ possible values, and it >> doesn't document the relation behind these values and the "dividers": >> >> "MD14=0, MD13=0: 6’B00_1111 >> MD14=0, MD13=1: 6’B01_0010 >> MD14=1, MD13=0: 6’B01_0111 >> MD14=1, MD13=1: 6’B01_1111" >> >> I also cannot see how you get to the RCLK/OSCCLK values by using EXTAL >> (33.33333 MHz on final boards) and the dividers above. > > See figure 8.1a. OSCCLK is EXTAL_divider / 8. Internal RCLK is > EXTAL_divider / 8 / 4. So, now assume the lower 6 bits of the RCKCR > register are a standard DIV6 divider where the divisor is the value of > these bits + 1. So, with EXTAL = 33.333MHz and MD14=MD13=1, the register > value becomes 0x1f and divisor = 32. > > So for internal RCLK: 33333333 / 32 (fixed prescaler) / 32 (DIV6) = 32552.1 > > According to the Salvator-X manual, section 2.1.1.9: > > When EXTAL = 20MHz, and MD14=0 and MD13=1, then regval = 0x12, divisor = 19: > > So for internal RCLK: 20000000 / 32 (fixed prescaler) / 19 (DIV6) = 32894.7 > > I tried all the combinations and they match the datasheet precisely. Thanks for the explanation. The numbers didn't match for me, as I had forgotten about the different EXTAL value. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index a9f933055663cb..4dda7f2ed0bcb6 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -116,6 +116,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + + DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, 0x0240, 8), + DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, 0x0240, 32), }; static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h index e864aae0a2561c..b67535607b93b7 100644 --- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h @@ -57,7 +57,8 @@ #define R8A7795_CLK_CSIREF 42 #define R8A7795_CLK_CP 43 #define R8A7795_CLK_CPEX 44 -#define R8A7795_CLK_R 45 -#define R8A7795_CLK_OSC 46 +#define R8A7795_CLK_RINT 45 +#define R8A7795_CLK_R 46 +#define R8A7795_CLK_OSC 47 #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */