| Message ID | 1458751122-23976-9-git-send-email-maxime.ripard@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Mar 24, 2016 at 12:38 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > The DRAM gates control whether the image / display devices on the SoC have > access to the DRAM clock or not. > > Enable it. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> I assume you'll add another version for A10s, or move the whole thing to sun5i.dtsi later?
On Thu, Mar 24, 2016 at 12:31:13PM +0800, Chen-Yu Tsai wrote: > On Thu, Mar 24, 2016 at 12:38 AM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > The DRAM gates control whether the image / display devices on the SoC have > > access to the DRAM clock or not. > > > > Enable it. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Acked-by: Chen-Yu Tsai <wens@csie.org> > > I assume you'll add another version for A10s, or move the whole thing > to sun5i.dtsi later? Indeed. Maxime
On Wed, Mar 23, 2016 at 05:38:31PM +0100, Maxime Ripard wrote: > The DRAM gates control whether the image / display devices on the SoC have > access to the DRAM clock or not. > > Enable it. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Applied, Maxime
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 9669b03f20f3..d3d2b19c97f1 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -62,7 +62,7 @@ "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>, - <&tcon_ch0_clk>; + <&tcon_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; }; @@ -151,6 +151,26 @@ "apb1_uart3"; }; + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-dram-gates-clk", + "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, + <25>, + <26>, + <29>, + <31>; + clock-output-names = "dram_ve", + "dram_csi", + "dram_de_fe", + "dram_de_be", + "dram_ace", + "dram_iep"; + }; + de_be_clk: clk@01c20104 { #clock-cells = <0>; #reset-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi index b1e4e0170d51..691d3de75b35 100644 --- a/arch/arm/boot/dts/sun5i-r8.dtsi +++ b/arch/arm/boot/dts/sun5i-r8.dtsi @@ -53,7 +53,7 @@ allwinner,pipeline = "de_be0-lcd0-tve0"; clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>, - <&tcon_ch1_clk>; + <&tcon_ch1_clk>, <&dram_gates 26>; status = "disabled"; }; };
The DRAM gates control whether the image / display devices on the SoC have access to the DRAM clock or not. Enable it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm/boot/dts/sun5i-a13.dtsi | 22 +++++++++++++++++++++- arch/arm/boot/dts/sun5i-r8.dtsi | 2 +- 2 files changed, 22 insertions(+), 2 deletions(-)